Heterogeneous multi-core unmanned aerial vehicle control method and device, computer equipment and storage medium
Patent Information
- Application Number
- CN202611103328.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2026-07-23
- Publication Date
- 2026-10-16
AI Technical Summary
然而，单核或同构多核架构方案存在以下显著问题：其一，资源竞争导致的不确定性，单一处理器或同构多核难以同时满足多任务对实时性和吞吐量的要求，特别是在执行视觉识别等计算密集型任务时，会占用大量处理器周期，导致硬实时飞控任务的任务切换延迟加剧，进而影响整个系统的响应速度和效率；其二，性能瓶颈，单一核心难以在高频飞行控制循环的同时，兼顾大吞吐量的图像数据处理，导致系统整体响应迟滞，无法满足复杂环境下的避障与自主导航需求
[0010] This application discloses a heterogeneous multi-core unmanned aerial vehicle (UAV) control method, apparatus, computer device, and storage medium. The method includes initializing the master core and the slave core, and establishing shared memory and a mailbox interrupt mechanism between the master core and the slave core; acquiring sensor data through the slave core according to a preset control cycle, performing attitude calculation on the sensor data to generate attitude state data, writing the attitude state data into the state buffer of the shared memory, and sending a state update event to the master core through the mailbox interrupt mechanism; responding to the state update event, reading the attitude state data from the state buffer through the master core, generating a target control command based on visual perception data, navigation planning data, and the attitude state data, writing the target control command into the instruction buffer of the shared memory, and sending an instruction ready event to the slave core through the mailbox interrupt mechanism; responding to the instruction ready event, reading the target control command from the instruction buffer through the slave core, performing closed-loop flight control calculation based on the target control command and local attitude state data, generating a UAV control signal, and driving the UAV to complete flight control operations through the UAV control signal. By employing the above method, this application initializes the master and slave cores and establishes shared memory and mailbox interrupt mechanisms within the same heterogeneous multi-core chip, eliminating the need for a separate MCU and its associated peripheral circuits. Shared memory serves as a high-speed data channel between the master and slave cores, and the mailbox interrupt mechanism enables event-driven synchronization and notification. The slave core writes attitude state data to the state buffer and sends state update events, while the master core writes target control commands to the command buffer and sends command ready events. This improves inter-core communication efficiency and enhances the operational coordination between hard real-time and soft real-time tasks in the UAV flight control system.