Image sensor and arrangement structure
By separating the overflow path and the quantization path in the image sensor, avoiding the overflow charge affecting the floating diffusion nodes, the problem of poor image quality is solved and the performance of the image sensor is improved.
Patent Information
- Application Number
- CN202420208725.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-29
- Publication Date
- 2024-12-10
- Estimated Expiration
- 2034-01-29
AI Technical Summary
In existing image sensors, the effect of overflow charge on floating diffusion nodes leads to poor image quality, including incomplete correlation dual sampling, dark current, solid-mode noise and light response inhomogeneity problems.
An image sensor is designed. By setting the separation of the overflow path and the quantization path in the pixel block, the overflow charge in the exposure stage is directly stored through the overflow path, avoiding passing through the floating diffusion node, thereby avoiding the impact on the quantization readout.
Improves image quality, reduces incomplete correlation dual sampling, dark current and solid-state mode noise, and improves uniformity of light response.
Smart Images
Figure CN222147724U_ABST
Abstract
Description
Technical Field
[0001] The utility model relates to the technical field of image sensors, in particular to an image sensor and an arrangement structure. Background Art
[0002] The image sensor includes a plurality of pixel blocks 100' arranged in an array. The circuit structure of each pixel block 100' is as follows: Figure 1 , including reset transistor M1', gain transistor M2', transfer transistor M3', overflow transistor M4', source follower transistor M5', selection transistor M6', photosensitive element PD' and overflow capacitor C1', and the specific connection is shown in the figure. In the exposure phase, the overflow charge generated by the photosensitive element PD' is stored in the overflow capacitor C1' via the transfer transistor M3', floating diffusion node FD', gain transistor M2' and overflow transistor M4'; in the quantization phase, the overflow charge stored in the overflow capacitor C1' is quantized and read out via the overflow transistor M4', gain transistor M2' and floating diffusion node FD', and the relevant timing is as follows Figure 2 shown.
[0003] The above circuit has the following disadvantages: 1. When the quantization readout is not completed, the floating diffusion node FD' cannot be reset, so the incomplete correlated double sampling (CDS), dark current, solid pattern noise (FPN), etc. will have a greater impact on the image; 2. Since the reset signal includes part of the charge overflowing to the floating diffusion node FD', the floating diffusion node FD' has a large amount of charge under strong light conditions, which will cause a great light response non-uniformity (PRNU) problem; 3. It may affect the working state of the source follower transistor M5', resulting in various undesirable responses of the image.
[0004] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the utility model and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the utility model. Utility Model Content
[0005] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide an image sensor and an arrangement structure for solving the problem of poor image quality caused by the overflow charge affecting the charge of the floating diffusion node in each pixel block of the prior art image sensor.
[0006] To achieve the above-mentioned purpose and other related purposes, the utility model provides an image sensor, comprising a plurality of pixel blocks arranged in an array, wherein the pixel blocks include a reset unit, a photosensitive unit, an overflow unit and a readout unit;
[0007] The reset unit is coupled to the floating diffusion node and is used to reset at least one of the floating diffusion node, the photosensitive unit and the overflow unit;
[0008] The photosensitive unit is coupled to the floating diffusion node, generates a first charge signal and a second charge signal based on photoelectric conversion, and stores the first charge signal and transfers the first charge signal to the floating diffusion node;
[0009] The overflow unit includes an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit, the quantization path is coupled to the floating diffusion node, the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node based on the quantization path;
[0010] The readout unit is coupled to the floating diffusion node and performs quantized readout on at least the first charge signal and the second charge signal.
[0011] Optionally, the overflow unit includes an exposure transistor, a quantization transistor and an overflow capacitor; the control end of the exposure transistor receives a first control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the overflow capacitor; the control end of the quantization transistor receives a second control signal, the first end is coupled to the floating diffusion node, and the second end is coupled to the first end of the overflow capacitor; the second end of the overflow capacitor is coupled to a ground potential or a variable potential; wherein the exposure transistor forms the overflow path, and the quantization transistor forms the quantization path.
[0012] Optionally, the pixel block further includes a fast reset unit coupled to two ends of the overflow capacitor, for quickly resetting the overflow unit.
[0013] Optionally, the fast reset unit includes a fast recovery transistor, a control end receiving a third control signal or coupled to its second end, a first end coupled to the first end of the overflow capacitor, and a second end coupled to the second end of the overflow capacitor; wherein the second end of the overflow capacitor is coupled to a variable potential.
[0014] Optionally, the photosensitive unit includes M photosensitive elements and M transmission transistors, which correspond to each other one by one, and M is an integer greater than or equal to 1; the control end of the transmission transistor receives a transmission control signal, the first end is coupled to the floating diffusion node, the second end is coupled to the first end of the photosensitive element, and the second end of the photosensitive element is coupled to a reference potential; wherein the overflow path is coupled to the first ends of S photosensitive elements, S is an integer greater than or equal to 1 and S is less than M;
[0015] Or, the photosensitive unit includes (N+T) photosensitive elements and N transfer transistors, the (N+T) photosensitive elements include N first photosensitive elements and T second photosensitive elements, the N first photosensitive elements correspond one-to-one to the N transfer transistors, N is an integer greater than or equal to 1, and T is an integer greater than or equal to 1; the control end of the transfer transistor receives a transmission control signal, the first end is coupled to the floating diffusion node, the second end is coupled to the first end of the first photosensitive element, and the second end of the first photosensitive element is coupled to a reference potential; the first end of the second photosensitive element is coupled to the overflow path, and the second end is coupled to a reference potential.
[0016] Optionally, the reset unit comprises a reset transistor, a control terminal receiving a reset control signal, a first terminal coupled to a first power supply potential, and a second terminal coupled to the floating diffusion node;
[0017] And / or, the read-out unit includes a source follower transistor and a selection transistor; the control end of the source follower transistor is coupled to the floating diffusion node, the first end is coupled to the second power supply potential, and the second end is coupled to the first end of the selection transistor; the control end of the selection transistor receives a selection signal, and the second end is coupled to the column line.
[0018] Optionally, the pixel block further includes a gain unit coupled between the reset unit and the floating diffusion node, for switching between different gain modes.
[0019] Optionally, the gain unit includes a gain transistor, a control end receiving a gain control signal, a first end coupled to the reset unit, and a second end coupled to the floating diffusion node; wherein the quantization path is coupled to the floating diffusion node or a low gain connection node corresponding to the gain unit.
[0020] The utility model also provides an arrangement structure of the image sensor as described above, comprising:
[0021] The reset unit includes a reset transistor, the photosensitive unit includes at least one photosensitive element and at least one transmission transistor, the overflow unit includes an exposure transistor, a quantization transistor and an overflow capacitor, and the readout unit includes a source follower transistor and a selection transistor;
[0022] The transfer transistor is arranged in a first corner area of the photosensitive element, the source follower transistor is arranged in a housing area of the transfer transistor away from the photosensitive element, the floating diffusion node is arranged in the housing area and on one side of the source follower transistor, the exposure transistor is arranged in a second corner area of the photosensitive element, the quantization transistor is arranged outside the housing area, and the reset transistor and the selection transistor are arranged outside the housing area.
[0023] Optionally, when the pixel block includes a gain unit and the gain unit includes a gain transistor, the gain transistor is arranged outside the accommodating area and between the quantization transistor and the floating diffusion node; and / or, when the pixel block includes a fast reset unit and the fast reset unit includes a fast return transistor, the fast return transistor is arranged on a side of the connection area of the overflow capacitor away from the quantization transistor; and / or, the first corner area and the second corner area are arranged facing each other in the horizontal direction; and / or, the quantization transistor is arranged on a side of the floating diffusion node away from the source follower transistor; and / or, the connection area of the overflow capacitor is arranged on a side of the quantization transistor away from the floating diffusion node; and / or, the reset transistor and the selection transistor are respectively arranged above and below the source follower transistor.
[0024] Optionally, the transfer transistor is arranged at a first angle in the first angular region, and the exposure transistor is arranged at a second angle in the second angular region, wherein the first angle is equal to the second angle.
[0025] As described above, the image sensor and arrangement structure of the utility model additionally sets an overflow path for overflow charges, and separates the overflow path and the quantization path so that the overflow charges in the exposure stage are directly stored through the overflow path without passing through the floating diffusion node, thereby avoiding the influence of the overflow charges on the charge of the floating diffusion node, thereby avoiding the influence on the subsequent quantization readout, which is beneficial to improving image quality. BRIEF DESCRIPTION OF THE DRAWINGS
[0026] Figure 1 Shown is a circuit diagram of a pixel block in a traditional image sensor.
[0027] Figure 2 Display as Figure 1 Timing diagram for the pixel block shown.
[0028] Figure 3 Shown is a circuit diagram of a pixel block in an image sensor in an embodiment of the present utility model.
[0029] Figure 4 Shown is another circuit schematic diagram of a pixel block in an image sensor according to an embodiment of the present utility model.
[0030] Figure 5 Shown is another circuit schematic diagram of a pixel block in an image sensor according to the first embodiment of the utility model.
[0031] Figure 6 Shown is a timing diagram of a pixel block in an image sensor according to an embodiment of the present utility model.
[0032] Figure 7Shown is another timing diagram of a pixel block in an image sensor according to an embodiment of the present invention.
[0033] Figure 8 Shown is another timing diagram of a pixel block in an image sensor according to an embodiment of the present invention.
[0034] Fig. 9 Shown is a circuit diagram of a pixel block in an image sensor in Embodiment 2 of the present utility model.
[0035] Fig.10 Shown is a timing diagram of a pixel block in an image sensor in the second embodiment of the present utility model.
[0036] Fig.11 Shown is a circuit diagram of a pixel block in an image sensor in Embodiment 3 of the present utility model.
[0037] Fig.12 Shown is another circuit schematic diagram of a pixel block in an image sensor in Embodiment 3 of the present utility model.
[0038] Fig.13 Shown is a timing diagram of a pixel block in the image sensor of the third embodiment of the present utility model.
[0039] Fig.14 Shown is a schematic diagram of the arrangement structure of the image sensor of the fourth embodiment of the utility model.
[0040] Component number description
[0041] 100', 100 pixel blocks
[0042] 110 Reset unit
[0043] 120 photosensitive units
[0044] 130 Overflow Unit
[0045] 140 Readout unit
[0046] 150 Gain Unit
[0047] 160 Fast reset unit DETAILED DESCRIPTION
[0048] The following is an explanation of the implementation of the present invention through specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific implementations, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention.
[0049] See also Figures 3 to 14 It should be noted that the illustrations provided in this embodiment are only used to illustrate the basic concept of the utility model in a schematic manner, and the illustrations only show the components related to the utility model rather than the number, shape and size of the components in actual implementation. The form, quantity and proportion of each component in actual implementation may be changed arbitrarily, and the component layout may also be more complicated.
[0050] Embodiment 1
[0051] like Figure 3 As shown, this embodiment provides an image sensor, including a plurality of pixel blocks 100 arranged in an array; each pixel block 100 includes a reset unit 110, a photosensitive unit 120, an overflow unit 130 and a readout unit 140; in one implementation, the circuit structure of each pixel block 100 is the same.
[0052] The reset unit 110 is coupled to the floating diffusion node FD, and is used to reset at least one of the floating diffusion node FD, the photosensitive unit 130 and the overflow unit 140 .
[0053] As an example, the reset unit 110 includes a reset transistor M1 , a control terminal of which receives a reset control signal RST, a first terminal of which is coupled to a first power supply potential, and a second terminal of which is coupled to a floating diffusion node FD.
[0054] In one implementation, the reset transistor M1 includes an NMOS tube. At this time, the gate of the reset transistor M1 receives the reset control signal RST, the drain is connected to the first power supply potential, and the source is connected to the floating diffusion node FD; wherein the first power supply potential is usually the potential of the working voltage and is always a high potential. Of course, in other implementations, it is also feasible for the reset transistor M1 to include a PMOS tube, which has no substantial impact on this embodiment.
[0055] The photosensitive unit 120 is coupled to the floating diffusion node FD, generates a first charge signal and a second charge signal based on photoelectric conversion, and stores the first charge signal and transfers the first charge signal to the floating diffusion node FD.
[0056] In combination with actual application scenarios, the first charge signal refers to the charge signal corresponding to the potential well portion, and the second charge signal refers to the charge signal corresponding to the overflow portion after the charge exceeds the potential well; when the amount of charge sensed by the photosensitive unit 120 does not reach the overflow state, the converted charge signal only includes the first charge signal, which is stored in the photosensitive unit 120. At this time, it can be considered that the second charge signal is zero; when the amount of charge sensed by the photosensitive unit 120 reaches the overflow state, the converted charge signal includes the first charge signal and the second charge signal, wherein the first charge signal is stored in the photosensitive unit 120, and the second charge signal overflows the photosensitive unit 120 and is stored in the overflow unit 130 based on the overflow path. In some applications, the first charge signal can also be defined as a potential well charge signal, and the second charge signal can be defined as an overflow charge signal.
[0057] As an example, Figure 3 and Figure 4 As shown, the photosensitive unit 130 includes M photosensitive elements PD and M transmission transistors M2, which correspond to each other, and M is an integer greater than or equal to 1; the control end of the transmission transistor M2 receives the transmission control signal TX, the first end is coupled to the floating diffusion node FD, the second end is coupled to the first end of the photosensitive element PD, and the second end of the photosensitive element PD is coupled to the reference potential; wherein the overflow path is coupled to the first end of S photosensitive elements, S is an integer greater than or equal to 1 and S is less than M, for example, in this example, S is 1. The overflow path of the overflow unit 130 is coupled to the first end of the corresponding photosensitive element PD to receive the overflow charge signal, which can be coupled to the first end of any photosensitive element PD, or can be coupled to the first ends of multiple photosensitive elements PD at the same time to achieve signal reception; of course, the overflow path of the overflow unit 130 can also be coupled to the second end of the corresponding transmission transistor M2 to receive the overflow charge signal, which can be coupled to the second end of any transmission transistor M2, or can be coupled to the second ends of multiple transmission transistors M2 at the same time to achieve signal reception. In one embodiment, when M is greater than 1, the photosensitive unit 120 is an M-sharing structure, for example, each photosensitive element shares a floating diffusion node region, a readout unit, and a reset unit. In one embodiment, (MS) photosensitive elements PD are used to obtain traditional image signals, and can obtain correlated double sampling data, and further, can obtain correlated double sampling data under different gains, and S photosensitive elements PD are used to obtain image signals with overflow signals, and can obtain correlated double sampling data, and can also obtain non-true correlated double sampling data.
[0058] In one implementation, the photosensitive element PD includes a photodiode, and the transmission transistor M2 includes an NMOS tube. At this time, the gate of the transmission transistor M2 receives the transmission control signal TX, the drain is connected to the floating diffusion node FD, the source is connected to the first end of the photosensitive element PD (such as the N-type ion doping region), and the second end of the photosensitive element PD (such as the P-type ion doping region) is connected to the reference potential, which is usually the ground potential or the negative potential. Of course, in other implementations, it is also feasible for the photosensitive element PD to include a grating or a photoconductor and the transmission transistor M2 to include a PMOS tube, which has no substantial impact on this embodiment.
[0059] As another example, Figure 5 As shown, the photosensitive unit 130 includes (N+T) photosensitive elements and N transmission transistors M2, the (N+T) photosensitive elements include N first photosensitive elements PD1 and T second photosensitive elements PD2, the N first photosensitive elements PD1 correspond to the N transmission transistors M2 one by one, N is an integer greater than or equal to 1, T is an integer greater than or equal to 1, in this example, T is equal to 1; the control end of the transmission transistor M2 receives the transmission control signal TX, the first end is coupled to the floating diffusion node FD, the second end is coupled to the first end of the first photosensitive element PD1, and the second end of the first photosensitive element PD1 is coupled to the reference potential; the first end of the second photosensitive element PD2 is coupled to the overflow path of the overflow unit 130, and the second end is coupled to the reference potential. In this example, when N is greater than 1, the photosensitive unit 120 is an N-sharing structure.
[0060] In one implementation, the first photosensitive element PD1 and the second photosensitive element PD2 include photodiodes, and the transfer transistor M2 includes an NMOS tube. At this time, the gate of the transfer transistor M2 receives the transmission control signal TX, the drain is connected to the floating diffusion node FD, the source is connected to the first end (such as the N-type ion doping region) of the first photosensitive element PD1, the second end (such as the P-type ion doping region) of the first photosensitive element PD1 is connected to the reference potential, the first end (such as the N-type ion doping region) of the second photosensitive element PD2 is connected to the overflow path of the overflow unit 130, and the second end (such as the P-type ion doping region) is connected to the reference potential, which is usually the ground potential or the negative potential. Of course, in other implementations, it is also feasible for the first photosensitive element PD1 and the second photosensitive element PD2 to include gratings or photoconductors, and the transfer transistor M2 to include a PMOS tube, which has no substantial impact on this embodiment.
[0061] The overflow unit 130 includes an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit 120, the quantization path is coupled to the floating diffusion node FD, the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node FD based on the quantization path. By adding the overflow path, the overflow path and the quantization path are separated, so as to avoid the second charge signal overflowed from the photosensitive unit 120 during the exposure stage passing through the floating diffusion node FD and remaining, which affects the subsequent quantization readout.
[0062] As an example, the overflow unit 130 includes an exposure transistor M3, a quantization transistor M4 and an overflow capacitor C1; the control end of the exposure transistor M3 receives a first control signal OFG, the first end is coupled to the photosensitive unit 120, and the second end is coupled to the first end of the overflow capacitor C1; the control end of the quantization transistor M4 receives a second control signal OF_CTL, the first end is coupled to the floating diffusion node FD, and the second end is coupled to the first end of the overflow capacitor C1; the second end of the overflow capacitor C1 is coupled to the ground potential; wherein the exposure transistor M3 forms an overflow path, and the quantization transistor M4 forms a quantization path.
[0063] In one implementation, the exposure transistor M3 includes an NMOS transistor, and the quantization transistor M4 includes an NMOS transistor. At this time, the gate of the exposure transistor M3 receives the first control signal OFG, the drain is connected to the photosensitive unit 120, and the source is connected to the first end of the overflow capacitor C1. The gate of the quantization transistor M4 receives the second control signal OF_CTL, the drain is connected to the floating diffusion node FD, and the source is connected to the first end of the overflow capacitor C1. Of course, in other implementations, it is also feasible for the exposure transistor M3 to include a PMOS transistor and the quantization transistor M4 to include a PMOS transistor, which has no substantial impact on this embodiment.
[0064] The readout unit 140 is coupled to the floating diffusion node FD, and performs quantized readout on at least the first charge signal and the second charge signal.
[0065] As an example, the readout unit 140 includes a source follower transistor M5 and a selection transistor M6; the control end of the source follower transistor M5 is coupled to the floating diffusion node FD, the first end is coupled to the second power supply potential, and the second end is coupled to the first end of the selection transistor M6; the control end of the selection transistor M6 receives the selection signal SEL, and the second end is coupled to the column line BIT.
[0066] In one implementation, the source follower transistor M5 includes an NMOS transistor, and the selection transistor M6 includes an NMOS transistor. At this time, the gate of the source follower transistor M5 is connected to the floating diffusion node FD, the drain is connected to the second power supply potential, the source is connected to the drain of the selection transistor M6, the gate of the selection transistor M6 receives the selection signal SEL, and the source is connected to the column line BIT; the second power supply potential is usually the same as the first power supply potential, both are working voltage potentials, such as always being a high potential. Of course, in other implementations, it is also feasible for the source follower transistor M5 to include a PMOS tube and the selection transistor M6 to include a PMOS tube, which has no substantial impact on this embodiment.
[0067] Correspondingly, such as Figures 6 to 8 As shown, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage and a quantization stage; wherein the image sensor is implemented using the circuit structure as described above.
[0068] Reset phase:
[0069] The floating diffusion node FD, the photosensitive unit 120 and the overflow unit 130 are reset; further, the floating diffusion node FD, the photosensitive unit 120 and the overflow unit 130 are reset through the reset unit 110 .
[0070] For example, the reset transistor M1 in the reset unit 110, the transfer transistor M2 in the photosensitive unit 120, and the quantization transistor M4 in the overflow unit 130 are controlled to be turned on, and the floating diffusion node FD, the photosensitive element PD in the photosensitive unit 120, and the overflow capacitor C1 in the overflow unit 130 are cleared to realize signal reset, and the reset operation is completed. After that, the reset transistor M1, the transfer transistor M2, and the quantization transistor M4 are controlled to be turned off. In an optional example, the exposure transistor M3 in the overflow unit 130 can be controlled to be turned on at the same time, so as to facilitate the charge clearing of the overflow capacitor C1 to realize signal reset.
[0071] Of course, the reset transistor M1 may not be turned off at the end of the reset phase, for example, the reset transistor M1 is turned on in the reset phase and turned off in the quantization phase. Furthermore, the reset transistor M1 is turned off after the select transistor M6 of the readout unit 140 is turned on for the first time. Figures 6 to 8 As shown, crosstalk of other pixel blocks to the floating diffusion node FD of the current pixel block is avoided during the exposure phase. Of course, it is also feasible to turn off the reset transistor M1 while the select transistor M6 is turned on.
[0072] Exposure stage:
[0073] The overflow path is opened and the quantization path is closed, and the second charge signal is stored in the overflow unit 130 through the overflow path.
[0074] For example, the exposure transistor M3 in the overflow unit 130 is controlled to be turned on, and the overflow path is opened at this time. The second charge signal overflowed from the photosensitive element PD in the photosensitive unit 120 is transferred to the overflow capacitor C1 of the overflow unit 130 through the overflow path for storage; since the quantization transistor M4 and the transfer transistor M2 in the overflow unit 130 are turned off in the reset phase, the quantization path is closed, and the overflowed second charge signal will not be transferred to the overflow unit 130 through the quantization path, and will not pass through the floating diffusion node FD, and will not remain in the floating diffusion node FD. Afterwards, the exposure transistor M3 is controlled to be turned off.
[0075] When the amount of charge sensed by the photosensitive element PD in the photosensitive unit 120 has not reached the overflow state, the converted charge signal only includes the first charge signal, which is stored on the photosensitive element PD. At this time, although the overflow path is opened, there is no second charge signal transferred to the overflow capacitor C1 through the overflow path. It can be considered that the corresponding second charge signal in this process is zero.
[0076] When the charge amount sensed by the photosensitive element PD in the photosensitive unit 120 reaches an overflow state, the converted charge signal includes a first charge signal and a second charge signal, wherein the first charge signal is stored on the photosensitive element PD, and the second charge signal is transferred to the overflow capacitor C1 through the overflow path for storage.
[0077] Quantification stage:
[0078] In one implementation, Figure 6 As shown, the overflow path is closed to perform quantization reading of the first reset signal and the first charge signal based on the floating diffusion node FD, thereby realizing the correlated double sampling of the first charge signal; and the floating diffusion node FD is reset to perform quantization reading of the second reset signal based on the floating diffusion node FD, and then the quantization path is controlled to be opened and then closed, and the second charge signal is transferred to the floating diffusion node FD through the quantization path for quantization reading, thereby realizing the correlated double sampling of the second charge signal.
[0079] For the first reset signal and the first charge signal: since the exposure transistor M3 in the overflow unit 130 is turned off during the exposure phase, the overflow path is closed; first, the selection transistor M6 in the readout unit 150 is controlled to be turned on, so as to perform quantized reading of the first reset signal (i.e., RST) based on the floating diffusion node FD; then, the transfer transistor M2 in the photosensitive unit 120 is controlled to be turned on and then turned off, so as to transfer the first charge signal (i.e., SIG) stored in the photosensitive element PD to the floating diffusion node FD and perform quantized reading. Furthermore, corresponding to the process in which the transfer transistor M2 is turned on and then turned off, the selection transistor M6 is turned off and then turned on.
[0080] For the second reset signal and the second charge signal: first control the reset transistor M1 in the reset unit 110 to open and then close, and perform a reset operation on the floating diffusion node FD, so as to quantize and read out the second reset signal (i.e., OF_RST1) based on the floating diffusion node FD; then control the quantization transistor M4 in the overflow unit 130 to open and then close, and transfer the second charge signal stored in the overflow capacitor C1 in the overflow unit 140 to the floating diffusion node FD through the quantization path, so as to quantize and read out the second charge signal (i.e., OF_SIG1) based on the floating diffusion node FD.
[0081] In another implementation, Figure 7 As shown, the overflow path is closed to perform quantization readout of the first reset signal and the first charge signal based on the floating diffusion node FD, thereby realizing correlated double sampling of the first charge signal; and the quantization path is opened, and the second charge signal is transferred to the floating diffusion node FD through the quantization path for quantization readout, and then the floating diffusion node FD is reset to perform quantization readout of the second reset signal based on the floating diffusion node FD, thereby realizing non-true correlated double sampling of the second charge signal.
[0082] The quantized readout of the first reset signal and the first charge signal in this implementation is the same as that in the previous implementation, and will not be described again here.
[0083] For the second reset signal and the second charge signal: first control the quantization transistor M4 in the overflow unit 130 to open, at this time the quantization path is opened, and the second charge signal stored in the overflow capacitor C1 in the overflow unit 140 is transferred to the floating diffusion node FD through the quantization path, so as to perform quantization reading of the second charge signal (i.e., OF_SIG2) based on the floating diffusion node FD; then control the reset transistor M1 in the reset unit 110 to open and then close, and perform a reset operation on the floating diffusion node FD, so as to perform quantization reading of the second reset signal (i.e., OF_RST2) based on the floating diffusion node FD.
[0084] Furthermore, before the second charge signal is quantized and read out, the transfer transistor M2 in the photosensitive unit 120 is controlled to be opened and then closed, and further, the selection transistor M6 in the readout unit 140 can be controlled to be closed and then opened at the same time; in addition, before the second charge signal is quantized and read out, the exposure transistor M3 in the overflow unit 130 is controlled to be opened and then closed, wherein the opening and closing of the exposure transistor M3 can be performed simultaneously with the opening and closing of the transfer transistor M2.
[0085] For the above-mentioned another implementation method, in the process of quantizing and reading out the second reset signal based on the reset operation, the process of opening and closing the reset transistor M1 corresponds to the operation of closing and opening the selection transistor M6 in the readout unit 140, wherein the reset transistor M1 is closed during the closing period of the selection transistor M6.
[0086] Of course, in other implementations, the correlated double sampling of the first charge signal, the correlated double sampling of the second charge signal, and the non-true correlated double sampling of the second charge signal may be performed successively, such as Figure 8 As shown, the relevant control can be found in the above text, which will not be described here. It should be noted that in one implementation, Figure 8 In the process of quantization in this manner, the reset step before quantization reading of the second reset signal (i.e., OF_RST1) can be omitted, that is, the operation of controlling the reset transistor M1 in the reset unit 110 to be turned on and then turned off is not performed, but the second reset signal (i.e., OF_RST1) is directly read, thereby reducing the signal loss in the subsequent overflow signal reading process.
[0087] Embodiment 2
[0088] like Fig. 9 As shown, the difference between this embodiment and embodiment 1 is that the pixel block 100 of this embodiment also includes a gain unit 150, which is coupled between the reset unit 110 and the floating diffusion node FD, and is used to switch between different gain modes, such as switching between a low conversion gain (LCG) mode and a high conversion gain (HCG) mode.
[0089] When the pixel block 100 includes the gain unit 150, the quantization path of the overflow unit 130 is coupled to the floating diffusion node FD or the connection node between the reset unit 110 and the gain unit 150, that is, the low gain connection node corresponding to the gain unit 150. In this embodiment, the quantization path of the overflow unit 130 is coupled to the low gain connection node corresponding to the gain unit 150 to optimize the quantization gain of the overflow charge signal.
[0090] As an example, the gain unit 150 includes a gain transistor M7, a control end receiving a gain control signal DCG, a first end coupled to the reset unit 110, and a second end coupled to the floating diffusion node FD. If the gain transistor M7 is turned on, the image sensor operates in the LCG mode, and if the gain transistor M7 is turned off, the image sensor operates in the HCG mode. In this embodiment, the quantization path of the overflow unit 130 is connected between the first end of the gain transistor M7 and the reset unit 110.
[0091] In one implementation, the gain transistor M7 includes an NMOS transistor. At this time, the gate of the gain transistor M7 receives the gain control signal DCG, the drain is connected to the source of the reset transistor M1, and the source is connected to the floating diffusion node FD. Of course, in other implementations, it is also feasible for the gain transistor M7 to include a PMOS transistor, which has no substantial impact on this embodiment.
[0092] Correspondingly, such as Fig.10 As shown, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage and a quantization stage; wherein the image sensor is implemented using the circuit structure as described above.
[0093] Reset phase:
[0094] The floating diffusion node FD, the photosensitive unit 120 and the overflow unit 130 are reset; further, the floating diffusion node FD, the photosensitive unit 120 and the overflow unit 130 are reset through the reset unit 110 .
[0095] The control method of the reset phase of this embodiment is substantially the same as that of the first embodiment, except that the gain transistor M7 in the gain unit 150 is also controlled to be turned on in this embodiment to facilitate the execution of the reset operation; wherein the gain transistor M7 is turned on in the reset phase and turned off in the quantization phase.
[0096] Exposure stage:
[0097] The overflow path is opened and the quantization path is closed, and the second charge signal is stored in the overflow unit 130 through the overflow path.
[0098] The control method of the exposure stage in this embodiment is the same as that in the first embodiment. For details, please refer to the first embodiment and will not be repeated here. In one implementation, the gain transistor M7 remains turned on in the exposure stage and continues to the subsequent corresponding quantization stage.
[0099] Quantification stage:
[0100] This embodiment is different from the first embodiment in that the quantization readout of the first reset signal and the first charge signal in the quantization stage; in this embodiment, the overflow path is closed to perform quantization readout of the first reset signal and the first charge signal in different gain modes based on the floating diffusion node FD, thereby realizing the correlated double sampling of the first charge signal in different gain modes. Specifically, the gain unit 150 is controlled to be turned on and then turned off to perform quantization readout of the first reset signal in different gain modes based on the floating diffusion node FD, and then the gain unit 150 is controlled to be turned off and then turned on to perform quantization readout of the first charge signal in different gain modes based on the floating diffusion node FD.
[0101] Since the gain transistor M7 in the gain unit 150 is turned on and remains on during the reset phase, the image sensor operates in the LCG mode, and thus the first reset signal (i.e., L_RST) in the LCG mode is quantized and read out based on the floating diffusion node FD; then the gain transistor M7 is controlled to be turned off, so that the image sensor switches to the HCG mode, and thus the first reset signal (i.e., H_RST) in the HCG mode is quantized and read out based on the floating diffusion node FD.
[0102] The transfer transistor M2 in the photosensitive unit 120 is controlled to open and then closed, and the first charge signal stored in the photosensitive element PD is transferred to the floating diffusion node FD, and the first charge signal (i.e., H_SIG) in the HCG mode is quantized and read out based on the floating diffusion node FD; the gain transistor M7 is controlled to open, so that the image sensor switches to the LCG mode again. Further, the transfer transistor M2 can be controlled to open and then closed at the same time, and the charge signal in the photosensitive element PD is transferred to the floating diffusion node FD. In the above state, the first charge signal (i.e., L_SIG) in the LCG mode is quantized and read out based on the floating diffusion node FD.
[0103] Furthermore, corresponding to the process in which the transmission transistor M2 is turned on and then turned off, the transistor M6 is selected to be turned off and then turned on.
[0104] The quantization readout of the second reset signal and the second charge signal in the quantization stage of this embodiment is the same as that of the first embodiment. For details, please refer to the first embodiment and will not be repeated here. In the subsequent quantization readout process, the gain transistor M7 remains on. It should be noted that since the gain transistor M7 remains on, it can be considered that the second charge signal is correlated double sampled in the LCG mode. Fig.10 OF_LCG_RST is used to represent OF_RST1, and OF_LCG_SIG is used to represent OF_SIG1. At the same time, OF_SIG is used to represent OF_SIG2, and OF_RST is used to represent OF_RST2.
[0105] Embodiment 3
[0106] like Fig.11 As shown, the difference between this embodiment and the first and second embodiments is that the pixel block 100 of this embodiment further includes a fast reset unit 160, which is coupled to both ends of the overflow capacitor C1 in the overflow unit 130, and is used to reset the overflow unit 130. Of course, the fast reset unit 160 can cooperate with the reset unit 110 to reset the overflow unit 130.
[0107] As an example, the fast reset unit 160 includes a fast return transistor M8, a control end receiving the third control signal OF_RST, a first end coupled to the first end of the overflow capacitor C1, and a second end coupled to the second end of the overflow capacitor C1; in an optional solution, the second end of the overflow capacitor C1 is coupled to the variable potential Vc instead of the ground potential, that is, the second end of the fast return transistor M8 is coupled to the variable potential Vc. In other examples, according to the threshold of the fast return transistor M8, the control end of the fast return transistor M8 can be short-circuited with the second end to achieve that the fast return transistor M8 can be turned on and off in the corresponding stage; at this time, the control end of the fast return transistor M8 is no longer connected to the third control signal OF_RST, such as Fig.12 shown.
[0108] In one implementation, the fast-return transistor M8 includes an NMOS transistor. At this time, the gate of the fast-return transistor M8 receives the third control signal OF_RST, the drain is connected to the first end of the overflow capacitor C1, and the source is connected to the second end of the overflow capacitor C1. Of course, in other implementations, it is also feasible for the fast-return transistor M8 to include a PMOS transistor, which has no substantial impact on this embodiment.
[0109] Correspondingly, such as Fig.13 As shown, this embodiment also provides a control method for an image sensor, including a reset stage, an exposure stage, and a quantization stage; wherein the image sensor is implemented using the circuit structure described above. In one implementation, the fast reset unit 160 is turned on during the quantization readout of the second reset signal of the non-true correlated double sampling. Of course, in other embodiments, the turning on action of the fast reset unit 160 can also be performed in other processes, for example, during the global reset of the circuit or the reset reading process of the signal in the overflow capacitor C1.
[0110] Reset phase:
[0111] This embodiment is different from the above two embodiments in the reset operation of the floating diffusion node FD, the photosensitive unit 120 and the overflow unit 130 during the reset stage; in this embodiment, the floating diffusion node FD and the photosensitive unit 120 are reset by the reset unit 110, and the overflow unit 130 is reset by the fast reset unit 160.
[0112] Alternatively, in this embodiment, the floating diffusion node FD, the photosensitive unit 120 , and the overflow unit 130 are reset by the reset unit 110 , and the overflow unit 130 is quickly reset by the fast reset unit 160 in coordination with the reset unit 110 .
[0113] For the case where the pixel block 100 does not include the gain unit 150: the reset transistor M1 in the reset unit 110 and the transfer transistor M2 in the photosensitive unit 120 are controlled to be turned on, and the floating diffusion node FD and the photosensitive element PD in the photosensitive unit 120 are charged to zero to achieve signal reset; at the same time, the fast reset transistor M8 in the fast reset unit 160 is controlled to be turned on and the variable potential is controlled to jump to a high potential, such as the power supply potential VDD, and the overflow capacitor C1 in the overflow unit 130 is charged to zero to achieve signal reset; in this way, the reset operation is completed. Afterwards, the reset transistor M1, the transfer transistor M2, and the fast reset transistor M8 are controlled to be turned off, and the variable potential is controlled to jump to a low potential, such as the ground potential.
[0114] In which, during the reset process, at least one of the exposure transistor M3 and the quantization transistor M4 in the overflow unit 130 remains open, which is conducive to the rapid reset of the overflow capacitor C1, that is, based on the reset unit 110 and the fast reset unit 160, the rapid reset operation of the overflow capacitor C1 of the overflow unit 130 is implemented.
[0115] For the case where the pixel block 100 includes the gain unit 150: when the floating diffusion node FD and the photosensitive unit 120 are reset by the reset unit 110, the control method is roughly the same as the case where the gain unit 150 is not included, the difference is that the gain transistor M7 in the gain unit 150 is also controlled to be turned on, wherein the gain transistor M7 is turned on in the reset stage and turned off in the quantization stage.
[0116] The exposure stage and the quantization stage are the same as the above two embodiments, and the details can be found in the relevant embodiments, which will not be repeated here. In one implementation, in the exposure stage and the quantization stage, the fast return transistor M8 remains turned off, and the variable potential remains at a low potential, such as the ground potential.
[0117] Embodiment 4
[0118] like Fig.14 As shown, this embodiment provides an arrangement structure of an image sensor, including the following arrangement; wherein, a pixel block 100 in the image sensor includes a reset unit 110 , a photosensitive unit 120 , an overflow unit 130 and a readout unit 140 .
[0119] The reset unit 110 includes a reset transistor M1, the photosensitive unit 120 includes at least one photosensitive element PD and at least one transfer transistor M2, the overflow unit 130 includes an exposure transistor M3, a quantization transistor M4 and an overflow capacitor C1, and the readout unit 140 includes a source follower transistor M5 and a selection transistor M6.
[0120] Among them, the transfer transistor M2 is arranged in the first corner area of the photosensitive element PD, the source follower transistor M5 is arranged in the accommodating area of the transfer transistor M2 away from the photosensitive element PD, the floating diffusion node FD is arranged in the accommodating area and on one side of the source follower transistor M5, the exposure transistor M3 is arranged in the second corner area of the photosensitive element PD, the quantization transistor M4 is arranged outside the accommodating area, and the reset transistor M1 and the selection transistor M6 are arranged outside the accommodating area.
[0121] In one implementation, the quantization transistor M4 is disposed outside the accommodation area and on a side of the floating diffusion node FD away from the source follower transistor M5, and the connection area of the overflow capacitor C1 is disposed on a side of the quantization transistor M4 away from the floating diffusion node FD. In one implementation, the reset transistor M1 and the selection transistor M6 are disposed outside the accommodation area and are disposed above and below the source follower transistor M5, respectively. In one implementation, the first corner area and the second corner area are arranged facing each other in the horizontal direction, and further, the transfer transistor M2 is arranged at a first angle in the first corner area, and the exposure transistor M3 is arranged at a second angle in the second corner area, wherein the first angle is equal to the second angle.
[0122] Furthermore, the pixel block 100 further includes a gain unit 150 ; and the gain unit 150 includes a gain transistor M7 . At this time, the gain transistor M7 is disposed outside the accommodation region and between the quantization transistor M4 and the floating diffusion node FD.
[0123] Furthermore, the pixel block 100 further includes a fast reset unit 160 ; and the fast reset unit 160 includes a fast reset transistor M8 . In one embodiment, the fast reset transistor M8 is disposed at a side of the connection region of the overflow capacitor C1 away from the quantization transistor M4 (not shown in the figure).
[0124] In summary, the image sensor and arrangement structure of the utility model additionally sets an overflow path for overflow charges, separates the overflow path and the quantization path, and allows the overflow charges in the exposure stage to be directly stored through the overflow path without passing through the floating diffusion node, thereby avoiding the overflow charges from affecting the charges of the floating diffusion node, thereby avoiding the impact on the subsequent quantization readout, and is conducive to improving the image quality. Therefore, the utility model effectively overcomes various shortcomings in the prior art and has a high industrial utilization value.
[0125] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or alter the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or alterations made by a person of ordinary skill in the art without departing from the spirit and technical concept disclosed in the present invention shall still be covered by the claims of the present invention.
Claims
1. An image sensor, characterized in that: It comprises a plurality of pixel blocks arranged in an array, wherein the pixel blocks comprise a reset unit, a photosensitive unit, an overflow unit and a readout unit; The reset unit is coupled to the floating diffusion node and is used to reset at least one of the floating diffusion node, the photosensitive unit and the overflow unit; The photosensitive unit is coupled to the floating diffusion node, generates a first charge signal and a second charge signal based on photoelectric conversion, and stores the first charge signal and transfers the first charge signal to the floating diffusion node; The overflow unit includes an overflow path and a quantization path, the overflow path is coupled to the photosensitive unit, the quantization path is coupled to the floating diffusion node, the second charge signal is stored based on the overflow path, and the second charge signal is transferred to the floating diffusion node based on the quantization path; The readout unit is coupled to the floating diffusion node and performs quantized readout on at least the first charge signal and the second charge signal.
2. The image sensor according to claim 1, characterized in that The overflow unit includes an exposure transistor, a quantization transistor and an overflow capacitor; the control end of the exposure transistor receives a first control signal, the first end is coupled to the photosensitive unit, and the second end is coupled to the first end of the overflow capacitor; the control end of the quantization transistor receives a second control signal, the first end is coupled to the floating diffusion node, and the second end is coupled to the first end of the overflow capacitor; the second end of the overflow capacitor is coupled to a ground potential or a variable potential; wherein the exposure transistor forms the overflow path, and the quantization transistor forms the quantization path.
3. The image sensor according to claim 2, characterized in that The pixel block further includes a fast reset unit coupled to both ends of the overflow capacitor and used for quickly resetting the overflow unit.
4. The image sensor according to claim 3, characterized in that: The fast reset unit includes a fast recovery transistor, a control end receiving a third control signal or coupled to its second end, a first end coupled to the first end of the overflow capacitor, and a second end coupled to the second end of the overflow capacitor; and / or, the second end of the overflow capacitor is coupled to a variable potential.
5. The image sensor according to claim 1, characterized in that The photosensitive unit includes M photosensitive elements and M transmission transistors, which correspond to each other one by one, and M is an integer greater than or equal to 1; the control end of the transmission transistor receives a transmission control signal, the first end is coupled to the floating diffusion node, the second end is coupled to the first end of the photosensitive element, and the second end of the photosensitive element is coupled to a reference potential; wherein the overflow path is coupled to the first ends of S photosensitive elements, S is an integer greater than or equal to 1 and S is less than M; Or, the photosensitive unit includes (N+T) photosensitive elements and N transfer transistors, the (N+T) photosensitive elements include N first photosensitive elements and T second photosensitive elements, the N first photosensitive elements correspond one-to-one to the N transfer transistors, N is an integer greater than or equal to 1, and T is an integer greater than or equal to 1; the control end of the transfer transistor receives a transmission control signal, the first end is coupled to the floating diffusion node, the second end is coupled to the first end of the first photosensitive element, and the second end of the first photosensitive element is coupled to a reference potential; the first end of the second photosensitive element is coupled to the overflow path, and the second end is coupled to a reference potential.
6. The image sensor according to claim 1, characterized in that: The reset unit comprises a reset transistor, a control terminal receiving a reset control signal, a first terminal coupled to a first power supply potential, and a second terminal coupled to the floating diffusion node; And / or, the read-out unit includes a source follower transistor and a selection transistor; the control end of the source follower transistor is coupled to the floating diffusion node, the first end is coupled to the second power supply potential, and the second end is coupled to the first end of the selection transistor; the control end of the selection transistor receives a selection signal, and the second end is coupled to the column line.
7. The image sensor according to any one of claims 1 to 6, characterized in that: The pixel block further includes a gain unit coupled between the reset unit and the floating diffusion node and used for switching between different gain modes.
8. The image sensor according to claim 7, characterized in that: The gain unit comprises a gain transistor, a control end receiving a gain control signal, a first end coupled to the reset unit, and a second end coupled to the floating diffusion node; And / or, the quantization path is coupled to the floating diffusion node or a low gain connection node corresponding to the gain unit.
9. An arrangement structure of an image sensor according to any one of claims 1 to 8, characterized in that: include: The reset unit includes a reset transistor, the photosensitive unit includes at least one photosensitive element and at least one transmission transistor, the overflow unit includes an exposure transistor, a quantization transistor and an overflow capacitor, and the readout unit includes a source follower transistor and a selection transistor; The transfer transistor is arranged in a first corner area of the photosensitive element, the source follower transistor is arranged in a housing area of the transfer transistor away from the photosensitive element, the floating diffusion node is arranged in the housing area and on one side of the source follower transistor, the exposure transistor is arranged in a second corner area of the photosensitive element, the quantization transistor is arranged outside the housing area, and the reset transistor and the selection transistor are arranged outside the housing area.
10. The arrangement structure of the image sensor according to claim 9, characterized in that: When the pixel block includes a gain unit and the gain unit includes a gain transistor, the gain transistor is arranged outside the accommodating area and between the quantization transistor and the floating diffusion node; and / or, when the pixel block includes a fast reset unit and the fast reset unit includes a fast recovery transistor, the fast recovery transistor is arranged on a side of the connection area of the overflow capacitor away from the quantization transistor; and / or, the first corner area and the second corner area are arranged opposite to each other in the horizontal direction; and / or, the quantization transistor is arranged on a side of the floating diffusion node away from the source follower transistor; and / or, the connection area of the overflow capacitor is arranged on a side of the quantization transistor away from the floating diffusion node; and / or, the reset transistor and the selection transistor are respectively arranged above and below the source follower transistor.
11. The arrangement structure of the image sensor according to claim 10, characterized in that: The transfer transistor is arranged at a first angle in the first angle region, and the exposure transistor is arranged at a second angle in the second angle region, wherein the first angle is equal to the second angle.