Avionics system test equipment

Abstract

The utility model relates to the technical field of avionics system testing, and discloses avionics system testing equipment, which comprises a signal processing module, a communication module and a processor, and is characterized in that the signal processing module comprises a gigabit communication interface and a 100M communication interface; the communication module is used for being in communication connection with an avionics system through a gigabit communication interface or a 100M communication interface; the signal processing module is used for being in communication connection with the gigabit communication interface through a media independent interface and being in communication connection with the 100M communication interface through a port physical layer chip; and the processor is used for being in communication connection with the signal processing module through the bus interface. In the embodiment of the invention, the communication module comprises the gigabit communication interface and the 100M communication interface, so that the data transmission requirement in a large-scale integrated verification environment can be met, and meanwhile, the test requirement on the avionics system in the large-scale integrated verification environment can be met.

Description

Technical Field

[0001] The present invention relates to the technical field of avionics system testing, and in particular to avionics system testing equipment. Background Art

[0002] In avionics systems, ARINC664 protocol is widely used. At the same time, ARINC664 bus has many interfaces and complex communication protocols in applications. Therefore, in the process of bus testing, there are high requirements for ARINC664 protocol consistency of test data, ICD (Interface Control Document) parsing and processing, communication simulation and data monitoring records. However, in the relevant ARINC664 bus test scheme, some interfaces of the avionics system can be tested through the test board, which has great limitations and cannot meet the test requirements of the avionics system in a large integrated verification environment. Summary of the invention

[0003] In view of this, the present invention provides an avionics system test device to solve the problem that the test requirements for the avionics system in a large-scale integrated verification environment cannot be met.

[0004] In a first aspect, the present invention provides an avionics system test device, comprising: a signal processing module, a communication module, and a processor, wherein the signal processing module comprises: a gigabit communication interface and a 100M communication interface;

[0005] A communication module, used for communicating with the avionics system through a gigabit communication interface or a 100M communication interface;

[0006] A signal processing module, used for communicating with the Gigabit communication interface through a media independent interface, and communicating with the 100M communication interface through a port physical layer chip;

[0007] The processor is used to communicate with the signal processing module through a bus interface.

[0008] In an optional implementation, the communication module includes: a Gigabit communication interface and a 100M communication interface, wherein the Gigabit communication interface includes: a 24-port Gigabit optical cage interface, and the 100M communication interface includes: a 24-port 100M Ethernet interface;

[0009] A gigabit optical cage interface, used for data transmission at a rate of gigabit or less with the avionics system;

[0010] 100M Ethernet interface, used for data transmission with the avionics system at a rate of 100M or less.

[0011] In an optional implementation, the processor includes: a video transmission interface, a universal serial bus interface, and a Gigabit Ethernet interface;

[0012] Video transmission interface, used for communication connection with a display terminal;

[0013] Universal serial bus interface, used for communication connection with external devices;

[0014] The Gigabit Ethernet interface is used to communicate with the remote control device and transmit the received test instructions to the processor.

[0015] In an optional implementation, the signal processing module includes: a time synchronization submodule, wherein the time synchronization submodule is communicatively connected to the processor.

[0016] In an optional embodiment, the avionics system test equipment further includes: a communication indicator light, wherein the communication indicator light is connected to the communication module via an IO interface;

[0017] The communication indicator light is used to display the indicator light color corresponding to the transmission status of the communication module, wherein the transmission status includes at least one of the following: 10M speed status, 100M speed status and 1G speed status.

[0018] In an optional embodiment, the avionics system test equipment further includes: a power supply device;

[0019] The power supply device is used to supply power to at least some functional modules in the avionics system test equipment through a MOS switch, and to control the signal processing module and the power supply timing of the signal processing module through a DC MOS.

[0020] In an optional implementation, a power supply device includes: an AC / DC converter, a first converter, and a second converter;

[0021] An AC-DC converter, used for outputting DC power of a preset voltage;

[0022] A first converter, used for outputting a first rated voltage to power a gigabit optical cage interface in the communication module;

[0023] The second converter is used to output a second rated voltage to power the 100M Ethernet interface in the communication module, and to output a third rated voltage to power the memory.

[0024] In an optional implementation, the avionics system testing equipment further includes: a memory, wherein the memory is communicatively connected to the processor via a hard disk interface. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0026] Figure 1 is an architectural diagram of an avionics system test device according to an embodiment of the present invention;

[0027] Figure 2 An architectural diagram of another avionics system test device according to an embodiment of the present invention;

[0028] Figure 3 is an architectural diagram of another avionics system test device according to an embodiment of the present invention;

[0029] Figure 4 is an architectural diagram of yet another avionics system testing device according to an embodiment of the present invention;

[0030] Figure 5 This is a schematic diagram of time synchronization via IRIG-B;

[0031] Figure 6 This is a circuit diagram for converting single-ended signals to differential signals through the MAX3070 chip;

[0032] Figure 7 It is a schematic diagram of supplying power to various functional modules in the avionics system test equipment through a power supply device;

[0033] Figure 8 It is the principle block diagram of the avionics system test equipment;

[0034] Fig. 9 This is the block diagram of the FPGA chip;

[0035] Fig.10 It is a schematic diagram of the signal output in the FPGA chip;

[0036] Fig.11 This is the overall block diagram of the CPU board;

[0037] Fig.12 It is the principle block diagram of the baseboard corresponding to the avionics system test equipment. DETAILED DESCRIPTION

[0038] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0039] In conjunction with the application scenarios on which the execution of the avionics system test system depends, the application scenarios are described here.

[0040] In avionics systems, ARINC664 protocol is widely used. At the same time, ARINC664 bus has many interfaces and complex communication protocols in applications. Therefore, in the process of bus testing, there are high requirements for ARINC664 protocol consistency of test data, ICD (Interface Control Document) parsing and processing, communication simulation and data monitoring records. However, in the relevant ARINC664 bus test scheme, some interfaces of the avionics system can be tested through the test board, which has great limitations and cannot meet the test requirements of the avionics system in a large integrated verification environment.

[0041] The embodiment of the present invention provides an avionics system test device, including: a signal processing module, a communication module, and a processor, wherein the signal processing module includes: a gigabit communication interface and a 100M communication interface; a communication module for communicating with the avionics system through the gigabit communication interface or the 100M communication interface; a signal processing module for communicating with the gigabit communication interface through a media independent interface, and communicating with the 100M communication interface through a port physical layer chip; a processor for communicating with the signal processing module through a bus interface. In the embodiment of the present disclosure, the communication module includes a gigabit communication interface and a 100M communication interface, which can meet the data transmission requirements in a large-scale integrated verification environment, and can generate test data, and determine the test results based on the test data, so as to meet the test requirements for the avionics system in a large-scale integrated verification environment.

[0042] In this embodiment, an avionics system test device is provided, and the avionics system test device can be used to test the avionics system. Figure 1 is an architectural diagram of an avionics system test device according to an embodiment of the present invention. Figure 1 As shown, the avionics system test equipment includes: a communication module 10, a signal processing module 20, and a processor 30, wherein the signal processing module 10 includes: a gigabit communication interface and a 100M communication interface;

[0043] The communication module 10 is used to communicate with the avionics system through a gigabit communication interface or a 100M communication interface.

[0044] The signal processing module 20 is used for communication connection with the Gigabit communication interface through the media independent interface, and communication connection with the 100M communication interface through the port physical layer chip.

[0045] In the disclosed embodiment, the gigabit communication interface in the communication module is a fiber optic interface, which can be connected to the core board in the signal processing module through an SGMII interface (Serial Gigabit Media Independent Interface).

[0046] In addition, the 100M communication interface is an electrical interface, which can be connected to the core board through a port physical layer (Physical, hereinafter referred to as PHY) chip. In the present disclosure, when the above-mentioned avionics system communicates with the avionics system test equipment, the received data can be processed by the PHY chip. For example, digital signals or analog signals can be converted, and the converted data can be transmitted. The specific data processing and transmission process will not be repeated here.

[0047] In the disclosed embodiment, the above-mentioned avionics system is an avionics system, and the main function of the avionics system is to manage and control the information of the aircraft, to achieve the determination and control of the flight status, the measurement of aircraft status parameters, the management of the human-machine interface, navigation and communication and other mission guarantees, etc. The avionics system includes a series of subsystems, such as a human-machine interaction system, a flight status sensor system, a navigation system, an external sensor system and a mission automation system, etc. The avionics system processes the information of various avionics equipment on the aircraft in a unified manner through a unified processor, and combines equipment with the same or similar functions into one component, comprehensively displays relevant parameters, and transmits relevant information through the onboard data bus, so that the performance of all avionics equipment on the entire aircraft reaches a higher level.

[0048] In the above-mentioned avionics system, the target protocol is usually the ARINC664 protocol (hereinafter referred to as the AFDX protocol). As can be seen from the above, the avionics system includes multiple subsystems, and the types of flight parameters corresponding to different subsystems can be different. Therefore, when testing the avionics system through the above-mentioned signal processing module, the subsystem to be tested can be determined according to the test items, and the signal processing module can be used to generate test data according to the parameter type corresponding to the subsystem to be tested and the AFDX protocol. Specifically, the signal processing module may include a core board, and the core board includes an FPGA chip to generate test data through the FPGA chip.

[0049] When generating test data, the test data generation methods of protocol layer data stimulation and data layer data stimulation can be supported respectively. Specifically, the protocol layer data stimulation is used to test the AFDX protocol data of the above-mentioned avionics system, for example, to test whether the data generated by the avionics system complies with the AFDX protocol. The data layer data stimulation is used to test the user-side data of the above-mentioned avionics system, for example, to test whether the avionics system can generate correct user data in response to the test instruction.

[0050] The processor 30 is used to communicate with the signal processing module through a bus interface.

[0051] In the disclosed embodiment, the processor includes a CPU board, and the CPU can store the test data in a memory, and the memory can be a SATA hard disk (Serial ATA, i.e., a serial port hard disk), and specifically, the memory can be mSATA. Here, the CPU board and the memory can communicate through a serial hard disk interface, and the serial hard disk interface can be a SATA interface.

[0052] After the communication module obtains the feedback data sent by the avionics system in response to the test data, the feedback data can be sent to the above-mentioned signal processing module. Then, the signal processing module can feed back the feedback data to the processor through the bus interface so that the processor determines the test result according to the feedback data.

[0053] Specifically, considering that the CPU board generally adopts the PCIE protocol, the bus interface may be a PCIE interface, and in order to adapt to the data transmission rate of the communication module, the PCIE interface may be a PCIE×4 interface. It should be understood that, considering that the feedback data received by the signal processing module is AFDX protocol data, the feedback data may be format-converted according to the PCIE protocol before being transmitted to the CPU board.

[0054] When the processor determines the test result based on the feedback data of the test data, it can count whether the data volume of the feedback data matches the test data, and determine the test result based on the comparison result of the data volume. For example, if it is determined based on the data volume that the test data is output through port 24, but only feedback data from port 20 is received, then the test result is determined to be that the port that has not fed back data is faulty.

[0055] In addition, the feedback data may be verified based on the test data to determine the fault data, and the test result may be determined based on the source and type of the fault data. The test result may be used to indicate a port or subsystem of the avionics system that has not passed the test.

[0056] It can be known from the above description that the system test equipment in the present disclosure includes: a signal processing module, a communication module, and a processor, wherein the signal processing module includes: a gigabit communication interface and a 100M communication interface; a communication module for communicating with the avionics system through a gigabit communication interface or a 100M communication interface; a signal processing module for communicating with the gigabit communication interface through a media independent interface, and communicating with the 100M communication interface through a port physical layer chip; a processor for communicating with the signal processing module through a bus interface. In the embodiment of the present disclosure, the communication module includes a gigabit communication interface and a 100M communication interface, which can meet the data transmission requirements in a large-scale integrated verification environment, and can generate test data, and determine the test results based on the test data, so as to meet the test requirements for the avionics system in a large-scale integrated verification environment.

[0057] In this embodiment, another avionics system test device is provided, which can be used to test the avionics system. Figure 2 is an architecture diagram of another avionics system test device according to an embodiment of the present invention. Figure 2 As shown, the avionics system test equipment includes:

[0058] The communication module 10 is used to communicate with the avionics system through a gigabit communication interface or a 100M communication interface.

[0059] Specifically, the above-mentioned Gigabit communication interface includes: 24-port Gigabit optical cage interface 11, and the above-mentioned 100M communication interface includes: 24-port 100M Ethernet interface 12.

[0060] The communication module 10 is used to communicate with the avionics system through a gigabit communication interface or a 100M communication interface. Figure 1 The communication module 10 of the illustrated embodiment will not be described in detail herein.

[0061] Specifically, the above-mentioned Gigabit communication interface includes: 24-port Gigabit optical cage interface 11, and the above-mentioned 100M communication interface includes: 24-port 100M Ethernet interface 12.

[0062] The above-mentioned Gigabit optical cage interface 11 is used for data transmission with the avionics system at a rate of Gigabit or less.

[0063] The 100M Ethernet interface 12 is used to transmit data at a rate of 100M or less with the avionics system.

[0064] In the disclosed embodiment, the gigabit optical cage interface may be an SFP (Small Form Pluggable) interface, which may be used to convert gigabit electrical signals and optical signals, and the SFP interface may be installed on the bottom plate of the avionics system test equipment in a group of 8 ports. Here, the SFP interface may be connected to the signal processing module via a media independent interface, and the media independent interface may be an SGMII interface (Serial Gigabit Media Independent Interface). It should be understood that the SFP interface supports data transmission rates of 1000Mbps, 100Mbps, and 10Mbps.

[0065] In addition, the 100M Ethernet interface can be a 100M RJ45 interface, and the 100M RJ45 interface can be installed on the bottom plate of the avionics system test equipment in a group of 8 ports. Here, the 100M RJ45 interface can be connected to the signal processing module through a port physical layer chip, and the port physical layer chip is the above-mentioned PHY chip. It should be understood that the 100M RJ45 interface supports data transmission rates of 100Mbps and 10Mbps.

[0066] The signal processing module 20 is used to communicate with the 100M communication interface through the media independent interface and communicate with the 100M communication interface through the port physical layer chip. Figure 1 The signal processing module 20 of the illustrated embodiment will not be described in detail herein.

[0067] The processor 30 is used to communicate with the signal processing module through the bus interface. Figure 1 The processor 30 of the illustrated embodiment will not be described in detail herein.

[0068] In the embodiment of the present disclosure, the above-mentioned communication module may include 24-port Gigabit optical cage interfaces and 24-port 100M Ethernet interfaces, thereby supporting the configuration of multiple data transmission rate interfaces such as 10 / 100 / 1000Mbps, thereby improving the scope of application of the present disclosure.

[0069] In this embodiment, another avionics system test device is provided, which can be used to test the avionics system. Figure 3 is an architecture diagram of another avionics system test device according to an embodiment of the present invention. Figure 3 As shown, the avionics system test equipment includes:

[0070] The communication module 10 is used to communicate with the avionics system through a gigabit communication interface or a 100M communication interface. Figure 1The communication module 10 of the illustrated embodiment will not be described in detail herein.

[0071] The signal processing module 20 is used to communicate with the 100M communication interface through the media independent interface and communicate with the 100M communication interface through the port physical layer chip. Figure 1 The signal processing module 20 of the illustrated embodiment will not be described in detail herein.

[0072] The processor 30 is used to determine the test result according to the test data, and store the test result in the memory through the serial hard disk interface.

[0073] Specifically, the processor 30 includes: a video transmission interface 31, a universal serial bus interface 32 and a Gigabit Ethernet interface 33;

[0074] The video transmission interface 31 is used for communication connection with a display terminal.

[0075] The universal serial bus interface 32 is used for communication with external devices.

[0076] The Gigabit Ethernet interface 33 is used to communicate with the remote control device and transmit the received test instructions to the processor.

[0077] In the disclosed embodiment, the video transmission interface may be a VGA (Video Graphics Array) interface, which is used to connect to a display terminal to display the test results through the display terminal. In addition, the universal serial bus interface may be a USB (Universal Serial Bus) interface, which may be used to connect to external hardware devices, such as a USB flash drive, a mouse, etc.

[0078] In addition, considering that there may be a need for remote testing when testing the avionics system, the avionics system test equipment can be connected to the remote control device through the Gigabit Ethernet interface, so that the tester can issue a test instruction based on the remote control device, thereby realizing remote testing of the avionics system. Here, the Gigabit Ethernet interface can be a Gigabit RJ45 interface.

[0079] In the disclosed embodiment, the processor includes a Gigabit Ethernet interface that can be used to communicate with a remote control device, thereby supporting remote testing of the avionics system to adapt to a variety of testing environments and improve the user experience.

[0080] In this embodiment, another avionics system test device is provided. The avionics system test device can be used to test the avionics system. Figure 4is a structural diagram of another avionics system test device according to an embodiment of the present invention. Figure 4 As shown, the avionics system test equipment includes:

[0081] The communication module 10 is used to communicate with the avionics system through a gigabit communication interface or a 100M communication interface. Figure 1 The communication module 10 of the illustrated embodiment will not be described in detail herein.

[0082] The signal processing module 20 is used to communicate with the 100M communication interface through the media independent interface and communicate with the 100M communication interface through the port physical layer chip.

[0083] Specifically, the signal processing module 20 includes: a time synchronization submodule 21, wherein the time synchronization submodule is communicatively connected with the processor;

[0084] In the disclosed embodiment, the event synchronization submodule can be used to synchronize the standard time between the avionics system test equipment and the avionics system. Specifically, considering that the time standards adopted by the avionics system test equipment and the avionics system may be different, if the time standards of the two are not unified, it may affect the final test results. For example, if the first time standard adopted by the avionics system is Sydney time, and the second time standard adopted by the avionics system test equipment is London time, then a time coordinate can be established with the standard time, so that the first time standard and the second time standard can be converted under the time coordinate.

[0085] It should be understood that the standard time may be the same as the first time standard or the second time standard, for example, the standard time may be London time. Alternatively, the standard time may be different from the first time standard or the second time standard, for example, the standard time may be Beijing time.

[0086] For example, when determining the above-mentioned standard time, when the above-mentioned avionics system test equipment and the avionics system are in master-slave mode, the time standard of the master device can be determined as the standard time, and the time standard of the slave device can be converted. Here, the synchronization accuracy during the conversion process can be 0.5us.

[0087] Specifically, the time synchronization submodule may be used to synchronize the time standard between the avionics system test equipment and the avionics system. Here, the time synchronization submodule may be IRIG-B (inter-range instrumentation group-B).

[0088] like Figure 5The figure shows a schematic diagram of time synchronization through IRIG-B, wherein, when the core board includes three FPGA chips, the three FPGA chips (FPGA1-FPGA3) can be connected between boards in an end-to-end manner through an IO interface.

[0089] Specifically, when IRIG-B communicates with the avionics system, it can use the HDMI interface (High Definition Multimedia Interface) to obtain the differential signal input by the avionics system, and after converting the differential signal to a single-ended signal, it can be input to the common IO port of FPGA1, and finally output the processed single-ended signal through FPGA3. Then, the single-ended signal can be converted into a differential signal and sent to the avionics system through the HDMI interface to achieve the conversion of the avionics system time standard.

[0090] The device model used for converting single-ended signals to differential signals in the above IRIG-B can be the MAX3070 chip, such as Figure 6 The circuit diagram shown is a circuit diagram for converting single-ended signals to differential signals through the MAX3070 chip. The specific signal conversion method is not described in detail in this disclosure.

[0091] The processor 30 is used to communicate with the signal processing module through the bus interface. Figure 1 The processor 30 of the illustrated embodiment will not be described in detail herein.

[0092] In the disclosed embodiment, the time standards of the synchronous avionics system test equipment and the avionics system can be unified through standard time, thereby avoiding the impact of inconsistent time standards on the test results.

[0093] In an optional embodiment, the above Figure 1 The corresponding avionics system test equipment further includes: a communication indicator light 40, wherein the communication indicator light 40 is connected to the communication module 20 via an IO interface;

[0094] The communication indicator light 40 is used to display the indicator light color corresponding to the transmission status of the communication module, wherein the transmission status includes at least one of the following: a 10M speed status, a 100M speed status, and a 1G speed status.

[0095] In the disclosed embodiment, the communication indicator light may be used to indicate the transmission status of the communication module. For example, the communication indicator light may be a dual-color LED (Light Emitting Diode), and different transmission rates in the communication module correspond to different light emission modes of the dual-color LED.

[0096] As can be seen from the above, there are usually multiple communication ports in the above communication module, so a corresponding LED can be set for each port. For example, when there are 24 communication ports in the communication module, the number of LEDs can also be 24, and they correspond one to one with the communication ports.

[0097] In addition, the above-mentioned avionics system test equipment may also include a status indicator light, which can be used to indicate the operating status of each functional module in the avionics system test equipment. For example, LED1 can be used to indicate the connectivity status of the power interface; LED2 can be used to indicate the connectivity status of the switch; LED3 can be used to indicate the connectivity status of the above-mentioned Gigabit RJ45 interface; LED4 can be used to indicate the connectivity status of the above-mentioned USB interface; LED5 can be used to indicate the connectivity status of the above-mentioned VGA interface; LED6 can be used to indicate the connectivity status of the above-mentioned HDMI interface; LED7-LED30 can be used to indicate the connectivity status of the above-mentioned communication ports; LED31 can be used to indicate whether the self-test results of each functional module in the above-mentioned avionics system test equipment are faulty.

[0098] In the disclosed embodiment, the operation status of the avionics system test equipment can be indicated by the communication indicator light and the status indicator light, so that the tester can better grasp the test progress and improve the user experience of the tester.

[0099] In an optional embodiment, the above Figure 1 The corresponding avionics system test equipment further includes: a power supply device 50;

[0100] The power supply device 50 is used to supply power to at least some functional modules in the avionics system test equipment through a MOS switch, and to control the signal processing module and the power supply timing of the signal processing module through a DC MOS.

[0101] Specifically, the power supply device comprises: an AC / DC converter 51, a first converter 52 and a second converter 53;

[0102] The AC-DC converter 51 is used to output DC power of a preset voltage;

[0103] A first converter 52, used for outputting a first rated voltage to power the gigabit optical cage interface in the communication module;

[0104] The second converter 53 is used to output a second rated voltage to power the 100M Ethernet interface in the communication module, and output a third rated voltage to power the memory.

[0105] In the embodiments of the present disclosure, Figure 7The schematic diagram of powering each functional module in the avionics system test equipment through the power supply device is shown, wherein the DC MOS is the above-mentioned direct current MOS, which is used to power the core board and the FPGA chip in the signal processing module according to the preset power supply timing, and the MOS switch is used to control whether to output current to Figure 7 In addition, the AC-DC converter Figure 7 Not shown.

[0106] Depend on Figure 7 It can be seen that the 3-way LTM4600 chip outputs a 3.3V voltage to provide power for the 24-port SFP interface (i.e. the above-mentioned Gigabit optical cage interface). Therefore, the above-mentioned first converter is used to convert the DC power of the preset voltage into 3.3V DC power.

[0107] In addition, Figure 7 The 3.3V voltage output by one LTM4622 chip is used to power three PHY chips. At the same time, the 2.5V and 1.5V currents output by one LTM4622 chip are used to power three PHY chip units, thereby realizing the power supply for the Ethernet interface. Therefore, the second converter is used to convert the DC power of the preset voltage into 3.3V and 2.5V DC power.

[0108] At the same time, Figure 7 The 3.3V current output by the LTM4622 chip in the middle channel is used to power the mSATA (ie, the above-mentioned memory), so the above-mentioned second converter is used to convert the DC power of the preset voltage into the DC power of 3.3V.

[0109] In addition, Figure 7 The middle LTM4600 chip outputs 5V voltage to provide voltage for the above-mentioned USB interface and fan, and also provides input voltage for the LTM4622 chip.

[0110] In the disclosed embodiment, multiple LTM4600 chips and LTM4622 chips can be used to power various functional modules in the avionics system test equipment, thereby improving power supply reliability and further improving the stability of the operation of the avionics system test equipment.

[0111] In an optional embodiment, the above Figure 1 The corresponding avionics system test equipment further includes: a memory 60, wherein the memory is communicatively connected to the processor via a hard disk interface.

[0112] In the embodiment of the present disclosure, the memory is the above-mentioned Figure 1 The SATA hard disk in the corresponding embodiment has a hard disk interface that is the above-mentioned SATA interface.

[0113] In an optional embodiment, if Figure 8 Shown above Figure 1 The principle block diagram of the corresponding avionics system test equipment, wherein the avionics system test equipment includes: 3×8 optical cages (i.e. the above-mentioned Gigabit optical cage interface), IRIGB (i.e. the above-mentioned time synchronization submodule), Ethernet interface (i.e. the above-mentioned Gigabit Ethernet interface), USB interface × 3, VGA interface, core board, CPU board, MiniSATA (i.e. the above-mentioned mSATA), 3×8RJ45 (i.e. the above-mentioned 100M Ethernet interface).

[0114] 3×8 optical cages are used for data transmission at Gigabit or below with the above-mentioned avionics systems.

[0115] In the disclosed embodiment, the implementation example of the 3×8 optical cage is as described in the above-mentioned embodiment corresponding to the communication module 10 and will not be described in detail here.

[0116] IRIGB is used to synchronize the standard time between the above-mentioned avionics system test equipment and the avionics system.

[0117] In the embodiment of the present disclosure, the implementation example of IRIGB is as described in the embodiment corresponding to the above-mentioned time synchronization submodule 21, and will not be repeated here.

[0118] The Ethernet interface is used to communicate with the remote control device and transmit the received test instructions to the processor.

[0119] In the embodiment of the present disclosure, the implementation example of the Ethernet interface is as described in the embodiment corresponding to the above-mentioned Gigabit Ethernet interface 33, which will not be repeated here.

[0120] USB ports × 3, used for communication with external devices.

[0121] In the embodiment of the present disclosure, the implementation example of the USB interface is as described in the embodiment corresponding to the universal serial bus interface 32 above, and will not be repeated here.

[0122] VGA interface, used for communication connection with a display terminal.

[0123] In the embodiment of the present disclosure, the implementation example of the VGA interface is as described in the embodiment corresponding to the above-mentioned video transmission interface 31, and will not be repeated here.

[0124] The core board is used to generate test data corresponding to the target protocol of the avionics system.

[0125] In the disclosed embodiment, the external interfaces of the core board COMe mainly use PCIE interface, USB interface, VGA interface, RJ45 interface, SATA interface and power supply. The PCIE interface uses the original PCIE X16 interface, and the PCIE interface clock uses ICS8543 for clock fan-out.

[0126] It should be understood that the above core board uses an FPGA chip as the core. Fig. 9 The block diagram of the FPGA chip shown in FIG. 1 mainly uses the PCIE interface, the mgt interface (i.e., the management interface), and the GPIO (General-purpose input / output) interface. Specifically, Fig.10 The figure shows a schematic diagram of signal output in the FPGA chip. The specific signal output implementation example is as described above. Figure 1 The corresponding embodiments are described and will not be repeated here.

[0127] The CPU board is used to determine the test result according to the test data and store the test result in the memory through the serial hard disk interface.

[0128] In the disclosed embodiment, the CPU board is COMe-63A, and its basic parameters are as follows: using CPU i7-6820EQ, DDR4 16G static power consumption is 8.5W, maximum power consumption is 58W (Burn-in V7.0 Pro / Boost mode), and the external interface is COMe (cluster communication port-e, serial communication) interface. Fig.11 The figure shows an overall block diagram of the CPU board. In addition, the implementation example of the CPU board is as described in the implementation example corresponding to the above-mentioned processor 30, which will not be repeated here.

[0129] MiniSATA, used to store the above test results.

[0130] 3×8RJ45, used for data transmission with the avionics system at a rate of 100 Mbps or less.

[0131] In the embodiments of the present disclosure, Fig.11 The figure shows the internal structure block diagram of the above RJ45 interface, and the present disclosure does not make any detailed description of the internal structure.

[0132] It should be understood that if Figure 8 The various functional modules in the avionics system test equipment shown in FIG. are installed on the bottom plate, specifically, Fig.12 Shown with Figure 8 The corresponding bottom board principle block diagram should be understood that COMe is the above core board, LED is the above Figure 1 In the corresponding embodiment, the LED, IRIG is the above-mentioned IRIG-B, and FAN is a fan.

[0133] In addition, when installing the above-mentioned avionics system test equipment, the interface switching function can be realized by adjusting the installation method of the base plate, for example, the interface can be switched to a gigabit interface or a 100 megabit interface.

[0134] In summary, the system test equipment in the present disclosure includes: a signal processing module, a communication module, and a processor, wherein the signal processing module includes: a gigabit communication interface and a 100M communication interface; a communication module for communicating with the avionics system through a gigabit communication interface or a 100M communication interface; a signal processing module for communicating with the gigabit communication interface through a media independent interface, and communicating with the 100M communication interface through a port physical layer chip; a processor for communicating with the signal processing module through a bus interface. In the embodiment of the present disclosure, the communication module includes a gigabit communication interface and a 100M communication interface, which can meet the data transmission requirements in a large-scale integrated verification environment, and can generate test data, and determine the test results based on the test data, so as to meet the test requirements for the avionics system in a large-scale integrated verification environment.

[0135] Those skilled in the art will appreciate that, in the above method of specific implementation, the order in which the steps are written does not imply a strict execution order and does not constitute any limitation on the implementation process. The specific execution order of the steps should be determined by their functions and possible internal logic.

[0136] Those skilled in the art can clearly understand that, for the convenience and simplicity of description, the specific working process of the system and device described above can refer to the corresponding process in the aforementioned method embodiment, and will not be repeated here. In the several embodiments provided in the present disclosure, it should be understood that the disclosed system, device and method can be implemented in other ways. The device embodiments described above are merely schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation. For example, multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some communication interfaces, and the indirect coupling or communication connection of the device or unit can be electrical, mechanical or other forms.

[0137] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

[0138] In addition, each functional unit in each embodiment of the present disclosure may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0139] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a non-volatile computer-readable storage medium that is executable by a processor. Based on this understanding, the technical solution of the present disclosure, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product, which is stored in a storage medium and includes several instructions for a computer device (which can be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in each embodiment of the present disclosure. The aforementioned storage medium includes: various media that can store program codes, such as a USB flash drive, a mobile hard disk, a read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0140] Finally, it should be noted that the above-described embodiments are only specific implementation methods of the present disclosure, which are used to illustrate the technical solutions of the present disclosure, rather than to limit them. The protection scope of the present disclosure is not limited thereto. Although the present disclosure is described in detail with reference to the above-described embodiments, ordinary technicians in the field should understand that any technician familiar with the technical field can still modify the technical solutions recorded in the above-described embodiments within the technical scope disclosed in the present disclosure, or can easily think of changes, or make equivalent replacements for some of the technical features therein; and these modifications, changes or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present disclosure, and should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. An avionics system test equipment, characterized in that: include: A signal processing module, a communication module, and a processor, wherein the signal processing module includes: a gigabit communication interface and a 100M communication interface; The communication module is used to communicate with the avionics system through the Gigabit communication interface or the 100M communication interface; The signal processing module is used to communicate with the Gigabit communication interface through a media independent interface, and to communicate with the 100M communication interface through a port physical layer chip; The processor is used to communicate with the signal processing module through a bus interface.

2. The avionics system test equipment according to claim 1, characterized in that: The communication module includes: a Gigabit communication interface and a 100M communication interface, wherein the Gigabit communication interface includes: a 24-port Gigabit optical cage interface, and the 100M communication interface includes: a 24-port 100M Ethernet interface; The Gigabit optical cage interface is used to perform data transmission at a rate of Gigabit or less with the avionics system; The 100M Ethernet interface is used to perform data transmission at a rate of 100M or less with the avionics system.

3. The avionics system test equipment according to claim 1, characterized in that: The processor includes: a video transmission interface, a universal serial bus interface and a Gigabit Ethernet interface; The video transmission interface is used to communicate with the display terminal; The universal serial bus interface is used for communication connection with external devices; The Gigabit Ethernet interface is used to communicate with the remote control device and transmit the received test instructions to the processor.

4. The avionics system test equipment according to claim 1, characterized in that: The signal processing module includes: a time synchronization submodule, wherein the time synchronization submodule is communicatively connected with the processor.

5. The avionics system test equipment according to claim 1, characterized in that: The avionics system test equipment further includes: a communication indicator light, wherein the communication indicator light is communicatively connected to the communication module via an IO interface; The communication indicator light is used to display the indicator light color corresponding to the transmission status of the communication module, wherein the transmission status includes at least one of the following: a 10M rate state, a 100M rate state, and a 1G rate state.

6. The avionics system test equipment according to claim 1, characterized in that: The avionics system test equipment further includes: a power supply device; The power supply device is used to supply power to at least some functional modules in the avionics system test equipment through a MOS switch, and to control the signal processing module and the power supply timing of the signal processing module through a DC MOS.

7. The avionics system test equipment according to claim 6, characterized in that: The power supply device comprises: an AC / DC converter, a first converter and a second converter; The AC-DC converter is used to output DC power of a preset voltage; The first converter is used to output a first rated voltage to power the gigabit optical cage interface in the communication module; The second converter is used to output a second rated voltage to power the 100M Ethernet interface in the communication module, and to output a third rated voltage to power the memory.

8. The avionics system test equipment according to claim 1, characterized in that: The avionics system testing equipment further includes: a memory, wherein the memory is communicatively connected to the processor via a hard disk interface.

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