Display substrate and display device

Abstract

The utility model discloses a display substrate and a display device. The display substrate comprises a plurality of circuit units, and each circuit unit comprises a pixel driving circuit, a first power line and at least one shading structure. The pixel driving circuit at least comprises a first transistor, a second transistor and a storage capacitor. In the direction perpendicular to the display substrate, the display substrate at least comprises a first conducting layer arranged on the substrate and a plurality of conducting layers arranged on the side, away from the substrate, of the first conducting layer, and gate electrodes of the first transistor and the second transistor are arranged in the first conducting layer. The at least one shading structure is arranged in any one or more of the plurality of conductive layers, and the orthographic projection of the shading structure on the substrate is at least partially overlapped with the orthographic projection of the gate electrode of the first transistor and / or the gate electrode of the second transistor on the substrate. By arranging the shading structure, a light leakage area is eliminated, the characteristic change of the first transistor and / or the second transistor is effectively avoided, and the problems of powdering and the like are effectively solved.

Description

Technical Field

[0001] The present invention relates to but is not limited to the field of display technology, and specifically to a display substrate and a display device. Background Art

[0002] Organic Light Emitting Diode (OLED) and Quantum-dot Light Emitting Diode (QLED) are active light-emitting display devices with the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, extremely high response speed, thinness, bendability and low cost. With the continuous development of display technology, flexible display devices (Flexible Display) using OLED or QLED as light-emitting devices and controlled by transistors (Thin Film Transistor, TFT) for signal control have become the mainstream products in the current display field. Utility Model Content

[0003] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of the claims.

[0004] The technical problem to be solved by the embodiments of the present disclosure is to provide a display substrate and a display device to solve the problem of powdering and the like in the existing display devices.

[0005] On the one hand, the present disclosure provides a display substrate, including multiple circuit units, at least one circuit unit including a pixel driving circuit, a first power line and at least one shading structure; the pixel driving circuit includes at least a first transistor, a second transistor and a storage capacitor, the storage capacitor includes a stacked first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to the first power line; in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer arranged on a substrate and multiple conductive layers arranged on a side of the first conductive layer away from the substrate, the gate electrode of the first transistor and the gate electrode of the second transistor are arranged in the first conductive layer, at least one shading structure is arranged in any one or more layers of the multiple conductive layers, and the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor and / or the gate electrode of the second transistor on the substrate.

[0006] In an exemplary embodiment, the first power line is arranged on one side of the second transistor in a first direction, the storage capacitor is arranged on one side of the second direction of the second transistor, and the first direction and the second direction intersect; the gate electrode of the second transistor includes a third sub-gate electrode extending along the first direction and forming a third channel region and a fourth sub-gate electrode extending along the second direction and forming a fourth channel region, and the fourth sub-gate electrode is arranged on one side of the third sub-gate electrode in the first direction; the shading structure is arranged on one side of the third channel region in the first direction, and the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode on the substrate.

[0007] In an exemplary embodiment, an orthographic projection of the light shielding structure on the substrate and an orthographic projection of the fourth sub-gate electrode on the substrate have a gate overlapping region, and in the first direction, a width of the gate overlapping region is greater than or equal to 0.5 μm.

[0008] In an exemplary embodiment, an orthographic projection of the light shielding structure on the substrate at least partially overlaps with an orthographic projection of the fourth channel region on the substrate.

[0009] In an exemplary embodiment, the fourth channel region has a channel area, the orthographic projection of the light shading structure on the substrate and the orthographic projection of the fourth channel region on the substrate have a channel overlapping region, the channel overlapping region has an overlapping area, and the ratio of the overlapping area to the channel area is greater than or equal to 0.05.

[0010] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one light-shielding structure includes a first light-shielding block arranged in the fourth conductive layer, the first light-shielding block is arranged on one side of the first direction of the third channel region, the orthographic projection of the first light-shielding block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a first overlapping area, and the shape of the first overlapping area is a strip shape extending along the second direction.

[0011] In an exemplary embodiment, the first light shielding block and the first power line are an integrated structure connected to each other.

[0012] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one light-shielding structure includes a second light-shielding block arranged in the third conductive layer, the second light-shielding block is arranged on one side of the first direction of the third channel region, the orthographic projection of the second light-shielding block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a second overlapping area, and the shape of the second overlapping area is a strip shape extending along the second direction.

[0013] In an exemplary embodiment, a gate electrode of the second transistor is connected to a first scan signal line, and the second light shielding block and the first scan signal line are an integral structure connected to each other.

[0014] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one light-shielding structure includes a third light-shielding block arranged in the second conductive layer, and the third light-shielding block is arranged on one side of the first direction of the third channel region, and the orthographic projection of the third light-shielding block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a third overlapping area, and the shape of the third overlapping area is a strip shape extending along the second direction.

[0015] In an exemplary embodiment, at least one circuit unit also includes a first shielding electrode, a first end of the first shielding electrode is connected to the second electrode plate, a second end of the first shielding electrode has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of a second active layer between two gate electrodes of the second transistor on the substrate, and the third shading block and the first shielding electrode are an integral structure that are interconnected.

[0016] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one shading structure includes a fourth shading block arranged in the second conductive layer, the fourth shading block is arranged on a side of the fourth channel region away from the storage capacitor, the orthographic projection of the fourth light shading block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a fourth overlapping area, and the shape of the fourth overlapping area is a strip shape extending along the first direction.

[0017] In an exemplary embodiment, at least one circuit unit also includes a first shielding electrode, a first end of the first shielding electrode is connected to the second electrode plate, a second end of the first shielding electrode has an orthographic projection on the substrate that at least partially overlaps with an orthographic projection of a second active layer between two gate electrodes of the second transistor on the substrate, and the fourth shading block and the first shielding electrode are an integral structure that are interconnected.

[0018] In an exemplary embodiment, the first power line is arranged on one side of the second transistor in a first direction, the storage capacitor is arranged on one side of the second transistor in a second direction, and the first direction and the second direction intersect; the first transistor is arranged on a side of the second transistor away from the storage capacitor, the first transistor includes a first sub-gate electrode forming a first channel region and a second sub-gate electrode forming a second channel region, and the second sub-gate electrode is arranged on one side of the first sub-gate electrode in the first direction; the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second sub-gate electrode on the substrate, and the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second channel region on the substrate.

[0019] In an exemplary embodiment, at least one light-shielding structure includes a fifth light-shielding block, and at least one fifth light-shielding block is arranged on a side of the second transistor away from the storage capacitor, the fifth light-shielding block and the first power line are an integral structure connected to each other, the orthographic projection of the fifth light-shielding block on the substrate at least partially overlaps with the orthographic projection of the first sub-gate electrode on the substrate, and the orthographic projection of the fifth light-shielding block on the substrate at least partially overlaps with the orthographic projection of the first channel region on the substrate.

[0020] In an exemplary embodiment, at least one circuit unit further includes a second shielding electrode and at least one initial signal line, wherein the initial signal line is configured to provide an initial signal to the pixel driving circuit, the second shielding electrode is connected to the initial signal line, and an orthographic projection of the second shielding electrode on the substrate at least partially overlaps with an orthographic projection of the first active layer between the two gate electrodes of the first transistor on the substrate.

[0021] In an exemplary embodiment, an orthographic projection of the second shielding electrode on the substrate at least partially overlaps an orthographic projection of the first power line on the substrate.

[0022] In an exemplary embodiment, the display substrate further includes a shielding layer disposed between the substrate and the first conductive layer, the shielding layer including at least a first shielding block and a second shielding block, the orthographic projection of the first shielding block on the substrate including the orthographic projection of the gate electrode of the second transistor on the substrate, and the orthographic projection of the second shielding block on the substrate including the orthographic projection of the gate electrode of the first transistor on the substrate.

[0023] On the other hand, the present disclosure further provides a display device, comprising the aforementioned display substrate.

[0024] The embodiments of the present disclosure provide a display substrate and a display device. By setting a shading structure, the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor and / or the gate electrode of the second transistor on the substrate, thereby eliminating the light leakage area, effectively avoiding the change of the characteristics of the first transistor and / or the second transistor, and effectively solving the problem of powdering.

[0025] Other aspects will be apparent upon reading and understanding the drawings and detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The accompanying drawings are used to provide an understanding of the technical solution of the present disclosure and constitute a part of the specification. Together with the embodiments of the present disclosure, they are used to explain the technical solution of the present disclosure and do not constitute a limitation on the technical solution of the present disclosure.

[0027] Figure 1 is a structural schematic diagram of a display device;

[0028] Figure 2 It is a schematic diagram of a planar structure of a display substrate;

[0029] Figure 3 A schematic diagram of a cross-sectional structure of a display substrate;

[0030] Figure 4 is a schematic diagram of an equivalent circuit of a pixel driving circuit;

[0031] Figure 5 A schematic diagram of a planar structure of a display substrate according to an exemplary embodiment of the present disclosure;

[0032] Figure 6 This is a schematic diagram of a display substrate after a shielding layer pattern is formed on the display substrate of the present disclosure;

[0033] Fig. 7A and Figure 7B This is a schematic diagram of a display substrate after a semiconductor layer pattern is formed on the display substrate of the present disclosure;

[0034] Fig. 8A and Figure 8BThis is a schematic diagram of a display substrate after a first conductive layer pattern is formed on the display substrate of the present disclosure;

[0035] Fig. 9A and Fig. 9B This is a schematic diagram of a display substrate after a second conductive layer pattern is formed on the display substrate of the present disclosure;

[0036] Fig.10 This is a schematic diagram of a display substrate after a fourth insulating layer pattern is formed on the display substrate of the present disclosure;

[0037] Fig.11A and Fig. 11B This is a schematic diagram of a display substrate after a third conductive layer pattern is formed on the display substrate of the present disclosure;

[0038] Fig.12 This is a schematic diagram of a display substrate after a first flat layer pattern is formed in the present disclosure;

[0039] Fig.13A and Fig. 13B This is a schematic diagram of a display substrate after a fourth conductive layer pattern is formed on the display substrate of the present disclosure;

[0040] Fig.14 This is a schematic diagram of a display substrate after a second flat layer pattern is formed on the display substrate of the present disclosure;

[0041] Fig.15A and Fig. 15B This is a schematic diagram of a display substrate after an anode conductive layer pattern is formed in the present disclosure;

[0042] Fig.16 This is a schematic diagram of a display substrate after a pixel definition layer pattern is formed on the display substrate of the present disclosure;

[0043] Fig.17 for Fig.15A A magnified image of area A;

[0044] Fig.18 for Fig.17 Sectional view along AA direction;

[0045] Fig.19 is a schematic diagram of a second transistor T2 being irradiated by light;

[0046] Fig. 20 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0047] Fig.21 for Fig. 20 A plan view of the third conductive layer;

[0048] Fig. 22 for Fig. 20 Cross-sectional view along the BB direction;

[0049] Fig.23 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0050] Fig.24 for Fig.23 A plan view of the second conductive layer;

[0051] Fig.25 for Fig.23 Sectional view along CC direction;

[0052] Fig.26 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0053] Fig. 27 for Fig.26 A plan view of the second conductive layer;

[0054] Fig.28 It is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure;

[0055] Fig.29 for Fig.28 A plan view of the fourth conductive layer;

[0056] Fig.30 The diagram is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure.

[0057] Description of reference numerals:

[0058] 10—substrate; 10A—first insulating layer; 10B—second insulating layer;

[0059] 10C—third insulating layer; 10D—fourth insulating layer; 10E—first flat layer;

[0060] 10F—second flat layer; 11—first active layer; 12—second active layer;

[0061] 13—third active layer; 14—fourth active layer; 15—fifth active layer;

[0062] 16—sixth active layer; 17—seventh active layer; 21—first gate electrode;

[0063] 22—second gate electrode; 24—fourth gate electrode; 27—seventh gate electrode;

[0064] 31—first scanning signal line; 32—second scanning signal line; 33—light emitting signal line;

[0065] 35—first shielding electrode; 36—second shielding electrode; 41—first initial signal line;

[0066] 42—second initial signal line; 43—first power connection line; 44—second power connection line;

[0067] 51—first connecting electrode; 52—second connecting electrode; 53—third connecting electrode;

[0068] 54—fourth connecting electrode; 61—first power line; 62—second power line;

[0069] 63—data signal line; 64—anode connection electrode; 71—first initial connection line;

[0070] 72—second initial connection line; 81—first electrode plate; 82—second electrode plate;

[0071] 83—board-level connecting strip; 84—opening; 90-1—first shielding connecting strip;

[0072] 90-2—second shielding connection strip; 90-3—third shielding connection strip; 90-4—fourth shielding connection strip;

[0073] 90A—first anode; 90B—second anode; 90C—third anode;

[0074] 91—first shielding electrode; 92—second shielding electrode; 93—third shielding electrode;

[0075] 94—fourth shielding electrode; 101—substrate; 102—driving structure layer;

[0076] 103—light emitting structure layer; 104—encapsulation structure layer; 110—first light shielding block;

[0077] 120—second light shielding block; 130—third light shielding block; 140—fourth light shielding block;

[0078] 150—Fifth shading block. DETAILED DESCRIPTION

[0079] In order to make the purpose, technical solutions and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail in conjunction with the accompanying drawings below. Note that the embodiments can be implemented in multiple different forms. A person of ordinary skill in the art can easily understand the fact that the methods and contents can be transformed into various forms without departing from the purpose and scope of the present disclosure. Therefore, the present disclosure should not be interpreted as being limited to the contents described in the following embodiments. In the absence of conflict, the embodiments in the present disclosure and the features in the embodiments can be arbitrarily combined with each other.

[0080] The proportions of the drawings in this disclosure can be used as a reference in the actual process, but are not limited to this. For example: the width-to-length ratio of the channel, the thickness and spacing of each film layer, the width and spacing of each signal line can be adjusted according to actual needs. The number of pixels in the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the figures. The drawings described in this disclosure are only structural schematic diagrams, and one method of this disclosure is not limited to the shapes or values ​​shown in the drawings.

[0081] In the present specification, ordinal numbers such as “first”, “second” and “third” are provided to avoid confusion among constituent elements, and are not intended to limit the number.

[0082] In this specification, for the sake of convenience, the words and phrases indicating the orientation or positional relationship, such as "middle", "upper", "lower", "front", "back", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., are used to illustrate the positional relationship of the constituent elements with reference to the drawings. This is only for the convenience of describing this specification and simplifying the description, and does not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation, and therefore cannot be understood as a limitation of the present disclosure. The positional relationship of the constituent elements is appropriately changed according to the direction in which each constituent element is described. Therefore, it is not limited to the words and phrases described in the specification, and can be appropriately replaced according to the situation.

[0083] In this specification, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, or an electrical connection; it can be a direct connection, or an indirect connection through an intermediate, or the internal communication of two elements. For ordinary technicians in this field, the specific meanings of the above terms in this disclosure can be understood according to specific circumstances.

[0084] In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. The transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to a region where current mainly flows.

[0085] In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. In the case of using transistors with opposite polarities or when the current direction changes during circuit operation, the functions of the "source electrode" and the "drain electrode" are sometimes interchanged. Therefore, in this specification, the "source electrode" and the "drain electrode" may be interchanged, and the "source terminal" and the "drain terminal" may be interchanged.

[0086] In this specification, "electrical connection" includes the case where components are connected together through an element having some electrical function. There is no particular limitation on the "element having some electrical function" as long as it can transmit and receive electrical signals between the connected components. Examples of "element having some electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0087] In this specification, "parallel" means a state where the angle formed by two straight lines is greater than -10° and less than 10°, and therefore, also includes a state where the angle is greater than -5° and less than 5°. In addition, "perpendicular" means a state where the angle formed by two straight lines is greater than 80° and less than 100°, and therefore, also includes a state where the angle is greater than 85° and less than 95°.

[0088] In this specification, "film" and "layer" may be interchanged. For example, "conductive layer" may be replaced by "conductive film". Similarly, "insulating film" may be replaced by "insulating layer".

[0089] The triangles, rectangles, trapezoids, pentagons or hexagons in this specification are not in the strict sense, and may be approximate triangles, rectangles, trapezoids, pentagons or hexagons, etc. There may be some small deformations caused by tolerances, and there may be chamfers, arc edges and deformations.

[0090] The term "about" in the present disclosure refers to a numerical value that is not strictly limited to allow for process and measurement errors.

[0091] Figure 1 FIG. 1 is a schematic diagram of the structure of a display device. Figure 1As shown, the display device may include a timing controller, a data driver, a scan driver, a light emitting driver and a pixel array, the timing controller is respectively connected to the data driver, the scan driver and the light emitting driver, the data driver is respectively connected to a plurality of data signal lines (D1 to Dn), the scan driver is respectively connected to a plurality of scan signal lines (S1 to Sm), and the light emitting driver is respectively connected to a plurality of light emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, i and j may be natural numbers, at least one sub-pixel Pxij may include a circuit unit and a light emitting unit, the circuit unit may include at least a pixel driving circuit, the pixel driving circuit is respectively connected to the scan signal line, the light emitting signal line and the data signal line, the light emitting unit may include a light emitting device, and the light emitting device is connected to the pixel driving circuit of the circuit unit. In an exemplary embodiment, the timing controller may provide a grayscale value and a control signal suitable for the specification of the data driver to the data driver, may provide a clock signal suitable for the specification of the scan driver, a scan start signal, etc. to the scan driver, and may provide a clock signal suitable for the specification of the light emitting driver, an emission stop signal, etc. to the light emitting driver. The data driver can generate data voltages to be provided to data signal lines D1, D2, D3, ... and Dn using grayscale values ​​and control signals received from the timing controller. For example, the data driver can sample grayscale values ​​using a clock signal, and apply data voltages corresponding to grayscale values ​​to data signal lines D1 to Dn in units of pixel rows, where n can be a natural number. The scan driver can generate scan signals to be provided to scan signal lines S1, S2, S3, ... and Sm by receiving clock signals, scan start signals, etc. from the timing controller. For example, the scan driver can sequentially provide scan signals with conduction level pulses to scan signal lines S1 to Sm. For example, the scan driver can be constructed in the form of a shift register, and can sequentially transmit scan start signals provided in the form of conduction level pulses to the next level circuit under the control of the clock signal to generate scan signals, where m can be a natural number. The light-emitting driver can generate emission signals to be provided to light-emitting signal lines E1, E2, E3, ... and Eo by receiving clock signals, emission stop signals, etc. from the timing controller. For example, the light emitting driver may sequentially provide an emission signal having a cut-off level pulse to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate an emission signal in a manner of sequentially transmitting an emission stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, and o may be a natural number. In an exemplary embodiment, a pixel array may be provided on a display substrate.

[0092] Figure 2 FIG. 1 is a schematic diagram of a planar structure of a display substrate. Figure 2As shown, the display substrate may include a plurality of pixel units P arranged in a matrix, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 emitting a third color light. Each sub-pixel may include a circuit unit and a light-emitting unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scanning signal line, the data signal line, and the light-emitting signal line, and the pixel driving circuit is configured to receive the data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a corresponding current to the light-emitting unit. The light-emitting unit in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel, and the light-emitting unit is configured to emit light of corresponding brightness in response to the current output by the pixel driving circuit of the sub-pixel.

[0093] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) emitting red light, the second sub-pixel P2 may be a green sub-pixel (G) emitting green light, and the third sub-pixel P3 may be a blue sub-pixel (B) emitting blue light. In an exemplary embodiment, the shape of the sub-pixels may be rectangular, rhombus, pentagonal or hexagonal, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel or triangular manner, which is not limited in the present disclosure.

[0094] In other exemplary embodiments, the pixel unit may include four sub-pixels, and the four sub-pixels may be arranged in parallel horizontally, in parallel vertically, or in a square, etc., which is not limited in the present disclosure.

[0095] Figure 3 FIG. 1 is a schematic diagram of a cross-sectional structure of a display substrate, illustrating the structure of three sub-pixels. Figure 3 As shown, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a substrate 101, a light emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the substrate 101, and an encapsulation structure layer 104 disposed on a side of the light emitting structure layer 103 away from the substrate 101. In some possible implementations, the display substrate may include other film layers, such as a touch structure layer, etc., which is not limited in the present disclosure.

[0096] In an exemplary embodiment, the substrate 101 may be a flexible substrate, or may be a rigid substrate. The driving structure layer 102 may include a plurality of circuit units, each of which may include at least a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of light-emitting units, each of which may include at least an anode, an organic light-emitting layer and a cathode, the anode is connected to the pixel driving circuit, the organic light-emitting layer is connected to the anode, the cathode is connected to the organic light-emitting layer, and the organic light-emitting layer emits light of corresponding colors under the drive of the anode and the cathode. The encapsulation structure layer 104 may include a first encapsulation layer, a second encapsulation layer and a third encapsulation layer stacked, the first encapsulation layer and the third encapsulation layer may be made of inorganic materials, the second encapsulation layer may be made of organic materials, and the second encapsulation layer is arranged between the first encapsulation layer and the third encapsulation layer to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that external water vapor cannot enter the light-emitting structure layer 103.

[0097] Figure 4 FIG. 1 is a schematic diagram of an equivalent circuit of a pixel driving circuit. Figure 4 As shown, the pixel driving circuit may include 8 transistors (first transistor T1 to seventh transistor T7) and 1 storage capacitor C, and the pixel driving circuit is respectively connected to 8 signal lines (first scanning signal line S1, second scanning signal line S2, third scanning signal line S3, light emitting signal line EM, first initial signal line INIT1, second initial signal line INIT2, data signal line DATA and first power line VDD).

[0098] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, a third node N3, and a fourth node N4. The first node N1 is respectively connected to the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first end of the storage capacitor C, the second node N2 is respectively connected to the first electrode of the third transistor T3, the second electrode of the fourth transistor T4, and the second electrode of the fifth transistor T5, the third node N3 is respectively connected to the second electrode of the second transistor T2, the second electrode of the third transistor T3, and the first electrode of the sixth transistor T6, and the fourth node N4 is respectively connected to the second electrode of the sixth transistor T6 and the second electrode of the seventh transistor T7.

[0099] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first node N1 , and a second end of the storage capacitor C is connected to the first power line VDD.

[0100] In an exemplary embodiment, the first transistor T1 may be referred to as a first initialization transistor, a gate electrode of the first transistor T1 is connected to the second scan signal line S2 , a first electrode of the first transistor T1 is connected to the first initial signal line INIT1 , and a second electrode of the first transistor T1 is connected to the first node N1 .

[0101] In an exemplary embodiment, the second transistor T2 may be referred to as a compensation transistor, a gate electrode of the second transistor T2 is connected to the first scan signal line S1 , a first electrode of the second transistor T2 is connected to the first node N1 , and a second electrode of the second transistor T2 is connected to the third node N3 .

[0102] In an exemplary embodiment, the third transistor T3 may be referred to as a driving transistor, a gate electrode of the third transistor T3 is connected to the first node N1, a first electrode of the third transistor T3 is connected to the second node N2, and a second electrode of the third transistor T3 is connected to the third node N3.

[0103] In an exemplary embodiment, the fourth transistor T4 may be referred to as a data writing transistor, a gate electrode of the fourth transistor T4 is connected to the first scan signal line S1, a first electrode of the fourth transistor T4 is connected to the data signal line DATA, and a second electrode of the fourth transistor T4 is connected to the second node N2.

[0104] In an exemplary embodiment, the fifth transistor T5 may be referred to as a first light emission control transistor, a gate electrode of the fifth transistor T5 is connected to the light emission signal line EM, a first electrode of the fifth transistor T5 is connected to the first power line VDD, and a second electrode of the fifth transistor T5 is connected to the second node N2.

[0105] In an exemplary embodiment, the sixth transistor T6 may be referred to as a second light emission control transistor, a gate electrode of the sixth transistor T6 is connected to the light emission signal line EM, a first electrode of the sixth transistor T6 is connected to the third node N3, and a second electrode of the sixth transistor T6 is connected to the fourth node N4.

[0106] In an exemplary embodiment, the seventh transistor T7 may be referred to as a second initialization transistor, a gate electrode of the seventh transistor T7 is connected to the third scan signal line S3, a first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and a second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0107] In an exemplary embodiment, a first electrode of the light emitting device EL is connected to the fourth node N4, and a second electrode of the light emitting device EL is connected to the second power supply line VSS. The light emitting device EL may be an OLED including a stacked first electrode (anode), an organic light emitting layer, and a second electrode (cathode), or may be a QLED including a stacked first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode).

[0108] In an exemplary embodiment, the signal of the first power line VDD is a high level signal that is continuously provided, and the signal of the second power line VSS is a low level signal that is continuously provided.

[0109] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a P-type transistor, or may be an N-type transistor. Using the same type of transistors in the pixel driving circuit can simplify the process flow, reduce the process difficulty of the display panel, and improve the yield of the product. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include a P-type transistor and an N-type transistor.

[0110] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be a low-temperature polysilicon transistor, or an oxide transistor, or a low-temperature polysilicon transistor and an oxide transistor. The active layer of the low-temperature polysilicon transistor is low-temperature polysilicon (LTPS), and the active layer of the oxide transistor is oxide semiconductor (Oxide). The low-temperature polysilicon transistor has the advantages of high mobility and fast charging, and the oxide transistor has the advantages of low leakage current. The low-temperature polysilicon transistor and the oxide transistor are integrated on a display substrate to form an LTPO (Low Temperature Polycrystalline + Oxide) display substrate, which can take advantage of the advantages of both, can achieve low-frequency driving, can reduce power consumption, and can improve display quality.

[0111] The exemplary embodiment of the present disclosure provides a display substrate. In an exemplary embodiment, the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a first power line and at least one shading structure; the pixel driving circuit includes at least a first transistor, a second transistor and a storage capacitor, the storage capacitor includes a stacked first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to the first power line; in a direction perpendicular to the display substrate, the display substrate includes at least a first conductive layer disposed on a substrate and a plurality of conductive layers disposed on a side of the first conductive layer away from the substrate, the gate electrode of the first transistor and the gate electrode of the second transistor are disposed in the first conductive layer, at least one shading structure is disposed in any one or more layers of the plurality of conductive layers, and the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor and / or the gate electrode of the second transistor on the substrate.

[0112] In an exemplary embodiment, the first power line is arranged on one side of the second transistor in a first direction, the storage capacitor is arranged on one side of the second direction of the second transistor, and the first direction and the second direction intersect; the gate electrode of the second transistor includes a third sub-gate electrode extending along the first direction and forming a third channel region and a fourth sub-gate electrode extending along the second direction and forming a fourth channel region, and the fourth sub-gate electrode is arranged on one side of the third sub-gate electrode in the first direction; the shading structure is arranged on one side of the third channel region in the first direction, and the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode on the substrate.

[0113] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one light-shielding structure includes a first light-shielding block arranged in the fourth conductive layer, the first light-shielding block is arranged on one side of the first direction of the third channel region, the orthographic projection of the first light-shielding block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a first overlapping area, and the shape of the first overlapping area is a strip shape extending along the second direction.

[0114] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one light-shielding structure includes a second light-shielding block arranged in the third conductive layer, the second light-shielding block is arranged on one side of the first direction of the third channel region, the orthographic projection of the second light-shielding block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a second overlapping area, and the shape of the second overlapping area is a strip shape extending along the second direction.

[0115] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one light-shielding structure includes a third light-shielding block arranged in the second conductive layer, and the third light-shielding block is arranged on one side of the first direction of the third channel region, and the orthographic projection of the third light-shielding block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a third overlapping area, and the shape of the third overlapping area is a strip shape extending along the second direction.

[0116] In an exemplary embodiment, the multiple conductive layers include at least a second conductive layer, a third conductive layer, and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one shading structure includes a fourth shading block arranged in the second conductive layer, the fourth shading block is arranged on a side of the fourth channel region away from the storage capacitor, the orthographic projection of the fourth light shading block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a fourth overlapping area, and the shape of the fourth overlapping area is a strip shape extending along the first direction.

[0117] In an exemplary embodiment, the first power line is arranged on a side of the second transistor in a first direction, the storage capacitor is arranged on a side of the second transistor in a second direction, and the first direction and the second direction intersect; the first transistor is arranged on a side of the second transistor away from the storage capacitor, the first transistor includes a first sub-gate electrode forming a first channel region and a second sub-gate electrode forming a second channel region, and the second sub-gate electrode is arranged on a side of the first sub-gate electrode in the first direction; at least one shading structure includes a fifth shading block, the fifth shading block is arranged on a side of the second transistor away from the storage capacitor, the orthographic projection of the fifth shading block on the substrate at least partially overlaps with the orthographic projection of the first sub-gate electrode on the substrate, and the orthographic projection of the fifth shading block on the substrate at least partially overlaps with the orthographic projection of the first sub-gate electrode on the substrate.

[0118] Figure 5 The present invention is a schematic diagram of a planar structure of a display substrate of an exemplary embodiment of the present invention. In an exemplary embodiment, on a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a substrate and a light-emitting structure layer disposed on a side of the driving structure layer away from the substrate. On a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units, at least one of which may include at least a pixel driving circuit, and the light-emitting structure layer may include a plurality of light-emitting units, at least one of which may include at least a light-emitting device, and the light-emitting device is connected to the pixel driving circuit of the corresponding circuit unit.

[0119] In an exemplary embodiment, the circuit unit mentioned in the present disclosure refers to an area divided according to a pixel driving circuit, and the light-emitting unit mentioned in the present disclosure refers to an area divided according to a light-emitting device. In an exemplary embodiment, the position and shape of the orthographic projection of the light-emitting unit on the substrate may correspond to the position and shape of the orthographic projection of the circuit unit on the substrate, or the position and shape of the orthographic projection of the light-emitting unit on the substrate may not correspond to the position and shape of the orthographic projection of the circuit unit on the substrate.

[0120] In an exemplary embodiment, the plurality of circuit units may form a plurality of unit rows and a plurality of unit columns, the plurality of circuit units in each unit row being sequentially arranged along a first direction X, and the plurality of circuit units in each unit column being sequentially arranged along a second direction Y, to form an array of circuit units arranged in an array, wherein the first direction X intersects with the second direction Y.

[0121] In an exemplary embodiment, the pixel driving circuit of at least one circuit unit may include at least a storage capacitor and a plurality of transistors, and the pixel driving circuit is respectively connected to the first scanning signal line 31, the second scanning signal line 32, the light emitting signal line 33, the first initial signal line 41, the second initial signal line 42, the first power line 61, and the data signal line 63. The first scanning signal line 31 and the second scanning signal line 32 are configured to respectively provide the first scanning signal and the second scanning signal to the pixel driving circuit, the light emitting signal line 33 is configured to provide the light emitting control signal to the pixel driving circuit, the first initial signal line 41 and the second initial signal line 42 are configured to respectively provide the first initial signal and the second initial signal to the pixel driving circuit, the first power line 61 is configured to provide the first power signal to the pixel driving circuit, and the data signal line 63 is configured to provide the data signal to the pixel driving circuit.

[0122] In an exemplary embodiment, the shapes of the first scan signal line 31, the second scan signal line 32, the light emitting signal line 33, the first initial signal line 41 and the second initial signal line 42 can be straight lines or folded lines with the main parts extending along the first direction X, and the shapes of the first power line 61 and the data signal line 63 can be straight lines or folded lines with the main parts extending along the second direction Y.

[0123] In the present disclosure, A extends along direction B means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a strip-shaped body, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extends along direction B" means "the main part of A extends along direction B".

[0124] In an exemplary embodiment, in the second direction Y, the first scan signal line 31, the second scan signal line 32 and the first initial signal line 41 may be located on the side of the storage capacitor in the opposite direction of the second direction Y, and the light emitting signal line 33 and the second initial signal line 42 may be located on the side of the storage capacitor in the second direction Y. Among them, the first scan signal line 31 may be located on the side of the storage capacitor in the opposite direction of the second direction Y, the first initial signal line 41 may be located on the side of the first scan signal line 31 away from the storage capacitor, the second scan signal line 32 may be located on the side of the first initial signal line 41 away from the storage capacitor, the light emitting signal line 33 may be located on the side of the storage capacitor in the second direction Y, and the second initial signal line 42 may be located on the side of the light emitting signal line 33 away from the storage capacitor.

[0125] In an exemplary embodiment, at least one circuit unit may further include a first power connection line 43. The shape of the first power connection line 43 may be a straight line or a broken line with the main part extending along the first direction X. The first power connection line 43 may be located between the first scanning signal line 31 and the light-emitting signal line 33. The first power connection line 43 is connected to the first power line 61 to form a mesh-like interconnected structure for transmitting the first power signal on the display substrate.

[0126] In an exemplary embodiment, at least one circuit unit may further include a second power connection line 44 whose main body extends along the first direction X and a second power line 62 whose main body extends along the second direction Y, and the second power connection line 44 is connected to the second power line 62 to form a mesh-like mesh connection structure for transmitting a second power signal on the display substrate. In an exemplary embodiment, the second power line 62 is configured to provide a second power signal to a cathode in the light-emitting device, realizing a VSS in pixel structure.

[0127] In an exemplary embodiment, at least one circuit unit may further include a first initial connection line 71, the shape of which may be a straight line or a broken line with the main body extending along the second direction Y. The first initial connection line 71 is connected to the first initial signal line 41 to form a mesh-like interconnected structure on the display substrate for transmitting the first initial signal.

[0128] In an exemplary embodiment, at least one circuit unit may further include a second initial connection line 72, the shape of which may be a straight line or a broken line with the main portion extending along the second direction Y. The second initial connection line 72 is connected to the second initial signal line 42 to form a mesh-like interconnected structure on the display substrate for transmitting the second initial signal.

[0129] In an exemplary embodiment, the storage capacitor 80 may include a first electrode plate and a second electrode plate stacked together, and the plurality of transistors may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, and a seventh transistor T7. The second transistor T2 and the fourth transistor T4 may be disposed on a side opposite to the second direction Y of the third transistor T3, the first transistor T1 may be disposed on a side of the second transistor T2 away from the third transistor T3 (storage capacitor), the fifth transistor T5 and the sixth transistor T6 may be disposed on a side of the third transistor T3 in the second direction Y, and the seventh transistor T7 may be disposed on a side of the sixth transistor T6 away from the third transistor T3 (storage capacitor).

[0130] In an exemplary embodiment, the gate electrode of the first transistor T1 is connected to the second scan signal line 32, the first electrode of the first transistor T1 is connected to the first initial signal line 41, and the second electrode of the first transistor T1 is respectively connected to the first electrode of the second transistor T2 and the first electrode plate of the storage capacitor 80. The gate electrode of the second transistor T2 is connected to the first scan signal line 31, and the second electrode of the second transistor T2 is connected to the second electrode of the third transistor T3. The gate electrode of the fourth transistor T4 is connected to the first scan signal line 31, the first electrode of the fourth transistor T4 is connected to the data signal line 63, and the second electrode of the fourth transistor T4 is connected to the first electrode of the third transistor T3. The gate electrode of the fifth transistor T5 is connected to the light emitting signal line 33, the first electrode of the fifth transistor T5 is respectively connected to the second electrode plate of the storage capacitor 80 and the first power line 61, and the second electrode of the fifth transistor T5 is connected to the first electrode of the third transistor T3. The gate electrode of the sixth transistor T6 is connected to the light emitting signal line 33, the first electrode of the sixth transistor T6 is connected to the second electrode of the third transistor T3, and the second electrode of the sixth transistor T6 is connected to the second electrode of the seventh transistor T7. A gate electrode of the seventh transistor T7 is connected to the second scanning signal line 62 of the next unit row, and a first electrode of the seventh transistor T7 is connected to the second initial signal line 42 .

[0131] In an exemplary embodiment, in the first direction X, the second transistor T2 may be disposed on a side opposite to the first direction X of the first power line 61, that is, the first power line 61 may be disposed on a side of the second transistor T2 in the first direction X. In the second direction Y, the second transistor T2 may be disposed on a side opposite to the second direction Y of the storage capacitor 80, that is, the storage capacitor 80 may be disposed on a side of the second transistor T2 in the second direction Y. The second transistor T2 is a dual-gate structure, and the gate electrode of the second transistor T2 may include a third sub-gate electrode 22-1 forming a third channel region and a fourth sub-gate electrode 22-2 forming a fourth channel region, the third sub-gate electrode 22-1 may be in a strip shape extending along the first direction X, the fourth sub-gate electrode 22-2 may be in a strip shape extending along the second direction Y, and the fourth sub-gate electrode 22-2 is disposed on a side of the third sub-gate electrode 22-1 in the first direction X (that is, a side close to the first power line 61).

[0132] In an exemplary embodiment, at least one circuit unit may further include a first light shielding block 110 as a light shielding structure, and the first light shielding block 110 may be disposed on one side of the third channel region of the second transistor T2 in the first direction X, and the orthographic projection of the first light shielding block 110 on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode 22-2 on the substrate, and a first gate overlap region is formed at an edge position of the fourth sub-gate electrode 22-2 close to the first power line 61, and the shape of the first gate overlap region may be a strip shape extending along the second direction Y. In an exemplary embodiment, the first light shielding block 110 is configured to block light from irradiating to the channel region of the second transistor T2.

[0133] In an exemplary embodiment, an orthographic projection of the first light shielding block 110 on the substrate may at least partially overlap an orthographic projection of the fourth channel region on the substrate.

[0134] In an exemplary embodiment, in a direction perpendicular to the display substrate, the display substrate may include at least a first conductive layer disposed on a substrate and a plurality of conductive layers disposed on a side of the first conductive layer away from the substrate, the gate electrode of the first transistor T1 and the gate electrode of the second transistor T2 may be disposed in the first conductive layer. The plurality of conductive layers may include at least a second conductive layer, a third conductive layer, and a fourth conductive layer sequentially disposed in a direction away from the substrate, and the first light shielding block 110 may be disposed in the fourth conductive layer.

[0135] In an exemplary embodiment, the first light shielding block 110 and the first power line 61 may be disposed in the same layer and be an integrated structure connected to each other.

[0136] In an exemplary embodiment, the display substrate may further include a blocking layer disposed between the substrate and the first conductive layer, the blocking layer may include at least a first blocking block and a second blocking block, the orthographic projection of the first blocking block on the substrate includes the orthographic projection of the gate electrode of the second transistor T2 on the substrate, and the orthographic projection of the second blocking block on the substrate includes the orthographic projection of the gate electrode of the first transistor T1 on the substrate.

[0137] In an exemplary embodiment, the display substrate may further include a semiconductor layer disposed between the blocking layer and the first conductive layer, and the semiconductor layer may include at least an active layer of the plurality of transistors.

[0138] In an exemplary embodiment, the first conductive layer may include at least a first plate of a storage capacitor, the second conductive layer may include at least a second plate of a storage capacitor, the third conductive layer may include at least a first scan signal line, a second scan signal line, a first initial signal line, a second initial signal line and a plurality of connecting electrodes, and the fourth conductive layer may include at least a first power line and a data signal line.

[0139] The following is an exemplary explanation through the preparation process of the display substrate. The "patterning process" mentioned in the present disclosure includes deposition of film layers, coating of photoresist on the film layers, mask exposure, development, etching, stripping of photoresist and other processes for metal materials, inorganic materials or transparent conductive materials, and includes coating of organic materials, mask exposure and development and other processes for organic materials. Deposition can be any one or more of sputtering, evaporation, chemical vapor deposition, coating can be any one or more of spraying, spin coating and inkjet printing, and etching can be any one or more of dry etching and wet etching, which are not limited in the present disclosure. "Thin film" refers to a layer of thin film made of a certain material on a substrate by deposition, coating or other processes. If the "thin film" does not require a patterning process during the entire production process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process during the entire production process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process contains at least one "pattern". The "A and B are arranged in the same layer" in the present disclosure means that A and B are formed simultaneously through the same patterning process, and the "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In the exemplary embodiments of the present disclosure, "the orthographic projection of B is within the range of the orthographic projection of A" or "the orthographic projection of A includes the orthographic projection of B" means that the boundary of the orthographic projection of B falls within the boundary of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B.

[0140] In an exemplary embodiment, taking three circuit units (the Mth unit row, the Nth unit column to the N+2th unit column) as an example, the preparation process of the display substrate in this embodiment may include the following operations.

[0141] (11) Forming a shielding layer pattern. In an exemplary embodiment, forming a shielding layer pattern may include: depositing a shielding film on a substrate, patterning the shielding film through a patterning process, and forming a shielding layer pattern on the substrate, such as Figure 6 In an exemplary embodiment, the shielding layer may be referred to as a bottom metal (LS) layer.

[0142] In an exemplary embodiment, the shielding layer pattern of each circuit unit may include at least a first shielding connection bar 90-1, a second shielding connection bar 90-2, a third shielding connection bar 90-3, a fourth shielding connection bar 90-4, a first shielding electrode 91, a second shielding electrode 92, a third shielding electrode 93 and a fourth shielding electrode 94.

[0143] In an exemplary embodiment, the shape of the first shielding electrode 91 may be rectangular, the corners of the rectangle may be chamfered or grooved, and the first shielding electrode 91 may be disposed in a middle region of the circuit unit in the first direction X and the second direction Y. In an exemplary embodiment, the first shielding electrode 91 is configured to shield the channel region of the third transistor T3.

[0144] In an exemplary embodiment, the shape of the first shielding connection strip 90-1 can be a straight line or a broken line with the main part extending along the first direction X. The first shielding connection strip 90-1 can be arranged on one side of the first shielding electrode 91 in the first direction X or on the side of the first shielding electrode 91 in the opposite direction of the first direction X. The first end of the first shielding connection strip 90-1 is connected to the first shielding electrode 91 of the current circuit unit, and the second end of the first shielding connection strip 90-1 is connected to the first shielding electrode 91 of the adjacent circuit unit in the first direction X.

[0145] In an exemplary embodiment, in at least one cell row, the first shielding electrode 91 and the first shielding connection bar 90 - 1 may be an integrated structure connected to each other.

[0146] In an exemplary embodiment, the shape of the second shielding connection strip 90-2 can be a straight line or a broken line with the main part extending along the second direction Y, and can be arranged on one side of the first shielding electrode 91 in the second direction Y. The first end of the second shielding connection strip 90-2 is connected to the first shielding electrode 91 of the circuit unit, and the second end of the second shielding connection strip 90-2 extends along the second direction Y and is connected to the fourth shielding electrode 94 of the adjacent circuit unit in the second direction Y.

[0147] In an exemplary embodiment, the shape of the third shielding connection strip 90-3 can be a straight line or a broken line with the main part extending along the second direction Y. The third shielding connection strip 90-3 can be arranged on the side of the first shielding electrode 91 in the opposite direction of the second direction Y. The first end of the third shielding connection strip 90-3 is connected to the first shielding electrode 91, and the second end of the third shielding connection strip 90-3 extends in the opposite direction of the second direction Y and is connected to the second shielding electrode 92.

[0148] In an exemplary embodiment, the shape of the fourth shielding connection strip 90-4 can be a straight line or a broken line with the main part extending along the second direction Y. The fourth shielding connection strip 90-4 can be arranged on the side of the second shielding electrode 92 away from the first shielding electrode 91. The first end of the fourth shielding connection strip 90-4 is connected to the second shielding electrode 92, and the second end of the fourth shielding connection strip 90-4 extends in the opposite direction of the second direction Y and is connected to the third shielding electrode 93.

[0149] In an exemplary embodiment, the second shielding electrode 92 may be in an "L" shape and may be disposed on one side of the first shielding electrode 91 in the opposite direction of the second direction Y. The first end of the second shielding electrode 92 is connected to the third shielding connection bar 90-3, and the second end of the second shielding electrode 92 is connected to the fourth shielding connection bar 90-4. In an exemplary embodiment, the second shielding electrode 92 is configured to shield the channel regions of the second transistor T2 and the fourth transistor T4.

[0150] In an exemplary embodiment, the third shielding electrode 93 may be in the shape of a strip extending along the first direction X, and may be disposed on a side of the fourth shielding connection bar 90-4 away from the first shielding electrode 91, a first end of the third shielding electrode 93 is connected to the fourth shielding connection bar 90-4, and a second end of the third shielding electrode 93 is connected to the fourth shielding electrode 94. In an exemplary embodiment, the third shielding electrode 93 is configured to shield the channel region of the first transistor T1.

[0151] In an exemplary embodiment, the fourth shielding electrode 94 may be in the shape of a strip extending along the second direction Y, and may be disposed on a side of the third shielding electrode 93 away from the first shielding electrode 91, a first end of the fourth shielding electrode 94 is connected to the third shielding electrode 93 of the present circuit unit, and a second end of the fourth shielding electrode 94 is connected to the second shielding connection strip 90-2 of the adjacent circuit unit in the opposite direction of the second direction Y. In an exemplary embodiment, the third shielding electrode 93 is configured to shield the channel region of the seventh transistor T7.

[0152] In an exemplary embodiment, in at least one unit column, the fourth shielding electrode 94, the third shielding electrode 93, the fourth shielding connection strip 90-4, the second shielding electrode 92, the third shielding connection strip 90-3, the first shielding electrode 91 and the second shielding connection strip 90-2 can be connected in sequence and form an interconnected integrated structure.

[0153] In an exemplary embodiment, since the fifth transistor T5 and the sixth transistor T6 are light emitting control transistors and have little impact on the entire circuit, no shielding block may be provided at the locations of the fifth transistor T5 and the sixth transistor T6.

[0154] In an exemplary embodiment, the shielding layer may extend to the frame area or the binding area and be connected to the power lead that transmits the first power signal. The shielding layers in the plurality of unit rows and the plurality of unit columns are interconnected as an integrated structure, which can ensure that the shielding layers in the display substrate have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0155] In an exemplary embodiment, the position and shape of the shielding layer in a plurality of cell rows may be substantially the same, and the position and shape of the shielding layer in a plurality of cell columns may be substantially the same.

[0156] (12) Forming a semiconductor layer pattern. In an exemplary embodiment, forming a semiconductor layer pattern may include: depositing a first insulating film and a semiconductor film in sequence on a substrate having the aforementioned pattern, patterning the semiconductor film through a patterning process to form a first insulating layer covering the shielding layer, and a semiconductor layer pattern disposed on the first insulating layer, such as Fig. 7A and Figure 7B As shown, Figure 7B for Fig. 7A Schematic diagram of the semiconductor layer in the figure.

[0157] In an exemplary embodiment, the semiconductor layer pattern of each circuit unit may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7 , and the first active layer 11 to the seventh active layer 17 are an integral structure connected to each other.

[0158] In an exemplary embodiment, in the second direction Y, the first active layer 11, the second active layer 12, and the fourth active layer 14 may be located on a side of the third active layer 13 in the opposite direction of the second direction Y, and the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be located on a side of the third active layer 13 in the second direction Y.

[0159] In an exemplary embodiment, the third active layer 13 may be shaped like an "Ω", the first active layer 11 may be shaped like an "n", the fourth active layer 14 may be shaped like an "I", and the second active layer 12, the fifth active layer 15, the sixth active layer 16, and the seventh active layer 17 may be shaped like an "L".

[0160] In an exemplary embodiment, the first to seventh active layers 11 to 17 may each include a first region, a second region, and a channel region between the first and second regions. In an exemplary embodiment, the second region 11-2 of the first active layer and the first region 12-1 of the second active layer may be connected to each other, and the second region 11-2 of the first active layer may serve as the first region 12-1 of the second active layer. The first region 13-1 of the third active layer, the second region 14-2 of the fourth active layer, and the second region 15-2 of the fifth active layer may be connected to each other, and the first region 13-1 of the third active layer may serve as the second region 14-2 of the fourth active layer and the second region 15-2 of the fifth active layer at the same time. The second region 12-1 of the second active layer, the second region 13-2 of the third active layer, and the first region 16-1 of the sixth active layer may be connected to each other, and the second region 12-1 of the second active layer may serve as the second region 13-2 of the third active layer and the first region 16-1 of the sixth active layer at the same time. The second region 16-2 of the sixth active layer and the second region 17-2 of the seventh active layer may be connected to each other, and the second region 16-2 of the sixth active layer may serve as the second region 17-2 of the seventh active layer. The first region 11-1 of the first active layer, the first region 14-1 of the fourth active layer, the first region 15-1 of the fifth active layer, and the first region 17-1 of the seventh active layer may be separately provided.

[0161] In an exemplary embodiment, the orthographic projection of the first active layer 11 on the substrate at least partially overlaps with the orthographic projection of the third blocking electrode 93 on the substrate, and the third blocking electrode 93 can serve as a blocking layer of the first transistor T1 to block the channel region of the first transistor T1 and ensure the electrical performance of the first transistor T1.

[0162] In an exemplary embodiment, the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the second shielding electrode 92 on the substrate, and the second shielding electrode 92 can serve as a shielding layer of the second transistor T2 to shield the channel region of the second transistor T2 and ensure the electrical performance of the second transistor T2.

[0163] In an exemplary embodiment, the orthographic projection of the third active layer 13 on the substrate at least partially overlaps with the orthographic projection of the first shielding electrode 91 on the substrate, and the first shielding electrode 91 can serve as a shielding layer of the third transistor T3 to shield the channel region of the third transistor T3 and ensure the electrical performance of the third transistor T3.

[0164] In an exemplary embodiment, an orthographic projection of the channel region of the third active layer 13 on the substrate is located within a range of an orthographic projection of the first shielding electrode 91 on the substrate.

[0165] In an exemplary embodiment, the orthographic projection of the seventh active layer 17 on the substrate at least partially overlaps with the orthographic projection of the fourth blocking electrode 94 on the substrate, and the fourth blocking electrode 94 can serve as a blocking layer of the seventh transistor T7 to block the channel region of the seventh transistor T7 and ensure the electrical performance of the seventh transistor T7.

[0166] In example embodiments, positions and shapes of semiconductor layers in a plurality of cell rows may be substantially the same, and positions and shapes of semiconductor layers in a plurality of cell columns may be substantially the same.

[0167] In an exemplary embodiment, the semiconductor layer may be made of polycrystalline silicon (p-Si), that is, the third transistor to the seventh transistor are LTPS transistors. In an exemplary embodiment, patterning the semiconductor film by a patterning process may include: first forming an amorphous silicon (a-si) film on the first insulating film, dehydrogenating the amorphous silicon film, and crystallizing the amorphous silicon film after the dehydrogenation to form a polycrystalline silicon film. Subsequently, the polycrystalline silicon film is patterned to form a semiconductor layer pattern.

[0168] (13) Forming a first conductive layer pattern. In an exemplary embodiment, forming the first conductive layer pattern may include: depositing a second insulating film and a first conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the first conductive film through a patterning process to form a second insulating layer covering the semiconductor layer pattern, and a first conductive layer pattern disposed on the second insulating layer, such as Fig. 8A and Figure 8B As shown, Figure 8B for Fig. 8A In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0169] In an exemplary embodiment, the first conductive layer pattern of each circuit unit includes at least a first gate electrode 21 , a second gate electrode 22 , a fourth gate electrode 24 , a seventh gate electrode 27 , a light emitting signal line 33 and a first plate 81 of a storage capacitor.

[0170] In an exemplary embodiment, the shape of the first electrode plate 81 may be rectangular, and the corners of the rectangle may be provided with chamfers or grooves, and the orthographic projection of the first electrode plate 81 on the substrate at least partially overlaps with the orthographic projection of the third active layer of the third transistor T3 on the substrate. In an exemplary embodiment, the first electrode plate 81 may simultaneously serve as a plate of the storage capacitor and a gate electrode of the third transistor T3.

[0171] In an exemplary embodiment, the orthographic projection of the first electrode plate 81 on the substrate is located within the range of the orthographic projection of the first shielding electrode 91 on the substrate.

[0172] In an exemplary embodiment, the shape of the first gate electrode 21 may be a strip shape with a main portion extending along the first direction X. The first gate electrode 21 may be located on a side of the first electrode plate 81 in the opposite direction of the second direction Y. The region where the first gate electrode 21 overlaps with the first active layer may serve as a gate electrode of the first transistor T1 of the double-gate structure. In an exemplary embodiment, the first gate electrode 21 is configured to be connected to a second scan signal line formed subsequently.

[0173] In an exemplary embodiment, in at least one circuit unit, the first gate electrode 21 may include a first sub-gate electrode 21-1 and a second sub-gate electrode 21-2, the first sub-gate electrode 21-1 and the second sub-gate electrode 21-2 are both strip-shaped extending along the first direction X, and the second sub-gate electrode 21-2 may be disposed on one side of the first sub-gate electrode 21-1 in the first direction X. In an exemplary embodiment, a region where the first sub-gate electrode 21-1 overlaps with the first active layer forms a first channel region T1-G1, and a region where the second sub-gate electrode 21-2 overlaps with the first active layer forms a second channel region T1-G2, forming a first transistor T1 of a dual-gate structure.

[0174] In an exemplary embodiment, in at least one circuit unit, the first sub-gate electrode 21 - 1 and the second sub-gate electrode 21 - 2 may be an integral structure connected to each other.

[0175] In an exemplary embodiment, in at least one unit row, the first gate electrodes 21 of a plurality of circuit units may be interconnected in an integrated structure, forming a gate line whose main portion extends along the first direction X.

[0176] In an exemplary embodiment, an orthographic projection of the first gate electrode 21 on the substrate at least partially overlaps an orthographic projection of the third shielding electrode 93 on the substrate.

[0177] In an exemplary embodiment, the second gate electrode 22 may be in an "L" shape and may be located between the first electrode plate 81 and the first gate electrode 21. The orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate, and the region where the second gate electrode 22 overlaps with the second active layer may serve as the gate electrode of the second transistor T2 of the dual-gate structure. In an exemplary embodiment, the second gate electrode 22 is configured to be connected to a first scanning signal line formed subsequently.

[0178] In an exemplary embodiment, in at least one circuit unit, the second gate electrode 22 may include a third sub-gate electrode 22-1 and a fourth sub-gate electrode 22-2, the third sub-gate electrode 22-1 is shaped like a strip extending along the first direction X, the fourth sub-gate electrode 22-2 is shaped like a strip extending along the second direction Y, the fourth sub-gate electrode 22-2 may be arranged on one side of the third sub-gate electrode 22-1 in the first direction X, the region where the third sub-gate electrode 22-1 overlaps with the second active layer forms a third channel region T2-G1, and the region where the fourth sub-gate electrode 22-2 overlaps with the second active layer forms a fourth channel region T2-G2, forming a second transistor T2 of a dual-gate structure.

[0179] In an exemplary embodiment, in at least one circuit unit, the third sub-gate electrode 22 - 1 and the fourth sub-gate electrode 22 - 2 may be an integral structure connected to each other.

[0180] In an exemplary embodiment, an orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps an orthographic projection of the second shielding electrode 92 on the substrate.

[0181] In an exemplary embodiment, the fourth gate electrode 24 may be in the shape of a strip extending along the first direction X, and may be located between the first electrode plate 81 and the first gate electrode 21. The orthographic projection of the fourth gate electrode 24 on the substrate at least partially overlaps with the orthographic projection of the fourth active layer on the substrate, and the region where the fourth gate electrode 24 overlaps with the fourth active layer may serve as the gate electrode of the fourth transistor T4. In an exemplary embodiment, the fourth gate electrode 24 is configured to be connected to a first scan signal line formed subsequently.

[0182] In an exemplary embodiment, an orthographic projection of the fourth gate electrode 24 on the substrate at least partially overlaps an orthographic projection of the second shielding electrode 92 on the substrate.

[0183] In an exemplary embodiment, the fourth gate electrode 24 in the present circuit unit and the second gate electrode 22 in the adjacent circuit unit in the first direction X may be an integrated structure connected to each other. For example, in a cell row, the fourth gate electrode 24 in the Nth cell column and the second gate electrode 22 in the N+1th cell column may be an integrated structure connected to each other.

[0184] In an exemplary embodiment, the seventh gate electrode 27 may be in the shape of a strip extending along the second direction Y and may be located on a side of the first gate electrode 21 away from the first electrode plate 81 . The area where the seventh gate electrode 27 overlaps with the seventh active layer may serve as the gate electrode of the seventh transistor T7 .

[0185] In an exemplary embodiment, an orthographic projection of the seventh gate electrode 27 on the substrate at least partially overlaps an orthographic projection of the fourth shielding electrode 94 on the substrate.

[0186] In an exemplary embodiment, the seventh gate electrode 27 of the circuit unit in the present unit row can be connected to the first gate electrode 21 of the circuit unit in the next unit row, the first transistor T1 of the present unit row and the seventh transistor T7 in the previous unit row are controlled by the same scan signal line, and the seventh transistor T7 of the present unit row and the first transistor T1 in the next unit row are controlled by the same scan signal line.

[0187] In an exemplary embodiment, the first gate electrode 21 of the circuit unit in the current unit row and the seventh gate electrode 27 of the circuit unit in the previous unit row can be an interconnected integrated structure, and the seventh gate electrode 27 of the circuit unit in the current unit row and the first gate electrode 21 of the circuit unit in the next unit row can be an interconnected integrated structure.

[0188] In an exemplary embodiment, the shape of the light-emitting signal line 33 can be a straight line or a broken line with the main part extending along the first direction X. The light-emitting signal line 33 can be located on one side of the second direction Y of the first electrode 81. The area where the light-emitting signal line 33 overlaps with the fifth active layer can be used as the gate electrode of the fifth transistor T5, and the area where the light-emitting signal line 33 overlaps with the sixth active layer can be used as the gate electrode of the sixth transistor T6.

[0189] In example embodiments, positions and shapes of the first conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the first conductive layers in a plurality of cell columns may be substantially the same.

[0190] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer can be used as a shield to perform conductorization on the semiconductor layer. The semiconductor layer in the area shielded by the first conductive layer forms the channel region of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the area not shielded by the first conductive layer is conductorized, that is, the first area and the second area of ​​the first transistor T1 to the seventh transistor T7 are both conductorized.

[0191] (14) Forming a second conductive layer pattern. In an exemplary embodiment, forming the second conductive layer pattern may include: depositing a third insulating film and a second conductive film in sequence on the substrate on which the aforementioned pattern is formed, patterning the second conductive film using a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, such as Fig. 9A and Fig. 9B As shown, Fig. 9B for Fig. 9A In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0192] In an exemplary embodiment, the second conductive layer pattern of each circuit unit includes at least a first shielding electrode 35 , a second shielding electrode 36 , and a second plate 82 of the storage capacitor.

[0193] In an exemplary embodiment, the outline of the second plate 82 of the storage capacitor can be rectangular, and the corners of the rectangle can be provided with chamfers or grooves. The orthographic projection of the second plate 82 on the substrate at least partially overlaps with the orthographic projection of the first plate 81 on the substrate. The second plate 82 can serve as another plate of the storage capacitor, and the first plate 81 and the second plate 82 constitute the storage capacitor of the pixel driving circuit.

[0194] In an exemplary embodiment, the second electrode plate 82 may be provided with a board-level connecting bar 83. The board-level connecting bar 83 may be in the shape of a straight line or a broken line extending along the first direction X. The board-level connecting bar 83 may be provided on one side of the second electrode plate 82 in the first direction X or on the side opposite to the first direction X. The first end of the board-level connecting bar 83 is connected to the second electrode plate 82 in the circuit unit, and the second end of the board-level connecting bar 83 is connected to the second electrode plate 82 in the adjacent circuit unit in the first direction X. Since the second electrode plate 82 in each circuit unit is connected to the first power line formed subsequently, by connecting the second electrode plates 82 of adjacent circuit units to each other, the second electrode plate 82 and the board-level connecting bar 83 may be reused as a power signal line, which may ensure that a plurality of second electrode plates in a unit row have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0195] In an exemplary embodiment, the second electrode plates 82 and the board-level connecting bars 83 in a plurality of circuit cells in one cell row may be an integral structure connected to each other.

[0196] In an exemplary embodiment, an opening 84 is provided on the second electrode plate 82. The opening 84 may be rectangular and may be located in the middle region of the second electrode plate 82, so that the second electrode plate 82 forms a ring structure. The opening 84 exposes the third insulating layer covering the first electrode plate 81, and the orthographic projection of the first electrode plate 81 on the substrate includes the orthographic projection of the opening 84 on the substrate. In an exemplary embodiment, the opening 84 is configured to accommodate a ninth via hole formed subsequently, and the ninth via hole is located in the opening 84 and exposes the first electrode plate 81, so that the first connecting electrode formed subsequently is connected to the first electrode plate 81.

[0197] In an exemplary embodiment, the first shielding electrode 35 may be in an inverted "U" shape, and may be located on a side of the second electrode plate 82 close to the second transistor T2. The first end of the first shielding electrode 35 is connected to the second electrode plate 82, and the positive projection of the second end of the first shielding electrode 35 on the substrate overlaps at least partially with the positive projection of the second active layer (the node between the two gate electrodes) between the two gate electrodes of the second transistor T2 on the substrate. In an exemplary embodiment, the first shielding electrode 35 is configured to shield the influence of the data voltage jump on the second transistor T2, so as to prevent the data voltage jump from affecting the normal operation of the pixel driving circuit, and improve the display effect.

[0198] In an exemplary embodiment, the first shielding electrode 35 may be provided in each circuit unit. The first shielding electrode 35 in the shape of an inverted "U" may include a first extension section 35-1, a second extension section 35-2, and a third extension section 35-3 connected in sequence. The shape of the first extension section 35-1 may be a strip shape in which the main part extends along the second direction Y, the first end of the first extension section 35-1 is connected to the second electrode plate 82, and the second end of the first extension section 35-1 is connected to the first end of the second extension section 35-2 after extending in the opposite direction of the second direction Y in a direction away from the second electrode plate 82. The shape of the second extension section 35-2 may be a strip shape in which the main part extends along the first direction X, the second end of the second extension section 35-2 is connected to the first end of the third extension section 35-3 after extending in the opposite direction of the first direction X in a direction close to the second transistor T2, and the positive projection of the second extension section 35-2 on the substrate at least partially overlaps with the positive projection of the first active layer on the substrate. The shape of the third extension segment 35-3 can be a strip shape in which the main part extends along the second direction Y, and the second end of the third extension segment 35-3 extends along the second direction Y toward the direction close to the second electrode 82. The positive projection of the third extension segment 35-3 on the substrate at least partially overlaps with the positive projection of the semiconductor layer between the two gate electrodes of the second transistor T2 on the substrate, and the third extension segment 35-3 is configured to shield the influence of the data voltage jump on the second transistor T2.

[0199] In an exemplary embodiment, in at least one circuit unit, the first shielding electrode 35 and the second electrode plate 82 may be an integral structure connected to each other. Since the second electrode plate 82 is connected to a first power line formed later, the first shielding electrode 35 has the potential of the first power line.

[0200] In an exemplary embodiment, the second shielding electrode 36 may be in an "L" shape and may be located on the side of the first gate electrode 21 away from the second electrode plate 82. The positive projection of the second shielding electrode 36 on the substrate at least partially overlaps with the positive projection of the first active layer (the node between the two gate electrodes) between the two gate electrodes of the first transistor T1 on the substrate. In an exemplary embodiment, the second shielding electrode 36 is configured to shield the influence of the data voltage jump on the first transistor T1, prevent the data voltage jump from affecting the normal operation of the pixel driving circuit, and improve the display effect.

[0201] In an exemplary embodiment, positions and shapes of the second conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the second conductive layers in a plurality of cell columns may be substantially the same.

[0202] (15) Forming a fourth insulating layer pattern. In an exemplary embodiment, forming the fourth insulating layer pattern may include: depositing a fourth insulating film on the substrate on which the aforementioned pattern is formed, patterning the fourth insulating film using a patterning process to form a fourth insulating layer covering the second conductive layer, wherein a plurality of via holes are disposed on the fourth insulating layer, such as Fig.10 shown.

[0203] In an exemplary embodiment, the plurality of vias of each circuit unit include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, and an eleventh via V11.

[0204] In an exemplary embodiment, the orthographic projection of the first via hole V1 on the substrate is located within the range of the orthographic projection of the first region of the first active layer on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the first via hole V1 are etched away to expose the surface of the first region of the first active layer, and the first via hole V1 is configured to connect a first initial signal line formed subsequently through the via hole to the first region of the first active layer.

[0205] In an exemplary embodiment, the orthographic projection of the second via hole V2 on the substrate is located within the range of the orthographic projection of the second area of ​​the first active layer (also the first area of ​​the second active layer) on the substrate, the fourth insulating layer, the third insulating layer, and the second insulating layer in the second via hole V2 are etched away to expose the surface of the second area of ​​the first active layer (also the first area of ​​the second active layer), and the second via hole V2 is configured to connect a subsequently formed first connecting electrode to the second area of ​​the first active layer (also the first area of ​​the second active layer) through the via hole.

[0206] In an exemplary embodiment, the orthographic projection of the third via hole V3 on the substrate is located within the range of the orthographic projection of the first area of ​​the fourth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the third via hole V3 are etched away to expose the surface of the first area of ​​the fourth active layer, and the third via hole V3 is configured to connect a subsequently formed second connecting electrode to the first area of ​​the fourth active layer through the via hole.

[0207] In an exemplary embodiment, the orthographic projection of the fourth via hole V4 on the substrate is located within the range of the orthographic projection of the first area of ​​the fifth active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via hole V4 are etched away to expose the surface of the first area of ​​the fifth active layer, and the fourth via hole V4 is configured to connect a subsequently formed third connecting electrode to the first area of ​​the fifth active layer through the via hole.

[0208] In an exemplary embodiment, the orthographic projection of the fifth via hole V5 on the substrate is located within the range of the orthographic projection of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the fifth via hole V5 are etched away to expose the surface of the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer), and the fifth via hole V5 is configured to connect a subsequently formed fourth connecting electrode to the second area of ​​the sixth active layer (also the second area of ​​the seventh active layer) through the via hole.

[0209] In an exemplary embodiment, the orthographic projection of the sixth via hole V6 on the substrate is located within the range of the orthographic projection of the first region of the seventh active layer on the substrate, the fourth insulating layer, the third insulating layer and the second insulating layer in the sixth via hole V6 are etched away to expose the surface of the first region of the seventh active layer, and the sixth via hole V6 is configured to connect a subsequently formed second initial signal line to the first region of the seventh active layer through the via hole.

[0210] In an exemplary embodiment, the orthographic projection of the seventh via hole V7 on the substrate is located within the range of the orthographic projection of the opening 84 on the substrate, the fourth insulating layer and the third insulating layer in the seventh via hole V7 are etched away to expose the surface of the first electrode plate 81, and the seventh via hole V7 is configured to connect a subsequently formed first connecting electrode to the first electrode plate 81 through the via hole.

[0211] In an exemplary embodiment, the orthographic projection of the eighth via hole V8 on the substrate is within the range of the orthographic projection of the second electrode plate 82 on the substrate, the fourth insulating layer in the eighth via hole V8 is etched away, exposing the surface of the second electrode plate 82, and the eighth via hole V8 is configured to connect the first power connection line formed subsequently to the second electrode plate 82 through the via hole. In an exemplary embodiment, there may be a plurality of eighth via holes V8 to increase connection reliability.

[0212] In an exemplary embodiment, the orthographic projection of the ninth via hole V9 on the substrate is located within the range of the orthographic projection of the second gate electrode 22 on the substrate, the fourth insulating layer and the third insulating layer in the ninth via hole V9 are etched away to expose the surface of the second gate electrode 22, and the ninth via hole V9 is configured to connect the subsequently formed first scanning signal line to the second gate electrode 22 through the via hole.

[0213] In an exemplary embodiment, the orthographic projection of the tenth via hole V10 on the substrate is located within the range of the orthographic projection of the first gate electrode 21 on the substrate, the fourth insulating layer and the third insulating layer in the tenth via hole V10 are etched away to expose the surface of the first gate electrode 21, and the tenth via hole V10 is configured to connect a subsequently formed second scanning signal line to the first gate electrode 21 through the via hole.

[0214] In an exemplary embodiment, the orthographic projection of the eleventh via hole V11 on the substrate is located within the range of the orthographic projection of the second shielding electrode 36 on the substrate, the fourth insulating layer in the eleventh via hole V11 is etched away to expose the surface of the second shielding electrode 36, and the eleventh via hole V11 is configured to connect a subsequently formed second initial signal line to the second shielding electrode 36 through the via hole.

[0215] In an exemplary embodiment, positions and shapes of the plurality of via holes in the plurality of cell rows may be substantially the same, and positions and shapes of the plurality of via holes in the plurality of cell columns may be substantially the same.

[0216] (16) Forming a third conductive layer pattern. In an exemplary embodiment, forming the third conductive layer may include: depositing a third conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a third conductive layer disposed on the fourth insulating layer, such as Fig.11A and Fig. 11B As shown, Fig. 11B for Fig.11A In an exemplary embodiment, the third conductive layer may be referred to as a first source-drain metal (SD1) layer.

[0217] In an exemplary embodiment, the third conductive layer of each circuit unit includes at least: a first scan signal line 31, a second scan signal line 32, a first initial signal line 41, a second initial signal line 42, a first power connection line 43, a second power connection line 44, a first connection electrode 51, a second connection electrode 52, a third connection electrode 53 and a fourth connection electrode 54.

[0218] In an exemplary embodiment, the shape of the first scan signal line 31 may be a straight line or a folded line with a main portion extending along the first direction X. The first scan signal line 31 may be located on one side of the second electrode 82 in the opposite direction of the second direction Y. The first scan signal line 31 is connected to the second gate electrode 22 through the ninth via hole V9 in each circuit unit. Since the second gate electrode 22 is connected to the fourth gate electrode 24, the first scan signal line 31 controls the conduction and disconnection of the second transistor T2 and the fourth transistor T4.

[0219] In an exemplary embodiment, the shape of the second scan signal line 32 may be a straight line or a folded line with a main portion extending along the first direction X. The second scan signal line 32 may be located on a side of the first scan signal line 31 away from the second electrode plate 82. The second scan signal line 32 is connected to the first gate electrode 21 through the tenth via hole V10 in each circuit unit. Since the first gate electrode 21 is connected to the seventh gate electrode 27, the second scan signal line 32 controls the conduction and disconnection of the first transistor T1 and the seventh transistor T7.

[0220] In an exemplary embodiment, the second scan signal line in the current unit row is equivalent to the third scan signal line in the previous unit row. The present disclosure effectively reduces the number of scan signal lines by setting the second scan signal line in the current unit row to simultaneously control the first transistor T1 in the current unit row and the seventh transistor T7 in the previous unit row, which is beneficial to reducing the processing of the circuit unit and improving the display resolution.

[0221] In an exemplary embodiment, the shape of the first initial signal line 41 can be a straight line or a broken line with the main part extending along the first direction X. The first initial signal line 41 can be located between the first scanning signal line 31 and the second scanning signal line 32. The first initial signal line 41 is connected to the first region of the first active layer through the first via V1 in each circuit unit, so that the first initial signal line 41 writes the first initial signal into the first electrode of the first transistor T1.

[0222] In an exemplary embodiment, in at least one circuit unit, a first initial signal line 41 may be connected to a first initial connection block 41-1, and the first initial connection block 41-1 is configured to be connected to a first initial connection line formed subsequently, so that the first initial signal line extending along the first direction and the first initial connection line extending along the second direction form a meshed meshed connection structure for transmitting the first initial signal. In an exemplary embodiment, the first initial connection block 41-1 may be disposed in a circuit unit of an Nth unit column.

[0223] In an exemplary embodiment, the shape of the second initial signal line 42 can be a straight line or a broken line with the main part extending along the first direction X. The second initial signal line 42 can be located on one side of the second electrode plate 82 in the second direction Y. The second initial signal line 42 is connected to the first area of ​​the seventh active layer in each circuit unit through the sixth via V6 in each circuit unit, so that the second initial signal line 42 writes the second initial signal into the first electrode of the seventh transistor T7.

[0224] In the exemplary embodiment, the second initial signal line 42 is also connected to the second shielding electrode 36 through the eleventh via hole V11 in each circuit unit, so the second initial signal line 42 and the second shielding electrode 36 have the same potential. Since the positive projection of the second shielding electrode 36 on the substrate covers the positive projection of the first active layer (the node between the two gate electrodes) between the two gate electrodes of the first transistor T1 on the substrate, the second shielding electrode 36 with a constant voltage can effectively shield the influence of the data voltage jump on the first transistor T1, thereby stabilizing the first transistor T1 and reducing leakage current.

[0225] In an exemplary embodiment, in at least one circuit unit, a second initial connection block 42-1 may be connected to the second initial signal line 42, and the second initial connection block 42-1 is configured to be connected to a second initial connection line formed subsequently, so that the second initial signal line extending along the first direction and the second initial connection line extending along the second direction form a meshed meshed connection structure for transmitting the second initial signal. In an exemplary embodiment, the second initial connection block 42-1 may be disposed in the circuit unit of the N+1th unit column.

[0226] In an exemplary embodiment, the shape of the first power connection line 43 may be a straight line or a folded line with the main part extending along the first direction X. The first power connection line 43 may be located between the first scanning signal line 31 and the light emitting signal line 33, and the orthographic projection of the first power connection line 43 on the substrate overlaps at least partially with the orthographic projection of the second electrode plate 82 on the substrate. A first power connection block 43-1 may be connected to the first power connection line 43, and the first power connection block 43-1 is connected to the second electrode plate 82 through the eighth via hole V8 in each circuit unit. In an exemplary embodiment, the first power connection line 43 is configured to be connected to the first power line formed subsequently, thereby realizing that the first power line writes the first power signal to the second electrode plate 82 of the storage capacitor.

[0227] In an exemplary embodiment, the shape of the second power connection line 44 can be a straight line or a broken line with the main part extending along the first direction X, and the second power connection line 44 can be located between the light emitting signal line 23 and the second initial signal line 42. In at least one circuit unit, a second power connection block 44-1 can be connected to the second power connection line 44, and the second power connection block 44-1 is configured to be connected to a second power line formed subsequently. In an exemplary embodiment, the second power connection block 44-1 can be set in the circuit unit of the N+2th unit column.

[0228] In an exemplary embodiment, the first connection electrode 51 may be in the shape of a strip extending along the second direction Y. The first end of the first connection electrode 51 is connected to the second region of the first active layer (also the first region of the second active layer) through the second via hole V2. The second end of the first connection electrode 51 is connected to the first electrode plate 81 through the seventh via hole V7 after extending along the second direction Y. In an exemplary embodiment, since the first electrode plate 81 also serves as the gate electrode of the third transistor T3, the first connection electrode 51 enables the second electrode of the first transistor T1, the first electrode of the second transistor T2, the gate electrode of the third transistor T3, and the first electrode plate 81 to have the same potential, thereby forming a first node N1 of the pixel driving circuit.

[0229] In an exemplary embodiment, the second connection electrode 52 may be in a block shape (eg, rectangular), connected to the first region of the fourth active layer through the third via hole V3, and configured to be connected to a subsequently formed data signal line.

[0230] In an exemplary embodiment, the third connection electrode 53 may be in the shape of a strip extending along the second direction Y, a first end of the third connection electrode 53 is connected to the first power connection line 43, and a second end of the third connection electrode 53 is connected to the first region of the fifth active layer through the fourth via hole V4 after extending along the second direction Y. Since the first power connection line 43 is configured to be connected to the first power line formed subsequently, the first power line writes the first power signal into the first electrode of the fifth transistor T5.

[0231] In an exemplary embodiment, in at least one unit row, the first power connection line 43 and the plurality of third connection electrodes 53 may be an integrated structure connected to each other, which can ensure that the first electrode of the fifth transistor T5 of the plurality of circuit units in one unit row and the second electrode 82 of the storage capacitor have the same potential, which is beneficial to improving the uniformity of the panel, avoiding poor display of the display substrate, and ensuring the display effect of the display substrate.

[0232] In an exemplary embodiment, the shape of the fourth connection electrode 54 can be a block shape (such as a rectangle), the fourth connection electrode 54 is connected to the second region of the sixth active layer (also the second region of the seventh active layer) through the fifth via V5, and the fourth connection electrode 545 is configured to be connected to the subsequently formed anode connection electrode.

[0233] In example embodiments, positions and shapes of the third conductive layers in a plurality of cell rows may be substantially the same, and positions and shapes of the third conductive layers in a plurality of cell columns may be substantially the same.

[0234] (17) Forming a first planar layer pattern. In an exemplary embodiment, forming the first planar layer pattern may include: coating a first planar film on the substrate on which the aforementioned pattern is formed, patterning the first planar film using a patterning process to form a first planar layer covering the third conductive layer, wherein a plurality of via holes are disposed on the first planar layer, such as Fig.12 shown.

[0235] In an exemplary embodiment, the plurality of via holes of each circuit unit includes at least a twenty-first via hole V21 , a twenty-second via hole V22 , and a twenty-third via hole V23 .

[0236] In an exemplary embodiment, the orthographic projection of the twenty-first via hole V21 on the substrate is located within the range of the orthographic projection of the second connecting electrode 52 on the substrate, the first flat layer in the twenty-first via hole V21 is removed to expose the surface of the second connecting electrode 52, and the twenty-first via hole V21 is configured to connect a subsequently formed data signal line to the second connecting electrode 52 through the via hole.

[0237] In an exemplary embodiment, the orthographic projection of the twenty-second via hole V22 on the substrate is located within the range of the orthographic projections of the first power connection line 43 and the third connection electrode 53 on the substrate, the first flat layer in the twenty-second via hole V22 is removed to expose the surfaces of the first power connection line 43 and the third connection electrode 53, and the twenty-second via hole V22 is configured to connect a subsequently formed first power line to the first power connection line 43 and the third connection electrode 53 through the via hole.

[0238] In an exemplary embodiment, the orthographic projection of the twenty-third via hole V23 on the substrate is within the range of the orthographic projection of the fourth connecting electrode 54 on the substrate, the first flat layer in the twenty-third via hole V23 is removed to expose the surface of the fourth connecting electrode 54, and the twenty-third via hole V23 is configured to connect a subsequently formed anode connecting electrode to the fourth connecting electrode 54 through the via hole.

[0239] In an exemplary embodiment, a twenty-fourth via V24 may be further provided on the first flat layer of at least one circuit unit. The orthographic projection of the twenty-fourth via V24 on the substrate is located within the range of the orthographic projection of the first initial connection block 41-1 on the first initial signal line 41 on the substrate, the first flat layer in the twenty-fourth via V24 is removed, exposing the surface of the first initial connection block 41-1, and the twenty-fourth via V24 is configured to connect the first initial connection line formed subsequently to the first initial connection block 41-1 through the via. In an exemplary embodiment, the twenty-fourth via V24 may be provided in the circuit unit of the Nth unit column.

[0240] In an exemplary embodiment, a twenty-fifth via V25 may also be provided on the first flat layer of at least one circuit unit. The orthographic projection of the twenty-fifth via V25 on the substrate is located within the range of the orthographic projection of the second initial connection block 42-1 on the second initial signal line 42 on the substrate, the first flat layer in the twenty-fifth via V25 is removed, exposing the surface of the second initial connection block 42-1, and the twenty-fifth via V25 is configured to connect the second initial connection line formed subsequently to the second initial connection block 42-1 through the via. In an exemplary embodiment, the twenty-fifth via V25 may be provided in the circuit unit of the N+1th unit column.

[0241] In an exemplary embodiment, a twenty-sixth via V26 may be further provided on the first flat layer of at least one circuit unit. The orthographic projection of the twenty-sixth via V26 on the substrate is located within the range of the orthographic projection of the second power connection block 44-1 on the second power connection line 44 on the substrate, the first flat layer in the twenty-fifth via V25 is removed, exposing the surface of the second power connection block 44-1, and the twenty-sixth via V26 is configured to connect the second power line formed subsequently to the second power connection block 44-1 through the via. In an exemplary embodiment, the twenty-sixth via V26 may be provided in the circuit unit of the N+2th unit column.

[0242] (18) Forming a fourth conductive layer pattern. In an exemplary embodiment, forming the fourth conductive layer may include: depositing a fourth conductive film on the substrate having the aforementioned pattern, patterning the third conductive film using a patterning process, and forming a fourth conductive layer disposed on the first planar layer, such as Fig.13A and Fig. 13B As shown, Fig. 13B for Fig.13A In an exemplary embodiment, the fourth conductive layer may be referred to as a second source-drain metal (SD2) layer.

[0243] In an exemplary embodiment, the fourth conductive layer of each circuit unit includes at least a first power line 61 , a data signal line 63 , and an anode connection electrode 64 .

[0244] In an exemplary embodiment, the shape of the first power line 61 can be a straight line or a broken line with the main part extending along the second direction Y. The first power line 61 is connected to the first power connection line 43 and the third connection electrode 53 through the twenty-second via V22, thereby realizing the mutual connection between the first power connection line 43 extending along the first direction X and the first power line 61 extending along the second direction Y of the main part, so that the first power connection line 43 and the first power line 61 form a mesh-like mesh connection structure for transmitting the first power signal on the display substrate, which can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0245] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps with the orthographic projection of the first connection electrode 51 on the substrate. Since the first connection electrode 51 serves as the first node N1 in the pixel driving circuit, the first power line 61 with a constant voltage can effectively shield the influence of other signals in the pixel driving circuit on the first node N1, thereby preventing other signals (such as data voltage jump) from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0246] In an exemplary embodiment, an orthographic projection of the first power line 61 on the substrate may include an orthographic projection of the first connection electrode 41 on the substrate.

[0247] In an exemplary embodiment, the orthographic projection of the first power line 61 on the substrate at least partially overlaps the orthographic projection of the second shielding electrode 36 on the substrate, which can further stabilize the first transistor T1 and reduce leakage current.

[0248] In an exemplary embodiment, the shape of the data signal line 63 can be a straight line or a folded line with a main portion extending along the second direction Y, and the data signal line 63 is connected to the second connection electrode 52 through the twenty-first via hole V21. Since the second connection electrode 52 is connected to the first region of the fourth active layer, the data signal line 63 can write the data signal to the first electrode of the fourth transistor T4.

[0249] In an exemplary embodiment, the shape of the anode connection electrode 64 can be a block shape (such as a rectangle), and the anode connection electrode 64 is connected to the fourth connection electrode 54 through the twenty-third via hole V23, and the anode connection electrode 64 is configured to be connected to the anode formed subsequently. Since the fourth connection electrode 54 is connected to the second area of ​​the sixth active layer and the second area of ​​the seventh active layer, the pixel driving circuit drives the light-emitting device to emit light.

[0250] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first initial connection line 71. The shape of the first initial connection line 71 may be a straight line or a folded line with the main body extending along the second direction Y, and the first initial connection line 71 is connected to the first initial connection block 41-1 through the twenty-fourth via hole V24. Since the first initial connection block 41-1 is connected to the first initial signal line 41, the first initial signal line 41 extending along the first direction X and the first initial connection line 71 extending along the second direction Y of the main body form a mesh-like mesh connection structure for transmitting the first initial signal on the display substrate, which can not only effectively reduce the resistance of the first initial signal line and reduce the voltage drop of the first initial signal, but also effectively improve the uniformity of the first initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0251] In an exemplary embodiment, the first preliminary connection line 71 may be disposed in a circuit cell of an N-th cell column.

[0252] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a second initial connection line 72. The second initial connection line 72 may be in the shape of a straight line or a folded line extending along the second direction Y, and the second initial connection line 72 is connected to the second initial connection block 42-1 through the twenty-fifth via hole V25. Since the second initial connection block 42-1 is connected to the second initial signal line 42, the second initial signal line 42 extending along the first direction X and the second initial connection line 72 extending along the second direction Y of the main part form a mesh-like mesh connection structure for transmitting the second initial signal on the display substrate, which can not only effectively reduce the resistance of the second initial signal line and reduce the voltage drop of the second initial signal, but also effectively improve the uniformity of the second initial signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0253] In an exemplary embodiment, the second preliminary connection line 72 may be disposed in a circuit cell of an N+1th cell column.

[0254] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a second power line 62. The second power line 62 may be in the shape of a straight line or a folded line with the main body extending along the second direction Y, and the second power line 62 is connected to the second power connection block 44-1 through the twenty-sixth via hole V26. Since the second power connection block 44-1 is connected to the second power connection line 44, the second power connection line 44 extending along the first direction X and the second power line 62 extending along the second direction Y of the main body are formed on the display substrate to form a meshed connection structure for transmitting the second power signal, which can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal, effectively improve the display uniformity, and improve the display quality and display quality.

[0255] In an exemplary embodiment, the second power line 62 can be arranged in the N+3th unit column, realizing the second power line located in the panel (VSS in Panel, referred to as SIP) structure, which can greatly reduce the width of the frame power lead, greatly reduce the width of the left and right frame, and improve the screen-to-body ratio, which is conducive to achieving full-screen display.

[0256] In an exemplary embodiment, the fourth conductive layer of at least one circuit unit may further include a first light shielding block 110 as a light shielding structure. The first light shielding block 110 may be in the shape of a strip extending along the second direction Y, and may be disposed on a side of the first power line 61 close to the second transistor T2. The first side of the first light shielding block 110 is connected to the first power line 61, and the orthographic projection of a portion of the first light shielding block 110 away from the first side on the substrate at least partially overlaps with the orthographic projection of the second gate electrode 22 of the second transistor T2 on the substrate. In an exemplary embodiment, the first light shielding block 110 is configured to block light from irradiating the channel region of the second transistor T2, thereby preventing the second transistor T2 from changing its characteristics due to light, improving the electrical characteristics of the second transistor T2, and avoiding problems such as powdering.

[0257] In an exemplary embodiment, the gate electrode of the second transistor T2 includes a third sub-gate electrode forming a third channel region and a fourth sub-gate electrode forming a fourth channel region. The first light-shielding block 110 can be arranged on one side of the third channel region in the first direction X. The orthographic projection of the first light-shielding block 110 on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode on the substrate to form a first gate overlap region. The shape of the first gate overlap region can be a strip shape extending along the second direction Y.

[0258] In an exemplary embodiment, in at least one circuit unit, the first power line 61 and the first light shielding block 110 may be an integral structure connected to each other.

[0259] (19) Forming a second planar layer pattern. In an exemplary embodiment, forming the second planar layer pattern may include: coating a second planar film on the substrate on which the aforementioned pattern is formed, patterning the second planar film using a patterning process to form a second planar layer covering the fourth conductive layer, wherein a plurality of via holes are disposed on the second planar layer, such as Fig.14 shown.

[0260] In an exemplary embodiment, the plurality of vias of each circuit unit includes at least an anode via V30. The orthographic projection of the anode via V30 on the substrate is within the range of the orthographic projection of the anode connection electrode 64 on the substrate, the second flat layer in the anode via V30 is removed, exposing the surface of the anode connection electrode 64, and the anode connection electrode is configured to connect a subsequently formed anode to the anode connection electrode 64 through the via.

[0261] At this point, the drive structure layer is prepared on the substrate. In a plane parallel to the display substrate, the drive structure layer may include a plurality of circuit units, each of which may include a pixel drive circuit, and a first scan signal line, a second scan signal line, a light-emitting signal line, a first initial signal line, a second initial signal line, a data signal line, and a first power line connected to the pixel drive circuit. In a plane perpendicular to the display substrate, the drive structure layer may at least include a shielding layer, a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, a fourth conductive layer, and a second flat layer sequentially arranged on the substrate. The shielding layer may at least include a shielding electrode, the semiconductor layer may at least include an active layer of the first transistor to the seventh transistor, the first conductive layer may at least include gate electrodes of a plurality of transistors, a light-emitting signal line, and a first plate of a storage capacitor, the second conductive layer may at least include a second plate of a storage capacitor, the third conductive layer may at least include a first scan signal line, a second scan signal line, a first initial signal line, a second initial signal line, and a plurality of connection electrodes, and the fourth conductive layer may at least include a first power line and a data signal line.

[0262] In an exemplary embodiment, the substrate may be a flexible substrate, or may be a rigid substrate. The rigid substrate may include, but is not limited to, one or more of glass and quartz, and the flexible substrate may be, but is not limited to, one or more of polyethylene terephthalate, polyethylene terephthalate, polyetheretherketone, polystyrene, polycarbonate, polyarylate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers. In an exemplary embodiment, the flexible substrate may include a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer stacked. The materials of the first and second flexible material layers may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film, and the materials of the first and second inorganic material layers may be silicon nitride (SiNx) or silicon oxide (SiOx), etc., for improving the water and oxygen resistance of the substrate, and the first and second inorganic material layers are also referred to as barrier layers, and the material of the semiconductor layer may be amorphous silicon (a-si).

[0263] In an exemplary embodiment, the shielding layer, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may be made of metal materials, such as any one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum neodymium alloy (AlNd) or molybdenum niobium alloy (MoNb), and may be a single layer structure, or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may be made of any one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first planar layer and the second planar layer may be made of organic materials, such as resin, etc.

[0264] In an exemplary embodiment, after the driving structure layer is prepared, a light emitting structure layer is prepared on the driving structure layer. The preparation process of the light emitting structure layer may include the following operations.

[0265] (20) Forming an anode conductive layer pattern. In an exemplary embodiment, forming the anode conductive layer pattern may include: depositing an anode conductive film on the substrate formed with the aforementioned pattern, patterning the anode conductive film using a patterning process to form an anode conductive layer disposed on the second flat layer, wherein the anode conductive layer includes at least a plurality of anode patterns, such as Fig.15A and Fig. 15B As shown, Fig. 15B for Fig.15A Schematic diagram of the plan view of the anode conductive layer.

[0266] In an exemplary embodiment, the plurality of anodes may include at least a first anode 90A located in the first light emitting unit, a second anode 90B located in the second light emitting unit, and a third anode 90C located in the third light emitting unit, and the first anode 90A, the second anode 90B, and the third anode 90C may be connected to the anode connection electrode 64 of the corresponding circuit unit through the anode via hole V30, respectively. The second anode 90B and the third anode 90C may be disposed on one side of the first anode 90A in the second direction Y, and the third anode 90C may be disposed on one side of the second anode 90B in the first direction X.

[0267] In an exemplary embodiment, the first light emitting unit may be a red light emitting unit emitting red light, the second light emitting unit may be a green light emitting unit emitting green light, and the third light emitting unit may be a blue light emitting unit emitting blue light.

[0268] In an exemplary embodiment, at least one of the first anode 90A, the second anode 90B and the third anode 90C may include an anode body portion and an anode connecting portion connected to each other, the anode connecting portion being connected to the anode body portion on one hand and to the anode connecting electrode 64 through the anode via V30 on the other hand.

[0269] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the first anode 90A on the substrate at least partially overlaps with the orthographic projection of the second gate electrode on the substrate, and the orthographic projection of the first anode 90A on the substrate at least partially overlaps with the orthographic projection of the first shading block 110 on the substrate.

[0270] In an exemplary embodiment, the anode conductive layer may have a single-layer structure, such as indium tin oxide ITO or indium zinc oxide IZO, or may have a multi-layer composite structure, such as ITO / Ag / ITO.

[0271] (21) Forming a pixel definition layer pattern. In an exemplary embodiment, forming a pixel definition layer pattern may include: coating a pixel definition film on a substrate formed with the aforementioned pattern, patterning the pixel definition film using a patterning process to form a pixel definition layer pattern covering the anode conductive layer pattern, wherein a plurality of pixel openings are provided on the pixel definition layer, such as Fig.16 shown.

[0272] In an exemplary embodiment, the plurality of pixel openings may include a first pixel opening 100A located in a red light emitting unit, a second pixel opening 100B located in a green light emitting unit, and a second pixel opening 100B located in a blue light emitting unit. The orthogonal projection of the first pixel opening 100A on the substrate is located within the range of the orthogonal projection of the first anode 90A on the substrate, and the pixel definition film in the first pixel opening 100A is removed to expose the surface of the first anode 90A. The orthogonal projection of the second pixel opening 100B on the substrate is located within the range of the orthogonal projection of the second anode 90B on the substrate, and the pixel definition film in the second pixel opening 100B is removed to expose the surface of the second anode 90B. The orthogonal projection of the third pixel opening 100C on the substrate is located within the range of the orthogonal projection of the third anode 90C on the substrate, and the pixel definition film in the third pixel opening 100C is removed to expose the surface of the third anode 90C.

[0273] In an exemplary embodiment, the subsequent preparation process may include: first forming an organic light-emitting layer by an evaporation or inkjet printing process, then forming a cathode on the organic light-emitting layer, and then forming a packaging structure layer, the packaging structure layer may include a stacked first packaging layer, a second packaging layer and a third packaging layer, the first packaging layer and the third packaging layer may be made of inorganic materials, the second packaging layer may be made of organic materials, and the second packaging layer is arranged between the first packaging layer and the third packaging layer to ensure that external water vapor cannot enter the light-emitting structure layer.

[0274] Fig.17 for Fig.15A A magnified image of area A. Fig.18 for Fig.17 The cross-sectional view along the AA axis. Fig.17 and Fig.18As shown, the shielding layer is disposed on the substrate 10, and the shielding layer may include at least a second shielding electrode 92, and the second shielding electrode 92 is configured to shield the channel region of the second transistor T2. The first insulating layer 10A is disposed on the side of the shielding layer away from the substrate 10, and the semiconductor layer is disposed on the side of the first insulating layer 10A away from the substrate 10. The semiconductor layer may include at least a second active layer 12 of the second transistor T2, and the orthographic projection of the second active layer 12 on the substrate at least partially overlaps with the orthographic projection of the second shielding electrode 92 on the substrate. The second insulating layer 10B is disposed on the side of the semiconductor layer away from the substrate 10, and the first conductive layer is disposed on the side of the second insulating layer 10B away from the substrate 10. The first conductive layer may include at least a second gate electrode 22 of the second transistor T2, and the orthographic projection of the second gate electrode 22 on the substrate at least partially overlaps with the orthographic projection of the second active layer on the substrate. The second gate electrode 22 may include a third sub-gate electrode and a fourth sub-gate electrode 22-2, the overlapping region of the third sub-gate electrode and the second active layer 12 is a third channel region, and the overlapping region of the fourth sub-gate electrode 22-2 and the second active layer 12 is a fourth channel region. The third insulating layer 10C is disposed on a side of the first conductive layer away from the substrate 10, the second conductive layer is disposed on a side of the third insulating layer 10C away from the substrate 10, the second conductive layer may include at least a first shielding electrode 35, and the first shielding electrode 35 is configured to shield the influence of the data voltage jump on the second transistor T2. The fourth insulating layer 10D is disposed on a side of the second conductive layer away from the substrate 10, the third conductive layer is disposed on a side of the fourth insulating layer 10D away from the substrate 10, the third conductive layer may include at least a first scan signal line 31 and a second connection electrode 52, the first scan signal line 31 is connected to the second gate electrode 22 through a via hole, and the second connection electrode 52 is connected to the first region of the fourth active layer through a via hole. The first flat layer 10E is disposed on a side of the third conductive layer away from the substrate 10, the fourth conductive layer is disposed on a side of the first flat layer 10E away from the substrate 10, the fourth conductive layer may at least include a first power line 61, a second power line 62 and a data signal line 63, and the data signal line 63 is connected to the second connection electrode 52 through a via hole. The second flat layer 10F is disposed on a side of the fourth conductive layer away from the substrate 10, the anode conductive layer is disposed on a side of the second flat layer 10F away from the substrate 10, and the anode conductive layer may at least include a first anode 90A.

[0275] In an exemplary embodiment, at least one circuit unit may further include a first light shielding block 110. The first light shielding block 110 may be in the shape of a strip extending along the second direction Y, and may be disposed on a side of the third channel region close to the first power line 61, and on a side of the first power line 61 close to the second gate electrode 22, and the first power line 61 and the first light shielding block 110 may be an integral structure connected to each other. The orthographic projection of the first light shielding block 110 on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode 22-2 of the second gate electrode 22 on the substrate. The first light shielding block 110 is configured to block light from irradiating the channel region of the second transistor T2, which can prevent the second transistor T2 from changing its characteristics due to light, improve the electrical characteristics of the second transistor T2, and avoid problems such as powdering.

[0276] In an exemplary embodiment, the orthographic projection of the first light shielding block 110 on the substrate and the orthographic projection of the fourth sub-gate electrode 22-2 on the substrate have a first gate overlapping region, and the shape of the first gate overlapping region can be a strip shape extending along the second direction Y, and can be located at the edge of the fourth sub-gate electrode 22-2 near the first power line 61.

[0277] In example embodiments, the first gate overlap region may have a first width L1, the first width L1 may be greater than or equal to 0.5 μm, and the first width L1 may be a maximum dimension in the first direction X of the first gate overlap region.

[0278] In an exemplary embodiment, an orthographic projection of the first light shielding block 110 on the substrate at least partially overlaps an orthographic projection of the fourth channel region on the substrate.

[0279] In an exemplary embodiment, the fourth channel region has a channel area. The orthographic projection of the first light shielding block 110 on the substrate and the orthographic projection of the fourth channel region on the substrate have a first channel overlapping region, the first channel overlapping region has a first overlapping area, and the ratio of the first overlapping area to the channel area may be greater than or equal to 0.05.

[0280] The inventors of the present application have found through research that the main reason for the powdering problem and other problems in the existing display devices is that the channel region of the transistor is irradiated by light. Fig.19 FIG. 1 is a schematic diagram of a second transistor T2 being illuminated by light. Fig.19As shown, in the existing display substrate, since there is a light leakage area on the side of the second transistor T2 close to the first power line 61, light can directly irradiate the channel area of ​​the second transistor T2, such as light G1. In addition, since a second shielding electrode 92 is provided under the second active layer 12 of the second transistor T2, the second shielding electrode 92 is configured to block impurity ions from entering the channel area, and thus the size of the second shielding electrode 92 is larger than the size of the second active layer 12, so that part of the light may irradiate the second shielding electrode 92, and then be reflected by the second shielding electrode 92 to irradiate the channel area of ​​the second transistor T2, such as light G2. Studies have shown that the channel area of ​​the second transistor T2 is irradiated with light and the current I is turned off. OFF The voltage Vgs of the third transistor T3 decreases, and the brightness of the corresponding light-emitting unit decreases, resulting in powdering and other problems. Further research shows that the brightness reduction and powdering phenomenon of the green light-emitting unit are more obvious.

[0281] An exemplary embodiment of the present disclosure provides a display substrate, in which a first light-shielding block is arranged in a fourth conductive layer, and an orthographic projection of the first light-shielding block on the substrate at least partially overlaps with an orthographic projection of a second gate electrode of the second transistor T2 on the substrate, thereby shielding light in a channel region of the second transistor T2, eliminating a light leakage region, and allowing light to be reflected between the fourth conductive layer and the anode conductive layer. The light will neither directly irradiate the channel region of the second transistor T2 nor be reflected from the first light-shielding block to the channel region of the second transistor T2, thereby effectively avoiding a change in the characteristics of the second transistor T2 and effectively solving problems such as powdering.

[0282] In an exemplary embodiment, a first light shielding block is provided on one side (right side, upper right side and lower right side) of the second transistor T2 close to the first power line, a second power line is provided on one side (left side) of the second transistor T2 away from the first power line, a first anode is provided on one side (lower side) of the second transistor T2 close to the storage capacitor, and a first shielding electrode is provided on one side (upper side) of the second transistor T2 away from the storage capacitor, so that the embodiment of the present disclosure can effectively prevent light from irradiating the channel region of the second transistor T2 in all directions, and avoid the characteristic change of the second transistor T2 to the greatest extent, and improve the display quality and display quality. In addition, the embodiment of the present disclosure sets the first light shielding block on the fourth conductive layer, which will not affect other wiring layouts.

[0283] The embodiment of the present disclosure provides a first power connection line and a first power line, and the first power connection line and the first power line form a mesh structure for transmitting a first power signal with a mesh connection structure on a display substrate. This can not only effectively reduce the resistance of the first power line and reduce the voltage drop of the first power signal, but also effectively improve the uniformity of the first power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0284] The embodiment of the present disclosure provides a second power connection line and a second power line, and the second power connection line and the second power line form a mesh structure for transmitting a second power signal on a display substrate with a mesh connection structure. This can not only effectively reduce the resistance of the second power line and reduce the voltage drop of the second power signal, but also effectively improve the uniformity of the second power signal in the display substrate, effectively improve the display uniformity, and improve the display quality.

[0285] The disclosed embodiment realizes a VSS in Panel (SIP) structure by setting a second power line in the display area, which can greatly reduce the width of the frame power lead, greatly reduce the width of the left and right frames, improve the screen-to-body ratio, and facilitate full-screen display.

[0286] The embodiment of the present disclosure sets the first initial connection line and the second initial connection line. The first initial signal line and the first initial connection line form a mesh structure for transmitting the first initial signal on the display substrate, and the second initial signal line and the second initial connection line form a mesh structure for transmitting the second initial signal on the display substrate. This can not only effectively reduce the resistance of the initial signal line and reduce the voltage drop of the initial signal, but also effectively improve the uniformity of the initial signal in the display substrate, effectively improve the display uniformity, and improve the display quality and display quality.

[0287] The embodiment of the present disclosure can shield the influence of the data voltage jump on the first transistor T1 and the second transistor T2 by providing a shielding electrode, thereby preventing the data voltage jump from affecting the normal operation of the pixel driving circuit and improving the display effect.

[0288] In the embodiment of the present disclosure, the first power line is provided to shield the first node N1 of the pixel driving circuit, thereby effectively preventing other signals from affecting the potential of the first node N1 of the pixel driving circuit, thereby improving the display effect.

[0289] The disclosed embodiment effectively reduces the resistance of the scan signal line and the voltage drop of the scan signal by disposing the first scan signal line and the second scan signal line in the first source-drain metal layer, thereby increasing the compensation speed and improving the display quality.

[0290] The preparation process disclosed in the present invention is well compatible with the existing preparation process, and the process is simple to realize, easy to implement, has high production efficiency, low production cost and high yield rate.

[0291] Fig. 20 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. Fig.21 for Fig. 20 A plan view of the third conductive layer in FIG. Fig. 22 for Fig. 20 In an exemplary embodiment, the structure of the pixel driving circuit in the circuit unit of this embodiment is similar to Figure 5 The structures shown are basically the same, except that the light shielding structure of this embodiment is a second light shielding block 120, and the second light shielding block 120 is disposed in the third conductive layer.

[0292] like Fig. 20 , Fig.21 and Fig. 22 As shown, the third conductive layer of at least one circuit unit may further include a second light shielding block 120 as a light shielding structure. The shape of the second light shielding block 120 may be a strip shape extending along the second direction Y. In the first direction X, the second light shielding block 120 may be arranged on the side of the third channel region close to the first power line 61. In the second direction Y, the second light shielding block 120 may be arranged on the side of the first scan signal line 31 away from the storage capacitor. The first end of the second light shielding block 120 is connected to the first scan signal line 31, and the second end of the second light shielding block 120 extends in a direction away from the storage capacitor, so that the positive projection of the second light shielding block 120 on the substrate overlaps at least partially with the positive projection of the fourth sub-gate electrode 22-2 of the second gate electrode 22 on the substrate. The second light shielding block 120 is configured to block light from irradiating the channel region of the second transistor T2, which can prevent the second transistor T2 from changing its characteristics due to light, improve the electrical characteristics of the second transistor T2, and avoid problems such as powdering.

[0293] In an exemplary embodiment, the orthographic projection of the second light shielding block 120 on the substrate and the orthographic projection of the fourth sub-gate electrode 22-2 on the substrate have a second gate overlapping region, and the shape of the second gate overlapping region can be a strip shape extending along the second direction Y, and can be located at the edge of the fourth sub-gate electrode 22-2 near the first power line 61.

[0294] In an exemplary embodiment, the second gate overlap region may have a second width L2, the second width L2 may be greater than or equal to 0.5 μm, and the second width L2 may be a maximum dimension of the second gate overlap region in the first direction X.

[0295] In an exemplary embodiment, an orthographic projection of the second light shielding block 120 on the substrate at least partially overlaps an orthographic projection of the fourth channel region on the substrate.

[0296] In an exemplary embodiment, the fourth channel region has a channel area. The orthographic projection of the second light shielding block 120 on the substrate and the orthographic projection of the fourth channel region on the substrate have a second channel overlapping region, the second channel overlapping region has a second overlapping area, and the ratio of the second overlapping area to the channel area may be greater than or equal to 0.05.

[0297] In an exemplary embodiment, in at least one circuit unit, the first scan signal line 31 and the second light shielding block 120 may be an integral structure connected to each other.

[0298] In the embodiment of the present disclosure, a second light-shielding block is arranged in the third conductive layer, and the orthographic projection of the second light-shielding block on the substrate at least partially overlaps with the orthographic projection of the second gate electrode of the second transistor T2 on the substrate, thereby shielding the light in the channel region of the second transistor T2 and eliminating the light leakage region, so that the light is reflected between the third conductive layer and the anode conductive layer. The light will neither directly irradiate the channel region of the second transistor T2 nor be reflected from the first light-shielding block to the channel region of the second transistor T2, thereby effectively avoiding the change in the characteristics of the second transistor T2 and effectively solving the problem of powdering.

[0299] In an exemplary embodiment, the light-shielding structure of this embodiment may only include a second light-shielding block set in the third conductive layer, or may include a second light-shielding block set in the third conductive layer and a first light-shielding block set in the fourth conductive layer, and the present disclosure is not limited thereto.

[0300] Fig.23 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. Fig.24 for Fig.23 A plan view of the second conductive layer in FIG. Fig.25 for Fig.23 In an exemplary embodiment, the structure of the pixel driving circuit in the circuit unit of this embodiment is similar to Figure 5 The structures shown are basically the same, except that the light shielding structure of this embodiment is a third light shielding block 130, and the third light shielding block 130 is disposed in the second conductive layer.

[0301] like Fig.23 , Fig.24 and Fig.25As shown, the second conductive layer of at least one circuit unit may further include a third light shielding block 130 as a light shielding structure. The third light shielding block 130 may be in the shape of a strip extending along the second direction Y, and may be disposed on a side of the third channel region close to the first power line 61. The orthographic projection of the third light shielding block 130 on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode 22-2 of the second gate electrode 22 on the substrate. The third light shielding block 130 is configured to block light from irradiating the channel region of the second transistor T2, thereby preventing the second transistor T2 from changing its characteristics due to light, improving the electrical characteristics of the second transistor T2, and avoiding problems such as powdering.

[0302] In an exemplary embodiment, the orthographic projection of the third light shielding block 130 on the substrate and the orthographic projection of the fourth sub-gate electrode 22-2 on the substrate have a third gate overlapping region, and the shape of the third gate overlapping region can be a strip shape extending along the second direction Y, and can be located at the edge of the fourth sub-gate electrode 22-2 near the first power line 61.

[0303] In an exemplary embodiment, the third gate overlap region may have a third width L3, the third width L3 may be greater than or equal to 0.5 μm, and the third width L3 may be a maximum dimension in the first direction X of the third gate overlap region.

[0304] In an exemplary embodiment, an orthographic projection of the third light shielding block 130 on the substrate at least partially overlaps an orthographic projection of the fourth channel region on the substrate.

[0305] In an exemplary embodiment, the fourth channel region has a channel area. The orthographic projection of the third light shielding block 130 on the substrate and the orthographic projection of the fourth channel region on the substrate have a third channel overlapping region, the third channel overlapping region has a third overlapping area, and the ratio of the third overlapping area to the channel area may be greater than or equal to 0.05.

[0306] In an exemplary embodiment, in at least one circuit unit, the third light shielding block 130 and the first shielding electrode 35 may be an integral structure connected to each other.

[0307] In an exemplary embodiment, the first shielding electrode 35 of this embodiment may include a first extension segment 35-1, a second extension segment 35-2 and a third extension segment 35-3 connected in sequence, and the positions and shapes of the second extension segment 35-2 and the third extension segment 35-3 are similar to those of the first shielding electrode 35 of the present embodiment. Figure 5 The structures shown are basically the same, except that the first extension segment 35 - 1 in this embodiment is bent so that a portion of the first extension segment 35 - 1 is close to the fourth sub-gate electrode 22 - 2 and overlaps with the fourth sub-gate electrode 22 - 2 .

[0308] In an exemplary embodiment, the first extending section 35 - 1 of the present embodiment may serve as the third light shielding block 130 , or the first shielding electrode 35 may serve as the third light shielding block 130 .

[0309] In the embodiment of the present disclosure, a third light-shielding block is arranged in the second conductive layer, and the orthographic projection of the third light-shielding block on the substrate at least partially overlaps with the orthographic projection of the second gate electrode of the second transistor T2 on the substrate, thereby shielding the light in the channel region of the second transistor T2 and eliminating the light leakage region, so that the light is reflected between the second conductive layer and the anode conductive layer. The light will neither directly irradiate the channel region of the second transistor T2 nor be reflected from the first light-shielding block to the channel region of the second transistor T2, thereby effectively avoiding changes in the characteristics of the second transistor T2 and effectively solving problems such as powdering.

[0310] In an exemplary embodiment, the light shading structure of the present embodiment may include only a third light shading block disposed in the second conductive layer, or may include a third light shading block disposed in the second conductive layer and a first light shading block disposed in the fourth conductive layer, or may include a third light shading block disposed in the second conductive layer and a second light shading block disposed in the third conductive layer, or may include a third light shading block disposed in the second conductive layer, a second light shading block disposed in the third conductive layer, and a first light shading block disposed in the fourth conductive layer, and the present disclosure is not limited thereto.

[0311] Fig.26 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. Fig. 27 for Fig.26 In an exemplary embodiment, the structure of the pixel driving circuit in the circuit unit of this embodiment is similar to Figure 5 The structures shown are basically the same, except that the light shielding structure of this embodiment is a fourth light shielding block 140 , and the fourth light shielding block 140 shields light from the upper side of the second transistor T2 .

[0312] like Fig.26 and Fig. 27 As shown, the second conductive layer of at least one circuit unit may further include a fourth light shielding block 140 as a light shielding structure. The fourth light shielding block 140 may be in the shape of a strip extending along the first direction X, and may be disposed on a side of the fourth channel region away from the storage capacitor. The orthographic projection of the fourth light shielding block 140 on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode 22-2 of the second gate electrode 22 on the substrate. The fourth light shielding block 140 is configured to block light from irradiating the channel region of the second transistor T2, thereby preventing the second transistor T2 from changing its characteristics due to light, improving the electrical characteristics of the second transistor T2, and avoiding problems such as powdering.

[0313] In an exemplary embodiment, the orthographic projection of the fourth light shielding block 140 on the substrate and the orthographic projection of the fourth sub-gate electrode 22-2 on the substrate have a fourth gate overlapping region, and the shape of the fourth gate overlapping region can be a strip shape extending along the first direction X, and can be located at the edge of the fourth sub-gate electrode 22-2 away from the storage capacitor.

[0314] In example embodiments, the fourth gate overlap region may have a fourth width, the fourth width may be greater than or equal to 0.5 μm, and the fourth width may be a maximum dimension of the fourth gate overlap region in the second direction Y.

[0315] In an exemplary embodiment, in at least one circuit unit, the fourth light shielding block 140 and the first shielding electrode 35 may be an integral structure connected to each other.

[0316] In an exemplary embodiment, the first shielding electrode 35 of this embodiment may include a first extension segment 35-1, a second extension segment 35-2 and a third extension segment 35-3 connected in sequence, and the positions and shapes of the first extension segment 35-1 and the third extension segment 35-3 are similar to those of the first shielding electrode 35 of the present embodiment. Figure 5 The structures shown are basically the same, except that the edge of the second extension segment 35-2 close to the fourth sub-gate electrode 22-2 in this embodiment moves downward toward the storage capacitor, so that the second extension segment 35-2 is close to the fourth sub-gate electrode 22-2 and overlaps with the fourth sub-gate electrode 22-2.

[0317] In an exemplary embodiment, the second extending section 35 - 2 of the present embodiment may serve as the fourth light shielding block 140 , or the first shielding electrode 35 may serve as the fourth light shielding block 140 .

[0318] In the embodiment of the present disclosure, a fourth light-shielding block is arranged in the second conductive layer, and the orthographic projection of the fourth light-shielding block on the substrate at least partially overlaps with the orthographic projection of the second gate electrode of the second transistor T2 on the substrate, thereby shielding the light in the channel region of the second transistor T2 and eliminating the light leakage region. The light will neither directly irradiate the channel region of the second transistor T2 nor be reflected from the first light-shielding block to the channel region of the second transistor T2, thereby effectively avoiding changes in the characteristics of the second transistor T2 and effectively solving problems such as powdering.

[0319] In an exemplary embodiment, the structure of the fourth light shielding block of this embodiment may be combined with the structures of the first light shielding block, the second light shielding block and the third light shielding block of the aforementioned embodiments, and the present disclosure does not limit this.

[0320] Fig.28 FIG. 1 is a schematic diagram of a planar structure of another display substrate according to an exemplary embodiment of the present disclosure. Fig.29 for Fig.28In an exemplary embodiment, the structure of the pixel driving circuit in the circuit unit of this embodiment is similar to Figure 5 The structures shown are basically the same, except that the light shielding structure of this embodiment is a fifth light shielding block 150, and the fifth light shielding block 150 can be arranged in the fourth conductive layer.

[0321] like Fig.28 and Fig.29 As shown, the fourth conductive layer of at least one circuit unit may further include a fifth light shielding block 150 as a light shielding structure. The fifth light shielding block 150 may be in a block shape (such as a rectangle), and may be disposed on a side of the first power line 61 close to the data signal line 63. The first end of the fifth light shielding block 150 is connected to the first power line 61, and the second end of the fifth light shielding block 150 extends in a direction close to the data signal line 63, so that the orthographic projection of the fifth light shielding block 150 on the substrate at least partially overlaps with the orthographic projection of the first sub-gate electrode 21-1 of the first gate electrode 21 on the substrate. The fifth light shielding block 150 is configured to block light from irradiating the channel region of the first transistor T1, thereby preventing the first transistor T1 from changing its characteristics due to light, improving the electrical characteristics of the first transistor T1, and improving the display quality and display quality.

[0322] In an exemplary embodiment, in at least one circuit unit, the first power line 61 and the fifth light shielding block 150 may be an integral structure connected to each other.

[0323] In an exemplary embodiment, the first gate electrode of the first transistor T1 may include a first sub-gate electrode 21-1 forming a first channel region and a second sub-gate electrode 21-2 forming a second channel region, and the second sub-gate electrode 21-2 may be disposed on one side of the first sub-gate electrode 21-1 in the first direction X. In at least one circuit unit, an orthographic projection of the fifth light shielding block 150 on the substrate at least partially overlaps an orthographic projection of the first sub-gate electrode 21-1 on the substrate, and an orthographic projection of the first power line 61 on the substrate at least partially overlaps an orthographic projection of the second sub-gate electrode 21-2 on the substrate.

[0324] In an exemplary embodiment, in at least one circuit unit, the orthographic projection of the fifth light shielding block 150 on the substrate includes an orthographic projection of the first channel region on the substrate that at least partially overlaps, and the orthographic projection of the first power line 61 on the substrate includes an orthographic projection of the second channel region on the substrate that at least partially overlaps, so that the first power line 61 and the fifth light shielding block 150 of the integrated structure can achieve complete shielding of the first transistor T1.

[0325] The embodiment of the present disclosure provides a fifth light-shielding block, and the orthographic projection of the fifth light-shielding block on the substrate at least partially overlaps with the orthographic projection of the first gate electrode of the first transistor T1 on the substrate, thereby shielding the light in the channel region of the first transistor T1, eliminating the light leakage area, effectively avoiding the characteristic change of the first transistor T1, and improving the display quality.

[0326] In an exemplary embodiment, the structure of the fifth light shielding block of this embodiment may be combined with the structures of the first light shielding block, the second light shielding block, the third light shielding block and the fourth light shielding block of the previous embodiments, and the present disclosure does not limit this.

[0327] Fig.30 FIG. 1 is a schematic diagram of a planar structure of another display substrate of an exemplary embodiment of the present disclosure. In an exemplary embodiment, the structure of the pixel driving circuit in the circuit unit of this embodiment is similar to Figure 5 The structures shown are basically the same, except that the fourth conductive layer of this embodiment further includes an anode spacer 200 .

[0328] like Fig.28 and Fig.29 As shown, the fourth conductive layer of at least one circuit unit may further include an anode pad 200. The anode pad 200 may be in a "C" shape, and may be disposed on a side of the first power line 61 close to the data signal line 63, and connected to the first power line 61. In an exemplary embodiment, the anode pad 200 is configured to allow the subsequently formed anode to have good flatness, which may effectively avoid defects such as off-screen watermarks (Mura) caused by poor anode flatness, and may effectively improve color deviation and improve display quality.

[0329] In an exemplary embodiment, the anode spacer 200 may be disposed in the circuit cells of the Nth cell column and the N+2th cell column.

[0330] The structure and preparation process shown above in the present disclosure are merely exemplary. In an exemplary embodiment, the corresponding structure can be changed and the patterning process can be increased or decreased according to actual needs, and the present disclosure does not limit this.

[0331] In an exemplary embodiment, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit, such as OLED, quantum dot display (QLED), light emitting diode display (Micro LED or Mini LED) or quantum dot light emitting diode display (QDLED), etc., which is not limited in the present disclosure.

[0332] The present disclosure also provides a method for preparing a display substrate to manufacture the display substrate provided in the above embodiment. In an exemplary embodiment, the display substrate includes a plurality of circuit units, at least one circuit unit includes a pixel driving circuit, a first power line, and at least one light shielding structure; the pixel driving circuit includes at least a first transistor, a second transistor, and a storage capacitor, the storage capacitor includes a stacked first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to the first power line; the preparation method may include:

[0333] A first conductive layer is formed on a substrate, wherein a gate electrode of the first transistor and a gate electrode of the second transistor are arranged in the first conductive layer,

[0334] A plurality of conductive layers are formed on a side of the first conductive layer away from the substrate, and at least one shading structure is arranged in any one or more of the plurality of conductive layers, and an orthographic projection of the shading structure on the substrate at least partially overlaps with an orthographic projection of the gate electrode of the first transistor and / or the gate electrode of the second transistor on the substrate.

[0335] The present disclosure also provides a display device, which includes the aforementioned display substrate. The display device can be any product or component with a display function, such as a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc., but the embodiments of the present invention are not limited thereto.

[0336] Although the embodiments disclosed in the present disclosure are as above, it should be noted that the above embodiments are merely exemplary and not restrictive. Therefore, the present disclosure is not limited to the contents specifically shown and described herein. Various modifications, substitutions or omissions may be made to the forms and details of the implementation without departing from the scope of the present disclosure.

Claims

1. A display substrate, characterized in that: It comprises a plurality of circuit units, at least one of which comprises a pixel driving circuit, a first power line and at least one shading structure; the pixel driving circuit comprises at least a first transistor, a second transistor and a storage capacitor, the storage capacitor comprises a stacked first electrode plate and a second electrode plate, the first electrode plate is connected to the second electrode of the first transistor and the first electrode of the second transistor, and the second electrode plate is connected to the first power line; in a direction perpendicular to a display substrate, the display substrate comprises at least a first conductive layer arranged on a substrate and a plurality of conductive layers arranged on a side of the first conductive layer away from the substrate, the gate electrode of the first transistor and the gate electrode of the second transistor are arranged in the first conductive layer, at least one shading structure is arranged in any one or more layers of the plurality of conductive layers, and the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the gate electrode of the first transistor and / or the gate electrode of the second transistor on the substrate.

2. The display substrate according to claim 1, characterized in that: The first power line is arranged on one side of the first direction of the second transistor, the storage capacitor is arranged on one side of the second direction of the second transistor, and the first direction and the second direction intersect; the gate electrode of the second transistor includes a third sub-gate electrode extending along the first direction and forming a third channel region and a fourth sub-gate electrode extending along the second direction and forming a fourth channel region, and the fourth sub-gate electrode is arranged on one side of the first direction of the third sub-gate electrode; the shading structure is arranged on one side of the first direction of the third channel region, and the orthographic projection of the shading structure on the substrate at least partially overlaps with the orthographic projection of the fourth sub-gate electrode on the substrate.

3. The display substrate according to claim 2, characterized in that: An orthographic projection of the light shielding structure on the substrate and an orthographic projection of the fourth sub-gate electrode on the substrate have a gate overlapping region, and in the first direction, a width of the gate overlapping region is greater than or equal to 0.5 μm.

4. The display substrate according to claim 2, characterized in that: An orthographic projection of the light shielding structure on the substrate at least partially overlaps with an orthographic projection of the fourth channel region on the substrate.

5. The display substrate according to claim 4, characterized in that: The fourth channel region has a channel area, the orthographic projection of the shading structure on the substrate and the orthographic projection of the fourth channel region on the substrate have a channel overlapping region, the channel overlapping region has an overlapping area, and the ratio of the overlapping area to the channel area is greater than or equal to 0.

05.

6. The display substrate according to claim 2, characterized in that: The multiple conductive layers include at least a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one shading structure includes a first shading block arranged in the fourth conductive layer, the first shading block is arranged on one side of the first direction of the third channel region, the orthographic projection of the first shading block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a first overlapping area, and the shape of the first overlapping area is a strip shape extending along the second direction.

7. The display substrate according to claim 6, characterized in that: The first light shielding block and the first power line are an integrated structure connected to each other.

8. The display substrate according to claim 2, characterized in that: The multiple conductive layers include at least a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one shading structure includes a second shading block arranged in the third conductive layer, the second shading block is arranged on one side of the first direction of the third channel region, the orthographic projection of the second shading block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a second overlapping area, and the shape of the second overlapping area is a strip shape extending along the second direction.

9. The display substrate according to claim 8, characterized in that: The gate electrode of the second transistor is connected to the first scanning signal line, and the second light shielding block and the first scanning signal line are an integrated structure connected to each other.

10. The display substrate according to claim 2, characterized in that: The multiple conductive layers include at least a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one shading structure includes a third shading block arranged in the second conductive layer, and the third shading block is arranged on one side of the first direction of the third channel region. The orthographic projection of the third shading block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a third overlapping area, and the shape of the third overlapping area is a strip shape extending along the second direction.

11. The display substrate according to claim 10, characterized in that: At least one circuit unit also includes a first shielding electrode, a first end of the first shielding electrode is connected to the second electrode plate, a second end of the first shielding electrode has an orthographic projection on the substrate that at least partially overlaps with a orthographic projection of a second active layer between two gate electrodes of the second transistor on the substrate, and the third shading block and the first shielding electrode are an integrated structure that are interconnected.

12. The display substrate according to claim 2, characterized in that: The multiple conductive layers include at least a second conductive layer, a third conductive layer and a fourth conductive layer arranged in sequence along a direction away from the substrate, and at least one shading structure includes a fourth shading block arranged in the second conductive layer, and the fourth shading block is arranged on a side of the fourth channel region away from the storage capacitor. The orthographic projection of the fourth shading block on the substrate and the orthographic projection of the fourth sub-gate electrode on the substrate form a fourth overlapping area, and the shape of the fourth overlapping area is a strip shape extending along the first direction.

13. The display substrate according to claim 12, characterized in that: At least one circuit unit also includes a first shielding electrode, a first end of the first shielding electrode is connected to the second electrode plate, a second end of the first shielding electrode has an orthographic projection on the substrate that at least partially overlaps with a orthographic projection of a second active layer between two gate electrodes of the second transistor on the substrate, and the fourth shading block and the first shielding electrode are an integrated structure that are interconnected.

14. The display substrate according to any one of claims 1 to 13, characterized in that: The first power line is arranged on one side of the first direction of the second transistor, the storage capacitor is arranged on one side of the second direction of the second transistor, and the first direction and the second direction intersect; the first transistor is arranged on a side of the second transistor away from the storage capacitor, the first transistor includes a first sub-gate electrode forming a first channel region and a second sub-gate electrode forming a second channel region, and the second sub-gate electrode is arranged on one side of the first direction of the first sub-gate electrode; the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second sub-gate electrode on the substrate, and the orthographic projection of the first power line on the substrate at least partially overlaps with the orthographic projection of the second channel region on the substrate.

15. The display substrate according to claim 14, characterized in that: At least one shading structure includes a fifth shading block, at least one fifth shading block is arranged on a side of the second transistor away from the storage capacitor, the fifth shading block and the first power line are an integrated structure connected to each other, the orthographic projection of the fifth shading block on the substrate at least partially overlaps with the orthographic projection of the first sub-gate electrode on the substrate, and the orthographic projection of the fifth shading block on the substrate at least partially overlaps with the orthographic projection of the first channel region on the substrate.

16. The display substrate according to any one of claims 1 to 13, characterized in that: At least one circuit unit also includes a second shielding electrode and at least one initial signal line, wherein the initial signal line is configured to provide an initial signal to the pixel driving circuit, the second shielding electrode is connected to the initial signal line, and the positive projection of the second shielding electrode on the substrate at least partially overlaps with the positive projection of the first active layer between the two gate electrodes of the first transistor on the substrate.

17. The display substrate according to claim 16, characterized in that: An orthographic projection of the second shielding electrode on the substrate at least partially overlaps with an orthographic projection of the first power line on the substrate.

18. The display substrate according to any one of claims 1 to 13, characterized in that: The display substrate also includes a shielding layer arranged between the base and the first conductive layer, the shielding layer includes at least a first shielding block and a second shielding block, the orthographic projection of the first shielding block on the base includes the orthographic projection of the gate electrode of the second transistor on the base, and the orthographic projection of the second shielding block on the base includes the orthographic projection of the gate electrode of the first transistor on the base.

19. A display device, characterized in that: The display substrate comprises the display substrate as claimed in any one of claims 1 to 18.

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