UWB radio frequency switch power supply management circuit

Abstract

The utility model relates to the technical field of UWB power supply management, and discloses a UWB radio frequency switch power supply management circuit, which comprises a first signal input end VCTL1, a second signal input end VCTL2, an external voltage input end VBIAS, a voltage selection unit, a clock generation unit, a driving voltage generation unit and a radio frequency channel switch unit. In actual use, high-level signals input by the first signal input end VCTL1 and the second signal input end VCTL2 are input to the driving voltage generation unit; when no external voltage is input into the external voltage input end VBIS, the high-level signal at the moment is 3.3 V, and the driving voltage generation unit outputs the 3.3 V high-level voltage; when external voltage is input into the external voltage input end VBIS, a high-level signal at the moment is 1.8 V, and the driving voltage generating unit boosts and outputs the external voltage, so that the radio frequency switch can meet two input conditions of 1.8 V and 3.3 V, can meet the complex power supply environment of practical application, and ensures the radio frequency performance of the radio frequency switch.

Description

Technical Field

[0001] The utility model relates to the technical field of UWB power management, in particular to a UWB radio frequency switch power management circuit. Background Art

[0002] UWB (Ultra-wide Band), an ultra-wideband, is mainly used in the field of distance measurement and positioning. It is fully capable of measuring distance and position with an accuracy of 5 to 10 centimeters. In contrast, Bluetooth, Wi-Fi and other narrowband radio standards can only achieve meter-level accuracy. In addition, because UWB radio pulses are extremely short, under the multipath effect, the direct path signal will not overlap with the multipath signal, so the signal integrity and strength will not be damaged. The above surface UWB technology has the advantages of ultra-precision, ultra-reliability and real-time in practical applications.

[0003] In actual application, the UWB chip only needs a UWB switch to realize the antenna's transceiver function. Due to the ultra-wide frequency band and low transmission power of the UWB signal, the higher the power supply voltage input to the UWB chip, the lower the insertion loss of the UWB switch. At the same time, the higher the power supply voltage level, the better its harmonic performance.

[0004] In the current power management scheme of the existing UWB switch, the high and low level states of the signals CTL1 and CTL2 are mainly used to control the on and off of the RF channel of the UWB switch. At the same time, the high level signals in the signals CTL1 and CTL2 are also used as the power source of the RF channel. For the signals CTL1 and CTL2, the higher the high level voltage, the more conducive to improving the RF performance of the UWB switch. Generally, the high level is 3.3V.

[0005] However, in actual applications, the high-level voltage of 3.3V is relatively high, which will increase the resource consumption of the LDO output power supply. Therefore, the high-level voltage can only be provided to 1.8V in general, and the 1.8V voltage will affect the RF performance of the UWB switch. The existing power management solution is not compatible with both 1.8V and 3.3V voltage inputs. Utility Model Content

[0006] In view of the shortcomings of the background technology, the utility model provides a UWB radio frequency switch power management circuit, and the technical problem to be solved is that the power management circuit of the existing UWB switch is not compatible with 1.8V and 3.3V voltage inputs.

[0007] In order to solve the above technical problems, the utility model provides the following technical solutions: a UWB radio frequency switch power management circuit, comprising a first signal input terminal VCTL1, a second signal input terminal VCTL2, an external voltage input terminal VBIAS, a voltage selection unit, a clock generation unit, a driving voltage generation unit and a radio frequency channel switch unit;

[0008] The first signal input terminal VCTL1 is electrically connected to the voltage selection unit and the radio frequency channel switch unit respectively, and the second signal input terminal VCTL2 is electrically connected to the voltage selection unit and the radio frequency channel switch unit respectively;

[0009] The voltage selection unit is used to select a high-level signal from the signals input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2 for output, and the output signal is Vcon; one of the signals input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is in a high-level state and the other is in a low-level state;

[0010] The RF channel switch unit drives the corresponding RF channel to be turned on based on the signal input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2;

[0011] The external voltage input terminal VBIAS is electrically connected to the clock signal generating unit and the driving voltage generating unit, respectively; when an external voltage is input to the external voltage input terminal VBIAS, the clock signal generating unit inputs a clock signal CLK to the driving voltage generating unit, and after receiving the clock signal CLK, the driving voltage generating unit boosts the external voltage and outputs it, and the boosted voltage VMAX is input to the RF channel switch unit; when the clock signal CLK is not input, the driving voltage generating unit selects the voltage Vcon for output, and the output voltage VMAX is input to the RF channel switch unit.

[0012] In some implementations, the high level state includes 3.3V and 1.8V, and the external voltage is 1.8V;

[0013] When the high level of the signal inputted by the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is 3.3V, no external voltage is inputted to the external voltage input terminal VBIAS;

[0014] When the high level of the signal inputted by the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is 1.8V, the external voltage input terminal VBIAS has an external voltage input.

[0015] In some implementations, the voltage selection unit includes a resistor R1, a resistor R2, a resistor R3, and a resistor R4;

[0016] The first signal input terminal VCTL1 is electrically connected to one end of the resistor R2, one end of the resistor R3, the anode of the diode D1, the anode of the diode D2, the source of the MOS transistor M1 and the source of the MOS transistor M2 respectively;

[0017] The second signal input terminal VCTL2 is electrically connected to one end of the resistor R1, the other end of the resistor R4, the anode of the diode D3, the anode of the diode D4, the source of the MOS transistor M4 and the source of the MOS transistor M5 respectively;

[0018] The drain of the MOS tube M2 is electrically connected to the source of the MOS tube M3, the drain of the MOS tube M3 is electrically connected to the drain of the MOS tube M1, the cathode of the diode D1, the source of the MOS tube M7 and the source of the MOS tube M8, the drain of the MOS tube M8 is electrically connected to the source of the MOS tube M9, and the drain of the MOS tube M9 is electrically connected to the drain of the MOS tube M7 and the cathode of the diode D2;

[0019] The drain of the MOS tube M5 is electrically connected to the source of the MOS tube M6, the drain of the MOS tube M6 is electrically connected to the drain of the MOS tube M4, the cathode of the diode D3, the source of the MOS tube M10 and the source of the MOS tube M11 respectively, the drain of the MOS tube M11 is electrically connected to the source of the MOS tube M12, the drain of the MOS tube M12 is electrically connected to the drain of the MOS tube M10, the drain of the MOS tube M7 and the cathode of the diode D2 respectively, for outputting the voltage Vcon;

[0020] The other end of the resistor R3 is electrically connected to the other end of the resistor R4, the gate of the MOS tube M1 and the gate of the MOS tube M4 respectively; the other end of the resistor R1 is electrically connected to the gate of the MOS tube M2, the gate of the MOS tube M6, the gate of the MOS tube M8, the gate of the MOS tube M12 and the gate of the MOS tube M7 respectively; the other end of the resistor R2 is electrically connected to the gate of the MOS tube M3, the gate of the MOS tube M5, the gate of the MOS tube M9 and the gate of the MOS tube M11 respectively.

[0021] In some implementations, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11 and MOS tube M12 are all PMOS tubes.

[0022] In a certain embodiment, the driving voltage generating unit includes a suspension detection unit, a boost unit, a complementary clock generating unit and a MOS tube MP100;

[0023] The detection end of the floating detection unit is electrically connected to the external voltage input end VBIAS and grounded through the resistor R100. The output end of the floating detection unit is electrically connected to the gate of the MOS tube MP100. The source of the MOS tube MP100 is used for inputting the voltage Vcon. The drain of the MOS tube MP100 is electrically connected to the boost unit for outputting the voltage VMAX.

[0024] The clock signal CLK is input to the complementary clock generating unit, and the complementary clock generating unit outputs complementary clock signals CLK1 and CLK2 based on the clock signal; the boosting unit boosts the external voltage input to the external voltage input terminal VBIAS based on the clock signals CLK1 and CLK2.

[0025] In a certain implementation manner, the suspension detection unit includes a MOS transistor MP51, a MOS transistor MP52, a MOS transistor MP53, a MOS transistor MN51, and a MOS transistor MN52;

[0026] The source of the MOS transistor MP51 is electrically connected to the source of the MOS transistor MP52, the source of the MOS transistor MP53 and the driving voltage output terminal of the driving voltage generating unit respectively;

[0027] The gate of the MOS tube MP51 is electrically connected to the gate of the MOS tube MN51, which is the detection end of the suspension detection unit. The drain of the MOS tube MP51 is electrically connected to the drain of the MOS tube MP53, the drain of the MOS tube MN51, the gate of the MOS tube MP52 and the gate of the MOS tube MN52 respectively. The gate of the MOS tube MP53 is electrically connected to the drain of the MOS tube MP52 and the drain of the MOS tube MN52 respectively, which is the output end of the suspension detection unit. The source of the MOS tube MN51 and the source of the MOS tube MN52 are both grounded.

[0028] In a certain implementation manner, the boost unit includes a capacitor C100, a capacitor C101, a capacitor C102, a diode D100, a diode D101, a MOS transistor MN100, and a MOS transistor MN101;

[0029] One end of the capacitor C100 is electrically connected to the drain of the MOS transistor MP100, the cathode of the diode D100 and the cathode of the diode D101 respectively, the other end of the capacitor C100 is grounded, the anode of the diode D100 is electrically connected to the drain of the MOS transistor MN100, the gate of the MOS transistor MN101 and one end of the capacitor C102 respectively, the other end of the capacitor C102 is used to input the clock signal CLK2; the anode of the diode D101 is electrically connected to the drain of the MOS transistor MN101, the gate of the MOS transistor MN100 and one end of the capacitor C101 respectively, the other end of the capacitor C101 is used to input the clock signal CLK1; the source of the MOS transistor MN100 is electrically connected to the external voltage input terminal VBIAS and the MOS transistor MN101 respectively.

[0030] In some implementations, the MOS transistor MP100 is a PMOS transistor.

[0031] In some implementations, the MOS transistor MN100 is an NMOS transistor.

[0032] In some implementations, the MOS transistor MN101 is an NMOS transistor.

[0033] Compared with the prior art, the utility model has the following beneficial effects: in actual use, the utility model has two working modes, the high-level signal inputted by the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is inputted into the driving voltage generating unit; when there is no external voltage inputted to the external voltage input terminal VBIS, the high-level signal at this time is 3.3V, and the driving voltage generating unit outputs the high-level voltage of 3.3V; when there is an external voltage inputted to the external voltage input terminal VBIS, the high-level signal at this time is 1.8V, and the driving voltage generating unit outputs the external voltage by boosting the voltage, so that the utility model can meet the two input conditions of 1.8V and 3.3V, so that the utility model can meet the complex power supply environment of actual application, and ensure the radio frequency performance of the radio frequency switch. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 It is a schematic diagram of the structure of the utility model in the embodiment;

[0035] Figure 2 is a circuit diagram of a voltage selection unit in an embodiment;

[0036] Figure 3 is a circuit diagram of a driving voltage generating unit in an embodiment;

[0037] Figure 4 is a circuit diagram of a suspension detection unit in an embodiment. DETAILED DESCRIPTION

[0038] Now the utility model is further described in detail with reference to the accompanying drawings. These drawings are simplified schematic diagrams, which only illustrate the basic structure of the utility model in a schematic manner, and therefore only show the components related to the utility model.

[0039] like Figure 1 As shown, a UWB radio frequency switch power management circuit includes a first signal input terminal VCTL1, a second signal input terminal VCTL2, an external voltage input terminal VBIAS, a voltage selection unit 1, a clock generation unit 2, a driving voltage generation unit 3 and a radio frequency channel switch unit 4;

[0040] The first signal input terminal VCTL1 is electrically connected to the voltage selection unit 1 and the radio frequency channel switch unit 4 respectively, and the second signal input terminal VCTL2 is electrically connected to the voltage selection unit 1 and the radio frequency channel switch unit 4 respectively;

[0041] The voltage selection unit 1 is used to select a high-level signal from the signals input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2 for output, and the output signal is Vcon; one of the signals input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is in a high-level state and the other is in a low-level state;

[0042] The RF channel switch unit 4 drives the corresponding RF channel to be turned on based on the signal input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2;

[0043] The external voltage input terminal VBIAS is electrically connected to the clock signal generating unit 2 and the driving voltage generating unit 3 respectively; when an external voltage is input to the external voltage input terminal VBIAS, the clock signal generating unit 2 inputs the clock signal CLK to the driving voltage generating unit 3, and the driving voltage generating unit 3 boosts the external voltage after receiving the clock signal CLK, and the boosted voltage VMAX is input to the RF channel switch unit 4; when no clock signal CLK is input, the driving voltage generating unit 3 selects the voltage Vcon for output, and the output voltage VMAX is input to the RF channel switch unit.

[0044] Specifically, in this embodiment, the high level is determined by the external input power supply, which can be 3.3V voltage or 1.8V voltage, and the external voltage is 1.8V; wherein the utility model has the following two power input modes:

[0045] When the high level of the signal inputted by the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is 3.3V, no external voltage is inputted to the external voltage input terminal VBIAS;

[0046] When the high level of the signal inputted from the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is 1.8V, the external voltage input terminal VBIAS has an external voltage input.

[0047] In actual use, the utility model has two working modes, the high-level signal input from the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is input to the driving voltage generating unit 3; when there is no external voltage input to the external voltage input terminal VBIS, the high-level signal at this time is 3.3V, and the driving voltage generating unit 3 outputs a high-level voltage of 3.3V; when there is an external voltage input to the external voltage input terminal VBIS, the high-level signal at this time is 1.8V, and the driving voltage generating unit 3 boosts the external voltage and outputs it, so that the utility model can meet the two input conditions of 1.8V and 3.3V, so that the utility model can meet the complex power supply environment of actual application, and ensure the RF performance of the RF switch.

[0048] like Figure 2 As shown, in this embodiment, the voltage selection unit 1 includes a resistor R1, a resistor R2, a resistor R3 and a resistor R4;

[0049] The first signal input terminal VCTL1 is electrically connected to one end of the resistor R2, one end of the resistor R3, the anode of the diode D1, the anode of the diode D2, the source of the MOS transistor M1 and the source of the MOS transistor M2 respectively;

[0050] The second signal input terminal VCTL2 is electrically connected to one end of the resistor R1, the other end of the resistor R4, the anode of the diode D3, the anode of the diode D4, the source of the MOS transistor M4 and the source of the MOS transistor M5 respectively;

[0051] The drain of the MOS tube M2 is electrically connected to the source of the MOS tube M3, the drain of the MOS tube M3 is electrically connected to the drain of the MOS tube M1, the cathode of the diode D1, the source of the MOS tube M7 and the source of the MOS tube M8, the drain of the MOS tube M8 is electrically connected to the source of the MOS tube M9, and the drain of the MOS tube M9 is electrically connected to the drain of the MOS tube M7 and the cathode of the diode D2;

[0052] The drain of the MOS tube M5 is electrically connected to the source of the MOS tube M6, the drain of the MOS tube M6 is electrically connected to the drain of the MOS tube M4, the cathode of the diode D3, the source of the MOS tube M10 and the source of the MOS tube M11 respectively, the drain of the MOS tube M11 is electrically connected to the source of the MOS tube M12, the drain of the MOS tube M12 is electrically connected to the drain of the MOS tube M10, the drain of the MOS tube M7 and the cathode of the diode D2 respectively, for outputting the voltage Vcon;

[0053] The other end of the resistor R3 is electrically connected to the other end of the resistor R4, the gate of the MOS tube M1 and the gate of the MOS tube M4 respectively; the other end of the resistor R1 is electrically connected to the gate of the MOS tube M2, the gate of the MOS tube M6, the gate of the MOS tube M8, the gate of the MOS tube M12 and the gate of the MOS tube M7 respectively; the other end of the resistor R2 is electrically connected to the gate of the MOS tube M3, the gate of the MOS tube M5, the gate of the MOS tube M9 and the gate of the MOS tube M11 respectively.

[0054] In actual use, when the signal inputted by the first signal input terminal VCTL1 is at a high level and the signal inputted by the second signal input terminal VCTL2 is at a low level, the voltage source V1IP is at a low level state V and the voltage source V2IP is at a high level state. At this time, the MOS transistors M1 and M7 are turned on, the MOS transistors M4 and M10 are turned off, and the voltage Vcon is connected to the signal inputted by the first signal input terminal VCTL1; at the same time, the MOS transistors M2, M8, M12 or M6 in the substrate selection device are turned on, and the MOS transistors M3, M9, M11 or M5 are turned off, so as to ensure that the circuit works normally without leakage through the substrate. When the signal inputted by the first signal input terminal VCTL1 is at a low level and the signal inputted by the second signal input terminal VCTL2 is at a high level, the working conditions are similar to the above and will not be described in detail.

[0055] Specifically, in the present embodiment, MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11 and MOS tube M12 are all PMOS tubes.

[0056] Specifically, Figure 3 As shown, the driving voltage generating unit 3 includes a floating detection unit 30, a boost unit 31, a complementary clock generating unit 32 and a MOS tube MP100;

[0057] The detection end of the floating detection unit 30 is electrically connected to the external voltage input end VBIAS and grounded through the resistor R100. The output end of the floating detection unit 30 is electrically connected to the gate of the MOS tube MP100. The source of the MOS tube MP100 is used for inputting the voltage Vcon. The drain of the MOS tube MP100 is electrically connected to the boost unit 31 for outputting the voltage VMAX.

[0058] The clock signal CLK is input to the complementary clock generating unit 32, and the complementary clock generating unit 32 outputs complementary clock signals CLK1 and CLK2 based on the clock signal CLK, wherein when the clock signal CLK1 is at a high level, the clock signal CLK2 is at a low level, and when the clock signal CLK1 is at a low level, the clock signal CLK2 is at a high level; the boosting unit 31 boosts the external voltage input to the external voltage input terminal VBIAS based on the clock signals CLK1 and CLK2.

[0059] Specifically, Figure 4 As shown, in this embodiment, the suspension detection unit 30 includes a MOS transistor MP51, a MOS transistor MP52, a MOS transistor MP53, a MOS transistor MN51 and a MOS transistor MN52;

[0060] The source of the MOS transistor MP51 is electrically connected to the source of the MOS transistor MP52, the source of the MOS transistor MP53 and the driving voltage output terminal of the driving voltage generating unit respectively;

[0061] The gate of the MOS tube MP51 is electrically connected to the gate of the MOS tube MN51, which is the detection end of the floating detection unit. The drain of the MOS tube MP51 is electrically connected to the drain of the MOS tube MP53, the drain of the MOS tube MN51, the gate of the MOS tube MP52, and the gate of the MOS tube MN52 respectively. The gate of the MOS tube MP53 is electrically connected to the drain of the MOS tube MP52 and the drain of the MOS tube MN52 respectively, which is the output end of the floating detection unit. The source of the MOS tube MN51 and the source of the MOS tube MN52 are both grounded.

[0062] In addition, in the device size selection of the floating detection unit 30, the W / L of the MOS tube MP51 is much smaller than the W / L of the MOS tube MN51, so when the voltage VMAX is 3V and the input VBIAS is 1.8V, the DC current of the MOS tube MP51 / MOS tube MN51 is small, and the MOS tube MN51 pulls down to flip the logic judgment. Finally, the effect of the floating detection unit 30 is that when the external voltage input terminal VBIAS is suspended, the input voltage is pulled down by the internal pull-down resistor to zero, and the output VOUT of the floating detection unit is 0V; when the external voltage input terminal VBIAS is powered on at 1.8V, the output VOUT of the floating detection unit is VMAX=3V.

[0063] Specifically, in this embodiment, the MOS tube MP100 is a PMOS tube. In actual use, when the floating detection unit 30 detects that there is no external voltage connected to the external voltage input terminal VBIAS, the floating detection unit 30 inputs a low-level signal to the gate of the MOS tube MP100 to turn on the MOS tube MP100. At this time, the voltage Vcon is input to the RF channel switch unit 4 through the drain of the MOS tube MP100;

[0064] When the floating detection unit 30 detects that an external voltage is connected to the external voltage input terminal VBIAS, the floating detection unit 30 inputs a high level signal to the gate of the MOS tube MP100 to turn off the MOS tube MP100. At this time, the boost unit 31 boosts the external voltage and inputs it to the RF channel switch unit 4.

[0065] Specifically, in this embodiment, the boost unit 31 includes a capacitor C100, a capacitor C101, a capacitor C102, a diode D100, a diode D101, a MOS transistor MN100 and a MOS transistor MN101;

[0066] One end of the capacitor C100 is electrically connected to the drain of the MOS transistor MP100, the cathode of the diode D100 and the cathode of the diode D101 respectively, the other end of the capacitor C100 is grounded, the anode of the diode D100 is electrically connected to the drain of the MOS transistor MN100, the gate of the MOS transistor MN101 and one end of the capacitor C102 respectively, the other end of the capacitor C102 is used for inputting the clock signal CLK2; the anode of the diode D101 is electrically connected to the drain of the MOS transistor MN101, the gate of the MOS transistor MN100 and one end of the capacitor C101 respectively, the other end of the capacitor C101 is used for inputting the clock signal CLK1; the source of the MOS transistor MN100 is electrically connected to the external voltage input terminal VBIAS and the MOS transistor MN101 respectively.

[0067] In actual use, when an external voltage is input to the external voltage input terminal VBIAS, the MOS tube MP100 is not turned on, and the boost unit 31 boosts the external voltage based on the clock signal CLK1 and the clock signal CLK2, and the boosted voltage is input to the RF channel switch unit 4 through the drain of the MOS tube MP100.

[0068] In addition, in this embodiment, the MOS transistor MN100 and the MOS transistor MN101 are both NMOS transistors.

[0069] The above is based on the enlightenment of this utility model. Through the above description, relevant staff can make various changes and modifications without deviating from the technical idea of ​​this utility model. The technical scope of this utility model is not limited to the content in the specification, and its technical scope must be determined according to the scope of the claims.

Claims

1. A UWB radio frequency switch power management circuit, characterized in that: It includes a first signal input terminal VCTL1, a second signal input terminal VCTL2, an external voltage input terminal VBIAS, a voltage selection unit, a clock generation unit, a driving voltage generation unit and a radio frequency channel switch unit; The first signal input terminal VCTL1 is electrically connected to the voltage selection unit and the radio frequency channel switch unit respectively, and the second signal input terminal VCTL2 is electrically connected to the voltage selection unit and the radio frequency channel switch unit respectively; The voltage selection unit is used to select a high-level signal from the signals input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2 for output, and the output signal is a voltage Vcon; one of the signals input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is in a high-level state and the other is in a low-level state; The RF channel switch unit drives the corresponding RF channel to be turned on based on the signal input to the first signal input terminal VCTL1 and the second signal input terminal VCTL2; The external voltage input terminal VBIAS is electrically connected to the clock generating unit and the driving voltage generating unit respectively; when an external voltage is input to the external voltage input terminal VBIAS, the clock generating unit inputs a clock signal CLK to the driving voltage generating unit, and after receiving the clock signal CLK, the driving voltage generating unit boosts the external voltage and outputs the boosted voltage VMAX, which is input to the RF channel switch unit; When the clock signal CLK is not input, the driving voltage generating unit selects the voltage Vcon for output, and the output voltage VMAX is input to the RF channel switch unit.

2. A UWB radio frequency switch power management circuit according to claim 1, characterized in that: The high level state includes 3.3V and 1.8V, and the external voltage is 1.8V; When the high level of the signal inputted by the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is 3.3V, no external voltage is inputted to the external voltage input terminal VBIAS; When the high level of the signal inputted by the first signal input terminal VCTL1 and the second signal input terminal VCTL2 is 1.8V, the external voltage input terminal VBIAS has an external voltage inputted thereto.

3. A UWB radio frequency switch power management circuit according to claim 1, characterized in that: The voltage selection unit includes a resistor R1, a resistor R2, a resistor R3 and a resistor R4; the first signal input terminal VCTL1 is electrically connected to one end of the resistor R2, one end of the resistor R3, the anode of the diode D1, the anode of the diode D2, the source of the MOS tube M1 and the source of the MOS tube M2 respectively; The second signal input terminal VCTL2 is electrically connected to one end of the resistor R1, the other end of the resistor R4, the anode of the diode D3, the anode of the diode D4, the source of the MOS transistor M4 and the source of the MOS transistor M5 respectively; The drain of the MOS tube M2 is electrically connected to the source of the MOS tube M3, the drain of the MOS tube M3 is electrically connected to the drain of the MOS tube M1, the cathode of the diode D1, the source of the MOS tube M7 and the source of the MOS tube M8, the drain of the MOS tube M8 is electrically connected to the source of the MOS tube M9, and the drain of the MOS tube M9 is electrically connected to the drain of the MOS tube M7 and the cathode of the diode D2; The drain of the MOS tube M5 is electrically connected to the source of the MOS tube M6, the drain of the MOS tube M6 is electrically connected to the drain of the MOS tube M4, the cathode of the diode D3, the source of the MOS tube M10 and the source of the MOS tube M11 respectively, the drain of the MOS tube M11 is electrically connected to the source of the MOS tube M12, the drain of the MOS tube M12 is electrically connected to the drain of the MOS tube M10, the drain of the MOS tube M7 and the cathode of the diode D2 respectively, for outputting the voltage Vcon; The other end of the resistor R3 is electrically connected to the other end of the resistor R4, the gate of the MOS tube M1 and the gate of the MOS tube M4 respectively; the other end of the resistor R1 is electrically connected to the gate of the MOS tube M2, the gate of the MOS tube M6, the gate of the MOS tube M8, the gate of the MOS tube M12 and the gate of the MOS tube M7 respectively; the other end of the resistor R2 is electrically connected to the gate of the MOS tube M3, the gate of the MOS tube M5, the gate of the MOS tube M9 and the gate of the MOS tube M11 respectively.

4. A UWB radio frequency switch power management circuit according to claim 3, characterized in that: MOS tube M1, MOS tube M2, MOS tube M3, MOS tube M4, MOS tube M5, MOS tube M6, MOS tube M7, MOS tube M8, MOS tube M9, MOS tube M10, MOS tube M11 and MOS tube M12 are all PMOS tubes.

5. The UWB radio frequency switch power management circuit according to claim 1, characterized in that: The driving voltage generating unit includes a suspension detection unit, a boost unit, a complementary clock generating unit and a MOS tube MP100; The detection end of the floating detection unit is electrically connected to the external voltage input end VBIAS and grounded through a resistor R100. The output end of the floating detection unit is electrically connected to the gate of the MOS tube MP100. The source of the MOS tube MP100 is used for inputting the voltage Vcon. The drain of the MOS tube MP100 is electrically connected to the boost unit for outputting the voltage VMAX. The clock signal CLK is input to the complementary clock generating unit, and the complementary clock generating unit outputs complementary clock signals CLK1 and CLK2 based on the clock signal; the boosting unit boosts the external voltage input to the external voltage input terminal VBIAS based on the clock signals CLK1 and CLK2.

6. A UWB radio frequency switch power management circuit according to claim 5, characterized in that: The suspension detection unit includes a MOS tube MP51, a MOS tube MP52, a MOS tube MP53, a MOS tube MN51 and a MOS tube MN52; The source of the MOS transistor MP51 is electrically connected to the source of the MOS transistor MP52, the source of the MOS transistor MP53 and the driving voltage output terminal of the driving voltage generating unit respectively; The gate of the MOS tube MP51 is electrically connected to the gate of the MOS tube MN51, which is the detection end of the suspension detection unit. The drain of the MOS tube MP51 is electrically connected to the drain of the MOS tube MP53, the drain of the MOS tube MN51, the gate of the MOS tube MP52 and the gate of the MOS tube MN52 respectively. The gate of the MOS tube MP53 is electrically connected to the drain of the MOS tube MP52 and the drain of the MOS tube MN52 respectively, which is the output end of the suspension detection unit. The source of the MOS tube MN51 and the source of the MOS tube MN52 are both grounded.

7. A UWB radio frequency switch power management circuit according to claim 5, characterized in that: The boost unit includes a capacitor C100, a capacitor C101, a capacitor C102, a diode D100, a diode D101, a MOS transistor MN100 and a MOS transistor MN101; one end of the capacitor C100 is electrically connected to the drain of the MOS transistor MP100, the cathode of the diode D100 and the cathode of the diode D101 respectively, the other end of the capacitor C100 is grounded, the anode of the diode D100 is electrically connected to the drain of the MOS transistor MN100, the gate of the MOS transistor MN101 and one end of the capacitor C102 respectively, and the other end of the capacitor C102 is used to input the clock signal CLK2; the anode of the diode D101 is electrically connected to the drain of the MOS transistor MN101, the gate of the MOS transistor MN100 and one end of the capacitor C101 respectively, and the other end of the capacitor C101 is used to input the clock signal CLK1; the source of the MOS transistor MN100 is electrically connected to the external voltage input terminal VBIAS and the MOS transistor MN101 respectively.

8. A UWB radio frequency switch power management circuit according to claim 7, characterized in that: The MOS tube MP100 is a PMOS tube.

9. A UWB radio frequency switch power management circuit according to claim 7, characterized in that: The MOS tube MN100 is an NMOS tube.

10. A UWB radio frequency switch power management circuit according to claim 7, characterized in that: The MOS tube MN101 is an NMOS tube.

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