Plug device and mainboard

Abstract

The embodiment of the utility model provides a plugging device and mainboard, the plugging device is connected with an FPGA chip, the plugging device is provided with at least one group of external interfaces, each group of external interfaces comprises at least one slot, and a to-be-identified card group is correspondingly plugged with the slots in the external interfaces, so that after the FPGA chip receives an identification signal sent by the plugging device, the to-be-identified card group receives the identification signal sent by the plugging device, and the to-be-identified card group sends the identification signal to the mainboard. Determining the type of the external interface and the position of the slot into which the to-be-identified card group is inserted according to the identification signal; wherein the identification signal has a corresponding relationship with the position and the shape of the slot.

Description

Technical Field

[0001] The utility model relates to the technical field of computers, in particular to a plug-in device and a mainboard. Background Art

[0002] The motherboard of an electronic device is generally provided with a variety of different data interfaces or data buses, such as a high-speed serial computer expansion bus standard peripheral component interconnect express (PCIe) slot. The central processing unit (CPU) can exchange data with different devices and hardware through the PCIe slot.

[0003] Currently, the number of PCIe slots on a motherboard can be expanded by inserting an expansion slot adapter card (Riser card) on the motherboard. However, since a large number of slots are provided on the motherboard for inserting the Riser card, when the Riser card is inserted, it is difficult for the motherboard to identify which slot the Riser card is inserted into. Utility Model Content

[0004] The utility model mainly provides a plug-in device and a mainboard, which can enable the mainboard to automatically determine the position of the card group to be identified and the type of the external interface, so as to facilitate the mainboard to realize accurate management of the PCIe slot and the inserted card group.

[0005] The technical solution of the utility model is achieved in this way:

[0006] In a first aspect, an embodiment of the utility model provides a plug-in device, which is connected to an FPGA chip, and is provided with at least one set of external interfaces, each set of external interfaces includes at least one slot, wherein:

[0007] The card group to be identified is correspondingly plugged into the slot in the external interface, so that after the FPGA chip receives the identification signal sent by the plug-in device, it determines the type of the external interface and the position of the slot into which the card group to be identified is inserted according to the identification signal; wherein the identification signal has a corresponding relationship with the position and shape of the slot.

[0008] In a second aspect, an embodiment of the utility model provides a mainboard, comprising a plug-in device and an FPGA chip as described in the first aspect, wherein the plug-in device and the FPGA chip are connected, and the plug-in device is provided with at least one set of external interfaces, and each set of external interfaces includes at least one slot, wherein:

[0009] The card group to be identified is correspondingly plugged into the slot in the external interface;

[0010] The FPGA chip is used to determine the type of the external interface and the position of the slot into which the card group to be identified is inserted according to the identification signal after receiving the identification signal sent by the plug-in device;

[0011] The identification signal corresponds to the position and shape of the slot.

[0012] The utility model provides a plug-in device and a mainboard. After a card group to be identified is connected to the mainboard through a slot on the plug-in device, the plug-in device generates an identification signal based on the slot into which the card group to be identified is inserted, and sends it to an FPGA chip, so that the FPGA chip can automatically determine the position of the slot into which the card group to be identified is inserted, and the type of the external interface. In this way, the mainboard can realize accurate management of the PCIe slot and the inserted card group. BRIEF DESCRIPTION OF THE DRAWINGS

[0013] Figure 1 A schematic diagram of the structure of a mainboard;

[0014] Figure 2 A schematic diagram of the structure of a plug-in device provided in an embodiment of the utility model;

[0015] Figure 3 A schematic diagram of the structure of a card to be identified provided in an embodiment of the utility model Figure 1 ;

[0016] Figure 4 A schematic diagram of the structure of a card to be identified provided in an embodiment of the utility model Figure 2 ;

[0017] Figure 5 A schematic diagram of the structure of a first type of card group to be identified provided in an embodiment of the utility model Figure 1 ;

[0018] Figure 6 A schematic diagram of the structure of a first type of card group to be identified provided in an embodiment of the utility model Figure 2 ;

[0019] Figure 7 A schematic diagram of the structure of a first type of card group to be identified provided in an embodiment of the utility model Figure 3 ;

[0020] Figure 8 A schematic diagram of the structure of a second type of card group to be identified provided in an embodiment of the utility model Figure 1 ;

[0021] Fig. 9 A schematic diagram of the structure of a second type of card group to be identified provided in an embodiment of the utility model Figure 2 ;

[0022] Fig.10A schematic diagram of the rear side of a server provided by an embodiment of the utility model;

[0023] Fig.11 A schematic diagram of the front side of a server provided by an embodiment of the utility model;

[0024] Fig.12 A schematic diagram of a first type of external interface provided by an embodiment of the utility model Figure 1 ;

[0025] Fig.13 A schematic diagram of a first type of external interface provided by an embodiment of the utility model Figure 2 ;

[0026] Fig.14 A schematic diagram of a second type of external interface provided by an embodiment of the utility model Figure 1 ;

[0027] Fig.15 A schematic diagram of a second type of external interface provided by an embodiment of the utility model Figure 2 ;

[0028] Fig.16 A schematic diagram of a third type of external interface provided by an embodiment of the utility model Figure 1 ;

[0029] Fig.17 A schematic diagram of a third type of external interface provided by an embodiment of the utility model Figure 2 ;

[0030] Fig.18 A schematic diagram of a first type of external interface provided by an embodiment of the utility model Figure 3 ;

[0031] Fig.19 A schematic diagram of a second type of external interface provided by an embodiment of the utility model Figure 3 ;

[0032] Fig. 20 A schematic diagram of a third type of external interface provided by an embodiment of the utility model Figure 3 ;

[0033] Fig.21 A schematic diagram of the structure of a mainboard provided in an embodiment of the utility model Figure 1 ;

[0034] Fig. 22 A schematic diagram of the structure of a mainboard provided in an embodiment of the utility model Figure 2 . DETAILED DESCRIPTION

[0035] In order to more thoroughly understand the features and technical contents of the embodiments of the present invention, the implementation of the embodiments of the present invention is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not intended to limit the embodiments of the present invention.

[0036] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art in the field of the present invention. The terms used herein are only for the purpose of describing the embodiments of the present invention and are not intended to limit the present invention.

[0037] In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

[0038] It should also be pointed out that the terms "first\second\third" involved in the embodiments of the present invention are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present invention described here can be implemented in an order other than that illustrated or described here.

[0039] Electronic devices, such as computer hosts or servers, can insert various function cards, such as network cards, graphics cards, sound cards, hard disks, etc., through the PCIe slots on the motherboard. However, due to the compact layout inside the server, the PCIe slots are too close to other components, and the function cards cannot be directly inserted into the PCIe slots; or due to the design structure limitations of the server itself, the server cannot be closed after a longer function card is inserted into the motherboard. In this case, the riser card can be inserted into the motherboard slot on the motherboard, and the riser card can be fixed to the motherboard with a special iron frame. Each riser card provides 1 or more standard PCIe slots. In this way, the riser card can be used to expand the PCIe slot to a position that is more suitable for inserting expansion cards, thereby improving the expansion capability and performance of the server.

[0040] Figure 1 The figure is a schematic diagram of the structure of a motherboard. At present, the motherboard of a server generally provides multiple motherboard slots for inserting riser cards. A riser card needs to be connected to a PCIe interface and a PWR / SB interface on the motherboard to work properly. Figure 1As shown in the figure, in a 2U server, 10 groups of interfaces including PCIe interfaces and PWR / SB interfaces are set on the mainboard. The PCIe interfaces included in the same group of interfaces may be adjacent to the PWR / SB interfaces or may not be adjacent. The dotted arrow indicates that the mainboard provides the PWR / SB interface to the riser card, and the solid arrow indicates that the mainboard provides the corresponding PCIe interface to the riser card, or it may indicate that the mainboard provides a group of interfaces including PCIe interfaces and PWR / SB interfaces to the riser card. In this way, after the riser card is inserted into the mainboard, the 10 expanded PCIe slots on the riser card can be connected to the mainboard. Since the PWR / SB connectors in the adjacent areas are all connected to the same bus and then connected to the processor, and the same model of riser cards use the same printed circuit board (PCB), although the CPU or field programmable gate array (FPGA) and other processors can identify the model of the inserted riser card and which motherboard slot the riser card is inserted into by checking the vital product data (VPD) of the inserted riser card, when a riser card expansion device capable of inserting a group of riser cards is inserted into the same motherboard slot, the processor cannot identify how many riser cards are inserted into the riser card expansion device and the specific insertion position. This is not conducive to the processor management and use of various function cards connected to the PCIe slot, and reduces the management efficiency of the processor.

[0041] Based on the problem that the processor cannot identify the insertion position of the riser card, the embodiment of the utility model provides a plug-in device and a motherboard. After the card group to be identified is connected to the motherboard through the slot on the plug-in device, the plug-in device generates an identification signal based on the slot where the card group to be identified is inserted, and sends it to the FPGA chip, so that the FPGA chip can automatically determine the position of the slot where the card group to be identified is inserted, and the type of the external interface. In this way, it is convenient for the motherboard to realize accurate management of the PCIe slot and the inserted card group.

[0042] The present invention is further described in detail below through the accompanying drawings and specific embodiments.

[0043] In one embodiment of the present invention, Figure 2 The present invention provides a schematic diagram of the structure of a plug-in device. The plug-in device can be connected to an FPGA chip, such as Figure 2 As shown, the plug-in device 10 is provided with at least one group of external connection interfaces, and each group of external connection interfaces includes at least one slot.

[0044] In the embodiment of the utility model, the plug-in device 10 can be a special iron frame, one end of which matches the motherboard slot on the motherboard. After being inserted into the motherboard through the motherboard slot, it communicates with the FPGA chip through the bus between the motherboard slot and the FPGA chip; a group of external interfaces are set at the other end of the plug-in device 10, and each group of external interfaces includes at least one slot, for example, Figure 2 As shown, the plug-in device may include a first group of external interfaces 101, ..., a Qth group of external interfaces 102, wherein the first group of external interfaces 101 includes a first slot a1, ..., an Nth slot a2; the Qth group of external interfaces 102 includes an Mth slot a3, ..., a Wth slot a4. It should be noted that multiple slots in the same group of external interfaces can be inserted into the motherboard through the same motherboard slot, and different groups of external interfaces can be connected by structural members or supporting components, or can be independent of each other.

[0045] In the embodiment of the utility model, the FPGA chip can be a processor arranged on a mainboard, and a mainboard slot is provided on the mainboard for inserting the plug-in device, and the mainboard slot is connected to the FPGA chip through a bus, thereby realizing the communication connection between the slot on the plug-in device and the FPGA chip. It should be noted that the plug-in device can also be connected to other processors with processing functions on the mainboard.

[0046] In an embodiment of the utility model, the card group to be identified is plugged into the slot in the external interface accordingly, so that after the FPGA chip receives the identification signal sent by the plug-in device, it determines the type of the external interface and the position of the slot into which the card group to be identified is inserted according to the identification signal.

[0047] The identification signal corresponds to the position and shape of the slot.

[0048] For example, Figure 3 A schematic diagram of the structure of a card to be identified provided in an embodiment of the utility model Figure 1 , Figure 4 A schematic diagram of the structure of a card to be identified provided in an embodiment of the utility model Figure 2 The card to be identified may be a riser card. Figure 3 The figure shows a schematic diagram of a riser card model Riser 4, which is a universal type suitable for a standard PWR connector. Figure 4 The figure shows a schematic diagram of a Riser card model Riser 7, which is a type of Riser card suitable for the GPU-PWR connector. It can be understood that Figure 3 and Figure 4This is just an example, and the riser card can also include other multiple types. The user can select one or more riser cards of the same type or different types as needed to form a card group to be identified, and the card group to be identified can be fixed on the plug-in device.

[0049] It should be noted that each slot in the external interface may be composed of at least one contact pin, and can be correspondingly plugged with one or more cards to be identified in the card group to be identified.

[0050] Moreover, for slots in different positions, the number of contact pins contained in the slots, the position arrangement of the contact pins and other characteristics are different, so that after the card to be identified in the card group is inserted into one of the slots on the plug-in device, different identification signals can be generated. The identification signal is associated with the slot on the plug-in device where the card to be identified is inserted, and the generated identification signal can mark the position of this slot to the FPGA chip.

[0051] After the card group to be identified is inserted, after the FPGA chip receives the above identification signal, it can first determine which motherboard slot the identification signal comes from based on the location where the identification signal is sent. On this basis, the above identification signal is analyzed to determine the location of each card to be identified in the card group to be identified in the slot where the plug-in device is plugged in, and the type of external interface of the current plug-in device plugged in the card group to be identified. It should be noted that the number of slots contained in different types of external interfaces and the shape of the slots can be different.

[0052] Furthermore, the FPGA chip can also detect the VPD of each card to be identified in the inserted card group to be identified, and determine the model of the inserted card to be identified, such as the riser card of the model Riser 4 or the riser card of the model Riser 7.

[0053] The embodiment of the utility model provides a plug-in device. After the card group to be identified is connected to the mainboard through the slot on the plug-in device, the plug-in device generates an identification signal based on the slot where the card group to be identified is inserted, and sends it to the FPGA chip, so that the FPGA chip can automatically determine the position of the slot where the card group to be identified is inserted, and the type of the external interface. In this way, it is convenient for the mainboard to realize accurate management of the PCIe slot and the inserted card group.

[0054] In another embodiment of the present invention, the types of the card groups to be identified may include: a first type of card group to be identified, the first type of card group to be identified includes three cards to be identified; a second type of card group to be identified, the second type of card group to be identified includes two cards to be identified.

[0055] In the embodiment of the present utility model, it should be noted that the type of the card group to be identified can also be determined based on a preset rule according to the number or type of riser cards included in the card group to be identified.

[0056] For example, Figure 5 A schematic diagram of the structure of a first type of card group to be identified provided in an embodiment of the utility model Figure 1 .like Figure 5 As shown, the first type of card group to be identified may include three riser cards arranged in sequence, and the three riser cards may be two riser cards of model Riser 4 and one riser card of model Riser 1 from top to bottom.

[0057] Or, illustratively, Figure 6 A schematic diagram of the structure of a first type of card group to be identified provided in an embodiment of the utility model Figure 2 .like Figure 6 As shown, in another optional implementation, the first type of card group to be identified may include three riser cards arranged in sequence, and the three riser cards may be two riser cards of model Riser 7 and one riser card of model Riser 4 from top to bottom.

[0058] Or, illustratively, Figure 7 A schematic diagram of the structure of a first type of card group to be identified provided in an embodiment of the utility model Figure 3 .like Figure 7 As shown, in another optional implementation, the first type of card group to be identified may include three riser cards arranged in sequence, and the three riser cards may be two riser cards of model Riser 7 and one riser card of model Riser 1 from top to bottom.

[0059] Understandably, Figure 5 , Figure 6 , Figure 7 These are just two examples of the first type of card group to be identified. In actual application, the models of the three riser cards included in the first type of card group to be identified can be the same, partially the same, or completely different, and the arrangement of the three riser cards is not specifically limited.

[0060] It should be noted that the first type of card group to be identified refers to a card group containing at most 3 riser cards. The plug-in device corresponding to the first type of card group to be identified must include at least 3 slots, wherein the 3 slots are used to plug in correspondingly to the three riser cards respectively.

[0061] For example, Figure 8 A schematic diagram of the structure of a second type of card group to be identified provided in an embodiment of the utility model Figure 1 .like Figure 8As shown, the second type of card group to be identified may also include two riser cards arranged in sequence, and the two riser cards may include a riser card of model Riser 7 and a riser card of model Riser 1.

[0062] Or, illustratively, Fig. 9 A schematic diagram of the structure of a second type of card group to be identified provided in an embodiment of the utility model Figure 2 .like Fig. 9 As shown, in another optional implementation manner, the second type of card group to be identified may include two riser cards arranged in sequence, and the two riser cards may include two riser cards of model Riser4.

[0063] See also Figure 8 , Fig. 9 It can be understood that the two riser cards in the second type of card group to be identified may be plugged into Figure 8 The external interface includes three slots, which may be plugged into Fig. 9 The external interface shown includes two slots. The number of slots included in the external interface may be associated with the position of the external interface group on the plug-in device. The number of contact pins included in the slots and the arrangement of the contact pins are associated with the position of the external interface and the position of the slots.

[0064] The embodiment of the utility model provides a plug-in device, which can be inserted into a first type of card group to be identified or a second type of card group to be identified. A user can select the card group to be identified to be inserted according to actual needs, thereby improving the flexibility and scalability of the plug-in device.

[0065] In yet another embodiment of the present invention, at least one group of external interfaces includes at least one of a first type of external interface, a second type of external interface, and a third type of external interface.

[0066] The first type of external interface includes a first slot, a second slot and a third slot.

[0067] The second type of external interface includes a fourth slot and a fifth slot.

[0068] The third type of external interface includes a sixth slot and a seventh slot.

[0069] Among them, the shape of the first slot, the shape of the second slot, the shape of the third slot, the shape of the fourth slot, the shape of the fifth slot, the shape of the sixth slot and the shape of the seventh slot are all different.

[0070] As mentioned above, different external interfaces may contain different numbers of slots, and the shapes of the slots, that is, the number and arrangement of contact pins contained in the slots may also be different accordingly. The shape is related to the position of the external interface in the server and the position of the slot in the external interface.

[0071] Fig.10 A schematic diagram of the rear side of a server provided by an embodiment of the utility model. Fig.10 As shown, four motherboard slots are provided on the motherboard in the rear area of ​​the server, which can be used to insert a plug-in device with four sets of external interfaces, or four plug-in devices each with a set of external interfaces. Among them, each SLOT represents a PCIe slot provided by the Riser card after the Riser card is inserted, which can be inserted with various functional cards. In the embodiment of the utility model, SLOT1 (PCIe slot 1) and SLOT2 (PCIe slot 2) indicate that the height at this place can only allow the external interface of the plug-in device to include 2 slots, and at most two Riser cards can be inserted, providing two PCIe slots SLOT1 and SLOT2; SLOT9 (PCIe slot 9) and SLOT10 (PCIe slot 10) are similar, and the height can only allow the external interface of the plug-in device to include 2 slots, and at most two Riser cards can be inserted. The positions of the three PCIe slots SLOT3 (PCIe slot 3), SLOT4 (PCIe slot 4), and SLOT5 (PCIe slot 5) can only allow the external interface of the plug-in device to include three slots, and two or three riser cards can be inserted, corresponding to the provision of two or three PCIe slots; similarly, the positions of the three PCIe slots SLOT6 (PCIe slot 6), SLOT7 (PCIe slot 7), and SLOT8 (PCIe slot 8) can only allow the external interface of the plug-in device to include three slots, and two or three riser cards can be inserted, corresponding to the provision of two or three PCIe slots. SLOT13 (PCIe slot 13) and SLOT14 (PCIe slot 14) are PCIe slots provided after other single riser cards are inserted.

[0072] Fig.11 A schematic diagram of the front side of a server provided by an embodiment of the utility model. Fig.11 As shown, a motherboard slot is provided on the motherboard in the front area of ​​the server, which can be used to insert a plug-in device with a set of external interfaces. Among them, SLOT11 (PCIe slot 11) and SLOT12 (PCIe slot 12) indicate that the height of the location only allows the external interface of the plug-in device to include 2 slots, and at most two riser cards can be inserted, providing two PCIe slots, SLOT11 and SLOT12. SLOT15 (PCIe slot 15) indicates the PCIe slot provided after the insertion of another single riser card.

[0073] In this way, the external interface can be connected to Fig.10 The server shown in the figure is connected to the two middle motherboard slots on the back side. After three Riser cards are inserted into the slot of the external interface, three PCIe slots, SLOT3, SLOT4, and SLOT5, or external interfaces for the three PCIe slots, SLOT6, SLOT7, and SLOT8, are provided. These are called the first type of external interfaces. Connect the external interface to Fig.10 The two motherboard slots on both sides of the rear side of the server shown in the figure are connected. After two Riser cards are inserted into the slot of the external interface, two PCIe slots SLOT1 and SLOT2 are provided, or two PCIe slots SLOT9 and SLOT10 are provided. The external interface is called the second type of external interface. Fig.11 The motherboard slot connection on the front side of the server shown in the figure provides external interfaces for two PCIe slots, SLOT11 and SLOT12, after two Riser cards are inserted into the slots of the external interface, which are called the third type of external interface.

[0074] In the embodiment of the utility model, the structure formed after the card group to be identified is inserted into the external interface of the plug-in device can also be called Cage. For the plug-in device of the first type of external interface inserted into the first type of card group to be identified or the second type of card group to be identified, which provides any one of the two groups of PCIe slots SLOT3 to SLOT5 or SLOT6 to SLOT8, its type can be marked as Cage1; for the plug-in device of the second type of external interface inserted into the second type of card group to be identified, which provides any one of the two groups of PCIe slots SLOT1, SLOT2 or SLOT9, SLOT10, its type can be marked as Cage2; for the plug-in device of the third type of external interface inserted into the second type of card group to be identified, which provides the two PCIe slots SLOT11, SLOT12, its type can be marked as Cage3.

[0075] The embodiment of the utility model provides a plug-in device, wherein the shapes of the slots included in the external interfaces at different positions are all different. Thus, after the Riser card is inserted, the identification signal generated is also correspondingly different, so that the FPGA chip can determine the position of the slot where the card group to be identified is inserted according to the identification signal.

[0076] In another embodiment of the present invention, Fig.12 A schematic diagram of a first type of external interface provided by an embodiment of the utility model Figure 1 , Fig.13 A schematic diagram of a first type of external interface provided by an embodiment of the utility model Figure 2 .like Fig.12 , Fig.13As shown, the connection end of the card to be identified includes a first pin, a second pin, a third pin and a fourth pin.

[0077] In an embodiment of the utility model, each card to be identified, i.e., a riser card, may include four pins (touch pins) arranged in sequence from top to bottom, and a slot in the external interface is also provided with at least one touch pin, and a position where no touch pin is provided also reserves a position after the pin is inserted, and the position reserved by each slot is slightly larger than the position occupied by the four pins of the card to be identified, so that even if the slot includes one or two touch pins, the card to be identified can still be inserted into the slot and fixed on the plug-in device.

[0078] The first slot 1031 includes four contact pins corresponding to the plugging positions of the first pin, the second pin, the third pin and the fourth pin respectively.

[0079] The second slot 1032 includes three contact pins corresponding to the insertion positions of the first pin, the second pin and the fourth pin respectively;

[0080] The third slot 1033 includes three contact pins corresponding to the positions of the first pin, the second pin and the third pin respectively.

[0081] like Fig.12 , Fig.13 As shown, in order to identify which slot of the first type of external interface has the card to be identified inserted into, 4 pins are set on the card to be identified. At the same time, different numbers and arrangements of contact pins are set on the slot of the first type of external interface. When the pin of the card to be identified contacts the contact pin, it is grounded, which enables the plug-in device to generate a signal with a level state of 0. When the position where the pin of the card to be identified is plugged in is not provided with a contact pin, the plug-in device can generate a signal with a level state of 1. In this way, after the card to be identified is inserted into the first slot 1031, the second slot 1032, and the third slot 1033 with different numbers and positions of contact pins, it can generate identification signals with different codes, marking the position of the slot and the type of the external interface to the FPGA chip.

[0082] Moreover, as mentioned above, the FPGA chip can identify which motherboard slot the identification signal comes from, that is, where the external interface is inserted into the server, but it cannot identify what type of external interface is inserted and the position of the card to be identified in the slot.

[0083] Thus, illustratively, for the first slot 1031, it can be set to include 4 contact pins arranged in sequence. After the card to be identified is inserted, the 4 pins of the card to be identified are plugged into the 4 contact pins in sequence, and the identification signals generated in sequence from the first pin ID to the fourth pin ID contain the code 0000, indicating that the external interface is a first-type identification interface including 3 slots, and the card to be identified is inserted into the first slot 1031; for the second slot 1032, 3 contact pins can be set at the corresponding plug-in positions of the first pin, the second pin, and the fourth pin of the card to be identified. After the card to be identified is inserted, the first pin, the second pin, and the fourth pin of the card to be identified are plugged into the 3 contact pins respectively, and the first pin ID to the fourth pin ID are connected to the corresponding positions of the first pin, the second pin, and the fourth pin of the card to be identified. The identification signal generated in sequence by the fourth pin ID includes a code of 0001, indicating that the external interface is a first-type identification interface including three slots, and the card to be identified is inserted into the second slot 1032; accordingly, for the third slot 1033, three contact pins can be set at the corresponding positions of the first pin, the second pin and the third pin of the card to be identified. After the card to be identified is inserted, the first pin, the second pin and the third pin of the card to be identified are respectively connected with the three contact pins, and the identification signal generated in sequence by the first pin ID to the fourth pin ID includes a code of 0010, indicating that the external interface is a first-type identification interface including three slots, and the card to be identified is inserted into the third slot 1033.

[0084] It should be noted that the cards to be identified can be inserted into the three slots at the same time, or one or two of the slots can be inserted into the card to be identified. When the card to be identified is inserted into each slot, different identification signals can be generated in real time based on the shape of the slot and sent to the FPGA chip.

[0085] In some embodiments, Fig.14 A schematic diagram of a second type of external interface provided by an embodiment of the utility model Figure 1 , Fig.15 A schematic diagram of a second type of external interface provided by an embodiment of the utility model Figure 2 .like Fig.14 , Fig.15 As shown, the connection end of the card to be identified includes a first pin, a second pin, a third pin and a fourth pin.

[0086] The fourth slot 1041 includes three contact pins corresponding to the positions of the first pin, the second pin and the third pin respectively.

[0087] The fifth slot 1042 includes two contact pins corresponding to the insertion positions of the first pin and the third pin respectively.

[0088] like Fig.14 , Fig.15As shown, in order to identify which slot of the second type external interface has the card to be identified inserted into, 4 pins arranged in sequence are set on each card to be identified, and at the same time, different numbers and arrangements of contact pins are set on the slot of the second type external interface. When the pin of the card to be identified contacts the contact pin, it is grounded, and the plug-in device can generate a signal with a level state of 0. When the position where the pin of the card to be identified is plugged in is not provided with a contact pin, the plug-in device can generate a signal with a level state of 1. In this way, after the card to be identified is inserted into the fourth slot 1041 and the fifth slot 1042 with different numbers and positions of contact pins, it can generate identification signals with different codes, marking the position of the slot and the type of the external interface to the FPGA chip.

[0089] Thus, illustratively, for the fourth slot 1041, three contact pins may be provided at the corresponding plug-in positions of the first pin, the second pin and the third pin of the card to be identified. After the card to be identified is inserted, the first pin, the second pin and the third pin of the card to be identified are respectively plugged into the three contact pins, so that the identification signals sequentially generated by the first pin ID to the fourth pin ID contain a code of 0100, indicating that the external interface is a second type of identification interface including two slots and connected to the rear side of the mainboard in the server, and the card to be identified is inserted into the fourth slot 1041; for the fifth slot 1042, two contact pins may be provided at the corresponding plug-in positions of the first pin and the third pin of the card to be identified. After the card to be identified is inserted, the first pin and the third pin of the card to be identified are respectively plugged into the two contact pins, and the identification signals sequentially generated by the first pin ID to the fourth pin ID contain a code of 0101, indicating that the external interface is a second type of identification interface including two slots and connected to the rear side of the mainboard in the server, and the card to be identified is inserted into the fifth slot 1042.

[0090] In some embodiments, Fig.16 A schematic diagram of a third type of external interface provided by an embodiment of the utility model Figure 1 , Fig.17 A schematic diagram of a third type of external interface provided by an embodiment of the utility model Figure 2 .like Fig.16 , Fig.17 As shown, the connection end of the card to be identified includes a first pin, a second pin, a third pin and a fourth pin.

[0091] The sixth slot 1051 includes three contact pins corresponding to the insertion positions of the first pin, the third pin and the fourth pin respectively.

[0092] The seventh slot 1052 includes two contact pins corresponding to the insertion positions of the first pin and the fourth pin respectively.

[0093] like Fig.16 , Fig.17As shown, in order to identify which slot of the third type external interface has the card to be identified inserted into, 4 pins arranged in sequence are set on each card to be identified. At the same time, different numbers and arrangements of contact pins are set on the slot of the third type external interface. When the pin of the card to be identified contacts the contact pin, it is grounded, and the plug-in device can generate a signal with a level state of 0. When the position where the pin of the card to be identified is plugged in is not provided with a contact pin, the plug-in device can generate a signal with a level state of 1. In this way, after the card to be identified is inserted into the sixth slot 1051 and the seventh slot 1052 with different numbers and positions of contact pins, it can generate identification signals with different codes, marking the position of the slot and the type of the external interface to the FPGA chip.

[0094] Thus, illustratively, for the sixth slot 1051, three contact pins may be provided at the plugging positions of the first pin, the third pin and the fourth pin of the card to be identified, and after the card to be identified is inserted, the first pin, the third pin and the fourth pin of the card to be identified are plugged correspondingly with the three contact pins, respectively, and the identification signals sequentially generated by the first pin ID to the fourth pin ID contain a code of 1000, indicating that the external interface is a third type of identification interface including two slots, connected to the front side of the mainboard in the server, and the card to be identified is inserted into the sixth slot 1051; for the seventh slot 1052, two contact pins may be provided at the plugging positions of the first pin and the fourth pin of the card to be identified, and after the card to be identified is inserted, the first pin and the fourth pin of the card to be identified are plugged correspondingly with the two contact pins, and the identification signals sequentially generated by the first pin ID to the fourth pin ID contain a code of 1001, indicating that the external interface is a third type of identification interface including two slots, connected to the front side of the mainboard in the server, and the card to be identified is inserted into the seventh slot 1052.

[0095] The embodiment of the utility model provides a plug-in device, wherein the first type of external interface includes a first slot, a second slot and a third slot with different numbers and positions of contact pins, the second type of external interface includes a fourth slot and a fifth slot with different numbers and positions of contact pins, and the third type of external interface includes a sixth slot 1051 and a seventh slot 1052 with different numbers and positions of contact pins. Through this structure, a mechanism for FPGA chip to identify the card to be identified with the same PCB can be realized, so that the FPGA chip can determine the type of the inserted external interface and the position where the card to be identified is inserted, and the flexibility of the plug-in device is also improved.

[0096] In another embodiment of the utility model, the identification signal includes a four-digit identification code, wherein the first two digits of the four-digit identification code are used to indicate the type of the external interface; and the last two digits of the four-digit identification code are used to indicate the position of the slot into which the card group to be identified is inserted.

[0097] In the embodiment of the present utility model, Fig.18A schematic diagram of a first type of external interface provided by an embodiment of the utility model Figure 3 ; Fig.19 A schematic diagram of a second type of external interface provided by an embodiment of the utility model Figure 3 ; Fig. 20 A schematic diagram of a third type of external interface provided by an embodiment of the utility model Figure 3 The arrows in the figure indicate that after the card to be identified is inserted into the slot, the pin pointed by the arrow contacts the contact pin, and its level state is 0, and the pin not pointed by the arrow does not contact the contact pin, and its level state is 1.

[0098] like Fig.18 , Fig.19 , Fig. 20 As shown, for a slot capable of inserting 4 pins, regardless of whether contact pins are provided at the corresponding positions of the pins, the positions where the 4 pins are inserted in the slot, ie, the first pin ID to the fourth pin ID, can be encoded in sequence into a four-digit identification code.

[0099] The first pin ID (CageID0) and the second pin ID (CageID1), that is, the first two digits of the identification code, can be used as the code of the external interface type. For example, Fig.18 As shown, when the first two digits of the identification code are 00, the type of the external interface is determined to be a first-class external interface; Fig.19 As shown, when the first two digits of the identification code are 01, the type of the external interface is determined to be a second type external interface; Fig. 20 As shown, when the first two digits of the identification code are 10, the type of the external interface is determined to be a third type external interface.

[0100] Furthermore, the third pin ID (SLOT_ID0) and the fourth pin ID (SLOT_ID1), that is, the last two digits of the identification code, can also be used as the code of the slot in the external interface. Fig.18 As shown, based on the first two identification codes being 00, when the code of the last two identification codes is 00, it is determined that the card to be identified is inserted into the first slot 1031, when the code of the last two identification codes is 01, it is determined that the card to be identified is inserted into the second slot 1032, and when the code of the last two identification codes is 10, it is determined that the card to be identified is inserted into the third slot 1033; as shown in FIG. Fig.19 As shown, based on the first two identification codes being 01, when the last two identification codes are coded as 00, it is determined that the card to be identified is inserted into the fourth slot 1041, and when the last two identification codes are coded as 01, it is determined that the card to be identified is inserted into the fifth slot 1042; Fig. 20As shown, based on the first two digits of the identification code being 10, when the code of the last two digits of the identification code is 00, it is determined that the card to be identified is inserted into the sixth slot 1051, and when the code of the last two digits of the identification code is 01, it is determined that the card to be identified is inserted into the seventh slot 1052.

[0101] It should be noted that the above Fig.12 , Fig.13 and Fig.18 Have a corresponding relationship, where Fig.12 , Fig.13 The four pins can be connected in sequence from top to bottom Fig.18 The first pin ID, the second pin ID, the third pin ID, and the fourth pin ID in the above correspond to each other; Fig.14 , Fig.15 and Fig.19 Have a corresponding relationship, where Fig.14 , Fig.15 The four pins can be connected to Fig.19 The fourth pin ID, the third pin ID, the second pin ID, and the first pin ID in the aforementioned Fig.16 , Fig.17 and Fig. 20 Have a corresponding relationship, where Fig.16 , Fig.17 The four pins are connected from top to bottom in sequence Fig. 20 The first pin ID, the second pin ID, the third pin ID, and the fourth pin ID correspond to each other.

[0102] It should be noted that, as mentioned above, the FPGA chip can determine which motherboard slot the received identification signal comes from, but it cannot determine the type of external interface included in the plug-in device on the motherboard slot, and which slot of the external interface the card to be identified is inserted into. Therefore, when the number of slots included in the external interface is less than 4, it can be represented by a two-digit identification code. In some optional embodiments, if the number of slots included in the external interface is multiple, the number of identification codes can be set to more digits, and the number of pins in the card to be identified and the number of contact pins in the plug-in device can be modified to adapt.

[0103] It should also be noted that the above embodiment is only an optional example of an encoding method when the type of external interface includes three types. In other embodiments, if the type of external interface includes more types, the number of pins of the card to be identified, the number of contact pins in the slot, and the encoding method can also adapt to changes.

[0104] It should also be noted that due to the limitation of the hardware connection and the way the FPGA chip reads the identification signal, the encoding order of the first two identification codes is opposite to the hardware connection method, and the encoding order of the last two identification codes is also opposite to the hardware connection method. Fig.18As shown, for the third slot 1033 whose last two digits are coded as 10, a contact pin is set at the position of the third pin to generate an identification signal with a level state of 0, and no contact pin is set at the position of the fourth pin to generate an identification signal with a level state of 1.

[0105] The embodiment of the utility model provides a plug-in device, which encodes the type of the external interface through the first two identification codes in the four-digit identification code, and encodes the position of the slot in the external interface into which the card group to be identified is inserted through the last two identification codes in the four-digit identification code. In this way, when the PCBs of the cards to be identified are the same, the position of the card to be identified and the type of the external interface can be identified, which improves the flexibility of the plug-in device and is easy to apply to the hardware testing process.

[0106] In another embodiment of the present invention, Fig.21 A schematic diagram of the structure of a mainboard provided in an embodiment of the utility model Figure 1 .like Fig.21 As shown, the mainboard 20 includes the plug-in device 10 and the FPGA chip 201 as in the aforementioned embodiment, the plug-in device 10 and the FPGA chip 201 are connected, and the plug-in device 10 is provided with at least one group of external interfaces, and each group of external interfaces includes at least one slot.

[0107] The card group to be identified is plugged into the slot in the external interface accordingly.

[0108] The FPGA chip 201 is used to determine the type of the external interface and the position of the slot into which the card group to be identified is inserted according to the identification signal after receiving the identification signal sent by the plug-in device 10.

[0109] The identification signal corresponds to the position and shape of the slot.

[0110] In an embodiment of the utility model, a plurality of motherboard slots can be arranged on the motherboard 20, and the motherboard slots are used to connect the plug-in device. The FPGA chip 201 can be arranged on the motherboard and connected to the motherboard slots through a bus, thereby realizing communication between the FPGA chip 201 and the plug-in device 10 and the card group to be identified plugged into the plug-in device 10.

[0111] As mentioned above, the plug-in device 10 includes at least one group of external interfaces, which can be, for example, a first type of external interface, a second type of external interface, and a third type of external interface, and at least one group of each type of external interface can be set on the mainboard. Different types of external interfaces include different numbers of slots, and the number and position of contact pins included in different slots are also different. In this way, after the card to be identified is inserted into the slot, the pin of the four pins of the card to be identified that is plugged with the contact pin is grounded, and the level state of the identification signal generated by the pin is 0; if the contact pin is not set at the corresponding position on the slot after the card to be identified is inserted, the pin cannot contact the slot, and the level state of the identification signal generated by the pin is 1.

[0112] In this way, after the card group to be identified is inserted into the slot, different identification signals can be generated based on the different shapes of the slots. The signal is transmitted to the FPGA chip 201 through the plug-in device and the bus on the main board, so that the FPGA chip 201 can determine which type of external interface is inserted and the position of the slot on the external interface into which the card to be identified is inserted based on the analysis of the identification signal.

[0113] In some embodiments, the FPGA chip 201 is also used to determine the type of the external interface based on the first two digits of the identification code in the identification signal after detecting the insertion of the card group to be identified; and to determine the position of the slot into which the card group to be identified is inserted based on the last two digits of the identification code in the identification signal.

[0114] Fig. 22 A schematic diagram of the structure of a mainboard provided in an embodiment of the utility model Figure 2 .like Fig. 22 As shown, the four-digit identification code in the identification signal generated by the plug device 10 is 1000, that is, the first pin ID is 1, the second pin ID is 0, the third pin ID is 0, and the fourth pin ID is 0.

[0115] In the embodiment of the utility model, the position where the contact pin is set in the plug-in device 10 is grounded after the card to be identified is inserted, and the position where the contact pin is not set still maintains a high level after the card to be identified is inserted, so that different identification signals are generated based on the shape of the slot and sent to the FPGA chip 201 through the PWR / SB interface 202. As mentioned above, the FPGA chip 201 can pre-use the first two digits of the identification code as the code of the type of the external interface and the last two digits of the identification code as the code of the position of the slot, so that after receiving the identification signal, the first two digits of the identification code and the last two digits of the identification code are analyzed respectively to determine the type of the external interface and the position of the slot where the card group to be identified is inserted.

[0116] Table 1

[0117] Slot 1 Slot 2 Slot 3 The first type of external interface: 00 00 01 10 The second type of external interface: 01 00 01 The third type of external interface: 10 00 01

[0118] Table 1 is a coding table of external interfaces and slots. Among them, slot 1, slot 2, and slot 3 represent different slots in different types of external interfaces. Exemplarily, as shown in Table 1, for the first type of external interface, its code is 00, the code of slot 1 (first slot) in the first type of external interface is 00, the code of slot 2 (second slot) is 01, and the code of slot 3 (third slot) is 10; for the second type of external interface, its code is 01, the code of slot 1 (fourth slot) in the second type of external interface is 00, and the code of slot 2 (fifth slot) is 01; for the third type of external interface, its code is 10, the code of slot 1 (sixth slot) in the third type of external interface is 00, and the code of slot 2 (seventh slot) is 01. The above Table 1 can be pre-stored in the FPGA chip 201, so that after analyzing the level state of the identification signal, the FPGA chip 201 can determine the type of external interface corresponding to the identification signal and the position of the slot inserted into the card group to be identified according to Table 1.

[0119] In some embodiments, continue to refer to Fig. 22 The mainboard also includes a central processor 203, which is connected to at least one set of external interfaces, wherein the central processor 203 is used to communicate with the card group to be identified based on the PCIe protocol after detecting that the card group to be identified is inserted.

[0120] In the embodiment of the utility model, a central processor 203 is also provided on the mainboard, and the central processor 203 and the card group to be identified plugged into the slot in the external interface on the plug-in device 10 can communicate through a high-speed data transmission interface 204, which can be PCIex8 or PCIex16, for example. Thus, the central processor 203 can communicate with the graphics card, wireless network card, solid-state hard disk and other function cards plugged into the card group to be identified, communicate with the data of these function cards, and perform data processing.

[0121] The embodiment of the utility model provides a mainboard, including an FPGA chip, a plug-in device and a central processor 203, wherein after the card group to be identified is plugged into the slots of different external interfaces on the plug-in device, different identification signals can be generated and sent to the FPGA chip, so that the FPGA chip can automatically determine the position of the slot where the card group to be identified is inserted and the type of the external interface based on the identification signal. In this way, it is convenient for the mainboard to realize accurate management of the PCIe slot and the inserted card group.

[0122] Those skilled in the art will appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed in the present invention can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present invention.

[0123] Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

[0124] It should be noted that, in the present utility model, the terms "comprise", "include" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

[0125] The serial numbers of the above-mentioned embodiments of the present invention are only for description and do not represent the advantages or disadvantages of the embodiments.

[0126] The methods disclosed in the several method embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments.

[0127] The features disclosed in several product embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new product embodiments.

[0128] The features disclosed in several method or device embodiments provided by the present invention can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0129] The above description is only a preferred embodiment of the present utility model and is not intended to limit the protection scope of the present utility model. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present utility model should be included in the protection scope of the present utility model.

Claims

1. A plug-in device, characterized in that: The plug-in device is connected to the FPGA chip, and the plug-in device is provided with at least one group of external interfaces, each group of the external interfaces includes at least one slot, wherein: The card group to be identified is plugged into the slot in the external interface accordingly, so that after receiving the identification signal sent by the plug-in device, the FPGA chip determines the type of the external interface and the position of the slot into which the card group to be identified is inserted according to the identification signal; wherein the identification signal has a corresponding relationship with the position and shape of the slot.

2. The device according to claim 1, characterized in that The types of the card groups to be identified include: A first type of card group to be identified, wherein the first type of card group to be identified includes three cards to be identified; The second type of card group to be identified includes two cards to be identified.

3. The device according to claim 1, characterized in that The at least one group of external interfaces includes at least one of a first type external interface, a second type external interface, and a third type external interface, wherein: The first type of external interface includes a first slot, a second slot and a third slot; The second type of external interface includes a fourth slot and a fifth slot; The third type external interface includes a sixth slot and a seventh slot, wherein the shapes of the first slot, the second slot, the third slot, the fourth slot, the fifth slot, the sixth slot and the seventh slot are all different.

4. The device according to claim 3, characterized in that The connection end of the card to be identified includes a first pin, a second pin, a third pin and a fourth pin; The first slot includes four contact pins, which respectively correspond to the insertion positions of the first pin, the second pin, the third pin and the fourth pin; The second slot includes three contact pins corresponding to the insertion positions of the first pin, the second pin and the fourth pin respectively; The third slot includes three contact pins corresponding to the positions of the first pin, the second pin and the third pin respectively.

5. The device according to claim 3, characterized in that The connection end of the card to be identified includes a first pin, a second pin, a third pin and a fourth pin; The fourth slot includes three contact pins corresponding to the positions of the first pin, the second pin and the third pin respectively; The fifth slot includes two contact pins corresponding to the insertion positions of the first pin and the third pin respectively.

6. The device according to claim 3, characterized in that The connection end of the card to be identified includes a first pin, a second pin, a third pin and a fourth pin; The sixth slot includes three contact pins corresponding to the insertion positions of the first pin, the third pin and the fourth pin respectively; The seventh slot includes two contact pins corresponding to the insertion positions of the first pin and the fourth pin respectively.

7. The device according to claim 1, characterized in that The identification signal includes a four-digit identification code, wherein: The first two digits of the four-digit identification code are used to indicate the type of the external interface; The last two digits of the four-digit identification code are used to indicate the position of the slot into which the card set to be identified is inserted.

8. A motherboard, characterized in that: The device comprises a plug-in device and an FPGA chip as claimed in any one of claims 1 to 7, wherein the plug-in device is connected to the FPGA chip, and the plug-in device is provided with at least one group of external interfaces, each group of the external interfaces comprises at least one slot, wherein: The card group to be identified is correspondingly plugged into the slot in the external interface; The FPGA chip is used to determine the type of the external interface and the position of the slot into which the card group to be identified is inserted according to the identification signal after receiving the identification signal sent by the plug-in device; The identification signal corresponds to the position and shape of the slot.

9. The mainboard according to claim 8, characterized in that: The FPGA chip is also used to determine the type of the external interface according to the first two digits of the identification code in the identification signal after detecting the insertion of the card group to be identified; and to determine the position of the slot into which the card group to be identified is inserted according to the last two digits of the identification code in the identification signal.

10. The mainboard according to claim 9, characterized in that: The mainboard further includes a central processing unit, and the central processing unit is connected to the at least one set of external interfaces, wherein: The central processor is used to communicate with the card group to be identified based on the PCIe protocol after detecting that the card group to be identified is inserted.

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