PXIe backboard with USB4 / Thunderbolt lightning interface

Abstract

The utility model belongs to the technical field of radio frequency microwave instruments, and discloses a PXIe backboard with a USB4 / Thunderbolt lightning interface, the PXIe backboard comprises a Thunderbolt-PCIe circuit, a PCIE bus expansion circuit and a PXIe clock circuit, the Thunderbolt-PCIe circuit is an ASM 2464PDX controller, the PCIE bus expansion circuit is an ASM 2824PCIe switch chip, and the PXIe clock circuit is an HMC7044 clock generator. According to the PXIe backboard with the USB4 / Thunderbolt lightning interface, the Thunderbolt standard and the PXIe standard can be effectively compatible, in-situ replacement of the PXIe backboard is realized, an existing PXIe service module is reused, the equipment performance is improved by using an external controller, the effect of reducing the test cost and the research and development cost is achieved, and meanwhile, the confidentiality requirement is met.

Description

TECHNICAL FIELD

[0001] The application relates to the technical field of radio frequency microwave instruments, and more particularly to a PXIe backboard with a USB4 / Thunderbolt interface. BACKGROUND

[0002] The PXIe bus standard is derived from the PXI bus standard by adding a PCIe bus, and is widely used in the field of test and measurement. Compared with desktop test equipment, modular test equipment using the PXIe bus standard has the characteristics of rich types, customization, flexibility, high data throughput and low cost, is accepted by the public, and is widely used.

[0003] The number of slots of a standard PXIe chassis backboard is not fixed and can be customized according to user requirements. It usually contains one system slot, one clock synchronization slot and a plurality of mixed slots to meet different use requirements. The standard PXIe chassis backboard defines only a mode in which the PCIe bus input of the system slot is connected to the PCIe bus output of the service slot. The chassis based on the PXIe standard backboard must be matched with a standard PXIe controller module to be used.

[0004] The Thunderbolt interface is a high-speed data transmission interface that can integrate data, video, audio and power transmission into a single interface. Due to the use of PCI Express and DisplayPort architecture, Thunderbolt can connect peripherals such as hard drives, RAID arrays, video capture devices and network interfaces at high speed, and can also transmit high-definition video using the DisplayPort protocol. Each Thunderbolt interface can also provide power to peripherals, thereby supporting the connection of multiple devices through a single interface. Thunderbolt 3 and above versions have supported data transmission capabilities of up to 40 Gbps, meeting the requirements of test and measurement equipment for data transmission rates.

[0005] Chassis equipped with a standard PXIe backboard (such as shown in Figure 1 ) must be matched with a standard PXIe controller for use. The disadvantage of this combination is that the use is limited to the controller. Because the design of the standard PXIe controller is limited by the space size, it leads to great design difficulty, the performance is relatively poor compared with desktop computers or notebook computers, and the selling price is relatively high. The selling price of a domestic brand PXIe controller is usually tens of thousands of yuan, and the selling price of an imported brand PXIe controller is even as high as hundreds of thousands of yuan. This invisibly increases the test use cost and research and development cost of users.

[0006] In addition, for users with security requirements, it is more difficult to purchase a domestically produced PXIe controller solution, and the cost will be higher. CONTENT OF THE INVENTION

[0007] In order to solve the above problems, the utility model provides a kind of PXIe backboard design scheme with thunderbolt interface, improve on the basis of standard PXIe backboard, increase thunderbolt data interface, and PXIe chassis based on this kind of backboard design does not need to use PXIe controller again.Use method changes to control by the thunderbolt interface of external computer, and user can configure different performance and localization computer according to use demand.In this way, user can obtain higher performance, lower cost, and meet the requirement of secrecy.

[0008] The PXIe backboard with USB4 / Thunderbolt interface provided by the application adopts the following technical scheme:

[0009] The PXIe backboard with USB4 / Thunderbolt interface comprises a Thunderbolt-PCIe circuit, a PCIE bus expansion circuit and a PXIe clock circuit, the Thunderbolt-PCIe circuit is an ASM2464PDX controller, the PCIE bus expansion circuit is an ASM2824 PCIe switch chip, and the PXIe clock circuit is an HMC7044 clock generator.

[0010] Further, the ASM2464PDX controller integrates 2-way USB 20Gbps physical interface, the ASM2464PDX controller integrates UFPCC logic for USB-C cable direction detection, and the ASM2464PDX controller integrates BMC physical interface for PD 5V UFP / Sink mode.

[0011] Further, the upstream interface of the ASM2824 PCIe switch chip supports a maximum PCIe Gen3 x8 Lane bandwidth, and the downstream interface can be flexibly configured into x1, x2, x4 and x8 modes.

[0012] Further, the ADI HMC7044 clock generator is a dual-phase-locked-loop clock generator supporting 4-way reference clock input and 14-way independent clock output.

[0013] In summary, the application includes at least one of the following beneficial technical effects:

[0014] The PXIe backboard with USB4 / Thunderbolt interface can effectively compatible Thunderbolt standard and PXIe standard, realize PXIe backboard in-situ replacement, reuse existing PXIe business module, use external controller to improve device performance, reduce test cost and R&D cost, and meet the requirement of secrecy. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 Design block diagram for the existing PXIe backplane;

[0016] Figure 2 Functional block diagram of the ASM2464PDX controller of the present application;

[0017] Figure 3 Functional block diagram of the ASM2824 of the present application;

[0018] Figure 4 Functional block diagram of the HMC7044 of the present application;

[0019] Figure 5 Design block diagram for the improved PXIe backplane of the present application;

[0020] Figure 6 Flow chart of the FPGA control of the present application;

[0021] Figure 7 Simulation configuration diagram of the HMC7044 of the present application;

[0022] Figure 8 Circuit design diagram of the ASM2464 of the present application;

[0023] Figure 9 Circuit design diagram of the ASM2824 of the present application. DETAILED DESCRIPTION

[0024] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application; obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application, and all other embodiments obtained by those of ordinary skill in the art without creative labor on the basis of the embodiments in the present application shall fall within the scope of protection of the present application.

[0025] In the description of the present application, it should be noted that the terms "upper", "lower", "inner", "outer", "top / bottom end" and the like indicate the orientation or positional relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as limiting the present application. In addition, the terms "first", "second" are only for the purpose of description, and cannot be understood as indicating or implying relative importance.

[0026] In the description of the present application, it should be explained that, unless otherwise explicitly specified and limited, the terms "mounting", "provided with", "sleeved / connected", "connected" and the like should be understood in a broad sense, for example, "connected" can be fixedly connected, or can be detachably connected, or integrally connected; can be mechanically connected, or can be electrically connected; can be directly connected, or can be indirectly connected through an intermediate medium, or can be internal communication of two elements. For those skilled in the art, the specific meanings of the above terms in the present application can be understood according to the specific circumstances.

[0027] The present application will be further described in detail below with reference to the accompanying drawings.

[0028] Reference Figures 2-9 The embodiment of the present application discloses a PXIe backplane with USB4 / Thunderbolt interface, which comprises a Thunderbolt-PCIe circuit, a PCIE bus expansion circuit and a PXIe clock circuit. The Thunderbolt-PCIe circuit is an ASM2464PDX controller, the PCIE bus expansion circuit is an ASM2824 PCIe switch chip, and the PXIe clock circuit is an HMC7044 clock generator.

[0029] At present, there are relatively few controller schemes supporting Thunderbolt-PCIe on the market. The mainstream controller schemes are Intel JHL6x40, JHL7x40 series Thunderbolt 3 controllers and JHL8x40 series Thunderbolt 4 controllers. However, due to the low support of Intel to small manufacturers and the high difficulty of chip configuration, the ASM2464PDX scheme of ASMedia which is more friendly to small manufacturers is finally selected for design in the present scheme.

[0030] ASM2464PDX is a USB4 / Thunderbolt3-PCIe / NVMe controller, and its function block diagram is as shown in Figure 2 It has the following characteristics:

[0031] General characteristics:

[0032] a) Support USB4 / Thunderbolt3 to PCIe / NVMe SSD

[0033] b) Integrated 2-way USB 20Gbps physical interface;

[0034] c) Integrated UFPCC logic for USB-C cable direction detection;

[0035] d) Integrated BMC physical interface for PD 5V UFP / Sink mode;

[0036] e) VCC / VCCL / VCCH power supply mode;

[0037] f) Support I2C / GPIO / UART interface;

[0038] USB features:

[0039] a) Support USB4 / Thunderbolt Gen3 x2, compatible with USB3.2 and USB 2.0;

[0040] b) Support BOT / UAS protocol;

[0041] c) Support USB connection power management;

[0042] d) Support USB hot plug;

[0043] e) Support spread spectrum clock control;

[0044] f) Support UNMAP command setting;

[0045] g) Compatible with USB4 Rev1.0 standard specification;

[0046] h) Support USB-C cable and connector specification Rev2.1;

[0047] i) Support USB power distribution specification Rev3.1;

[0048] PCIe features:

[0049] a) Support up to PCIe Gen4 x4;

[0050] b) Refer to PCIe NVMe SSD;

[0051] c) Support spread spectrum clock control;

[0052] d) Support 100MHz differential reference clock output;

[0053] e) Support multiple PCIe slot types: M.2, U.2 and CFexpress;

[0054] f) Support PCIe connection power management;

[0055] g) Compatible with PCIe base specification Rev 4.0;

[0056] h) Compatible with PCIe M.2 specification Rev 1.1;

[0057] 2. PCIE bus extension circuit design scheme:

[0058] The utility model selects ASMedia ASM2824 PCIe switch chip scheme to design, and ASM2824 has low delay, low cost, low power consumption advantage. Figure 3

[0059] 3, PXIe clock circuit design scheme:

[0060] The utility model selects ADI HMC7044 clock generator as PXIe clock circuit design scheme, and HMC7044 is a kind of double phase-locked loop clock generator supporting 4-way reference clock input, 14-way clock independent output, its function block diagram as shown in Figure 4

[0061] The hardware function block diagram of the utility model as shown in Figure 5 Mainly include FPGA, Clock Generator, PCIeSwitch and Thunderbolt Controller etc.Parts.The main signal flow is divided into three types: control signal, clock signal and data signal:

[0062] 1, control flow signal:

[0063] Control flow signal is configured to all functional devices in the entire case, so that functional devices can be set to run to achieve the intended function, to realize the conversion function from thunderbolt interface to PXIe interface, all control signals are issued from FPGA uniform.

[0064] FPGA is the control center of the entire case, and FPGA is programmed by burning firmware. After the whole machine is powered on, FPGA will initialize configuration to clock generator (HMC7044), PCIe bus switch (ASM2824) according to the solidified program, and thunderbolt interface controller (ASM2464PDX) directly carries out corresponding configuration through FLASH, so that all functional devices of the whole machine play the intended function. The case control flow as shown in Figure 6

[0065] 2, clock flow signal:

[0066] Clock flow signal mainly provides various reference clock signals for thunderbolt interface controller, PCIe switch and PXIe connector, so that the clock of each part of the system circuit is synchronized. System clock signal flow as shown in Figure 4 ​​​As shown in the green part, all reference clock signals are generated and distributed by HMC7044. The HMC7044 output clock signals include the 25MHz reference clock required by ASM2824 and ASM2464, and the 10MHz, 100MHz, Sync-100MHz standard clock signals on the PXIe connector.

[0067] The PCIe x4 data bus clock (100MHz) is generated by the ASM2464 controller internally and output to the uplink clock port of the ASM2824 bus switch, and the ASM2824 distributes the clock signal to the four downstream bus ports, and finally connected to the standard PXIe XP3 connector, which is used by the PXIe standardized module device.

[0068] The 10MHz clock signal defined on the standard PXIe XP4 connector is directly provided by the HMC7044, and the 100MHz, Sync-100MHz clock signals are on the standard PXIe XP3 connector.

[0069] 3. Data flow signal:

[0070] The data flow signal is mainly Thunderbolt and PCIe bus data signal flow, which is bidirectional data.

[0071] The Thunderbolt data flow mainly exists between the Thunderbolt controller and the Type C connector, which is used for high-speed data interaction with the external controller, mainly for test parameter issuing and test result back analysis.

[0072] The PCIe x4 data flow is mainly initiated by the Thunderbolt control and connected to the PXIe XP3 standard connector through the PCIe switch, which is used for data interaction with the standard PXIe test module.

[0073] 4. FPGA circuit design

[0074] The design of the utility model has low requirements on FPGA, and there is no complex logic control and algorithm implementation, so the cost is the priority factor for FPGA design selection, and Intel Max10 series 10M08SAU169I7G type FPGA is selected for design. The FPGA power supply and peripheral circuit design adopts the general processing method in the industry, and there is no special design requirement, and the detailed design consideration can refer to the content of the Intel Max10 series FPGA related manual documents.

[0075] 5. HMC7044 circuit design

[0076] The focus of the reference clock signal generation design is the HMC7044 multi-channel clock generator circuit, which includes two phase-locked loops. The first phase-locked loop is designed to lock a 100MHz reference clock output from a 10MHz reference clock. The second phase-locked loop is designed to lock an internal VCO and output multiple required reference clock signals by frequency division. The HMC7044 simulation configuration is as shown in Figure 7 .

[0077] The configuration method of the first phase-locked loop of HMC7044: the reference input port is configured as CLKin0 port, the reference clock input frequency is 10MHz, the input R divider frequency division ratio is 1, the external VCXO clock frequency is 100MHz, and the N divider frequency division ratio is 10.

[0078] The configuration method of the second phase-locked loop of HMC7044: the R divider frequency division ratio is 1, the frequency multiplier is not enabled, the internal VCO mode is enabled, the N divider frequency division ratio is 30, and the internal VCO is locked at 3GHz. Only the first phase-locked loop is actually used, and after the 100M output, frequency division is directly performed in the following.

[0079] The output port configuration is configured according to the reference clock frequency of the system. The configuration parameters include only the output signal type and the frequency division ratio. In this scheme, the general signal type is LVDS differential signal output, the frequency division ratio is configured as 30 to output a 100MHz reference clock, the frequency division ratio is configured as 120 to output a 25MHz reference clock, and so on.

[0080] 6. Thunderbolt controller circuit design

[0081] The Thunderbolt controller circuit design is as shown in Figure 8 . The design focus is the left Thunderbolt interface and PCIe bus interface. The right power supply, reset, SPI, and other general-purpose circuits are designed according to the general method in the industry. The GPIO part can be defined or deleted according to different use requirements except for the multiplexed pins, and there is no special requirement.

[0082] The Thunderbolt interface signal is connected to the Type C connector. When designing, attention should be paid to the differential pair PCB trace impedance control and equal length design, and ESD protection should be included.

[0083] The PCIe bus interface signal is connected to the PCIe bus switch uplink port. When designing, attention should be paid to the differential pair PCB trace impedance control and equal length design, and the number of REFCLK clock signals should be adjusted according to different use requirements.

[0084] 7. PCIe bus switch circuit design

[0085] The main function of the PCIe bus switch is to distribute the uplink PCIe data to multiple downlink devices, realizing the function of a single controller mounting multiple PCIe devices. The ASM2824 supports uplink single lane highest PCIe x8 configuration, and downlink maximum 12 lane PCIe bus configuration. Users can modulate according to actual needs, and are not limited to the downlink 4x4 mode used in the present scheme. If the downlink port configuration is adjusted, attention should be paid to checking the chip specification book to determine the configuration mode of the clock with the lane, and to ensure that the clock with the lane matches the PXIe data bus.

[0086] The ASM2824 power supply, reset and other circuit design has no special requirements, and can be designed according to the conventional design in the industry. The detailed circuit design is shown in Figure 9

[0087] The above are preferred embodiments of the present application, and are not intended to limit the protection scope of the present application. Therefore, any equivalent changes made according to the structure, shape and principle of the present application should be covered within the protection scope of the present application.​

Claims

1. A PXIe backplane with USB4 / Thunderbolt lighting interface, characterized in that, The Thunderbolt-PCIe circuit is an ASM2464PDX controller, the PCIE bus expansion circuit is an ASM2824 PCIe switch chip, and the PXIe clock circuit is an ADIHMC7044 clock generator.

2. The PXIe backplane with USB4 / Thunderbolt lighting interface according to claim 1, wherein: The ASM2464PDX controller integrates 2-way USB 20Gbps physical interfaces, the ASM2464PDX controller integrates UFPCC logic for USB-C cable direction detection, and the ASM2464PDX controller integrates BMC physical interfaces for PD 5V UFP / Sink mode.

3. The PXIe backplane with USB4 / Thunderbolt lighting interface of claim 1, wherein: The upstream interface of the ASM2824 PCIe switch chip supports a maximum PCIe Gen3x8 Lane bandwidth, and the downstream interface can be flexibly configured in x1, x2, x4 or x8 mode.

4. The PXIe backplane with USB4 / Thunderbolt lighting interface of claim 1, wherein: The ADI HMC7044 clock generator is a dual phase-locked loop clock generator supporting 4-way reference clock input and 14-way independent clock output.

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