Internal analog power supply voltage generation circuit applied to high-speed chip
By generating adaptive voltages through process corner compensation, temperature compensation, and calibration circuits, the clock delay inconsistency caused by PVT variations in high-speed SerDes circuits is resolved, achieving timing stability and low bit error rate under different conditions.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- SUZHOU YINNAWE SEMICON CO LTD
- Filing Date
- 2025-06-26
- Publication Date
- 2026-05-01
AI Technical Summary
In high-speed SerDes circuits, clock delay inconsistencies caused by PVT variations affect the bit error rate, and existing technologies struggle to maintain timing requirements under different PVT conditions.
A process angle compensation circuit, a temperature compensation circuit, and a calibration circuit are used to generate voltages VDIO, VT, and VREF that vary with process angle and temperature. VDDR is output through the output circuit to drive the load, and VDDR is calibrated through the calibration circuit to keep it consistent with VREF.
Maintaining consistent clock and data delays at different temperatures and process angles constrains signal timing in high-speed circuits and reduces bit error rate.
Smart Images
Figure CN224190447U_ABST
Abstract
Description
An internal analog power supply voltage generation circuit for high-speed chips Technical Field
[0001] This utility model relates to the field of power supply circuit technology, and in particular to an internal analog power supply voltage generation circuit for high-speed chips. Background Technology
[0002] As the speed requirements of SerDes circuits continue to increase, the circuit requirements for core modules, such as DFE, DEMUX, MUX, and CLKPATH, are also gradually increasing. Many data and clock interactions need to be completed within one or half a cycle. Therefore, reducing the spatiotemporal offset caused by PVT (Process-Voltage-Temperature) within this short time interval is essential. As shown in Figure 1, the DFF samples data D1 through CLK. Due to temperature and process angle variations, a time delay difference of t2-t1 occurs. The time interval during which the DFF can sample D1 in the next clock cycle changes from 1T to 1T-(t2-t1), where 1T is one clock cycle. As the speed increases, 1T-(t2-t1) becomes smaller and smaller. This reduction in sampling time margin has a significant impact on the bit error rate of high-speed SerDes circuits. Therefore, to ensure that timing requirements are met under different PVTs, it is crucial to provide an internal analog voltage that can keep the clock delay at a low level under different PVTs. Summary of the Invention
[0003] In response to the aforementioned problems and technical requirements, the applicant has proposed a method for generating internal analog power supply voltage for high-speed chips.
[0004] The technical solution of this utility model is as follows:
[0005] An internal analog power supply voltage generation circuit for high-speed chips includes a process corner compensation circuit, a calibration circuit, a temperature compensation circuit, and an output circuit, all connected in an adaptive manner.
[0006] The process angle compensation circuit is used to generate a voltage VDIO that varies with the process angle, and the temperature compensation circuit is used to generate a voltage VT that varies with the temperature.
[0007] The output circuit is used to output voltage VDDR according to voltage VREF, and the calibration circuit is used to calibrate voltage VDDR according to voltage VREF, wherein voltage VREF is the sum of voltage VDIO and voltage VT.
[0008] A further technical solution is that the process corner compensation circuit includes an NMOS transistor MN and a PMOS transistor MP;
[0009] The source of the NMOS transistor MN is grounded, and the gate of the NMOS transistor MN is connected to the drain of the NMOS transistor MN, the drain of the PMOS transistor MP, and the gate of the PMOS transistor MP.
[0010] A further technical solution is that the temperature compensation circuit includes resistors R1 and R2, a positive temperature coefficient current source for providing a positive temperature coefficient current IPTAT, and a constant current source for providing a current ICC.
[0011] The output terminal of the positive temperature coefficient current source is connected to one end of resistor R1, the input terminal of the constant current source is connected to one end of resistor R1, the output terminal of the constant current source is grounded, the other end of resistor R1 is connected to one end of resistor R2 to form the output terminal of voltage VREF, and the other end of resistor R2 is connected to the source of PMOS transistor MP.
[0012] A further technical solution is that the positive temperature coefficient current source includes a current mirror, a reference transistor group, resistors R4, R5, and R6, transistors Q1 and Q2, and operational amplifier U2.
[0013] The current mirror includes PMOS transistors M6 and M7, and the reference transistor group includes PMOS transistors M8 and M9.
[0014] The source of PMOS transistor M6 is connected to the source of PMOS transistor M8, and the drain of PMOS transistor M6 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 forms the output terminal of positive temperature coefficient current IPTAT.
[0015] The gate of PMOS transistor M6 is connected to the gate of PMOS transistor M8, the gate of PMOS transistor M7 is connected to the gate of PMOS transistor M9, the drain of PMOS transistor M8 is connected to the source of PMOS transistor M9, and the drain of PMOS transistor M9 is connected to voltage VBG1P2V.
[0016] A further technical solution is that the drain of the PMOS transistor M9 is connected to one end of resistors R4 and R5, the other end of resistor R4 is connected to the emitter of transistor Q1 and the inverting input of operational amplifier U2, the other end of resistor R5 is connected to the non-inverting input of operational amplifier U2 and one end of resistor R6, the other end of resistor R6 is connected to the emitter of transistor Q2, and the output of operational amplifier U2 is connected to the gate of PMOS transistor M8.
[0017] The base of transistor Q1 is connected to the collector of transistor Q1, and the collector of transistor Q1 is connected to the collector and base of transistor Q2.
[0018] A further technical solution is that the output circuit includes a resistor R3, an NMOS transistor NSF1, and an NMOS transistor NSF2. The drain of the NMOS transistor NSF1 is connected to the power supply voltage, the source of the NMOS transistor NSF1 is grounded through the resistor R3, the gate of the NMOS transistor NSF1 is connected to the gate of the NMOS transistor NSF2, and the source of the NMOS transistor NSF2 forms the output terminal of the voltage VDDR.
[0019] A further technical solution is that the NMOS transistor NSF1 and NMOS transistor NSF2 have the same current density.
[0020] A further technical solution is that the calibration circuit includes an operational amplifier U1, a resistor string, a multiplexer, a comparator, and a counter, wherein...
[0021] The non-inverting input of the comparator is connected to the output of voltage VREF, the inverting input of the comparator is connected to the output of voltage VDDR, the output of the comparator is connected to the control terminal of the counter, and the output of the counter is connected to the control terminal of the multiplexer.
[0022] A further technical solution is that the operational amplifier U1 includes PMOS transistor M3, PMOS transistor M4, NMOS transistor M1, NMOS transistor M2 and NMOS transistor M5;
[0023] The source of PMOS transistor M3 is connected to the source of PMOS transistor M4, the gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4, the gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, the drain of PMOS transistor M3 is connected to the drain of NMOS transistor M1, the gate of NMOS transistor M1 is connected to the output terminal of voltage VREF, the source of NMOS transistor M1 is connected to the drain of NMOS transistor M5 and the source of NMOS transistor M2, the source of NMOS transistor M5 is grounded, the drain of PMOS transistor M4 is connected to the drain of NMOS transistor M2 through a resistor series, and the gate of NMOS transistor M2 is grounded through resistor R3.
[0024] A further technical solution is that the resistor string includes n resistors connected in series, and the n resistors connected in series form n+1 connection nodes, where n is an integer greater than 1.
[0025] The multiplexer includes n+1 input terminals, each of which is connected to a corresponding connection node. The output terminal of the multiplexer is connected to the gate of the NMOS transistor NSF1.
[0026] The beneficial technical effects of this utility model are:
[0027] The internal analog power supply voltage generation circuit for high-speed chips provided by this invention can provide a voltage VDDR that follows process angle and temperature changes, so that the clock and data delays of the chip can remain basically consistent under different temperatures and process angles, which is beneficial to constrain the signal timing in high-speed circuits. Attached Figure Description
[0028] Figure 1 is a schematic diagram of clock delay at different temperatures and process angles.
[0029] Figure 2 is a schematic diagram of an embodiment of the internal analog power supply voltage generation circuit for high-speed chips provided by this utility model.
[0030] Figure 3 is a circuit diagram of one embodiment of the positive temperature coefficient current source provided by this utility model.
[0031] Figure 4 is a circuit diagram of one embodiment of the calibration circuit provided by this utility model.
[0032] Figure 5 is a circuit diagram of one embodiment of the calibration circuit provided by this utility model.
[0033] Figure 6 is a timing diagram of one embodiment of the operation process of the calibration circuit provided by this utility model. Detailed Implementation
[0034] The specific embodiments of this utility model will be further described below with reference to the accompanying drawings. It should be understood that the specific embodiments described herein are for illustrative purposes only and are not intended to limit the scope of this disclosure.
[0035] This invention provides an internal analog power supply voltage generation circuit for high-speed chips. It can be installed inside the high-speed chip and aims to provide an internal analog power supply voltage that adapts to changes in process angle and temperature, ensuring that clock and data delays remain essentially consistent across different temperatures and process angles. The internal analog power supply voltage generation circuit for high-speed chips includes a process angle compensation circuit, a calibration circuit, a temperature compensation circuit, and an output circuit, all connected in a compatible manner.
[0036] The process angle compensation circuit is used to generate a voltage VDIO that varies with the process angle, and the temperature compensation circuit is used to generate a voltage VT that varies with the temperature.
[0037] The output circuit is used to output voltage VDDR according to voltage VREF, and the calibration circuit is used to calibrate the output voltage VDDR according to voltage VREF, wherein voltage VREF is the sum of voltage VDIO and voltage VT.
[0038] Specifically, the process angle compensation circuit is connected to the temperature compensation circuit and the calibration circuit, and the calibration circuit is connected to the output circuit. The process angle compensation circuit is used to compensate for the speed difference of transistors at different process angles, generating a voltage VDIO that varies with the process angle. The temperature compensation circuit is used to compensate for the speed difference of transistors at different temperatures, generating a voltage VT that varies with the temperature. The sum of the voltage VDIO and the voltage VT forms the voltage VREF. Since the voltage VREF is only a reference voltage and cannot drive the load or provide current to the load, the output circuit also needs to output a voltage VDDR based on the voltage VREF. The generated voltage VDDR can drive the load and provide a large current. Without considering random circuit mismatch, the voltage VDDR basically follows the voltage VREF.
[0039] However, in practical applications, there will be random errors between the voltage output from the VDDR output terminal and the voltage VREF. Therefore, this invention includes a calibration circuit to calibrate the output voltage VDDR according to the voltage VREF, so that the voltage output from the VDDR output terminal is basically consistent with the voltage VREF. The specific forms and working principles of the process corner compensation circuit, calibration circuit, temperature compensation circuit, and output circuit can be found in the following description.
[0040] Further, referring to Figure 2, the process corner compensation circuit includes an NMOS transistor MN and a PMOS transistor MP; the source of the NMOS transistor MN is grounded, and the gate of the NMOS transistor MN is connected to the drain of the NMOS transistor MN, the drain of the PMOS transistor MP, and the gate of the PMOS transistor MP. The temperature compensation circuit includes resistors R1 and R2, a positive temperature coefficient current source for providing a positive temperature coefficient current IPTAT, and a constant current source for providing a current ICC.
[0041] The output terminal of the positive temperature coefficient current source is connected to one end of resistor R1, the input terminal of the constant current source is connected to one end of resistor R1, the output terminal of the constant current source is grounded, the other end of resistor R1 is connected to one end of resistor R2 to form the output terminal of voltage VREF, and the other end of resistor R2 is connected to the source of PMOS transistor MP.
[0042] The voltage VDIO is the source voltage of the PMOS transistor MP, VDIO = V GSP +V GSN V GSP V is the voltage between the gate and source of the PMOS transistor MP. GSN V is the voltage between the gate and source of the NMOS transistor MN. GSP and V GSN As the process angle changes, a voltage VDIO is generated that varies with the process angle.
[0043] The temperature compensation circuit includes resistors R1 and R2, a positive temperature coefficient current source for providing a positive temperature coefficient current IPTAT, and a constant current source for providing a current ICC. The positive temperature coefficient current IPTAT alone can only match a limited temperature change. Therefore, a constant current source is set to provide a current ICC. The positive temperature coefficient current IPTAT is subtracted from the current ICC to match the temperature change, increasing the proportion of the current magnitude changing with temperature. The voltage VT = (IPTAT - ICC)R2, where R2 is the resistance value of resistor R2.
[0044] The output terminal of the positive temperature coefficient current source is connected to one end of resistor R1, the input terminal of the constant current source is connected to one end of resistor R1, the output terminal of the constant current source is grounded, the other end of resistor R1 is connected to one end of resistor R2 to form the output terminal of voltage VREF, the other end of resistor R2 is connected to the source of PMOS transistor MP, and the voltage VREF = VDIO + VT. The specific form of the constant current source is the same as that of the prior art.
[0045] Further, please refer to Figure 3. The positive temperature coefficient current source includes a current mirror, a reference transistor group, resistors R4, R5, and R6, transistors Q1 and Q2, and operational amplifier U2.
[0046] The current mirror includes PMOS transistors M6 and M7, and the reference transistor group includes PMOS transistors M8 and M9.
[0047] The source of PMOS transistor M6 is connected to the source of PMOS transistor M8, and the drain of PMOS transistor M6 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 forms the output terminal of the positive temperature coefficient current IPTAT. The gate of PMOS transistor M6 is connected to the gate of PMOS transistor M8, the gate of PMOS transistor M7 is connected to the gate of PMOS transistor M9, the drain of PMOS transistor M8 is connected to the source of PMOS transistor M9, and the drain of PMOS transistor M9 is connected to the voltage VBG1P2V. The drain of PMOS transistor M9 is connected to one end of resistors R4 and R5. The other end of resistor R4 is connected to the emitter of transistor Q1 and the inverting input of operational amplifier U2. The other end of resistor R5 is connected to the non-inverting input of operational amplifier U2 and one end of resistor R6. The other end of resistor R6 is connected to the emitter of transistor Q2. The output of operational amplifier U2 is connected to the gate of PMOS transistor M8. The base of transistor Q1 is connected to the collector of transistor Q1. The collector of transistor Q1 is connected to the collector and base of transistor Q2.
[0048] Specifically, the voltage VBG1P2V is a zero-temperature coefficient reference voltage, which can be generated by a bandgap reference circuit. Both transistors Q1 and Q2 are PNP transistors. The current mirror can generate an IPTAT current of 10uA to 30uA through programmable control, increasing the robustness of the circuit. The specific method of programmable control can be consistent with existing technologies. The positive temperature coefficient current source utilizes the negative temperature coefficient characteristic of the voltage between the base and emitter of the transistor (VBE) to generate the positive temperature coefficient current IPTAT, which can be expressed as:
[0049]
[0050] Where M represents the size ratio of PMOS transistors M6 and M7 to PMOS transistors M8 and M9, R4||R5 represents the equivalent resistance value of resistors R4 and R5 connected in parallel, and VBE1 represents the voltage between the base and emitter of transistor Q1.
[0051] Furthermore, the output circuit includes a resistor R3, NMOS transistors NSF1 and NMOS transistor NSF2. The drains of NMOS transistors NSF1 and NSF2 are connected to the power supply voltage (AVDD18). The source of NMOS transistor NSF1 is grounded through resistor R3. The gates of NMOS transistors NSF1 and NMOS transistor NSF2 are connected. The source of NMOS transistor NSF2 forms the output terminal of voltage VDDR. By proper selection, the current densities of NMOS transistors NSF1 and NMOS transistor NSF2 are made the same. The output terminal of voltage VDDR is connected to the components requiring power in the high-speed chip. Figure 2 uses a delay chain formed by multiple inverters connected in series as an example; the output terminal of voltage VDDR is connected to the power supply pins of each inverter in the delay chain. It should be noted that the gates of both NMOS transistors NSF1 and NMOS transistor NSF2 need to be connected to a large capacitor to ground (not shown in the figure).
[0052] The calibration circuit includes an operational amplifier U1, a resistor string, a multiplexer, a comparator, and a counter. As shown in Figure 4, the non-inverting input of the comparator is connected to the output of voltage VREF, the inverting input of the comparator is connected to the output of voltage VDDR, the output of the comparator is connected to the control terminal of the counter, the output of the counter is connected to the control terminal of the multiplexer, and the counter is connected to the sampling clock CLK.
[0053] As shown in Figure 5, the operational amplifier U1 includes PMOS transistor M3, PMOS transistor M4, NMOS transistor M1, NMOS transistor M2 and NMOS transistor M5;
[0054] The source of PMOS transistor M3 is connected to the source of PMOS transistor M4, the gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4, the gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, the drain of PMOS transistor M3 is connected to the drain of NMOS transistor M1, the gate of NMOS transistor M1 is connected to the output terminal of voltage VREF, the source of NMOS transistor M1 is connected to the drain of NMOS transistor M5 and the source of NMOS transistor M2, the source of NMOS transistor M5 is grounded, the drain of PMOS transistor M4 is connected to the drain of NMOS transistor M2 through a resistor series, and the gate of NMOS transistor M2 is grounded through resistor R3.
[0055] The resistor string includes n resistors connected in series, forming n+1 connection nodes, where n is an integer greater than 1; the multiplexer includes n+1 input terminals, each of which is connected to one of the connection nodes, and the output terminal of the multiplexer is connected to the gate of the NMOS transistor NSF1.
[0056] Specifically, each of the resistors in the resistor string that are directly connected to the drain of PMOS transistor M4 and the drain of NMOS transistor M2 forms two connection nodes at one end, that is, two connection nodes are formed at the beginning and end of the resistor string, and one connection node is formed between each two adjacent resistors in the resistor string, for a total of n+1 connection nodes.
[0057] Ignoring random errors, the calibration voltage V output by the calibration circuit MUX =0, the gate voltage VG_GATE of the NMOS transistors NSF1 and NFS2 can be expressed as:
[0058] VG_GATE = VREF + VGS NSF1
[0059] Among them, VGS NSF1 Let VDDR be the voltage between the gate and source of the NMOS transistor NSF1.
[0060] VDDR = VG_GATE-VGS NSF2 =VREF+VGS NSF1 -VGS NSF2
[0061] Among them, VGS NSF2 VGS is the voltage between the gate and source of NMOS transistor NSF2. Since the current densities of NMOS transistors NSF1 and NSF2 are the same, VGS... NSF1 =VGS NSF2 We can obtain:
[0062] VDDR = VREF
[0063] Therefore, ideally, the voltage VDDR should be equal to the voltage VREF. However, in actual applications, due to the presence of a random error V X , the actual output voltage VDDR at the output terminal of the voltage VDDR may be lower than VREF. At this time, the calibration circuit outputs a calibration voltage V[[ID=�]] MUX to compensate for the random error V X , and the actual output voltage VDDR at the output terminal of the voltage VDDR = VREF + V MUX - V x , where the calibration circuit makes the calibration voltage V MUX approximately equal to V x , so that the output voltage at the output terminal of the voltage VDDR is basically the same as the voltage VREF.
[0064] The working principle of the calibration circuit is specifically as follows: The comparator generates an UP signal by comparing the voltage VREF with the voltage VDDR. The UP signal controls the counting direction of the counter, adjusts the count code output by the counter, and controls the multiplexer to select an input terminal signal for output through the count code. In this embodiment, the count code is a five-bit binary count code, represented by VG_SEL<4:0>. The five-bit count code can represent 32 count values. Therefore, 31 resistors connected in series are correspondingly arranged in the resistor string and form 32 connection nodes, which are connected to the 32 input terminals of the multiplexer one by one, and are sorted in sequence with the connection node adjacent to the drain of the NMOS transistor M2 as the zero connection node. Each connection node corresponds to a count value.
[0065] When VDDR < VREF, the UP signal is logic "1". When the rising edge of the sampling clock CLK arrives each time, the counter acts as an adder to carry the least significant bit of VG_SEL<4:0>. VG_SEL<4:0> controls the multiplexer to select the connection node input corresponding to the count value and outputs the calibration voltage V MUX to the gate of the NMOS transistor NSF1 in the output circuit until the UP signal flips. Similarly, when VDDR > VREF, the UP signal is logic "0". When the rising edge of the sampling clock CLK arrives each time, the counter acts as a subtractor to control the count value of VG_SEL<4:0> to decrease by one. VG_SEL<4:0> controls the multiplexer to select the connection node voltage input corresponding to the count value and outputs the calibration voltage V MUX to the gate of the NMOS transistor NSF1 in the output circuit until the UP signal flips. In this embodiment, the resistances of the resistors in the resistor string are all the same. Therefore, when the count value increases or decreases by one, the calibration voltage V MUX increases or decreases by the same voltage step.
[0066] Figure 6 illustrates the timing diagram of the calibration circuit calibrating VDDR. As shown in Figure 6, when VDDR has a random error lower than VREF, the UP signal gradually increases the count value of VG_SEL<4:0> (assuming it is initially 15) until VDDR moves up and down near VREF.
[0067] In practical implementation, the target voltage required under the (TT, 55℃) condition (i.e., process angle TT and temperature 55℃) can be determined according to the high-speed circuit structure of the specific application. Then, the target voltage required by the high-speed circuit under the (SS / FF / SF / FS, -40℃ / 125℃) condition with the same delay can be determined by the delay circuit. Based on the confirmation results of different process angles and temperatures, the components in the process angle compensation circuit and temperature compensation circuit are selected so that the VDDR output of the analog power supply voltage generation circuit can be as close as possible to the target voltage required by the high-speed circuit under different process angles and temperatures.
[0068] Taking TSMC 28nm as an example, this invention verifies the application effect of the analog power supply voltage generation circuit by changing the process angle and temperature. As shown in the table below, the analog power supply voltage VDDR will follow the temperature and process angle changes, so that the delay change of the clock circuit it drives remains within a small range.
[0069] Table 1. Application Effects of Internal Simulated Power Supply Voltage Generation Circuit
[0070] TT,55SS,-40SS,125FF,-40FF,125VDIO(V)0.65280.86510.66540.65620.4657VDDR(V)0. 8950.96780.99780.77320.8122Delay(ps)8.10E-128.36E-128.48E-128.15E-127.63E-12 surface
[0071] In the description of this specification, the terms "an embodiment / mode," "example," etc., refer to a specific feature, structure, or characteristic described in connection with that embodiment / mode or example that is included in at least one embodiment / mode or example of this application. In this specification, the illustrative expressions of the above terms do not necessarily refer to the same embodiment / mode or example. In the description of this application, "multiple" means at least two, such as two, three, etc., unless otherwise explicitly specified.
[0072] Those skilled in the art should understand that the above descriptions are merely preferred embodiments of the present invention, and the present invention is not limited to the above embodiments. It is understood that other improvements and variations directly derived or conceived by those skilled in the art without departing from the spirit and concept of the present invention should be considered to be included within the protection scope of the present invention.
Claims
1. An internal analog power supply voltage generation circuit for high-speed chips, characterized in that, The device includes a process corner compensation circuit, a calibration circuit, a temperature compensation circuit, and an output circuit, all connected in an adaptive manner. The process corner compensation circuit generates a voltage VDIO that varies with the process corner, and the temperature compensation circuit generates a voltage VT that varies with the temperature. The output circuit outputs a voltage VDDR based on a voltage VREF, and the calibration circuit calibrates the voltage VDDR based on the voltage VREF, where the voltage VREF is the sum of the voltage VDIO and the voltage VT.
2. The internal analog power supply voltage generation circuit for high-speed chips according to claim 1, characterized in that, The process corner compensation circuit includes an NMOS transistor MN and a PMOS transistor MP; the source of the NMOS transistor MN is grounded, and the gate of the NMOS transistor MN is connected to the drain of the NMOS transistor MN, the drain of the PMOS transistor MP, and the gate of the PMOS transistor MP.
3. The internal analog power supply voltage generation circuit for high-speed chips according to claim 2, characterized in that, The temperature compensation circuit includes resistors R1 and R2, a positive temperature coefficient current source for providing a positive temperature coefficient current IPTAT, and a constant current source for providing a current ICC. The output terminal of the positive temperature coefficient current source is connected to one end of resistor R1, the input terminal of the constant current source is connected to one end of resistor R1, the output terminal of the constant current source is grounded, the other end of resistor R1 is connected to one end of resistor R2 to form the output terminal of voltage VREF, and the other end of resistor R2 is connected to the source of PMOS transistor MP.
4. The internal analog power supply voltage generation circuit for high-speed chips according to claim 3, characterized in that, The positive temperature coefficient current source includes a current mirror, a reference transistor group, resistors R4, R5, and R6, transistors Q1 and Q2, and operational amplifier U2. The current mirror includes PMOS transistors M6 and M7, and the reference transistor group includes PMOS transistors M8 and M9. The source of PMOS transistor M6 is connected to the source of PMOS transistor M8, and the drain of PMOS transistor M6 is connected to the source of PMOS transistor M7. The drain of PMOS transistor M7 forms the output terminal of the positive temperature coefficient current IPTAT. The gate of PMOS transistor M6 is connected to the gate of PMOS transistor M8, the gate of PMOS transistor M7 is connected to the gate of PMOS transistor M9, the drain of PMOS transistor M8 is connected to the source of PMOS transistor M9, and the drain of PMOS transistor M9 is connected to voltage VBG1P2V.
5. The internal analog power supply voltage generation circuit for high-speed chips according to claim 4, characterized in that, The drain of PMOS transistor M9 is connected to one end of resistors R4 and R5. The other end of resistor R4 is connected to the emitter of transistor Q1 and the inverting input of operational amplifier U2. The other end of resistor R5 is connected to the non-inverting input of operational amplifier U2 and one end of resistor R6. The other end of resistor R6 is connected to the emitter of transistor Q2. The output of operational amplifier U2 is connected to the gate of PMOS transistor M8. The base of transistor Q1 is connected to the collector of transistor Q1. The collector of transistor Q1 is connected to the collector and base of transistor Q2.
6. The internal analog power supply voltage generation circuit for high-speed chips according to claim 3, characterized in that, The output circuit includes a resistor R3, an NMOS transistor NSF1, and an NMOS transistor NSF2. The drain of the NMOS transistor NSF1 is connected to the power supply voltage, the source of the NMOS transistor NSF1 is grounded through the resistor R3, the gate of the NMOS transistor NSF1 is connected to the gate of the NMOS transistor NSF2, and the source of the NMOS transistor NSF2 forms the output terminal of the voltage VDDR.
7. The internal analog power supply voltage generation circuit for high-speed chips according to claim 6, characterized in that, The NMOS transistors NSF1 and NMOS transistors NSF2 have the same current density.
8. The internal analog power supply voltage generation circuit for high-speed chips according to claim 6, characterized in that, The calibration circuit includes an operational amplifier U1, a resistor string, a multiplexer, a comparator, and a counter. The non-inverting input of the comparator is connected to the output of voltage VREF, the inverting input of the comparator is connected to the output of voltage VDDR, the output of the comparator is connected to the control terminal of the counter, and the output of the counter is connected to the control terminal of the multiplexer.
9. The internal analog power supply voltage generation circuit for high-speed chips according to claim 8, characterized in that, The operational amplifier U1 includes PMOS transistors M3, M4, M1, M2, and M5. The source of PMOS transistor M3 is connected to the source of PMOS transistor M4, the gate of PMOS transistor M3 is connected to the gate of PMOS transistor M4, the gate of PMOS transistor M3 is connected to the drain of PMOS transistor M3, the drain of PMOS transistor M3 is connected to the drain of NMOS transistor M1, the gate of NMOS transistor M1 is connected to the output terminal of voltage VREF, the source of NMOS transistor M1 is connected to the drain of NMOS transistor M5 and the source of NMOS transistor M2, the source of NMOS transistor M5 is grounded, the drain of PMOS transistor M4 is connected to the drain of NMOS transistor M2 through a resistor series, and the gate of NMOS transistor M2 is grounded through resistor R3.
10. The internal analog power supply voltage generation circuit for high-speed chips according to claim 8, characterized in that, The resistor string includes n resistors connected in series, forming n+1 connection nodes, where n is an integer greater than 1; the multiplexer includes n+1 input terminals, each of which is connected to one of the connection nodes, and the output terminal of the multiplexer is connected to the gate of the NMOS transistor NSF1.