Broadband low noise amplifier

Abstract

The broadband low-noise amplifier comprises a first-stage common-source amplifier and a second-stage common-source amplifier which are sequentially connected between an input end Rfin and an output end RFout, and the input end of the first-stage common-source amplifier and the input end of the second-stage common-source amplifier are both connected with a direct-current power supply VDD through a biasing circuit; the utility model is suitable for a 5G communication system, a millimeter wave radar and an ultra wide band (UWB) receiver front-end module.

Description

Technical Field

[0001] This utility model relates to the field of radio frequency integrated circuit technology, and in particular to a broadband low-noise amplifier. Background Technology

[0002] Low-noise amplifiers (LNAs), as the core module of the RF receiver front-end, have their broadband performance, noise figure (NF), temperature stability, and energy efficiency ratio being key factors limiting the sensitivity of modern communication systems (such as 5G, UWB, and radar). In recent years, GaAs technology has become the preferred solution for LNA design due to its high electron mobility and low noise characteristics; however, existing technologies still face the following bottlenecks in multi-performance synergistic optimization:

[0003] 1. The contradiction between broadband matching and noise performance: Although traditional distributed amplifiers can achieve a bandwidth of 1-12.5GHz, the noise figure (NF) deteriorates to over 1.8dB, and the gain drop in the low-frequency band is particularly prominent. Although resistive feedback structures (such as multiple resistive feedback MRFB technology) can control the chip area, the NF deteriorates to over 1.5dB, and the linearity (OIP3 < 23dBm) is insufficient.

[0004] 2. Insufficient temperature stability: Existing industrial-grade solutions exhibit gain fluctuations exceeding ±3dB within a temperature range of -40℃ to 85℃, which is insufficient to meet the stringent gain consistency requirements of radar systems.

[0005] 3. Deterioration in linearity in bypass mode: Traditional bypass schemes experience a 1.5dB gain drop when the output power increases to 10dBm, leading to significant harmonic distortion and affecting the system's dynamic range. Insufficient isolation in direct-through mode can easily cause signal leakage, resulting in link self-oscillation or spurious interference.

[0006] 4. Power consumption and energy efficiency ratio limitations: The quiescent current of multi-stage amplification architecture is generally higher than 50mA@5V, which does not meet the green communication standard, and the energy efficiency ratio is only 5.8mW / dB. Utility Model Content

[0007] To address the problems existing in the prior art, the purpose of this utility model is to provide a broadband low-noise amplifier, which is applicable to 5G communication systems, millimeter-wave radar, and ultra-wideband (UWB) receiver front-end modules.

[0008] To achieve the above objectives, the technical solution adopted by this utility model is: a broadband low-noise amplifier, comprising: sequentially connected to the input terminal Rf in and output RF out The first-stage common-source amplifier and the second-stage common-source amplifier are connected to the DC power supply VDD via a bias circuit.

[0009] As a further improvement of this utility model, the first-stage common-source amplifier includes a transistor M1, a resistor R1, a capacitor C2, a resistor R2, an inductor L3, and a capacitor C3. The gate of the transistor M1 is connected to the input terminal Rf. in One end of resistor R1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the drain of transistor M1. The source of transistor M1 is connected to one end of capacitor C3 and one end of resistor R2, respectively. The other end of capacitor C3 is grounded, and the other end of resistor R2 is connected to one end of inductor L3. The other end of inductor L3 is grounded.

[0010] As a further improvement of this utility model, the gate of the transistor M1 is connected to the input terminal Rf in An input inductor L1 is connected between the input inductor L1 and the common terminal of the gate of transistor M1, and the bias circuit is connected to the bias circuit through a bias inductor L2. The common terminal of the bias inductor L2 and the bias circuit is grounded through a capacitor C1.

[0011] As a further improvement of this utility model, the second-stage common-source amplifier includes a transistor M2, a resistor R3, an inductor L4, a capacitor C6, and a capacitor C7. The gate of the transistor M2 is connected to the drain of the transistor M1 and one end of the resistor R3. The other end of the resistor R3 is connected to the bias circuit and one end of the inductor L4. The other end of the inductor L4 is connected to one end of the capacitor C6. The other end of the capacitor C6 is connected to the source of the transistor M2. The drain of the transistor M2 is connected to one end of the capacitor C7. The other end of the capacitor C7 is grounded.

[0012] As a further improvement of this utility model, a capacitor C4 is connected between the gate of transistor M2 and the drain of transistor M1. The common terminal of the drain of transistor M2 and capacitor C7 is grounded in sequence through inductor L5, inductor L6 and capacitor C5, and the common terminal of inductor L6 and capacitor C5 is connected to the common terminal of the drain of transistor M1 and capacitor C4.

[0013] As a further improvement of this utility model, the source of transistor M2 is connected to the output terminal RF via output inductor L8 and output capacitor C8 in sequence. out The source of transistor M2 and the common terminal of output inductor L8 are connected to the bias circuit via bias inductor L7. The common terminal of bias inductor L7 and the bias circuit are connected via capacitor C. 10 Grounding.

[0014] As a further improvement of this utility model, the common terminal of the output inductor L8 and the output capacitor C8 is grounded through capacitor C9.

[0015] The beneficial effects of this utility model are:

[0016] This invention solves the problem of linearity degradation in bypass mode: by using a dynamic RLC feedback network (R = 150Ω, L = 0.5-1.2nH) to suppress nonlinear distortion, OIP3 is improved to >26dBm (44% improvement over existing technologies), meeting the requirements of high dynamic range communication. It eliminates the impact of temperature drift on gain stability: a temperature-compensated bias circuit (bandgap reference source + PTAT current mirror) is designed to control gain temperature fluctuations within ±1.5dB (46% improvement over existing technologies), adapting to industrial-grade temperature ranges (-40℃-85℃). It suppresses high-frequency noise figure degradation: an input-stage parasitic capacitance compensation structure (L1 = 2.2nH series inductor) is used to offset the gate-source capacitance Cgs (180fF), achieving NF < 1.2dB across the entire 1-9GHz band. It overcomes multi-octave bandwidth limitations: based on an adjustable RLC feedback network and current multiplexing architecture, the operating bandwidth is extended to 1-9GHz (8 octaves), achieving a relative bandwidth of 160%. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the amplifier circuit structure in an embodiment of the present invention;

[0018] Figure 2 This is a noise three-temperature test diagram in an embodiment of the present invention;

[0019] Figure 3 This is an example of inputting a three-temperature test graph in an embodiment of the present invention;

[0020] Figure 4 This is an example of an embodiment of the invention that outputs a matched three-temperature test graph;

[0021] Figure 5 This is a gain three-temperature test diagram in an embodiment of the present invention;

[0022] Figure 6 This is a three-temperature test graph of OP1dB (characterizing linearity) in an embodiment of the present invention. Detailed Implementation

[0023] The embodiments of this utility model will now be described in detail with reference to the accompanying drawings.

[0024] Example

[0025] like Figure 1As shown, a broadband low-noise amplifier includes two common-source (CS) amplification stages sharing a single DC path. The input stage employs a parallel RC voltage to extend the operating frequency range of the low-noise amplifier, improve stability, and mitigate nonlinearity issues. A source-side bypass capacitor serves as a low-noise grounding mechanism for the transistors. A carefully designed series inductor is used to cancel parasitic input capacitance introduced by the gate-source junction, thereby achieving broadband input matching. The parallel inductor at the input provides a bias path for the input transistors, offering better noise performance compared to using large resistors.

[0026] The output stage employs an RLC feedback network with frequency-dependent parallel voltage feedback, further widening the operating bandwidth of the low-noise amplifier. By carefully tuning the RLC components, a positive slope gain can be achieved within the desired frequency range. A T-network configuration composed of LC components is used for output matching to ensure wideband operation. Coupling capacitors facilitate signal transmission between amplification stages, and sufficiently large inductor values ​​are chosen to prevent AC leakage while allowing DC current to flow between stages, thus contributing to DC current reuse. Smaller parallel capacitors are used to assist in inter-stage matching.

[0027] Specifically, the core components of the current multiplexing of this utility model are a two-stage common-source amplifier and C4, L5, L6 and C7.

[0028] The input inductor L1 is connected to the input terminal on one side and to the gates of L2, R1 and M1 on the other side.

[0029] The first-stage common-source amplifier mainly consists of M1, R1, C2, R2, L3, and C3;

[0030] The gate of M1 is connected to the feedback resistor R1, the bias inductor L2, and the input inductor L1; the source of M1 is connected to the bypass capacitor C3 and the resistor R2; the drain of M1 is connected to the feedback capacitor C2, the coupling capacitor C4, the inductor L6, and the capacitor C5. The coupling capacitor C4 forms the AC path between the two stages of the amplifier. L5 and L6 are chosen with sufficiently large inductance values ​​to prevent AC leakage while allowing DC current to flow between the two stages, thus facilitating the reuse of DC current. The feedback loop formed by R1 and C2 is used to adjust the S-parameters and noise of the first-stage amplifier.

[0031] The second-stage amplifier mainly consists of M2, R3, L4, C6, and C7;

[0032] The gate of M2 is connected to coupling capacitor C4 and feedback resistor R3; the drain of M2 is connected to bypass capacitor C7 and inductor L5; the source of M2 is connected to feedback capacitor C6, bias inductor L7, and output inductor L8. The feedback loop composed of R3, L4, and C6 is used to adjust the S-parameters and noise of the second-stage amplifier.

[0033] The two amplifier stages are connected in parallel with C4 via an inductor consisting of L5 and L6. L5 and L6 are designed separately because a larger inductor occupies a larger area of ​​the layout, and designing them in two parts can optimize the layout area.

[0034] C1 and C 10 As a parallel capacitor near the DC power supply, it mainly serves to filter and decouple, preventing fluctuations in the DC power supply.

[0035] In practical implementation, 1. Process implementation: 0.15μm GaAs process is used, with a chip area of ​​1.8×1.1mm. 2 .

[0036] Current reuse path: M1 and M2 share the same DC path, and a U-shaped trace is used to reduce parasitic inductance (L_para<0.05nH).

[0037] Metal layer stacking: M1→Via→M2, DC resistance <0.1Ω.

[0038] Thermal management design: Heat dissipation vias (10μm in diameter, 50μm in spacing) are provided in the power transistor area.

[0039] 2. Key parameters and component connection relationships:

[0040] Input level:

[0041] L1 (2.2nH): Connected in series between the input port and the gate of M1 to compensate for the Cgs (180fF) of M1;

[0042] C3 (1pF): Connected in parallel between the source of M1 and ground to achieve low-noise grounding;

[0043] M1 (GaAs pHEMT): Gate width W = 4 × 50 μm, gate length L = 0.15 μm.

[0044] Interstage coupling:

[0045] C4 (2pF MIM capacitor): Connects the drain of M1 and the gate of M2 to achieve AC coupling and DC isolation;

[0046] L6 (0.8nH) and L5 (1.2nH): Choose sufficiently large inductance values ​​to prevent AC leakage, while allowing DC current to flow between the two stages, thus facilitating the reuse of DC current;

[0047] C5 (100nF): Use a smaller parallel capacitor to assist in interstage matching.

[0048] Output stage:

[0049] RLC feedback network: R = 150Ω, L = 0.86nH, C = 0.5pF connected in parallel, connecting the drain and gate of M2;

[0050] LC T-type matching network: L8 = 1.5nH and C9 = 0.3pF constitute the output matching.

[0051] Bias circuit:

[0052] Bandgap reference source: generates a 1.2V reference voltage with a temperature coefficient <10ppm / ℃;

[0053] PTAT current mirror: output bias current I_bias = 8.5mA, temperature coefficient +0.1% / ℃.

[0054] 3. Testing and verification:

[0055] Frequency response test: 0.5-10GHz VNA scan: Vector network analyzer: Keysight N5227B (10MHz-67GHz);

[0056] Noise test: Keysight N8975A+N4002A noise probe was used.

[0057] To explore adaptability in industrial environments, additional tests were conducted at -40°C and +85°C. The test results for gain, input-output matching, output 1dB compression point, and noise are as follows: Figures 2-5 As shown, the changes in all parameters are within the predicted range, proving its good performance within the industrial temperature range; it also possesses excellent input matching and high OP. 1dB ,like Figure 6 As shown.

[0058] The embodiments described above merely illustrate specific implementations of this utility model, and while the descriptions are detailed, they should not be construed as limiting the scope of this utility model patent. It should be noted that those skilled in the art can make various modifications and improvements without departing from the concept of this utility model, and these modifications and improvements all fall within the protection scope of this utility model.

Claims

1. A broadband low-noise amplifier, characterized in that, include: Connected sequentially to input terminal Rf in and output RF out The first-stage common-source amplifier and the second-stage common-source amplifier are connected, and the input terminals of the first-stage common-source amplifier and the second-stage common-source amplifier are both connected to the DC power supply VDD via a bias circuit.

2. The broadband low-noise amplifier according to claim 1, characterized in that, The first-stage common-source amplifier includes transistor M1, resistor R1, capacitor C2, resistor R2, inductor L3, and capacitor C3. The gate of transistor M1 is connected to the input terminal Rf. in One end of resistor R1 is connected to one end of capacitor C2, and the other end of capacitor C2 is connected to the drain of transistor M1. The source of transistor M1 is connected to one end of capacitor C3 and one end of resistor R2, respectively. The other end of capacitor C3 is grounded, and the other end of resistor R2 is connected to one end of inductor L3. The other end of inductor L3 is grounded.

3. The broadband low-noise amplifier according to claim 2, characterized in that, The gate and input terminal Rf of transistor M1 in An input inductor L1 is connected between the input inductor L1 and the common terminal of the gate of transistor M1, and the bias circuit is connected to the bias circuit through a bias inductor L2. The common terminal of the bias inductor L2 and the bias circuit is grounded through a capacitor C1.

4. The broadband low-noise amplifier according to claim 2 or 3, characterized in that, The second-stage common-source amplifier includes transistor M2, resistor R3, inductor L4, capacitor C6, and capacitor C7. The gate of transistor M2 is connected to the drain of transistor M1 and one end of resistor R3. The other end of resistor R3 is connected to the bias circuit and one end of inductor L4. The other end of inductor L4 is connected to one end of capacitor C6. The other end of capacitor C6 is connected to the source of transistor M2. The drain of transistor M2 is connected to one end of capacitor C7. The other end of capacitor C7 is grounded.

5. The broadband low-noise amplifier according to claim 4, characterized in that, A capacitor C4 is connected between the gate of transistor M2 and the drain of transistor M1. The common terminal of the drain of transistor M2 and capacitor C7 is grounded in sequence through inductor L5, inductor L6 and capacitor C5. The common terminal of inductor L6 and capacitor C5 is connected to the common terminal of the drain of transistor M1 and capacitor C4.

6. The broadband low-noise amplifier according to claim 4, characterized in that, The source of transistor M2 is connected to the output terminal RF via output inductor L8 and output capacitor C8 in sequence. out The source of transistor M2 and the common terminal of output inductor L8 are connected to the bias circuit via bias inductor L7. The common terminal of bias inductor L7 and the bias circuit are connected via capacitor C. 10 Grounding.

7. The broadband low-noise amplifier according to claim 6, characterized in that, The common terminal of the output inductor L8 and the output capacitor C8 is grounded through capacitor C9.

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