Vertical structure LED chip for display screen

Abstract

The utility model discloses a vertical structure LED chip for a display screen, which relates to the technical field of semiconductors, and is characterized in that the cross section of a chip body is of a square structure, and the side length of the chip body ranges from 100 microns to 500 microns; the square structure is evenly divided into four areas anticlockwise according to the shape of a Chinese character'tian ', the P electrode columns are located in the third area, at most one N-type conductive column is arranged in any one of the first area, the second area and the fourth area, the small conductive columns are evenly distributed in the first area, the second area and the fourth area, the diameter range of the small conductive columns is 1-50 micrometers, and the diameter range of the small conductive columns is 1-50 micrometers. The distance between the adjacent conductive small columns ranges from 10 micrometers to 100 micrometers. According to the utility model, the square-structured chip areas are uniformly divided according to the shape of the Chinese character'tian ', and the P electrode columns, the N-type conductive columns and the small conductive columns are reasonably arranged, so that the uniformity of current distribution in the small-size vertical-structured LED chip can be effectively improved, thereby avoiding aggravation of heat effect and ensuring the luminous efficiency.

Description

Technical Field

[0001] This utility model relates to the field of semiconductor technology, and specifically to a vertical structure LED chip for display screens. Background Technology

[0002] With the rapid development of display technology, LED chips are widely used in displays due to their advantages such as high brightness, high reliability, and low power consumption. Compared with upright LED chips, vertical LED chips have better heat dissipation performance and higher luminous efficiency, thus having significant technological advantages in the display field.

[0003] However, as chip size continues to miniaturize, achieving efficient arrangement of P electrodes and internal conductive structures (N-type conductive pillars and conductive pegs) within a limited area of ​​a vertical LED chip has become a technical challenge. This is especially true in small chips with side lengths less than 1000 micrometers, where the spatial arrangement of P electrodes and N-type conductive pillars and conductive pegs is not ideal and can easily affect the uniformity of current distribution. This not only exacerbates the thermal effect of small vertical LED chips but also reduces their luminous efficiency. Utility Model Content

[0004] The purpose of this invention is to overcome the shortcomings of the prior art. This invention provides a vertical structure LED chip for display screens. By dividing the square chip area into a grid pattern and arranging P-electrode pillars, N-type conductive pillars and conductive small pillars in a reasonable manner, the uniformity of current distribution in small-sized vertical structure LED chips can be effectively improved, thereby avoiding the aggravation of thermal effects and ensuring luminous efficiency.

[0005] This utility model provides a vertical structure LED chip for a display screen, including a chip body, wherein the chip body is provided with one P electrode post, at least one N-type conductive post and multiple conductive small posts; the cross-section of the chip body is a square structure, and the side length of the square structure ranges from 100 to 500 μm;

[0006] The square structure is divided into four regions in a counterclockwise direction in a grid pattern: a first region, a second region, a third region, and a fourth region. The P-electrode post is located in the third region. At most one N-type conductive post is provided in any one of the first, second, and fourth regions. Multiple conductive posts are evenly distributed in the first, second, and fourth regions. The diameter of any conductive post ranges from 1 to 50 μm, and the spacing between adjacent conductive posts ranges from 10 to 100 μm.

[0007] Specifically, the chip body comprises, from bottom to top, an N-electrode layer, a conductive substrate, a bonding metal layer, a first passivation layer, a metal barrier layer, a metal reflective layer, a second passivation layer, a transparent conductive layer, a P-type GaN layer, an MQW light-emitting layer, an N-type GaN layer, a U-type GaN layer, and a third passivation layer.

[0008] The bonding metal layer extends into the N-type GaN layer to form at least one N-type conductive pillar, the first passivation layer extends to cover the sidewall of the N-type conductive pillar to form a first passivation sleeve, and the second passivation layer extends to cover the sidewall of the first passivation sleeve to form a second passivation sleeve.

[0009] The metal reflective layer extends through the second passivation layer to form a plurality of conductive pillars, and the upper end of any of the conductive pillars contacts the transparent conductive layer;

[0010] A P-type conductive window is formed in the chip body. The P-type conductive window extends from the surface of the third passivation layer to the metal barrier layer. The P-electrode post is formed on the metal barrier layer of the P-type conductive window. Electrode passivation sleeves are formed around the P-electrode post.

[0011] Specifically, the metal barrier layer extends to cover the exposed sidewall of the metal reflective layer to form a first barrier sleeve, the side of the first barrier sleeve is in contact with the side of the first passivation sleeve, and the upper end of the first barrier sleeve is in contact with the second passivation layer.

[0012] Specifically, the metal reflective layer comprises, from bottom to top, a TiW thin layer and an Ag thin layer, the Ag thin layer extending through the second passivation layer to form a plurality of conductive pillars.

[0013] Specifically, a first frame-shaped trench is formed in the chip body. The first frame-shaped trench extends from the surface of the U-shaped GaN layer to the surface of the second passivation layer. The first frame-shaped trench is connected to the P-shaped conductive window. The P-electrode post, the N-shaped conductive post, and the conductive pillar are all located in the inner perimeter region of the first frame-shaped trench.

[0014] The transparent conductive layer, P-type GaN layer, MQW light-emitting layer, N-type GaN layer and U-type GaN layer around the first frame-shaped trench serve as a barrier structure, and the third passivation layer extends to fill the first frame-shaped trench.

[0015] Specifically, the inclination angle of the sidewall of the first frame-shaped groove ranges from 10 to 30°.

[0016] Specifically, a frame-shaped reflective wall or a frame-shaped light-absorbing wall is arranged around the perimeter of the retaining wall structure, and the third passivation layer extends to cover the top of the frame-shaped reflective wall or the top of the frame-shaped light-absorbing wall.

[0017] Specifically, the retaining wall structure includes an inner frame retaining wall and an outer frame retaining wall arranged at intervals, and a frame-shaped reflective wall or a frame-shaped light-absorbing wall is provided between the inner frame retaining wall and the outer frame retaining wall.

[0018] Specifically, the third passivation layer at the top of the retaining wall structure protrudes to form the enclosure wall structure.

[0019] Specifically, the thickness of the P electrode post ranges from 0.5 to 1.5 μm, the thickness of the N electrode layer ranges from 0.5 to 1 μm, the thickness of the first passivation layer ranges from 300 to 1500 nm, the thickness of the second passivation layer ranges from 50 to 500 nm, the thickness of the transparent conductive layer ranges from 10 to 20 nm, and the thickness of the third passivation layer ranges from 10 to 100 nm.

[0020] Compared with the prior art, the beneficial effects of this utility model are:

[0021] This invention discloses a vertical structure LED chip for display screens. The chip has a square cross-section with a side length ranging from 100 to 500 μm, resulting in a small size. Within this small vertical structure LED chip are one P-electrode, at least one N-type conductive pillar, and multiple conductive pillars (with diameters ranging from 1 to 50 μm). The square chip area is divided into four regions (first region, second region, third region, and fourth region) in a counter-clockwise tic-tac-toe pattern. The P-electrode is located in the third region, while at most one N-type conductive pillar is located in any of the first, second, and fourth regions. The multiple conductive pillars are evenly distributed across the first, second, and fourth regions, with a spacing of 10 to 100 μm between adjacent conductive pillars. This rational arrangement of the P-electrode, N-type conductive pillar, and conductive pillars within the small vertical structure LED chip effectively improves the uniformity of current distribution, thereby avoiding exacerbating the thermal effects of the small vertical structure LED chip and ensuring its luminous efficiency. Attached Figure Description

[0022] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0023] Figure 1 This is a schematic diagram showing the arrangement of the P-type electrode post, the N-type conductive post, and the conductive micro-post in an embodiment of this utility model;

[0024] Figure 2 This is a first structural schematic diagram of the vertical LED chip in this embodiment of the present invention;

[0025] Figure 3 This is a first structural schematic diagram of the retaining wall structure in an embodiment of this utility model;

[0026] Figure 4 This is a schematic diagram of the second structure of the vertical LED chip in this embodiment of the present invention;

[0027] Figure 5 This is a schematic diagram of the third structure of the vertical LED chip in this embodiment of the present invention;

[0028] Figure 6 This is a schematic diagram of the fourth structure of the vertical LED chip in this embodiment of the present invention;

[0029] Figure 7 This is a second structural schematic diagram of the retaining wall structure in an embodiment of this utility model;

[0030] Figure 8 This is a fifth structural schematic diagram of the vertical LED chip in this embodiment of the present invention;

[0031] Figure 9 This is a sixth structural schematic diagram of the vertical LED chip in this embodiment of the present invention.

[0032] In the attached figures, 1 is a P-type electrode post; 2 is an N-type conductive post; 3 is a conductive pillar; 4 is a P-type conductive window; 5 is an electrode passivation sleeve; 6 is a first frame-shaped trench; 11 is a first region; 12 is a second region; 13 is a third region; 14 is a fourth region; 100 is an N-type electrode layer; 200 is a conductive substrate; 300 is a bonding metal layer; 410 is a first passivation layer; 411 is a first passivation sleeve; 420 is a second passivation layer; 421 is a second passivation sleeve; and 430 is a third passivation layer. Layers; 431, Enclosure structure; 500, Metal barrier layer; 510, First barrier sleeve; 600, Metal reflective layer; 610, TiW thin layer; 620, Ag thin layer; 700, Transparent conductive layer; 800, Epitaxial layer; 810, P-type GaN layer; 820, MQW light-emitting layer; 830, N-type GaN layer; 840, U-type GaN layer; 900, Barrier structure; 901, Frame-shaped inner barrier wall; 902, Frame-shaped outer barrier wall; 910, Frame-shaped shielding wall. Detailed Implementation

[0033] The technical solutions of the present utility model will be clearly and completely described below with reference to the accompanying drawings of the embodiments. Obviously, the described embodiments are only some embodiments of the present utility model, and not all embodiments. Based on the embodiments of the present utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of the present utility model.

[0034] This utility model provides a vertical structure LED chip for a display screen, including a chip body. Figure 1 This diagram illustrates the arrangement of the P-type electrode post, N-type conductive post, and conductive pillars in an embodiment of the present invention. The chip body contains one P-type electrode post 1, at least one N-type conductive post 2, and multiple conductive pillars 3. The cross-section of the chip body is square, with a side length ranging from 100 to 500 μm. The square structure is divided into a first region 11, a second region 12, a third region 13, and a fourth region 14 in a counter-clockwise zigzag pattern. The P-type electrode post 1 is located in the third region 13. At most one N-type conductive post 2 is provided in any one of the first region 11, the second region 12, and the fourth region 14. Multiple conductive pillars 3 are evenly distributed in the first region 11, the second region 12, and the fourth region 14. The diameter of any conductive pillar 3 ranges from 1 to 50 μm, and the spacing between adjacent conductive pillars 3 ranges from 10 to 100 μm.

[0035] This invention discloses a vertically structured LED chip for a display screen. The chip has a square cross-section with a side length ranging from 100 to 500 μm, making it small in size. Within this small vertically structured LED chip are one P-electrode post 1, at least one N-type conductive post 2, and multiple conductive micropillars 3 (diameter ranging from 1 to 50 μm). The square chip area is divided into four regions (first region 11, second region 12, third region 13, and fourth region 14) in a counter-clockwise crisscross pattern. The P-electrode post 1 is located in the third region 13, while the first region 11 and second region 12 are... At most one N-type conductive pillar 2 is set in any region of the fourth region 14, and multiple conductive pillars 3 are evenly distributed in the first region 11, the second region 12 and the fourth region 14, with the spacing between adjacent conductive pillars 3 ranging from 10 to 100 μm. This allows the P-electrode pillar 1, N-type conductive pillar 2 and conductive pillar 3 to be reasonably arranged in the small-sized vertical structure LED chip, which can effectively improve the uniformity of current distribution in the small-sized vertical structure LED chip, thereby avoiding the aggravation of the thermal effect of the small-sized vertical structure LED chip and ensuring the luminous efficiency of the small-sized vertical structure LED chip.

[0036] Preferably, the side length of the square structure is in the range of 300 to 305 μm, the diameter of the conductive post 3 is 10 μm, the spacing between adjacent conductive posts 3 is 25 μm, and the uniformity of current distribution is excellent.

[0037] Figure 2 This diagram illustrates a first structural schematic of a vertical LED chip according to an embodiment of the present invention. The chip body, from bottom to top, includes an N-electrode layer 100, a conductive substrate 200, a bonding metal layer 300, a first passivation layer 410, a metal barrier layer 500, a metal reflective layer 600, a second passivation layer 420, a transparent conductive layer 700, a P-type GaN layer 810, an MQW light-emitting layer 820, an N-type GaN layer 830, a U-type GaN layer 840, and a third passivation layer 430. The bonding metal layer 300 extends into the N-type GaN layer 830 to form at least one N-type conductive pillar 2. The first passivation layer 410 extends to cover the N-type... A first passivation sleeve 411 is formed on the sidewall of the conductive pillar 2, and a second passivation layer 420 extends to cover the sidewall of the first passivation sleeve 411 to form a second passivation sleeve 421; the metal reflective layer 600 extends through the second passivation layer 420 to form a plurality of conductive pillars 3, and the upper end of any conductive pillar 3 contacts the transparent conductive layer 700; a P-type conductive window 4 is formed in the chip body, the P-type conductive window 4 extends from the surface of the third passivation layer 430 to the metal barrier layer 500, the P-electrode pillar 1 is formed on the metal barrier layer 500 of the P-type conductive window 4, and an electrode passivation sleeve 5 is formed around the P-electrode pillar 1.

[0038] When the vertical structure LED chip emits light, the current path is as follows: P-electrode post 1 → metal blocking layer 500 → metal reflective layer 600 → conductive post 3 → transparent conductive layer 700 → P-type GaN layer 810 → MQW light-emitting layer 820 → N-type GaN layer 830 → N-type conductive post 2 → metal bonding layer → conductive substrate 200 → N-electrode layer 100.

[0039] The N-electrode layer 100 and the P-electrode post 1 are located on opposite sides of the conductive substrate 200. During operation, no current accumulation occurs between the N-electrode layer 100 and the P-electrode post 1, meaning no electric field is generated between them. This gives the vertical LED chip excellent resistance to ion migration and hydrolysis, maintaining good stability and a low failure rate under various environments. Furthermore, the P-electrode post 1 is located on the side of the MQW light-emitting layer 820, avoiding the light-emitting surface of the vertical LED chip and thus preventing partial obstruction of the light-emitting area, ensuring the effective luminous efficiency of the vertical LED chip. In addition, the N-electrode layer 100 is laid flat on the bottom of the entire conductive substrate 200, allowing direct mounting onto the corresponding substrate without the need for gold wire bonding at the N-electrode terminal.

[0040] For further details, please refer to Figure 2 The metal barrier layer 500 extends to cover the exposed sidewall of the metal reflective layer 600 to form a first barrier sleeve 510. The side of the first barrier sleeve 510 is in contact with the side of the first passivation sleeve 411, and the upper end of the first barrier sleeve 510 is in contact with the second passivation layer 420. The first barrier sleeve 510 can effectively cover the exposed sidewall of the metal reflective layer 600, preventing the migration and diffusion of metal components.

[0041] In some specific embodiments, please refer to Figure 2 The metal reflective layer 600 comprises, from bottom to top, a TiW thin layer 610 and an Ag thin layer 620 sequentially disposed. The Ag thin layer 620 extends through the second passivation layer 420 to form a plurality of conductive pillars 3. The Ag thin layer 620 can effectively reflect light, and the conductive pillars 3 formed by the extension of the Ag thin layer 620 have good conductivity, which can effectively guide current injection into the transparent conductive layer 700; the TiW thin layer 610 has good mechanical strength, which can effectively protect the Ag thin layer 620.

[0042] Specifically, the thickness of the Ag thin layer 620 ranges from 50 to 250 nm, and the thickness of the TiW thin layer 610 ranges from 100 to 400 nm; preferably, the thickness of the Ag thin layer 620 is 180 nm, and the thickness of the TiW thin layer 610 is 250 nm.

[0043] In some specific embodiments, please refer to Figure 1 The multiple conductive pillars 3 are distributed in a rhomboid shape, forming a dense and uniform current shunt path, which helps to further reduce the difference in current distribution.

[0044] Figure 3 This shows a first structural schematic diagram of the retaining wall structure in an embodiment of the present invention. Figure 4This diagram illustrates a second structural schematic of a vertical LED chip according to an embodiment of the present invention. A first frame-shaped trench 6 is formed in the chip body, extending from the surface of the U-shaped GaN layer 840 to the surface of the second passivation layer 420. The first frame-shaped trench 6 communicates with the P-shaped conductive window 4. The P-electrode post 1, the N-shaped conductive post 2, and the conductive pillar 3 are all located within the inner periphery of the first frame-shaped trench 6. The transparent conductive layer 700, the P-shaped GaN layer 810, the MQW light-emitting layer 820, the N-shaped GaN layer 830, and the U-shaped GaN layer 840 surrounding the first frame-shaped trench 6 serve as a barrier structure 900. The third passivation layer 430 extends to fill the first frame-shaped trench 6. The barrier structure 900 isolates the chip's light-emitting area (i.e., the inner periphery of the first frame-shaped trench 6) from the chip dicing path (not shown in the diagram, located outside the barrier structure 900), reducing damage to the chip's light-emitting area during chip dicing.

[0045] Optional, Figure 5 The diagram shows a third structural schematic of the vertical LED chip in this embodiment of the present invention. The inclination angle of the sidewall of the first frame-shaped groove 6 is in the range of 10 to 30°. This is the angle at which the sidewall of the first frame-shaped groove 6 deviates from the vertical plane, so that the inner sidewall of the baffle structure 900 has a certain inclination angle, which is beneficial to redirect the light scattered laterally from the chip's light-emitting area back to the front of the chip.

[0046] Optional, Figure 6 This diagram illustrates a fourth structural design of the vertical LED chip in this embodiment of the invention. A frame-shaped shielding wall 910 surrounds the periphery of the barrier structure 900. The frame-shaped shielding wall 910 is either a frame-shaped reflective wall or a frame-shaped light-absorbing wall. The third passivation layer 430 extends to cover the top of the frame-shaped reflective wall or the top of the frame-shaped light-absorbing wall. The frame-shaped reflective wall or frame-shaped light-absorbing wall can shield the side light emission from the chip's light-emitting area, preventing optical crosstalk between the vertical LED chips in the display screen and thus improving the display quality.

[0047] Optional, Figure 7 This shows a second structural schematic diagram of the retaining wall structure in an embodiment of the present invention. Figure 8The diagram shows a fifth structural schematic of a vertical LED chip according to an embodiment of the present invention. The barrier structure 900 includes an inner frame-shaped barrier 901 and an outer frame-shaped barrier 902 spaced apart. A frame-shaped shielding wall 910 is provided between the inner frame-shaped barrier 901 and the outer frame-shaped barrier 902. The frame-shaped shielding wall 910 is either a frame-shaped reflective wall or a frame-shaped light-absorbing wall. The inner frame-shaped barrier 901 and the outer frame-shaped barrier 902 sandwich the frame-shaped reflective wall or the frame-shaped light-absorbing wall in the middle, which can effectively protect the frame-shaped reflective wall or the frame-shaped light-absorbing wall and reduce damage to the frame-shaped reflective wall or the frame-shaped light-absorbing wall during chip cutting.

[0048] The frame-shaped reflective wall is made of materials including but not limited to Ag or Al, while the frame-shaped light-absorbing wall is made of materials including but not limited to Ni, Ti or Cr.

[0049] Figure 9 The diagram shows a sixth structural schematic of a vertical LED chip in an embodiment of the present invention. The third passivation layer 430 on the top of the barrier structure 900 protrudes to form a wall structure 431. The wall structure 431 can provide anchoring points for subsequent encapsulation materials (such as epoxy resin) and enhance interface adhesion.

[0050] Specifically, the protrusion height of the wall structure 431 ranges from 20 to 50 nm. If the protrusion height of the wall structure 431 is greater than 50 nm, the structural stability will be reduced, and it will be easy to break or collapse under the action of external force. If the protrusion height of the wall structure 431 is less than 20 nm, it will be difficult to play an anchoring role.

[0051] In some specific embodiments, please refer to Figure 1 The P-type GaN layer 810, the MQW light-emitting layer 820, the N-type GaN layer 830, and the U-type GaN layer 840 constitute an epitaxial layer 800. An N-type conductive opening is formed in the epitaxial layer 800. The N-type conductive opening extends from the P-type GaN layer 810 to the N-type GaN layer 830. The first passivation sleeve 411, the second passivation sleeve 421, and the N-type conductive pillar 2 are located in the N-type conductive opening. The thickness of the P-type GaN layer 810 is h1, and the thickness of the MQW light-emitting layer 820 is h2. Therefore, the depth H of the N-type conductive opening is 1.4*(h1+h2), ensuring that the N-type conductive pillar 2 can penetrate into the N-type GaN layer 830 by a sufficient distance.

[0052] Specifically, the overall diameter of the N-type conductive opening ranges from 20 to 200 μm, and its diameter gradually decreases along the direction from the P-type GaN layer 810 to the N-type GaN layer 830, which facilitates the forming of the first passivation sleeve 411 and the second passivation sleeve 421.

[0053] Furthermore, the overall diameter of the N-type conductive post 2 ranges from 10 to 100 μm, matching the gradual diameter of the N-type conductive opening, thus exhibiting good current conduction efficiency.

[0054] In some specific embodiments, the thickness of the first passivation layer 410 ranges from 300 to 1500 nm, and the first passivation layer 410 can be a SiO2 layer or a SiN layer. x One or more combinations of the first passivation layer 410 and the Al2O3 layer can effectively insulate and isolate the bonded metal layer 300 and the metal barrier layer 500, and the first passivation sleeve 411 formed by the extension of the first passivation layer 410 can effectively insulate and isolate the N-type conductive pillar 2 and the first barrier sleeve 510; preferably, the first passivation layer 410 is a SiO2 layer with a thickness of 600nm.

[0055] In some specific embodiments, the metal barrier layer 500 is a first stacked structure, which is one or more of the following: Ni layer, Ti layer, Au layer, Pt layer, Ru layer, La layer, Cr layer, and Al layer. This first stacked structure can not only effectively cover the metal reflective layer 600, but also serve as the main structure of the fan-out P electrode post 1.

[0056] In some specific embodiments, the thickness of the second passivation layer 420 ranges from 50 to 500 nm, and the second passivation layer 420 can be a SiO2 layer or a SiN layer. x One or more combinations of the first passivation layer and the second passivation layer 420, including the first passivation layer and the second passivation layer 700, can effectively insulate and isolate the metal reflective layer 600 and the transparent conductive layer 700, so that the metal reflective layer 600 and the transparent conductive layer 700 can only be connected through the conductive pillars 3, which is beneficial to the uniform dispersion of current injected into the transparent conductive layer 700; the second passivation layer 420 extended to form the second passivation sleeve 421 can effectively passivate and protect the sidewall of the N-type conductive opening, and avoid leakage current from the sidewall of the N-type conductive opening; preferably, the second passivation layer 420 is a SiO2 layer with a thickness of 400nm.

[0057] In some specific embodiments, the thickness of the transparent conductive layer 700 ranges from 10 to 20 nm, and the transparent conductive layer 700 is an ITO layer; preferably, the thickness of the ITO layer is 15 nm, balancing light transmittance and current spreading efficiency.

[0058] In some specific embodiments, the thickness of the third passivation layer 430 ranges from 10 to 100 nm, and the third passivation layer 430 is a SiO2 layer or an Al2O3 layer, which can effectively protect the top of the U-shaped GaN layer 840, the sidewalls of the first frame-shaped trench 6, etc.; preferably, the thickness of the third passivation layer 430 is 50 nm, and the third passivation layer 430 is a SiO2 layer.

[0059] In some specific embodiments, the P electrode post 1 is a second stacked structure, which is a stack of Cr / Ti / Ni / Au layers with a thickness ranging from 0.5 to 1.5 μm, exhibiting good conductivity and structural stability; preferably 1 μm.

[0060] In some specific embodiments, the N electrode layer 100 is a third stacked structure, which is a stack of Cr / Ti / Ni / Au layers with a thickness ranging from 0.5 to 1 μm. It has good conductivity, high heat dissipation performance, and good structural stability; preferably 0.8 μm.

[0061] In some specific embodiments, an N-type conductive pillar 2 is provided in any one of the first region 11, the second region 12 and the fourth region 14, which results in good uniformity of current distribution and high luminous efficiency of the chip.

[0062] This invention discloses a vertically structured LED chip for a display screen. The chip has a square cross-section with a side length ranging from 100 to 500 μm, making it small in size. Within this small vertically structured LED chip are one P-electrode post 1, at least one N-type conductive post 2, and multiple conductive micropillars 3 (diameter ranging from 1 to 50 μm). The square chip area is divided into four regions (first region 11, second region 12, third region 13, and fourth region 14) in a counter-clockwise crisscross pattern. The P-electrode post 1 is located in the third region 13, while the first region 11 and second region 12 are... At most one N-type conductive pillar 2 is set in any region of the fourth region 14, and multiple conductive pillars 3 are evenly distributed in the first region 11, the second region 12 and the fourth region 14, with the spacing between adjacent conductive pillars 3 ranging from 10 to 100 μm. This allows the P-electrode pillar 1, N-type conductive pillar 2 and conductive pillar 3 to be reasonably arranged in the small-sized vertical structure LED chip, which can effectively improve the uniformity of current distribution in the small-sized vertical structure LED chip, thereby avoiding the aggravation of the thermal effect of the small-sized vertical structure LED chip and ensuring the luminous efficiency of the small-sized vertical structure LED chip.

[0063] Furthermore, in the vertical structure LED chip for display screen of this invention, the N-electrode layer 100 and the P-electrode post 1 are located on opposite sides of the conductive substrate 200. During operation, no current accumulation occurs between the N-electrode layer 100 and the P-electrode post 1, meaning no electric field is generated between them. This gives the vertical structure LED chip excellent resistance to ion migration and hydrolysis, maintaining good stability under different environments and resulting in a low failure rate. The P-electrode post 1 is located on the side of the MQW light-emitting layer 820, avoiding the light-emitting surface of the vertical structure LED chip, thus preventing partial obstruction of the light-emitting area and ensuring the effective luminous efficiency of the vertical structure LED chip. The N-electrode layer 100 is laid flat on the bottom of the entire conductive substrate 200 and can be directly mounted onto the corresponding substrate without the need for gold wire bonding at the N-electrode terminal.

[0064] Furthermore, the vertical structure LED chip for display screens of this invention features a barrier structure 900, which, in conjunction with a frame-shaped reflective wall or frame-shaped light-absorbing wall, not only reduces damage to the chip's light-emitting area during chip cutting but also effectively shields the side light emission from the chip's light-emitting area, preventing optical crosstalk from occurring in the vertical structure LED chip within the display screen, thereby improving the display quality. The frame-shaped reflective wall or frame-shaped light-absorbing wall is sandwiched between the inner frame barrier 901 and the outer frame barrier 902, effectively protecting the frame-shaped reflective wall or frame-shaped light-absorbing wall and reducing damage during chip cutting. Additionally, the third passivation layer 430 at the top of the barrier structure 900 protrudes to form a surrounding wall structure 431, which provides anchoring points for subsequent encapsulation materials (such as epoxy resin), enhancing interface adhesion.

[0065] After testing, the optimized small-sized vertical structure LED chip has a junction temperature that is reduced by at least 5.46% and a brightness that is increased by at least 8.10%. Moreover, compared with the same size upright structure LED chip and flip structure LED chip, the vertical structure LED chip of this invention has a significant advantage in luminous efficiency.

[0066] The above provides a detailed description of a vertical structure LED chip for a display screen provided by the embodiments of this utility model. Specific examples have been used to illustrate the principle and implementation of this utility model. The description of the above embodiments is only for the purpose of helping to understand the method and core idea of ​​this utility model. At the same time, for those skilled in the art, there will be changes in the specific implementation and application scope based on the idea of ​​this utility model. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. A vertically structured LED chip for a display screen, characterized in that, The chip body includes a P-type electrode post, at least one N-type conductive post, and multiple conductive micropillars. The cross-section of the chip body is square, and the side length of the square structure ranges from 100 to 500 μm. The square structure is divided into four regions in a counterclockwise direction in a grid pattern: a first region, a second region, a third region, and a fourth region. The P-electrode post is located in the third region. At most one N-type conductive post is provided in any one of the first, second, and fourth regions. Multiple conductive posts are evenly distributed in the first, second, and fourth regions. The diameter of any conductive post ranges from 1 to 50 μm, and the spacing between adjacent conductive posts ranges from 10 to 100 μm.

2. The vertical structure LED chip for a display screen as described in claim 1, characterized in that, The chip body comprises, from bottom to top, an N-electrode layer, a conductive substrate, a bonding metal layer, a first passivation layer, a metal barrier layer, a metal reflective layer, a second passivation layer, a transparent conductive layer, a P-type GaN layer, an MQW light-emitting layer, an N-type GaN layer, a U-type GaN layer, and a third passivation layer. The bonding metal layer extends into the N-type GaN layer to form at least one N-type conductive pillar, the first passivation layer extends to cover the sidewall of the N-type conductive pillar to form a first passivation sleeve, and the second passivation layer extends to cover the sidewall of the first passivation sleeve to form a second passivation sleeve. The metal reflective layer extends through the second passivation layer to form a plurality of conductive pillars, and the upper end of any of the conductive pillars contacts the transparent conductive layer; A P-type conductive window is formed in the chip body. The P-type conductive window extends from the surface of the third passivation layer to the metal barrier layer. The P-electrode post is formed on the metal barrier layer of the P-type conductive window. Electrode passivation sleeves are formed around the P-electrode post.

3. The vertical structure LED chip for a display screen as described in claim 2, characterized in that, The metal barrier layer extends to cover the exposed sidewall of the metal reflective layer to form a first barrier sleeve. The side of the first barrier sleeve is in contact with the side of the first passivation sleeve, and the upper end of the first barrier sleeve is in contact with the second passivation layer.

4. The vertical structure LED chip for a display screen as described in claim 2, characterized in that, The metal reflective layer comprises, from bottom to top, a TiW thin layer and an Ag thin layer, the Ag thin layer extending through the second passivation layer to form a plurality of conductive pillars.

5. The vertical structure LED chip for a display screen as described in claim 2, characterized in that, The chip body has a first frame-shaped trench that extends from the surface of the U-shaped GaN layer to the surface of the second passivation layer. The first frame-shaped trench is connected to the P-shaped conductive window. The P-electrode post, the N-shaped conductive post, and the conductive pillar are all located in the inner perimeter region of the first frame-shaped trench. The transparent conductive layer, P-type GaN layer, MQW light-emitting layer, N-type GaN layer and U-type GaN layer around the first frame-shaped trench serve as a barrier structure, and the third passivation layer extends to fill the first frame-shaped trench.

6. The vertical structure LED chip for a display screen as described in claim 5, characterized in that, The inclination angle of the sidewall of the first frame-shaped groove ranges from 10 to 30°.

7. The vertical structure LED chip for a display screen as described in claim 5, characterized in that, The retaining wall structure is surrounded by a frame-shaped reflective wall or a frame-shaped light-absorbing wall, and the third passivation layer extends to cover the top of the frame-shaped reflective wall or the top of the frame-shaped light-absorbing wall.

8. The vertical structure LED chip for a display screen as described in claim 5, characterized in that, The retaining wall structure includes an inner frame-shaped retaining wall and an outer frame-shaped retaining wall spaced apart, with a frame-shaped reflective wall or a frame-shaped light-absorbing wall provided between the inner frame-shaped retaining wall and the outer frame-shaped retaining wall.

9. The vertical structure LED chip for a display screen as described in claim 5, characterized in that, The third passivation layer at the top of the retaining wall structure protrudes to form the enclosure wall structure.

10. The vertical structure LED chip for a display screen as described in claim 2, characterized in that, The thickness of the P electrode post ranges from 0.5 to 1.5 μm, the thickness of the N electrode layer ranges from 0.5 to 1 μm, the thickness of the first passivation layer ranges from 300 to 1500 nm, the thickness of the second passivation layer ranges from 50 to 500 nm, the thickness of the transparent conductive layer ranges from 10 to 20 nm, and the thickness of the third passivation layer ranges from 10 to 100 nm.

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