tiled screen
By using an interlaced gate drive circuit design and data line layout, the problem of poor display on splicing screens was solved, achieving a more uniform display effect.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- BOE TECHNOLOGY GROUP CO LTD
- Filing Date
- 2025-06-18
- Publication Date
- 2026-06-12
Smart Images
Figure CN224354970U_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of display technology, and more particularly to a video wall. Background Technology
[0002] In related technologies, video walls include multiple display panels that can be distributed along rows and columns. Each display panel scans line by line from top to bottom. However, in video walls, there is an interval of A-1 rows of pixel driving circuit scanning time between the scanning time of the last row of pixel driving circuits in the previous display panel and the scanning time of the first row of pixel driving circuits in the adjacent next display panel, where A is the total number of rows in the previous display panel. This results in noticeable display defects at the splicing position between the previous and next display panels.
[0003] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Utility Model Content
[0004] This disclosure first provides a video wall, wherein the video wall includes at least a plurality of display panels distributed along a second direction, the display areas of the display panels include a first display area and a second display area distributed along the second direction, and the display panels further include:
[0005] Multiple pixel driving circuits are located in the display area, and the multiple pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting;
[0006] A gate driving circuit, the gate driving circuit including a multi-stage shift register unit;
[0007] The first-level shift register unit to the nth-level shift register unit are used to provide gate drive signals to the pixel driving circuit in the first display area, and in the first-level shift register unit to the nth-level shift register unit, the output terminal of the upper-level shift register unit is connected to the input terminal of the lower-level shift register unit.
[0008] The (n+1)th stage shift register unit to the last stage shift register unit are used to provide gate drive signals to the pixel driving circuit in the second display area, and in the (n+1)th stage shift register unit to the last stage shift register unit, the output terminal of the lower stage shift register unit is connected to the input terminal of the upper stage shift register unit;
[0009] n is a positive integer greater than 1.
[0010] In one exemplary embodiment of this disclosure, the input terminals of the first-stage shift register unit and the last-stage shift register unit are respectively connected to different initialization signal terminals.
[0011] In one exemplary embodiment of this disclosure, the input terminals of the first-stage shift register unit and the last-stage shift register unit are connected to the same initialization signal terminal.
[0012] In one exemplary embodiment of this disclosure, the display panel further includes:
[0013] Multiple data lines extend along a second direction, including multiple first data lines and multiple second data lines. The first data lines are used to provide data signals to the pixel driving circuit in the first display area, and the second data lines are used to provide data signals to the pixel driving circuit in the second display area.
[0014] In one exemplary embodiment of this disclosure, the second direction is a column direction, and each column of the pixel driving circuit is provided with a first data line and a second data line. The display panel further includes a source driving chip. The first data line is used to provide data signals to the pixel driving circuit corresponding to it and located in the first display area, and the second data line is used to provide data signals to the pixel driving circuit corresponding to it and located in the second display area. The first data line and the second data line are respectively connected to different output terminals of the source driving chip.
[0015] In one exemplary embodiment of this disclosure, the display panel further includes:
[0016] A source driver chip, which provides data signals to the data line through its output terminal;
[0017] A gating circuit is connected between the same output terminal of the source driver chip and the first data line and the second data line. The gating circuit is used to respond to a gating signal to connect the output terminal of the source driver chip and the first data line and the second data line in a time-division manner.
[0018] In one exemplary embodiment of this disclosure, the second direction is a column direction, and each column of the pixel driving circuit is provided with a first data line and a second data line. The first data line is used to provide a data signal to the pixel driving circuit corresponding to it and located in the first display area, and the second data line is used to provide a data signal to the pixel driving circuit corresponding to it and located in the second display area. The gating circuit connects the first data line and the second data line corresponding to the same column of pixel driving circuits.
[0019] In one exemplary embodiment of this disclosure, the display panel further includes:
[0020] Multiple data lines extending along a second direction are provided to provide data signals to the pixel driving circuit.
[0021] Multiple source driver chips, including a first source driver chip and a second source driver chip, are located on opposite sides of the display area in the second direction. Some of the data lines are connected to the first source driver chip through one end close to the first source driver chip, and some of the data lines are connected to the second source driver chip through one end close to the second source driver chip.
[0022] In one exemplary embodiment of this disclosure, the data lines connecting the first source driver chip and the data lines connecting the second source driver chip are alternately distributed along the first direction.
[0023] In one exemplary embodiment of this disclosure, the display panel includes a plurality of pixel units, which are arrayed along a first direction and a second direction, and each pixel unit includes a plurality of adjacent pixel driving circuits distributed along the first direction.
[0024] The second direction is the column direction, and the pixel units located in adjacent columns are respectively connected to the first source driver chip and the second source driver chip via data lines.
[0025] In one exemplary embodiment of this disclosure, the display panel further includes:
[0026] A first clock signal line group, comprising at least one clock signal line, wherein the clock signal line in the first clock signal line group is used to provide clock signals to the first-level shift register unit to the nth-level shift register unit;
[0027] The second clock signal line group includes at least one clock signal line, which is used to provide clock signals to the (n+1)th stage shift register unit to the last stage shift register unit.
[0028] In one exemplary embodiment of this disclosure, the display panel further includes:
[0029] A clock signal line group includes at least one clock signal line, which is used to provide a clock signal to the gate drive circuit.
[0030] The first-level shift register unit is the first-level shift register unit, the last-level shift register unit is the m-th level shift register unit, and the same clock signal terminals of the (1+x)-th level shift register unit and the (mx)-th level shift register unit are connected to the same clock signal line, where m is a positive integer greater than n and x is an integer greater than or equal to 0.
[0031] In one exemplary embodiment of this disclosure, the gate driving circuit includes m shift register units;
[0032] When m is even, n equals m / 2;
[0033] When m is odd, n equals (m+1) / 2 or n equals (m-1) / 2.
[0034] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description
[0035] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.
[0036] Figure 1 This is a structural schematic diagram of a video wall in related technologies;
[0037] Figure 2 This is a schematic diagram of the structure of an exemplary embodiment of the splicing screen disclosed herein;
[0038] Figure 3 This is a schematic diagram of the display panel structure in an exemplary embodiment of the splicing screen disclosed herein;
[0039] Figure 4 This is a timing diagram of each node in a driving method for the display panel in the splicing screen disclosed herein;
[0040] Figure 5 This is a timing diagram of each node in another driving method for the display panel in the splicing screen disclosed herein;
[0041] Figure 6 This is a schematic diagram of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein;
[0042] Figure 7 for Figure 6 The diagram shows a schematic representation of the shift register unit in an exemplary embodiment of the display panel.
[0043] Figure 8 for Figure 7 The timing diagram of each node in a driving method of the gate driving circuit formed by the shift register unit shown;
[0044] Figure 9 This is a schematic diagram of the pixel circuit in an exemplary embodiment of the display panel of this disclosure;
[0045] Figure 10 for Figure 9 The timing diagram of signals at each node in a driving method of the pixel circuit shown is shown.
[0046] Figure 11 for Figure 6 A schematic diagram of the shift register unit in another exemplary embodiment of the display panel shown;
[0047] Figure 12 for Figure 11 The timing diagram of each node in a driving method of the gate driving circuit formed by the shift register unit shown;
[0048] Figure 13 This is a schematic diagram of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein;
[0049] Figure 14 for Figure 13 The diagram shows the timing of each node in a driving method for the display panel.
[0050] Figure 15 This is a schematic diagram of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein;
[0051] Figure 16 for Figure 15 The diagram shows the timing of each node in a driving method for the display panel.
[0052] Figure 17 This is a schematic diagram of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein;
[0053] Figure 18 for Figure 17 The diagram shows the timing of each node in a driving method for the display panel.
[0054] Figure 19 This is a schematic diagram of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein;
[0055] Figure 20 This is a schematic diagram of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein;
[0056] Figure 21 This is a schematic diagram of the structure of the display panel in another exemplary embodiment of the splicing screen disclosed herein. Detailed Implementation
[0057] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, they are provided so that this disclosure will be more comprehensive and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore their detailed description will be omitted.
[0058] The terms “a,” “one,” and “the” are used to indicate the existence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended meaning of inclusion and that there may be other elements / components / etc. in addition to the listed elements / components / etc.
[0059] In the description of this disclosure, unless otherwise expressly specified and limited, the terms “first” and “second” are used for descriptive purposes only and should not be construed as indicating or implying relative importance; the term “multiple” refers to two or more; and the term “and / or” includes any and all combinations of one or more associated listed items. In particular, references to “the / described” object or “a” object are also intended to indicate one of a possible plurality of such objects.
[0060] Unless otherwise specified or stated, the terms "connection," "fixed," etc., should be interpreted broadly. For example, "connection" can be a fixed connection, a detachable connection, an integral connection, an electrical connection, or a signal connection; "connection" can be a direct connection or an indirect connection through an intermediate medium. Those skilled in the art can understand the specific meaning of the above terms in this disclosure according to the specific circumstances.
[0061] Furthermore, it should be understood that the directional terms such as "upper," "lower," "inner," and "outer" described in the exemplary embodiments of this disclosure are used to describe the angles shown in the accompanying drawings and should not be construed as limiting the exemplary embodiments of this disclosure. It should also be understood that, in the context of an element or feature being connected to one or more "upper," "lower," "inner," or "outer" elements, it can be directly connected to one or more "upper," "lower," "inner," or "outer" elements, or indirectly connected to one or more "upper," "lower," "inner," or "outer" elements through intermediate elements.
[0062] like Figure 1The diagram shown illustrates the structure of a video wall in the related art. This video wall includes multiple display panels Pl1, Pl2, Pl3, and Pl4. These display panels are arranged in an array along a first direction X and a second direction Y, where the first direction X and the second direction Y intersect. For example, the first direction X can be a row direction, and the second direction Y can be a column direction. In the related art, each display panel scans row by row along the same direction. Figure 1 As shown, each display panel scans line by line from top to bottom. However, in a video wall, there is an interval of A-1 rows of pixel driving circuit scanning time between the scanning time of the last row of pixel driving circuits on display panel Pl1 and the scanning time of the first row of pixel driving circuits on display panel Pl3, where A is the total number of rows on display panel Pl1. This means that the first row of pixel driving circuits on display panel Pl3 has already written new data signals, while the last row of pixel driving circuits on display panel Pl1 is still maintaining the data signals from the previous frame. This technology can cause noticeable display defects at the splicing position of display panels Pl1 and Pl3 in a video wall.
[0063] Based on this, this exemplary embodiment provides a video wall, such as... Figure 2 , Figure 3 As shown, Figure 2 This is a schematic diagram illustrating the structure of an exemplary embodiment of the splicing screen disclosed herein. Figure 3 This is a schematic diagram of the structure of the display panel in an exemplary embodiment of the splicing screen disclosed herein.
[0064] The splicing screen includes at least a plurality of display panels Pl1 and Pl2 distributed along the second direction. The display area AA of the display panel includes a first display area AA1 and a second display area AA2 distributed along the second direction Y. The display panel also includes: a plurality of pixel driving circuits Pix and a gate driving circuit Cg. The plurality of pixel driving circuits Pix are located in the display area AA. The plurality of pixel driving circuits Pix are arrayed along the first direction X and the second direction Y. The first direction X and the second direction Y intersect. For example, the first direction X can be a row direction and the second direction Y can be a column direction. The gate driving circuit Cg includes a multi-stage shift register unit GOA. The first-stage shift register unit GOA(1) to the nth-stage shift register unit GOA(n) are used to provide gate driving signals to the pixel driving circuit in the first display area AA1. In the first-stage shift register unit GOA(1) to the nth-stage shift register unit GOA(n), the output terminal out of the upper-stage shift register unit is connected to the input terminal in of the lower-stage shift register unit. The (n+1)th-stage shift register unit GOA(n+1) to the last-stage shift register unit GOA(m) are used to provide gate driving signals to the pixel driving circuit in the second display area AA2. In the (n+1)th-stage shift register unit GOA(n+1) to the last-stage shift register unit GOA(m), the output terminal of the lower-stage shift register unit is connected to the input terminal of the upper-stage shift register unit. n is a positive integer greater than 1, and m is a positive integer greater than n.
[0065] In this exemplary embodiment, the first-level shift register unit GOA(1) to the nth-level shift register unit GOA(n) can provide gate drive signals to the pixel driving circuit Pix row by row from top to bottom, and the last-level shift register unit GOA(m) to the (n+1)th-level shift register unit GOA(n+1) can provide gate drive signals to the pixel driving circuit Pix row by row from bottom to top. This setting can reduce the time difference between the scanning time of the last row pixel driving circuit in display panel P11 and the first row pixel driving circuit in display panel P12, thereby improving the display effect of the splicing screen.
[0066] In this exemplary embodiment, as Figure 3 As shown, the input terminal in of the first-stage shift register unit GOA(1) and the input terminal in of the last-stage shift register unit GOA(m) are connected to different initialization signal terminals. For example, the input terminal in of the first-stage shift register unit GOA(1) is connected to the first initialization signal terminal STV1, and the input terminal in of the last-stage shift register unit GOA(m) is connected to the second initialization signal terminal STV2.
[0067] like Figure 4The diagram shows the timing of each node in a driving method for a display panel in the splicing screen disclosed herein. STV1 is the timing diagram of the signals at the first initialization signal terminal, STV2 is the timing diagram of the signals at the second initialization signal terminal, out1 represents the timing diagram of the signals at the output terminal of the first-stage shift register unit GOA(1), out1 represents the timing diagram of the signals at the output terminal of the second-stage shift register unit GOA(2), out(n) represents the timing diagram of the signals at the output terminal of the nth-stage shift register unit GOA(n), out(n+1) represents the timing diagram of the signals at the output terminal of the (n+1)th-stage shift register unit GOA(n+1), out(m-1) represents the timing diagram of the signals at the output terminal of the (m-1)th-stage shift register unit GOA(m-1), and out(m) represents the timing diagram of the signals at the output terminal of the mth-stage shift register unit GOA(m).
[0068] like Figure 4 As shown, the first initialization signal terminal STV1 and the second initialization signal terminal STV2 output input signals sequentially, with the first initialization signal terminal STV1 outputting an input signal earlier than the second initialization signal terminal STV2. Correspondingly, the (1+x)th stage shift register unit and the (mx)th stage shift register unit output gate drive signals sequentially, with the (mx)th stage shift register unit outputting its gate drive signal later than the (1+x)th stage shift register unit but earlier than the (1+x+1)th stage shift register unit, where x is an integer greater than or equal to 0. For example, when x equals 0, the (m)th stage shift register unit outputs its gate drive signal later than the first stage shift register unit but earlier than the second stage shift register unit; when x equals 1, the (m-1)th stage shift register unit outputs its gate drive signal later than the second stage shift register unit but earlier than the third stage shift register unit. Similarly, the gate driving circuit scans the pixel driving circuit line by line from the top and bottom sides of the display panel toward the center.
[0069] like Figure 4 As shown, when m is even, n can be equal to m / 2; when m is odd, n can be equal to (m+1) / 2.
[0070] like Figure 5The diagram shows the timing diagram of each node in another driving method of the display panel in the splicing screen of this disclosure. Among them, STV1 is the timing diagram of the signal on the first initialization signal terminal, STV2 is the timing diagram of the signal on the second initialization signal terminal, out1 represents the timing diagram of the signal on the output terminal of the first-stage shift register unit GOA(1), out2 represents the timing diagram of the signal on the output terminal of the second-stage shift register unit GOA(2), out(n) represents the timing diagram of the signal on the output terminal of the nth-stage shift register unit GOA(n), out(n+1) represents the timing diagram of the signal on the output terminal of the (n+1)th-stage shift register unit GOA(n+1), out(m-1) represents the timing diagram of the signal on the output terminal of the (m-1)th-stage shift register unit GOA(m-1), and out(m) represents the timing diagram of the signal on the output terminal of the mth-stage shift register unit GOA(m).
[0071] like Figure 5 As shown, the second initialization signal terminal STV2 and the first initialization signal terminal STV1 output input signals sequentially, with the second initialization signal terminal STV2 outputting an input signal earlier than the first initialization signal terminal STV1. Correspondingly, the (mx)th stage shift register unit and the (1+x)th stage shift register unit output gate drive signals sequentially, with the (1+x)th stage shift register unit outputting its gate drive signal later than the (mx)th stage shift register unit but earlier than the (mx-1)th stage shift register unit. For example, when x equals 0, the first stage shift register unit outputs its gate drive signal later than the mth stage shift register unit but earlier than the (m-1)th stage shift register unit. When x equals 1, the second stage shift register unit outputs its gate drive signal later than the (m-1)th stage shift register unit but earlier than the (m-2)th stage shift register unit. Similarly, the gate driving circuit scans the pixel driving circuit line by line from the top and bottom sides of the display panel toward the center.
[0072] like Figure 5 As shown, when m is even, n can be equal to m / 2; when m is odd, n can be equal to (m-1) / 2.
[0073] In this exemplary embodiment, as Figure 4 , 5 As shown, each shift register unit sequentially outputs gate drive signals, allowing the pixel drive circuit in the display panel to scan line by line. Correspondingly, as... Figure 3As shown, each column of pixel driving circuits can be equipped with a corresponding data line Da. The data line Da extends along the second direction Y and is used to provide data signals to the corresponding column of pixel driving circuits row by row.
[0074] In this exemplary embodiment, as Figure 3 As shown, the output terminal out of each shift register unit GOA provides a gate drive signal to a row of pixel driving circuits. It should be understood that in other exemplary embodiments, the output terminal out of each shift register unit GOA can also provide a gate drive signal to multiple rows of pixel driving circuits. Accordingly, each column of pixel driving circuits needs to be equipped with one or more data lines.
[0075] In this exemplary embodiment, as Figure 3 As shown, the output of the upper-level shift register unit is connected to the input of the adjacent lower-level shift register unit. It should be understood that in other exemplary embodiments, the output of the upper-level shift register unit may also be connected to the input of the lower-level shift register units that are spaced apart from each other.
[0076] like Figure 6 The diagram shown is a structural schematic of the display panel in another exemplary embodiment of the splicing screen disclosed herein. Figure 3 Based on the display panel shown, the display panel may further include: a first clock signal line group LC1 and a second clock signal line group LC2. The first clock signal line group LC1 includes at least one clock signal line, which is used to provide clock signals to the first-level shift register unit GOA(1) to the nth-level shift register unit GOA(n). The second clock signal line group LC2 includes at least one clock signal line, which is used to provide clock signals to the (n+1)th-level shift register unit GOA(n+1) to the last-level shift register unit GOA(m).
[0077] In this exemplary embodiment, as Figure 7 As shown, Figure 6The diagram shows a schematic of the shift register unit in an exemplary embodiment of the display panel. The shift register unit may include: a first input circuit 411, a second input circuit 412, a first output circuit 413, a second output circuit 414, an isolation circuit 415, a first control circuit 416, and a second control circuit 417. The first input circuit 411 is connected to a first power supply terminal VGL, a first node N1, and a first clock signal terminal ca, and is used to transmit the signal from the first power supply terminal VGL to the first node N1 in response to the signal from the first clock signal terminal ca. The second input circuit 412 is connected to the first clock signal terminal ca, an input terminal in, and a second node N2, and is used to transmit the signal from the input terminal in to the second node N2 in response to the signal from the first clock signal terminal ca. The first output circuit 413 is connected to the first node N1, a second power supply terminal VGH, and an output terminal out, and is used to transmit the signal from the second power supply terminal VGH to the output terminal out in response to the signal from the first node N1. The second output circuit 414 is connected to the output terminal out, the second clock signal terminal cb, and the third node N3, and is used to transmit the signal of the second clock signal terminal cb to the output terminal out in response to the signal of the third node N3. The isolation circuit 415 is connected to the second node N2, the first power supply terminal VGL, and the third node N3, and is used to connect the second node N2 and the third node N3 in response to the signal of the first power supply terminal VGL. The first control circuit 416 is connected to the first node N1, the first clock signal terminal ca, and the second node N2, and is used to transmit the signal of the first clock signal terminal ca to the first node N1 in response to the signal of the second node N2. The second control circuit 417 is connected to the first node N1, the second node N2, the second power supply terminal VGH, and the second clock signal terminal cb, and is used to simultaneously connect the second power supply terminal VGH and the second node N2 in response to the signals of the first node N1 and the second clock signal terminal cb.
[0078] In this exemplary embodiment, the first input circuit 411 may include a third transistor T3, with its first terminal connected to the first power supply terminal VGL, its second terminal connected to the first node N1, and its control terminal connected to the first clock signal terminal ca. The second input circuit 412 may include a fourth transistor T4, with its first terminal connected to the input terminal in, its second terminal connected to the second node N2, and its control terminal connected to the first clock signal terminal ca. The first output circuit 413 may include a fifth transistor T5 and a first capacitor C1, with its first terminal connected to the second power supply terminal VGH, its second terminal connected to the output terminal out, its control terminal connected to the first node N1, and its first capacitor C1 connected between the second power supply terminal VGH and the first node N1. The second output circuit 414 may include a sixth transistor T6 and a second capacitor C2, with its first terminal connected to the second clock signal terminal cb, its second terminal connected to the output terminal out, its control terminal connected to the third node N3, and its second capacitor C2 connected between the third node N3 and the output terminal out. The isolation circuit 415 may include a seventh transistor T7, with its first terminal connected to the second node N2, its second terminal connected to the third node N3, and its control terminal connected to the first power supply terminal VGL. The first control circuit may include an eighth transistor T8, with its first terminal connected to the first node N1, its second terminal connected to the first clock signal terminal ca, and its control terminal connected to the second node N2. The second control circuit 417 may include a ninth transistor T9 and a tenth transistor T10. The first terminal of the ninth transistor T9 is connected to the second power supply terminal VGH, and its control terminal is connected to the first node N1. The first terminal of the tenth transistor T10 is connected to the second terminal of the ninth transistor, its second terminal connected to the second node N2, and its control terminal connected to the second clock signal terminal cb. In this exemplary embodiment, the third to tenth transistors may be P-type transistors, the first power supply terminal VGL is a low-level power supply terminal, and the second power supply terminal VGH is a high-level power supply terminal.
[0079] In this exemplary embodiment, as Figure 6 , Figure 7 As shown, the first clock signal line group LC1 may include the first clock signal line CK1 and the third clock signal line CK3, within the range from the first-level shift register unit GOA(1) to the nth-level shift register unit GOA(n):
[0080] The first clock signal line CK1 can be connected to the first clock signal terminal ca in the odd-level shift register unit and the second clock signal terminal cb in the even-level shift register unit; the third clock signal line CK3 can be connected to the second clock signal terminal cb in the odd-level shift register unit and the first clock signal terminal ca in the even-level shift register unit.
[0081] The second clock signal line group LC2 may include the second clock signal line CK2 and the fourth clock signal line CK4, within the range from the (n+1)th stage shift register unit GOA(n+1) to the last stage shift register GOA(m):
[0082] The second clock signal line CK2 is connected to the first clock signal terminal ca of the m-th stage shift register unit, and also to the first clock signal terminal ca of the shift register unit with the same odd / even stage type as the m-th stage shift register unit. Furthermore, the second clock signal line CK2 is also connected to the second clock signal terminal cb of the (m-1)-th stage shift register unit, and also to the second clock signal terminal cb of the shift register unit with the same odd / even stage type as the (m-1)-th stage shift register unit. For example, when the m-th stage shift register unit is an even-stage shift register unit, the second clock signal line CK2 connects the first clock signal terminal ca of the m-th stage shift register unit and the first clock signal terminal ca of the even-stage shift register unit. The second clock signal line CK2 is also connected to the second clock signal terminal cb of the (m-1)-th stage shift register unit and the second clock signal terminal cb of the odd-stage shift register unit. The fourth clock signal line CK4 is connected to the second clock signal terminal cb of the m-th stage shift register unit, and also to the second clock signal terminal cb of the shift register unit with the same odd / even stage type as the m-th stage shift register unit. Furthermore, the fourth clock signal line CK4 is also connected to the first clock signal terminal ca of the (m-1)-th stage shift register unit, and also to the first clock signal terminal ca of the shift register unit with the same odd / even stage type as the (m-1)-th stage shift register unit. For example, when the m-th stage shift register unit is an even-stage shift register unit, the fourth clock signal line CK4 connects the second clock signal terminal cb of the m-th stage shift register unit and the second clock signal terminal cb of the even-stage shift register unit. Additionally, the fourth clock signal line CK4 also connects the first clock signal terminal ca of the (m-1)-th stage shift register unit and the first clock signal terminal ca of the odd-stage shift register unit.
[0083] It should be noted that in this exemplary embodiment and the following embodiments, m and n are described as even numbers.
[0084] In this exemplary embodiment, as Figure 8 As shown, Figure 7The diagram shows the timing diagrams of each node in a driving method for the gate driving circuit formed by the shift register unit shown. CK1 is the timing diagram for the signals on the first clock signal line, CK2 is the timing diagram for the signals on the second clock signal line, CK3 is the timing diagram for the signals on the third clock signal line, CK4 is the timing diagram for the signals on the fourth clock signal line, STV1 is the timing diagram for the signals on the first initialization signal terminal, STV2 is the timing diagram for the signals on the second initialization signal terminal, out1 represents the timing diagram for the signals on the output terminal of the first-stage shift register unit GOA(1), and out2 represents the timing diagram for the signals on the output terminal of the second-stage shift register unit GOA(1). A(2) Timing diagram of signals at the output terminal, out(n) represents the timing diagram of signals at the output terminal of the nth stage shift register unit GOA(n), out(n+1) represents the timing diagram of signals at the output terminal of the (n+1)th stage shift register unit GOA(n+1), out(m-1) represents the timing diagram of signals at the output terminal of the (m-1)th stage shift register unit GOA(m-1), and out(m) represents the timing diagram of signals at the output terminal of the mth stage shift register unit GOA(m). The first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4 sequentially output valid pulse signals. The valid pulse signal is a signal that can turn on the target circuit. In this exemplary embodiment, the valid pulse signal is a low-level signal.
[0085] The driving method for the display panel may include a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.
[0086] In the first stage t1: the first initialization signal terminal STV1 and the first clock signal line CK1 output low-level signals, the fourth transistor T4 in the first-stage shift register unit GOA(1) is turned on, and the first initialization signal terminal STV1 inputs a low-level signal to the third node N3 through the fourth transistor T4 in the first-stage shift register unit.
[0087] In the second stage t2: the second initialization signal terminal STV2 and the second clock signal line CK2 output low-level signals, the fourth transistor T4 in the m-th stage shift register unit GOA(m) is turned on, and the second initialization signal terminal STV2 inputs a low-level signal to the third node N3 through the fourth transistor T4 in the m-th stage shift register unit.
[0088] In the third stage t3: the third clock signal line CK3 outputs a low-level signal, and the third clock signal line CK3 inputs a low-level signal to the output terminal out through the sixth transistor T6 in the first stage shift register unit.
[0089] In the fourth stage t4: the fourth clock signal line CK4 outputs a low-level signal, and the fourth clock signal line CK4 inputs a low-level signal to the output terminal out through the sixth transistor T6 in the m-th stage shift register unit.
[0090] Similarly, this gate drive circuit can sequentially output gate drive signals from the top and bottom ends toward the middle position.
[0091] like Figure 9 The diagram shown is a schematic representation of the pixel circuit in an exemplary embodiment of the display panel of this disclosure. The pixel circuit may include: a tenth transistor T10, an eleventh transistor T11, a driving transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a capacitor C. In this configuration, the tenth transistor T10 has its first terminal connected to the first initial signal terminal Vinit1, its second terminal connected to node N, and its gate connected to the first reset signal terminal Re1; the eleventh transistor T11 has its first terminal connected to node N, its second terminal connected to the first terminal of the driving transistor T3, and its gate connected to the gate drive signal terminal Gate; the gate of the driving transistor T3 is connected to node N; the fourth transistor T4 has its first terminal connected to the data line Da, its second terminal connected to the second terminal of the driving transistor T3, and its gate connected to the gate drive signal terminal Gate; the fifth transistor T5 has its first terminal connected to the first power supply terminal VDD, its second terminal connected to the second terminal of the driving transistor T3, and its gate connected to the enable signal terminal EM; the sixth transistor T6 has its first terminal connected to the first terminal of the driving transistor T3, and its gate connected to the enable signal terminal EM; the seventh transistor T7 has its first terminal connected to the second initial signal terminal Vinit2, its second terminal connected to the second terminal of the sixth transistor T6, and its gate connected to the second reset signal terminal Re2. A capacitor C is connected between the gate of the driving transistor T3 and the first power supply terminal VDD. This pixel circuit can be connected to an OLED light-emitting unit to drive the OLED to emit light. The OLED can be connected between the second terminal and the second power supply terminal VSS of the sixth transistor T6. Among them, the tenth transistor T10, the eleventh transistor T11, the driving transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be P-type transistors.
[0092] like Figure 10 As shown, Figure 9The diagram shows the timing diagram of signals at each node in a driving method for the pixel circuit shown. Here, Gate represents the timing diagram of signals at the gate drive signal terminal Gate, Re1 represents the timing diagram of signals at the first reset signal terminal Re1, Re2 represents the timing diagram of signals at the second reset signal terminal Re2, EM represents the timing diagram of signals at the enable signal terminal EM, and Da represents the timing diagram of signals at the data line Da. The driving method for this pixel circuit may include a reset phase t1, a compensation phase t2, and an emission phase t3. In the reset phase t1: the first reset signal terminal Re1 outputs a low-level signal, the tenth transistor T10 is turned on, and the first initial signal terminal Vinit1 inputs a first initial signal to node N. During the compensation phase t2: the second reset signal terminal Re2 and the gate drive signal terminal Gate output low-level signals, the fourth transistor T4, the eleventh transistor T11, and the seventh transistor T7 are turned on, and at the same time, the data line Da outputs a data signal to write a voltage Vdata+Vth to node N, where Vdata is the voltage of the data signal and Vth is the threshold voltage of the driving transistor T3. The second initial signal terminal Vini2 inputs a second initial signal to the second terminal of the sixth transistor T6. During the light emission phase t3: the enable signal terminal EM outputs a low-level signal, the sixth transistor T6 and the fifth transistor T5 are turned on, and the driving transistor T3 drives the light-emitting unit to emit light under the action of the voltage Vdata+Vth at node N.
[0093] Figure 7 The gate drive circuit formed by the shift register unit shown can drive the shift register unit to the gate drive circuit. Figure 9 The gate drive signal is provided by any one of the gate drive signal terminal Gate, the first reset signal terminal Re1, and the second reset signal terminal Re2.
[0094] It should be understood that the pixel driving circuit in the display panel provided in this exemplary embodiment is not limited to... Figure 9 The structure shown is illustrated. In other exemplary embodiments, the pixel driving circuit may also have other structures.
[0095] Furthermore, in other exemplary embodiments, Figure 6 The shift register unit in the display panel shown can also be of other structures. For example... Figure 11 As shown, Figure 6 The diagram shows a schematic of the shift register unit in another exemplary embodiment of the display panel. The gate drive circuit formed by this shift register unit can drive... Figure 9 The enable signal terminal in the circuit provides the gate drive signal.
[0096] In this exemplary embodiment, as Figure 11As shown, the shift register unit may include: an eleventh transistor T11, a twelfth transistor T12, a third transistor T3, a fourth transistor T4, a first capacitor C1, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a second capacitor C2, a tenth transistor T10, and a third capacitor C3. The first electrode of the eleventh transistor T11 is connected to the input terminal in, the second electrode is connected to the first node N1, and the gate is connected to the first clock signal terminal ca. The first electrode of the twelfth transistor T12 is connected to the first power supply terminal VGL, the second electrode is connected to the second node N2, and the gate is connected to the first clock signal terminal ca. The first electrode of the third transistor T3 is connected to the second clock signal terminal cb, and the gate is connected to the second node N2. The first electrode of the fourth transistor T4 is connected to the second electrode of the third transistor T3, the second electrode is connected to the third node N3, and the gate is connected to the second clock signal terminal cb. The first electrode of the first capacitor C1 can be connected to the second node N2, and the second electrode can be connected to the first power supply terminal VGL. The fifth transistor T5 has its first electrode connected to the second power supply terminal VGH, its second electrode connected to the third node N3, and its gate connected to the first node N1. The sixth transistor T6 has its first electrode connected to the first clock signal terminal ca, its second electrode connected to the second node N2, and its gate connected to the first node N1. The seventh transistor T7 has its first electrode connected to the second power supply terminal VGH, and its gate connected to the second node N2. The eighth transistor T8 has its first electrode connected to the second electrode of the seventh transistor T7, its second electrode connected to the first node N1, and its gate connected to the second clock signal terminal cb. The ninth transistor T9 has its first electrode connected to the first power supply terminal VGL, its second electrode connected to the output terminal Output, and its gate connected to the first node N1. The first electrode of the second capacitor C2 can be connected to the first node N1, and its second electrode can be connected to the second power supply terminal VGH. The tenth transistor T10 has its first electrode connected to the second power supply terminal VGH, its second electrode connected to the output terminal Output, and its gate connected to the third node N3. The first electrode of the third capacitor C3 is connected to the third node N3, and its second electrode can be connected to the second power supply terminal VGH. Figure 11 All transistors in the shift register unit shown can be P-type transistors, the first power supply terminal VGL is a low-level power supply terminal, and the second power supply terminal VGH is a high-level power supply terminal.
[0097] In this exemplary embodiment, as Figure 12 As shown, Figure 11The diagram shows the timing diagrams of each node in a driving method for the gate driving circuit formed by the shift register unit shown. CK1 is the timing diagram for the signals on the first clock signal line, CK2 is the timing diagram for the signals on the second clock signal line, CK3 is the timing diagram for the signals on the third clock signal line, CK4 is the timing diagram for the signals on the fourth clock signal line, STV1 is the timing diagram for the signals on the first initialization signal terminal, STV2 is the timing diagram for the signals on the second initialization signal terminal, out1 represents the timing diagram for the signals on the output terminal of the first-stage shift register unit GOA(1), out2 represents the timing diagram for the signals on the output terminal of the second-stage shift register unit GOA(2), out(n) represents the timing diagram for the signals on the output terminal of the nth-stage shift register unit GOA(n), out(m-1) represents the timing diagram for the signals on the output terminal of the (m-1)th-stage shift register unit GOA(m-1), and out(m) represents the timing diagram for the signals on the output terminal of the mth-stage shift register unit GOA(m). The first clock signal line CK1, the second clock signal line CK2, the third clock signal line CK3, and the fourth clock signal line CK4 sequentially output valid pulse signals (low-level pulse signals).
[0098] The driving method for the display panel may include a first stage t1, a second stage t2, a third stage t3, and a fourth stage t4.
[0099] In the first stage t1: the first initialization signal terminal STV1 outputs a high level, the first clock signal line CK1 outputs a low level signal, the eleventh transistor T11 and the twelfth transistor T12 in the first-stage shift register unit GOA(1) are turned on, the first initialization signal terminal STV1 inputs a high level signal to the first node N1 through the eleventh transistor T11 in the first-stage shift register unit, and the first power supply terminal VGL inputs a low level to the second node through the twelfth transistor T12 in the first-stage shift register unit.
[0100] In the second stage t2: the second initialization signal terminal STV2 outputs a high-level signal, the second clock signal line CK2 outputs a low-level signal, and the eleventh transistor T11 and the twelfth transistor T12 in the m-th stage shift register unit GOA(m) are turned on. The second initialization signal terminal STV2 inputs a low-level signal to the first node N1 through the eleventh transistor T11 in the m-th stage shift register unit. The first power supply terminal VGL inputs a low level to the second node through the twelfth transistor T12 in the m-th stage shift register unit.
[0101] In the third stage t3: the third clock signal line CK3 outputs a low-level signal, the third transistor T3 and the fourth transistor T4 in the first-stage shift register unit are turned on, the third clock signal line CK3 inputs a low level to the third node N3 in the first-stage shift register unit, the tenth transistor T10 in the first-stage shift register unit is turned on, and the second power supply terminal VGH inputs a high-level signal to the output terminal out in the first-stage shift register unit.
[0102] In the fourth stage t4: the fourth clock signal line CK4 outputs a low-level signal, the third transistor T3 and the fourth transistor T4 in the m-th stage shift register unit are turned on, the third clock signal line CK3 inputs a low level to the third node N3 in the m-th stage shift register unit, the tenth transistor T10 in the m-th stage shift register unit is turned on, and the second power supply terminal VGH inputs a high-level signal to the output terminal out in the m-th stage shift register unit.
[0103] Similarly, this gate drive circuit can sequentially output gate drive signals from the top and bottom ends toward the middle position.
[0104] like Figure 13 The diagram shown is a structural schematic of the display panel in another exemplary embodiment of the splicing screen disclosed herein. Compared to Figure 6 The display panel shown is shown. Figure 13 The input terminal in of the first-stage shift register unit GOA(1) and the input terminal in of the last-stage shift register unit GOA(m) of the display panel shown are connected to the same initialization signal terminal STV. The (1+x)th stage shift register unit and the (mx)th stage shift register unit can simultaneously output gate drive signals, where x is an integer greater than or equal to 0. For example, the first-stage shift register unit and the (m)th stage shift register unit can simultaneously output gate drive signals, and the second-stage shift register unit and the (m-1)th stage shift register unit can simultaneously output gate drive signals.
[0105] In this exemplary embodiment, Figure 13 The shift register unit in the middle can be as follows Figure 7 or Figure 11 As shown.
[0106] like Figure 13As shown, the display panel includes a clock signal line group LC, which includes at least one clock signal line used to provide a clock signal to the gate drive circuit; wherein, the first-stage shift register unit GOA(1) is the first-stage shift register unit, the last-stage shift register unit GOA(m) is the m-th stage shift register unit, and the same clock signal terminals of the (1+x)-th stage shift register unit and the (mx)-th stage shift register unit are connected to the same clock signal line, where m is a positive integer greater than n and x is an integer greater than or equal to 0. For example, as Figure 13 As shown, the clock signal line group LC includes a first clock signal line CK1 and a second clock signal line CK2. The first clock signal line CK1 can be connected to the first clock signal terminals of the first-stage shift register unit and the (m)th-stage shift register unit. The second clock signal line CK2 can be connected to the second clock signal terminals of the first-stage shift register unit and the (m)th-stage shift register unit. Similarly, the first clock signal line CK1 can be connected to the second clock signal terminals of the second-stage shift register unit and the (m-1)th-stage shift register unit. The second clock signal line CK2 can be connected to the first clock signal terminals of the second-stage shift register unit and the (m-1)th-stage shift register unit.
[0107] In addition, such as Figure 13 As shown, in the range from the first-level shift register unit GOA(1) to the nth-level shift register unit GOA(n):
[0108] The first clock signal line CK1 can be connected to the first clock signal terminal ca in the odd-level shift register unit and the second clock signal terminal cb in the even-level shift register unit; the third clock signal line CK3 can be connected to the second clock signal terminal cb in the odd-level shift register unit and the first clock signal terminal ca in the even-level shift register unit.
[0109] like Figure 14 As shown, Figure 13 The diagram shows the timing of each node in a driving method for the display panel. Among them, Figure 14 This shows that when the shift register unit is Figure 7The structure shown is a timing diagram of each node on the display panel. CK1 is the timing diagram of the signals on the first clock signal line, CK2 is the timing diagram of the signals on the second clock signal line, STV is the timing diagram of the signals on the initialization signal terminal, out1 represents the timing diagram of the signals on the output terminal of the first-stage shift register unit GOA(1), out2 represents the timing diagram of the signals on the output terminal of the second-stage shift register unit GOA(2), out(n-1) represents the timing diagram of the signals on the output terminal of the (n-1)th-stage shift register unit GOA(n+3), and out(n) represents the timing diagram of the nth-stage shift register. The timing diagrams for the signals at the output terminals of the unit GOA(n) are shown below. out(n+1) represents the timing diagram for the signals at the output terminals of the (n+1)th stage shift register unit GOA(n+1), out(n+2) represents the timing diagram for the signals at the output terminals of the (n+2)th stage shift register unit GOA(n+2), out(m-1) represents the timing diagram for the signals at the output terminals of the (m-1)th stage shift register unit GOA(m-1), and out(m) represents the timing diagram for the signals at the output terminals of the m-th stage shift register unit GOA(m).
[0110] In this exemplary embodiment, as Figure 14 As shown, in the first stage t1: the initial signal terminal STV and the first clock signal line CK1 output low-level signals, and the initial signal terminal STV inputs a low level to the third node N3 in the first-stage shift register unit GOA(1) and the last-stage shift register unit GOA(m). In the second stage t2: the second clock signal line CK2 outputs a low-level signal, and the second clock signal line CK2 inputs a low-level signal to the output terminal out in the first-stage shift register unit GOA(1) and the last-stage shift register unit GOA(m). Similarly, this gate drive circuit can sequentially output gate drive signals from the top and bottom ends towards the middle position.
[0111] In this exemplary embodiment, as Figure 13 As shown, since there are two rows of pixel driving circuits scanning simultaneously in the display panel, the multiple data lines Da include multiple first data lines Da1 and multiple second data lines Da2. The first data line Da1 is used to provide data signals to the pixel driving circuit in the first display area AA1, and the second data line Da2 is used to provide data signals to the pixel driving circuit in the second display area AA2.
[0112] In this exemplary embodiment, as Figure 15The diagram shown is a structural schematic of a display panel in another exemplary embodiment of the splicing screen disclosed herein. Each column of pixel driving circuits can be correspondingly provided with a first data line Da1 and a second data line Da2. The first data line Da1 provides data signals to the pixel driving circuit corresponding to it and located in the first display area AA1, and the second data line Da2 provides data signals to the pixel driving circuit corresponding to it and located in the second display area AA2. The display panel also includes a source driver chip DIC, and the first data line Da1 and the second data line Da2 are respectively connected to different output terminals of the source driver chip DIC.
[0113] like Figure 16 As shown, Figure 15 The diagram shows the timing diagrams of each node in a driving method for the display panel. Da1 is the timing diagram of the signals on the first data signal line, Da2 is the timing diagram of the signals on the second data signal line, out1 represents the timing diagram of the signals at the output of the first-stage shift register unit GOA(1), out2 represents the timing diagram of the signals at the output of the second-stage shift register unit GOA(2), out(n-1) represents the timing diagram of the signals at the output of the (n-1)th-stage shift register unit GOA(n+3), and out(n) represents the timing diagram of the nth-stage shift register unit GOA(n+3). The timing diagrams for the signals at the output terminals of the register unit GOA(n) are as follows: out(n+1) represents the timing diagram for the signals at the output terminals of the (n+1)th stage shift register unit GOA(n+1), out(n+2) represents the timing diagram for the signals at the output terminals of the (n+2)th stage shift register unit GOA(n+2), out(m-1) represents the timing diagram for the signals at the output terminals of the (m-1)th stage shift register unit GOA(m-1), and out(m) represents the timing diagram for the signals at the output terminals of the mth stage shift register unit GOA(m).
[0114] Figure 15 The gate drive circuit in the display panel shown is used to provide gate drive signals to the transistors connected to the data lines. For example... Figure 16 As shown, in the first stage t1, the first-level shift register unit GOA(1) and the last-level shift register unit GOA(m) output valid levels. Correspondingly, the first data line Da1 and the second data line Da2 output data signals to realize the data writing of the first row pixel driving circuit and the last row pixel driving circuit. In the second stage t2, the second-level shift register unit GOA(2) and the (m-1)th-level shift register unit GOA(m-1) output valid levels. Correspondingly, the first data line Da1 and the second data line Da2 output data signals to realize the data writing of the second row pixel driving circuit and the (m-1)th row pixel driving circuit. And so on, the display panel can realize line-by-line scanning from the top and bottom sides of the display panel towards the middle position.
[0115] In this exemplary embodiment, as Figure 17 The diagram shown is a structural schematic of a display panel in another exemplary embodiment of the splicing screen disclosed herein. The display panel further includes: multiple gating circuits MUX, each MUX connected between the same output terminal of the source driver chip DIC and the first data line Da1 and the second data line Da2. The gating circuits MUX are used to respond to a gating signal to time-division multiplex the output terminal of the source driver chip DIC with the first data line Da1 and the second data line Da2.
[0116] In this exemplary embodiment, as Figure 17 As shown, each column of pixel driving circuits is provided with a first data line Da1 and a second data line Da2. The first data line Da1 provides a data signal to the pixel driving circuit corresponding to it and located in the first display area AA1, and the second data line Da2 provides a data signal to the pixel driving circuit corresponding to it and located in the second display area AA2. The gating circuit MUX connects the first data line Da1 and the second data line Da2 corresponding to the same column of pixel driving circuits. It should be understood that in other exemplary embodiments, the gating circuit MUX may also connect the first data line Da1 and the second data line Da2 corresponding to different columns of pixel driving circuits.
[0117] In this exemplary embodiment, as Figure 17 As shown, the gating circuit MUX may include a first transistor T1 and a second transistor T2. The first transistor T1 has its first terminal connected to the output terminal of the source driver chip DIC, its second terminal connected to the first data line Da1, and its gate connected to the first gating signal line Mx1. The second transistor T2 has its first terminal connected to the same output terminal of the source driver chip DIC, its second terminal connected to the second data line Da2, and its gate connected to the second gating signal line Mx2. The first transistor T1 and the second transistor T2 may be P-type transistors.
[0118] like Figure 18 As shown, Figure 17The diagram shows the timing diagrams of each node in a driving method for the display panel. Da1 is the timing diagram of the signals on the first data signal line, Da2 is the timing diagram of the signals on the second data signal line, Mx1 is the timing diagram of the signals on the first strobe signal line, Mx2 is the timing diagram of the signals on the second strobe signal line, out1 represents the timing diagram of the signals at the output terminal of the first-stage shift register unit GOA(1), out2 represents the timing diagram of the signals at the output terminal of the second-stage shift register unit GOA(2), and out(n-1) represents the signals at the output terminal of the (n-1)th-stage shift register unit GOA(n+3). The timing diagrams are as follows: out(n) represents the timing diagram of the signal at the output terminal of the nth stage shift register unit GOA(n), out(n+1) represents the timing diagram of the signal at the output terminal of the (n+1)th stage shift register unit GOA(n+1), out(n+2) represents the timing diagram of the signal at the output terminal of the (n+2)th stage shift register unit GOA(n+2), out(m-1) represents the timing diagram of the signal at the output terminal of the (m-1)th stage shift register unit GOA(m-1), and out(m) represents the timing diagram of the signal at the output terminal of the mth stage shift register unit GOA(m).
[0119] In the first stage t1, the first gating signal line Mx1 outputs a low-level signal, the first transistor T1 is turned on, and the source driver chip DIC inputs a data signal to the first data line Da1. In the second stage t2, the second gating signal line Mx2 outputs a low-level signal, the second transistor T2 is turned on, and the source driver chip DIC inputs a data signal to the second data line Da2. In the third stage t3, the first-stage shift register unit GOA(1) and the last-stage shift register unit GOA(m) output low-level signals, the data line signals stored on the first data line Da1 are transmitted to the pixel driver circuit in the first display area AA1, and the data line signals stored on the second data line Da2 are transmitted to the pixel driver circuit in the second display area AA2. This process continues, allowing the display panel to scan line by line from the top and bottom to the center. The gating circuit in this display panel reduces the number of source driver chips.
[0120] like Figure 19The diagram shown is a structural schematic of a display panel in another exemplary embodiment of the splicing screen disclosed herein. The display panel includes multiple source driver chips, among which a first source driver chip DIC1 and a second source driver chip DIC2 are located on opposite sides of the display area AA in the second direction Y. A portion of the data lines Da are connected to the first source driver chip DIC1 via their ends near the first source driver chip DIC1, and a portion of the data lines Da are connected to the second source driver chip DIC2 via their ends near the second source driver chip DIC2. This configuration reduces the number of data line pins on one side of the display panel, thereby facilitating the bonding and connection of data lines and source driver chips.
[0121] In this exemplary embodiment, as Figure 19 As shown, the display panel includes multiple pixel units Pz, which are arranged in an array along the first direction X and the second direction Y. Each pixel unit Pz includes multiple adjacent pixel driving circuits Pix arranged along the first direction X. The pixel units Pz in adjacent columns are respectively connected to the first source driver chip DIC1 and the second source driver chip DIC2 via data lines.
[0122] like Figure 20 The diagram shown is a schematic representation of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein. In a display panel architecture without a gating circuit, the number of data line pins on one side of the display panel can also be reduced by placing the source driver chips on both sides of the display area AA in the second direction Y.
[0123] like Figure 21 The diagram shown is a schematic representation of the display panel structure in another exemplary embodiment of the splicing screen disclosed herein. In the display panel architecture without a gating circuit, the data lines connecting the first source driver chip DIC1 and the data lines connecting the second source driver chip DIC2 can be alternately distributed along the first direction X.
[0124] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the disclosure herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the claims.
[0125] It should be understood that this disclosure is not limited to the precise structures described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this disclosure is defined only by the appended claims.
Claims
1. A type of video wall, wherein, The video wall includes at least a plurality of display panels distributed along a second direction, and the display areas of the display panels include a first display area and a second display area distributed along the second direction. The display panels also include: Multiple pixel driving circuits are located in the display area, and the multiple pixel driving circuits are arranged in an array along a first direction and a second direction, the first direction and the second direction intersecting; A gate driving circuit, the gate driving circuit including a multi-stage shift register unit; The first-level shift register unit to the nth-level shift register unit are used to provide gate drive signals to the pixel driving circuit in the first display area, and in the first-level shift register unit to the nth-level shift register unit, the output terminal of the upper-level shift register unit is connected to the input terminal of the lower-level shift register unit. The (n+1)th stage shift register unit to the last stage shift register unit are used to provide gate drive signals to the pixel driving circuit in the second display area, and in the (n+1)th stage shift register unit to the last stage shift register unit, the output terminal of the lower stage shift register unit is connected to the input terminal of the upper stage shift register unit; n is a positive integer greater than 1.
2. The splicing screen according to claim 1, wherein, The input terminals of the first-stage shift register unit and the last-stage shift register unit are connected to different initialization signal terminals.
3. The splicing screen according to claim 1, wherein, The input terminals of the first-stage shift register unit and the last-stage shift register unit are connected to the same initialization signal terminal.
4. The splicing screen according to claim 3, wherein, The display panel also includes: Multiple data lines extend along a second direction, including multiple first data lines and multiple second data lines. The first data lines are used to provide data signals to the pixel driving circuit in the first display area, and the second data lines are used to provide data signals to the pixel driving circuit in the second display area.
5. The splicing screen according to claim 4, wherein, The second direction is the column direction. Each column of the pixel driving circuit is provided with a first data line and a second data line. The display panel also includes a source driver chip. The first data line is used to provide data signals to the pixel driving circuit corresponding to it and located in the first display area. The second data line is used to provide data signals to the pixel driving circuit corresponding to it and located in the second display area. The first data line and the second data line are respectively connected to different output terminals of the source driver chip.
6. The splicing screen according to claim 4, wherein, The display panel also includes: A source driver chip, which provides data signals to the data line through its output terminal; A gating circuit is connected between the same output terminal of the source driver chip and the first data line and the second data line. The gating circuit is used to respond to a gating signal to connect the output terminal of the source driver chip and the first data line and the second data line in a time-division manner.
7. The splicing screen according to claim 6, wherein, The second direction is the column direction. Each column of the pixel driving circuit is provided with a first data line and a second data line. The first data line is used to provide data signals to the pixel driving circuit corresponding to it and located in the first display area. The second data line is used to provide data signals to the pixel driving circuit corresponding to it and located in the second display area. The gating circuit connects the first data line and the second data line corresponding to the same column of pixel driving circuits.
8. The video wall according to any one of claims 1-7, wherein, The display panel also includes: Multiple data lines extending along a second direction are provided to provide data signals to the pixel driving circuit. Multiple source driver chips, including a first source driver chip and a second source driver chip, are located on opposite sides of the display area in the second direction. Some of the data lines are connected to the first source driver chip through one end close to the first source driver chip, and some of the data lines are connected to the second source driver chip through one end close to the second source driver chip.
9. The splicing screen according to claim 8, wherein, The data lines connecting the first source driver chip and the data lines connecting the second source driver chip are alternately distributed along the first direction.
10. The splicing screen according to claim 8, wherein, The display panel includes a plurality of pixel units, which are arranged in an array along the first direction and the second direction. Each pixel unit includes a plurality of adjacent pixel driving circuits arranged along the first direction. The second direction is the column direction, and the pixel units located in adjacent columns are respectively connected to the first source driver chip and the second source driver chip via data lines.
11. The splicing screen according to claim 2, wherein, The display panel also includes: A first clock signal line group, comprising at least one clock signal line, wherein the clock signal line in the first clock signal line group is used to provide clock signals to the first-level shift register unit to the nth-level shift register unit; The second clock signal line group includes at least one clock signal line, which is used to provide clock signals to the (n+1)th stage shift register unit to the last stage shift register unit.
12. The splicing screen according to claim 3, wherein, The display panel also includes: A clock signal line group includes at least one clock signal line, which is used to provide a clock signal to the gate drive circuit. The first-level shift register unit is the first-level shift register unit, the last-level shift register unit is the m-th level shift register unit, and the same clock signal terminals of the (1+x)-th level shift register unit and the (mx)-th level shift register unit are connected to the same clock signal line, where m is a positive integer greater than n and x is an integer greater than or equal to 0.
13. The video wall according to any one of claims 1-10, wherein, The gate drive circuit includes m shift register units; When m is even, n equals m / 2; When m is odd, n equals (m+1) / 2 or n equals (m-1) / 2.