An LCD display

Abstract

The utility model discloses a LCD display screen is applied to display technical field, include: glass substrate and FPC, glass substrate surface is provided with at least two display drive chips and at least two first wire, FPC surface is provided with at least one second wire, the resistance value of second wire is less than the resistance value of first wire, between adjacent two display drive chips is connected with synchronous signal transmission channel, at least part synchronous signal transmission channel is first transmission channel, first transmission channel includes the first wire of connection in proper order, a second wire and another first wire, two first wire in first transmission channel is connected with adjacent two display drive chips respectively. The utility model will be between adjacent display drive chip synchronous signal by the wire transmission of high resistance value of glass substrate surface all -way originally, change into part path through the wire transmission of low resistance value of FPC surface, can effectively reduce synchronous signal transmission delay time.

Description

Technical Field

[0001] This utility model relates to the field of display technology, and in particular to an LCD display screen. Background Technology

[0002] Traditional LCD (Liquid Crystal Display) screens typically have multiple integrated circuits (ICs) connected in series on a glass substrate to drive higher screen resolutions. When using multiple ICs, a synchronization signal is needed to ensure they operate synchronously. The signal transmission wires on the glass substrate are usually made of ITO (Indium Tin Oxide), so the ICs on the substrate are interconnected using ITO wires to transmit synchronization signals. However, ITO wires have a relatively high resistance, which introduces significant delays in the transmission of synchronization signals. This delay limits the number of ICs that can be connected in series on an LCD screen, thus limiting its application in high-resolution displays. Utility Model Content

[0003] In view of this, the purpose of this utility model is to provide an LCD display screen that transmits synchronization signals through low-resistance wires on the surface of an FPC, thereby achieving a significant reduction in latency.

[0004] To solve the above-mentioned technical problems, this utility model provides an LCD display screen, including: a glass substrate and an FPC; at least two display driver chips and at least two first wires are disposed on the surface of the glass substrate; at least one second wire is disposed on the surface of the FPC; the resistance value of the second wire is less than the resistance value of the first wire;

[0005] A synchronization signal transmission channel is connected between two adjacent display driver chips; at least part of the synchronization signal transmission channel is a first transmission channel; the first transmission channel includes a first wire, a second wire, and another first wire connected in sequence; the two first wires in the first transmission channel are respectively connected to the two adjacent display driver chips.

[0006] Optionally, the FPC is located on the side of the display driver chip near the edge of the glass substrate.

[0007] Optionally, the display driver chips are arranged sequentially along a first direction; a second direction is perpendicular to the first direction; in the second direction, all the first transmission channels are located on the same side of the display driver chips.

[0008] Optionally, the first conductor is an ITO conductor.

[0009] Optionally, the second wire is a metal wire.

[0010] Optionally, the display driver chip is connected to the first wire via conductive adhesive.

[0011] Optionally, the second wire is connected to the first wire via conductive adhesive.

[0012] Optionally, the LCD display screen further includes: a microcontroller; a display data transmission channel is connected between each display driver chip and the microcontroller; the display data transmission channel includes a first wire and a second wire connected in sequence; the end of the first wire in the display data transmission channel away from the second wire is connected to the display driver chip, and the end of the second wire away from the first wire is connected to the microcontroller.

[0013] Optionally, all of the aforementioned synchronization signal transmission channels are the first transmission channel.

[0014] Optionally, part of the synchronization signal transmission channel is the first transmission channel, and the remaining part of the synchronization signal transmission channel is the second transmission channel; the second transmission channel includes one of the first wires; the two ends of the first wire in the second transmission channel are respectively connected to two adjacent display driver chips.

[0015] As can be seen, the LCD display provided by this utility model changes the transmission of synchronization signals between adjacent display driver chips from the original method of transmitting the entire signal through high-resistance wires on the glass substrate surface to a method where a portion of the signal is transmitted through low-resistance wires on the FPC surface. By providing low-resistance wires on the FPC surface to connect adjacent display driver chips and enable them to communicate with each other, the total resistance of the synchronization signal transmission channel is significantly reduced compared to communicating solely through high-resistance wires on the glass substrate. This new method more effectively reduces signal transmission delay time, significantly reducing the synchronization signal delay between multiple display driver chips, thus enabling the cascading of more display driver chips and improving the feasibility of applications in high-resolution displays. Attached Figure Description

[0016] To more clearly illustrate the technical solutions in the embodiments of this utility model or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of this utility model. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0017] Figure 1 This is a schematic diagram of the structure of a traditional LCD display screen;

[0018] Figure 2 This is a schematic diagram of synchronous signal transmission in a traditional LCD display screen.

[0019] Figure 3 This is a schematic diagram of the structure of an LCD display screen provided in an embodiment of the present utility model.

[0020] The annotations in the attached figures are explained as follows:

[0021] 1-Glass substrate; 2-Display driver chip; 3-FPC; 4-Conductive adhesive; 5-ITO wire; 6-First wire; 7-Second wire. Detailed Implementation

[0022] To make the objectives, technical solutions, and advantages of the embodiments of this utility model clearer, the technical solutions of the embodiments of this utility model will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this utility model, and not all embodiments. Based on the embodiments of this utility model, all other embodiments obtained by those skilled in the art without creative effort are within the protection scope of this utility model.

[0023] Driven by the demand for mobile electronic products and the rapid development of low-cost, high-density, and mass-production electronic manufacturing technologies, these products often incorporate LCD displays. LCD displays require display driver chips to provide control and drive signals, traditionally connected to a PCB (Printed Circuit Board). However, the development of COG (Chip-on-Glass) technology has enabled the display driver chip to be directly mounted on the display screen. Due to its low cost and ability to reduce screen thickness, COG has rapidly grown and become a major packaging form for LCD display driver chips, thus becoming an important component of these display modules.

[0024] like Figure 1 As shown, COG directly attaches the display driver chip 2 to the glass substrate 1 of the LCD display screen using conductive adhesive 4, thereby interconnecting and encapsulating the conductive bumps of the display driver chip 2 with the ITO transparent conductive pads on the glass substrate 1.

[0025] Pixels on an LCD screen are typically driven by a single source driver. Therefore, a single display driver chip often contains hundreds or even thousands of source drivers. As screen resolution increases, a single display driver chip cannot provide enough source drivers. As a result, multiple display driver chips are used to drive the same display module. COG technology allows several display driver chips to be cascaded directly on the glass substrate, providing the required number of source drivers and thus enabling the driving of higher screen resolutions.

[0026] When using multiple display driver chips to drive an LCD screen, synchronization signals are required to ensure that the chips work in sync. Otherwise, significant timing differences in the drive signals output by different chips can degrade display quality, and in severe cases, cause abnormal images. Because the display driver chips are placed on a glass substrate, the signal transmission lines on the glass substrate are made of ITO (Indium Tin Oxide), an N-type oxide semiconductor. ITO thin films are transparent conductive films made of indium tin oxide semiconductors, and their transparency makes them suitable for use as conductors on glass substrates. Therefore, as... Figure 2 As shown, multiple display driver chips 2 on the glass substrate 1 are interconnected and transmit synchronization signals using ITO wires 5.

[0027] However, the resistance of ITO wires is still relatively high compared to ordinary metal wires, which will cause a significant delay in the transmission of synchronization signals. This delay limits the number of display driver chips that can be connected in series, thus limiting its application in high-resolution displays. Therefore, this application provides an LCD display that effectively reduces the synchronization signal transmission delay by changing the transmission of the synchronization signal between adjacent display driver chips from the original high-resistance wires on the glass substrate surface to a partial path transmission through low-resistance wires on the FPC (Flexible Printed Circuit) surface.

[0028] Please refer to Figure 3 , Figure 3 This is a schematic diagram of the structure of an LCD display screen provided in an embodiment of the present utility model. The LCD display screen may include: a glass substrate 1 and an FPC 3; at least two display driver chips 2 and at least two first wires 6 are disposed on the surface of the glass substrate 1; at least one second wire 7 is disposed on the surface of the FPC 3; the resistance value of the second wire 7 is less than the resistance value of the first wire 6.

[0029] A synchronization signal transmission channel is connected between two adjacent display driver chips 2; at least part of the synchronization signal transmission channel is a first transmission channel; the first transmission channel includes a first wire 6, a second wire 7 and another first wire 6 connected in sequence; the two first wires 6 in the first transmission channel are respectively connected to the two adjacent display driver chips 2.

[0030] In this embodiment, all synchronization signal transmission channels can be first transmission channels; alternatively, some synchronization signal transmission channels can be first transmission channels, and the remaining synchronization signal transmission channels can be second transmission channels. The second transmission channel includes a first wire 6; the two ends of the first wire 6 in the second transmission channel are respectively connected to two adjacent display driver chips 2. It should be noted that the former changes all synchronization signal transmission channels to transmit synchronization signals via the second wire 7 of the FPC3, which can significantly reduce the total resistance value of the synchronization signal transmission channels, thereby more effectively reducing the synchronization signal transmission delay time; while in the latter, although some synchronization signal transmission channels still use conventional paths, the total resistance value of the synchronization signal transmission channels is still lower than the resistance value of simply using high-resistance wires, which can also reduce the synchronization signal transmission delay time.

[0031] This embodiment does not limit the specific type of the first conductive wire 6. The first conductive wire 6 can be, but is not limited to, an ITO conductive wire. It should be noted that ITO is a common material in the prior art. This embodiment does not limit the internal composition of the first conductive wire 6, but directly uses an ITO conductive wire made of existing materials. Moreover, ITO conductive wires are suitable for being disposed on the surface of the glass substrate 1 due to their transparent properties.

[0032] This embodiment does not limit the specific type of the second wire 7, as long as the resistance value of the second wire 7 is less than that of the first wire 6. The second wire 7 can be, but is not limited to, a metal wire. It should be noted that metal is a common material in the prior art. This embodiment does not limit the internal composition of the second wire 7, but directly uses a metal wire made of existing materials. The resistance value of a metal wire is much lower than that of an ITO wire.

[0033] It should be noted that using COG offers advantages such as low cost, reduced display thickness, and increased display resolution. However, the resistance of the ITO conductors causes significant delays in the transmission of synchronization signals, and the more display driver chips 2 are connected in series, the more severe the delay problem becomes. Traditional methods do not offer the advantages of COG. Compared to the previous architecture, this embodiment still maintains the use of COG technology. All contacts of the display driver chips 2 are still connected via the first conductor 6 on the glass substrate 1, and each display driver chip 2 transmits display data through the FPC3; only the path for transmitting synchronization signals is via the second conductor 7 on the FPC3.

[0034] This embodiment does not limit the specific connection method between the display driver chip 2 and the glass substrate 1, as long as it ensures that the display driver chip 2 can be fixed on the surface of the glass substrate 1. For example, the display driver chip 2 can be connected to the first wire 6 through conductive adhesive 4, that is, the display driver chip 2 is fixed on the surface of the glass substrate 1 through conductive adhesive 4. This embodiment does not limit the specific type of conductive adhesive 4, as long as it has conductivity and adhesion. The conductive adhesive 4 can be, but is not limited to, anisotropic conductive film (ACF). It should be noted that anisotropic conductive film is a common material in the prior art. This embodiment does not limit the internal composition of the conductive adhesive 4, but directly uses anisotropic conductive film made of existing materials.

[0035] This embodiment does not limit the specific connection method between FPC3 and glass substrate 1, as long as it ensures that FPC3 can be fixed to the surface of glass substrate 1. For example, the second wire 7 is connected to the first wire 6 through conductive adhesive 4, that is, FPC3 is fixed to the surface of glass substrate 1 through conductive adhesive 4. This embodiment does not limit the specific type of conductive adhesive 4, as long as it has conductivity and adhesion. Conductive adhesive 4 can be, but is not limited to, anisotropic conductive adhesive. It should be noted that anisotropic conductive adhesive is a common material in the prior art. This embodiment does not limit the internal composition of conductive adhesive 4, but directly uses anisotropic conductive adhesive made of existing materials.

[0036] This embodiment does not limit the specific location of FPC3, as long as it ensures that the second conductor 7 can be connected to the first conductor 6. For example, FPC3 can be located on the side of the display driver chip 2 near the edge of the glass substrate 1. It should be noted that in this embodiment, the closer the junction of FPC3 and the glass substrate 1 is to the display driver chip 2, the better. This can shorten the distance of the synchronization signal from the display driver chip 2 to FPC3 via the first conductor 6, so that most of the synchronization signal path between the display driver chips 2 is on FPC3, making its total path resistance much smaller than the ITO resistance value, thereby significantly reducing the delay of the synchronization signal.

[0037] In this embodiment, each display driver chip 2 is equipped with at least two source drivers, and each source driver drives one pixel. This embodiment does not limit the specific number of display driver chips 2; it can be determined based on the specific number of pixels disposed on the surface of the glass substrate 1. It should be noted that the more display driver chips 2 are connected in series, the more significant the delay reduction effect is compared to the method of communication solely through high-resistance wires on the glass substrate 1.

[0038] This embodiment does not limit the specific arrangement of the display driver chips 2. It can be determined according to the specific arrangement of the pixels on the surface of the glass substrate 1. For example, the display driver chips 2 can be arranged sequentially along the first direction; the second direction is perpendicular to the first direction; in the second direction, all the first transmission channels are located on the same side of the display driver chips 2. It should be noted that the first direction in this embodiment can be the length direction of the glass substrate 1 or the width direction of the glass substrate 1. In this embodiment, the synchronization signal transmission channel connected to the input end of the head display driver chip 2 and the synchronization signal transmission channel connected to the output end of the tail display driver chip 2 in the first direction are still set on the surface of the glass substrate 1. The synchronization signal transmission channels at both ends of the head and tail include a first wire 6. In this embodiment, the synchronization signal transmission channels other than the head and tail ends (i.e., the synchronization signal transmission channels between adjacent display driver chips 2) are partially set on the surface of the FPC3. In this embodiment, setting the first transmission channels on the same side can shorten the distance of the first wire 6 from the display driver chip 2 to the FPC3, so that most of the synchronization signal path between the display driver chips 2 is on the FPC3, making its total path resistance much smaller than the ITO resistance value, thereby significantly reducing the delay of the synchronization signal.

[0039] Furthermore, the LCD display screen in this embodiment may also include: a microcontroller; a display data transmission channel connected between each display driver chip 2 and the microcontroller; the display data transmission channel includes a first wire 6 and a second wire 7 connected in sequence; the end of the first wire 6 away from the second wire 7 in the display data transmission channel is connected to the display driver chip 2, and the end of the second wire 7 away from the first wire 6 is connected to the microcontroller. It should be noted that in this embodiment, each display driver chip 2 is connected to the FPC 3 to receive display data transmitted by the microcontroller, and converts the display data given by the microcontroller into a driving signal for each source driver (the driving signal includes grayscale data, which is the voltage corresponding to the grayscale), and finally drives the grayscale displayed by each pixel through the driving signal. In this embodiment, the FPC 3 is used for transmitting display data, and using the FPC 3 to transmit synchronization signals does not increase additional material costs.

[0040] Based on the above embodiments, this application changes the transmission of synchronization signals between adjacent display driver chips from the original method of transmitting the entire signal through high-resistance wires on the glass substrate surface to a method where a portion of the signal is transmitted through low-resistance wires on the FPC surface. By providing low-resistance wires on the FPC surface to connect adjacent display driver chips and enable them to communicate with each other, the total resistance of the synchronization signal transmission channel is significantly reduced compared to communicating solely through high-resistance wires on the glass substrate. This new method more effectively reduces signal transmission delay, significantly reducing the latency of synchronization signals transmitted between multiple display driver chips, thus enabling the cascading of more display driver chips and improving the feasibility of applications in high-resolution displays.

[0041] The above provides a detailed description of an LCD display screen provided by this utility model. For those skilled in the art, based on the ideas of the embodiments of this utility model, there will be changes in the specific implementation methods and application scope. Therefore, the content of this specification should not be construed as a limitation of this utility model.

Claims

1. An LCD display screen, characterized in that, include: A glass substrate and an FPC; at least two display driver chips and at least two first wires are disposed on the surface of the glass substrate; At least one second conductor is provided on the surface of the FPC; The resistance of the second conductor is less than the resistance of the first conductor; A synchronization signal transmission channel is connected between two adjacent display driver chips; At least a portion of the synchronization signal transmission channel is a first transmission channel; the first transmission channel includes a first wire, a second wire, and another first wire connected in sequence; The two first wires in the first transmission channel are respectively connected to the two adjacent display driver chips.

2. The LCD display screen according to claim 1, characterized in that, The FPC is located on the side of the display driver chip near the edge of the glass substrate.

3. The LCD display screen according to claim 2, characterized in that, The display driver chips are arranged sequentially along a first direction; the second direction is perpendicular to the first direction; in the second direction, all the first transmission channels are located on the same side of the display driver chips.

4. The LCD display screen according to claim 1, characterized in that, The first conductor is an ITO conductor.

5. The LCD display screen according to claim 1, characterized in that, The second conductor is a metal conductor.

6. The LCD display screen according to claim 1, characterized in that, The display driver chip is connected to the first wire via conductive adhesive.

7. The LCD display screen according to claim 1, characterized in that, The second wire is connected to the first wire via conductive adhesive.

8. The LCD display screen according to claim 1, characterized in that, Also includes: microcontroller; Each of the display driver chips and the microcontroller is connected to a display data transmission channel; The display data transmission channel includes a first wire and a second wire connected in sequence; In the display data transmission channel, the end of the first wire that is away from the second wire is connected to the display driver chip, and the end of the second wire that is away from the first wire is connected to the microcontroller.

9. The LCD display screen according to any one of claims 1 to 8, characterized in that, All of the aforementioned synchronization signal transmission channels are the first transmission channel.

10. The LCD display screen according to any one of claims 1 to 8, characterized in that, Part of the synchronization signal transmission channel is the first transmission channel, and the remaining part of the synchronization signal transmission channel is the second transmission channel; the second transmission channel includes one of the first wires; The two ends of the first wire in the second transmission channel are respectively connected to the two adjacent display driver chips.

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