Zero intermediate frequency receiving circuit

Abstract

The application discloses a kind of zero intermediate frequency receiving circuits, it is related to radio frequency signal processing technical field, including the radio frequency receiving antenna of connection in turn, low noise amplifier, quadrature demodulator and baseband signal processing unit, quadrature demodulator is also connected with the output end of voltage-controlled oscillator, the input end of voltage-controlled oscillator is connected with voltage control module;Voltage control module includes first resistance network, second resistance network and in-phase amplification unit, the input end of first resistance network inputs first voltage signal, the output end of first resistance network is connected with the output end of second resistance network, the input end of second resistance network inputs second voltage signal, the output end of first resistance network and the output end of second resistance network are also connected with the input end of in-phase amplification unit, the output end of in-phase amplification unit is connected with voltage-controlled oscillator.The application improves the working stability and adaptability of zero intermediate frequency receiving circuit.

Description

Technical Field

[0001] This application relates to the field of radio frequency signal processing technology, and in particular to zero intermediate frequency (IF) receiving circuits. Background Technology

[0002] Zero-IF (zero intermediate frequency) is a radio frequency (RF) receiver architecture whose core idea is to directly down-convert the received RF signal to baseband (around 0Hz), eliminating the intermediate frequency (IF) processing stage found in traditional superheterodyne receivers. This technology is widely used in modern wireless communications (such as Wi-Fi, Bluetooth, 5G, and IoT devices) due to its simplified structure, reduced cost, and ease of integration.

[0003] Zero-IF (zero intermediate frequency) operation places strict requirements on the voltage range of the control signal, especially when it involves the back-end oscillator. Typically, the control voltage needs to be limited to a specific range to ensure the oscillator operates within a linearly adjustable range, thereby achieving stable frequency control characteristics. Since different oscillators, different RF chips, and even different communication standards have different requirements for the voltage control range, the voltage signal acquired or distributed from the front end may have unstable amplitude and inappropriate DC bias. If directly fed into the oscillator, this can lead to inaccurate output frequency, modulation distortion, and even problems with the phase-locked loop (PLL) failing to lock. Utility Model Content

[0004] The main purpose of this application is to provide a zero intermediate frequency (IF) receiving circuit, which aims to solve the problem that the voltage signal directly acquired at the front end cannot be matched with the oscillator.

[0005] To achieve the above objectives, this application adopts the following technical solution:

[0006] This application provides a zero intermediate frequency (IF) receiving circuit, which includes a radio frequency receiving antenna, a low noise amplifier, a quadrature demodulator and a baseband signal processing unit connected in sequence. The quadrature demodulator is also connected to the output terminal of a voltage-controlled oscillator, and the input terminal of the voltage-controlled oscillator is connected to a voltage control module.

[0007] The voltage control module includes a first resistor network, a second resistor network, and a non-inverting amplifier unit. The input terminal of the first resistor network receives a first voltage signal, and the output terminal of the first resistor network is connected to the output terminal of the second resistor network. The input terminal of the second resistor network receives a second voltage signal, and the output terminals of the first and second resistor networks are also connected to the input terminal of the non-inverting amplifier unit. The output terminal of the non-inverting amplifier unit is connected to a voltage-controlled oscillator.

[0008] In one embodiment, the first resistor network includes a first resistor, a second resistor, a third resistor, and a fourth resistor;

[0009] One end of the first resistor is connected to one end of the second resistor. One end of the first resistor and one end of the second resistor are both connected to the first voltage signal. The other end of the first resistor and the other end of the second resistor are connected. The other end of the first resistor and the other end of the second resistor are also connected to one end of the third resistor and one end of the fourth resistor. One end of the third resistor and one end of the fourth resistor are connected. The other end of the third resistor is grounded. The other end of the fourth resistor is connected to the other end of the second resistor network and the in-phase amplifier unit, respectively.

[0010] In one embodiment, the second resistor network includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor;

[0011] One end of the fifth resistor is connected to one end of the sixth resistor. One end of the fifth resistor and one end of the sixth resistor are both connected to the second voltage signal. The other end of the fifth resistor is connected to the other end of the sixth resistor. The other end of the fifth resistor and the other end of the sixth resistor are both connected to one end of the seventh resistor. The other end of the seventh resistor is connected to one end of the eighth resistor. One end of the eighth resistor is also connected to one end of the ninth resistor. The other end of the eighth resistor is connected to the output terminal of the first resistor network and the non-inverting amplifier unit, respectively. The other end of the ninth resistor is grounded.

[0012] In one embodiment, the in-phase amplifier unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, and an operational amplifier;

[0013] The output terminals of the first resistor network and the second resistor network are connected to the non-inverting input terminal of the operational amplifier through the tenth resistor. One end of the eleventh resistor is connected to one end of the twelfth resistor and the inverting input terminal of the operational amplifier, respectively. The other end of the eleventh resistor is connected to the output terminal of the operational amplifier. One end of the twelfth resistor is connected to one end of the eleventh resistor and the inverting input terminal of the operational amplifier, respectively. The other end of the twelfth resistor is grounded.

[0014] In one embodiment, the voltage value of the first voltage signal is less than the voltage value of the second voltage signal.

[0015] One or more technical solutions proposed in this application have at least the following technical effects:

[0016] By introducing a voltage control module into the zero-IF receiver circuit, and utilizing the cooperation of a resistor network and a non-inverting amplifier unit, unstable or improperly amplitude voltage signals from the front end are precisely processed and converted into stable control voltages limited to a specific range. This reliably drives the voltage-controlled oscillator (VCO) within its linearly adjustable range, ensuring the accuracy and stability of the output frequency and avoiding problems such as frequency drift, modulation distortion, or phase-locked loop (PLL) lockout failure caused by voltage mismatch. This solution not only improves the operational stability and adaptability of the zero-IF receiver circuit but also boasts advantages such as simple structure, ease of integration, and adaptability to different oscillator voltage requirements, thus meeting the application needs of various wireless communication systems. Attached Figure Description

[0017] Figure 1 This is a schematic diagram of the module connection of the zero intermediate frequency receiving circuit in an embodiment of this application.

[0018] Figure 2 This is a schematic diagram of the module connection of the voltage control module in an embodiment of this application.

[0019] Figure 3 This is a circuit connection diagram of the voltage control module in an embodiment of this application.

[0020] The realization of the purpose, functional features and advantages of this application will be further explained in conjunction with the embodiments and with reference to the accompanying drawings. Detailed Implementation

[0021] To make the objectives, technical solutions, and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of this application, and not all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0022] It should be noted that in this application, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that an apparatus or system comprising a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such an apparatus or system. Without further limitations, an element defined by the phrase "comprising..." does not exclude the presence of other identical elements in the apparatus or system including that element. In this application, unless otherwise expressly specified and limited, the terms "connected," "fixed," etc., should be interpreted broadly. For example, "connected" can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium; it can be the internal communication of two elements or the interaction between two elements. In this application, if descriptions refer to "first," "second," etc., such descriptions are for descriptive purposes only and should not be construed as indicating or implying their relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first" or "second" may expressly or implicitly include at least one of those features. For those skilled in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances. Furthermore, the technical solutions of the various embodiments can be combined with each other, but only on the basis that those skilled in the art can implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection claimed in this application.

[0023] Zero-IF (zero intermediate frequency) receiver architecture is a widely used receiving method in modern wireless communication systems. Its core idea is to directly down-convert the radio frequency signal received by the antenna to baseband (i.e., a frequency close to 0 Hz) using a mixer, thus eliminating the intermediate frequency processing stage found in traditional superheterodyne receivers. This architecture has advantages such as simple structure, fewer components, ease of integration, and low cost, and is therefore widely used in products such as Wi-Fi, Bluetooth, 5G, and the Internet of Things.

[0024] However, although zero-IF receivers have a simple architecture, they have strict requirements on the voltage range of the signal, especially when it comes to the back-end oscillator. Usually, the control voltage needs to be limited to a specific range to ensure that the oscillator operates in the linearly adjustable range, thereby obtaining stable frequency control characteristics.

[0025] The practical problem is that different oscillators, different RF chips, and even different communication standards have different requirements for voltage control range. Moreover, the voltage signal acquired or distributed by the front end may have unstable amplitude and inappropriate DC bias. If it is directly fed into the oscillator, it will lead to inaccurate output frequency, modulation distortion, and even the inability of the phase-locked loop to lock.

[0026] To address the aforementioned technical problems, this application provides a zero-IF receiving circuit, the specific embodiments and implementation methods of which are as follows:

[0027] This embodiment proposes a zero intermediate frequency (IF) receiver circuit. Figure 1 This is a schematic diagram of the module connection of the zero intermediate frequency (IF) receiver circuit in this embodiment. Figure 2 This is a schematic diagram of the module connection of the voltage control module in this embodiment. Figure 3 This is a schematic diagram of the module circuit connection of the voltage control module in this embodiment. The following is in conjunction with... Figure 1 , Figure 2 and Figure 3 This embodiment provides a detailed description of a zero-IF receiving circuit.

[0028] In this embodiment, the zero intermediate frequency (IF) receiving circuit includes a radio frequency receiving antenna, a low-noise amplifier, a quadrature demodulator, and a baseband signal processing unit connected in sequence. The quadrature demodulator is also connected to the output terminal of a voltage-controlled oscillator (VCO), and the input terminal of the VCO is connected to a voltage control module.

[0029] The voltage control module includes a first resistor network R1, a second resistor network R2, and a non-inverting amplifier unit. The input terminal of the first resistor network R1 receives a first voltage signal, and the output terminal of the first resistor network R1 is connected to the output terminal of the second resistor network R2. The input terminal of the second resistor network R2 receives a second voltage signal, and the output terminals of the first resistor network R1 and the second resistor network R2 are also connected to the input terminal of the non-inverting amplifier unit. The output terminal of the non-inverting amplifier unit is connected to a voltage-controlled oscillator.

[0030] The first resistor R1 network includes a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. One end of the first resistor R1 is connected to one end of the second resistor R2. One end of both the first resistor R1 and one end of the second resistor R2 are connected to a first voltage signal. The other end of the first resistor R1 is connected to the other end of the second resistor R2. The other ends of the first resistor R1 and the second resistor R2 are also connected to one end of the third resistor R3 and one end of the fourth resistor R4. One end of the third resistor R3 and one end of the fourth resistor R4 are connected. The other end of the third resistor R3 is grounded. The other end of the fourth resistor R4 is connected to the other end of the second resistor R2 network and the in-phase amplifier unit.

[0031] The second resistor network R2 includes a fifth resistor R5, a sixth resistor R6, a seventh resistor R7, an eighth resistor R8, and a ninth resistor R9. One end of the fifth resistor R5 is connected to one end of the sixth resistor R6. Both ends of the fifth resistor R5 and the sixth resistor R6 are connected to a second voltage signal. The other ends of the fifth resistor R5 and the sixth resistor R6 are connected to one end of the seventh resistor R7. The other end of the seventh resistor R7 is connected to one end of the eighth resistor R8. One end of the eighth resistor R8 is also connected to one end of the ninth resistor R9. The other end of the eighth resistor R8 is connected to the output terminal of the first resistor network R1 and the non-inverting amplifier unit. The other end of the ninth resistor R9 is grounded.

[0032] The non-inverting amplifier unit includes a tenth resistor R10, an eleventh resistor R11, a twelfth resistor R12, and an operational amplifier U1. The output terminals of the first resistor R1 network and the second resistor R2 network are connected to the non-inverting input terminal of the operational amplifier U1 through the tenth resistor R10. One end of the eleventh resistor R11 is connected to one end of the twelfth resistor R12 and the inverting input terminal of the operational amplifier U1, and the other end of the eleventh resistor R11 is connected to the output terminal of the operational amplifier U1. One end of the twelfth resistor R12 is connected to one end of the eleventh resistor R11 and the inverting input terminal of the operational amplifier U1, and the other end of the twelfth resistor R12 is grounded.

[0033] The voltage value of the first voltage signal is less than the voltage value of the second voltage signal.

[0034] Specifically, the zero-IF receiving circuit first receives the RF signal through the RF receiving antenna and amplifies the signal using a low-noise amplifier. Then, the signal enters the quadrature demodulator, where it is mixed with the in-phase and quadrature components of the local oscillator signal generated by the voltage-controlled oscillator (VCO) to generate the baseband I and Q signals. Next, the baseband signal processing unit removes unwanted high-frequency components from the baseband signal (for example, by adjusting the signal gain through a variable gain amplifier and removing unwanted high-frequency components using a low-pass filter) before outputting it to subsequent processing units. The input voltage of the VCO is provided by the voltage control module. The overall structure is divided into two main parts. The first part is a dual voltage divider input network, consisting of a first resistor network and a second resistor network. The first resistor network consists of a first resistor R1, a second resistor R2, a third resistor R3, and a fourth resistor R4. The first voltage signal VDD1 is divided by the first resistor network to generate the first precise DC level (Ui1). The second resistor network consists of the fifth resistor R5, the sixth resistor R6, the seventh resistor R7, the eighth resistor R8, and the ninth resistor R9. The second voltage signal VDD2 is precisely divided by the second resistor network to generate a second precise DC level (Ui2).

[0035] The non-inverting amplifier unit includes operational amplifier U1, tenth resistor R10, eleventh resistor R11, and twelfth resistor R12. Fourth resistor R4 and fifth resistor R5 connect the outputs of the two resistor networks to the non-inverting input (+) of operational amplifier U1 via tenth resistor R10, forming a non-inverting adder input structure. In this embodiment, operational amplifier U1 operates in non-inverting adder mode, and the closed-loop gain is set via eleventh resistor R11 and twelfth resistor R12.

[0036] Understandably, the voltage control module determines the reference level and ratio through the front-end voltage divider, and controls the overall output range through the back-end operational amplifier gain. The two can be adjusted independently without interfering with each other, making it easier to debug and adapt to different target oscillators.

[0037] Furthermore, the voltage value of the first voltage signal is less than the voltage value of the second voltage signal.

[0038] In one example, the voltage value of the first voltage signal VDD1 is 1.3V, and the voltage value of the second voltage signal VDD2 is 5V. In this example, the first resistor R1 (2KΩ) and the second resistor R2 (100KΩ) are connected in parallel and then connected to the third resistor R3 (56KΩ) and the fourth resistor R4 (56KΩ) respectively. The other end of the third resistor R3 is grounded, and the other end of the fourth resistor R4 serves as the output terminal of the first resistor network and is connected to the second resistor network and the non-inverting amplifier unit. The fifth resistor R5 (3.3KΩ) and the sixth resistor R6 (2.4KΩ) are connected in parallel and then connected to one end of the eighth resistor R8 (56KΩ) and the ninth resistor R9 (56KΩ) respectively through the seventh resistor R7 (9.16KΩ). The other end of the eighth resistor R8 serves as the output terminal of the second resistor network and is connected to the output terminal of the first resistor network and the non-inverting amplifier unit respectively. The non-inverting amplifier unit consists of an operational amplifier U1, a tenth resistor R10 (10KΩ), an eleventh resistor R11 (1.8KΩ), and a twelfth resistor R12 (750Ω). The positive input terminal of the operational amplifier U1 is connected to the first resistor network and the second resistor network through the tenth resistor R10. The inverting input terminal of the operational amplifier U1 is connected to the output terminal of the operational amplifier U1 through the feedback resistor (eleventh resistor R11) and grounded through the twelfth resistor R12.

[0039] This example demonstrates high-precision voltage range adjustment through a parallel voltage divider formed by multiple resistors in the first and second resistor networks. Then, the operational amplifier (op-amp) is used to adjust the required voltage range, creating a suitable voltage level. Specifically, the output voltages of the two voltage divider networks are sent to the non-inverting input of the op-amp via resistors R4 and R8, forming a weighted voltage sum U(+) = [R4 / (R4+R8)]*Ui2 + [R8 / (R4+R8)]*Ui1. Here, R4 and R8 act as input weighting resistors, determining the proportion of the two input voltages in the sum. By adjusting the values ​​of R4 and R8, the bias level and amplitude input to the op-amp can be controlled. With the op-amp in positive amplification mode, the output voltage value is obtained using the positive amplification formula Uout = (1 + R11 / R12)*U(+). This amplifies the initially small voltage divider level to the range required by the target oscillator.

[0040] Understandably, this example allows matching the control voltage range required by different voltage-controlled oscillators (VCOs) by changing the voltage divider resistors and op-amp gain. Adjusting the voltage divider and gain separately prevents mutual interference, facilitating rapid fine-tuning during experiments. The high input impedance of the non-inverting amplifier minimizes its impact on the voltage divider network, resulting in low output noise. It is important to note that during PCB layout, the voltage divider resistor network should be kept away from high-frequency lines and inductors to reduce induced interference. The reference voltage point should use a low-noise power supply or be stabilized through an RC filter. The op-amp power supply must have good decoupling capacitors to prevent high-frequency oscillations.

[0041] In summary, this embodiment introduces a voltage control module into the zero-IF receiver circuit. By utilizing a resistor network and a non-inverting amplifier unit, it precisely processes unstable or improperly amplituded voltage signals from the front end, converting them into stable control voltages limited to a specific range. This reliably drives the voltage-controlled oscillator (VCO) within its linearly adjustable range, ensuring the accuracy and stability of the output frequency and avoiding problems such as frequency drift, modulation distortion, or PLL lockout failure caused by voltage mismatch. This solution not only improves the operational stability and adaptability of the zero-IF receiver circuit but also offers advantages such as simple structure, ease of integration, and adaptability to different oscillator voltage requirements, thus meeting the application needs of various wireless communication systems.

[0042] In this embodiment, the above are merely preferred embodiments of this application and do not limit the patent scope of this application. Any equivalent structural or procedural transformations made using the content of this application's specification and drawings, or direct or indirect applications in other related technical fields, are similarly included within the patent protection scope of this application.

Claims

1. A zero-IF receiver circuit, characterized in that, It includes a radio frequency receiving antenna, a low-noise amplifier, a quadrature demodulator and a baseband signal processing unit connected in sequence. The quadrature demodulator is also connected to the output of a voltage-controlled oscillator, and the input of the voltage-controlled oscillator is connected to a voltage control module. The voltage control module includes a first resistor network, a second resistor network, and a non-inverting amplifier unit. The input terminal of the first resistor network receives a first voltage signal, and the output terminal of the first resistor network is connected to the output terminal of the second resistor network. The input terminal of the second resistor network receives a second voltage signal. The output terminals of the first resistor network and the second resistor network are also connected to the input terminal of the non-inverting amplifier unit, and the output terminal of the non-inverting amplifier unit is connected to the voltage-controlled oscillator.

2. The zero-IF receiving circuit according to claim 1, characterized in that, The first resistor network includes a first resistor, a second resistor, a third resistor, and a fourth resistor; One end of the first resistor is connected to one end of the second resistor, and both ends of the first resistor and the second resistor are connected to a first voltage signal. The other ends of the first resistor and the second resistor are connected to each other. The other ends of the first resistor and the second resistor are also connected to one end of the third resistor and one end of the fourth resistor. One end of the third resistor and one end of the fourth resistor are connected to each other. The other end of the third resistor is grounded. The other end of the fourth resistor is connected to the other end of the second resistor network and the in-phase amplifier unit.

3. The zero-IF receiving circuit according to claim 1, characterized in that, The second resistor network includes a fifth resistor, a sixth resistor, a seventh resistor, an eighth resistor, and a ninth resistor; One end of the fifth resistor is connected to one end of the sixth resistor. One end of the fifth resistor and one end of the sixth resistor are both connected to a second voltage signal. The other end of the fifth resistor is connected to the other end of the sixth resistor. The other end of the fifth resistor and the other end of the sixth resistor are both connected to one end of the seventh resistor. The other end of the seventh resistor is connected to one end of the eighth resistor. One end of the eighth resistor is also connected to one end of the ninth resistor. The other end of the eighth resistor is connected to the output terminal of the first resistor network and the non-inverting amplifier unit, respectively. The other end of the ninth resistor is grounded.

4. The zero-IF receiving circuit according to claim 1, characterized in that, The in-phase amplifier unit includes a tenth resistor, an eleventh resistor, a twelfth resistor, and an operational amplifier; The output terminals of the first resistor network and the second resistor network are connected to the non-inverting input terminal of the operational amplifier through the tenth resistor. One end of the eleventh resistor is connected to one end of the twelfth resistor and the inverting input terminal of the operational amplifier, respectively. The other end of the eleventh resistor is connected to the output terminal of the operational amplifier. One end of the twelfth resistor is connected to one end of the eleventh resistor and the inverting input terminal of the operational amplifier, respectively. The other end of the twelfth resistor is grounded.

5. The zero-IF receiving circuit according to claim 1, characterized in that, The voltage value of the first voltage signal is less than the voltage value of the second voltage signal.

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