A frequency constant multi-step duty ratio adjustable circuit
By using a frequency-constant, multi-level adjustable duty cycle circuit, employing a third-party process library buffer as a delay unit, and combining components such as an RC oscillator, the chip area and power consumption issues caused by PLLs were resolved, achieving a circuit design with high-precision duty cycle adjustment and low power consumption.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Utility models(China)
- Current Assignee / Owner
- XIAN JINGHUIXIN SEMICONDUCTOR TECHNOLOGY CO LTD
- Filing Date
- 2025-07-30
- Publication Date
- 2026-06-19
AI Technical Summary
Traditional PLL designs increase chip area and power consumption, and are costly, making it difficult to achieve low power consumption when outputting high-frequency, high-precision clocks.
A frequency-constant, multi-level adjustable duty cycle circuit is adopted. The standard buffer cell provided by a third-party technology library is used as the delay unit. The duty cycle of the output square wave is adjustable in multiple levels through simple logic gates. Combined with components such as RC oscillator, gate control unit, fractional frequency divider and multiplexer, the dependence on PLL is reduced.
It achieves high-precision duty cycle adjustment, reduces chip area and power consumption, lowers costs, and maintains constant frequency, thereby improving the circuit's performance balance.
Smart Images
Figure CN224385482U_ABST
Abstract
Description
Technical Field
[0001] This utility model relates to the technical field of frequency-constant multi-level duty cycle adjustable circuits, specifically a frequency-constant multi-level duty cycle adjustable circuit. Background Technology
[0002] In modern integrated circuit design, frequency and duty cycle adjustment are key factors in achieving high performance and low power consumption. Especially in circuit designs involving high-speed clock signals and precise delay control, the use of phase-locked loops (PLLs) to generate high-frequency clock signals as the sampling output clock for delay circuits has become a common method. PLLs can provide accurate clock outputs, ensuring timing consistency and stability, and are widely used in communications, digital signal processing, and radio frequency systems.
[0003] However, with the increasing complexity of chip design, traditional PLL designs have certain limitations. First, while PLLs can output high-frequency clock signals, the resulting increase in chip area and cost requires additional hardware resources and IP licensing fees, which is particularly significant in large-scale integrated circuits. Second, PLL operation typically involves significant power consumption, especially at high frequencies, where power consumption is often quite substantial. This necessitates designers to consider additional low-power processing schemes to ensure the overall power consumption of the chip remains acceptable.
[0004] Therefore, in order to reduce chip area and power consumption while meeting the requirements of high-frequency, high-precision clock output, a frequency-constant, multi-level adjustable duty cycle circuit has emerged. This type of circuit can flexibly adjust the duty cycle according to application requirements and optimize power consumption and performance through multi-level design, avoiding the drawbacks of over-reliance on PLLs. Its key technology lies in precisely controlling the duty cycle of the output signal through different adjustment mechanisms while maintaining a constant frequency, thereby achieving a balance between high efficiency and low power consumption.
[0005] Internally, chips typically output a low-frequency clock via an RC oscillator, or a high-frequency clock via an internal PLL circuit. The PLL's reference clock comes from an external pin or the internal RC oscillator. The high-frequency clock output from the PLL or the RC oscillator can be fed to other parts of the chip as a working clock, or it can be divided by a frequency divider and then fed to other parts of the chip as a working clock. If the chip only has an RC oscillator (typically outputting a square wave with a 1:1 duty cycle), and an adjustable duty cycle (i.e., an adjustable high-level pulse width) is required, an internal PLL is necessary to output a high-frequency clock as the sampling clock. This necessitates adding a PLL module internally, increasing chip cost and power consumption. No solution has yet been proposed to address these technical issues. Utility Model Content
[0006] To address the problems in related technologies, this invention proposes a frequency-constant, multi-level adjustable duty cycle circuit to overcome the aforementioned technical issues in existing technologies. The purpose of this invention is to use standard buffer units provided by a third-party process library as delay units, and to achieve multi-level adjustable duty cycle of the output square wave through simple logic gates, thereby saving circuit implementation resources and complexity. The adjustable accuracy of the square wave can be achieved at the 1-2ns level for each level, resulting in high precision.
[0007] To achieve the above objectives, this utility model provides the following technical solution: a frequency-constant type multi-level duty cycle adjustable circuit, comprising:
[0008] The multiple programmable memory retains its contents even when power is off and can be reprogrammed and updated multiple times according to user needs to save critical information inside the chip.
[0009] An RC oscillator generates oscillation using an amplifier and a feedback network. Different frequencies can be output by adjusting the values of resistors and capacitors. It serves as the internal clock source of the chip and is connected to a multiple programmable memory.
[0010] A gated unit, clock-gated, can switch the clock output according to an enable signal, serving as a low-power processing logic unit. The gated unit is connected to an RC oscillator.
[0011] The fractional frequency divider performs corresponding frequency division processing on the clock source according to the configuration parameters, and supports fractional frequency division. The fractional frequency divider is connected to the gate control unit.
[0012] The delay unit uses a buffer provided by a third-party technology library as the delay unit to delay the square wave output from the clock source by 1-2ns.
[0013] AND gates implement AND logic, and the AND gates are connected to delay units;
[0014] OR gate, implementing OR logic, the OR gate is connected to a delay unit;
[0015] A multiplexer is used to perform path selection, and the multiplexer is connected to AND gates and OR gates respectively.
[0016] Preferably, the multiple programmable memory mainly performs the function of actively loading the key information stored inside the chip as soon as the chip is powered on.
[0017] Preferably, the fractional frequency divider performs fractional frequency division on the output frequency of the RC oscillator, and the specific value of the output frequency division can be adjusted according to different configuration parameters.
[0018] Preferably, the delay unit calls the standard buffer of the process library as the delay unit, which can perform multi-level delay on the square wave provided by the clock source, and send the taps of the multi-level delay to the next level respectively to complete the calculation of the AND gate and OR gate.
[0019] Preferably, the multiplexer selects which stage of delay output to be the final output of the circuit.
[0020] Compared with the prior art, the beneficial effects of this utility model are:
[0021] This invention relates to a frequency-constant, multi-level adjustable duty cycle circuit. It uses standard buffer cells provided by a third-party process library as delay units and achieves multi-level adjustable duty cycle of the output square wave through simple logic gates, saving circuit implementation resources and complexity. The adjustable accuracy of the square wave can reach the 1-2ns level for each level, achieving high precision. It does not use the commonly used PLL structure as the sampling clock for delay, reducing chip area cost and power consumption. Attached Figure Description
[0022] Figure 1 This is a structural block diagram of the entire utility model;
[0023] Figure 2 This is a schematic diagram of the internal structure of the delay unit of this utility model;
[0024] Figure 3 This is a waveform diagram of the actual control of this utility model;
[0025] Figure 4 This is a schematic diagram of the structure of the multiplexer of this utility model.
[0026] Explanation of reference numerals in the attached figures:
[0027] 100. Multiple Programmable Memory; 101. RC Oscillator; 102. Gating Unit; 103. Fractional Divider; 104. Delay Unit; 105. AND Gate; 106. OR Gate; 107. Multiplexer. Detailed Implementation
[0028] The technical solutions of the present invention will be clearly and completely described below with reference to the accompanying drawings of the embodiments of the present invention.
[0029] Example
[0030] Please see Figure 1-4 This utility model proposes a technical solution for a frequency-constant, multi-level adjustable duty cycle circuit: a frequency-constant, multi-level adjustable duty cycle circuit, comprising:
[0031] The multiple programmable memory 100 retains its stored content even when power is off and can be reprogrammed and updated multiple times as needed by the user. It is used to save key information inside the chip; specifically, the key information includes chip ID number, version number, key, analog circuit configuration parameters, etc.
[0032] The RC oscillator 101 generates oscillation using an amplifier and a feedback network. Different frequencies can be output by adjusting the values of resistors and capacitors. As the internal clock source of the chip, the RC oscillator 101 is connected to the multiple programmable memory 100.
[0033] Gating unit 102, clock gating, can switch the clock output according to the enable signal, and serves as a low-power processing logic unit. Gating unit 102 is connected to RC oscillator 101.
[0034] The fractional frequency divider 103 performs corresponding frequency division processing on the clock source according to the configuration parameters, and supports fractional frequency division. The fractional frequency divider 103 is connected to the gate control unit 102; specifically, it can perform frequency divisions of 2.5, 3.5, 4.5, etc.
[0035] Delay unit 104 uses a buffer provided by a third-party technology library as a delay unit to delay the square wave output from the clock source by 1-2ns.
[0036] AND gate 105 implements AND logic and is connected to delay unit 104;
[0037] OR gate 106 implements OR logic and is connected to delay unit 104;
[0038] Multiplexer 107 enables 1-to-1 selection from 128 channels. Multiplexer 107 is connected to AND gate 105 and OR gate 106 respectively.
[0039] In this embodiment, as Figure 1 As shown, the RC oscillator 101 outputs 40MHz. After passing through the gating unit 102, the subsequent drive of this clock can be turned off at any time to reduce power consumption. The fractional divider 103 performs fractional division of the output frequency of the RC oscillator 101. The specific value of the output division can be adjusted according to different configuration parameters. This example mainly supports four frequency points: 1.7MHz, 2.4MHz, 3MHz, and 3.2MHz. The delay unit 104 calls the standard buffer in the technology library as the delay unit, which can perform multi-level delay on the square wave provided by the clock source, and send the taps of the multi-level delay to the next level, namely AND gate 105 and OR gate 106. After processing by AND gate 105 and OR gate 106, it is sent to the multiplexer 107 to complete the final multiplexing and output.
[0040] like Figure 2The delay unit 104 in the application example is shown. Its internal structure can call three buffers from third-party process libraries as the delay unit. The delay range of the delay unit 104 is approximately 1 to 2 ns. This value may change depending on the specific parameters of the third-party process library, but it will not affect the final function.
[0041] Figure 3 The diagram shows the actual control waveform of this invention. The RC oscillator 101 outputs a square wave with an original 1:1 duty cycle. The output waveform of the delay unit 104 is a square wave with a certain delay from the square wave output by the RC oscillator 101. Different delay taps can be selected, such as a 1-stage delay (through one delay unit 104), a 2-stage delay (through one delay unit 104), a 3-stage delay (through three delay units 104), etc. The output of the AND gate 105 is a logical AND operation between the output of the RC oscillator 101 and the output of the delay unit 104. The output of the OR gate 106 is a logical OR operation between the output of the RC oscillator 101 and the output of the delay unit 104.
[0042] Figure 4 The diagram shows a multiplexer 107 described in this utility model. The input of the multiplexer 107 comes from the output of AND gate 105 and OR gate 106. Different taps correspond to delay level adjustment taps of level 1, level 2, level 3, up to level 64. The final output is controlled by the SEL signal.
[0043] Furthermore, the multiple programmable memory 100 mainly performs the task of actively loading the key information stored inside the chip as soon as it is powered on.
[0044] In this embodiment, simulated configuration parameters are provided to the internal RC circuit so that its output clock frequency meets the system requirements.
[0045] Furthermore, the fractional frequency divider 103 performs fractional frequency division on the output frequency of the RC oscillator 101. The specific value of the output frequency division can be adjusted according to different configuration parameters.
[0046] In this embodiment, four frequency outputs are supported: 1.7MHz, 2.4MHz, 3MHz, and 3.2MHz.
[0047] Please see Figure 1 As shown, further, the delay unit 104 calls the standard buffer of the technology library as the delay unit, which can perform multi-level delay on the square wave provided by the clock source, and send the taps of the multi-level delay to the next level respectively to complete the calculation of AND gate 105 and OR gate 106.
[0048] Furthermore, the multiplexer 107 selects which stage of delay output to use as the final output of the circuit.
[0049] This invention uses a buffer standard cell provided by a third-party process library as a delay unit. It achieves multi-level adjustable duty cycle of the output square wave through simple logic gates, saving circuit implementation resources and complexity. The adjustable accuracy of the square wave can reach the 1-2ns level for each level, achieving high precision. This invention does not use the commonly used PLL structure as the sampling clock for the delay, reducing chip area cost and power consumption.
[0050] In the description of this utility model, it should be understood that the terms "coaxial", "bottom", "one end", "top", "middle", "other end", "upper", "side", "top", "inner", "front", "center", "both ends", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the drawings. They are only for the convenience of describing this utility model and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this utility model.
[0051] In this utility model, unless otherwise explicitly specified and limited, the terms "installation", "setting", "connection", "fixing", "screw connection", etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal connection of two components or the interaction between two components. Unless otherwise explicitly limited, those skilled in the art can understand the specific meaning of the above terms in this utility model according to the specific circumstances.
[0052] Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the present invention, the scope of which is defined by the appended claims and their equivalents.
Claims
1. A frequency-constant, multi-level adjustable duty cycle circuit, characterized in that, include: The multiple programmable memory (100) does not lose its stored contents when power is off and can be reprogrammed and updated multiple times according to user needs to save key information inside the chip. An RC oscillator (101) generates oscillation using an amplifier and a feedback network. Different frequencies are output by adjusting the resistance and capacitance values. As the internal clock source of the chip, the RC oscillator (101) is connected to a multiple programmable memory (100). The gate unit (102) is clock-gated and can switch the clock output according to the enable signal. It serves as a low-power processing logic unit. The gate unit (102) is connected to the RC oscillator (101). The fractional frequency divider (103) performs corresponding frequency division processing on the clock source according to the configuration parameters, and supports fractional frequency division. The fractional frequency divider (103) is connected to the gate control unit (102). The delay unit (104) uses a buffer provided by a third-party technology library as the delay unit to delay the square wave output from the clock source by 1-2ns. AND gate (105) implements AND logic, and the AND gate (105) is connected to the delay unit (104); OR gate (106) implements OR logic, and the OR gate (106) is connected to the delay unit (104); A multiplexer (107) enables 1-to-1 selection from 128 channels. The multiplexer (107) is connected to an AND gate (105) and an OR gate (106) respectively.
2. The frequency constant multi-step duty cycle adjustable circuit according to claim 1, characterized in that: The multiple programmable memory (100) is mainly responsible for actively loading the key information stored inside the chip when it is powered on.
3. The frequency constant multi-step duty cycle adjustable circuit according to claim 1, characterized in that: The fractional frequency divider (103) performs fractional frequency division on the output frequency of the RC oscillator (101). The specific value of the output frequency division can be adjusted according to different configuration parameters.
4. The frequency-constant type multi-level duty cycle adjustable circuit according to claim 1, characterized in that: The delay unit (104) calls the standard buffer of the process library as the delay unit, which can perform multi-level delay on the square wave provided by the clock source, and send the taps of the multi-level delay to the next level respectively, and complete the calculation of the AND gate (105) and OR gate (106).
5. The frequency-constant type multi-level duty cycle adjustable circuit according to claim 1, characterized in that: The multiplexer (107) selects which stage of delay output is the final output of the circuit.