Low-power-consumption phase-locked loop circuit with automatic frequency calibration

Abstract

The invention discloses a low-power-consumption phase-locked loop circuit with an automatic frequency calibration function. Comprising a voltage-controlled oscillator, an automatic frequency calibration module, a programmable frequency divider, a phase frequency detector, a plurality of charge pump arrays and a switch filter, wherein the automatic frequency calibration module and the programmable frequency divider are in signal connection with the voltage-controlled oscillator; the phase frequency detector is in signal connection with the programmable frequency divider; the charge pump arrays are in signal connection with the phase frequency detector; the switch filter is in signal connection with the voltage-controlled oscillator; the voltage-controlled oscillator comprises a plurality of delay units, and the voltage-controlled oscillator is an annular oscillator formed by cascading a plurality of delay unit rings. The delay unit is a cross-coupled structure based on an inverter and comprises a plurality of transistors, and the plurality of transistors comprise a plurality of PMOS (P-channel Metal Oxide Semiconductor) transistors and a plurality of NMOS (N-channel Metal Oxide Semiconductor) transistors. According to the invention, under the low power supply voltage, four-phase intermediate frequency signals are output with extremely low power consumption, and the application requirements of rapid locking and low noise are met.

Description

Technical Field

[0001] The invention relates to the technical field of analog integrated circuits, and in particular to a low-power consumption phase-locked loop circuit with automatic frequency calibration. Background Art

[0002] With the development of phase-locked loop technology, many phase-locked loop architectures have been proposed, such as charge pump phase-locked loop, sub-sampling phase-locked loop, and full digital phase-locked loop.

[0003] The traditional phase-locked loop structure has high power consumption and basically works at a power supply voltage greater than or equal to 0.5V. According to the output frequency band, it can usually be divided into two categories. One is a high-frequency phase-locked loop with an output frequency of GHz, which is often used in transmitters to generate high-frequency carrier signals. The phase noise requirements of this type of phase-locked loop are strict, and LC oscillators are basically used as voltage-controlled oscillators. At the same time, in order to suppress the noise in the band, sub-sampling phase-locked loop structures are increasingly used. Although this type of phase-locked loop can output high frequencies at the GHz level and obtain clock jitter at the fs level, the power consumption has often reached the mW level. At the same time, the use of inductors increases the complexity of the layout design. The other is a phase-locked loop with an output frequency of MHz, which is often used to generate intermediate frequency clocks. The phase noise requirements of this type of phase-locked loop are relatively less stringent, and ring oscillators are basically used as voltage-controlled oscillators. In order to suppress the noise of the ring oscillator, a phase-locked loop architecture with a larger bandwidth is usually selected. However, at a power supply voltage greater than 0.5V, the power consumption of this type of phase-locked loop is still at least tens of μW. In the application of passive Internet of Things, its power consumption is still relatively large.

[0004] In recent years, a dual-loop charge pump phase-locked loop architecture has been proposed under a power supply voltage of 0.3 to 0.4V. According to the influence of the loop control voltage on the frequency of the voltage-controlled oscillator, it can be divided into a low-gain branch and a high-gain branch. The charge pump of the low-gain branch only contains a pull-up current, so there is no current mismatch. Although the current of the high-gain branch is adapted, when its current is much smaller than that of the high-gain branch, the reference spurious caused by it is suppressed by the low-gain branch. At the same time, due to the existence of the high-gain branch, a certain degree of frequency adjustment range can be met. However, it still has several problems: First, it is not suitable for wide-band output. Because the frequency adjustment range of the voltage-controlled oscillator is quite limited by the two loop control voltages. Second, it is difficult for the adopted voltage-controlled oscillator structure to output a signal with a duty cycle of about 50%. In this dual-loop charge pump phase-locked loop architecture, the two control voltages are connected to the gate and substrate of the PMOS transistor respectively. As the control voltage changes, the strength of the pull-up current and the strength of the NMOS pull-down current cannot remain consistent, so its duty cycle will change greatly with the change of the control voltage. Third, the dual-loop phase-locked loop structure cannot control the size of the locking voltage. Depending on the relative strength of the two loops, the current frequency, and the current working environment, the final two control voltages will fall at a random value that is difficult to predict. When the control voltage is close to the ground or power supply, there will be a large current mismatch for the high-gain branch, which will cause the reference spurious and noise of the output signal to deteriorate. Summary of the invention

[0005] In view of the shortcomings of the prior art, the purpose of the present invention is to provide a low-power phase-locked loop circuit with automatic frequency calibration, which outputs a four-phase intermediate frequency signal with extremely low power consumption under low power supply voltage and meets the application requirements of fast locking and low noise. In order to achieve the above-mentioned purpose and other advantages according to the present invention, a low-power phase-locked loop circuit with automatic frequency calibration is provided, comprising:

[0006] A voltage controlled oscillator, an automatic frequency calibration module connected to the voltage controlled oscillator signal and a programmable frequency divider, a frequency detector connected to the programmable frequency divider signal, a plurality of charge pump arrays connected to the frequency detector signal and a switch filter connected to the charge pump signal, wherein the switch filter is connected to the voltage controlled oscillator signal;

[0007] Wherein, the voltage-controlled oscillator comprises a plurality of delay units, and the voltage-controlled oscillator is a ring oscillator composed of a plurality of the delay units cascaded in a ring;

[0008] The delay unit is based on a cross-coupled structure of an inverter, and the delay unit includes a plurality of transistors, wherein the plurality of transistors include a plurality of PMOS transistors and a plurality of NMOS transistors;

[0009] The gates of at least two PMOS transistors and two NMOS transistors are connected to the differential input of the delay unit, and the gates of at least two PMOS transistors and two NMOS transistors are connected to the differential output of the delay unit;

[0010] The sources of all PMOS transistors are connected to the power supply, and the drains are connected to the differential output of the delay unit;

[0011] The sources of all the NMOS transistors are grounded, and the drains are connected to the differential outputs of the delay unit.

[0012] Preferably, the programmable frequency divider comprises a pre-divider, an arbitrary frequency divider and a multiplexer, wherein the arbitrary frequency divider is composed of a 5-bit counter based on a trigger.

[0013] Preferably, the phase frequency detector comprises a trigger including a reset terminal and a combinational logic, and the phase frequency detector is used to output a pull-up signal when the rising edge of the reference clock arrives first;

[0014] When the rising edge of the feedback comes first, the pull-down signal is output;

[0015] When the rising edge of the reference clock and the feedback clock both arrive, reset occurs and the pull-up and pull-down signals are turned off.

[0016] Preferably, the charge pump includes a pull-up current and a pull-down current array at the enable end, and each charge pump array includes a PMOS transistor responsible for providing the pull-up current and an NMOS transistor responsible for the pull-down current.

[0017] Preferably, the switch filter is connected to the current output point of the charge pump on the left side and to the control voltage point of the voltage-controlled oscillator on the right side; and one side of the switch in the switch filter is a second-order filter composed of a capacitor and a resistor, and the other side includes a capacitor;

[0018] The switch is a deep N-well NMOS transistor.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] (1) Low operating voltage. Except for the automatic frequency calibration module, the present invention is designed under a power supply voltage of 0.3V and is suitable for systems with low power supply voltage. The present invention is particularly important for systems where the power is obtained by an energy harvesting module and can only provide a low power supply voltage.

[0021] (2) Extremely low power consumption. A low-power oscillator and loop structure are used to achieve a frequency output of 8.25M~63.25MHz with a power consumption of 2~5uW. This power consumption basically meets the power consumption requirements of all systems, and is especially suitable for passive IoT systems such as backscatter chips.

[0022] (3) High-precision, fast automatic frequency calibration and wide-band output. Using the four-phase clock of the voltage-controlled oscillator for calibration, a frequency calibration with a resolution of 0.25MHz is achieved in a very short calibration time (within 12us), achieving the effect of fast frequency band selection. At the same time, a wider frequency output range is obtained through the switch capacitor array corresponding to this calibration.

[0023] (4) Ensure 50% duty cycle clock output: Since the frequency is adjusted by the varactor and discrete capacitor array, the pull-up current of the PMOS tube and the pull-down current of the NMOS tube in the oscillator will not change with the change of the control voltage. At the same time, the differential structure is adopted, so that the clock output is basically maintained at 50% duty cycle within the output frequency range. This is beneficial to applications with strict duty cycle requirements.

[0024] (5) Low clock jitter at high loop bandwidth: Through an adjustable charge pump array, the highest possible bandwidth can be achieved at different clock frequencies, thereby better suppressing the low-frequency phase noise of the ring oscillator and obtaining better clock jitter. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A schematic diagram of the system structure of a low-power phase-locked loop circuit with automatic frequency calibration according to the present invention;

[0026] Figure 2 A circuit diagram of a voltage-controlled oscillator with a low-power phase-locked loop circuit with automatic frequency calibration according to the present invention;

[0027] Figure 3 The automatic frequency calibration module structure and timing diagram of the low power consumption phase-locked loop circuit with automatic frequency calibration according to the present invention;

[0028] Figure 4 The system working flow chart of the low power consumption phase-locked loop circuit with automatic frequency calibration according to the present invention. DETAILED DESCRIPTION

[0029] The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0030] Reference Figure 1 , a low power phase-locked loop circuit with automatic frequency calibration, comprising:

[0031] A voltage-controlled oscillator, an automatic frequency calibration module connected to the voltage-controlled oscillator signal and a programmable frequency divider, a frequency detector connected to the programmable frequency divider signal, a plurality of charge pump arrays connected to the frequency detector signal and a switch filter connected to the charge pump signal, wherein the switch filter is connected to the voltage-controlled oscillator signal; the input and output are: the input is a reference clock output by a crystal oscillator and shaped into a square wave, and the output is a four-phase square wave clock oscillating from a voltage-controlled oscillator and output through a multi-stage inverter.

[0032] The parameter indicators of the present invention are: the output reference clock is 2.75MHz, the power supply voltage of the analog part (all modules except the automatic frequency calibration module) is 0.3V, the power supply voltage of the digital part (automatic frequency calibration module) is 0.5V, and it is tape-out and tested under 65nm process conditions, the output frequency range is 8.25M~63.25MHz, and the power consumption is about 2~5uW.

[0033] Reference Figure 2 , the voltage-controlled oscillator comprises a plurality of delay units, and the voltage-controlled oscillator is a ring oscillator composed of a plurality of the delay units cascaded in a ring;

[0034] When working, the whole system is reset first, and after the reset is completed, the automatic frequency calibration process is entered first. At this time, the loop of the phase-locked loop is disconnected, the control voltage of the voltage-controlled oscillator is connected to half of the power supply voltage, and the four-phase clock outputted by it is connected to the automatic frequency calibration module. After calibration, the frequency of the voltage-controlled oscillator is roughly adjusted to select a suitable frequency band. After the automatic frequency calibration module is completed, an end signal will be output, and the loop of the phase-locked loop is closed at this time and starts to lock. The reference clock obtained by the external crystal oscillator frequency division and the feedback clock of the voltage-controlled oscillator after the loop frequency divider frequency division are input to the frequency detector; the output control signal controls the opening and closing of the pull-up or pull-down current of the charge pump; the charge pump is connected to the switch filter; at the same time, the output of the frequency detector is also connected to the timing logic of the switch control, so that after the charge pump completes charging the capacitor on the left side of the filter, the switch is turned on to charge the capacitor on the right side. The control voltage output by the switch filter is connected to the voltage control bit of the voltage-controlled oscillator, which is the bottom of the varactor in the present invention, so as to achieve accurate adjustment of the output frequency of the voltage-controlled oscillator. As mentioned above, the clock at this time will be fed back to the frequency detector through the programmable frequency divider in the loop, and the cycle will repeat. Finally, after a period of locking, the phase-locked loop will finally output the required frequency.

[0035] The delay unit is based on a cross-coupled structure of an inverter, and the delay unit includes a plurality of transistors, wherein the plurality of transistors include a plurality of PMOS transistors and a plurality of NMOS transistors;

[0036] The gates of at least two PMOS transistors and two NMOS transistors are connected to the differential input of the delay unit, and the gates of at least two PMOS transistors and two NMOS transistors are connected to the differential output of the delay unit; the sources of all PMOS transistors are connected to the power supply, and the drains are connected to the differential output of the delay unit; the sources of all NMOS transistors are grounded, and the drains are connected to the differential output of the delay unit. Specifically, the voltage-controlled oscillator is a ring oscillator composed of four delay units cascaded in a loop, each delay unit is based on the cross-coupling structure of the inverter, and its delay is mainly determined by the power supply voltage, transistor size, and load capacitance. Each delay unit includes eight transistors, wherein the gates of two PMOS transistors and two NMOS transistors are connected to the differential input of this delay unit, and are also the differential output of the previous delay unit; the gates of the other two PMOS transistors and two NMOS transistors are connected to the differential output of this delay unit. The sources of all PMOS transistors are connected to the power supply, and the drains are connected to the differential output of the delay unit; the sources of all NMOS transistors are grounded, and the drains are connected to the differential output of the delay unit. If the large signal delay of each delay unit is recorded as τ, the output frequency of this oscillator is approximately:

[0037]

[0038] When the power supply voltage is fixed, the frequency can be controlled by adjusting the size of the transistor and the size of the load capacitance. In the present invention, the transistor size is determined by simulation according to the required output frequency range. Therefore, the frequency adjustment is mainly controlled by the nodes connected to the input and output of the delay unit. In the present invention, there are two main adjustment methods for the capacitance: one is to adjust the capacitance of the varactor by adjusting the voltage difference at both ends of the varactor, and the other is to control the capacitor array switch connected to the oscillator to adjust the total capacitance value loaded on the oscillator by the capacitor array. These two adjustment methods correspond to the fine adjustment of the oscillator frequency by the loop control voltage in the closed-loop locking process of the phase-locked loop, and the coarse adjustment of the oscillator frequency by the control code output by the automatic frequency calibration module in the automatic frequency calibration process.

[0039] Furthermore, the programmable frequency divider includes a pre-divider, an arbitrary frequency divider and a multiplexer, wherein the arbitrary frequency divider is composed of a 5-bit counter based on a trigger. When the count reaches the set value, the counter is reset through logical judgment, thereby realizing an arbitrary frequency division of 3 to 31. In order to adapt to a lower reference frequency, it may be necessary to perform pre-division through a pre-divider. In the present invention, a 4-division asynchronous pre-divider and an 11-division synchronous pre-divider are designed, and the frequency division branch is selected through a multiplexer.

[0040] Reference Figure 3The automatic frequency calibration module is responsible for coarse frequency adjustment in the initial stage of operation. At this time, the loop of the phase-locked loop is disconnected, and the control voltage of the voltage-controlled oscillator is connected to half of the power supply voltage. The process of automatic frequency calibration is as follows: the four-phase clock output by the voltage-controlled oscillator is input into four asynchronous counters for counting respectively, and then added, and the sum is subtracted from the preset binary frequency code, and the difference is input into the finite state machine. In the state machine, the initial control code after reset is 1000000. According to the positive and negative input difference, the control code of the next step is searched using a binary search algorithm. According to the size of the difference, it is determined whether it is within the allowable error range. If it is within the allowable error range, it means that the frequency of the voltage-controlled oscillator at this time is already close to the set frequency, so the automatic frequency calibration process is exited in advance. If the difference is not within the allowable error range, the calibration process is continued to update the output control code. Then, the state machine internally determines whether the maximum number of updates has been reached. For example, for the 7-bit control code output by the present invention, the maximum number of updates is 6. When the maximum number of updates is reached, the automatic frequency calibration process is exited. After the calibration process is completed, the automatic frequency calibration module is turned off to save power consumption, and the control voltage of the voltage-controlled oscillator is connected back to the phase-locked loop to start the locking process of the phase-locked loop.

[0041] Furthermore, the phase frequency detector includes a trigger including a reset terminal and a combinational logic, and the phase frequency detector is used to output a pull-up signal when the rising edge of the reference clock arrives first;

[0042] When the rising edge of the feedback comes first, the pull-down signal is output;

[0043] When the rising edge of the reference clock and the feedback clock both arrive, reset occurs and the pull-up and pull-down signals are turned off.

[0044] Furthermore, the charge pump includes a pull-up current and a pull-down current array at the enable end, and each charge pump array includes a PMOS transistor responsible for providing a pull-up current and an NMOS transistor responsible for pulling down the current. In order to adjust the current size of the charge pump over a larger range, it is necessary to set the transistor size in each charge pump array through simulation, so that the ratio of the current sizes that can be provided by adjacent arrays roughly satisfies the relationship of 2 times. For example, if the charge pump module includes 5 charge pumps, the ratio of the current sizes they provide should be approximately 1:2:4:8:16. By adjusting the enable of the charge pump array, the current size provided by the charge pump can be controlled, thereby indirectly adjusting the power consumption and bandwidth parameters of this phase-locked loop.

[0045] Furthermore, the switch filter is connected to the current output point of the charge pump on the left side and the control voltage point of the voltage-controlled oscillator on the right side; and the switch in the switch filter is a second-order filter composed of capacitors and resistors on one side, and a capacitor on the other side; the switch is a deep N-well NMOS transistor. The timing logic circuit that controls the switch is connected to the gate of the NMOS switch, and its logic is: after the pull-up and pull-down control signals output by the frequency detector and phase detector are turned off, a high level is output through the NOR gate, and a D flip-flop with reset is input, followed by some combinational logic and a high-potential bootstrap inverter, so as to increase the output high level to about 2 times the power supply voltage. At the same time, the output of the D flip-flop is also input into an adjustable delay module, and the output of this delay module is connected to the reset end of the D flip-flop. After the delay of the delay module, the D flip-flop is reset, thereby outputting a low level. Therefore, the conduction time of the switch is determined by the delay of this adjustable delay module. Through simulation, it can be known that, under the same conditions, the switch on time is longer, and the locking curve of the phase-locked loop is close to the locking curve of the second-order filter without the switch. The switch on time is changed, which can bring smaller reference spurs to the output clock. In the present invention, a multi-bit capacitor array is designed to adjust the length of the switch on time.

[0046] In the present invention, each charging and discharging process is as follows: the current of the charge pump first charges and discharges the left side of the switch filter, and after the charge pump is charged and discharged, the switch is turned on to make the left side of the filter charge and discharge the capacitor on the right side. The specific capacitance and resistance values ​​need to be determined according to the requirements of the bandwidth and phase margin of the phase-locked loop. When the charge pump current is adjustable, the bandwidth of this filter is mainly adjusted by the size of the charge pump current. Therefore, the selection of the resistance and capacitance values ​​of this filter is mainly to adjust the phase margin of this phase-locked loop. When the capacitance on the right side of the switch filter is smaller than that on the left side, the switch filter can be approximately regarded as a second-order filter consisting only of the left side, so that the transfer function can be calculated more conveniently to quickly determine the specific parameters of the resistance and capacitance.

[0047] The number of devices and processing scales described here are used to simplify the description of the present invention, and the application, modification and variation of the present invention will be obvious to those skilled in the art.

[0048] Although the embodiments of the present invention have been disclosed as above, they are not limited to the applications listed in the specification and implementation modes. They can be fully applied to various fields suitable for the present invention. For those familiar with the art, additional modifications can be easily implemented. Therefore, without departing from the general concept defined by the claims and the scope of equivalents, the present invention is not limited to the specific details and the illustrations shown and described herein.

Claims

1. A low-power phase-locked loop circuit with automatic frequency calibration, characterized in that: include: A voltage controlled oscillator, an automatic frequency calibration module connected to the voltage controlled oscillator signal and a programmable frequency divider, a frequency detector connected to the programmable frequency divider signal, a plurality of charge pump arrays connected to the frequency detector signal and a switch filter connected to the charge pump signal, wherein the switch filter is connected to the voltage controlled oscillator signal; Wherein, the voltage-controlled oscillator comprises a plurality of delay units, and the voltage-controlled oscillator is a ring oscillator composed of a plurality of the delay units cascaded in a ring; The delay unit is based on a cross-coupled structure of an inverter, and the delay unit includes a plurality of transistors, wherein the plurality of transistors include a plurality of PMOS transistors and a plurality of NMOS transistors; The gates of at least two PMOS transistors and two NMOS transistors are connected to the differential input of the delay unit, and the gates of at least two PMOS transistors and two NMOS transistors are connected to the differential output of the delay unit; The sources of all PMOS transistors are connected to the power supply, and the drains are connected to the differential output of the delay unit; The sources of all the NMOS transistors are grounded, and the drains are connected to the differential outputs of the delay unit.

2. A low power consumption phase locked loop circuit with automatic frequency calibration as claimed in claim 1, characterized in that: The programmable frequency divider includes a pre-frequency divider, an arbitrary frequency divider and a multiplexer, wherein the arbitrary frequency divider is composed of a 5-bit counter based on a trigger.

3. A low power consumption phase locked loop circuit with automatic frequency calibration as claimed in claim 1, characterized in that: The phase frequency detector comprises a trigger including a reset terminal and a combinational logic, and the phase frequency detector is used to output a pull-up signal when the rising edge of the reference clock arrives first; When the rising edge of the feedback comes first, the pull-down signal is output; When the rising edge of the reference clock and the feedback clock both arrive, reset occurs and the pull-up and pull-down signals are turned off.

4. A low power consumption phase locked loop circuit with automatic frequency calibration as claimed in claim 1, characterized in that: The charge pump includes a pull-up current and a pull-down current array at an enable end, and each charge pump array includes a PMOS transistor responsible for providing a pull-up current and an NMOS transistor responsible for a pull-down current.

5. A low power consumption phase locked loop circuit with automatic frequency calibration as claimed in claim 1, characterized in that: The switch filter has a current output point connected to the charge pump on the left side and a control voltage point of the voltage-controlled oscillator on the right side; and the switch in the switch filter has a second-order filter composed of a capacitor and a resistor on one side and a capacitor on the other side; The switch is a deep N-well NMOS transistor.

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