Oscillator frequency modulation circuit and communication chip

Abstract

The invention provides an oscillator frequency modulation circuit and a communication chip. The oscillator frequency modulation circuit comprises a first resonance area which comprises a first resonance circuit, a first coupling tube (Mn) and a second coupling tube (Mp), wherein the first coupling tube (Mn) and the second coupling tube (Mp) are cross-coupled with the first resonance circuit; the second resonance area comprises a second resonance circuit, and the second resonance circuit comprises a first branch circuit electrically connected with the first coupling tube (Mn) and a second branch circuit electrically connected with the second coupling tube (Mn); the second branch is electrically connected with the second coupling tube (Mp); the first tail inductor (Ln) is connected to the first branch in series; the second tail inductor (Lp) is connected in series with the second branch; and the differential capacitor array (Ct) is connected between the first branch circuit and the second branch circuit in parallel. According to the oscillator frequency modulation circuit and the communication chip, low noise can be realized in a broadband range, the anti-interference capability is realized, meanwhile, the occupied area is relatively small, and high-quality signals can be continuously output for a multi-protocol system.

Description

Technical Field

[0001] The present disclosure relates to the field of communication chips, and more specifically, to an oscillator frequency modulation circuit and a communication chip. Background Art

[0002] With the continuous development of communication protocols, people's demand for high-quality, broadband transmission is growing, and a single communication chip is required to support the parallel operation of multiple communication protocols. Examples of multiple communication protocols include but are not limited to Wi-Fi, Bluetooth, Thread, ZigBee, etc. As an important module for signal transmission, the voltage-controlled oscillator with tail inductor resonance can provide high-quality signal output at a single frequency, but performs poorly under wide bandwidth. In addition, the common tail inductor design will occupy a large chip area, and its resonant frequency is easily interfered by the coexistence of multiple protocols, making it difficult to continuously output high-quality signals to the system. Summary of the invention

[0003] The object of the present disclosure is to provide an improved oscillator frequency modulation circuit, which can at least solve one or more of the above problems.

[0004] In one aspect of the present disclosure, an oscillator frequency modulation circuit is provided, comprising a first resonance region, comprising a first resonance circuit and a first coupling tube and a second coupling tube cross-coupled with the first resonance circuit; and a second resonance region, comprising a second resonance circuit, wherein the second resonance circuit comprises: a first branch electrically connected to the first coupling tube; a second branch electrically connected to the second coupling tube; a first tail inductor connected in series to the first branch; a second tail inductor connected in series to the second branch; and a differential capacitor array connected in parallel between the first branch and the second branch.

[0005] In some examples, the differential capacitor array may be arranged close to a common source node of the first coupling tube and the second coupling tube.

[0006] In some examples, the second resonant circuit further includes a decoupling capacitor connected in parallel between the first branch and the second branch.

[0007] In some examples, the first tail inductor may be arranged between the differential capacitor array and the decoupling capacitor on the first branch, and the second tail inductor may be arranged between the differential capacitor array and the decoupling capacitor on the second branch.

[0008] In some examples, the differential capacitor array may include a plurality of branches connected in parallel between the first branch and the second branch, wherein each branch includes at least one switch and at least one capacitor.

[0009] In some examples, each of the at least one switch may be selected from an N-type switch or a P-type switch, wherein at least one capacitor may be arranged on one side or both sides of the at least one switch.

[0010] In some examples, each of the multiple branches may include at least one of a single NMOS tube and a single-sided MOM capacitor, a single PMOS tube and a single-sided MOM capacitor, a single NMOS tube and a double-sided MOM capacitor, and a single PMOS tube and a double-sided MOM capacitor.

[0011] In some examples, the capacitance value of the differential capacitor array may be determined by a state of the at least one switch.

[0012] In some examples, the state of the at least one switch may be determined by a control word of the differential capacitor array.

[0013] In some examples, the control word of the differential capacitor array may be determined based on a calibrated control word of the first resonant region.

[0014] In some examples, the coupling coefficient between the first tail inductor and the second tail inductor can be configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array.

[0015] In some examples, the first branch may be connected to a power source, and the second branch may be connected to a ground.

[0016] In some examples, the first resonant circuit may have a PMOS structure, an NMOS structure, or a CMOS structure.

[0017] In some examples, the decoupling capacitor may be a high-Q capacitor.

[0018] In some examples, the first resonant circuit includes a main inductor, a variable capacitor, and a fixed capacitor connected in parallel. In another aspect of the present disclosure, a communication chip is provided, including a processor, a memory, a communication interface, and an oscillator frequency modulation circuit according to the present disclosure.

[0019] In some examples, the power supply of the oscillator frequency modulation circuit can be an on-chip LDO or an off-chip LDO.

[0020] As an example and not a limitation, the advantages provided by the oscillator frequency modulation circuit and communication chip provided by the present disclosure may include: achieving low noise within a wide frequency band, having anti-interference capabilities, occupying a small area, and being able to continuously output high-quality signals for multi-protocol systems.

[0021] Specifically, the oscillator frequency modulation circuit and inductor architecture provided by the present disclosure can provide one or more of the following and other advantages:

[0022] (1) By setting a frequency modulation circuit at the end of the voltage-controlled oscillator and selecting different differential capacitors in different frequency bands, the double or quadruple frequency of the main resonant frequency can be generated. This design can not only avoid interference, but also the low parasitic characteristics of the differential capacitors broaden the frequency range of the oscillator's noise suppression, thereby improving the voltage-controlled oscillator's anti-interference ability and overall performance in a wide frequency band.

[0023] (2) By placing a centrally symmetrical differential capacitor array underneath the center of a digital-8-like inductor and optimizing the ratio of capacitor to inductor, for example, while keeping the tail resonant frequency unchanged, increasing the differential capacitor value and reducing the inductor value, the area of ​​the tail oscillator can be significantly reduced without affecting the performance.

[0024] (3) Use a new type of digital 8-type inductor and place the input and output terminals on opposite sides of the inductor. This design not only separates the decoupling capacitor and the differential capacitor in spatial layout, reducing wiring complexity and improving area utilization, but also the two-loop magnetic flux of the inductor flows in opposite directions, balancing the in and out of spatial interference, which can effectively improve the anti-interference ability. In addition, if the power tail and ground tail inductors are implemented in layers, the coupling coefficient can be increased and the common-mode noise can be reduced while further saving half the area.

[0025] (4) This disclosure introduces an oscillator frequency modulation circuit and an inductor architecture solution while maintaining the original main body design, without adding extra area and power consumption, thereby effectively saving manufacturing costs. At the same time, due to the versatility of the design, this solution can be widely used in various voltage-controlled oscillators, helping to achieve the goals of broadband high performance, anti-interference, and low area.

[0026] It should be understood that the above-listed technical problems and advantages are only examples and are not limitations of the present disclosure. In addition, the present disclosure is not limited to the technical solutions that solve all the above-mentioned technical problems at the same time. The technical solutions of the present disclosure can be implemented to solve one or more of the above-mentioned or other technical problems, and to provide one or more of the above-mentioned or other advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] Figure 1 A schematic circuit diagram showing an oscillator frequency modulation circuit according to an embodiment of the present disclosure;

[0028] Figure 2 A schematic diagram showing an inductor according to an embodiment of the present disclosure;

[0029] Figure 3 A schematic diagram showing an inductor according to another embodiment of the present disclosure;

[0030] Figure 4 A schematic diagram showing the spatial layout of an inductor architecture according to some embodiments of the present disclosure is shown;

[0031] Figure 5 A schematic diagram showing an inductor architecture according to some other embodiments of the present disclosure;

[0032] Figure 6 A schematic diagram showing the layout of the inductor and capacitor of an oscillator according to some embodiments of the present disclosure;

[0033] Figure 7 A schematic diagram showing the layout of the inductor and capacitor of an oscillator according to some other embodiments of the present disclosure;

[0034] Figure 8 A schematic diagram showing the layout of the inductor and capacitor of the oscillator according to some other embodiments of the present disclosure;

[0035] Fig. 9 A schematic diagram showing the layout of the inductor and capacitor of the oscillator in some further embodiments of the present disclosure is shown;

[0036] Fig.10 A schematic diagram showing an inductor architecture according to the prior art and an inductor architecture according to some embodiments of the present disclosure; and

[0037] Fig.11 A schematic diagram showing the layout of the inductor and capacitor of an oscillator according to some other embodiments of the present disclosure is shown. DETAILED DESCRIPTION

[0038] The following will be combined with the drawings and specific implementation methods to describe the scheme of the present disclosure in detail. It should be understood that the embodiments shown in the drawings and described below are only illustrative and not intended to limit the present disclosure.

[0039] In the context of the present disclosure, unless otherwise specifically stated, ordinal numbers such as “first”, “second”, etc. are only used to distinguish different elements but not to limit their order.

[0040] The inventors of the present disclosure fully recognize the deficiencies in the prior art and have proposed creative improvements and optimizations to oscillator frequency modulation circuits, inductors, inductor architectures, and inductor and capacitor layouts of oscillator frequency modulation circuits. The improvements in various aspects will be described in detail below in conjunction with the exemplary embodiments of the present disclosure.

[0041] Oscillator frequency modulation circuit

[0042] Figure 1 FIG. 1 is a schematic circuit diagram of an oscillator frequency modulation circuit 100 according to an embodiment of the present disclosure. Figure 1As shown, the oscillator frequency modulation circuit 100 includes a first resonance region 102 and a second resonance region 104. The first resonance region includes a first resonance circuit 106 and a first coupling tube 110 and a second coupling tube 112 cross-coupled with the first resonance circuit 106. In one embodiment, the first coupling tube 110 can be implemented as an N-type coupling tube (which can be expressed as a coupling tube Mn), and the second coupling tube can be implemented as a P-type coupling tube (which can be expressed as a coupling tube Mp). Those skilled in the art should understand that the implementation of the present disclosure is not limited to this, and different types of coupling tubes can be used without departing from the scope of the present disclosure.

[0043] In the first resonant region 102, the first resonant circuit 110 may include a main inductor 110 (which may be represented as a main inductor Lm), a variable capacitor 112 (which may be represented as a variable capacitor Cv), and a fixed capacitor 114 (which may be represented as a fixed capacitor Cm) connected in parallel. Those skilled in the art should understand that the first resonant circuit may adopt different circuit structures without departing from the scope of the present disclosure.

[0044] The second resonant region 104 includes a second resonant circuit 108. The second resonant circuit 108 may include a first branch 116 electrically connected to the first coupling tube 110 and a second branch 118 electrically connected to the second coupling tube 112. A first tail inductor 120 (which may be represented as a tail inductor Ln) is connected in series to the first branch 116, and a second tail inductor (which may be represented as a tail inductor Lp) is connected in series to the second branch 118.

[0045] The second resonant circuit 108 further includes a differential capacitor array 124 (represented as a capacitor array Ct) connected in parallel between the first branch 116 and the second branch 118. Optionally, the second resonant circuit 108 may further include a decoupling capacitor 126 (represented as a decoupling capacitor Cd) connected in parallel between the first branch 116 and the second branch 118.

[0046] In some embodiments of the present disclosure, the first resonant region constitutes the main resonant cavity of the voltage-controlled oscillator, which is responsible for continuously adjusting the clock frequency and providing it to the system. The second resonant region is used to suppress the common-mode noise of the first resonant region, and the high impedance generated by the resonance is used to prevent the common-mode noise from flowing back. Usually, the second resonant frequency is selected to be twice or four times the first resonant frequency.

[0047] In some embodiments, the second resonant region of the present invention provides a unique circuit structure, for example, connecting the power tail inductance path and the ground tail inductance path through a group of capacitor arrays, close to the common source node of the coupling tubes Mn and Mp. Generally, the first resonant region will be frequency calibrated through software or hardware algorithms to compensate for the deviation of the capacitance in the chip during mass production, and the calibrated control word maps the deviation value of the chip capacitance. The second resonant region is linked to the capacitor array control word of the first resonant region, and the resonant frequency of the tail inductors Lp and Ln can be changed by adjusting the control word of the tail inductor differential capacitor array Ct, thereby widening the resonant frequency range and effectively suppressing the common mode noise of the entire frequency band.

[0048] In some embodiments, Figure 1 As shown, the differential capacitor array 124 may be arranged near a common source node of the first coupling tube 110 and the second coupling tube 112 .

[0049] In some embodiments, the first tail inductor 120 is arranged between the differential capacitor array 124 and the decoupling capacitor 126 on the first branch 116 , and the second tail inductor 122 is arranged between the differential capacitor array 124 and the decoupling capacitor 126 on the second branch 118 .

[0050] In some embodiments, the differential capacitor array 116 includes a plurality of branches 128a, 128b, etc. connected in parallel between the first branch 116 and the second branch 118, wherein each branch includes at least one switch and at least one capacitor. Figure 1 As shown, branch 128a includes a switch 132 and two capacitors 130. Those skilled in the art should understand that the implementation of the disclosed solution is not limited thereto.

[0051] It should be understood that the differential capacitor array can be composed of N-type switches, P-type switches, or a combination of single-sided and double-sided capacitors according to the circuit structure and application requirements.

[0052] In some embodiments, each of the at least one switch is selected from an N-type switch or a P-type switch, wherein the at least one capacitor 130 may be disposed on one side or both sides of the at least one switch.

[0053] In some embodiments, each of the multiple branches may include at least one of a single NMOS tube and a single-sided MOM capacitor, a single PMOS tube and a single-sided MOM capacitor, a single NMOS tube and a double-sided MOM capacitor, and a single PMOS tube and a double-sided MOM capacitor.

[0054] In some embodiments, the capacitance value of the differential capacitor array 124 is determined by the state of at least one switch.

[0055] In some embodiments, the state of at least one switch is determined by a control word of the differential capacitor array 124 .

[0056] In some embodiments, the control word of the differential capacitor array 124 is further determined based on the calibrated control word of the first resonant region 106 .

[0057] In some embodiments, the coupling coefficient between the first tail inductor 120 and the second tail inductor 122 is configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array 124 .

[0058] In some embodiments, the coupling coefficient between the tail inductors Lp and Ln can be determined according to the system environment and design goals to eliminate the common mode noise between the power supply side and the ground side through magnetic coupling. In addition, the power supply can be powered by an on-chip LDO or an off-chip LDO, and the decoupling capacitor can use a high-Q capacitor to ensure the current loop between the power supply and the ground, while eliminating the influence of additional parasitic inductance to ensure the accuracy of the resonant frequency of the second resonant region.

[0059] In some embodiments, the first branch 116 is connected to a power source, and the second branch 118 is connected to ground.

[0060] It should be understood that the first resonant circuit may have a PMOS structure, an NMOS structure, a CMOS structure, or other equivalent structures without departing from the scope of the present disclosure.

[0061] In some embodiments, the oscillator frequency modulation circuit uses a differential capacitor array, which is placed between the power tail inductor path and the ground tail inductor path, close to the common source node of the voltage-controlled oscillator differential coupling tube. Among them, the two groups of tail inductors can be configured to have a certain coupling coefficient. By adjusting the capacitance value of the differential capacitor array, the second resonant frequency can be adjusted to about 2 times or 4 times the main resonant frequency to hinder the backflow of common-mode noise or avoid the interference of co-frequency spurious. Compared with the solution of two groups of single-ended capacitor arrays, the use of a differential capacitor array can be simplified to using only one set of switches and only half the capacitor area. Due to the reduction of the parasitic capacitance and parasitic resistance of the array, not only the adjustment range of the second resonant frequency is expanded, but also the Q value of the second resonant cavity is improved. In addition, the design is easy to implement in the layout, which significantly improves the area utilization.

[0062] In different application scenarios, the oscillator frequency modulation circuit can use a PMOS structure, an NMOS structure or a CMOS structure as the core architecture of the voltage-controlled oscillator.

[0063] Depending on the performance requirements and layout, the coupling coefficient of the two sets of tail inductors can be adjusted from close to 0 to close to 1 to achieve the best balance between noise, area and anti-interference performance.

[0064] The present disclosure also provides a communication chip, including a processor, a memory, a communication interface, and an oscillator frequency modulation circuit according to the present disclosure.

[0065] In some embodiments, the power supply of the oscillator frequency modulation circuit can be an on-chip LDO or an off-chip LDO.

[0066] Inductors

[0067] The present disclosure also provides an improved inductor.

[0068] Figure 2 FIG. 2 is a schematic diagram of an inductor 200 according to an embodiment of the present disclosure.

[0069] like Figure 2 As shown, the inductor 200 includes an input terminal 202, an output terminal 206, and an even number of coils formed of electrical conductors connected between the input terminal 202 and the output terminal 204. For example, coils 206 and 208. Figure 2 As shown, the input terminal 202 and the output terminal 204 are arranged on opposite sides of the inductor 200 rather than on the same side.

[0070] In addition, in the inductor 200, half of the coils in the even number of coils are arranged symmetrically with respect to the other half of the coils and have opposite rotation directions. In this way, the two coils present a state where the magnetic flux flows in opposite directions, which can effectively offset the same-frequency interference.

[0071] Figure 3 FIG. 1 is a schematic diagram of an inductor 300 according to another embodiment of the present disclosure. Figure 2 Unlike the illustrated embodiment, the inductor 300 includes four coils 306a, 306b, 308a, 308b formed of electrical conductors connected between the input terminal 302 and the output terminal 304. In some embodiments, half of the coils in the even number of coils are annularly nested, and the other half of the coils in the even number of coils are annularly nested.

[0072] In other embodiments, half of the even-numbered coils are concentric, and the other half of the even-numbered coils are concentric.

[0073] In some embodiments, the inductor is composed of at least one turn, and can be extended to two turns or more as required.

[0074] like Figure 2 and Figure 3 As shown, the inductor according to the embodiment of the present disclosure may be referred to herein as a “quasi-figure-8 inductor” due to its shape characteristics.

[0075] In some embodiments, inductor 200 or 300 is an on-chip inductor.

[0076] In some embodiments, half of the coils and the other half of the coils of the even number of coils are disposed on the same metal layer.

[0077] In some embodiments, half of the coils and the other half of the coils in the even number of coils are connected by skipping layers at the parts where there are crossover lines between them, and the rest of the parts are arranged on the same metal layer.

[0078] In some embodiments, half of the coils and parts of the other half of the coils of the even number of coils are disposed on the first metal layer, and the remaining parts are disposed on the second metal layer.

[0079] It should be understood that on-chip inductors are very sensitive to noise, area, and anti-interference performance, so the improvements proposed in the present disclosure can bring significant performance improvements to on-chip inductors.

[0080] In some embodiments, the even number of coils includes two coils.

[0081] In some embodiments, the even number of coils includes four coils.

[0082] In some embodiments, the inductor 200 or 300 is configured to have an integral structure.

[0083] Inductor Architecture

[0084] The present disclosure also provides an improved inductor architecture, including a first inductor and a second inductor, and a differential capacitor array connected in parallel between the first inductor and the second inductor, wherein the first inductor and the second inductor are at least partially stacked on the differential capacitor array.

[0085] In some embodiments, the first inductor and the second inductor are arranged to overlap.

[0086] In a further embodiment, the first inductor and the second inductor are stacked together on the differential capacitor array.

[0087] In some embodiments, the first inductor and the second inductor are separately arranged, and the differential capacitor array is split into a first differential capacitor array and a second differential capacitor array, wherein the first inductor is configured to at least partially stack on the first differential capacitor array, and the second inductor is configured to at least partially stack on the second differential capacitor array.

[0088] In some embodiments, the inductor architecture is an on-chip inductor architecture.

[0089] In some embodiments, the first inductor and the second inductor are disposed on different metal layers.

[0090] In some embodiments, portions of the first inductor and the second inductor are disposed on the first metal layer, and the remaining portions are disposed on the second metal layer.

[0091] In some embodiments, the first inductor and the second inductor are configured to have shapes that are mirror images of each other.

[0092] In some embodiments, the first inductor and the second inductor are tail inductors of an oscillator frequency modulation circuit.

[0093] In some embodiments, each of the first inductor and the second inductor is an inductor according to the present disclosure.

[0094] Figure 4 FIG. 4 is a schematic diagram showing the spatial layout of inductor architectures 402 and 404 according to some embodiments of the present disclosure.

[0095] Figure 4 (a) shows a structure including a single-turn inductor and a capacitor array arrangement below the inductor. Figure 4 (b) shows the structure of the capacitor array arrangement under the inductor. This architecture uses at least two layers of metal, where the upper layer of metal adopts a symmetrical figure-8 design as the inductor body of the second resonant region, and the input and output are located on opposite sides of the inductor. Unlike the traditional figure-8-shaped inductor architecture, the simple traditional symmetrical winding method will place the input and output on the same side, requiring more signal flow wiring connections in the same area, ultimately increasing signal crosstalk and layout complexity. Figure 4 (a) and Figure 4 As shown in (b), the relatively low-level metal is suspended below the center of the inductor and led out from the input and output sides respectively. Due to the use of a figure-8-like design, the magnetic flux of the two turns of the inductor flows in opposite directions, which can effectively reduce co-frequency interference. This spatial layout solution can effectively reduce the area and bring obvious cost advantages to the chip. The double-turn inductor is similar to the single-turn inductor, but the middle cross line needs to use a higher-level metal for layer jump connection.

[0096] Figure 4 (c) shows a capacitor array. In the illustrated embodiment, the capacitor array is arranged in a central symmetric manner. Taking a 4-bit binary code as an example, the capacitors CAP1X, CAP2X, CAP4X, and CAP8X in the capacitor array correspond to 1, 2, 4, and 8 unit codes, respectively, and CAP1XD is a dummy cell of CAP1X for overall matching. Figure 4 As shown in (c), the switch sw is located close to the capacitor unit and can be adjusted according to the actual layout. Figure 4 The layout shown is by way of example only and is not limiting.

[0097] Figure 5 Schematic diagrams of inductor architectures 506 and 512 according to other embodiments of the present disclosure are shown.

[0098] Figure 5This is another schematic diagram of an inductor architecture provided by an embodiment of the present disclosure. By arranging in a vertical plane in space, dual inductors can be realized in the same area. It is characterized by a higher coupling coefficient and a smaller area. The common-mode current flow direction is indicated in the figure, and the magnetic flux flow direction of the laminated metal is the same and in a superimposed state. The dual inductor can be realized by two completely independent layers of metal, or each group of inductors occupies half of the two layers of metal, combined with a plane and space combination. Figure 5 The capacitor array layout shown can be used with Figure 4 Similarly, it can be hidden under the inductor to facilitate the differential layout of the capacitor. The overall digital 8-type inductor has a strong suppression effect on close-in interference.

[0099] Oscillator Inductor and Capacitor Layout

[0100] Figure 1 In the oscillator frequency modulation circuit 100 according to one embodiment of the present disclosure, the first tail inductor 112 and each of the tail inductors are implemented as an inductor according to the present disclosure.

[0101] In some embodiments, the first tail inductor and the second tail inductor are configured to have shapes that are mirror images of each other. As a non-limiting example, Figure 6 The tail inductors 608 and 610 are shown as mirror images of each other. It should be understood that "mirror images of each other" refers to a state where the overall shapes of the coils are roughly mirror images of each other, and does not require that all parts of the two coils are in a mirror image relationship.

[0102] In some embodiments, the first tail inductor and the second tail inductor are stacked above the differential capacitor array. Figure 6 The tail inductors 608 and 610 shown in (a) are stacked above the differential capacitor arrays 612 and 614.

[0103] In some embodiments, the first tail inductor and the second tail inductor are arranged substantially axisymmetrically with respect to the central axis of the main inductor, for example, see Figure 6-Figure 8 shown.

[0104] In some embodiments, the first tail inductor and the second tail inductor are arranged at the input end and the output end of the inductor coil of the main inductor. Figure 6 As shown in (a), the tail inductors 608 and 610 are shown.

[0105] In some embodiments, the first tail inductor and the second tail inductor are arranged obliquely relative to the central axis of the inductor coil of the main inductor. Figure 8 As shown in (a), the tail inductors 808 and 810.

[0106] In some embodiments, the first tail inductor and the second tail inductor are arranged at an angle of 45 degrees relative to the central axis of the inductor coil of the main inductor. Figure 8 (b) is shown as tail inductors 818 and 820.

[0107] In some embodiments, the first tail inductor and the second tail inductor are arranged to overlap each other. Fig. 9 As shown in (a), the tail inductors 908 and 910.

[0108] According to the inductor architecture disclosed in the present invention, a quasi-digital 8 type inductor is mainly used. Different from conventional inductors, the inductor disclosed in the present invention is characterized by input from one side and output from the other side after winding. In addition, a capacitor array network is provided below the central winding of the inductor. According to the direction of current flow, the two coils of the quasi-digital 8 type inductor present a state in which the magnetic flux flows in opposite directions, which can effectively offset the same-frequency interference, suppress its absorption of strays in similar frequency bands, and have no effect on the main inductance. At the same time, the input and output ends are separated in layout, so that the decoupling capacitors and the frequency modulation capacitors are distributed on both sides of the inductor to avoid occupying the same area, and both sides can use high-level metal low-resistance connections to reduce wiring complexity and significantly improve area utilization.

[0109] In some embodiments, the capacitor array is realized by adding low-level parallel metal wires on the input side of the inductor, adding low-level vertical metal wires on the output side, and folding them inward to the parallel side after extension. The basic units of the overall capacitor array are arranged in binary coding and laid out in a centrally symmetrical manner to ensure the balance of the inductance. Since the central area of ​​the digital 8-type inductor is not the main magnetic flux concentration area, and the magnetic flux flows in opposite directions on both sides, the centrally symmetrical capacitor array is hidden here and the effect on the inductor performance is negligible. When this inductor architecture is combined with the oscillator frequency modulation circuit, it not only achieves high-performance broadband frequency modulation, but also improves the anti-interference ability while reducing the area.

[0110] In addition, in some embodiments, at least one set of tail inductors is included. When two sets of tail inductors are used, the same level of metal can be used in different areas, or laminated metal can be used in the same area. When laminated metal is used, the lamination method can be optimized according to the size of the required inductance coupling coefficient. Optionally, the capacitor array of the present solution can be connected to the input and output of a single-sided inductor respectively, or connected to each other through the output ends of the two sets of inductors. The layout of the capacitor array can be flexibly selected according to the top-level design. It can be hidden directly below the inductor or arranged near the inductor to meet different application requirements.

[0111] The following is an example of an oscillator inductor and capacitor layout according to an embodiment of the present disclosure.

[0112] Figure 6 Schematic diagrams showing oscillator inductor and capacitor layouts 602 and 604 according to some embodiments of the present disclosure.

[0113] Figure 6 (a) and Figure 6 (b) is a schematic diagram of the layout of a complete oscillator inductor and capacitor provided in an embodiment of the present disclosure. The two groups of tail inductors use a single-turn metal wire and are located on both sides of the inductors 606 and 616 of the first resonance area. The magnetic flux flow direction of the tail inductor is indicated in the figure. The symmetrical layout balances the magnetic flux distribution and does not affect the inductors 606 and 616 of the first resonance area. The tail inductor can be arranged horizontally or vertically as required. In this embodiment, the coupling capacitor (located in the area between VDD and VSS, not shown in the figure) and the capacitor array of the second resonance area are separated in space, which can effectively reduce winding and reduce area. The differential inductor arrays of the second resonance area are respectively arranged on both sides of the inductors of the first resonance area. This symmetrical design can increase space utilization and reduce the overall area of ​​the circuit.

[0114] Figure 7 Schematic diagrams showing oscillator inductor and capacitor layouts 702 and 704 according to some other embodiments of the present disclosure.

[0115] Figure 7 is another complete oscillator inductor and capacitor layout provided by the embodiment of the present disclosure, relative to Figure 4 , the two groups of tail inductors use double-loop metal wires. For the same resonant frequency, the double-loop inductor produces a larger inductance value, which can achieve the required inductance in a smaller area, further reducing the layout area.

[0116] Figure 8 Schematic diagrams showing oscillator inductor and capacitor layouts 802 and 804 according to some other embodiments of the present disclosure.

[0117] Figure 8 This is another complete oscillator inductor and capacitor layout provided by the embodiment of the present disclosure. Figure 5 , the two groups of tail inductors are tilted at a 45-degree angle to the main inductor. Since the magnetic flux polarity bisector of the quasi-digital-8 inductor is substantially perpendicular to the hypotenuse current line of the octagonal inductor in the first resonant region, the tail inductor has little effect on the inductance of the first resonant region. This layout can place the tail inductor close to the main inductor, further improving the area utilization. Optionally, as Figure 8 As shown, the differential capacitor array can be arranged at the output end of the two groups of tail inductors, close to the extension line of the inductor of the first resonance region. In addition, the tail inductor can also be implemented by a single-turn inductor.

[0118] Fig. 9 Schematic diagrams of oscillator inductor and capacitor layouts 902 and 904 are shown in some further embodiments of the present disclosure.

[0119] Fig. 9This is another complete oscillator inductor and capacitor layout provided by an embodiment of the present disclosure, in which two groups of tail inductors are placed directly below the first resonant inductor. The magnetic flux flow direction of the tail inductor is symmetrically distributed, and has almost no effect on the first resonant inductor. In terms of layout, the digital-8-type inductor still has a strong inhibitory effect on close-band interference. The differential capacitor array can be placed below the center of the digital-8-type inductor, and by mapping with the capacitor control word of the first resonant area, the differential capacitor array control word is adjusted to adjust the resonant frequency of the second resonant area to cover the target frequency points of the entire frequency band. Fig. 9 (c) and Fig. 9 (d) is an exploded view further showing two sets of tail inductors stacked on a common differential capacitor array.

[0120] It should be understood that if the solution of overlapping the two tail inductors Ln and Lp is adopted (such as Fig. 9 As shown), then only one set of differential capacitor arrays can be set up and placed under the two overlapping inductors. If the two tail inductors Ln and Lp do not overlap and are placed separately in mirror image, then one set of differential capacitor arrays can be split into two sets of half-sized differential capacitor arrays, each placed under the corresponding inductor, and Lp and Ln are connected to the other inductor lead wires respectively (for example Figures 6 to 8 shown).

[0121] Fig.10 Schematic diagrams showing inductor architectures 1002 and 1004 according to the prior art and inductor architectures 1006 and 1008 according to some embodiments of the present disclosure. Fig.10 In the inductor architecture 1002 shown in (a), an 8-shaped inductor 1010 according to the prior art is connected to a capacitor 1012. Fig.10 In (b), the octagonal inductor 1014 according to the prior art is also connected to the capacitor 1016.

[0122] In contrast, Fig.10 (c) shows that the single-turn inductor 1018 according to the present disclosure is arranged above the differential capacitor array 1020, Fig.10 (d) shows that the double-loop inductor 1022 according to the present disclosure is arranged above the differential capacitor array 1024. In this way, compared with the solution of two sets of single-ended capacitor arrays, the use of the differential capacitor array can be simplified to use only one set of switches, and only half of the capacitor area is used, which greatly reduces the area of ​​the tail oscillator and is easier to implement in the layout.

[0123] Fig.11 Schematic diagrams showing the layouts 1102, 1104, 1106 and 1108 of the inductors and capacitors of the oscillator according to some other embodiments of the present disclosure. Fig.11 As shown, layouts 1102 and 1104 are Figure 6The layout shown is similar, but the differential capacitor array is not placed directly under the inductor. Similarly, layouts 1106 and 1108 are similar to Figure 7 The layout shown is similar, but again the differential capacitor array is not arranged directly below the inductor. In this way, the inductor can be only partially stacked above the differential capacitor array without departing from the scope of the present disclosure.

[0124] Although various embodiments of various aspects of the present disclosure have been described for the purpose of the present disclosure, it should not be understood that the teachings of the present disclosure are limited to these embodiments. The features disclosed in a specific embodiment are not limited to this embodiment, but can be combined with the features disclosed in different embodiments. For example, one or more features and / or functions of the product according to the present disclosure described in one embodiment may also be applied individually, in combination or as a whole in another embodiment. It should be understood by those skilled in the art that there are also possible more optional embodiments and variations, and various changes and modifications can be made to the above structure without departing from the scope of protection of the present disclosure.

Claims

1. An oscillator frequency modulation circuit, comprising: A first resonance region includes a first resonance circuit and a first coupling tube (Mn) and a second coupling tube (Mp) cross-coupled with the first resonance circuit; as well as The second resonance region includes a second resonance circuit, wherein the second resonance circuit includes: a first branch electrically connected to the first coupling tube (Mn); a second branch electrically connected to the second coupling tube (Mp); A first tail inductor (Ln) connected in series to the first branch; a second tail inductor (Lp) connected in series with the second branch; and A differential capacitor array (Ct) is connected in parallel between the first branch and the second branch.

2. The oscillator frequency modulation circuit according to claim 1, characterized in that: The differential capacitor array (Ct) is arranged close to a common source node of the first coupling transistor (Mn) and the second coupling transistor (Mp).

3. The oscillator frequency modulation circuit according to claim 1, characterized in that: The second resonant circuit further includes a decoupling capacitor (Cd) connected in parallel between the first branch and the second branch.

4. The oscillator frequency modulation circuit according to claim 3, characterized in that: The first tail inductor (Ln) is arranged between the differential capacitor array (Ct) and the decoupling capacitor (Cd) on the first branch, and the second tail inductor (Lp) is arranged between the differential capacitor array (Ct) and the decoupling capacitor (Cd) on the second branch.

5. The oscillator frequency modulation circuit according to claim 1, characterized in that: The differential capacitor array (Ct) includes a plurality of branches connected in parallel between the first branch and the second branch, wherein each branch includes at least one switch and at least one capacitor.

6. The oscillator frequency modulation circuit according to claim 4, characterized in that: Each of the at least one switch is selected from an N-type switch or a P-type switch, wherein at least one capacitor is arranged on one side or both sides of the at least one switch.

7. The oscillator frequency modulation circuit according to claim 5, characterized in that: Each of the plurality of branches includes at least one of a single NMOS tube and a single-sided MOM capacitor, a single PMOS tube and a single-sided MOM capacitor, a single NMOS tube and a double-sided MOM capacitor, and a single PMOS tube and a double-sided MOM capacitor.

8. The oscillator frequency modulation circuit according to claim 4, characterized in that: The capacitance value of the differential capacitor array (Ct) is determined by the state of the at least one switch.

9. The oscillator frequency modulation circuit according to claim 7, characterized in that: The state of the at least one switch is determined by a control word of the differential capacitor array (Ct).

10. The oscillator frequency modulation circuit according to claim 8, characterized in that: The control word of the differential capacitor array (Ct) is determined based on the calibrated control word of the first resonant region.

11. The oscillator frequency modulation circuit according to claim 1, characterized in that: The coupling coefficient between the first tail inductor (Ln) and the second tail inductor (Lp) is configured to be adjusted between 0 and 1 according to the capacitance value of the differential capacitor array (Ct).

12. The oscillator frequency modulation circuit according to claim 1, characterized in that: The first branch is connected to a power source, and the second branch is grounded.

13. The oscillator frequency modulation circuit according to claim 2, characterized in that: The first resonant circuit has a PMOS structure, an NMOS structure or a CMOS structure.

14. The oscillator frequency modulation circuit according to claim 3, characterized in that: The decoupling capacitor (Cd) is a high-Q capacitor.

15. The oscillator frequency modulation circuit according to claim 1, characterized in that: The first resonant circuit includes a main inductor (Lm), a variable capacitor (Cv), and a fixed capacitor (Cm) connected in parallel. 16 . A communication chip, comprising a processor, a memory, a communication interface, and an oscillator frequency modulation circuit according to any one of claims 1 to 15 .

17. The communication chip according to claim 15, characterized in that: The power supply of the oscillator frequency modulation circuit is an on-chip LDO or an off-chip LDO.

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