High-current wide-capacitance-range LDO (Low Dropout Regulator) based on frequency compensation circuit

Abstract

The invention discloses a high-current wide-capacitance-range LDO (Low Dropout Regulator) based on a frequency compensation circuit. The LDO comprises a first-stage operational amplifier, a second-stage operational amplifier and a third-stage operational amplifier The secondary operational amplifier is used for carrying out secondary amplification on the amplified error signal; the driving circuit is used for enhancing the driving capability of the error signal subjected to secondary amplification; the current output circuit is used for adjusting the output current of the output demand according to the secondary amplified error signal with the enhanced driving capability and the input voltage; the feedback circuit is used for generating new feedback voltage according to the output current; the first-stage operational amplifier is also used for amplifying a new error signal; and the frequency compensation circuit is used for adjusting the positions of a plurality of zero poles in the new error signal according to the output current by utilizing the multi-zero pole dynamic compensation branch and the current buffer compensation branch so as to offset a secondary pole and widen the whole unit gain bandwidth at the same time to obtain an adjusted error signal. According to the invention, a large bandwidth can still be obtained in a large current output range and a large load capacitance range.

Description

Technical Field

[0001] The present invention belongs to the technical field of low-dropout linear regulator chips, and in particular relates to a high-current and wide-capacitance range LDO (Low-Dropout Regulator) based on a frequency compensation circuit. Background Art

[0002] With the popularity of modern new energy vehicles, the performance requirements for on-board power management chips have risen. Since there are many electronic devices in new energy vehicles, far more than traditional vehicles, such as advanced driver assistance systems, battery management systems, infotainment systems, etc. These modules may require higher power supply, so in order to meet the requirements, the current range of the LDO output must be larger and the load capacity must be stronger. For specific modules (such as microcontrollers and sensors), low-power LDOs may also be required, but they need to meet a wider range of current output capabilities (for example, a few mA to hundreds of mA), which requires the LDO to have a large enough output range to meet the above requirements.

[0003] There are various types of loads in new energy vehicles, including sensors, MCUs (Microcontroller Units), communication modules, audio modules, and high-power modules. These loads have different requirements for power supply. Low current loads such as sensors or MCUs require smaller load capacitance to maintain response speed. High current loads such as infotainment systems and drive motor controllers require large capacitors at the output of the LDO to stabilize the output power supply and improve transient current performance. Therefore, the design of the LDO must also support a wide range of load capacitance to deal with the above problems.

[0004] In the design of vehicle-mounted LDO, the characteristics that are more concerned about in order to meet vehicle-mounted needs are large load current and a wide load capacitance range to provide diversified load requirements. Among these, the range of output current and the size of external capacitance will affect the system stability of the LDO. In order to be able to design an LDO with a large load capacity and allow a large range of external load capacitance, a corresponding compensation scheme is required to make the designed LDO loop stable under any conditions. Since the vehicle-mounted low-dropout linear regulator needs to meet large load currents and a wide range of external load capacitance, a good compensation method is required to keep the LDO system in a stable state. The current technical solutions include ESR (Equivalent Series Resistance) compensation and dynamic zero compensation.

[0005] In LDOs using the traditional two-stage op amp structure, most of them currently use external ESR capacitor compensation methods for compensation. Figure 1As shown, an ESR capacitor is connected to the output of the LDO to achieve the purpose of stabilizing the system. The principle of ESR compensation is that there are two main low-frequency poles in the two-stage LDO that affect the stability of the system, located at the output of the error amplifier EA and the output of the LDO (the output impedance of the follower BUFFER is small and the pole frequency is high and is not included). When two poles appear in the unity gain bandwidth, the phase margin of the LDO circuit system is at least less than 45°, that is, there is a possibility of instability. In order to make the phase margin greater than 45° in the unity gain bandwidth, it is necessary to satisfy that there is only one pole in the unity gain bandwidth or there is a left half plane zero point that offsets the second pole. The approach taken by ESR compensation is to generate a left half plane zero point between the first and second poles by adding an ESR capacitor at the output end, and use the phase increase of this zero point to reduce the impact of the phase reduction of the second pole on the LDO phase margin.

[0006] When designing a low-dropout linear regulator with a large load current, the output current variation range is large, which will cause the pole position at the LDO output to shift. When the output current is small, that is, when the LDO load is large, the load resistance RL is small. At this time, since RL is small, it can be seen from the pole formula that the pole position moves to a higher frequency. In order to obtain a larger unity gain bandwidth and stabilize the system, the dynamic zero compensation method can be used. Figure 2 As shown, a series capacitor and resistor are added between EA and BUFFER, where the total resistance of the compensation circuit is determined by R1 and the transistor MN1 in the linear region. The connection mode of MN1 is that the triode is in the linear region, and the resistance of MOS will increase or decrease with the increase or decrease of the output current. The change of the resistance value will change the zero point position, so that this zero point changes with the change of the main pole position.

[0007] However, ESR compensation and dynamic zero compensation have the following disadvantages respectively:

[0008] 1) Disadvantages of ESR compensation: This method uses the zero point introduced by ESR compensation to bring about a +45° phase and the -45° phase brought by the secondary pole to neutralize the secondary pole so that the secondary pole will not affect the stability of the LDO system. After compensation, the design requirement of a phase margin greater than 45° can be achieved. However, there are two obvious disadvantages when applied to LDOs with a large output current variation range: The first disadvantage is that when the current changes, the resistance R at the output end of the LDO is increased. OUTThe change further causes the bandwidth of the LDO to change. When the output current is small, the main pole shifts to the left, which reduces the unity gain bandwidth, which will reduce the dynamic response performance of the LDO under the condition of low load current, and also reduce the LDO power supply rejection ratio. The second disadvantage is that LDOs with larger output currents often use larger power tubes. The large size will make the parasitic capacitance of the power tube very large. The large parasitic capacitance will cause the third pole to be at a lower frequency position. The appearance of the third pole will further affect the stability of the LDO.

[0009] 2) Disadvantages of dynamic zero compensation: Traditional dynamic zero compensation performs well when the output current range is not very large. However, when the output current range is very large, the dynamic zero compensation may not be able to fully cover all working conditions, resulting in a non-optimal compensation effect. Summary of the invention

[0010] In order to solve the above problems existing in the prior art, the present invention provides a high current and wide capacitance range LDO based on a frequency compensation circuit. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0011] In a first aspect, an embodiment of the present invention provides a high current and wide capacitance range LDO based on a frequency compensation circuit, comprising:

[0012] A first-stage operational amplifier, used to amplify an error signal; the error signal is the difference between a reference voltage and a feedback voltage;

[0013] A secondary operational amplifier, connected to the primary operational amplifier, for performing secondary amplification on the amplified error signal;

[0014] A driving circuit, connected to the secondary operational amplifier, for enhancing the driving capability of the secondary amplified error signal;

[0015] A current output circuit, connected to the driving circuit, for adjusting the output current required by the output according to the secondary amplified error signal with enhanced driving capability and the input voltage, so as to output the required output voltage through the load circuit;

[0016] A feedback circuit, connected to the current output circuit, and used to generate a new feedback voltage according to the output current;

[0017] The first-stage operational amplifier is connected to the feedback circuit and is also used to amplify a new error signal; the new error signal is the difference between the reference voltage and the new feedback voltage;

[0018] A frequency compensation circuit, connected to the current output circuit and the first-stage operational amplifier, for adjusting the positions of multiple zero poles in the new error signal according to the output current by using a multi-zero-pole dynamic compensation branch and a current buffer supplement branch to offset the secondary poles while widening the entire unit gain bandwidth, thereby obtaining an adjusted error signal;

[0019] The secondary operational amplifier is connected to the frequency compensation circuit and is also used to perform secondary amplification on the adjusted error signal.

[0020] In one embodiment of the present invention, the first-stage operational amplifier includes transistors MN1 to MN6, transistors MP1 to MP4, and a current source I bias ;in,

[0021] The gate of transistor MN1 is used as the reference voltage V ref The input terminal, the source of transistor MN1 and the source of transistor MN2, the current source I bias The input end of the transistor MN1 is connected, the drain of the transistor MN1 is connected to the source of the transistor MP1 and the drain of the transistor MP3, the gate of the transistor MN2 is connected to the feedback circuit, the drain of the transistor MN2 is connected to the source of the transistor MP2 and the drain of the transistor MP4, the gate of the transistor MN3 and the gate of the transistor MN4 are both connected to the third bias voltage, the source of the transistor MN3 is connected to the drain of the transistor MN5, the drain of the transistor MN3 is connected to the drain of the transistor MP1, the gate of the transistor MN5, the gate of the transistor MN6, and the current buffer supplement branch, the source of the transistor MN4 is connected to the drain of the transistor MN6, the drain of the transistor MN4 is connected to the drain of the transistor MP2 and the multi-zero-pole dynamic compensation branch, the source of the transistor MN5, the source of the transistor MN6, and the current source I bias The output ends of the transistors MP1 and MP2 are grounded, the gates of the transistors MP1 and MP2 are connected to the second bias voltage, the gates of the transistors MP3 and MP4 are connected to the first bias voltage, and the sources of the transistors MP3 and MP4 are connected to the power supply VDD.

[0022] In one embodiment of the present invention, the secondary operational amplifier includes a high voltage power tube HVMN1, a resistor R P , transistor MN7; wherein,

[0023] The gate of the high-voltage power tube HVMN1 is connected to the power supply VDD, and the drain of the high-voltage power tube HVMN1 is connected to the resistor R P The source of the high-voltage power tube HVMN1 is connected to the drain of the transistor MN7, the gate of the transistor MN7 is connected to the first-stage operational amplifier, the source of the transistor MN7 is grounded, and the resistor R PThe other end is connected to the input voltage V IN .

[0024] In one embodiment of the present invention, the driving circuit includes a follower BUFFER; the input end of the follower BUFFER is connected to the secondary operational amplifier, and the output end of the follower BUFFER is connected to the current output circuit.

[0025] In one embodiment of the present invention, the current output circuit includes a high-voltage power tube HVMP1; the source of the high-voltage power tube HVMP1 is connected to the input voltage V IN The drain of the high-voltage power tube HVMP1 is connected to the feedback circuit, the load circuit, and the current buffer supplement branch, and the gate of the high-voltage power tube HVMP1 is connected to the multi-zero-pole dynamic compensation branch.

[0026] In one embodiment of the present invention, the feedback circuit includes a resistor R1 and a resistor R2; wherein,

[0027] One end of the resistor R1 is connected to the current output circuit, the other end of the resistor R1 is connected to one end of the resistor R2 and the first-stage operational amplifier, and the other end of the resistor R2 is grounded.

[0028] In one embodiment of the present invention, the multi-zero-pole dynamic compensation branch in the frequency compensation circuit includes N parallel zero-pole compensation sub-branches, where N is an integer greater than 1; each zero-pole compensation sub-branch is composed of a fixed capacitor and a variable resistor connected in series, the other end of the fixed capacitor is connected to the first-level operational amplifier, and the other end of the variable resistor is grounded; wherein the variable resistor of each zero-pole compensation sub-branch is generated by a variable resistor generating module according to the output current adjusted by the current output circuit; the ratio of the fixed capacitors in all zero-pole compensation sub-branches is 1:2:…:2 N-1 , the ratio of the resistance of the variable resistor is 2 N-1 :…:2:1.

[0029] In one embodiment of the present invention, the variable resistance generating module includes N variable resistance generating branches, a transistor MN8, a high voltage power tube HVMP2, a resistor R s ;in,

[0030] N variable resistance generating branches are connected in parallel, and each variable resistance generating branch includes a fixed resistor and a plurality of transistors connected in series with the fixed resistor, the other end of the fixed resistor is connected to the corresponding fixed capacitor, and the source of the last transistor is connected to the source of the transistor MN8; the ratio of the resistance values ​​of the fixed resistors in all variable resistance generating branches is 2 N-1 :…:2:1, the ratio of the number of transistors is 2 N-1 :…:2:1;

[0031] The gate of transistor MN8 is connected to the drain of transistor MN8, the drain of high-voltage power tube HVMP2, and the gates of all transistors in each variable resistance generating branch. The gate of high-voltage power tube HVMP2 is connected to the current output circuit. The source of high-voltage power tube HVMP2 is connected to resistor R s One end of the resistor R s The other end is connected to the input voltage V IN .

[0032] In one embodiment of the present invention, the current buffer supplementary branch in the frequency compensation circuit includes a capacitor C1; one end of the capacitor C1 is connected to the current output circuit, and the other end of the capacitor C1 is connected to the first-stage operational amplifier.

[0033] In one embodiment of the present invention, the load circuit includes a resistor R L and capacitor C L ;in,

[0034] Resistor R L One end of the capacitor C L One end of the current output circuit is connected and serves as the output voltage V OUT The output terminal, resistor R L The other end of the capacitor C L The other ends are grounded.

[0035] Beneficial effects of the present invention:

[0036] The high-current and wide-capacitance-range LDO based on the frequency compensation circuit proposed in the present invention aims at the problem of LDO circuit instability caused by a large load current variation range and a large load capacitance allowable range, and proposes a new frequency compensation scheme. Compared with the traditional compensation circuit, the multi-zero-pole dynamic compensation and the current buffer compensation are innovatively combined to realize frequency compensation for the LDO circuit with a large current and a wide capacitance range, thereby reducing the power consumption of the dynamic compensation circuit and expanding the frequency compensation range, so that the LDO circuit can obtain a good phase margin under the conditions of a wide output current range and a wide capacitance load, and can achieve a small bandwidth loss, thereby ensuring that a large bandwidth can still be obtained under a large current output range and a large load capacitance range, and the stability of the LDO circuit can be guaranteed, thereby solving the stability problem of the high-current and wide capacitance range LDO.

[0037] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the traditional LDO structure based on ESR compensation;

[0039] Figure 2 This is a schematic diagram of the traditional LDO structure based on dynamic zero compensation;

[0040] Figure 3 It is a structural schematic diagram of a high current and wide capacitance range LDO based on a frequency compensation circuit provided by an embodiment of the present invention;

[0041] Figure 4 This is a specific circuit diagram of a high current and wide capacitance range LDO based on a frequency compensation circuit provided by an embodiment of the present invention;

[0042] Figure 5 is a schematic diagram of a variable resistance generating circuit provided by an embodiment of the present invention;

[0043] Figure 6 The embodiment of the present invention provides Figure 4 Schematic diagram of the corresponding small signal model of LDO;

[0044] Figure 7 The embodiment of the present invention provides Figure 4 Schematic diagram of frequency response comparison before and after adding a multi-zero-pole dynamic compensation branch. DETAILED DESCRIPTION

[0045] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0046] See also Figure 3 The embodiment of the present invention provides a high current and wide capacitance range LDO based on a frequency compensation circuit, comprising:

[0047] A first-stage operational amplifier is used to amplify the error signal; the error signal is the difference between the reference voltage and the feedback voltage;

[0048] A secondary operational amplifier, connected to the primary operational amplifier, for performing secondary amplification on the amplified error signal;

[0049] A driving circuit, connected to the secondary operational amplifier, for enhancing the driving capability of the secondary amplified error signal;

[0050] A current output circuit is connected to the driving circuit and is used to adjust the output current required by the output according to the error signal of the secondary amplification with enhanced driving capability and the input voltage, so as to output the required output voltage through the load circuit;

[0051] A feedback circuit is connected to the current output circuit and is used to generate a new feedback voltage according to the output current;

[0052] The first-stage operational amplifier is connected to the feedback circuit and is also used to amplify the new error signal; the new error signal is the difference between the reference voltage and the new feedback voltage;

[0053] A frequency compensation circuit is connected to the current output circuit and the first-stage operational amplifier, and is used to use a multi-zero-pole dynamic compensation branch and a current buffer supplementary branch to adjust the positions of multiple zero poles in a new error signal according to the output current to offset the secondary poles while widening the entire unit gain bandwidth, thereby obtaining an adjusted error signal;

[0054] The secondary operational amplifier is connected to the frequency compensation circuit and is also used for secondary amplification of the adjusted error signal.

[0055] Next, each part is introduced in detail.

[0056] In the embodiment of the present invention, the first-stage operational amplifier is as follows Figure 4 As shown, it includes transistors MN1 to MN6, transistors MP1 to MP4, and a current source I bias ;in,

[0057] The gate of transistor MN1 is used as the reference voltage V ref The input terminal, the source of transistor MN1 and the source of transistor MN2, the current source I bias The input terminal of transistor MN1 is connected, the drain of transistor MN1 is connected to the source of transistor MP1 and the drain of transistor MP3, the gate of transistor MN2 is connected to the feedback circuit, the drain of transistor MN2 is connected to the source of transistor MP2 and the drain of transistor MP4, and the gate of transistor MN3 and the gate of transistor MN4 are both connected to the third bias voltage V b3 The source of transistor MN3 is connected to the drain of transistor MN5, the drain of transistor MN3 is connected to the drain of transistor MP1, the gate of transistor MN5, the gate of transistor MN6, and the current buffer supplement branch, the source of transistor MN4 is connected to the drain of transistor MN6, the drain of transistor MN4 is connected to the drain of transistor MP2 and the multi-zero-pole dynamic compensation branch, the source of transistor MN5, the source of transistor MN6, and the current source I bias The output terminals of the transistors MP1 and MP2 are both connected to the ground, and the gates of the transistors MP1 and MP2 are both connected to the second bias voltage V b2 The gate of transistor MP3 and the gate of transistor MP4 are both connected to the first bias voltage V b1 , the source of transistor MP3 and the source of transistor MP4 are both connected to the power supply VDD. Among them, the reference voltage V ref , the first bias voltage V b1 , the second bias voltage V b2 , the third bias voltage V b3 Set according to actual needs.

[0058] In the embodiment of the present invention, transistors MN1 to MN6 are NMOS transistors; and transistors MP1 to MP4 are PMOS transistors.

[0059] Furthermore, in the embodiment of the present invention, the secondary operational amplifier is as follows: Figure 4 As shown, it includes high-voltage power tube HVMN1, resistor R P , transistor MN7; wherein,

[0060] The gate of the high-voltage power tube HVMN1 is connected to the power supply VDD, and the drain of the high-voltage power tube HVMN1 is connected to the resistor R P The source of the high-voltage power tube HVMN1 is connected to the drain of the transistor MN7, the gate of the transistor MN7 is connected to the first-stage operational amplifier, the source of the transistor MN7 is grounded, and the resistor R P The other end is connected to the input voltage V IN Among them, the input voltage V IN Set according to actual needs.

[0061] In the embodiment of the present invention, the transistor MN7 is an NMOS transistor; the high-voltage power tube HVMN1 is an NMOS power tube.

[0062] Furthermore, the driving circuit in the embodiment of the present invention is as follows Figure 4 As shown, it includes a follower BUFFER; the input end of the follower BUFFER is connected to the secondary operational amplifier, and the output end of the follower BUFFER is connected to the current output circuit.

[0063] Furthermore, the current output circuit in the embodiment of the present invention is as follows Figure 4 As shown, it includes a high-voltage power tube HVMP1; the source of the high-voltage power tube HVMP1 is connected to the input voltage V IN The drain of the high-voltage power tube HVMP1 is connected to the feedback circuit, the load circuit, and the current buffer supplement branch, and the gate of the high-voltage power tube HVMP1 is connected to the multi-zero-pole dynamic compensation branch.

[0064] The high-voltage power tube HVMP1 in the embodiment of the present invention is a PMOS power tube.

[0065] Furthermore, the feedback circuit in the embodiment of the present invention is as follows: Figure 4 As shown, it includes a resistor R1 and a resistor R2; wherein one end of the resistor R1 is connected to the current output circuit, the other end of the resistor R1 is connected to one end of the resistor R2 and a first-stage operational amplifier, and the other end of the resistor R2 is grounded.

[0066] Furthermore, in the embodiment of the present invention, the multi-zero-pole dynamic compensation branch in the frequency compensation circuit includes N parallel zero-pole compensation sub-branches, where N is an integer greater than 1; each zero-pole compensation sub-branch is composed of a fixed capacitor and a variable resistor connected in series, the other end of the fixed capacitor is connected to a first-level operational amplifier, and the other end of the variable resistor is grounded; wherein the variable resistor of each zero-pole compensation sub-branch is generated by a variable resistor generating module according to an output current adjusted by a current output circuit; the ratio of the fixed capacitors in all zero-pole compensation sub-branches is 1:2:…:2 N-1 , the ratio of the resistance of the variable resistor is 2 N-1 :…:2:1. Figure 4 The structure of the multi-zero-pole dynamic compensation branch with N=3 is shown.

[0067] The variable resistance generating module in the embodiment of the present invention includes N variable resistance generating branches, a transistor MN8, a high voltage power tube HVMP2, a resistor R s ;in,

[0068] N variable resistance generating branches are connected in parallel, and each variable resistance generating branch includes a fixed resistor and a plurality of transistors connected in series with the fixed resistor, the other end of the fixed resistor is connected to the corresponding fixed capacitor, and the source of the last transistor is connected to the source of the transistor MN8; the ratio of the resistance values ​​of the fixed resistors in all variable resistance generating branches is 2 N-1 :...:2:1, the ratio of the number of transistors is 2 N-1 :...:2:1; The gate of transistor MN8 is connected to the drain of transistor MN8, the drain of high-voltage power tube HVMP2, and the gates of all transistors in each variable resistance generating branch. The gate of high-voltage power tube HVMP2 is connected to the current output circuit. The source of high-voltage power tube HVMP2 is connected to resistor R s One end of the resistor R s The other end is connected to the input voltage V IN .like Figure 5 The structure of the variable resistance generating module with N=3 is shown.

[0069] In the embodiment of the present invention, the transistor MN8 is an NMOS transistor; the high-voltage power transistor HVMP2 is a PMOS power transistor.

[0070] Furthermore, the current buffer supplementary branch in the frequency compensation circuit in the embodiment of the present invention is as follows: Figure 4 As shown, it includes a capacitor C1; one end of the capacitor C1 is connected to the current output circuit, and the other end of the capacitor C1 is connected to the first-stage operational amplifier.

[0071] Furthermore, the load circuit in the embodiment of the present invention is as follows Figure 4 As shown, including resistor R Land capacitor C L ; Among them, the resistor R L One end of the capacitor C L One end of the current output circuit is connected and used as the output voltage V OUT The output terminal, resistor R L The other end of the capacitor C L The other ends are grounded.

[0072] Next, the working principle of the LDO proposed in the present invention is introduced.

[0073] Before analyzing the LDO circuit, we first analyze the LDO circuit to obtain the small signal model of the LDO. From the small signal model, we can see that when the frequency compensation circuit is not added, there are three poles in the LDO circuit, which are Figure 4 The output node A of the first-stage operational amplifier, the gate B of the high-voltage power tube HVMP1, and the output terminal C of the LDO are as follows:

[0074]

[0075] Among them, ω in formula (1) A represents the frequency of the pole at the output node of the first stage operational amplifier, R EA represents the equivalent resistance of the output node of the first-stage operational amplifier, C EA represents the parasitic capacitance of the output node of the first-stage operational amplifier; in formula (2), ω B Represents the frequency of the pole at the gate of the high-voltage power tube HVMP1, R g Represents the equivalent resistance at the gate of the high-voltage power tube HVMP1, C g represents the equivalent capacitance at the gate of the high-voltage power tube HVMP1; in formula (3), ω C represents the frequency of the LDO output pole, R L represents the load resistance at the LDO output, C L Represents the load capacitance at the output of the LDO. In the design, it is located at the pole of A. EA and C EA The size of is fixed and will not change with the output current and load capacitance, so ω A The frequency position of is fixed; the pole located at B changes with the load, and may be lower than the unity gain frequency or higher than the unity gain frequency; the pole located at C moves in a wide frequency range with the load current. In this case, the main pole is C when lightly loaded, and gradually transitions to A as the load increases. Considering that there may be three poles that appear below the unity gain frequency, it is difficult to achieve stability even if a zero is introduced within the bandwidth.

[0076] The above analysis shows that there is a problem with the stability of the LDO, so a frequency compensation circuit designed by the present invention is added to compensate for it. The following is an analysis of how the LDO can achieve stability after adding the frequency compensation circuit.

[0077] Figure 6 is a small signal model of the LDO circuit including the frequency compensation circuit, where gm1 is the transconductance of transistor MN1, gm2 is the transconductance of transistor MN6, gm3 is the transconductance of high-voltage power tube HVMP1, gm4 is the transconductance of transistor MN5, and F=R2 / (R1+R2) is the feedback factor. Figure 4 and Figure 5 Taking N=3 as an example, since the influence of three multi-zero-pole dynamic compensation branches and one current buffer compensation branch on the circuit is directly considered, too many poles will appear, making the transfer function impossible to calculate. In order to reduce the difficulty of analysis, the influence of the two types of compensation on the circuit are discussed below.

[0078] For the current buffer compensation branch, see Figure 4 The red lines mark the branches and Figure 6 The red line marks the branch. The current buffer compensation branch includes capacitor C1, which acts on the components in the LDO circuit including high-voltage power tube HVMP1, high-voltage power tube HVMN1, transistor MN2, transistor MN4, transistor MN5, (source) follower BUFFER, resistor R P , transistor MP2, transistor MP4. When current buffer compensation is considered, the multi-zero-pole dynamic compensation branch is equivalent to C Z and R Z Series (such as Figure 6 In the blue dashed box, r is used for calculation convenience. o =1 / gm4. The transfer function of the current buffer compensation branch is obtained by calculation:

[0079]

[0080] Observe the denominator of the transfer function in formula (4). The highest order term is fifth, which means there are five poles. Ignoring the higher order terms and considering only the first two poles, we can get the frequency of two poles and two zeros:

[0081]

[0082] Due to r o and C1 are small, so the frequency ω Z2 Higher, no effect on the circuit, here do not consider this high frequency zero point. First point, through the frequency ω1 and frequency ω A It can be seen from the comparison that the main pole frequency ω1 after frequency compensation is significantly lower than the main pole frequency ω before compensation A, which means that the loop gain starts to decrease from a lower frequency. By adjusting the parameters, it can be reduced to 0 before the pole brought by point B takes effect. Secondly, the frequency at the main pole A is less sensitive to changes in load current and capacitance than before compensation, especially under heavy load conditions, which makes the main pole more stable. The second point, the frequency change at the second pole (secondary pole) C is divided into light load and heavy load conditions; under light load conditions, g m2 R g g m3 R L C1 is much larger than C Z , formula (6) can be simplified as:

[0083]

[0084] From formula (9), we can see that under light load conditions, the frequency ω'2 is always less than the frequency ω Z1 , by designing R Z The resistance is used to control ω Z1 The distance between ω'2 and the zero point can compensate the second pole C, ensuring that the phase margin is still greater than 60 degrees when the gain drops to 0, and is in a stable state. L Much smaller than R EA , formula (6) can be simplified as:

[0085]

[0086] It can be seen from formula (10) that when the frequency of the second pole under heavy load conditions is greater than the frequency of the second pole under light load conditions, if it is stable under light load conditions, it is guaranteed to be stable under heavy load conditions.

[0087] From the above analysis, it can be seen that the stability of the LDO circuit is improved after compensation by the current buffer compensation branch. However, under light load conditions, if the load capacitance is large, the main pole and the second pole will be closer, and the unit gain bandwidth will be very small. Therefore, a multi-zero-pole dynamic compensation branch is added to increase the circuit unit gain bandwidth.

[0088] For the multi-zero-pole dynamic compensation branch, see Figure 4 The circuit in the blue dotted box and Figure 6 The blue dotted line frame part of the circuit, the zero-pole branch compensation branch is a variable resistor R Z1 , variable resistor R Z2 , variable resistor R Z3 , fixed capacitor C Z1 , fixed capacitor C Z2 , fixed capacitor C Z3 The variable resistor R Z1 , R Z2 , R Z3 The circuit is generated by a variable resistor. Figure 5As shown, the variable resistor R Z3 By fixed resistor R C and several transistors MN connected in series 11 Composition, variable resistor R Z2 By fixed resistor R B and several transistors MN connected in series 10 Composition, variable resistor R Z1 By fixed resistor R A And several transistors MN9 connected in series. In addition to the above components, the variable resistance generation circuit also has a resistor R S , high-voltage power tube HVMP2, and transistor MN8. The gate of HVMP2 in the variable resistance generation module is connected to the gate of HVMP1 to form a current mirror. The width-to-length ratio of HVMP2 and HVMP1 is set at a certain ratio so that the current flowing through HVMP2 and the load current I OUT Proportional, such as load current I OUT When the load current I is 100mA, the width-to-length ratio of HVMP2 to HVMP1 is set so that the current flowing through HVMP2 is 1mA. OUT Here we add resistor R S Improves the linearity of the dynamic resistance of the variable resistor generating branch and the load current change. 10 MN 11 The width-to-length ratio of each transistor is the same, and the sampled current flows through MN8 to control MN9 and MN 10 MN 11 The voltage of each transistor gate in the heavy load condition is MN9, MN 10 MN 11 The resistance value formed by each lattice tube is too small, so a fixed resistor R is added A , R B , R C , to increase the total resistance and help stabilize the loop.

[0089] A dynamic network with multiple zero-pole dynamic compensation branches is used to solve the problem of a large pole variation range. Multiple zero-pole points move together to offset the secondary poles while widening the unity gain bandwidth. Figure 4 The blue dotted box shows the structure of N=3. Three zero-pole compensation sub-branches are designed to form a compensation network. The resistance values ​​of the three zero-pole compensation sub-branches are proportional, and the capacitance values ​​are also proportional, resulting in three zeros and three poles, which are distributed alternately. Figure 4 Fixed capacitor C Z1 :C Z2 :C Z3 =1:2:4, Figure 5 Fixed resistor RA :R B :R C =1:2:4, Figure 5 The number of transistors in MN9:MN 10 :MN 11 =1:2:4, Figure 6 Middle C EA Much smaller than the compensation capacitor C Z1 , C Z2 , C Z3 , so it can be ignored.

[0090] The transfer function of the multi-zero-pole dynamic compensation branch is as follows:

[0091]

[0092] Due to R A :R B :R C =1R:2R:4R,C Z1 :C Z2 :C Z3 =1C:2C:4C, R EA If R is much larger than R, the transfer function of the multi-zero-pole dynamic compensation branch is simplified:

[0093]

[0094] From formula (11), we can see that Figure 4 The frequencies of the three poles generated by the multi-zero-pole dynamic compensation branch are recorded as P1, P2, and P3, and the frequencies of the three zeros generated are recorded as Z1, Z2, and Z3. Analyzing the size of the generated zero poles, the frequency size relationship between the zero and the pole is P1<Z1<P2<Z2<P3<Z3, so the generated zero poles will act on each other in phase. In order to verify the effect of adding a multi-zero-pole dynamic compensation branch, Figure 7 The frequency response comparison results before and after adding the multi-zero-pole dynamic compensation branch are given. Figure 7 It can be seen that after adding the multi-zero-pole dynamic compensation branch, the phase margin can be improved, and the main pole P EA The phase margin is always greater than 90° within the unit gain bandwidth, which is determined by the pole frequency P1 of the multi-zero-pole dynamic compensation branch and the main pole ω1 of the current buffer compensation branch. No matter how the frequency POUT of the pole at the output of the LDO changes, the phase margin is always guaranteed to be greater than 90° within the unit gain bandwidth, and on this basis, the unit gain bandwidth of the LDO circuit is improved.

[0095] The embodiment of the present invention provides a frequency compensation circuit for a large current and wide capacitance range LDO. Compared with the traditional compensation circuit, it uses a combination of multi-zero-pole dynamic compensation and current buffer compensation technology: the variable resistor in the multi-zero-pole dynamic compensation branch is generated by a variable resistor generation module. The current buffer compensation branch of the LDO is implemented by a Miller capacitor, which is connected from the output node of the LDO to the gate of the active current mirror loads MN5 and MN6 of the operational amplifier; the multi-zero-pole dynamic compensation branch of the LDO is connected to the output node of the first-level operational amplifier in series with multiple fixed capacitors and variable resistors, wherein the resistance value of the variable resistor can change with the increase or decrease of the load current, thereby generating multiple zero points of frequency change. The current buffer compensation branch can separate the pole existing at the output end of the first-level operational amplifier and the pole existing at the output end of the LDO, push away the two pole positions, and then solve the problem of the possible second pole entering the unit gain bandwidth through the multi-zero-pole dynamic compensation branch. In the design of the multi-zero-pole dynamic compensation branch, multiple zero-pole generation branches are designed, and the generated multiple zero-poles can ensure that the LDO is in a stable state when the load current is the lowest and the load current is the highest. It can be seen that the frequency compensation scheme proposed in the embodiment of the present invention can enable the LDO circuit to maintain the stability of the system under a larger output current range and a wide load capacitance range, and improve the bandwidth of the LDO circuit, so that the LDO circuit can both ensure stability and have a larger bandwidth. The two compensation methods are innovatively combined to compensate the LDO. Different from the traditional dynamic compensation, multiple branches are connected in parallel to generate multiple zeros and poles to enable the LDO circuit to obtain a larger bandwidth. At the same time, the main pole is set on the chip using this compensation method, which can reduce the LDO chip's requirements for external capacitors to ensure system stability.

[0096] In the description of the present invention, it should be understood that the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0097] Although the present invention is described herein in conjunction with various embodiments, in the process of implementing the claimed invention, those skilled in the art may understand and implement other variations of the disclosed embodiments by viewing the specification and its drawings. In the specification, the word "comprising" does not exclude other components or steps, and "a" or "one" does not exclude multiple situations. Certain measures are recorded in different embodiments, but this does not mean that these measures cannot be combined to produce good results.

[0098] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A high current and wide capacitance range LDO based on a frequency compensation circuit, characterized in that: include: A first-stage operational amplifier, used to amplify an error signal; the error signal is the difference between a reference voltage and a feedback voltage; A secondary operational amplifier, connected to the primary operational amplifier, for performing secondary amplification on the amplified error signal; A driving circuit, connected to the secondary operational amplifier, for enhancing the driving capability of the secondary amplified error signal; A current output circuit, connected to the driving circuit, for adjusting the output current required by the output according to the secondary amplified error signal with enhanced driving capability and the input voltage, so as to output the required output voltage through the load circuit; A feedback circuit, connected to the current output circuit, for generating a new feedback voltage according to the output current; The first-stage operational amplifier is connected to the feedback circuit and is also used to amplify a new error signal; the new error signal is the difference between the reference voltage and the new feedback voltage; A frequency compensation circuit, connected to the current output circuit and the first-stage operational amplifier, for adjusting the positions of multiple zero poles in the new error signal according to the output current by using a multi-zero-pole dynamic compensation branch and a current buffer supplement branch to offset the secondary poles while widening the entire unit gain bandwidth, thereby obtaining an adjusted error signal; The secondary operational amplifier is connected to the frequency compensation circuit and is also used to perform secondary amplification on the adjusted error signal.

2. The high current and wide capacitance range LDO based on the frequency compensation circuit according to claim 1, characterized in that: The first-stage operational amplifier includes transistors MN1 to MN6, transistors MP1 to MP4, and a current source I bias ;in, The gate of transistor MN1 is used as the reference voltage V ref The input terminal, the source of transistor MN1 and the source of transistor MN2, the current source I bias The input end of the transistor MN1 is connected, the drain of the transistor MN1 is connected to the source of the transistor MP1 and the drain of the transistor MP3, the gate of the transistor MN2 is connected to the feedback circuit, the drain of the transistor MN2 is connected to the source of the transistor MP2 and the drain of the transistor MP4, the gate of the transistor MN3 and the gate of the transistor MN4 are both connected to the third bias voltage, the source of the transistor MN3 is connected to the drain of the transistor MN5, the drain of the transistor MN3 is connected to the drain of the transistor MP1, the gate of the transistor MN5, the gate of the transistor MN6, and the current buffer supplement branch, the source of the transistor MN4 is connected to the drain of the transistor MN6, the drain of the transistor MN4 is connected to the drain of the transistor MP2 and the multi-zero-pole dynamic compensation branch, the source of the transistor MN5, the source of the transistor MN6, and the current source I bias The output ends of the transistors MP1 and MP2 are grounded, the gates of the transistors MP1 and MP2 are connected to the second bias voltage, the gates of the transistors MP3 and MP4 are connected to the first bias voltage, and the sources of the transistors MP3 and MP4 are connected to the power supply VDD.

3. The high current and wide capacitance range LDO based on the frequency compensation circuit according to claim 1, characterized in that: The secondary operational amplifier includes a high voltage power tube HVMN1, a resistor R P , transistor MN7; wherein, The gate of the high-voltage power tube HVMN1 is connected to the power supply VDD, and the drain of the high-voltage power tube HVMN1 is connected to the resistor R P The source of the high-voltage power tube HVMN1 is connected to the drain of the transistor MN7, the gate of the transistor MN7 is connected to the first-stage operational amplifier, the source of the transistor MN7 is grounded, and the resistor R P The other end is connected to the input voltage V IN .

4. The high current and wide capacitance range LDO based on the frequency compensation circuit according to claim 1, characterized in that: The driving circuit comprises a follower BUFFER; the input end of the follower BUFFER is connected to the secondary operational amplifier, and the output end of the follower BUFFER is connected to the current output circuit.

5. The high current and wide capacitance range LDO based on frequency compensation circuit according to claim 1, characterized in that: The current output circuit includes a high-voltage power tube HVMP1; the source of the high-voltage power tube HVMP1 is connected to the input voltage V IN The drain of the high-voltage power tube HVMP1 is connected to the feedback circuit, the load circuit, and the current buffer supplement branch, and the gate of the high-voltage power tube HVMP1 is connected to the multi-zero-pole dynamic compensation branch.

6. The high current and wide capacitance range LDO based on frequency compensation circuit according to claim 1, characterized in that: The feedback circuit includes a resistor R1 and a resistor R2; wherein, One end of the resistor R1 is connected to the current output circuit, the other end of the resistor R1 is connected to one end of the resistor R2 and the first-stage operational amplifier, and the other end of the resistor R2 is grounded.

7. The high current and wide capacitance range LDO based on frequency compensation circuit according to claim 1, characterized in that: The multi-zero-pole dynamic compensation branch in the frequency compensation circuit includes N parallel zero-pole compensation sub-branches, where N is an integer greater than 1; each zero-pole compensation sub-branch is composed of a fixed capacitor and a variable resistor connected in series, the other end of the fixed capacitor is connected to the first-level operational amplifier, and the other end of the variable resistor is grounded; wherein the variable resistor of each zero-pole compensation sub-branch is generated by a variable resistor generating module according to the output current adjusted by the current output circuit; the ratio of the fixed capacitors in all zero-pole compensation sub-branches is 1:2:…:2 N-1 , the ratio of the resistance of the variable resistor is 2 N-1 :…:2:

1.

8. The high current and wide capacitance range LDO based on the frequency compensation circuit according to claim 7, characterized in that: The variable resistance generation module includes N variable resistance generation branches, a transistor MN8, a high voltage power tube HVMP2, a resistor R s ;in, N variable resistance generating branches are connected in parallel, and each variable resistance generating branch includes a fixed resistor and a plurality of transistors connected in series with the fixed resistor, the other end of the fixed resistor is connected to the corresponding fixed capacitor, and the source of the last transistor is connected to the source of the transistor MN8; the ratio of the resistance values ​​of the fixed resistors in all variable resistance generating branches is 2 N -1 :…:2:1, the ratio of the number of transistors is 2 N-1 :…:2:1; The gate of transistor MN8 is connected to the drain of transistor MN8, the drain of high-voltage power tube HVMP2, and the gates of all transistors in each variable resistance generating branch. The gate of high-voltage power tube HVMP2 is connected to the current output circuit. The source of high-voltage power tube HVMP2 is connected to resistor R s One end of the resistor R s The other end is connected to the input voltage V IN .

9. The high current and wide capacitance range LDO based on frequency compensation circuit according to claim 1, characterized in that: The current buffer supplementary branch in the frequency compensation circuit includes a capacitor C1; one end of the capacitor C1 is connected to the current output circuit, and the other end of the capacitor C1 is connected to the first-stage operational amplifier.

10. The high current and wide capacitance range LDO based on frequency compensation circuit according to claim 1, characterized in that: The load circuit includes a resistor R L and capacitor C L ;in, Resistor R L One end of the capacitor C L One end of the current output circuit is connected and serves as the output voltage V OUT The output terminal, resistor R L The other end of the capacitor C L The other ends are grounded.

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