Secure information overlay on digital video signals in Ultra High Definition in real time

The FPGA-based system architecture addresses the challenge of delay-free, high-resolution image display in medical applications by separating critical and non-critical processing, ensuring real-time operation and operational reliability for safe medical imaging.

DE102017010351B4Active Publication Date: 2025-09-25BRAINLAB AG
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Patent Information

Application Number
DE102017010351
Authority / Receiving Office
DE · DE
Patent Type
Patents
Current Assignee / Owner
Filing Date
2017-11-09
Publication Date
2025-09-25
Estimated Expiration
2037-11-09

AI Technical Summary

Technical Problem

Existing video processing technologies fail to provide delay-free, high-resolution image display for medical applications, particularly in Ultra HD or 4K resolutions, leading to potential operational risks due to image transmission delays and lacking operational reliability.

Method used

A system architecture utilizing modern FPGA systems with integrated application processors and real-time processors, separating safety-critical and non-safety-critical image processing, where the critical part is implemented in dedicated hardware and monitored by redundant processors, while the non-critical part resembles a classic PC setup with additional video encoding and decoding capabilities.

Benefits of technology

Achieves real-time, delay-free image processing with high operational reliability, ensuring safe and efficient handling of high-resolution medical imaging data, supporting complex image processing tasks and enabling simultaneous display for multiple operators.

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Abstract

System for superimposing at least one additional video signal onto a video signal which enters the system via a first digital video input (1, 8) and leaves the system via a digital video output (2, 9), characterized in that the system is implemented on an FPGA (Field Programmable Gate Array) semiconductor circuit and is divided into a non-safety-critical part (B) and a safety-critical part (A) which is independent of the latter and connected to the latter via a video signal connection (100), wherein the non-safety-critical part (B) is designed for image processing and comprises at least one of the following components: - a processor (101), - a video encoder / decoder unit (103), - a working memory (104), - at least one interface (105), and wherein the safety-critical part (A) is designed to superimpose the video signals in resolutions of Ultra HD / 4K or higher and with a delay of less than one line between the video signal leaving the system and the video signal entering the system.
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