Game machine

Abstract

To make it possible to perform improved image performance control and to perform effective performance by visually emphasizing a specific scene and its switching.SOLUTION: A game machine has: image control means issuing a display list; and image generation means having a drawing circuit generating image data on the basis of the display list and basic data. The image control means has setting means setting an appropriate abnormality determination time to a register of the image generation means. The image generation means has setting means setting an appropriate abnormality determination time to a register of the image generation means; the image generation means has monitoring means monitoring a memory access time interval and / or a decoding execution time by the drawing circuit and determination means determining that an abnormal condition has occurred when they are beyond the abnormality determination time. In a character information display performance, a first / second dynamic display performance which can perform dynamic display of character information at a first / second changing speed, executes specific display processing displaying the character information in a specific display mode during the second dynamic display performance, but not during the first dynamic display performance.SELECTED DRAWING: Figure 17

Description

[Technical field]

[0001] The present invention relates to a gaming machine such as a pachinko machine. [Background technology]

[0002] 2. Description of the Related Art In gaming machines such as pachinko machines, various effects can be executed according to the gaming status, mainly based on image display on an image display means such as a liquid crystal display means. [Prior art documents] [Patent documents]

[0003] [Patent Document 1] Patent Publication No. 2022-030912 Summary of the Invention [Problem to be solved by the invention]

[0004] In this type of gaming machine, various animation images are displayed on the image display means, and in many cases, various text information is displayed in addition to the images of characters, etc. This text information is not just a presentation image, but also plays a role in informing the player of information, so the question is how to display it in a way that enhances the presentation effect together with other images while ensuring visibility. Thus, further advances in image presentation and improvements in image presentation control are desired. The present invention has been made in consideration of the above circumstances, and aims to provide a gaming machine that is capable of executing improved image presentation control and can further enhance the presentation effect of the text information displayed on the image display means, together with other images. [Means for solving the problem]

[0005] The present invention relates to a gaming machine that has an image control means for issuing a display list specifying display contents to be displayed on an image display means, and an image generation means having a drawing circuit for generating image data for realizing the display contents based on the display list and basic data of an appropriate storage means, and that is capable of executing effects including image display on the image display means, wherein the image control means has setting means for setting an appropriate abnormality determination time in a predetermined register of the image generation means, while the image generation means has a monitoring means for monitoring a memory access time interval by the drawing circuit and / or a decode execution time for decoding the basic data. The display device has a viewing means and a judgment means for judging that an abnormality has occurred when the memory access time interval or the decode execution time exceeds the abnormality judgment time, and the presentation includes a character information display presentation for dynamically displaying character information, and the character information display presentation can execute a first dynamic display presentation for dynamically displaying the character information at a first change rate and a second dynamic display presentation for dynamically displaying the character information at a second change rate different from the first change rate, and is configured to execute a specific display process for displaying the character information in a specific display mode during the second dynamic display presentation, and not execute the specific display process during the first dynamic display presentation. Effect of the Invention

[0006] According to the present invention, it is possible to execute a smooth and appropriate image control operation, and it is possible to further improve the presentation effect of the character information displayed on the image display means together with other images. [Brief description of the drawings]

[0007] [Figure 1] 1 is a perspective view showing a pachinko machine according to an embodiment of the present invention. [Diagram 2] 2 is a front view showing a gaming area of ​​the gaming machine of FIG. 1. [Diagram 3] 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. [Figure 4] This illustrates the internal configurations of the performance interface board, the performance control board, and the liquid crystal interface board. [Diagram 5]FIG. 2 is a circuit block diagram illustrating a composite chip including associated circuit elements. [Figure 6] 1 is a diagram for explaining an index space and a virtual drawing space. [Figure 7] 1 is a diagram illustrating a display circuit. [Figure 8] 4 is a diagram illustrating an internal configuration of a data transfer circuit. [Figure 9] 11 is a diagram for explaining a transfer operation of a display list and a voice command list. [Figure 10] 11 is a diagram for explaining a filter process based on a display list. [Figure 11] 1 is a diagram for explaining the procedure for playing IPB stream video. [Figure 12] 4 is a diagram illustrating an internal configuration and a control procedure of an audio processing unit. [Figure 13] 1 is a diagram for explaining a drawing pipeline process of a drawing circuit. [Figure 14] FIG. 2 is a process diagram illustrating various rendering modes that utilize all or part of the rendering pipeline steps. [Figure 15] 13 is a flowchart explaining the control operation of a performance control CPU that does not include a preload operation. [Figure 16] 16 is a flowchart illustrating a part of FIG. 15. [Figure 17] 13 is a flowchart explaining the control operation of the performance control CPU, including the preload operation. [Figure 18] FIG. 13 is a diagram showing an example of a performance display by a display device. [Figure 19] An explanatory diagram showing the fluctuation of mini patterns. [Figure 20] A diagram showing the types of preview effects and the settings of the probability of winning. [Figure 21] A diagram showing the overall structure of the step-up preview performance. [Figure 22] A diagram showing the types of the third and fifth second half performances of the step-up preview performance. [Diagram 23]A figure showing an overview of a specific example of a step-up preview performance. [Figure 24] This is a diagram (part 1) showing details of the image changes during the period from the start of high-brightness performance WO11 to the end of high-brightness performance WO12 and the transition to a decorative pattern changing screen, as a specific example of a step-up preview performance. [Diagram 25] This is a second figure showing details of the image changes from the start of high-brightness performance WO11 to the end of high-brightness performance WO12 and the transition to a decorative pattern changing screen, as a specific example of a step-up preview performance. [Figure 26] This is a third figure showing details of the image changes during the period from the start of high-brightness performance WO11 to the end of high-brightness performance WO12 and the transition to a decorative pattern changing screen, as a specific example of a step-up preview performance. [Figure 27] A diagram showing the types of presentation modes of reach preview presentations. [Figure 28] A figure showing an overview of a specific example of a reach preview performance. [Figure 29] FIG. 1 is a diagram (part 1) showing details of image changes during the period from the start of high-brightness performance WO21 to the transition to a decorative pattern changing screen, among specific examples of reach-notice performances. [Diagram 30] FIG. 2 is a diagram (part 2) showing details of the image changes during the period from the start of the high-brightness performance WO21 to the transition to a decorative pattern changing screen, among other specific examples of reach-notice performances. [Diagram 31] FIG. 3 is a diagram (part 3) showing details of the image changes during the period from the start of the high-brightness performance WO21 to the transition to a decorative pattern changing screen, among other specific examples of reach-notice performances. [Diagram 32] A diagram showing an overview of a specific example of button preview performance 1. [Diagram 33] This figure shows details of the image changes in button introduction performance BA0, a specific example of button preview performance 1. [Diagram 34] This figure shows details of the image changes in high-brightness effect WO31, a specific example of button preview effect 1. [Diagram 35]This figure shows details of the image change from high-brightness performance WO32 to high-brightness performance WO33, a specific example of button preview performance 1. [Diagram 36] This figure shows the types of dialogue preview performance 1 and their contents, the dialogue content and display color, and the character type. [Figure 37] A diagram showing an overview of a specific example of dialogue preview performance 1. [Figure 38] FIG. 13 is a diagram (part 1) showing details of image changes during the period from the start of high-brightness performance WO41 to the end of high-brightness performance WO42, in a specific example of dialogue preview performance 1. [Figure 39] FIG. 2 is a diagram (part 2) showing details of image changes during the period from the start of high-brightness performance WO41 to the end of high-brightness performance WO42 in a specific example of dialogue preview performance 1. [Diagram 40] FIG. 3 is a diagram (part 3) showing details of image changes during the period from the start of high-brightness performance WO41 to the end of high-brightness performance WO42 in a specific example of dialogue preview performance 1. [Diagram 41] A figure showing an overview of a specific example of a pseudo-consecutive preview performance. [Diagram 42] This figure shows details of the image changes during the period from the first pseudo-consecutive first half performance PF1A, through the high brightness performance WO51, to the start of the first pseudo-consecutive second half performance PF1B, as a specific example of a pseudo-consecutive preview performance. [Diagram 43] This figure shows details of the image changes during the period from the second pseudo-consecutive first half performance PF2A, through the high brightness performance WO52, to the start of the second pseudo-consecutive second half performance PF2B, as a specific example of a pseudo-consecutive preview performance. [Diagram 44] A diagram showing an overview of a specific example of button preview performance 2. [Diagram 45] This is a diagram (part 1) showing details of the image changes in button teasing performance BB1, one of the specific examples of button preview performance 2. [Figure 46] This is a diagram (part 2) showing details of the image changes in button teasing performance BB1, one of the specific examples of button preview performance 2. [Figure 47]This is a diagram (part 3) showing details of the image changes in button teasing performance BB1, one of the specific examples of button preview performance 2. [Figure 48] A diagram showing the types of presentation aspects of interruption notice presentations. [Figure 49] A figure showing an overview of a specific example of an interruption notice performance. [Figure 50] FIG. 13 is a diagram (part 1) showing details of image changes during the period from the start of high-brightness effect WO71 to the end of high-brightness effect WO73, among specific examples of cut-in advance notice effects. [Figure 51] FIG. 2 is a diagram (part 2) showing details of image changes during the period from the start of high-brightness performance WO71 to the end of high-brightness performance WO73, among specific examples of cut-in notice performances. [Figure 52] FIG. 11 is a diagram (part 3) showing details of image changes during the period from the start of high-brightness performance WO71 to the end of high-brightness performance WO73, among specific examples of cut-in advance performances. [Figure 53] A diagram showing an overview of a specific example of dialogue preview performance 2. [Figure 54] FIG. 13 is a diagram (part 1) showing details of image changes during the period from character appearance performance SB1 to line output performance SB3, among other specific examples of line preview performance 2. [Figure 55] FIG. 2 is a diagram (part 2) showing details of image changes during the period from character appearance performance SB1 to line output performance SB3 in a specific example of line preview performance 2. [Figure 56] A figure showing an overview of a specific example of a reliability suggestion effect. [Figure 57] FIG. 13 is a diagram (part 1) showing details of image changes during the period from the first character string start performance PR1 to the second line output performance PR4 as a specific example of a reliability suggestion performance. [Figure 58] FIG. 2 is a diagram (part 2) showing details of the image changes during the period from the first character string start performance PR1 to the second line output performance PR4 as a specific example of a reliability suggestion performance. [Figure 59] A figure showing an overview of a specific example of a reach title display presentation. [Figure 60] This figure shows details of the image changes during the period from the title display start performance TS1 to the title announcement performance TS, among specific examples of reach title display performances. [Figure 61] FIG. 13 is a diagram showing an overview of a specific example of operation presentation. [Figure 62] This figure shows details of the image changes during the period from the operation display start presentation BC1 to the operation promotion presentation BC2, among specific examples of operation presentations. [Figure 63] A figure showing an overview of a specific example of a reach development performance. [Figure 64] FIG. 13 is a diagram (part 1) showing details of image changes during a period of high-brightness effect WOB1, among specific examples of reach development effects. [Figure 65] FIG. 2 is a diagram (part 2) showing details of image changes during a period of high-brightness effect WOB1, among specific examples of reach development effects. [Figure 66] FIG. 11 is a diagram (part 3) showing details of image changes during a period of high-brightness effect WOB1, among specific examples of reach development effects. [Figure 67] FIG. 11 is an explanatory diagram showing another example of a high-brightness image. BEST MODE FOR CARRYING OUT THEINVENTION

[0008] The present invention will be described in detail below based on the embodiments. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM is composed of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached to be able to open and close via a hinge 2 fixed to the outer frame 1. A game board 5 is detachably attached to this inner frame 3 from the front side, not from the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so that they can be opened and closed. In this specification, the glass door 6 and the front panel 7 are collectively referred to as a front door member. The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may be referred to as a game frame.

[0009] Illuminated lamps such as LED lamps are arranged around the periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right positions and on the lower side of the glass door 6. The two speakers arranged on the upper side are configured to output the sounds of the left and right channels R and L, respectively, and the speaker on the lower side is configured to output low tones.

[0010] An upper tray 8 for storing game balls to be launched is attached to the front panel 7, and a lower tray 9 for storing game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0011] A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his / her right hand off the launch handle 10. This chance button 11 is not normally functional, but when the game state becomes a button chance state, a built-in lamp is lit and the button becomes operable. The button chance state is a game state that is provided as necessary.

[0012] In addition, a rotary switch type volume switch VLSW is located below the chance button 11, and the player can adjust the speaker volume in eight steps from silent level (=0) to the maximum level (=7) by operating the volume switch VLSW. The speaker volume is initially set by a setting switch (not shown) that can be operated only by the attendant, and the initially set volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality notification sound that notifies the occurrence of an abnormal situation is emitted at the maximum volume regardless of the initially set volume by the attendant or the volume set by the player.

[0013] An operation panel 12 for operating the ball lending machine is provided on the right side of the upper tray 8, and includes a degree display section that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of a specified amount of game balls, and a return switch that commands the return of the card when the game ends.

[0014] As shown in Fig. 2, a guide rail 13 consisting of an outer rail and an inner rail made of metal is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in the approximate center of the guide rail 13. A movable performance body (not shown) is stored in a concealed state below the central opening HO, and during a movable advance notice performance, the movable performance body rises and becomes exposed, thereby realizing an advance notice performance with a predetermined reliability. Here, the advance notice performance is a performance that uncertainly notifies the player that a favorable jackpot state will occur, and the reliability of the advance notice performance means the probability that the jackpot state will occur.

[0015] A display device (image display means) DS consisting of a large (for example, 1280 pixels wide x 1024 pixels high) liquid crystal color display is disposed in the central opening HO. The display device DS is composed of a main liquid crystal display section MONI and an LED backlight section BL, and is a device that variably displays specific symbols (decorative symbols 164 described later) related to the jackpot state, as well as displays background images and various characters in an animated manner. This display device DS has special symbol display sections Da-Dc in the center and a normal symbol display section 19 in the upper right section. The special symbol display sections Da-Dc may execute reach effects that anticipate the arrival of a jackpot state, and appropriate advance notice effects are executed in and around the special symbol display sections Da-Dc.

[0016] In the game area where the game balls fall, there are arranged a first symbol start hole 15a, a second symbol start hole 15b, a first big prize hole 16a, a second big prize hole 16b, a normal prize hole 17, and a gate 18. Each of these prize holes 15 to 18 has a detection switch inside so that it can detect the passage of the game ball.

[0017] Above the first symbol start opening 15a, there is disposed a performance stage 14 configured so that the game ball that enters from the introduction opening IN can enter the first symbol start opening 15 after moving in a seesaw or roulette shape. When the game ball enters the first symbol start opening 15a, the special symbol display sections Da to Dc are configured to start varying.

[0018] The second pattern starting opening 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped pattern after the normal pattern display section 19 changes displays a winning pattern, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0019] The normal symbol display unit 19 displays normal symbols. When a gaming ball passing through the gate 18 is detected, the normal symbols change for a predetermined period of time and then stop displaying a stopping symbol determined by a random number value for lottery extracted at the time the gaming ball passes through the gate 18.

[0020] The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening and closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first pattern start opening 15a, and the second large prize opening 16b is configured to correspond to the second pattern start opening 15b.

[0021] In other words, when a game ball enters the first pattern start opening 15a, the special pattern display sections Da to Dc begin to change in size, and then, when a predetermined jackpot pattern is aligned in the special pattern display sections Da to Dc, a special game representing the first jackpot begins, and the sliding plate of the first large prize opening 16a opens forward, facilitating the entry of the game ball.

[0022] On the other hand, as a result of the change action started by the entry of the game ball into the second symbol start hole 15b, when a predetermined jackpot symbol is aligned in the special symbol display section Da-Dc, a special game as a second jackpot is started, and the opening and closing plate of the second big prize entry hole 16b is opened to facilitate the entry of the game ball. The game value of the special game (jackpot state) varies depending on the aligned jackpot symbols, but which game value is awarded is determined in advance based on the result of a lottery according to the timing of the entry of the game ball.

[0023] In a typical jackpot state, after the opening and closing plate of the big prize opening 16 is opened, the opening and closing plate closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered the prize. This operation continues for a maximum of, for example, 15 times, and is controlled to be in a state advantageous to the player. If the stopped pattern after the change of the special pattern display sections Da to Dc is a specific pattern among the special patterns, a special privilege is given in which the game after the end of the special game will be in a high probability state (probability state).

[0024] Fig. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the above-mentioned operations. Fig. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNT arranged on the payout control board 25. As shown in Figure 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC 24V and outputs various DC voltages (35V, 12V, 5V) along with the AC 24V, a main control board 21 that is responsible for overall game control operations, a presentation interface board 22 equipped with a digital amplifier 29 for sound presentation and the like, a presentation control board 23 that executes lamp presentation, sound presentation, and image presentation in a unified manner based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the presentation control board 23 and the display device DS, a payout control board 25 that controls the payout motor M based on the control commands CMD' received from the main control board 21 to pay out game balls, and a launch control board 26 that launches game balls in response to the player's operation.

[0025] Fig. 4 is a somewhat detailed diagram of a portion of Fig. 3(a), and shows the schematic internal configuration of the performance interface board 22, performance control board 23, and liquid crystal interface board 24. As shown in Fig. 4 and Fig. 3(a), the performance interface board 22, performance control board 23, and liquid crystal interface board 24 are directly connected to male and female connectors without going through wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made complex and advanced, the storage space of the entire board can be minimized, and noise resistance can be improved by shortening the connection lines.

[0026] As shown in Fig. 3(a), the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel in two batches of 8 bits each.

[0027] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 with built-in computer circuits such as a general performance circuit (image generating means) 52 and a built-in CPU circuit (image control means) 51. These control boards 21, 25, 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are sometimes referred to functionally as the main control unit 21, the performance control unit 23, and the payout control unit 25 in this specification. Note that the performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

[0028] This pachinko machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Fig. 3(a) and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 on the outside of that, and is fixedly installed in the game hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a change in the model, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All members except the frame side member GM1 are board side members GM2.

[0029] As shown in the dashed frame in Fig. 3(a), the frame side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are fixed to appropriate positions in the inner frame 3. Meanwhile, a main control board 21 and a performance control board 23 are fixed to the back of the game board 5 together with a display device DS and other circuit boards. The frame side member GM1 and the board side member GM2 are electrically connected by centralized connectors C1 to C3 arranged in one place.

[0030] The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

[0031] The DC 35V is used as a driving power source for the ball feed solenoid and launch solenoid in relation to the launching operation of the game ball, and as a driving power source for the electromagnetic solenoid that opens and closes the electric tulip (variable winning device) and the large winning port 16. The DC 12V is used as a driving power source for the LED lamps and motors controlled by each control board, and as a power source voltage for the digital amplifier, while the DC 5V is used as a power source voltage for the one-chip microcomputer of the payout control board 25 and the main control board 21, and as a power source voltage for the logic elements mounted on each control board. The DC 5V is also stepped down in level by the DC / DC converter of the performance interface board 22 and the performance control board 23, and the stepped down voltages of various levels are used as power source voltages for various computer circuits (such as the composite chip 50).

[0032] The backup power supply BAK is a DC 5V power supply for holding data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

[0033] On the other hand, after the power is cut off, the backup power supply BAK holds the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power is cut off after the power is turned on. Note that the backup power supply board 33 is equipped with an electric double layer capacitor that can hold the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

[0034] In this embodiment, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT is configured to have a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light, a phototransistor TR that uses a DC voltage of 5V received from the power supply board 20 as a power source and turns ON based on the light emitted by the photodiode D, and an output unit that outputs an H-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransistor TR. The photodiode D and the phototransistor TR constitute a photocoupler PH.

[0035] In the above configuration, after power is turned on, the photocoupler PH quickly turns ON, causing the power supply abnormality signal ABN to go to a normal level (H). However, if the AC power supply drops abnormally for some reason (normally due to a power cut), the photocoupler PH turns OFF, causing the power supply abnormality signal ABN to go to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the power supply abnormality signal ABN of an abnormal level executes a backup process to store necessary information in its own built-in RAM. As explained above, the information in the built-in RAM is maintained by the backup power supply BAK, so that the game operation before the power cut can be resumed after the power is turned on.

[0036] As shown in Figures 3(a) and 4, the performance interface board 22 is equipped with a reset circuit RST3 and a digital amplifier 29 (AMP), the performance control board 23 is equipped with a composite chip 50 which has built-in computer circuits such as an overall performance circuit 52 and an built-in CPU circuit 51, and the LCD interface board 24 is equipped with a clock circuit 38 (RTC), a performance data memory 39 (SRAM) which stores performance data, and a power supply control circuit SPY.

[0037] In this embodiment, the overall performance circuit 52 built into the composite chip 50 includes a video processing unit VDP (Video Display Processor), an audio processing unit SND (Audio Processor), a motor control unit MT_CTL, and a lamp control unit L_CTL. Based on the control from the built-in CPU circuit 51, the overall performance circuit 52 performs intermittent operation with an operation period δ (= 1 / 30 seconds) to perform image performance using the display device DS, audio performance driving the speaker via the digital amplifier 29, motor performance rotating the performance motors M1 to Mn to move the role objects, and lamp performance blinking LED lamps. In the following description, the built-in CPU circuit 51 may be abbreviated as the CPU circuit 51.

[0038] When the power is turned on, the reset circuit RST3 generates a power reset signal based on the rise in the power supply voltage of 5V received from the power supply circuit 20, and resets the power supply to the internal circuitry and other electronic elements of the composite chip 50. As explained above, the internal circuitry of the composite chip 50 includes a video processing section VDP (Video Display Processor) and an audio processing section SND (Audio Processor), and the power reset signal is nothing but a system reset signal SYS of the composite chip 50, which synchronously resets the power supply to the CPU circuit 51 and the overall performance circuit 52.

[0039] In this embodiment, during the L assertion period of the system reset signal SYS, all internal circuits are initialized uniformly, and default values ​​are set in the performance control register RGij of the composite chip 50. After that, when the system reset signal SYS transitions to H level, the boot program is started, and the necessary initial setting operation is performed on the performance control register RGij. On the other hand, when the DC voltage of 5V drops (usually when the power is cut off), the system reset signal SYS drops to L level, so that the CPU circuit 51 and the general performance circuit 52 of the performance control board 23 are in a stopped state.

[0040] As described later, this embodiment is configured so that the system reset signal SYS does not change even if the WDT (Watch Dog Timer) circuit 58 is activated, and all internal circuits are not initialized uniformly even in the event of an abnormality that activates the WDT 58. That is, this embodiment is configured so that a predetermined internal circuit that is arbitrarily selected is initialized.

[0041] Next, the clock circuit 38 and the performance data memory 39 mounted on the liquid crystal interface board 24 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is cut off, the timekeeping operation of the clock circuit 38 continues, and the game performance information stored in the performance data memory 39 is permanently stored and held (non-volatile).

[0042] The clock circuit 38 is configured to be able to output an interrupt signal (RTC interrupt) to the CPU circuit 51. The RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is started after a predetermined time has elapsed, but in this embodiment, an alarm interrupt IRQ_RTC that updates the daily game performance information at the end of business each day is used.

[0043] As shown in Fig. 3(a), the main control unit 21 and the payout control board 25 are each equipped with a reset circuit RST1, RST2, and are configured so that when the power is turned on, a power reset signal is generated and each computer circuit is power reset. In this way, in this embodiment, the main control unit 21, the payout control unit 25, and the performance interface board 22 are each provided with reset circuits RST1 to RST3, and for example, the system reset signal generated by the power supply board 20 is not transmitted between the circuit boards. In other words, since there is no wiring cable for transmitting the system reset signal, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

[0044] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the dispensing control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, each CPU is forcibly reset. Also, the main control unit 21 is provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25, and determines whether or not to initialize the entire area of ​​the built-in RAM of the one-chip microcomputer of each control unit 21, 25.

[0045] As shown in Fig. 3(a), the main control unit 21 receives a prize ball count signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN from the payout control unit 25. The status signal CON includes, for example, a supply out signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after the power is turned on.

[0046] The main control unit 21 also receives switch signals from detection switches built into each winning hole 16-18 on the game board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Each switch signal indicating the winning status of the symbol start hole 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0047] As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connection connector C2 (see Fig. 3(a) and Fig. 4). The 12V DC voltage is the power supply voltage for the digital amplifier 29, and is also used as the drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the play frame and is used as the drive voltage for solenoids that reciprocate movable objects.

[0048] Meanwhile, the DC voltage 5V is supplied as a power supply voltage to the circuit elements in various parts of the performance interface board 22, and is also supplied to a DC / DC converter DC to generate 3.3V (see FIG. 4). The generated DC voltage 3.3V becomes the base voltage for the power reset signal (system reset signal) SYS generated by the reset circuit RST3. The DC voltage 5V distributed to the performance interface board 22 is also distributed to the performance control board 23 together with the 3.3V generated by the DC / DC converter DC. The DC voltage 3.3V distributed to the performance control board 23 is then supplied as a power supply voltage to the composite chip 50 and external ROM 55.

[0049] As shown in Fig. 4, two DC / DC converters DC1 and DC2 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the VRAM 53 and the expansion RAM 54. Therefore, the DC voltage of 1.5V is also supplied to the VRAM 53 and the expansion RAM 54 as the power supply voltage.

[0050] As shown in Fig. 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Fig. 4, the control command CMD and the strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via an input buffer 40. Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 57 obtains the control command CMD based on an interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

[0051] 4, the input buffer 44 of the performance interface board 22 receives switch signals of the chance button 11 and the volume switch VLSW from the frame relay board 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW, and a 1-bit length indicating the ON / OFF state of the chance button 11.

[0052] The performance interface board 22 is also connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay board 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43 in FIG. 4. The input buffer 43a receives the outputs SN0 to SNn of the origin sensor that grasps the current position of the role object, which is the movable performance body (the rotational positions of the performance motors M1 to Mn), and transmits these to the motor control unit MT_CTL of the performance control board 23.

[0053] The lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers serial signals received from the lamp control unit L_CTL and the motor control unit MT_CTL of the performance control board 23 to each driver IC. The serial signals are specifically lamp (motor) drive signals SDATA and clock signals CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronous manner, and lamp performances using numerous LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn are executed.

[0054] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2, and the driver IC of the lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 output by the lamp control unit L_CTL via the frame relay board 36 in synchronization with the clock signal CK0. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 output from the CPU circuit 51 (PIO 62) changes to an active level, thereby updating the lighting state of the lamp group CH0 all at once.

[0055] The above also applies to the lamp drive board 30, and the driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 for the lamp group CH1 output from the lamp control unit L_CTL in synchronization with the clock signal CK1. Then, when the operation control signal ENABLE1 output from the CPU circuit 51 (actually the PIO 62) changes to an active level, the lighting states of the lamp group CH1 are updated all at once.

[0056] Meanwhile, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 by receiving a lamp drive signal transmitted in clock synchronous manner from the motor control unit MT_CTL, and drives the performance motor group M1 to Mn, which is composed of a plurality of stepping motors, by receiving a motor drive signal transmitted in clock synchronous manner. Since the lamp drive signal and the motor drive signal are the same type of serial signal, a series of composite serial signals SDATA2 are output from the motor control unit MT_CTL in synchronization with the clock signal CK2, and the driver IC that receives this updates the drive state of the lamp group CH2 and the motor group M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0057] In this embodiment, for the motor lamp drive board 31, the motor control unit MT_CTL is in charge of the motor performance and the lamp performance for convenience, so the operation control signal ENABLE2 is also output from the motor control unit MT_CTL. Note that the lamp drive signals SDATA0 and SDATA1 for the lamp drive board 37 and the lamp drive board 30 may also be configured to be output from the motor control unit MT_CTL.

[0058] 4, the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (Real Time Clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that when the clock circuit 38 is chip-selected by a chip select signal, the CPU circuit 51 can arbitrarily access the internal register (having a 4-bit address value).

[0059] In addition, the performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), and is connected to 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus. When the chip is selected, the game performance information and other data stored in the SRAM (performance data memory) 39 can be appropriately read / written by the CPU circuit 51.

[0060] In addition, a power supply control circuit SPY that controls the power supply to the display device DS and the backlight board BL is mounted on the liquid crystal interface board 24. Specifically, the power supply control circuit SPY controls the start timing of supplying power supply voltages of 12V and 5V to the display device DS and the backlight board BL with a control signal STBY, and controls the brightness of the backlight light and the start timing of light emission with a control signal PWM.

[0061] As shown on the right side of Figure 4, the performance control board 23 is equipped with a composite chip 50 which incorporates a CPU circuit 51 and an overall performance circuit 52, a VRAM 53 which is rapidly accessed via R / W from the CPU circuit 51 and the overall performance circuit 52, an expansion RAM 54 which can store large amounts of data, and an external ROM 55 which stores CG data and other data in a non-volatile manner.

[0062] The VRAM 53 is capable of high-speed access with a theoretical transfer speed of about 102 GB / sec, and has a storage capacity of about 48 MB. The VRAM 53 is primarily used for (1) storing reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73 (see FIG. 5(a)). It can also (2) store a copy of data in the external ROM 55, and (3) be used as a work area for the CPU circuit 51.

[0063] The expansion RAM 54 can operate at a theoretical transfer rate of about 17.0 GB / sec, has a storage capacity of about 1 GB, and can be used in the same manner as the VRAM 53. That is, the expansion RAM 54 can be used (1) to store reference data for the display circuit 71, drawing circuit 74, and GDEC circuit 73, (2) to store copies of data in the external ROM 55, and (3) as a work area for the CPU circuit 51.

[0064] The external ROM 55 in this embodiment is a non-volatile storage device that stores a boot program that starts when the power is turned on, a control program for the CPU circuit 51 that realizes performance control, control data including lamp drive data, CG compressed data for image performance, and audio compressed data for audio performance. The storage capacity of the external ROM 55 is about 256 GB at maximum, but since high-speed access is not possible, in this embodiment, a part of the data in the external ROM 55 is transferred to the extended RAM 54 when the power is turned on. Specifically, the control program and control data that operate the CPU circuit 51 are transferred and copied from the external ROM 55 to the extended RAM 54 by the boot program stored in the external ROM 55 when the power is turned on.

[0065] 5(a) is a circuit block diagram illustrating the composite chip 50 constituting the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL and a voice command list VC, and an overall performance circuit 52 that executes image performances based on the display list DL and voice performances based on the voice command list VC, as well as lamp and motor performances. The CPU circuit 51 and the overall performance circuit 52 are connected via a CPU bus unit 56 that relays data transmitted and received between them.

[0066] First, the CPU bus section 56 located between the CPU circuit 51 and the overall performance circuit 52 will be described. As shown in Fig. 5(a), the CPU bus section 56 is connected to the VRAM 53, the expansion RAM 54, and the external ROM 55 via the VRAM IF section 53a, the expansion RAM IF section 54a, and the CG bus IF section 55a. Therefore, in this embodiment, the VRAM 53, the expansion RAM 54, and the external ROM 55 can be accessed not only by the overall performance circuit 52, but also by the CPU circuit 51.

[0067] The VRAMIF section 53a, the extended RAMIF section 54a, and the CG busIF section 55a are connected to the VRAM 53, the extended RAM 54, and the external ROM 55 via an arbitration circuit ICM (Inter Connect Module) (not shown). The arbitration circuit ICM is located between each functional block of the overall performance circuit 52 and the VRAMI / F section 53a, the extended RAMI / F section 54a, and the CG busI / F section 55a, and arbitrates data requests issued by each functional block as appropriate to establish the necessary connection relationships.

[0068] In any case, the CPU circuit 51 of this embodiment can access the VRAM 53, the expansion RAM 54, and the external ROM 55. However, after the CPU circuit 51 transfers and copies the control program and control data from the external ROM 55 to the expansion RAM 54 when the power is turned on, the CPU circuit 51 does not access the external ROM 55. In other words, after the copy operation, the CPU circuit 51 executes a control operation based on the control program and control data copied to the expansion RAM 54.

[0069] This CPU circuit 51 can read / write access various performance control registers RGij to control the internal operation of the overall performance circuit 52. The data transfer circuit 70 can also transmit and receive data between the CPU circuit 51 and the overall performance circuit 52 via the CPU bus unit 56. The data transmission from the CPU circuit 51 to the overall performance circuit 52 includes the issuance of a display list DL and a voice command list VC.

[0070] As shown on the right side of Figure 5(a), the overall performance circuit 52 includes (1) a data transfer circuit 70, (2) a display circuit 71, (3) a preloader 72, (4) a GDEC (Graphic Decoder) circuit 73, (5) a drawing circuit 74, (6) an image filter circuit 75, (7) an index table IDXTBL, (8) a motor control unit MT_CTL, (9) a lamp control unit L_CTL, and (10) an audio processing unit SND, and the performance control register RGij is used to enable the CPU circuit 51 to appropriately control the internal circuits of the overall performance circuit 52.

[0071] Therefore, the performance control registers RGij are broadly divided into (1) data transfer registers, (2) display registers, (3) preload registers, (4) GDEC registers, (5) drawing registers, (6) image filter registers, (7) index table registers, (8) MT_CTL registers, (9) L_CTL registers, (10) sound registers, etc., corresponding to the above-mentioned circuits (1) to (10), and a system control register is provided for overall system control (see Figure 5(b)). Note that the system control register and each of the registers (1) to (10) for the individual circuits are actually composed of multiple register groups that are further divided.

[0072] Based on the above, the CPU circuit 51 will be described. The CPU circuit 51 is a circuit with the same performance as a general-purpose one-chip microcomputer, and as shown on the left side of Fig. 5(a), it is configured with a performance control CPU 57 that comprehensively controls image / audio / lamp / motor performance based on a control program, a watchdog timer (WDT) 58 that forcibly resets the CPU when the program goes out of control, an internal RAM 59 with a storage capacity of about 2MB that is used as a working area for the performance control CPU 57, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without passing through the performance control CPU 57, a serial input / output port (SIO) 61 with multiple input ports Si and output ports So, a parallel input / output port (PIO) 62 with multiple input ports Pi and output ports Po, and an operation control register REG in which a setting value is set to control the internal configuration of the CPU circuit 51.

[0073] For convenience, the term "input / output port" is used in this specification, but the input / output port includes an input port and an output port that operate independently in the performance control unit 23. This also applies to the input / output circuit 64p corresponding to the parallel input / output port 62 and the input / output circuit 63s corresponding to the serial input / output port 63, which will be described below.

[0074] The parallel input / output port (PIO) 62 is connected to an external device (performance interface board 22) through an input / output circuit 64p, and the performance control CPU 57 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB through the input circuit 64p. The 3-bit encoder output and 1-bit switch signal are supplied to the parallel input / output port 62 through the input / output circuit 64p.

[0075] Similarly, the received control command CMD is supplied to the parallel input / output port 62 via the input / output circuit 64p. The strobe signal STB is supplied to the interrupt terminal of the performance control CPU 57 via the input / output circuit 64p, thereby starting the reception interrupt process. Therefore, the performance control CPU 57, which has grasped the control command CMD based on the reception interrupt process, will unify the control of the sound performance, lamp performance, motor performance, and image performance corresponding to this control command CMD through a performance drawing, etc. The parallel input / output port 62 outputs the operation control signals ENABLE0 to ENABLE1 for the lamp performance via the input / output circuit 64p.

[0076] Also, the serial input / output port (SIO) 61 is configured to be able to transmit and receive serial signals via the input / output circuit 63s. Therefore, as shown by the dashed line in Fig. 5(a), a clock signal CK that realizes synchronous serial transmission and a drive serial signal SDATA can also be output via the input / output circuit 63s internally connected to the serial input / output port SIO 61. However, in this embodiment, the lamp / motor performance is realized by using the lamp control unit L_CTL and the motor control unit MT_CTL of the overall performance circuit 52 without using the serial input / output port 61.

[0077] Incidentally, a DL buffer BUF for sequentially updating and storing a display list DL in which a series of instruction commands specifying one frame of the display device DS are listed is secured in the built-in RAM 59 of the CPU circuit 51. Moreover, this DL buffer BUF is configured by partitioning areas, and also sequentially updating and storing a voice command list VC specifying the performance contents of the voice performance.

[0078] In this embodiment, the instruction commands of the display list DL that specifies one frame of the display screen include (1) an index table control command (first command) related to the index table IDXTBL that manages the index space, (2) a texture load command (first command) such as a LOADTX command for reading and decoding (decompressing / expanding) image material (texture) from the external ROM 55, (3) a filter execution command (second command) that specifies the filter processing for the decompressed image data, (4) a drawing command such as a SPRITE command for placing the image material after decoding (expanding) at a predetermined position in the virtual drawing space, (5) a pipeline command related to the drawing pipeline operation, and (6) an overall control command that specifies the overall operation of the overall performance circuit 52, all of which are configured as an integer multiple (>0) of 32 bits. The display list DL is configured to end with a predetermined end command EODL (32 bits long) after listing an appropriate number of instruction commands.

[0079] Also, the voice command list VC, which specifies the operation of the voice processing unit SND that executes the voice performance, lists an appropriate number of voice commands and then ends with a predetermined end command EOSC (32-bit length). Here, the voice commands are roughly divided into track-related commands that specify the operation of the pre-processing unit FT shown in Fig. 12(a), master effect-related commands that specify the operation of the post-processing unit BK shown in Fig. 12(a), and other system-related commands, and each voice command is composed of an integer multiple (>0) of 32 bits.

[0080] As described later, the rendering pipeline operation of this embodiment is executed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB secured as an index space, and the depth / stencil buffer, and is configured to include an input assembler process IA, a geometry engine process TL, a rasterizer process RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process RO. The above-mentioned (5) pipeline command functions as a setting command that specifies the specific operation of each process (IA, TL, RS, TX, PS, PX, RO) and the R / W position of the vertex buffer VB.

[0081] Incidentally, texture is generally a concept referring to the feel and texture of an object's surface, but in this specification, image data before and after decoding is collectively referred to as texture. For example, sprite image data that makes up a still image, frame image data that makes up one frame of a video, and pasted image data that is pasted onto drawing primitives such as triangular polygons and quadrilateral polygons are also referred to as texture.

[0082] Then, (2) the texture is read out from external ROM 55 and decoded by the LOADTX command, which is a texture load command, (5) the source image data is set to be a texture by the SETTXINDEX command, which is a texture sampler process TX command included in the pipeline commands, and (4) the texture is virtually rendered in the virtual rendering space shown in Figure 6(c) by the SPRITE command, which is a rendering command. The contents rendered in the virtual rendering space are output to the display device DS via the frame buffer FB, which will be described later.

[0083] The index space managed by the index table control command (1) above means a one-dimensional or two-dimensional memory work area (logical address space) used by the overall performance circuit 52 during drawing operations, etc. This index space is specified as a one-dimensional or two-dimensional logical address space by the index number written in the instruction command of the display list DL.

[0084] That is, in this embodiment, an index space is reserved in an appropriate location of memory (VRAM 53 and expansion RAM 54) accessible as a memory work area, and this is specified by an index number. Also, VRAM 53 and expansion RAM 54 are divided into virtual work areas (AAC area, page area, arbitrary area), and index space can be reserved for each (see FIG. 6(a) and FIG. 6(b)). Therefore, the index number becomes a unique value for each virtual work area, and texture load commands, filter execution commands, drawing commands, pipeline commands, etc. are simplified.

[0085] It also allows individual operation for each virtual work area (AAC area, page area, arbitrary area). For example, in the AAC area, index space is automatically secured as an area for expanding decoded data, and is automatically released. Therefore, index numbers are not required in the ACC area.

[0086] As a specific control operation, the virtual work area (AAC area, page area, arbitrary area) is defined in the initial processing after power-on, and the necessary index space is secured in the necessary virtual work area at the necessary timing thereafter. The secured index space is then linked to the index number and managed by the index table IDXTBL, thereby realizing operations based on the index number thereafter.

[0087] The relationship between the virtual working area and the actual working areas, which are the VRAM 53 and the expansion RAM 54, will be explained below. First, the VRAM 53 is divided into a shared area that can be used as both an AAC area and a page area, and other optional areas. Specifically, in the initial processing after power-on, an appropriate top address and area data size for the VRAM 53 are set in the corresponding performance control register RGij, thereby securing the shared area of ​​the VRAM 53. Then, areas other than the shared area secured in the VRAM 53 automatically become optional areas of the VRAM 53 (FIG. 6(a)).

[0088] The shared area secured in the VRAM 53 can be used as an ACC area that does not require management of index numbers, and as a page area that requires management of index space by index numbers. Therefore, when using a shared area, it is necessary to specify that an index space is secured in the AAC area with the SETTXINDEX command, and then specify the size and storage address of the texture (image material) with the LOADTX command, and the decompressed data of the read texture can be expanded in the index space that is automatically secured in the ACC area.

[0089] Therefore, in this embodiment, taking the above-mentioned simplicity into consideration, for still images and I stream moving images (S stream moving images composed only of I pictures, which will be described later), decoded data is developed in the AAC area of ​​the VRAM 53. That is, in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as an AAC area.

[0090] Next, in the initial processing after power-on, the top address and area data size on the expansion RAM 54 are set in the corresponding performance control register RGij, so that the page area of ​​the expansion RAM 54 is secured, and the other area becomes the arbitrary area of ​​the expansion RAM 54 (FIG. 6(b)). Here, the arbitrary area means an area in the expansion RAM 54 and the VRAM 53 that is allowed to be used arbitrarily, and not only can the index space be secured, but other uses are also possible. Therefore, in this embodiment, a preload area for pre-transferring (preloading) the CG data acquired from the external ROM 55 is secured in the arbitrary area of ​​the expansion RAM 54 (see FIG. 6(b)), and a preload buffer for storing the rewrite list DL' obtained by the preloader 72 rewriting the display list DL is secured in the arbitrary area of ​​the VRAM 53 (see FIG. 6(a)).

[0091] Furthermore, in this embodiment, the control programs and control data stored in the external ROM 55 are transferred and copied to any area of ​​the extended RAM 54 when the power is turned on (see FIG. 6(b)). Of course, all or part of the control programs and control data may be transferred and copied to the VRAM 53 instead of the extended RAM 54. Furthermore, it is not limited to the control programs and control data, and it is also possible to adopt a configuration in which all or part of CG compressed data and audio compressed data are also transferred and copied to the RAMs 53 and 54.

[0092] In any case, the index space can be appropriately allocated in the extended RAM 54 and VRAM 53 in (1) the ACC area, (2) the VRAM page area, (3) the VRAM arbitrary area, (4) the extended RAM page area, and (5) the extended RAM arbitrary area, but in this embodiment, the shared area of ​​the VRAM 53 is used exclusively as the AAC area. However, the area allocated as the shared area in the VRAM 53 can be used as both a page area and an AAC area, so the following explanation will be given with this point in mind.

[0093] When reserving an index space in the page area of ​​the VRAM 53, it is necessary to set an index number and a space size in a predetermined performance control register RGij for the VRAM. Also, the index space in the page area of ​​the extended RAM 54 is reserved by setting an index number and a space size in a predetermined performance control register RGij for the extended RAM. In this embodiment, the page area of ​​the extended RAM 54 is used to develop video frames. In addition, in the page area, the top address of the index space is appropriately determined based on internal processing, so there is the convenience of not needing to manage the top address. In other words, in the page area, when reserving an index space, there is no need to worry about overlap with an existing index space.

[0094] On the other hand, when a two-dimensional index space is reserved in an arbitrary area of ​​the VRAM 53 or an arbitrary area of ​​the extended RAM 54, it is necessary to set the index number, the top address of the index space, and the horizontal and vertical sizes of the index space in the corresponding predetermined performance control register RGij. Note that in the case of a one-dimensional index space, the vertical size is not necessary.

[0095] In this way, when the index space is reserved in an arbitrary area, the start address and size can be set in detail, and there is an advantage that the memory can be used efficiently. Therefore, in this embodiment, the frame buffer FB that completes one frame of image data for the display device DS is reserved as a two-dimensional index space in an arbitrary area of ​​the VRAM 53 (see FIG. 6(a)). It goes without saying that the frame buffer FB may also be reserved in an arbitrary area of ​​the expansion RAM 54.

[0096] The frame buffer FB allocated in any area of ​​the VRAM 53 corresponds to the drawing area of ​​a virtual drawing space that is the drawing target of drawing commands such as the SPRITE command. Figure 6(c) shows the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be set arbitrarily within the virtual drawing space, and the frame buffer FB that stores image data to be output to the display device DS.

[0097] One frame of image data for the display screen is written into the frame buffer FB by the drawing circuit 74, while one frame of image data for the display screen is read out by the display circuit 71. The frame buffer FB has a double buffer structure made up of a pair of index spaces, and is made up of a first buffer with index number N1 and a second buffer with index number N2.

[0098] For the display circuit 71, the first buffer and the second buffer are read-out areas for image data, and the image data in the first buffer and the second buffer are read out in sequence for each operating period δ by toggling the index numbers N1 / N2 based on the embedded information in a specified display register RGij.

[0099] On the other hand, for the drawing circuit 74, the first buffer and the second buffer are write areas for image data, and image data is written alternately to the first buffer and the second buffer by toggling the index numbers N1 / N2 for each operating period δ based on the instruction command on the display list DL.

[0100] The writing operation of the drawing circuit 74 corresponds to the reading operation of the display circuit 71, so that image data written to the first buffer in one operation cycle is read by the display circuit 71 in the next operation cycle, and in the operation cycle in which the image data in the first buffer is read, the drawing circuit 74 writes image data to the second buffer. Subsequent operations are the same, and the first buffer and the second buffer are used alternately as the "writing area" and the "reading area".

[0101] In this embodiment, index spaces secured in any area of ​​the VRAM 53 or the extended RAM 54 are used as general working spaces other than the frame buffer FB and the decompression space for compressed data. These various index spaces can be secured when necessary and released when not necessary, but when an index space is secured / released, the contents of the index table IDXTBL, which stores the index space in association with the index number, are updated, enabling subsequent consistent operation.

[0102] The index space and the CPU circuit 51 have been explained above. Next, the overall performance circuit 52 will be explained.

[0103] The overall presentation circuit 52 includes (1) various presentation control registers RGij, whose internal operation is determined by the presentation control CPU 57; (2) a data transfer circuit 70 that transmits and receives data between circuits inside and outside the chip; (3) an index table IDXTBL that manages an index space, which is a working area secured in the VRAM 53 and the expansion RAM 54; (4) a preloader 72 that can perform a preload operation to access the external ROM 55 for reading prior to a drawing operation; and (5) a Graphic Decoder (GDEC) circuit that decodes compressed data for image presentation read from the external ROM 55. ) 73, (6) a drawing circuit 74 that generates one frame of image data for the display device DS in a frame buffer FB by appropriately combining the decoded still image data and video data, (7) a plurality of display circuits 71 that reads the image data generated by the drawing circuit 74 in the frame buffer FB and outputs the image data after appropriate image processing, (8) an output selection unit 76 that appropriately selects and outputs the output of the plurality of display circuits 71, (9) an output unit 77 that converts the image data output by the output selection unit 76 into an LVDS signal or the like and outputs the converted signal, (10) a voice processing unit SND that executes voice effects based on a voice command list VC, (11) a motor control unit MT_CTL that executes motor effects, and (12) a lamp control unit L_CTL that executes lamp effects (see FIG. 5(a)). The voice processing unit SND includes a voice decoder that decodes compressed data for voice effects read from the external ROM 55.

[0104] The motor performance is executed based on the control operation of the performance control CPU 57, specifically, based on the set value of the performance control register RGij for the motor performance and the control data (motor drive data) copied to the expansion RAM 54. The lamp performance is also executed based on the control operation of the performance control CPU 57, specifically, based on the set value of the performance control register RGij for the lamp performance and the control data (lamp drive data) copied to the expansion RAM 54.

[0105] 5(b) illustrates the relationship between the CPU bus unit 56, the CG bus IF unit 55a, the extended RAM IF unit 54a, and the VRAM IF unit 53a, and the performance control register RGij, the external ROM 55, the extended RAM 54, and the VRAM 53. As illustrated, the CG compressed data acquired from the external ROM 55 is supplied to the GDEC circuit 73 via the CG bus IF unit 55a and the data transfer circuit 70, and the decompressed (decoded) data is expanded in a predetermined index space secured in the extended RAM 54 or the VRAM 53.

[0106] As described above, in this embodiment, an ACC area for developing still images is reserved in the VRAM 53, and a page area for developing video frames is reserved in the expansion RAM 54. Then, decoded data of still images and videos is developed in a predetermined index space of the ACC area / page area. Note that decompressed data of compressed CG data acquired from the external ROM 55 may be transferred to the preload area of ​​the expansion RAM 54 as preload data.

[0107] Next, the display circuit 71 will be described with reference to Fig. 7. The display circuit 71 is a circuit that reads image data from the frame buffer FB in synchronization with the dot clock DCK, performs final image processing, and outputs the data. The final image processing includes, for example, a scaling process of a scaler that enlarges / reduces the image to a similar shape, a subtle color correction process, and a dithering process that minimizes the quantization error of the entire image. These image processes are uniformly executed based on the setting value of the performance control register RGij (display register). Then, the digital RGB signal that has undergone the uniform image processing is output together with a horizontal synchronization signal, a vertical synchronization signal, and the like.

[0108] As shown in Fig. 7, three display circuits A / B / C are provided that perform the above operations in parallel, but in this embodiment, since there is only one display device, only a frame buffer FB (=FBa) is reserved for the display circuit A. However, if frame buffers FBa to FBc are reserved, it is also possible to drive two other display devices that can perform independent image presentations.

[0109] Next, returning to Fig. 5(a), the data transfer circuit 70 will be explained. The data transfer circuit 70 is a circuit that executes data transfer operations between the internal resources of the overall performance circuit 52 and the external storage medium as the transfer source and transfer destination in a DMA (Direct Memory Access) manner. Fig. 8 is a block diagram showing the internal configuration of this data transfer circuit 70 together with the related circuit configuration.

[0110] The transfer sources of the data transfer circuit 70 in this embodiment include the CPU address space via the CPU bus unit 56, the external ROM 55, the expansion RAM 54, and the VRAM 53, as well as the CPU register port PORT. On the other hand, the transfer destinations of the data transfer circuit 70 include the CPU register port PORT, as well as the CPU address space, the expansion RAM 54, the VRAM 53, the checksum circuit, the drawing circuit 74, the preloader 72, and the audio processing unit SND.

[0111] Here, the CPU address space means a storage area accessible by the performance control CPU 57. The CPU register port PORT is a 32-bit register connected to the CPU bus section 56, and the performance control CPU 57 can arbitrarily access it via R / W.

[0112] Moreover, virtual work areas such as page areas and arbitrary areas are defined in the expansion RAM 54 and VRAM 53, and index spaces specified by index numbers are secured / released within these virtual work areas, so that the operation of the data transfer circuit 70 is executed by referring to an index table IDXTBL that stores the relationship between the index spaces and real address spaces. The index spaces secured in the expansion RAM 54 or VRAM 53 can also be set as the data transfer source or data transfer destination of the data transfer circuit 70. Therefore, data of the frame buffer FB secured in an arbitrary area of ​​the VRAM 53 can also be transferred to the expansion RAM 54.

[0113] 8, the transfer size that the data transfer circuit 70 can transfer is 32 bits x (01h to 4000_0000h) when passing through the data relay units CH0 to CH1, and 32 bits x (01h to 100_0000h) when passing through the data relay units CH2 to CH4. That is, the data transfer circuit 70 of this embodiment can transfer data of any size that is an integer multiple of 32 bits, although there is a predetermined upper limit. Here, h means a hexadecimal number, and the upper limit of the transfer size is specifically 32 x 1,073,741,824 bits when passing through the data relay units CH0 to CH1, and 32 x 16,777,216 bits when passing through the data relay units CH2 to CH4.

[0114] 8, the data transfer circuit 70 is configured to receive necessary data from the external ROM 55 via an arbitration circuit ICM that has a router function and arbitrates access paths, and to transmit and receive necessary data to and from the VRAM 53 and the extended RAM 54. The external ROM 55, VRAM 53, and extended RAM 54 are accessed via a CG bus IF unit 55a, a VRAM IF unit 53a, and an extended RAM IF unit 54a.

[0115] This data transfer circuit 70 is composed of a 32-bit x 130-stage CPU data FIFO (First In First Out) circuit connected to a 32-bit CPU register port PORT, and five channel data relay units CH0 to CH4. As explained above, the CPU register port PORT is configured to be R / W accessible from the performance control CPU 57.

[0116] The data relay unit CH0 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages and a checksum circuit. Each of the data relay units CH1 to CH4 is composed of a CH0 data FIFO circuit of 1024 bits x 18 stages. The data relay units CH2 to CH4 are connected in one direction to the drawing circuit 74, the preloader 72, and the sound processing unit SND.

[0117] On the other hand, the CPU data FIFO circuit and the data relay units CH0-CH1 are configured to be capable of bidirectional communication, so that a predetermined amount of data set in the data transfer register is transmitted and received from a predetermined transfer source set in the data transfer register to a predetermined transfer destination set in the data transfer register via the CPU data FIFO circuit or the data relay units CH0-CH1.

[0118] Regardless of which path is taken among the data relay units CH0 to CH4, the amount of data to be transferred (transfer data size) must be set in 32-bit units as described above, and there are also certain limitations on the start addresses of the transfer source and destination. Specifically, the start addresses of the transfer source and destination must be set in 8-bit units in the CPU address space, and in 32-bit units in the VRAM 53 and expansion RAM 54. The transfer source start address in the external ROM 55 is also set in 32-bit units.

[0119] When passing through the data relay units CH0-CH1, the transfer source and / or transfer destination is the external ROM 55, the VRAM 53, or the expansion RAM 54, and when passing through the CPU data FIFO circuit connected to the CPU register port PORT, the transfer source or transfer destination is the CPU address space. The CPU address space naturally includes the built-in RAM 59.

[0120] The data relay units CH0-CH1 capable of bidirectional communication have been described above, but the data relay units CH2-CH4 form one-way communication paths. The performance control CPU 57 can transmit the display list DL and voice command list VC in the DL buffer BUF of the built-in RAM 59 one-way to the data relay units CH2-CH4 by write accessing the CPU register port PORT in 32-bit units via the CPU bus unit 56.

[0121] In addition, the internal RAM 59 can also be selected as the data transfer source, so that data can be transferred via the data relay units CH2 to CH4 (without going through the CPU register port PORT) with the DL buffer BUF as the data transfer source and the drawing circuit 74, the preloader 72, or the audio processing unit SND as the data transfer destination.

[0122] In this case, the start address of the data transfer source built-in RAM 59 is specified in 8-bit units, so the lowest 7 bits of the start address of the DL buffer BUF must be 0. Also, regardless of whether the data is transferred via the CPU register port PORT or not, the amount of data to be transferred (data transfer size) must be set in 32-bit units.

[0123] In any case, the data relay unit CH2, the data relay unit CH3, and the data relay unit CH4 are unidirectionally connected to the drawing circuit 74, the preloader 72, and the voice processing unit SND, respectively. Therefore, a display list DL of a predetermined data transfer size is transferred to the drawing circuit 74 via the data relay unit CH2, and to the preloader 72 via the data relay unit CH3. Also, a voice command list VC of a predetermined data transfer size is transferred to the voice processing unit SND via the data relay unit CH4.

[0124] As described above, in this embodiment, the transfer paths of the display list DL and the voice command list VC are prepared as follows: (1) a first path that passes through the CPU register port PORT; and (2) a second path that does not pass through the CPU register port PORT; either of these can be used. The same is true for other data; there is (1) a first path that passes through the CPU register port PORT and data relay units CH0 to CH4; and (2) a second path that passes only through the data relay units CH0 to CH4. The first path is used for data transfers in which the performance control CPU 57 is directly involved, and the second path is used for data transfers in which the performance control CPU 57 is not directly involved (DMA operation).

[0125] 8, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, when the first path is used, when 1024-bit data is accumulated in the CPU data FIFO circuit, the accumulated data is transferred to one of the data relay units CH0 to CH4 (hereinafter referred to as a channel data FIFO).

[0126] That is, if data less than 32 stages is written to the CPU data FIFO circuit, the data transfer to the channel data FIFO does not occur, and when the 32nd stage data is written, the 32nd stage of accumulated data is transferred to the channel data FIFO, and the data is further transferred to the next destination. On the other hand, since the data transfer size is an arbitrary value that is an integer multiple of 32 bits, the data in the CPU data FIFO circuit may end up less than 32 stages, but when the cumulative size of the written data reaches the transfer size previously set in the data transfer register, the accumulated data less than 32 stages will be transferred to the channel data FIFO and the next destination.

[0127] Thus, in this embodiment, the transfer size of the data transfer circuit 70 is an arbitrary value of an integer multiple of 32 bits, regardless of whether the transfer is via the first path or the second path. The instruction commands constituting the display list DL and the voice commands constituting the voice command list VC are all composed of an integer multiple of 32 bits. Therefore, in this embodiment, there is no restriction on the number of commands in the display list DL or the voice command list VC, and any list configuration can be adopted. Also, there is no need to adjust the total data size by adding dummy commands, etc.

[0128] 9A shows the operation of transferring the display list DL to the drawing circuit 74 via the CPU register port PORT and the data relay unit CH2 (FIG. 9A), the operation of transferring the display list DL from the internal RAM 59 to the drawing circuit 74 via the data relay unit CH2 (FIG. 9B), and the operation of transferring a rewrite list DL', which is a modified display list, from the VRAM 53 to the drawing circuit 74 via the data relay unit CH2 (FIG. 9C).

[0129] Figures 9(d) and 9(e) show the operation of transferring a display list DL to the preloader 72 via the CPU register port PORT and the data relay unit CH3, and the operation of transferring a display list DL from the internal RAM 59 to the preloader 72 via the data relay unit CH3.

[0130] Also, Figures 9(f) and 9(g) show the operation of transferring the voice command list VC to the voice processing unit SND via the CPU register port PORT and the data relay unit CH4, and the operation of transferring the voice command list VC from the built-in RAM 59 to the voice processing unit SND via the data relay unit CH4.

[0131] The CPU circuit 51 starts the operations of the drawing circuit 74, the preloader 72, and the sound processing unit SND prior to the start of operation of the data transfer circuit 70, so that the drawing circuit 74 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 72 executes necessary preload operations based on the transferred display list DL. The transferred display list DL is judged by a display list analyzer built into the drawing circuit 74 and the preloader 72, and processing according to the type of instruction command is executed. Also, the sound processing unit SND starts or progresses sound performance based on the transferred sound command list VC.

[0132] Note that data other than the display list DL and the voice command list VC in the CPU address space can be transmitted to the data relay units CH0 to CH4 via the CPU bus unit 56, and then further via the CPU register port PORT, or directly. The data relay units CH0 to CH1 then transfer the transmitted data to a predetermined destination in the VRAM 53 or the expansion RAM 54 via the arbitration circuit ICM. The reverse transfer operation is similar, and the data relay units CH0 to CH1 that receive data via the arbitration circuit ICM transfer the data to a predetermined destination in the CPU address space via the CPU register port PORT, or directly.

[0133] Next, the preloader 72 will be described, but it is optional whether or not to utilize the preloader 72. When the display list analyzer interprets the display list DL transferred from the data relay unit CH3 of the data transfer circuit 70 and detects a LOADTX command, the preloader 72 pre-transfers (preloads) the CG data in the external ROM 55 referenced by the LOADTX command to the preload area of ​​the expansion RAM 54 (see FIG. 6(b)).

[0134] Furthermore, the preloader 72 stores a rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer in the DL buffer BUF' (see FIG. 6(a)) of the VRAM 53 in response to the above-mentioned LOADTX command. Note that the DL buffer BUF' and the preload area are secured in advance during the initial processing after the CPU is reset.

[0135] The rewrite list DL' is then transferred to the drawing circuit 74 via the arbitration circuit ICM and data relay unit CH2 of the data transfer circuit 70 when the drawing operation of the drawing circuit 74 begins (see FIG. 9(c)). The drawing circuit 74 then executes the drawing operation based on the rewrite list DL'. Therefore, CG data that should normally be obtained from the external ROM 55 based on a LOADTX command or the like is quickly obtained from the preload area of ​​the expansion RAM 54 as preload data that has been pre-read into the preload area. Taking this into consideration, the preloader 72 is put into operation in a normal device configuration.

[0136] In this embodiment, since the preload area is set in the external expansion RAM 54, which has a sufficient storage capacity, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. In other words, multiple preloading is realized by appropriately setting the operation period of the preloader 72, which is a series of preloading operations including the CG data prefetching operation, within the range of an integer multiple of the operation cycle δ of the overall performance circuit 52 during intermittent operation.

[0137] However, in the following explanation, for the sake of convenience, an embodiment without multiple preloading will be explained, so the preloader 72 of the embodiment will complete the preloading operation for one frame during one operation period 6. In this embodiment, the operation period 6 during intermittent operation of the overall performance circuit 52 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS.

[0138] Next, the drawing circuit 74 sequentially analyzes the instruction command sequence of the display list DL and the rewrite list DL' transferred via the data transfer circuit 70, and works together with the GDEC circuit 73 and the geometry engine to draw one frame's worth of image of the display device DS in the frame buffer FB secured in the VRAM 53.

[0139] As described above, when the preloader 72 is operated, the CG data in the rewrite list DL' is referenced not to the external ROM 55 but to a preload area set in the expansion RAM 54. Therefore, sequential access to the CG data that occurs during the execution of drawing by the drawing circuit 74 can be quickly executed, and high-resolution moving images with fast movement can be drawn without any problems.

[0140] Incidentally, regardless of whether the preloader 72 is enabled or disabled, even if data bit corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 74 cannot detect this. Therefore, in this embodiment, a timeout monitoring circuit having a configuration similar to that of a watchdog timer is provided to detect an abnormality in which memory access is not performed for a certain period of time after the drawing circuit 74 starts operating.

[0141] In order to detect an operational abnormality of the drawing circuit 74, this embodiment is provided with a time setting register (predetermined register) TO that can arbitrarily set a timeout time (abnormality determination time). The time setting register TO is a type of drawing register, and the operation of the drawing circuit 74 is configured to be started based on a set value in the predetermined drawing register (drawing operation permission / prohibition register).

[0142] When a predetermined timeout time is set in the time setting register TO and start information is set in the drawing operation permission register, the drawing circuit 74 starts operation, and in response, the timeout monitoring circuit (monitoring means) monitors the memory access period (memory access time interval). If no memory access is performed even after the timeout time has elapsed, an abnormality flag in a predetermined drawing register is set ON and an abnormality interrupt is initiated.

[0143] Although it is possible to deal with this abnormal interrupt by starting an interrupt processing program, in this embodiment, the appearance of an abnormal screen is prevented by checking the ON / OFF state of the abnormal flag for each operation cycle δ of the overall performance circuit 52. Specifically, when the abnormal flag is ON, even if the operation of the drawing circuit 74 has been completed, the screen update for that operation cycle is skipped.

[0144] Here, as in the configurations of Patent Documents 1 and 2, if a measure to activate the WDT 58 or a measure to reset the drawing circuit 74 is taken, there is a risk of an unnatural screen display appearing, but in this embodiment, the appearance of an abnormal screen is easily prevented with a minimum of measures. Also, the timeout period to be monitored can be set arbitrarily taking into consideration the arrangement of the LOADTX command in the display list DL, the access time of the external ROM 55, etc., and therefore an optimal monitoring operation can be realized.

[0145] In the above configuration, the memory access cycle is monitored from the start of operation of the drawing circuit 74 to its end, but instead of or in addition to this configuration, it is also preferable to adopt a configuration that monitors the operation time from the start of operation of the GDEC circuit 73 to its end. In this case, too, an optimal value can be set in the time setting register TO' taking into account the data capacity of the texture, thereby achieving optimal monitoring operation.

[0146] In the latter configuration, the timeout monitoring circuit starts monitoring each time the GDEC circuit 73 starts decoding the CG compressed data, and ends the monitoring operation at the end of the decoding. In addition, as in the former configuration, when a timeout occurs, the abnormality flag of a specified drawing register is set ON and an abnormality interrupt is started, and when an abnormality is detected, screen updates in that operation cycle are skipped. In this embodiment, a flag polling method is adopted in which the ON / OFF state of the abnormality flag is checked every operation cycle δ of the overall performance circuit 52, but a configuration in which an abnormality interrupt processing program is started and screen updates in the operation cycle in which a problem occurs may also be adopted.

[0147] Next, the image filter circuit 75 is a circuit that functions based on instruction commands (filter execution commands) written in the display list DL, and executes appropriate filter processing on textures temporarily stored in the VRAM 53 or the expansion RAM 54. That is, the image filter circuit 75 of the embodiment does not perform a uniform filter operation based on the setting value in the performance control register RGij, but rather enables free filter processing on required image data by arbitrarily writing appropriate instruction commands in the display list DL.

[0148] The content of the filter processing is determined by the selection of a filter execution command and the setting parameters of the selected command, but the executable filter processing includes (1) FIR (Finite Impulse Response) filter processing, (2) downsampling processing, and (3) linear interpolation processing. Here, the downsampling processing is a process different from the scaling processing in the display circuit 71 that operates based on the setting value in the performance control register RGij (display register).

[0149] That is, downsampling does not reduce an image to a similar shape as in scaling, but includes an operation of reducing an image only in the vertical direction or only in the horizontal direction. Although not limited to this, downsampling reduces the texture by calculating the average value of the image information of pixels in a predetermined range surrounding the target pixel and performing a thinning process such as a moving average process.

[0150] 10(a) is a diagram for explaining an example of an operation in which FIR filter processing is executed twice in succession by a filter execution command. First, the SETFTINDEX command sets the destination index space in which the reference texture to be filtered should be saved (command process L20), and then the LOADTX command retrieves the reference texture from the external ROM 55 specified by the command setting parameters, and saves the decoded image data in the destination index space (command process L21).

[0151] The following SETFTINDEX command sets the index space in which the resultant texture will be saved (command process L22), and the SETFTSAMP command and SETFTCOEF command set filter coefficients and other information (command process L23), before executing FIR filter processing with the FTEXECFIR command (command process L24).The SETFTINDEX command distinguishes between specifying an index space for the reference texture or an index space for the resultant texture, depending on the setting parameters of the command.

[0152] As shown in Figure 10(b), the image data expanded in the index space for the reference texture specified by the instruction command L20 is subjected to FIR filtering processing specified by the instruction command L23, and then stored in the index space for the result texture specified by the instruction command L22.

[0153] Next, the SETFTINDEX command sets the index space of the reference texture (command process L25), and the SETTXINDEX command sets the index space in which the resultant texture is to be saved (command process L26). In command L25, the image data after the filter process is set as the reference texture, so the resultant texture specified by command L22 is changed to the reference texture by command L25.

[0154] Thereafter, the necessary filter coefficients are set using the SETFTSAMP and SETFTCOEF commands, and other information is set (command process L27), after which the necessary FIR filter processing is executed using the FTEXECFIR command (command process L28).The image data after filter processing is then stored in the index space specified by command L26, so by executing the SPRITE command after functioning the SETTXMODE command (command process L29), the image data that has undergone FIR filter processing will be drawn in an appropriate rectangular section in the virtual drawing space.

[0155] 10(c) is a diagram for explaining an example of an operation in which scaling processing is executed by a filter execution command. First, a SETFTINDEX command is used to set a storage index space in which to store the reference texture to be scaled (command process L30), and then a LOADTX command is used to obtain the reference texture from the external ROM 55 specified by the setting parameters of the command (command process L31).

[0156] Next, the SETTXINDEX command is used to set an index space for storing auxiliary data required for enlargement / reduction (command process L32). Here, the auxiliary data is plane information extracted from the reference texture, and is information that characterizes the reference texture. The reason why such auxiliary data is an issue is that the scaling process of the embodiment includes deformations of dissimilar shapes that are not similar shapes, and therefore appropriate complementation processes are performed to eliminate the unnaturalness of the image after deformation.

[0157] Therefore, in the scaling process of this embodiment, following command L32, the FTEXECGRD command is written to generate auxiliary information (plane information) in the index space defined by command L32 (command process L33). The necessary preparations are completed with the commands up to this point, so next, the index space to be used as the texture is set with the SETTXINDEX command (command process L34), and the necessary information is set with the SETTXSAMP command, after which the scaling process is executed with the SETTXMODE command (command process L35).

[0158] As a result of the above, the image data after scaling is stored in the index space specified by command L34, so by executing the SPRITE command after activating the SETTXMODE command (command process L36), the image data after scaling is drawn in an appropriate rectangular section of the virtual drawing space.

[0159] The image filter circuit 75 has been described above, but the GDEC circuit 73 executes decoding processing by software processing corresponding to each compression algorithm for compressed data such as streaming video, still images, and other α values. In the case of this embodiment, streaming video is divided into S stream, IP stream, and IPB stream, and the frames constituting the streaming video are composed of an appropriate combination of I pictures, S pictures, P pictures, or B pictures.

[0160] An I (Intra coded) picture means an intra (intra-picture) coded picture, and refers to image data obtained by compressing an input picture as it is, independent of other pictures. On the other hand, an S picture is image data that performs predictive coding by referring to the I pictures immediately before and after, and has the advantage of having a higher compression rate than an I picture. The S stream video of this embodiment is a video combining these I pictures and S pictures, and by arranging the I pictures according to a certain period, it is possible to perform random access and reverse playback starting from the I picture, thereby realizing effective image presentation. It is also possible to have an S stream video that does not include an S picture, and an S stream video without an S picture is substantially the same as an I stream video.

[0161] Next, a P picture (Predictive coded) is image data that performs forward predictive coding to predict the current frame from a past frame in time, and predictive coding is performed from an I picture or P picture located in the past in time. On the other hand, a B picture (Bidirectional coded) is image data that performs bidirectional predictive coding to execute backward prediction to predict the current frame from a future frame in addition to forward prediction, and predictive coding is performed from an I picture or P picture located in the past and future in time.

[0162] Generally, inter-frame prediction techniques include forward prediction, which predicts the current frame from a past frame, backward prediction, which predicts the current frame from a future frame, and bidirectional prediction, which performs backward prediction in addition to forward prediction.B pictures perform bidirectional prediction, which allows for improved prediction accuracy.

[0163] Therefore, in this embodiment, in addition to S stream video that combines I pictures and S pictures, it is configured to be possible to play IP stream video and IPB stream video that appropriately combine I pictures, P pictures, and B pictures. Note that IP stream video is composed of a combination of I pictures and P pictures, and IPB stream video is composed of a combination of I pictures, P pictures, and B pictures.

[0164] As is clear from the above relationship, with S stream video containing S pictures and IPB stream video, the need for backward predictive coding makes it necessary to acquire and decode I pictures and P pictures that are to be played back later in time prior to acquiring S pictures and B pictures.

[0165] Therefore, this embodiment is configured so that one LOADTX command can specify multiple textures, that is, main frame CG data and sub-frame CG data. Here, main frame refers to CG frame data that should be played back at the current timing, and sub-frame refers to CG frame data that should be played back at a different timing.

[0166] For example, in an S picture, predictive coding is performed by referring to the nearest I picture (the previous or next). Therefore, in an S stream video that consists of successive I pictures and S pictures, the CG data for the S picture as the main frame and the I picture as the sub-frame may be obtained and decoded with a single LOADTX command.

[0167] In addition, since bidirectional predictive coding is performed for B pictures (bidirectional coded), it is necessary to secure CG data of past frames and CG data of future frames in a decoded state prior to the decoding process of B pictures. Therefore, in this embodiment, when playing IPB stream video, it is necessary to secure a first reference buffer for storing past frames and a second reference buffer for storing future frames prior to this playback operation. The reference buffer is an index space having a capacity sufficient to store reference images, and is secured in an arbitrary area of ​​the VRAM 53 or the extended RAM 54, and is identified by a unique index number.

[0168] Fig. 11 is a diagram explaining the playback procedure of IPB streaming video, with the playback operation progressing from the top to the bottom of the page. Fig. 11 is divided horizontally into six sections, which show, from the left, (1) the LOADTX command on the display list DL, (2) pictures constituting the IPB streaming video, (3) main frame and subframe decoding processing, (4) reference image decoding processing, (5) reference buffer where the reference images are stored, and (6) index space (expansion space) where the decoded images displayed on the display screen are stored.

[0169] The downward arrow in the first column indicates the transition of the operation cycle of the general performance circuit 52 (GDEC circuit 73) which operates intermittently, and the downward arrow in the sixth column indicates the display order of the images displayed on the display device DS. In the following explanation, for convenience, a group of video frames played at timings T1 to T7 is called a GOP (Group Of Picture), but the GOP can be changed appropriately based on the embedded parameters of the LOADTX command on a series of display lists for video playback.

[0170] First, the LOADTX command at timing T1 to play back an I-picture specifies the addresses of the I-picture (I1) as the main frame and the P-picture (P1) as the sub-frame by the embedded parameters of the command, as well as the index number of the expansion space in which the decoded data is to be stored.

[0171] Therefore, the I-picture (I1) acquired based on the instruction of the LOADTX command at timing T1 is decoded and stored in the first reference buffer that stores past frames together with the original expansion space. Also, a P-picture (P1) is acquired based on the instruction of the LOADTX command at timing T1, and the decoded data is stored as a reference image in the second reference buffer that stores future frames. Although not limited to this, the reference image is stored in a state compressed by a special method.

[0172] Next, the LOADTX command at timing T2 specifies only the B picture (B1) as the main frame. Then, as a bidirectional predictive operation, image data B1 of the current frame is reproduced based on the I picture (I1) of the first reference buffer, the P picture (P1) of the second reference buffer, and the B picture (B1) and stored in the storage space. The same is true for the LOADTX command at the following timing T3, which reproduces image data B2 of the current frame based on the I picture (I1) of the first reference buffer, the P picture (P1) of the second reference buffer, and the B picture (B2) and stored in the storage space.

[0173] Next, in the LOADTX command at timing T4 when the P picture is to be played back, the embedded parameters of the command instruct that the P picture (P1) as the main frame should be obtained from the second reference buffer, and the address of the P picture (P2) as the subframe is specified.

[0174] Therefore, at timing T4, the P picture (P1) in the second reference buffer, which has been compressed using a special method, is decompressed and saved in the decompression space, and the P picture (P1) is stored in the first reference buffer as a past frame image for subsequent processing. Also, a future P picture (P2) is obtained in response to an instruction from the LOADTX command at timing T4, and the decoded data is saved in the second reference buffer as a reference image for the future frame.

[0175] The operations at the subsequent times T5 and T6 are substantially the same as those at the times T2 and T3. That is, at the time T5, a B3 picture image based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B3) is rendered in the rendering space based on the bidirectional prediction. At the time T6, a B4 picture image based on the P picture (P1) of the first reference buffer, the P picture (P2) of the second reference buffer, and the B picture (B4) is rendered in the rendering space.

[0176] Next, the LOAD command at timing T7 instructs that the P picture (P2) as the main frame should be obtained from the second reference buffer. Also, the address of the I picture (I2) as the sub-frame is specified. Therefore, at timing T7, the P picture (P2) in the second reference buffer is decompressed and stored in the expansion space, and the I picture (I2) is obtained by the instruction of the LOADTX command at timing T7, and the decoded data is stored in the second reference buffer as a reference image for a future frame.

[0177] At the next timing T9, an instruction is given to obtain an I-picture (I2) as a main frame from the second reference buffer. Therefore, the I-picture (I2) in the second reference buffer is decompressed and saved in the expansion space, and the I-picture (I2) is stored in the first reference buffer as a past frame image for subsequent processing. Note that the LOAD command at timing T9 specifies the address of the P-picture (P3), which is a subframe, so the P-picture (P3) is obtained and its decoded data is saved in the second reference buffer as a reference image for a future frame.

[0178] 12(a) is a block diagram showing the internal configuration of the audio processing unit SND. As shown in the figure, the audio processing unit SND is divided into a pre-processing unit FT in which 64-track processing blocks are arranged so as to be able to operate in parallel, a post-processing unit BK consisting of a master effect unit, a master volume unit, an output protection unit, and a serializer, and a mixer MX that transmits the output of the pre-processing unit FT to the post-processing unit BK.

[0179] As shown in the figure, the pre-processing unit FT is provided with 64 decoders that receive audio compression data (compressed phrase data) from the external memory 55. Meanwhile, the post-processing unit BK is configured to be able to output audio signals SDOUTA-SDOUTD of four paths A / B / C / D as serial data together with a clock signal SBCLK and a control signal SLRCLK via a serializer. The serial data SDOUTA-SDOUTD of the four paths A / B / C / D includes right data R and left data L on each data line, and depending on whether the control signal SLRCLK is in an H level period or an L level period, it is specified whether the serial data SDOUTA at that timing is left data L or right data R.

[0180] Next, the internal operation of the preprocessing unit FT will be explained. The phrase data decompressed by the decoder has its volume appropriately adjusted in the primary volume, secondary volume, and panpot unit. Here, the primary volume and secondary volume are responsible for two-stage volume adjustment, and the panpot unit adjusts the volume ratio between the left and right speakers. The specific operation contents of the primary volume, secondary volume, and panpot unit are each specified by the voice command written in the voice command list VC.

[0181] Incidentally, phrase data is audio data that realizes one unit of audio performance, and includes one piece of background sound, sound effects, calls, and other audio performance units. One phrase data is output to eight paths from the panpot section of the pre-processing section FT. As shown in the figure, in this embodiment, 64-track processing blocks (pre-processing sections FT) are arranged to be able to operate in parallel, and up to 64 phrase data can be output to the mixer MX, and the audio data collected into eight paths, which are the left and right audio R / L of the four paths A / B / C / D, is transmitted to the post-processing section BK.

[0182] In the panpot section, the volume ratio of the left and right speakers can be adjusted, so for example, in the panpot section of the first track, the left and right volume ratio can be set to maximum:zero and output only to the first line of the mixer MX, while in the panpot section of the second track, the left and right volume ratio can be set to zero:maximum and output only to the second line of the mixer MX. Therefore, for example, the first phrase data, which is the left audio, is output only to the first line, and the second phrase data, which is the right audio, is output only to the second line, making it possible to play in stereo on the left and right speakers of system A.

[0183] Next, the internal operation of the post-processing unit BK will be described. The master effect executes audio filter processing, and the master volume determines the final volume. The specific operation contents are specified by the voice commands written in the voice command list VC. The master volume is used, for example, for a silent warning that instantly silences the volume effect, and the master effect is used, for example, for a sound change warning that drastically changes the sound quality.

[0184] Fig. 12(b) illustrates the relationship between the voice command list VC and the voice effects realized by the voice commands written in the voice command list VC. Here, a START command for instructing the start of playback of specific phrase data, a PAUSE command for instructing the stop of playback of specific phrase data, a RESUME command for instructing the restart of playback of specific phrase data, and a STOP command for instructing the end of playback of specific phrase data are shown as examples. Note that the voice command list VC is composed of one or more voice commands written therein, but must be terminated by a predetermined end command EOSC.

[0185] First, in the voice command list VC1, the start of reproduction of 64 types of phrase data is instructed by voice commands START1 to START64. Therefore, when the decoding process of the 64 types of compressed phrase data is completed, the reproduction operation of the 64 types of phrase data is started.

[0186] Next, since the voice command list VC2 contains the voice commands PAUSE1, PAUSE2, and STOP64, playback of the phrase data 1, 2, and 64 is paused or stopped. After that, the voice command list VC3 contains the voice commands RESUME1 and RESUME2, so playback of the paused phrase data 1 and 2 is resumed.

[0187] The voice command list VC can be output not only at the start and end of playback of phrase data, but also at any necessary timing in the operation period δ (= 1 / 30 seconds) of the overall performance circuit 52. That is, the display list DL is output every operation period δ of the overall performance circuit 52, but the voice command list VC is generally output irregularly.

[0188] Next, a description will be given of the rendering pipeline process executable in the rendering circuit 74. Fig. 13(a) illustrates a portion of the rendering circuit 74 that is related to the rendering pipeline process. The display list analyzer sequentially analyzes the instruction commands written in the display list DL, and transfers the instruction commands to an appropriate internal circuit according to their type. Note that in Fig. 13(a), the instruction commands are particularly written as rendering commands, and in the following description, the instruction commands may be referred to as rendering commands.

[0189] The internal circuits that receive the drawing commands are configured to operate in parallel, and the display list analyzer analyzes the drawing commands written in the display list DL in the order in which they are written, and transfers the drawing commands one after another to the corresponding internal circuits (see Figure 13(a)).

[0190] Incidentally, the internal circuitry of the drawing circuit 74 operates asynchronously with the CPU circuit 51 that issues the display list DL and the data transfer circuit 70 that transfers the configuration data of the display list DL in sequence, and generally, the operating speed of the internal circuitry of the drawing circuit 74 is much slower than the transfer speed of the configuration data of the display list DL.

[0191] Therefore, the internal circuit that receives the drawing command is provided with a standby queue that accumulates drawing commands before processing begins, and the display list analyzer puts the drawing command into the standby queue on the condition that there is space in the standby queue. In other words, the display list analyzer stalls (temporarily stops) the input operation until the standby queue becomes empty, so there is no risk of losing the drawing command. Note that the numbers shown for the standby queue are merely an example showing the number of stages in the queue.

[0192] As explained earlier, the instruction commands written in the display list DL include: (1) index table control commands related to the index table IDXTBL that manages the index space; (2) texture load commands such as the LOADTX command for reading image material (texture) from external ROM 55 and decoding (decompressing / expanding) it; (3) filter execution commands that specify the filter processing to be performed on the decompressed image data; (4) drawing commands such as the SPRITE command for placing the decoded (expanded) image material at a predetermined position in the virtual drawing space; and (5) pipeline commands related to drawing pipeline operations.

[0193] 13(a), an index table control command (1) is transferred to the control circuit of the index table IDXTBL, a texture load command (2) is transferred to the GDEC circuit 73, and a filter execution command (3) is transferred to the image filter circuit 75, and each is processed appropriately by the destination circuit. Specifically, the GDEC circuit 73 operates based on the transferred drawing command (texture load command), obtains the necessary texture, and loads the decompressed data into the decode space.

[0194] Furthermore, the index table IDXTBL is updated appropriately by the control circuit of the index table IDXTBL. The image filter circuit 75 performs a specified filter process on a specified reference texture and stores the filter process result in a specified index space (see FIG. 10). When a specified drawing command (high-speed transfer command) is received, the high-speed transfer circuit TRNS functions to transmit and receive data at high speed between the VRAM 53 and the expansion RAM 54. The high-speed transfer circuit TRNS is an internal circuit of the drawing circuit 74, and is a circuit separate from the data transfer circuit 70.

[0195] When using the data transfer circuit 70, the CPU circuit 51 must set the type of source medium and transfer start address, the type of destination medium and receiving start address, and transfer size in a specified performance control register RGij (data transfer register), but the high-speed transfer circuit TRNS has the simplicity of being able to function when necessary by an instruction command (transfer execution command) in the display list DL, and has the advantage of being able to transfer two-dimensional data at high speed in units of index space. Note that in a control program that is constantly functioning, using the data transfer circuit 70 only when necessary is not easy in terms of program configuration.

[0196] As explained above, the rendering pipeline operation is performed using the vertex buffer VB built into the rendering circuit 74, the frame buffer FB reserved as an index space, and the depth / stencil buffer which manages the anterior-posterior relationship of polygons and whether or not pixels are displayed, and is configured to execute an input assembler process (acquisition process) IA, a geometry engine process TL, a rasterizer process (primitive process) RS, a texture sampler process TX, a texture process PS, a pixel drawing process PX, and a render process (image generation process) RO as required.

[0197] That is, the rendering pipeline process is executed from upstream to downstream, passing through all or some of the processes in the order of process IA → process TL (process VB) → process RS → process TX → process PS → process PX → process RO. Each process operates in parallel, but since the downstream process takes longer to complete the execution of rendering commands, the number of stages in the waiting queue that accumulates the rendering commands input to each process is configured so as not to be less than the number of stages in the waiting queue on the upstream side.

[0198] As shown in FIG. 13(a), the number of stages in the waiting queue is 1 stage → 5 stages → 14 stages → 18 stages → 18 stages → 23 stages, corresponding to process IA → process TL → process RS → process TX → process PS → process PX → process RO, and the number of stages at each process is the same as or greater than the number of stages in the upstream waiting queue.

[0199] The pipeline commands described above are setting commands that stipulate the operation of each pipeline process (IA, TL, VB, RS, TX, PS, PX, RO). The acquired pipeline commands are transferred to the parameter setting unit SET, which sets the operating parameters required for the necessary internal circuits, such as the geometry engine.

[0200] In this embodiment, as shown in FIG. 13(b), the rendering pipeline is composed of process IA, process TL, process RS, process TX, process PS, process PX, and process RO. First, the input assembler process IA acquires a vertex stream of a three-dimensional 3D rendering object, which is usually defined in local coordinates, stores information required for subsequent processing, and outputs vertex data having specified vertex information.

[0201] In this process IA, in addition to the setting commands for process IA (pipeline commands), drawing commands such as DRAW and DRAWD are used. The DRAW command specifies the top address of the memory (external ROM 55 in this embodiment) in which a series of vertex streams are stored, and the number of vertices.

[0202] On the other hand, in the DRAWD command, a series of vertex streams are embedded in the command. The specific operation contents of the DRAW command and the DRAWD command are specified by the embedded information of each command and the setting command for the process IA. Note that in the vertex stream, a vertex color (RGBA color information) can be specified for each vertex, but if the vertex color is not specified, a default value is set as the vertex information in the input assembler process IA. Here, RBG means color information of R=Red, B=Blue, G=Green, and A is an alpha value α indicating opacity, and is used in the alpha blending process when compositing images by overlapping them.

[0203] In the subsequent geometry engine process TL, a matrix operation for transforming the vertex coordinates of the 3D drawing object and a lighting process for light sources are performed on the vertex data output from the input assembler process IA. In the coordinate transformation process, a view matrix operation for transforming local coordinates into view coordinates and a matrix operation for projective transformation (perspective projection) are performed.

[0204] Here, the view coordinate system has the viewpoint as its origin and the line of sight to infinity (0,0,-∞). In projective transformation, in order to realize a sense of perspective corresponding to the placement position of a 3D drawing object, the view coordinate system is transformed into the clip coordinate system by enlarging / reducing the shape of the 3D drawing object.

[0205] The specific content of the matrix operation is specified by the setting command (pipeline command) for the TL process, and the execution of a specified geometry matrix operation is instructed by the DRAW command or DRAWD command. Therefore, the process IA and the process TL can be executed together by one drawing command (DRAW / DRAWD). However, in either case, the execution result of the geometry matrix operation by the drawing command (DRAW / DRAWD) is saved in the vertex buffer VB.

[0206] The geometry engine process TL is not essential, and when a vertex stream defined by clip coordinates is obtained from the external ROM 55, the information passes through the input assembler process IA and is stored directly in the vertex buffer VB. The input assembler process IA and the geometry engine process TL may be repeated for multiple 3D drawing objects, and the vertex buffer VB is configured to store a maximum of 256 vertices.

[0207] Next, in the rasterizer process RS, primitives are generated and drawn based on the vertex information in the vertex buffer VB, and pixel data of a 3D drawing object is generated after removing polygons that do not need to be drawn by conversion from the clip coordinate system to the window coordinate system, clipping, culling, scissoring, etc. In other words, a three-dimensional 3D image object is determined to be placed at a predetermined position and with a predetermined attitude in the window coordinate system (world coordinates) corresponding to the virtual drawing space.

[0208] To generate primitives, a triangle drawing method such as a triangle list, triangle strip, or triangle fan, and a line drawing method such as a line list, line strip, or line fan can be appropriately selected and used.

[0209] In addition, in the rasterizer process RS, in addition to the setting commands (pipeline commands) for the RS process that specifically define the processing contents, drawing commands DRAW command, DRAWD command, DRAWI command, and SPRITE command are used as appropriate.

[0210] Here, the DRAWI command generates and draws primitives based on vertex data obtained from the vertex buffer VB, whereas the DRAW command generates and draws primitives based on a vertex stream obtained from the external ROM 55, and the DRAWD command generates and draws primitives based on a vertex stream embedded in the command.

[0211] Therefore, the rasterizer process RS can be executed without going through the geometry engine process TL. For example, in the case of a two-dimensional 2D drawing object, the geometry engine process TL is not particularly necessary. In either case, each polygon generated through the rasterizer process RS has RGBA color information for each pixel based on the vertex color for each vertex.

[0212] Next, in the texture sampler process TX, the index space to be used as the texture is specified, and the texture coordinates for each pixel are specified. Then, in the texture process PS, the pixel color obtained in the rasterizer process RS and the texture color are appropriately calculated.

[0213] In these steps TX and PS, and in the following step PX, in addition to the setting commands (pipeline commands) in each step, the drawing commands DRAW, DRAWD, DRAWI, and SPRITE are used as appropriate. In the DRAW, DRAWD, and DRAWI commands, the texture is pasted into the area surrounded by specified vertices, and in the SPRITE command, the texture is pasted into a specified rectangular area.

[0214] Then, in the subsequent pixel drawing process PX, the drawing color and background color are mixed, and tone mapping and inverse tone mapping for adjusting contrast are performed. In this PX process, pixel data having predetermined information is input for each pixel from the texture process PS, and data (background color) stored at the pixel drawing position is input for each pixel from the frame buffer FB.

[0215] The final rendering process RO refers to the depth / stencil buffer etc., performs a pixel test to determine whether or not to display the pixel based on the pixel's depth information and stencil information, and writes the completed drawing object to the frame buffer FB after processing such as alpha blending for overlapping multiple drawing objects. Writing to the frame buffer FB is nothing more than drawing in the virtual drawing space shown in Figure 6, and normally the SPRITE command is used.

[0216] In addition to the DRAW, DRAWD, DRAWI, and SPRITE commands, the rendering process RO can use the CLEAR command, which fills the frame buffer FB with a single color, and the CLEARZ command, which fills the depth-stencil buffer with a single color. The CLEAR command is used to clear the frame buffer FB prior to the start of drawing operations, and the CLEARZ command is used when depth information or stencil information is not required.

[0217] In this way, in the present invention, all or some of the series of drawing pipeline steps function to write two-dimensional or three-dimensional drawing objects one after another into the frame buffer FB, ultimately completing one frame's worth of image data for the display device.

[0218] Figure 14 is a process diagram showing various rendering modes that utilize all or part of the rendering pipeline process. First, the rendering mode in Figure 14(a) is an operation mode that uses the above-mentioned CLEAR command and CLEARZ command, and only the render process RO functions.

[0219] 14(b), the rasterizer process RS, texture sampler process TX, texture process PS, pixel drawing process PX, and render process RO function. Note that the rasterizer process RS simply adds an offset value to the X and Y coordinates of the vertices in the window coordinate system, but this offset value is related to the rectangular area to which the SPRITE command is pasted.

[0220] The actual operation is as follows: the SETTXINDEX command sets the destination index space, the LOADTX command gets a specified texture and expands it into the above index space, and the SPRITE command secures this expanded texture in a specified position. The expanded texture information is then referenced and finally written to the frame buffer FB. In principle, video playback and playback of still images of simple shapes are achieved in this sprite drawing mode.

[0221] The drawing mode shown in Fig. 14(c) is an example of operation for triangle drawing and line drawing using all the processes of the drawing pipeline. Note that the only difference between triangle drawing and line drawing is the method of generating primitives. In either case, primitives are identified and drawn based on the vertex stream of the 3D drawing object supplied to the input assembler process IA.

[0222] 14(d) shows a drawing operation using the DRAW command, DRAWD command, etc., in which pixel data for a drawing object is generated in the rasterizer process RS without performing a coordinate transformation process. This operation is typically used when a two-dimensional 2D drawing object, the contour of which can be identified by a vertex stream, is displayed on a display screen.

[0223] Figures 14(e) and (f) show operation modes when vertex data is stored in the vertex buffer VB, and are divided into (e) where coordinate transformation processing is performed and (f) where coordinate transformation processing is not performed. These operations are executed by the DRAW command or the DRAWD command. Figure 14(g) shows an operation mode that uses the vertex data stored in the vertex buffer VB, and is executed by the DRAWI command.

[0224] As described above, the rendering pipeline of this embodiment can be used in various ways. For example, playback of 2D still images and streaming video (S stream, IPB stream, IP stream) requires simple sprite drawing, so the playback operation is realized in the operating mode of Figure 14(b) as described above.

[0225] As described above, the display list analyzer judges the drawing commands in the display list DL and transfers them to the processing blocks of the pipeline steps corresponding to the drawing commands. The transferred drawing commands are then first put into the waiting queues of the pipeline steps, and the processing corresponding to the drawing commands is executed in the order of their input.

[0226] However, since the operation of the data transfer circuit 70, which transfers the display list DL, is much faster than the progress of this rendering pipeline, for example, if you want to display multiple 3D rendering objects on the screen and also other 2D drawing objects on the screen, there will be a long wait for the execution of the SPRITE command in the rendering process RO.

[0227] That is to say, since it takes a certain amount of time to process a coordinate transformation matrix for a 3D drawing object, for example, a large number of SPRITE commands will accumulate in the standby queue of an RO process, etc. However, in this embodiment, as explained above, the input of drawing commands is put on hold until the standby queue is empty (stall state), and moreover the number of stages in the standby queue of the downstream process is the same as or greater than the number of stages in the standby queue of the upstream process, so that the commands written in the display list DL can be operated smoothly in the order in which they are written.

[0228] Note that drawing commands transferred from the waiting queue are also put on hold (stalled) until the necessary start conditions are met, so that inconsistent drawing operations such as rewriting the index space do not occur.

[0229] Having described the circuit configuration above, we now turn to a description of the control operation by the CPU circuit 51. As described above, when the power is turned on, prior to the start of the control operation, a reset period occurs during which the system reset signal SYS is maintained at the L level for a predetermined period of time.

[0230] During this reset period, first, one or two oscillator circuits that control the operation of the general performance circuit 52 and the built-in CPU circuit 51 start oscillating, and wait for the oscillation frequency of each system clock to stabilize. Next, the internal circuit of the composite chip 50 is initialized in synchronization with each system clock, and a predetermined default value is set in the performance control register RGij and the operation control register REG. Hereinafter, this operation will be referred to as a hardware reset in this specification to distinguish it from a software reset, which will be described later.

[0231] When this hardware reset period ends, the performance control CPU 57 of the built-in CPU circuit 51 executes the boot program stored in the external ROM 55 and transfers the control program and control data from the external ROM 55 to the extended RAM 54. Then, the performance control CPU 57 continues the control operation based on the control program transferred to the extended RAM 54.

[0232] The control operation executed by the performance control CPU 57 is as shown in Fig. 15, and includes a main process (a) consisting of an initial process and the subsequent regular process, a timer interrupt process (b) that is started every 1 ms, a VBLANK interrupt process (c) that is started upon receiving a VBLANK signal output from the general performance circuit 52 at the start timing of the vertical blanking period of the display device DS, and a reception interrupt process (not shown) for receiving a control command CMD. The VBLANK signal is generated every 1 / 60 seconds.

[0233] As shown in Fig. 15(b), in the timer interrupt process, a sensor signal is acquired to grasp the motor position, etc. (ST20), and when necessary, a lamp performance or a motor performance is started or progressed (ST21). In this embodiment, the lamp performance is realized by the operation of the performance control CPU 57 and the lamp control unit L_CTL based on the lamp drive data, which is the control data. The motor performance is realized by the operation of the performance control CPU 57 and the motor control unit MT_CTL based on the lamp drive data, which is the control data. Also, in the VBLANK interrupt process that is started upon receiving the VBLANK signal, as shown in Fig. 15(c), the interrupt counter VCNT is incremented and the process ends (ST22).

[0234] First, the main process will be described in the case where the preloader 72 is not utilized. As shown in Fig. 15(a), first, an initial setting process (ST1) is executed, and appropriate setting values ​​are set in the performance control register RGij of the overall performance circuit 52 and the operation control register REG of the CPU circuit 51.

[0235] The setting process for the performance control register RGij includes the process of reserving an appropriate virtual working area (AAC area, page area, arbitrary area) in the VRAM 53 and the extended RAM 54 (see Fig. 6(a) and Fig. 6(b)), and the process of reserving an index space essential for game control operations, such as the frame buffer FB. As explained above, the frame buffer FB is composed of a first buffer with index number N1 and a second buffer with index number N2.

[0236] The start address of the shared area (used as the AAC area in this embodiment) secured in the VRAM 53 is set in 4k byte units (the lower 15 bits are zero), and the area size is secured as an integer multiple of 4k bytes. Also, the page area secured in the expansion RAM 54 is set in 32k byte units (the lower 18 bits are zero), and the area size is secured as an integer multiple of 32k bytes.

[0237] Moreover, the set value in the operation control register REG includes operation parameters for the watchdog timer WDT 58, and these operation parameters include an operation start instruction and a counter value. The WDT 58 in the embodiment is configured to count down an initial value (counter value), and by reloading the counter value before the count value reaches an underflow where it becomes zero, activation of the WDT 58 is prevented.

[0238] On the other hand, when the count value underflows, a WDT reset request is generated, and the WDT 58 starts, resulting in a software reset state. In standard operation, all internal circuits are initialized, and the values ​​of all registers RGij and REG, except for certain registers, return to their initial values ​​(default values), and the WDT 58 stops operating. The only exception is the register that maintains its register value, which is the register that indicates the operating state of the WDT.

[0239] However, in this embodiment, operations other than the standard operation described above are also possible, and (1) whether to initialize the internal circuitry, and (2) whether to initialize the system clock circuitry even if the internal circuitry is initialized, can be arbitrarily selected by setting corresponding values ​​in a specified operation control register REG during the initial setting process after a hardware reset. Therefore, in this embodiment, based on the set value in the specified operation control register REG, the internal circuitry is not initialized during a software reset, and the game operation is resumed from the process of step ST1.

[0240] Thus, in this embodiment, unlike the configurations of Prior Art Documents 1 and 2, even if the WDT 58 underflows, the hardware reset state is not entered, so there is an advantage that the game operation can be quickly resumed. Note that after the software reset, the WDT stops operating, so there is no risk of the software reset operation being repeatedly started.

[0241] When the initial setting process (ST1) including the above processes is completed, the intermittently executed steady-state process (ST2 to ST10) is started. As shown as step ST2 in Fig. 15(a), the steady-state process is started when the interrupt counter VCNT becomes VCNT>=2, so that the operation period (operation cycle) δ of the steady-state process is 1 / 30 seconds corresponding to the operation period (1 / 60 seconds) of the VBLANK signal.

[0242] Then, in the process of step ST3, after resetting the interrupt counter VCNT, it is judged whether or not the operation start condition for starting the normal operation is satisfied. Specifically, a predetermined performance control register RGij indicating the operation state of the drawing circuit 74 is accessed for READ, and it is judged whether or not the drawing circuit 74 has finished the drawing operation based on the display list DL of the previous operation cycle at this timing. Also, in the drawing operation of the previous operation cycle, it is judged whether or not the memory access period of the drawing circuit 74 has exceeded the timeout time set in the time setting register TO based on the ON / OFF state of a predetermined abnormality flag.

[0243] If the abnormality flag is ON because memory access by the drawing circuit 74 has taken an abnormally long time, even if the drawing circuit 74 has finished drawing operation, it is determined that the operation start condition is not satisfied, and the process proceeds to the performance command analysis process of step ST9.

[0244] The processing of steps ST4 to ST8 is skipped in order to avoid an unreasonable screen display, since there is a possibility that normal image data, including garbled bits in the instruction command, is not being generated since the memory access of the drawing circuit 74 is taking an abnormally long time.

[0245] In the performance command analysis process (ST9), it is determined whether or not a control command CMD has been received from the main control board 21, and if a control command CMD has been received, the control command CMD is analyzed and necessary processing is executed. Here, the necessary processing includes a process for preparing to start a new variable performance based on a control command CMD that instructs the start of a variable performance, and a process for starting an error notification based on a control command CMD that indicates the occurrence of an error.

[0246] Next, the counter value is reloaded into the watchdog timer WDT 58 to prevent the watchdog timer 58 from starting (ST10). As explained above, even in the event of an abnormality that would cause the watchdog timer 58 to start, the composite chip 50 of this embodiment goes into a software reset state that is different from a hardware reset. This completes the operation of the current operation cycle, so the process moves to step ST2 to wait for the next VBLANK interrupt.

[0247] Although the above describes the case where the operation start conditions are not satisfied, normally, after the judgment process of step ST3, the display circuit 71 specifies the image data to be read based on the set value of the specified display register RGij, and starts the operation of the display circuit (ST4). As described above, the frame buffer FB has a double buffer structure, and the first buffer and the second buffer are controlled by the set value of the specified display register RGij so that they are switched in a toggle manner.

[0248] Specifically, the index number N1 / N2 of the first buffer or the second buffer specified as the "write area" by the display list DL of the previous operation cycle is set. By executing this step ST4, the "write area" of the previous operation cycle changes to the "read area" of the current operation cycle, so that the display circuit 71 outputs the image data completed by the drawing circuit 74 in the immediately previous operation cycle to the display device DS. That is, the process of step ST4 also includes an instruction to start the read operation of the display circuit 71.

[0249] When the processing of step ST4 having the above significance is completed, the performance control CPU 57 then completes a display list DL that specifies image data that the display circuit 71 should output to the display device DS in the next operation cycle (ST5). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of the built-in RAM 59 is reserved in advance, and the display list DL is completed there (see FIG. 8).

[0250] In principle, the display list DL is created every time with its contents changed for each operation cycle, but the leading area of ​​the display list DL contains a command that specifies the index number of the frame buffer FB. As explained earlier, the frame buffer FB is an index space with a double-buffer structure with index numbers N1 and N2. And, in order to use the double buffer in a toggle manner, each display list DL alternates between the frame buffer FB with index number N1 and the frame buffer FB with index number N2 to rotate the "write area."

[0251] The performance control CPU 57 issues the display list DL thus completed to the general performance circuit 52 (ST6). Next, the performance control CPU 57 updates the performance scenario EN that centrally manages the image performance, audio performance, lamp performance, and motor performance (ST7), and if it is a necessary performance timing, issues a voice command list VC to the voice processing unit SND to start or progress the audio performance (ST8).

[0252] In addition, when the start time of the motor performance or lamp performance managed by the performance scenario EN is reached, the timer interrupt process (FIG. 15(b)) executes the motor performance or lamp performance based on the corresponding motor drive data or lamp drive data. The process of steps ST9 to ST10 following step ST8 is as described above.

[0253] Fig. 16(a) and Fig. 16(b) are flow charts showing the specific contents of the display list DL issuing process (ST6), and Fig. 16(c) is a schematic diagram showing the operation contents of the DL issuing process (ST6). As explained with reference to Fig. 9, the display list DL issuing process includes a case where the CPU register port PORT is accessed by write in 32-bit units (Fig. 9(a)), and a case where the CPU register port PORT is not accessed (Fig. 9(b)). The operation contents of each case are shown in Fig. 16.

[0254] First, referring to FIG. 16(a), the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (data transfer channel CH2), and sets the total size of the transfer data in a specified transfer register RGij (ST30).

[0255] Here, the display list DL is issued with a termination command EODL, the contents of which differ for each operation cycle. In this embodiment, the instruction command used for the display list DL, including the termination command EODL, is one word or multiple words (=N*32 bits), so no adjustment process for the amount of data is required. In other words, the total size of the transfer data set in the transfer register RGij is an arbitrary value that is an integer multiple of 32 bits.

[0256] Next, the performance control CPU 57 sets the number of writes corresponding to the total size of the transfer data in the management counter CN (ST31), starts the operation of the drawing circuit 74 (ST32), and then starts the operation of the data transfer circuit 70 (ST33). Here, the instruction to start the operation of the drawing circuit 74 and the data transfer circuit 70 is realized by a setting process to a predetermined drawing register RGij and a transfer register RGij, respectively.

[0257] Next, the performance control CPU 57 writes the configuration data of the display list DL in 32-bit units to the CPU register port PORT while checking that the 130-stage CPU data FIFO circuit is not full (ST35). Then, it continues the write operation while decrementing the management counter CN (ST36, ST37).

[0258] As explained above, the CPU data FIFO circuit receives data in 32-bit units, while the data relay units CH0 to CH4 receive data in 1024-bit units. Therefore, in principle, when 1024-bit data is accumulated in the CPU data FIFO circuit, the accumulated data is transferred to the data relay unit CH2, but when the set value (total size of the transfer data) of the transfer register RGij is reached, the accumulated data in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0259] The above process ends the DL issuing process (ST6) via the CPU register port PORT, but next, Fig. 16 (b) shows an example in which the data transfer circuit 70 reads out a display list from the list buffer (DL buffer BUF) without going through the CPU register port PORT. In this case, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (ST40), and sets the total size of the transfer data and the top address of the list buffer BUF in a specified transfer register RGij (ST41).

[0260] As explained above, since the top address of the list buffer BUF set in the internal RAM 59 must be set in 8-bit units, the lowest 7 bits of the start address of the DL buffer BUF are zero. This address condition applies not only to the top address of the list buffer BUF that stores the display list DL, but also to the top address of the list buffer BUF that stores the voice command list VC.

[0261] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST42), and then starts the operation of the data transfer circuit 70 (ST43). These operation instructions are also realized by setting processes to the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and the data transfer circuit 70 ends its operation when the transfer of a predetermined size of data is completed. Therefore, after the processing of step ST43, the performance control CPU 57 can immediately move on to another process following the display list issuing process (ST6).

[0262] In this case as well, when the amount of transfer data reaches the set value (total size of transfer data) in the transfer register RGij, the data stored in the CPU data FIFO circuit at that time is transferred to the data relay unit CH2.

[0263] The above describes the process of issuing a display list DL based on Figures 16(a) and 16(b). However, when issuing a voice command list VC to the voice processing unit SND, the processing content is essentially the same as that shown in Figures 16(a) and 16(b) (see Figures 9(f) and 9(g)).

[0264] That is, the voice command list VC in which the voice commands are listed is terminated with a predetermined end command EOSC before being issued. Note that the voice command, including the end command EOSC, is one word or multiple words (=N*32 bits), so no adjustment processing of the data amount is required.

[0265] Although the above describes the case where the preloader 72 is not used, the main processing when the preloader 72 is used is as shown in Fig. 17(a). The processing content shown in Fig. 17(a) is similar to the processing content in Fig. 15(a).

[0266] However, as shown in FIG. 17(a), (a) after creating a display list DL for the next operation cycle (ST5), the display list DL is issued to the preloader 72 (ST60) instead of the drawing circuit 74, and (b) this display list DL is rewritten by the preloader 72 to become a rewrite list DL', but the rewrite list DL' rewritten in the previous operation cycle is acquired by the drawing circuit 74 (ST41) prior to the processing of step ST5, which is different from the processing of FIG. 15(a).

[0267] 17(a), the issue process (ST60) for issuing the display list DL to the preloader 72 is substantially the same as that of FIG. 16(a) and (b), except that the issue destination is changed to the preloader 72. The outline of the operation is as shown in FIG. 9(d) and FIG. 9(e), and in response to the change in the issue destination to the preloader 72, the data relay unit CH2 is changed to the data relay unit CH3 (data transfer channel CH3), but otherwise the operation is the same as that of FIG. 16(a) and FIG. 16(b), and the corresponding operations are shown in FIG. 17(b) and FIG. 17(c).

[0268] On the other hand, the process (ST41 in FIG. 17) for causing the drawing circuit 74 to obtain the rewrite list DL' is shown in FIG. 17(d). As shown in FIG. 9(c), in this embodiment, the rewrite list DL' is stored in the preload buffer of the VRAM 53 (see FIG. 6(a)).

[0269] In the process of step ST41 in Fig. 17, the performance control CPU 57 sets the transfer register RGij to use the data relay unit CH2 (transfer channel CH2) (ST50 in Fig. 17(d)). Next, the total size of the rewrite list DL', which is the transfer data, and the top address of the preload buffer in which the rewrite list DL' is stored are set in a predetermined transfer register RGij (ST51).

[0270] Since the starting address in VRAM 53 needs to be set in 32-bit units, the starting address of the preload buffer that stores the rewrite list DL' needs to have the lowest 31 bits set to zero; in this embodiment, the preload buffer is allocated at a position that satisfies this condition.

[0271] Next, the performance control CPU 57 starts the operation of the drawing circuit 74 (ST52) and starts the operation of the data transfer circuit 70 (ST53). These operation instructions are realized by setting the predetermined drawing register RGij and transfer register RGij, respectively. Then, the data transfer process is started by this operation instruction, and the data transfer circuit 70 ends its operation when the data transfer is completed.

[0272] Next, the presentation centered on image display on the display device DS will be explained. The presentation means used for this presentation include the display device DS, as well as light-emitting means (illumination lamps) such as the frame side LED lamps (i.e., the glass door 6, front panel 7 side) and the board side LED lamps (i.e., the game board 5 side), sound output means such as speakers, movable presentation bodies, etc., which are controlled by the presentation control board (presentation execution means) 23 to execute various presentations.

[0273] The display device DS displays various performance images, notification images, etc., and as shown in Figure 18, is composed of a decorative pattern display means 161, a mini pattern display means 162, a reserved image display means 163, etc., and the decorative pattern display means 161 can variably display a decorative pattern 164, and the mini pattern display means 162 can variably display a mini pattern 165, and the reserved image display means 163 can display various images such as first and second reserved images X1-X4, Y1-Y4 indicating the first and second special reserved numbers.

[0274] The decorative symbol display means 161 is configured to be able to variably display decorative symbols 164 by the display device DS based on the entry of a game ball into the first and second symbol start holes 15a and 15b (establishment of a predetermined symbol start condition). The decorative symbols 164 include a left decorative symbol (first decorative symbol) 164a variably displayed on the special symbol display section Da (see FIG. 2), a right decorative symbol (second decorative symbol) 164b variably displayed on the special symbol display section Dc (see FIG. 2), and a center decorative symbol (third decorative symbol) 164c variably displayed on the special symbol display section Db (see FIG. 2), and each of the decorative symbols 164a to 164c is configured as a symbol row in which a plurality of symbols are arranged endlessly. In addition, each of the decorative patterns 164a to 164c has a main body portion (number portion) 166 consisting of numbers such as "1" to "8" and the like, and characters and other decorative portions 167 accompanying this main body portion 166. The display can be changed to a number of different display modes, including a non-decorative display mode in which the main body portion 166 is displayed but the decorative portion 167 is not displayed, and a decorative display mode in which both the main body portion 166 and the decorative portion 167 are displayed, and it is also possible to enlarge, reduce, change the display position, etc.

[0275] When a game ball enters the first and second pattern starting holes 15a, 15b (when the pattern starting conditions are met), the decorative patterns 164a-164c are displayed fluctuating for a predetermined period of time according to a predetermined fluctuation pattern, and if the jackpot determination random number value contained in the first special random number information (random number information) obtained when the game ball enters the first pattern starting hole 15a matches a predetermined jackpot determination value, they stop in a jackpot presentation mode, otherwise they stop in a miss presentation mode, and if the jackpot determination random number value contained in the second special random number information (random number information) obtained when the game ball enters the second pattern starting hole 15b matches a predetermined jackpot determination value, they stop in a miss presentation mode, otherwise they stop in a miss presentation mode. Among the decorative symbols 164a to 164c, combinations (predetermined combinations) of all the same symbols, such as "2·2·2" and "7·7·7", result in a big win presentation, and other combinations result in a loss presentation, or the like.

[0276] In the pattern change based on the entry of a game ball into the first pattern start hole 15a, when the decorative patterns 164a to 164c become a jackpot performance mode, a special game as a first jackpot is started, and the slide plate of the first big prize winning hole 16a is opened. In addition, in the pattern change based on the entry of a game ball into the second pattern start hole 15b, when the decorative patterns 164a to 164c become a jackpot performance mode, a special game as a second jackpot is started, and the opening and closing plate of the second big prize winning hole 16b is opened. Note that the decorative pattern display means 161 is not limited to one in which the decorative patterns 164a to 164c are arranged in the left-right direction and changed by vertical scrolling, etc., but may be, for example, a case in which the decorative patterns 164a to 164c are arranged in the up-down direction and changed by horizontal scrolling, etc.

[0277] The fluctuation pattern of the decorative pattern 164 starts with a normal fluctuation in which each row of the decorative patterns 164a to 164c fluctuates, and if a reach state such as "2·↓·2" or "7·↓·7" is established during the normal fluctuation, it is configured to go through one or more stages of reach performance (N reach, S reach, SP reach, etc.) and finally stop. A reach fluctuation pattern is when the normal fluctuation develops into a reach performance and becomes a jackpot performance mode or a miss performance mode, and a normal fluctuation pattern is when the normal fluctuation develops into a miss performance mode without developing into a reach performance mode.

[0278] The mini symbol display means 162 is configured to be capable of displaying a mini symbol 165 by the display device DS in response to the display of the decorative symbol 164 based on the entry of a game ball into the first and second symbol start holes 15a and 15b. The decorative symbol 164 is not always displayed even during the pattern change from when the pattern change starts based on the entry of a game ball into the first and second symbol start holes 15a and 15b until the change stops (hereinafter, simply referred to as during pattern change), and may disappear partly or entirely from the screen depending on the performance content such as a reach performance, whereas the mini symbol 165 is always displayed on the display device DS during the pattern change. Note that the mini symbol 165 may disappear from the screen during a part of the pattern change. Also, the mini symbol 165 may be difficult or impossible to see during a part of the period when a movable performance body (not shown) moves.

[0279] The mini pattern 165 has the same number of pattern rows (three in this case) and the type of pattern (number patterns from "1" to "8" in this case) as the decorative pattern 164, but has only a main body with numbers such as "1" to "8" and no decorative part, and is displayed in a smaller size than the decorative pattern 164 near the periphery of the display screen DSa of the display device DS as shown in FIG. 18. In addition, the display state of the mini pattern 165 is only a "change stop state" and a "high-speed change state", and there is no speed change during the change (deceleration, frame advance, etc.) like the decorative pattern 164. When the pattern change starts, the change stop state due to a predetermined change start result or the previous stop result is instantly switched to a predetermined change start result, and then the pattern rows change in a high-speed change state in which they change in a cyclical manner at a predetermined speed, and when the pattern change stops, the high-speed change state is switched to a change stop state due to a predetermined change stop result. In addition, the speed of change of the mini pattern 165 during the high-speed changing state is always constant, and as shown in Figure 19, on a display device DS which displays video at a predetermined frame rate (e.g., 60 fps), the high-speed changing display of the mini pattern 165 is performed at a speed where the pattern row goes around once every N frames.

[0280] In addition, in the decorative pattern 164, the variation stop number is the variation start number for the next variation, but the mini pattern 165 is always set to a predetermined variation start number, and when the variation starts, the variation stop number of the previous variation is instantly switched to a predetermined variation start number, and then the high-speed variation starts from that variation start number. This is because if the previous variation was a reach-miss variation or a jackpot variation, if the variation stop number is used as the variation start number to start the variation of the mini pattern 165, the high-speed variation will occur with the left and right patterns or all patterns aligned, which may give the player the misunderstanding that it will be a reach or jackpot again. Therefore, the variation start number of the mini pattern 165 must be set to a number that is unrelated to reach or jackpot, such as "1·3·5". The variation stop number of the mini pattern 165 is the same as the variation stop number of the decorative pattern 164.

[0281] The reserved image display means 163 executes a reserved display effect that displays a reserved image showing the number of random number information stored in the reserved storage means. Here, when a game ball enters the first and second pattern start holes 15a and 15b during a special reserved period including during the pattern variation of the decorative pattern display means 161 and during a jackpot (special game), the first and second special random number information acquired thereby are reserved and stored in a predetermined reserved storage means with a predetermined upper reserved number limit, for example, four pieces each, and then, when the special reserved period ends, the reserved memory is consumed and a new pattern variation by the decorative pattern display means 161 is started. The reserved image display means 163 is configured to notify the number of stored first and second special random number information (first and second special reserved numbers) by the number of displayed reserved images.

[0282] As shown in FIG. 18, the display device DS is configured to display the first and second reserved images X1-X4, Y1-Y4, etc., which indicate the first and second special reserved numbers, superimposed on the front of a predetermined reserved base image 168. The reserved image display means 163 additionally displays the first and second reserved images X1-, Y1- on the reserved base image 168 when the first and second special reserved numbers increase based on game balls entering the first and second pattern start holes 15a, 15b, and shifts the first and second reserved images X1-, Y1- by one toward the front of the queue (for example, the right side of the screen) when the first and second special reserved numbers decrease based on the start of a new variation of the decorative pattern 164 by the decorative pattern display means 161. The reserved base image 168 is displayed on the periphery or in the vicinity of the display screen DSa, and is displayed horizontally along the lower edge of the display screen DSa in this embodiment.

[0283] Next, specific examples of effects during the change of the decorative pattern 164 (there may be periods when at least a part of the decorative pattern 164 is not displayed) will be described, focusing on the image effects by the display device DS, the light-emitting effects by light-emitting means (illumination lamps) such as the frame-side LED lamp and the board-side LED lamp, and the sound output effects by the sound output means. In the following description, the frame-side LED lamp will be referred to as the "frame-side lamp La", the board-side LED lamp will be referred to as the "board-side lamp Lb", and they will be collectively referred to as the "effect lamp L". In the drawings used in the following description, the board-side lamp Lb and the frame-side lamp La will be represented in a simplified diagram showing the state in which the former are arranged on the upper side and both the left and right sides of the display device DS, and the latter are arranged on both the left and right sides of the former, as shown in FIG. 18. Of course, the arrangement of the board-side lamp Lb and the frame-side lamp La is not limited to this.

[0284] Below, as specific examples of the preview performances executed during the pattern change, eight types of preview performances, namely, step-up preview performance, reach preview performance, button preview performance 1, dialogue preview performance 1, pseudo consecutive preview performance, button preview performance 2, interrupt preview performance, and dialogue preview performance 2, will be explained in order. These eight types of preview performances are selected and executed based on the setting of the jackpot reliability as shown in FIG. 20. Here, the "jackpot reliability" is an example of the reliability regarding the occurrence of a predetermined event, and here refers to the reliability that the decorative pattern 164 will become a jackpot performance mode. After explaining these eight types of preview performances, several examples (reliability suggestion performance, reach title display performance, operation performance, reach development performance) of various performances that can be adopted as part of these various preview performances, etc. will be explained.

[0285] In addition, the contents described below for each effect are not limited to each effect, and may be adopted for other effects. For example, the configuration of the high brightness effect that appears in the step-up notice effect may be adopted in other notice effects such as reach notice effects and dialogue notice effects, or in partial effects such as reliability suggestion effects.

[0286] [Step Up Preview] 21 to 26 show an example of a step-up notice performance executed during normal fluctuation in a reach fluctuation pattern or a normal fluctuation pattern. The step-up notice performance (specific notice performance) is a performance executed up to a predetermined stage among a plurality of stages (here, five stages) of performance steps according to the reliability of a jackpot, and is set so that the reliability of a jackpot increases as the stage of the performance step progresses.

[0287] As shown in FIG. 21, in this step-up preview performance, five kinds of characters, an elephant, a lion, a fox, a squirrel, and a bear, which correspond to the first to fifth performance steps, each take turns shooting an arrow at a balloon, and the performance steps proceed until an arrow shot by one of the characters hits the target and the balloon bursts. First, a step-up introduction performance ST0 is performed, which indicates that the step-up preview performance is about to start (FIG. 21(a)). In this step-up introduction performance ST0, the five kinds of characters each aiming at a balloon appear all at once, suggesting the content of the step-up preview performance. Of course, the characters may appear in the order of the corresponding performance steps: elephant → lion → fox → squirrel → bear, or in any other order.

[0288] Following the step-up introduction performance ST0 (Fig. 21(a)), the first step performance ST1 begins as the first stage. The first step performance ST1 is made up of a first first half performance ST1A and a first second half performance ST1B, with the first first half performance ST1A being executed first. In this first first half performance ST1A, a scene is played in which the first character, an elephant, fires an arrow (Fig. 21(b1)), and if the arrow hits a balloon (Fig. 21(d1)), it is determined that the performance step will end at the first stage, and the first second half performance ST1B is executed. The second half performance, including this first second half performance ST1B, will be described later.

[0289] On the other hand, if the arrow shot by the elephant does not hit the balloon (FIG. 21(c1)), the first second half performance ST1B is not executed, and the second first half performance ST2A of the second step performance ST2 is started as the second stage. In this second first half performance ST2A, a scene in which the second character, a lion, shoots an arrow is performed (FIG. 21(b2)). If the arrow hits the balloon (FIG. 21(d2)), it is determined that the performance step ends at that second stage, and the second second half performance ST2B is executed. In this way, arrows are shot in the order of the elephant, lion, fox, squirrel, and bear until the arrow shot by any character hits the balloon (FIGS. 21(b1)-(b5)). When the arrow hits the balloon (FIGS. 21(d1)-(d5)), it is determined that the performance step ends at that stage, and the second half performances ST1B-ST5B corresponding to that stage are executed. In addition, since the step-up preview performance in this embodiment only exists up to the fifth stage, the arrow shot by the bear in at least the fifth first half performance ST5A will definitely hit the balloon (Figure 21 (d5)).

[0290] In addition, in the step-up preview performance of this embodiment, multiple types (here, five types of each) of the first to fifth latter half performances ST1B to ST5B are provided, and one of the multiple types is selected depending on the reliability of the occurrence of a specified event (here, the reliability of a jackpot).

[0291] FIG. 22 illustrates five types of modes (variations) for each of the third second half performance ST3B and the fifth second half performance ST5B among the first to fifth second half performances ST1B to ST5B. Of course, similar variations using the respective characters are prepared for the other first, second, and fourth second half performances ST1B, ST2B, and ST4B, but they are omitted here. In the first to fifth second half performances ST1B to ST5B, the reserved pedestal image 168 is displayed at the lower side of the display screen DSa, and the mini pattern 165 is displayed at the upper side of the display screen DSa, and the first and second reserved images X1 to X4, Y1 to Y4, etc. are displayed in front of the reserved pedestal image 168, and the step-up notice performance image 169 is displayed behind the reserved pedestal image 168 and the mini pattern 165. However, in the first half performance, the reserved pedestal image 168 may be displayed, and the reserved pedestal image 168 may not be displayed during the second half performance. This makes it possible to enlarge the display area of ​​the latter half performance for displaying the jackpot reliability, and to execute a more impactful display performance. In the first to fifth latter half performances ST1B to ST5B, the decorative pattern 164 during the change is not displayed.

[0292] The five types of third second half performances ST3Ba to ST3Be shown in Figures 22 (a1) to (e1) have in common the step-up preview performance image 169 in that it features a fox, which is the character of the third step performance ST3, and in the basic screen layout centered around the fox and a specified text image, but they differ in the content of the displayed text image, the display mode of the text image (here, the display color), and the display color (base color) of at least a portion of the step-up preview performance image 169.

[0293] That is, the step-up notice performance images 169 of the third latter half performances ST3Ba to ST3Be shown in Fig. 22(a1) to (e1) are common in that the character image of a fox is displayed large in a positional relationship that divides the background image into a left background image and a right background image, and a character image consisting of a predetermined line string (which may be composed of only one character) is displayed horizontally in front of the character image (fox) and the background image so as to straddle them. On the other hand, the content of the line string is different for all five types, and the content of the line string corresponding to the third latter half performances ST3Ba to ST3Be is "Good things are going to happen," "Okay, let's do our best," "Even better things are going to happen," "It's going to be okay," and "I feel great." In addition, the display color (display mode) of the line string is also different for all five types, and the display color (inner color of the character) of the line string corresponding to the third latter half performances ST3Ba to ST3Be is "blue," "red," "gold," "danger color," and "rainbow color (rainbow)." Here, the "danger colors" refer to a striped color scheme made up of multiple colors different from the colors of the rainbow, and in this embodiment, the three colors yellow, black, and red are arranged in diagonal stripes.

[0294] Furthermore, for the step-up notice performance image 169 of the third latter half performance ST3Ba to ST3Bd (FIGS. 22(a1) to (d1)) other than the third latter half performance ST3Be (FIG. 22(e1)), the base color corresponds to the display color of the dialogue character string, and the colors "blue", "red", "gold", and "danger color" are used in at least a part (right background image, etc.) of the step-up notice performance image 169 corresponding to the respective character colors "blue", "red", "gold", and "danger color". Here, the "danger color" as the base color is the same as the "danger color" as the character color in that it is composed of three colors, yellow, black, and red, but the striped color scheme is only yellow and black, and the character string "DANGER" is continuously arranged in red on the black line, so that it is different from the "danger color" as the character color. Note that the configuration of the danger color is not limited to this, and it may be different from other character colors / base colors.

[0295] Furthermore, the five types of the fifth second half performances ST5Ba to ST5Be shown in Figures 22 (a2) to (e2) have in common the step-up preview performance image 169 in that a bear, which is the character of the fifth step performance ST5, appears, and that the basic screen layout is centered around the bear and a specified text image. However, the content of the text image displayed on the screen, the display mode of the text image (here, the display color), and the display color (base color) of at least a portion of the step-up preview performance image 169 are different.

[0296] That is, the step-up notice performance images 169 of the fifth latter half performances ST5Ba to ST5Be shown in Fig. 22(a2) to (e2) are common in that a bear character image is displayed large in a positional relationship that divides the background image into a left background image and a right background image, and a character image consisting of a predetermined line character string (which may be composed of only one character) is displayed horizontally in front of the character image (bear) and the background image so as to straddle them. On the other hand, the content of the line character string is different for all five types, and the content of the line character string corresponding to the fifth latter half performances ST5Ba to ST5Be is "Maybe we can do it," "A little bit more," "I'm feeling refreshed," "I'm excited," and "Very satisfied!". In addition, the display color of the line character string is also different for all five types, and the display color (inner color of the character) of the line character string corresponding to the fifth latter half performances ST5Ba to ST5Be is "blue," "red," "gold," "danger color," and "rainbow color (rainbow)." As described above, the contents of the dialogue character strings in the fifth second half performances ST5Ba to ST5Be are all different from the contents of the dialogue character strings in the third second half performances ST3Ba to ST3Be, but the contents of at least some of the dialogue character strings may be common.

[0297] Furthermore, for the step-up preview performance images 169 of the fifth second half performances ST5Ba to ST5Bd (Figures 22 (a2) to (d2)) other than the fifth second half performance ST5Be (Figure 22 (e2)), the base color of the screen corresponds to the display color of the dialogue string, and the colors "blue," "red," "gold," and "danger color" are used in at least a part of the screen (such as a part of the background image) corresponding to the respective text colors of "blue," "red," "gold," and "danger color."

[0298] Here, the jackpot reliability is set to gradually increase from the third latter half performance ST3Ba to ST3Be and from the fifth latter half performance ST5Ba to ST5Be. That is, the relationship between the display color of the dialogue string and the jackpot reliability increases in the order of "blue", "red", "gold", "danger", and "rainbow". Incidentally, "rainbow" indicates that the jackpot reliability is 100%, that is, that the jackpot is confirmed. In this way, the third latter half performance ST3Ba to ST3Be and the fifth latter half performance ST5Ba to ST5Be have different jackpot reliability according to the display color of the dialogue string, so that the character image (specific character information) or the step-up notice performance image 169 having the character image can be said to be a specific image having reliability information regarding the jackpot. The same is true for the other first, second, and fourth latter half performances.

[0299] In this way, for example, the third latter half performance ST3Ba (FIG. 22(a1)) and the fifth latter half performance ST5Ba (FIG. 22(a2)) are examples of the A-1 reliability specific image corresponding to the A-1 reliability, and the third latter half performance ST3Bb (FIG. 22(b1)) and the fifth latter half performance ST5Bb (FIG. 22(b2)) are examples of the A-2 reliability specific image corresponding to the A-2 reliability. In this embodiment, the five display colors "blue", "red", "gold", "danger color", and "rainbow" used in this step-up notice performance are a full lineup of reliability information related to a jackpot (reliability information related to the occurrence of a predetermined event), and are set so that the jackpot reliability increases in that order, but in other notice performances, it is not necessary to use all of the five display colors as reliability information, and only some of the colors such as "red" and "gold" may be used. However, even in that case, the relationship of the high and low reliability of the jackpot (for example, "gold" is higher than "red") is assumed to remain unchanged.

[0300] The base color of the step-up notice performance image 169 does not need to be completely the same as the text color, and may be a similar color. Also, for the third latter half performance ST3Be, the fifth latter half performance ST5Be, etc., in which the text color is "rainbow," the base color of the screen may be made to correspond to the text color by making at least a part of the display color other than the dialogue text "rainbow." Also, in this embodiment, the display modes other than the display color of the dialogue text, such as the font and size of the dialogue text, are approximately common to the five types of the third latter half performance ST3Ba to ST3Be, the fifth latter half performance ST5Ba to ST5Be, etc., but other display modes (fonts, etc.) may be made different along with the text color, or the text color may be approximately the same and other specific display modes (fonts, etc.) may be made different, and the specific display modes may be used as reliability information.

[0301] Next, a specific example of the step-up notice performance will be described by taking the case where the performance step progresses to the third stage and ST3Bc (Fig. 22(c1)) is selected as the third latter half performance as an example, but first, an overview will be described with reference to Fig. 23. When the step-up notice performance starts during normal fluctuation in the reach fluctuation pattern, the speaker starts outputting BGM1 related to this step-up notice performance as BGM, and on the display screen DSa, the decorative pattern 164 during high speed fluctuation is hidden, and the reserved pedestal image 168 is displayed on the lower end side, and the mini pattern 165 is displayed on the upper end side, and behind them, a performance image related to the step-up introduction performance ST0 is displayed (Fig. 23(a)).

[0302] In this step-up introduction performance ST0, five kinds of characters, an elephant, a lion, a fox, a squirrel, and a bear, corresponding to the five performance steps, are lined up, and a step-up advance notice performance image 169 is displayed in which each character is preparing to shoot an arrow at a balloon. A player who sees this can recognize that this is a step-up advance notice performance in which the performance steps proceed until one of the characters pops the balloon. In addition, in this step-up introduction performance ST0 (FIG. 23(a)), for example, at the start, a predetermined introduction sound is output from the speaker as a sound effect. Furthermore, during this step-up introduction performance ST0 (FIG. 23(a)), at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) emits light in an introduction light-emitting mode corresponding to this step-up introduction performance ST0, for example, orange. Note that "at least a part of the performance lamps L" may be only one of the frame side lamps La and the board side lamps Lb, or both, or at least one of a part of the frame side lamps La and a part of the board side lamps Lb. This also applies to all the following explanations.

[0303] Following the step-up introduction performance ST0 (FIG. 23(a)), one or more step performances from the first stage to a predetermined stage, here the first step performance ST1 to the third step performance ST3, are executed in sequence. That is, first, the first first half performance ST1A of the first step performance ST1 starts as the first stage (FIG. 23(b)). In this first first half performance ST1A, the first character, an elephant, fires an arrow at a balloon, but is unable to hit the balloon.

[0304] Also, during this first first half performance ST1A (Figure 23(b)), for example at the start, a predetermined first start sound is output from the speaker as a sound effect, and following this first start sound, a first first half voice such as "Let's go" is output as a dialogue sound. Note that the output of the first first half voice may start after the output of the first start sound has ended, or may start while the first start sound is being output. Furthermore, during this first first half performance ST1A (Figure 23(b)), at least a part of the performance lamps L (here, both the frame-side lamps La and the board-side lamps Lb) emit light in a first half light-emitting mode corresponding to the first half performance (first light-emitting mode corresponding to the first half performance), for example in green.

[0305] When the elephant's arrow misses the balloon, the first first half performance ST1A ends, and the second first half performance ST2A of the second step performance ST2 begins (FIG. 23(c)). In this second first half performance ST2A, the second character, the lion, fires an arrow at the balloon, but just like the first step performance ST1, he is unable to hit the balloon.

[0306] During this second first half performance ST2A (Figure 23(c)), for example at the start, a predetermined second start sound is output from the speaker as a sound effect, and following the second start sound, a second first half voice such as "This time for sure" is output as a dialogue sound. The second start sound may be the same as the first start sound or may be different. Also, the output of the second first half voice may start after the output of the second start sound has ended, or may start while the second start sound is being output. Furthermore, during this second first half performance ST2A (Figure 23(c)), at least a portion of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) continue to emit light in a first half light emission mode corresponding to the first half performance, for example green.

[0307] When the arrow shot by the lion misses the balloon, the second first half performance ST2A ends, and the third first half performance ST3A of the third step performance ST3 starts (FIG. 23(d)). In this third first half performance ST3A, the third character, the fox, fires an arrow at the balloon, and in the example of FIG. 23, the arrow hits the balloon perfectly (FIG. 23(d)).

[0308] Also, during this third first half performance ST3A (FIG. 23(d)), for example, at the start, a predetermined third start sound is output from the speaker as a sound effect, and further, following the third start sound, a third first half voice such as "How is it?" is output as a dialogue sound. The third start sound may be the same as the first and second start sounds, or may be different. Also, the output of the third first half voice may start after the output of the third start sound ends, or may start during the output of the third start sound. Furthermore, during this third first half performance ST2A (FIG. 23(d)), at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) continue to emit light in a first half light-emitting mode corresponding to the first half performance, for example, green light, until just before the arrow hits the balloon, and then transition to a first half end light-emitting mode, for example, a short-time off state, when the arrow hits the balloon or just before that.

[0309] The first half light emission state may be different for each of the first half performances ST1A to ST5A. In this case, the light emission state may be changed, for example, when the second start sound, the third start sound, etc. are generated. By configuring in this way, it is possible to configure so that the player can easily sense the step-up stage. Also, the light emission state may be temporarily changed when the second start sound, the third start sound, etc. are generated. In this case, the light emission state does not change in the first to fifth first half performances ST1A to ST5A, but at least before and after the timing when the second start sound, the third start sound, etc. are output, the light emission state will be different (for example, white). By configuring in this way, it is possible to configure so that the player can easily sense that the step-up stage has changed.

[0310] When the arrow hits the balloon (Fig. 23(d)), it is determined that the performance step ends at the third stage, and at that timing (first timing), a high-brightness performance WO11 (first high-brightness performance) (Fig. 23(e)) is performed, and during (or after) the high-brightness performance WO11, one of multiple types (here, five types) of third latter half performances ST3Ba to ST3Be, here the third latter half performance ST3Bc, is executed (Fig. 23(f)). That is, the high-brightness performance WO11 is executed at the timing (first timing) when the first scene image of the first half performance switches to the second scene image of the latter half performance.

[0311] Here, the high-brightness effect is an effect that reduces the visibility of an image (here, step-up preview effect image 169) behind the high-brightness image 170 by displaying the high-brightness image 170. All of the high-brightness effects in this embodiment are so-called whiteouts, and use a white high-brightness image 170, but the color of the high-brightness image may be any color other than white, such as gray, yellow, blue, red, etc., or may be composed of multiple colors. Also, there may be cases where no image is displayed behind the high-brightness image 170.

[0312] In the high-brightness performance WO11, the high-brightness image 170a is displayed in front of the step-up notice performance image (specific image) 169 and behind the mini pattern 165, the reserved pedestal image 168, and the reserved images X1 to X4, Y1 to Y4 in front of them, so that the visibility of the step-up notice performance image (specific image) 169 can be changed without changing the visibility of the reserved images X1 to X4, Y1 to Y4, and the mini pattern 165. This is the same for other high-brightness performances described later. In the high-brightness performance WO11, the common high-brightness image 170a is displayed regardless of which of the third latter half performances ST3Ba to ST3Be is selected. The same is true for the other first, second, fourth, and fifth latter half performances.

[0313] However, the present invention is not limited to this, and the visibility of the mini pattern 165, the reserved images X1-, Y1-, and the reserved pedestal image 168 may be reduced by displaying the high-brightness image 170 in front of at least one of them. In this case, the high-brightness image 170 may be displayed in front of the reserved pedestal image 168 and behind the reserved images X1-, Y1-. This makes it possible to execute a high-brightness performance with a wider range and more impact without reducing the visibility of at least the reserved images X1-, Y1-. In addition, it is preferable to configure the display area that does not overlap with the high-brightness image 170 to be smaller than the area in which the high-brightness image 170 is displayed. This makes it possible to give a stronger impression of the image behind being concealed by the high-brightness image 170. In addition, it is preferable to set the display area that does not overlap with the high-brightness image 170 as an area in which information suggesting reliability (text information, character images, and other images displayed in a reliability color) is not located among the images of the third latter half performance ST3B that will be displayed thereafter. This allows the high-brightness image 170 to have a concealing effect without concealing the entire area of ​​the display screen with the high-brightness image 170.

[0314] The high-brightness image 170 is displayed in white in a predetermined range on the screen, and is set to an arbitrary transmittance within the range. The transmittance of the high-brightness image 170 may be uniform or non-uniform within the display range. When the transmittance of the high-brightness image 170 is non-uniform, the transmittance and / or the rate of change in the transmittance of the high-brightness image 170 may be different between an area where information suggesting reliability (text information, character images, other images displayed in a reliability color) is located and the other area. In this case, it is desirable to configure the transmittance and / or the rate of change in the transmittance to be lower in an area where information suggesting reliability (text information, character images, other images displayed in a reliability color) is located. In addition, the transmittance and / or the rate of change in the transmittance may be lower in an area where particularly important text information or other images displayed in a reliability color among information suggesting reliability is located than in an area where a character image is located, or vice versa. In this way, by making the transmittance and the rate of change of the transmittance of the high-brightness image different depending on the display position, it is possible to prevent the high-brightness presentation from becoming monotonous. Also, it is possible to make the display content of the image of the third latter half presentation ST3B, for example, understand from the high and low transmittance and the rate of change of the transmittance, and it is possible to make the high-brightness presentation more complex and interesting.

[0315] The size (display range) of the high-brightness image can be changed over time, and the transmittance value and the transmittance distribution can also be changed over time. If the transmittance of the high-brightness image 170 is 0%, the image behind the high-brightness image 170 becomes completely invisible, and if the transmittance of the high-brightness image 170 is 100%, the high-brightness image 170 itself becomes completely invisible. Therefore, if the transmittance of a specific portion of the high-brightness image 170 is 100%, it can be considered that the specific portion is not a part that constitutes the high-brightness image 170 in the first place. If the transmittance of a specific portion of the high-brightness image 170 changes from a value less than 100% to 100%, it can be considered that the specific portion is out of the range of the high-brightness image 170 when it reaches 100%.

[0316] During the high brightness performance WO11 (FIG. 23(e)), the output of BGM1 related to the step-up notice performance continues. During the high brightness performance WO11, a predetermined emphasis sound is output as a sound effect, and this predetermined emphasis sound is selected from the first to fifth predetermined emphasis sounds according to reliability information related to the jackpot in the latter half performance (for example, according to which of ST3Ba to ST3Be is selected in the case of the third latter half performance). That is, when an image (first reliability specific image) relating to the third latter half performance ST3Ba (FIG. 22(a1)) is displayed during the display of the high brightness image 170a, a first predetermined emphasis sound corresponding to the image (first reliability specific image) relating to the third latter half performance ST3Ba can be output (first sound performance), and when an image (second reliability specific image) relating to the third latter half performance ST3Bc (FIG. 22(c1)) is displayed during the display of the high brightness image 170a, a third predetermined emphasis sound corresponding to the image (second reliability specific image) relating to the third latter half performance ST3Bc can be output (second sound performance). This has the advantage that the reliability information can be notified to the player in advance by sound during the high brightness performance WO11 where the dialogue character string (character information) is still not visible or difficult to see, and the performance effect is improved.

[0317] Also, a common predetermined emphasis sound may be output for each jackpot reliability in the latter half performance. For example, a common first predetermined emphasis sound may be output when displaying an image (first reliability specific image) related to the third latter half performance ST3Ba (Fig. 22(a1)), when displaying an image (first reliability specific image) related to the third latter half performance ST3Bb (Fig. 22(b1)), and when displaying an image (first reliability specific image) related to the third latter half performance ST3Bc (Fig. 22(c1)), and a common second emphasis sound may be output when displaying an image (first reliability specific image) related to the third latter half performance ST3Bd (Fig. 22(d1)), and when displaying an image (first reliability specific image) related to the third latter half performance ST3Be (Fig. 22(e1)). This allows the player to be notified of the expected reliability information in advance by the contents of the predetermined emphasis sound, which has the advantage of improving the performance effect.

[0318] The first to fifth predetermined emphasis sounds may be configured so that the higher the jackpot reliability is based on the reliability information on the jackpot in the latter half performance, the larger the output volume and / or output time. In this case, the third predetermined emphasis sound (first specific sound) output when the high brightness performance WO11 is executed (second first high brightness performance) during the third latter half performance ST3Bc (FIG. 22(c1)) is larger in output volume and / or output time than the first predetermined emphasis sound (second specific sound) output when the high brightness performance WO11 is executed (second second high brightness performance) during the third latter half performance ST3Ba (FIG. 22(a1)).

[0319] Also, the first to fifth predetermined emphasis sounds may be configured to be accompanied by a vibration effect by activating the vibration means as the jackpot reliability is higher based on the reliability information regarding the jackpot in the latter half performance. For example, the first to third predetermined emphasis sounds may be configured not to be accompanied by a vibration effect, and the fourth to fifth predetermined emphasis sounds may be configured to be accompanied by a vibration effect. Also, only the fifth predetermined emphasis sound may be configured to be accompanied by a vibration effect. Here, the vibration means can be configured to vibrate a predetermined part such as the chance button 11. Also, when two types of predetermined emphasis sounds, the first predetermined emphasis sound and the second predetermined emphasis sound, are used, only one of the second predetermined emphasis sounds may be configured to be accompanied by a vibration effect. Also, it is not necessary to always accompany the vibration effect, and there may be cases where a vibration effect is performed or not performed together with the execution of the predetermined emphasis sound. More preferably, it is desirable to configure the vibration effect to be accompanied only when the expectation of a jackpot is high.

[0320] Also, during the high-brightness performance WO11 (first high-brightness performance), at least a part of the performance lamps L (here, both the frame-side lamps La and the board-side lamps Lb) emits light in the first high-brightness medium light-emitting mode (the first light-emitting mode corresponding to the high-brightness performance) (the first light-emitting performance in which the light-emitting means is illuminated in the first light-emitting mode, the first light-emitting performance). In this embodiment, the first high-brightness medium light-emitting mode during the high-brightness performance WO11 is a cyclic change mode that cyclically changes to multiple colors (e.g., three colors: gold, green, and white) including the character color (e.g., gold) of the third latter half performance ST3B. Note that the first high-brightness medium light-emitting mode may be a single color such as gold, as long as it includes a color corresponding to the character color (e.g., gold) of the third latter half performance ST3B. This has the advantage that the reliability information can be notified to the player in advance by emitting light during the high-brightness performance WO11 in which the dialogue character string (character information) is still not visible or difficult to see, improving the performance effect. When the effect lamp L is illuminated in a color corresponding to an image, the color of the light does not have to be exactly the same as the color of the image, as long as it is a similar color (for example, yellow for a gold image).

[0321] As described above, during the third second half performance ST3Bc (Figure 23 (f)) after the end of the high-brightness performance WO11, a step-up preview performance image 169 is displayed in which a fox character image is displayed large in a position that divides the background image into a left background image and a right background image, and a line of dialogue saying "It feels like something even better is going to happen" is displayed in "gold" in front of the character image (fox) and the background image, spanning them.

[0322] During this third latter half performance ST3Bc (FIG. 23(f)), the output of BGM1 related to the step-up preview performance continues, and a predetermined third latter half voice is output as a dialogue sound. This third latter half voice corresponds to the dialogue string (text information) displayed on the screen, and in this case, "It seems like something even better could happen" is output. When this dialogue sound is output, it is desirable to have the character image perform a so-called lip-syncing action (speaking action).

[0323] Furthermore, during the third latter half performance ST3Bc (FIG. 23(f)), at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) emit light in a second half light-emitting mode (third light-emitting mode corresponding to a specific image) corresponding to the third latter half performance ST3Bc, for example, in a cyclic change mode in which the color of the text (here, gold) of the third latter half performance ST3Bc is cyclically changed (here, three colors: gold, green, and white). In this way, the second half light-emitting mode may be the same as the previous first high brightness medium light-emitting mode or may be different, but it is preferable to configure it so that it includes the text color (here, gold) of the third latter half performance ST3Bc. As a result, even after the display of the image performance of the third latter half performance ST3Bc has ended, it is possible to perform a light-emitting performance with a light-emitting mode corresponding to the text color (here, gold) indicating the degree of expectation, and it is possible to execute a notification with the text color (here, gold) indicating the degree of jackpot reliability as much as possible for players who missed the image performance. Moreover, it is desirable that the light color of this latter half light-emitting mode does not include colors corresponding to other latter half performances (here, blue, red, danger color, rainbow color). The latter half light-emitting mode may be configured with only a light color corresponding to the text color (e.g., gold). It may also be configured not to include the text color of the third latter half performance ST3Bc (here, gold), which makes it possible to visually sense that the performance period of the third latter half performance ST3Bc has ended.

[0324] After the third latter half performance ST3Bc is executed, the high-brightness performance WO12 (A second high-brightness performance) is executed at that timing (second timing) (FIG. 23(g)), and during the execution of the high-brightness performance WO12, the step-up notice performance image 169 related to the third latter half performance ST3Bc is switched to a variable screen of the decorative pattern 164 (specific image end performance) (FIG. 23(h)). Here, the high-brightness performance WO12 is different from the high-brightness performance WO11 in the display area of ​​the high-brightness image and the rate of change of the transmittance. This makes it possible to clearly express the start and end of the latter half performance. Note that the high-brightness performance WO12 has the same minimum transmittance value (0%) as the high-brightness performance WO11, but this may also be different. Also, the high-brightness performance WO12 may have the same display area of ​​the high-brightness image as the high-brightness performance WO11. Also, the transmittance (minimum value) and / or the rate of change of the transmittance may be the same. This makes it possible to give the player a sense of expectation that the latter half of the performance may still continue. Also, it is desirable that the high-brightness performance WO12 is displayed so that at least the area where the information suggesting the reliability of the latter half of the performance (text information, character images, other images displayed in a reliability color) is located is concealed by the high-brightness image. This makes it possible to end the latter half of the performance without a sense of incongruity and transition to the pattern variation screen. Also, it may be configured so that at least the area where any one of the information suggesting the reliability of the latter half of the performance (text information, character images, other images displayed in a reliability color) is located is concealed by the high-brightness image.

[0325] During the high brightness performance WO12 (FIG. 23(g)), for example, the output of BGM is stopped. During the high brightness performance WO12, a specific emphasis sound is output as a sound effect, and this specific emphasis sound is selected from the first to fifth specific emphasis sounds according to the reliability information on the jackpot in the latter half performance (for example, according to which of ST3Ba to ST3Be is selected in the case of the third latter half performance). During the high brightness performance WO12, a common specific emphasis sound may be output as a sound effect. That is, regardless of the contents of the reliability information on the jackpot in the latter half performance, a common specific emphasis sound may be output. As a result, for example, during the high brightness performance WO11, a different predetermined emphasis sound is output according to the reliability information on the jackpot in the latter half performance, while during the high brightness performance WO12, a common specific emphasis sound can be output regardless of the reliability information on the jackpot, making it possible to perform expressions using different performance effects in the high brightness performance WO11 and the high brightness performance WO12. In addition, the predetermined emphasis sound in the high brightness effect WO11 may be configured to be common regardless of the reliability information regarding the jackpot, and the specific emphasis sound in the high brightness effect WO12 may be configured to be different depending on the reliability information regarding the jackpot.

[0326] The first to fifth specific emphasis sounds may be configured so that the higher the jackpot reliability is based on the reliability information on the jackpot in the latter half performance, the larger the output volume and / or output time. In this case, the third specific emphasis sound (first specific sound) output when the high brightness performance WO12 is executed (second first high brightness performance) during the third latter half performance ST3Bc (FIG. 22(c1)) is larger in output volume and / or output time than the first specific emphasis sound (second specific sound) output when the high brightness performance WO12 is executed (second second high brightness performance) during the third latter half performance ST3Ba (FIG. 22(a1)). Also, the first to fifth specific emphasis sounds in the high brightness performance WO12 may be different from or the same as the first to fifth predetermined emphasis sounds in the high brightness performance WO11.

[0327] Furthermore, during the high-brightness performance WO12 (second high-brightness performance), at least a part of the performance lamps L (here, both the frame-side lamps La and the board-side lamps Lb) emits light in a second high-brightness medium light-emitting mode (second light-emitting mode), for example, in a cyclic change mode that cyclically changes to a plurality of colors (here, three colors: gold, green, and white) including the text color (here, gold) of the third latter half performance ST3Bc (specific light-emitting performance in which the light-emitting means emits light in a specific light-emitting mode according to a specific image). In this way, the latter half light-emitting mode may be the same as the first high-brightness medium light-emitting mode and the latter half light-emitting mode, or may be different, but it is preferable to configure it so that it includes the text color (here, gold) of the third latter half performance ST3Bc. In addition, the latter half light-emitting mode may be configured so that it does not include the text color (here, gold). In addition, by configuring the first high-brightness medium light-emitting mode to include the text color and the latter half light-emitting mode to not include the text color, it is possible to avoid the performance expression becoming monotonous and prevent a decrease in the performance effect.

[0328] When the symbol changing screen starts after the high-brightness effect WO12, a symbol stopping sound is output as a sound effect in accordance with the stopping of the decorative symbols 164a to 164c.

[0329] Next, the step-up notice performance shown in FIG. 23 will be described in more detail with respect to the performance period centered on the high-brightness performances WO11 and WO12. FIG. 24 to FIG. 26 show the change in the display screen and the light-emitting means at even shorter time intervals than FIG. 23 for the period of FIG. 23(e) to (h), that is, the period from the start of the high-brightness performance WO11 to the end of the high-brightness performance WO12 and the transition to the variable screen of the decorative pattern 164. Note that the display images of 22 frames shown in FIG. 24 to FIG. 26 do not show all the frames in the period of FIG. 23(e) to (h), but are extracted from all the frames at a constant pitch. Therefore, in FIG. 24 to FIG. 26, the time intervals between adjacent frames are all the same (here, A milliseconds). Thus, in Figures 24 to 26, when the number of frames doubles, the time also doubles. For example, the elapsed time between Figures 24(a) to (c) is the same as between Figures 24(d) to (f), but the elapsed time between Figures 24(a) to (c) and Figures 24(d) to (g) is longer than the former.

[0330] First, the details of the high-brightness performance WO11 will be described. In the high-brightness performance WO11 shown in Fig. 24(a) to Fig. 25(j), at the start, a high-brightness image 170a is displayed in front of the step-up notice performance image (specific image) 169 and behind the mini pattern 165, the reserved pedestal image 168, and the reserved images X1 to X4, Y1 to Y4 in front of it (Fig. 24(a)) (high-brightness image display process), and the size (range) and transmittance of the high-brightness image 170a gradually change and finally disappear (Fig. 24(j)).

[0331] The high-brightness image 170a is configured so that its size (range) is maximum at the start of display (FIG. 24(a)) and gradually decreases over time. That is, the high-brightness performance WO11 is configured with an enlargement change performance that changes the size (range) of the high-brightness image 170a in the enlargement direction and a reduction change performance that changes the size (range) of the high-brightness image 170a in the reduction direction, and the execution time of the latter (FIGS. 24(a) to 25(j)) is longer than that of the former (FIG. 24(a)). In the high-brightness performance WO11, the coverage rate of the high-brightness image 170a with respect to the entire step-up notice performance image 169 is less than 100%, and even when the size (range) of the high-brightness image 170a is maximum (FIG. 24(a)), a part of the step-up notice performance image 169 is visible from the front. Of course, when the size (range) of the high-brightness image 170a is maximum, the coverage rate of the high-brightness image 170a with respect to the entire step-up notice performance image 169 may be 100%. Also, it is sufficient that part of the predetermined information (text information, character image, reliability color display image, etc.) in the step-up notice performance image is concealed by the high-brightness image 170a, making it difficult to perceive and / or to see, and it is not necessary that all of the predetermined information is concealed.

[0332] The high-brightness image 170a is set so that the transmittance is approximately uniform within its range. The high-brightness image 170a is configured so that not only its size (range) but also its transmittance changes over time (transmittance change processing, transmittance change performance), with the transmittance at the start of display (FIG. 24(a)) being minimum (e.g., 0%) and gradually increasing (rising) at a constant rate over time. That is, the high-brightness performance WO11 is composed of a low-transmittance change performance that changes the transmittance of the high-brightness image 170a in a decreasing direction and a high-transmittance change performance that changes the transmittance of the high-brightness image 170a in an increasing direction, and the latter (FIGS. 24(a) to 25(j)) takes longer to execute than the former (FIG. 24(a)).

[0333] The minimum transmittance of the high-brightness image 170a may be greater than 0%. The rate of change (amount of change per unit time) of the transmittance of the high-brightness image 170a may not be constant. The transmittance of the high-brightness image 170a may be non-uniform, and the non-uniform transmittance may be changed over time. The size (range) of the high-brightness image 170a may be changed without changing the transmittance, or the transmittance may be changed without changing the size (range) of the high-brightness image 170a. However, the reduction in the size (range) of the high-brightness image 170a means that the transmittance of a part of the high-brightness image 170a increases and reaches 100%, and the part can be considered to have essentially disappeared. Therefore, changing the size (range) of the high-brightness image 170a can be said to essentially change the transmittance of the high-brightness image 170a.

[0334] In the high-brightness performance WO11, the step-up notice performance image 169 displayed behind the high-brightness image 170a is switched from the previous image of the third first half performance ST3A (see FIG. 23(d)) to the image of the third second half performance ST3Bc (see FIG. 22(c1)) when the high-brightness image 170a starts to be displayed (FIG. 24(a)). As a result, after the start of the high-brightness performance WO11, the size (range) of the high-brightness image 170a gradually decreases, and as the transmittance also gradually increases, the visibility of the step-up notice performance image 169 improves, and when the high-brightness image 170a eventually disappears (FIG. 25(j)), the entire step-up notice performance image 169 (excluding the part hidden behind the mini pattern 165, etc.) becomes completely visible.

[0335] Also, during the high-brightness performance WO11, the performance lamp L emits light in the first high-brightness medium light-emitting mode. The first high-brightness medium light-emitting mode is a cyclic change mode that cyclically changes to multiple colors (e.g., three colors: gold, green, and white) including the text color (e.g., gold) of the third latter half performance ST3Bc, and the light-emitting color changes in the order of green (FIG. 24(a)-(c)), white (FIG. 24(d)-(f)), and gold (FIG. 24(g)-(i)) so that, for example, light emission in gold corresponding to the text color appears in the latter half or final stage of the high-brightness performance WO11. However, without being limited to this, the light-emitting mode of the performance lamp L, for example, the brightness and / or the light-emitting color, may be changed according to the change in the transmittance of the high-brightness image 170a. This allows the change in the transmittance of the high-brightness image 170a to be more closely associated with the change in the light-emitting mode, thereby enhancing the performance effect. Also, the light emission mode (e.g., brightness and light emission color) of the performance lamp L may be changed stepwise according to the change in the transmittance of the high-brightness image 170a. For example, when the transmittance of the high-brightness image 170a is 0% to 30%, the first light emission mode is selected, when it is 31% to 70%, the second light emission mode is selected, and when it is 71% to 99%, the third light emission mode is selected, and so on.

[0336] As described above, during the high-brightness performance WO11, the visibility of the step-up advance notice performance image 169 behind the high-brightness image 170a changes over time due to changes in the size (range) and / or transmittance of the high-brightness image 170a, and the text information constituting the step-up advance notice performance image 169 transitions from an invisible (or difficult to see) state to a visible (or easily visible) state at a predetermined time point (e.g., FIG. 24(d)). That is, during the high-brightness performance WO11, a first transmittance change process that changes the transmittance of the high-brightness image 170a while the text information is invisible (or difficult to see), and a second transmittance change process that changes the transmittance of the high-brightness image 170a while all of the text information is visible (or easily visible) can be executed, and the execution time differs between the former (e.g., FIG. 24(a)-(d)) and the latter (e.g., FIG. 24(d)-FIG. 25(j)), with the latter execution time being longer than the former. In this way, by making the execution time of the latter longer than that of the former, the text information in which the player is most interested can be disclosed to the player at an early stage, and the display time of the high-brightness image can be sufficiently provided, thereby enhancing the presentation effect of the high-brightness presentation itself.

[0337] The execution time of the first transmittance change process may be longer than that of the second transmittance change process, or the execution times of the first and latter processes may be approximately the same. By making the execution time of the first transmittance change process longer than that of the second transmittance change process, the disclosure of the text information can be delayed, which makes it possible to increase the player's sense of expectation and tension. Furthermore, once the text information has been revealed, it is desirable to disclose the entire information as soon as possible (to increase visibility so that the text information can be easily seen as soon as possible), so when the execution time of the first transmittance change process is set long, it is desirable to have a shorter execution time of the second transmittance change process.

[0338] The boundary between the state in which the text information is not visible (or difficult to see) and the state in which it is visible (or easily visible) may be defined as the text information becoming visible (or easily visible) when, for example, at least a part of the text information is no longer overlapped with the high-brightness image. Also, the text information may be defined as becoming visible (or easily visible) when the entirety of the text information is no longer overlapped with the high-brightness image.

[0339] During high-brightness performance WO11, a first range change process can be executed to change the size (range) of high-brightness image 170a while the text information is not visible (or difficult to see), and a second range change process can be executed to change the size (range) of high-brightness image 170a while all of the text information is visible (or easy to see), with the execution times of the former (e.g., Figures 24(a)-(d)) and the latter (e.g., Figures 24(d)-25(j)) being different, the latter being longer than the former. Note that the execution time of the first range change process may be longer than that of the second range change process, or the execution times of the former and latter may be approximately the same.

[0340] When the high brightness performance WO11 ends and the entire step-up preview performance image 169 for the third latter half performance ST3Bc becomes visible (FIG. 25(j)), the line sound (third latter half voice) of "Even better things could happen" corresponding to the line string (text information) displayed on the screen is output, and the step-up preview performance image 169 is dynamically displayed in response to the output of the line sound (post-execution dynamic display process, post-execution change process). That is, as shown in FIG. 25(j)-(o), while the line sound (third latter half voice) is being output, the fox character image performs a so-called lip-syncing action in accordance with the line sound, and the line string performs a predetermined action (here, each character swings). Also, the display color of the characters corresponding to the line sound being output temporarily changes (for example, from gold to white). As a result, it is recognized that the white part moves, for example, from left to right on the string of "Even better things could happen" displayed in gold. Note that the dialogue may be output without the character's lip-syncing.

[0341] When the post-execution dynamic display process (FIG. 25(j)-(o)) in the third latter half performance ST3Bc ends, the high-brightness performance WO12 starts. In the high-brightness performance WO12 shown in FIG. 25(o)-FIG. 26(v), similar to the high-brightness performance WO11, the high-brightness image 170b appears before the step-up notice performance image 169 and after the mini pattern 165, the reserved pedestal image 168, and the reserved images X1-X4, Y1-Y4 in front of them, and then disappears. However, the display pattern of the high-brightness image 170b in this high-brightness performance WO12 (second high-brightness performance) is different from the display pattern of the high-brightness image 170a in the high-brightness performance WO11 (first high-brightness performance), and the length of the execution time is also different. In addition, the high-brightness effect WO12 (second high-brightness effect), like the high-brightness effect WO11 (first high-brightness effect), may be configured to transition to a pattern-changing screen by displaying a high-brightness image with a low transmittance (e.g., 0%) for a short period of time, and then increasing the transmittance of the high-brightness image over a longer period of time.

[0342] That is, the high-brightness image 170b is configured so that its size (range) gradually increases over time, reaching a maximum at a predetermined time (Fig. 25(o) to Fig. 26(s)), and then gradually decreases over time and finally disappears (Fig. 26(s) to (v)). In this way, the high-brightness performance WO12 is configured with an enlargement change performance that changes the size (range) of the high-brightness image 170b in the enlargement direction, and a reduction change performance that changes the size (range) of the high-brightness image 170b in the reduction direction, and the execution time of the latter (Fig. 26(s) to (v)) is shorter than that of the former (Fig. 25(o) to Fig. 26(s)). In the high-brightness performance WO12, the coverage rate of the high-brightness image 170b with respect to the entire step-up notice performance image 169 is less than 100%, and even when the size (range) of the high-brightness image 170b is at its maximum (Fig. 26(s)), a part of the step-up notice performance image 169 is outside the range of the high-brightness image 170b. Of course, when the size (range) of the high-brightness image 170b is at its maximum, the coverage rate of the high-brightness image 170 relative to the entire step-up preview performance image 169 may be 100%.

[0343] The high-brightness performance WO12 (second high-brightness performance) and the high-brightness performance WO11 (first high-brightness performance) may be configured to have different coverage rates of high-brightness images with respect to the entire step-up preview performance image, and in this case, it is desirable that at least the information suggesting reliability (text information, character information, display suggesting reliability color) is covered by high-brightness images in both the high-brightness performance WO12 (second high-brightness performance) and the high-brightness performance WO11 (first high-brightness performance). Also, at the timing of executing the high-brightness performance WO12 (second high-brightness performance), the information suggesting reliability has already been disclosed, so there may be areas / ranges where this information is not hidden by the high-brightness images.

[0344] The high-brightness image 170b is set so that the transmittance is approximately uniform within its range. The high-brightness image 170b is configured so that not only its size (range) but also its transmittance changes (transmittance change processing, transmittance change performance), and the transmittance gradually decreases at a constant rate of change over time, for example, to a minimum (0% here) at a predetermined point in time (FIGS. 25(o) to 26(s)), and then gradually increases at a constant rate of change over time (FIGS. 26(s) to (v)). That is, the high-brightness performance WO12 is composed of a low-transmittance change performance that changes the transmittance of the high-brightness image 170b in a decreasing direction and a high-transmittance change performance that changes the transmittance of the high-brightness image 170b in an increasing direction, and the latter (FIGS. 26(s) to (v)) has a shorter execution time than the former (FIGS. 25(o) to 26(s)). Although the minimum transmittance of the high-brightness image 170b is set to 0% (FIG. 26(s)), it may be greater than 0%. Of course, the transmittance of the high-brightness image 170b may be made non-uniform, and the non-uniform transmittance may be changed over time. In addition, the execution time of the high transmittance change presentation may be longer than that of the low transmittance change presentation, or the execution times of both may be approximately the same.

[0345] Also, the size (range) may be changed without changing the transmittance of high-brightness image 170b, or the transmittance may be changed without changing the size (range) of high-brightness image 170b. However, since a reduction in the size (range) of high-brightness image 170b means that the transmittance of a part of high-brightness image 170b has increased to 100% and that part has essentially disappeared, changing the size (range) of high-brightness image 170b can be said to essentially change the transmittance of high-brightness image 170b.

[0346] In the high-brightness performance WO12, the step-up notice performance image 169 displayed behind the high-brightness image 170b is switched to a variable screen (see FIG. 23(h)) of the decorative pattern 164, for example, when the size (range) of the high-brightness image 170b becomes maximum and the transmittance becomes minimum (FIG. 26(s)), or at a timing close to that. As a result, after the start of the high-brightness performance WO12, the size (range) of the high-brightness image 170b gradually increases, and the transmittance also gradually decreases, so that the visibility of the step-up notice performance image 169 related to the third latter half performance ST3B decreases, and the screen is switched to the variable screen of the decorative pattern 164 at the point when the visibility of the step-up notice performance image 169 is at its lowest (FIG. 26(s)), or at a timing close to that. Then, the size (range) of the high-brightness image 170b gradually decreases, and the visibility of the changing screen of the decorative pattern 164 improves as the transmittance gradually increases, and when the high-brightness image 170b eventually disappears (FIG. 26(v)), the entire changing screen of the decorative pattern 164 (excluding the part hidden behind the mini pattern 165, etc.) becomes completely visible. In this way, during the execution of the high-brightness effect WO12, a specific image end effect is executed to end the display of the step-up notice effect image (specific image) 169.

[0347] In addition, during the third latter half performance ST3Bc after the high brightness performance WO11 ends (during dynamic display processing after execution), the performance lamp L emits light in the latter half emission mode, and during the subsequent high brightness performance WO12, the performance lamp L emits light in the second high brightness medium emission mode. In this embodiment, both the latter half emission mode and the second high brightness medium emission mode are common to the first high brightness medium emission mode, and are cyclic change modes that cyclically change to multiple colors (e.g., three colors: gold, green, and white) including the text color (e.g., gold) of the third latter half performance ST3Bc, and the emission color changes in the order of green (Figure 25(j) to (l)), white (Figure 25(m) to (o)), gold (Figure 25(p) to (r)), and green (Figure 26(s) to (u)). In addition, at least one of the latter half emission mode and the second high brightness medium emission mode may be made different from the first high brightness medium emission mode. However, even in this case, it is preferable that any light emission mode includes a color corresponding to the character color (for example, gold).

[0348] As described above, the step-up notice performance has a first half performance before displaying the step-up notice performance image 169 (specific image) having reliability information on the jackpot (i.e., text information whose display color and content differ according to the reliability of the jackpot), and a second half performance that displays the step-up notice performance image 169 (specific image) having the reliability information on the jackpot, and after the first half performance is executed, before or at the start of the second half performance, a high-brightness performance WO11 is executed in front of the specific image. Also, the performance lamp (light-emitting means) L emits light in a first half light-emitting mode (first light-emitting mode) corresponding to this first half performance in the first half performance, and emits light in a first high-brightness medium light-emitting mode (second light-emitting mode) corresponding to this high-brightness performance WO11 in the high-brightness performance WO11.

[0349] In the high-brightness performances WO11 and WO12 of the step-up notice performance, the high-brightness images 170a and 170b are displayed in front of the step-up notice performance image 169 (specific image) and behind the first and second reserved images (reserved images) X1-, Y1- and the mini pattern 165, thereby changing the visibility of the step-up notice performance image 169, while not changing the visibility of the first and second reserved images X1-, Y1- and the mini pattern 165. The high-brightness performance WO11 is composed of a low-transmittance change performance that changes the transmittance of the high-brightness image 170a in a decreasing direction, and a high-transmittance change performance that changes the transmittance of the high-brightness image 170a in an increasing direction, and the latter (FIGS. 24(a) to 25(j)) has a longer execution time than the former (FIG. 24(a)). On the other hand, in the high-brightness performance WO12, the execution time is shorter for the high-transmittance change performance (FIGS. 26(s) to (v)) than for the low-transmittance change performance (FIGS. 25(o) to 26(s)).

[0350] In addition, in the high-brightness performance WO11 of the step-up preview performance, it is possible to execute a high-brightness image display process (Figure 24(a)) that displays a high-brightness image 170a, and a transmittance change process (Figures 24(a) to 25(j)) that changes the transmittance of the high-brightness image 170a displayed by the high-brightness image display process.By increasing the transmittance of the high-brightness image 170a by the transmittance change process, the visibility of the step-up preview performance image 169 behind it is gradually improved. In addition, the step-up preview performance image 169 is provided with a character image (specific character information) having reliability information, and during the high-brightness performance WO11, a first transmittance change process can be executed which changes the transmittance of the high-brightness image 170a in a state in which the character information is not visible (or difficult to see), and a second transmittance change process can be executed which changes the transmittance of the high-brightness image 170a in a state in which all of the character information is visible (or easy to see), and the execution time of the former (e.g., Figures 24(a) to (d)) is different from that of the latter (e.g., Figures 24(d) to 25(j)), with the latter execution time being longer than the former.

[0351] In addition, in the step-up notice performance, it is possible to display any one of a plurality of types of specific images, including a step-up notice performance image (A-1 reliability specific image having A-1 reliability information corresponding to A-1 reliability) displayed in the third latter half performance ST3Ba (FIG. 22(a1)) and a step-up notice performance image (A-2 reliability specific image having A-2 reliability information corresponding to A-2 reliability higher than A-1 reliability) displayed in the third latter half performance ST3Bc (FIG. 22(c1)), and the high brightness image 170 in the high brightness performance WO11 While the third second half performance ST3Ba is displayed, the high-brightness image 170a is common to both the third second half performance ST3Ba and the third second half performance ST3Bb, and in the case of the third second half performance ST3Ba, a first predetermined emphasis sound corresponding to the image related to the third second half performance ST3Ba (first reliability level specific image) can be output (first sound performance), and in the case of the third second half performance ST3Bc, a third predetermined emphasis sound corresponding to the image related to the third second half performance ST3Bc (second reliability level specific image) can be output (second sound performance) while the high-brightness image 170a is displayed.

[0352] In addition, in the step-up notice performance, during execution of the high-brightness performance WO12, the step-up notice performance image 169 relating to the third latter half performance ST3Bc is switched to a variable screen of the decorative pattern 164, so that it is possible to execute a specific image end performance that ends the display of the step-up notice performance image 169 including the text image. Also, when executing the specific image end performance during execution of the high-brightness performance WO12, the performance lamp (light-emitting means) L is made to emit light (specific light-emitting mode) in the second high-brightness medium light-emitting mode (specific light-emitting mode according to the specific image) including the text color of the latter half performance.

[0353] In the step-up notice performance, a step-up notice performance image (specific image) 169 having reliability information on a big win is displayed during the execution of a high-brightness performance WO11 (first high-brightness performance), and then the display is terminated during the execution of a high-brightness performance WO12 (second high-brightness performance) (performance at the end of a specific image). The high-brightness performance WO11 and the high-brightness performance WO12 have different execution times, and in the examples of Figs. 24 to 26, the high-brightness performance WO11 has a longer execution time than the high-brightness performance WO12.

[0354] In addition, in the step-up preview performance, a step-up preview performance image 169 having jackpot reliability information is displayed while the high-brightness performance WO11 is being executed, and after the high-brightness performance WO11 ends, a post-execution dynamic display process is executed to dynamically display at least a part of the step-up preview performance image 169, and a post-execution change process (Figures 25(j) to (o)) is executed to make a predetermined change (color change) to at least a part of the step-up preview performance image 169.

[0355] In addition, in the step-up preview performance, it is possible to execute a high-brightness performance (A-1 high-brightness performance) WO11 that displays a high-brightness image (A-2 high-brightness image) 170a, and a high-brightness performance (A-2 high-brightness performance) WO12 that displays a high-brightness image (A-2 high-brightness image) 170b. The high-brightness performance (A-1 high-brightness performance) WO11 is executed at a first timing when the first scene image relating to the first half performance switches to the second scene image relating to the second half performance, and the high-brightness performance (A-2 high-brightness performance) WO12 is executed at a second timing thereafter.

[0356] In the step-up notice performance, during the high-brightness performance WO11, the display of a character image having jackpot reliability information is started, and when the display of the character image is ended, the high-brightness performance WO12 (performance at the end of a specific image) can be executed. During the high-brightness performance WO11, a first light-emitting performance is executed in which the performance lamp (light-emitting means) L is illuminated in a first high-brightness medium light-emitting mode (first light-emitting mode) corresponding to the reliability information (for example, display color) in the character image, and during the high-brightness performance WO12 (performance at the end of a specific image), a second light-emitting performance is executed in which the performance lamp (light-emitting means) L is illuminated in a second high-brightness medium light-emitting mode (second light-emitting mode). Note that the second high-brightness medium light-emitting mode (second light-emitting mode) may be different from the first high-brightness medium light-emitting mode (first light-emitting mode).

[0357] In the step-up preview performance, the third predetermined emphasis sound (first specific sound B) outputted when the high brightness performance WO11 is executed (first high brightness performance B) during the third latter half performance ST3Bc (Fig. 22(c1)) is larger in output volume and / or output time than the first predetermined emphasis sound (second specific sound B) outputted when the high brightness performance WO11 is executed (second high brightness performance B) during the third latter half performance ST3Ba (Fig. 22(a1)). It may be configured to execute the vibration performance substantially simultaneously with the third predetermined emphasis sound. It may also be configured to execute the vibration performance instead of the third predetermined emphasis sound.

[0358] The step-up preview performance is an example of a text information display performance that displays text information, and is capable of executing a high-brightness performance WO11 as a text information display start performance (first specific performance) that is performed when the display of text information begins, and a high-brightness performance WO12 as a text information display end performance (second specific performance) that is performed when the display of text information ends.After the high-brightness performance WO11 (text information display start performance) is executed, a display mode change process (specific display process that displays text information in a specific display mode) (Figures 25 (j) to (o)) is executed to change the display mode of the text information, and the display mode change process (specific display process) is not executed while the high-brightness performance WO12 (text information display end performance) is being executed.

[0359] In the above step-up preview performance, the number of variations of the reliability display that can be executed in the first to fifth latter half performances ST1B to ST5B is uniformly five (FIG. 22), but the number of variations of the reliability suggestion that can be executed in the first to fifth latter half performances ST1B to ST5B executed thereafter may be different depending on the contents of the first to fifth first half performances ST1A to ST5A. Specifically, in the first to third latter half performances ST1B to ST3B, three types of reliability suggestions from the lowest reliability may be executable, and in the fourth and fifth latter half performances ST4B to ST5B, five types of reliability suggestions may be executable. Also, in the fourth and fifth latter half performances ST4B to ST5B, reliability suggestions (two types with high reliability) that are not executed in the first to third latter half performances ST1B to ST3B may be executable. In addition, the number of variations in executable reliability suggestions may be varied depending on the character or stage, such as three types for the first second half performance ST1B, three types for the second second half performance ST2B, three types for the third second half performance ST3B, five types for the fourth second half performance ST4B, and four types for the fifth second half performance ST5B.

[0360] Also, depending on the selection rate of each character, the number of variations of the reliability suggestion of the character with a high selection rate may be increased, and the number of variations of the reliability suggestion of the character with a low selection rate may be decreased. By configuring in this way, it is possible to show more presentation variations to the player, and it is possible to configure the presentation so that the player does not get bored. Also, the number of variations of the reliability suggestion of the character with a low selection rate may be increased more than that of the character with a high selection rate. Also, when the selection rates are set in descending order of elephant, lion, fox, squirrel, and bear, the number of variations of the reliability suggestion of the fox and squirrel may be increased more than that of the elephant and lion. Furthermore, in this case, the number of variations of the reliability suggestion of the bear may be decreased more than that of the fox and squirrel. In this case, it is preferable to configure the reliability suggestion variation executed when the bear is selected so that only the high reliability one is prepared, and no low reliability one is prepared.

[0361] The above-mentioned various configurations in the step-up preview performance are not limited to this step-up preview performance, but can be similarly adopted in other various performances (preview performances and partial performances). For example, various configurations such as the high brightness performances WO11 and WO12 in the step-up preview performance may be adopted in the reach preview performance, the dialogue preview performance, etc. described later.

[0362] [Reach announcement] 27 to 31 show an example of a reach notice performance executed during normal fluctuation in a reach fluctuation pattern or a normal fluctuation pattern. This reach notice performance (specific notice performance) is a performance that notifies the establishment of a reach state, and is composed of a reach notice first half performance RC1 and a reach notice second half performance RC2, and the performance mode of the reach notice second half performance RC2 is set to be selected from a plurality of types (four types shown in FIG. 27 here) according to the type of the selected fluctuation pattern. The jackpot reliability is set to gradually increase from the first performance mode RC2a (FIG. 27(a)) to the fourth performance mode RC2d (FIG. 27(d)). In this way, for example, the performance image according to the first performance mode RC2a (FIG. 27(a)) is an example of a B-1 reliability specific image corresponding to the B-1 reliability, and the performance image according to the second performance mode RC2b (FIG. 27(b)) is an example of a B-2 reliability specific image corresponding to the B-2 reliability.

[0363] The multiple types (four types) of performance modes RC2a to RC2d of this reach notice second half performance RC2 are generally the same in terms of the characters appearing in the performance images and their actions, but the dialogue strings displayed in front of the character images, etc., the corresponding dialogue sounds output as voice, and the base colors of the performance images are different. That is, as shown in Fig. 27, the same kappa character image is displayed in all of the first to fourth performance modes RC2a to RC2d, but the dialogue strings displayed in front of the character images and the corresponding dialogue sounds are different in all four types, and are "It's a reach!", "It's a SP reach!", "Great chance!!", and "Super hot!!", respectively.

[0364] In addition, the display color of the dialogue character string and the base color of the performance image are different for all four types, and the display color (inner color) and base color of the dialogue character string corresponding to the first to fourth performance modes RC2a to RC2d are "blue", "red", "gold", and "danger color", respectively. The danger color is as described above. In this way, the first to fourth performance modes RC2a to RC2d have different jackpot reliability depending on the display color of the character string, so it can be said that the character image (specific character information) or the reach notice performance image having the character image has reliability information regarding the jackpot. It is also possible to provide multiple display modes (here, display colors) for a common character string. In the case where the character string itself indicates reliability, such as "super hot", it is desirable to enable the performance expression by multiple display modes (display colors) with different reliability, such as configuring it so that "super hot" in danger color indicates higher reliability than "super hot" in gold. In this case, a plurality of display modes other than the display color (character color), for example, different sizes of character outlines, may be provided.

[0365] Next, a specific example of the reach notice performance will be described by taking as an example a case where the first performance mode RC2a (FIG. 27(a)) of the first to fourth performance modes RC2a to RC2d is selected, but first, an overview will be described with reference to FIG. 28. When the reach notice performance starts during normal fluctuation in the reach fluctuation pattern, the speaker starts outputting BGM2 related to this reach notice performance as BGM, and the decorative pattern 164 during high-speed fluctuation is hidden on the display screen DSa, and the reserved pedestal image 168 is displayed on the lower end side, and the mini pattern 165 is displayed on the upper end side, and a reach notice performance image 171 related to the reach notice first half performance RC1 is displayed behind them (FIG. 28(a)). This reach notice performance image 171 related to the reach notice first half performance RC1 is composed of a scene in which a kappa character flies in the sky.

[0366] During this reach notice first half performance RC1 (FIG. 28(a)), at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) emits light in the first half light emission mode corresponding to the reach notice first half performance, for example, orange. At the start of the reach notice performance, a predetermined start sound may be output as a sound effect.

[0367] After that, the reach notice first half performance RC1 transitions to the reach notice second half performance RC2 (here, the first performance aspect RC2a), and the reach notice performance image 171 switches to a scene in which the kappa character shows a close-up of the upper body (Fig. 28(b)~). In addition, at the time of the scene change (switching from the first scene image to the second scene image) accompanying the transition from this reach notice first half performance RC1 to the reach notice second half performance RC2 (first timing), a high-brightness performance (first high-brightness performance) WO21 is executed (Fig. 28(b)) by displaying the high-brightness image 170c, which reduces the visibility of the image behind the high-brightness image 170c (here, the reach notice performance image 171). Thus, at the first timing when the high-brightness performance WO21 is performed, the dialogue character string (character image) having the reliability information regarding the jackpot is not yet displayed on the screen. In this high-brightness rendering WO21, the minimum transmittance of the high-brightness image is set to greater than 0%, but the minimum transmittance of the high-brightness image may be set to 0% so that the character image behind it becomes completely invisible.

[0368] During the high-brightness performance WO21 (FIG. 28(b)), the output of the BGM2 related to the reach notice performance continues. At the start of the high-brightness performance WO21, a predetermined first emphasis sound is output as a sound effect. During the high-brightness performance WO21, at least a part of the performance lamps L (here, both the frame-side lamps La and the board-side lamps Lb) emit light in a high-brightness medium light-emitting mode. This high-brightness medium light-emitting mode includes a specific color (e.g., blue) corresponding to the text color of the reach notice second half performance RC2, and is configured to change, for example, from a specific color (here, white) to a specific color (here, blue). Note that this high-brightness medium light-emitting mode may be configured not to include the specific color corresponding to the text color. This makes it possible to prevent the content of the text information to be displayed subsequently from being revealed in advance.

[0369] When the high-brightness performance WO21 ends and the reach preview performance image 171 becomes fully visible (Fig. 28(c)), the dialogue string (text information) "It's a reach!" starts to be displayed in front of the character image (text information display start performance). At this time, the dialogue string appears accompanied by the first dynamic display performance (Fig. 28(c) -> (d)). That is, during the first dynamic display period in which the first dynamic display performance is executed, a text information display start performance (first specific performance) is executed when starting to display text information. In this first dynamic display performance, the dialogue string moves toward a predetermined display position at a first change speed (here, a movement involving rotation).

[0370] During the character information display start performance, the output of the BGM2 related to the reach notice performance continues. Also, when the display of the dialogue string starts (when the character information display start performance starts), a predetermined character appearance sound is output as a sound effect. Also, during the character information display start performance, at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) emit light in a character appearance light-emitting mode. This character appearance light-emitting mode is a cyclic change mode that cyclically changes to multiple colors (e.g., blue and white) including the character color (here, blue) of the dialogue string displayed on the screen. Note that, for the light-emitting color used in this cyclic change mode, it is preferable not to use a color (here, red, gold, etc.) that indicates higher reliability than the character color (here, blue) of the dialogue string, and in this case, it is preferable to use a color that indicates lower reliability than the character color of the dialogue string or a light-emitting color (here, white, etc.) that is not used to suggest reliability. Also, a light-emitting mode that corresponds only to the character color of the dialogue string may be adopted, or a light-emitting mode other than continuous lighting, such as a flashing light-emitting mode, may be adopted. Also, it may be configured so that only specific light-emitting points have a light-emitting color corresponding to the character color of the dialogue string, and other light-emitting points have other light-emitting modes (for example, white or off). In this case, for the other light-emitting modes, it is preferable not to use a color (here, red, gold, etc.) that indicates higher reliability than the light-emitting color (here, blue) that corresponds to the character color of the dialogue string, and it is preferable to use a color that indicates lower reliability than the character color of the dialogue string or a light-emitting color that is not used to suggest reliability (here, white, etc.).

[0371] When the dialogue character string is displayed at a predetermined display position through the first dynamic display performance (second timing), a high-brightness performance (A second high-brightness performance) WO22 is executed, which reduces the visibility of the image behind the high-brightness image 170d (here, the reach notice performance image 171) by displaying the high-brightness image 170d (FIG. 28(d)). Thus, at the second timing when the high-brightness performance WO22 is performed, the dialogue character string (character image) having the reliability information on the big win is already displayed on the screen. During this high-brightness performance WO22, the output of the BGM2 related to the reach notice performance continues, and a predetermined second emphasis sound is output as a sound effect. Also, during the high-brightness performance WO22, at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) continues to emit light in the character appearance light-emitting mode.

[0372] When the high brightness performance WO22 ends and the reach notice performance image 171 including the dialogue string becomes completely visible (FIG. 28(e)), a predetermined reach notice voice is output as a dialogue sound (dialogue output performance). This reach notice voice corresponds to the dialogue string displayed on the screen, and is output as "reach" here. However, without being limited to this, the dialogue output performance of "reach" may be configured to be executed while the high brightness performance WO22 is being executed, or the dialogue output performance may be configured to be executed from the timing when the dialogue string appears before the execution of the high brightness performance WO22. During the dialogue output performance, the output of the BGM2 related to the reach notice performance continues, and at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) emits light in a dialogue output light emitting mode (here, blue) corresponding to the character color of the dialogue string (i.e., the reliability information).

[0373] When the dialogue output performance ends, a final performance (specific image final performance) is executed to end the display of the reach notice performance image 171 related to the reach notice performance and switch to a pattern change screen (Fig. 28(f)). During this final performance, at least a part of the performance lamps L (here, both the frame side lamps La and the board side lamps Lb) emits light in a final light-emitting mode (e.g., orange) different from the previous dialogue output light-emitting mode (here, blue) or character appearance light-emitting mode (here, blue and white cyclic change mode), but this final light-emitting mode may be configured to be the same light-emitting mode as either the dialogue output light-emitting mode or the character appearance light-emitting mode. When the pattern change screen starts after the final performance (Fig. 28(g)), a pattern stop sound is output as a sound effect in accordance with the stop of the decorative patterns 164a to 164c. In addition, the reach preview effect shown in FIG. 28 has a different jackpot reliability from the step-up preview effect shown in FIG. 23, and here the latter has a higher jackpot reliability than the former (FIG. 20).

[0374] The high-brightness performance (A-2 high-brightness performance) WO22 may be configured to have a different execution time from the high-brightness performance (A-1 high-brightness performance) WO21, or may be configured to have the same execution time. The two may also be configured to have different or the same transmittance for the high-brightness image. The two may also be configured to have different or the same display range for the high-brightness image. Furthermore, since no character string is displayed during the execution of the high-brightness performance (A-1 high-brightness performance) WO21, and character strings are displayed during the execution of the high-brightness performance (A-2 high-brightness performance) WO22, the high-brightness performance (A-2 high-brightness performance) WO22 only needs to display a high-brightness image so as to make at least the character strings difficult to see, and may be configured to have different transmittances for the character (kappa) part and the character string part, for example. Also, the high-brightness image may be executed so that it does not overlap or only partially overlaps the character (kappa) portion, and the high-brightness image may be executed so that it overlaps the character string portion. Also, when the character (kappa) and / or the character string are dynamically displayed, it is desirable that they are always dynamically displayed within the display range of the high-brightness image. However, this is not limited to this, and it may be configured so that there are times when the character (kappa) and / or the character string overlap the display range of the high-brightness image and times when they do not overlap during the dynamic display of the character (kappa) and / or the character string. This makes it possible to change the visibility of the character (kappa) and / or the character string during the dynamic display, and to improve the presentation effect. Also, it may be configured so that the dynamic pattern when the character (kappa) and / or the character string are dynamically displayed during the execution of the high-brightness presentation is different from the dynamic pattern when the character (kappa) and / or the character string are dynamically displayed after the execution of the high-brightness presentation is completed.

[0375] Next, the performance period centered on the high brightness performances WO21 and WO22 in the reach notice performance shown in FIG. 28 will be described in more detail. FIG. 29 to FIG. 31 show the change in the display screen and the light emitting means at even shorter time intervals than FIG. 28 during the period of FIG. 28(b) to (g), that is, the period from the start of the high brightness performance WO21 to the end of the reach notice performance and the transition to the variable screen of the decorative pattern 164. Note that the 20 frames of display images shown in FIG. 29 to FIG. 31 are extracted at a constant pitch from all the frames during the period of FIG. 28(b) to (g). Therefore, in FIG. 29 to FIG. 31, the time interval between adjacent frames is the same, and is A milliseconds, the same as FIG. 24 to FIG. 26 in the step-up notice performance.

[0376] First, the details of the high-brightness performance WO21 will be described. In the high-brightness performance WO21 shown in Fig. 29(a)-(f), at the start, a high-brightness image 170c is displayed in front of the reach notice performance image 171 and behind the mini symbol 165, reserved pedestal image 168, and the reserved images X1-X4, Y1-Y4 in front of it (Fig. 29(a)), and the transmittance of the high-brightness image 170c gradually changes and finally disappears (Fig. 29(f)).

[0377] Here, the high-brightness image 170c is displayed in a range (size) that covers the entire reach notice performance image 171, and the transmittance is uniform within the display range, so that the display range does not change over time, but the transmittance changes over time (transmittance change processing, transmittance change performance). The transmittance of the high-brightness image 170c is configured to be minimum (25% here) at the start of display (FIG. 29(a)), and to gradually increase (rise) at a constant rate of change over time (first display pattern). That is, the high-brightness performance WO21 is configured with a low-transmittance change performance that changes the transmittance of the high-brightness image 170c in a decreasing direction, and a high-transmittance change performance that changes the transmittance of the high-brightness image 170c in an increasing direction, and the latter (FIGS. 29(a) to (f)) has a longer execution time than the former (FIG. 29(a)). In the high-brightness image 170c, the minimum transmittance is greater than 0% (here, 25%), and even at the start of display at this minimum transmittance (FIG. 29(a)), the reach notice performance image 171 is slightly visible. The transmittance at the start of display of the high-brightness image 170c may be set to 0%, so that the display content behind the high-brightness image 170c cannot be seen at the start of display.

[0378] Of course, the high-brightness image 170c may be set to a display range (size) in which the coverage rate of the reach notice performance image 171 is less than 100%, or the transmittance within the display range may be non-uniform. The display range (size) may be changed over time while changing the transmittance or without changing the transmittance. The minimum transmittance of the high-brightness image 170c may be set to 0%. The execution time of the high transmittance change performance may be shorter than that of the low transmittance change performance, or the execution times of both may be approximately the same.

[0379] Also, at a predetermined time during the high-brightness performance WO21, for example, at the start (FIG. 29(a)), the performance scenario is switched, and the reach notice performance image 171 behind the high-brightness image 170c is switched from the image of the previous reach notice first half performance RC1 to the image of the reach notice second half performance RC2. That is, the high-brightness performance WO21 is an example of a high-brightness performance at the time of image change that can be executed when performing an image change process that changes from the first image to the second image, and is an example of a high-brightness performance at the time of scenario change that is executed at the timing of switching the performance scenario. As a result, after the start of the high-brightness performance WO21, as the transmittance of the high-brightness image 170c gradually increases, the visibility of the reach notice performance image 171 improves, and when the high-brightness image 170c eventually disappears (FIG. 29(f)), the entire reach notice performance image 171 (excluding the part hidden behind the mini pattern 165, etc.) becomes completely visible.

[0380] During the execution of the high-brightness effect WO21, the mini-pattern 165 goes from between "3·5·7" and "4·6·8" (Fig. 29(a)) to "8·2·4" (Fig. 29(f)). In other words, the execution time of the high-brightness effect WO21 (Figs. 29(a) to (f)) is longer than the period in which the mini-pattern 165 goes through one cycle.

[0381] During the high-brightness effect WO21, the effect lamp L emits light in a medium-high-brightness light-emitting mode. The medium-high-brightness light-emitting mode is configured to emit a predetermined color (white here) until a predetermined point in time during the high-brightness effect WO21 (FIG. 29(a)-(b)), and to change to a specific color (blue here) thereafter (FIG. 29(c)-(e)).

[0382] When the high brightness effect WO21 ends and the reach notice effect image 171 becomes completely visible (Fig. 29(f)), the character information display start effect (Figs. 29(f)-(h)) is performed at the same time, or at a specified timing thereafter. In this character information display start effect, the dialogue string (text information) "It's a reach!" appears in front of the character image, etc., accompanied by a first dynamic display effect (first dynamic display period). In this first dynamic display effect, the dialogue string moves at a first change speed (here, a movement accompanied by rotation and shrinking changes) toward a specified display position. Due to this first dynamic display effect accompanied by rotation and shrinking changes, the player perceives the dialogue string as moving toward the back of the screen while rotating, for example, clockwise. It should be noted that the dialogue string "It's a reach!" is displayed in "blue" (Figure 27(a)), but the display mode (display color and shape) of the dialogue string does not change during the first dynamic display performance (a specific display process that displays text information in a specific display mode is not executed).

[0383] When the dialogue string reaches a predetermined display position through the first dynamic display performance (Fig. 29(h)), a high-brightness performance WO22 (Figs. 29(h) to 30(l)) is executed, which displays a high-brightness image 170d to reduce the visibility of the image behind the high-brightness image 170d (here, the reach notice performance image 171). Unlike the high-brightness performance WO21, this high-brightness performance WO22 is executed when the performance scenario is not switched, that is, at a timing when the reach notice performance image 171 is not changed. In this way, the high-brightness performance WO22 is an example of a high-brightness performance when an image is not changed that can be executed when a predetermined image is not changed (image change), and is an example of a high-brightness performance when a scenario is not switched that is executed at a timing when the performance scenario is not switched.

[0384] In this high-brightness performance WO22, similarly to the high-brightness performance WO21, a high-brightness image 170d appears in front of the reach notice performance image 171 and behind the mini pattern 165, reserved pedestal image 168, and the reserved images X1 to X4, Y1 to Y4 in front of it, and then disappears, but the change (display pattern) of the high-brightness image 170d is different from the high-brightness image 170b in the high-brightness performance WO21. Note that the high-brightness image may be configured to appear in front of the reserved pedestal image 168 and the reserved images X1 to X4, Y1 to Y4 in front of it, and this is also the case in other performances.

[0385] That is, the high-brightness image 170d is displayed in a range (size) that covers the entire reach notice performance image 171, and the transmittance is uniform within the display range, and the display range does not change with time, and the transmittance changes with time (transmittance change processing, transmittance change performance), which is common to the high-brightness image 170c, but the transmittance gradually decreases with time and becomes a minimum (here, 40%) at a predetermined time (FIGS. 29(h) to 30(j)), and then gradually increases with time (FIGS. 30(j) to (l)) (second display pattern). Thus, the high-brightness performance WO22 is composed of a low-transmittance change performance that changes the transmittance of the high-brightness image 170d in a decreasing direction and a high-transmittance change performance that changes the transmittance of the high-brightness image 170d in an increasing direction, and the former (FIGS. 29(h) to 30(j)) and the latter (FIGS. 30(j) to (l)) have approximately the same execution time. Of course, the execution time of the high transmittance change effect may be longer than that of the low transmittance change effect, or vice versa. Note that in the high-brightness image 170d, the minimum transmittance is greater than 0% (here, 40%), and the reach notice effect image 171 is visible even at the predetermined time when the minimum transmittance is reached (FIG. 30(j)).

[0386] During the execution of the high-brightness effect WO22, the mini-pattern 165 goes from "5·7·1" (Fig. 29(h)) to "7·1·3" (Fig. 30(l)). In other words, the execution time of the high-brightness effect WO22 (Figs. 29(h) to 30(l)) is longer than the period for the mini-pattern 165 to go through one cycle. Also, the execution time of the high-transmittance change effect may be longer than that of the low-transmittance change effect, or vice versa.

[0387] During this high-brightness performance WO22, an arrival emphasis operation is performed to emphasize that the dialogue string has reached a predetermined display position, in this case an expansion / contraction operation (enlargement / reduction operation) of the dialogue string (FIGS. 29(h) to 30(l)). The type of arrival emphasis operation is arbitrary, and may be any type, such as a bound operation of the dialogue string or a transformation operation other than enlargement / reduction. Furthermore, the high-brightness performance WO22 may be configured to be executed at the timing when the arrival emphasis operation of the dialogue string is completed. In other words, during the high-brightness performance WO22, the transformation operation of the dialogue string may not be executed. Alternatively, during the high-brightness performance WO22, only a smaller transformation operation is performed on the dialogue string than the arrival emphasis operation of the dialogue string performed before the execution of the high-brightness performance WO22.

[0388] During the period from the text information display start effect to the high brightness effect WO22, the effect lamp L emits light in a text appearance light-emitting mode. The text appearance light-emitting mode is a cyclic change mode in which the light changes cyclically among a plurality of colors (e.g., blue and white) including the text color (here, blue) of the dialogue string displayed on the screen, and the light color changes from white (FIG. 29(f)-(g)) to blue (FIG. 29(h)-(i)) to white (FIG. 30(j)-(k)).

[0389] When the high brightness performance WO22 ends and the entire reach notice performance image 171 including the dialogue string becomes visible (Fig. 30(l)), a dialogue output performance is performed and a dialogue sound (reach notice voice) of "It's a reach" corresponding to the dialogue string (text information) displayed on the screen is output, and during this dialogue output performance (second dynamic display period), a second dynamic display performance is performed for the dialogue string (Figs. 30(l)-(p)). In this second dynamic display performance, the dialogue string is displayed at a second change speed (here, slower than the first change speed) different from the change speed during the first dynamic display performance (first change speed), for example, slowly shrinking. This shrinking display allows the player to recognize the dialogue string as moving towards the back of the screen.

[0390] During the second dynamic display period in which the second dynamic display performance is performed for the dialogue character string, the mini-pattern 165 goes from "7·1·3" (FIG. 30(l)) to "1·3·5" (FIG. 30(p)). That is, the second dynamic display period (FIG. 30(l)-(p)) is longer than the period in which the mini-pattern 165 goes around, and is longer than the first dynamic display period (FIG. 29(f)-(h)). In the example of FIG. 29, the first dynamic display period (FIG. 29(f)-(h)) is shorter than the period in which the mini-pattern goes around.

[0391] During this second dynamic display performance (FIG. 30(l)-(p)), a display mode change process (specific display process for displaying character information in a specific display mode) is performed to change the display mode (here, display color) of the dialogue character string. This display mode change process is performed within the outline of the dialogue character string (character information), and for example, the display color of the character corresponding to the dialogue sound being output changes temporarily (for example, from blue to white). As a result, the white part is recognized as moving, for example, from left to right on the character string "It's a reach!" displayed in blue. When performing a predetermined change performance within the outline of the dialogue character string in this way, the dialogue character string may be configured to be displayed dynamically, or an effect image may be displayed in a stationary state. Note that, when this dialogue sound is output, it is preferable to have the character image perform a so-called lip-syncing action (speaking action). Also, the display mode change process (specific display process for displaying character information in a specific display mode) in which the white part moves on the dialogue character string is preferably performed in response to the output of the dialogue sound. By synchronizing the output timing of the dialogue sound with the change (movement) of the display color on the dialogue character string in this way, even if lip-syncing (speaking) is not involved, it is possible to more clearly express the relationship between the output of the dialogue sound and the dialogue character string being output. The lip-syncing may be performed while the high-brightness image is being displayed, or may be configured to be performed after the display of the high-brightness image has ended. When the lip-syncing is performed while the high-brightness image is being displayed, it is desirable to configure the lip-syncing to be performed at least while the dialogue character string is being displayed or after the first dynamic display of the dialogue character string has ended, but this is not limiting, and the lip-syncing may be configured to be performed during the first dynamic display.

[0392] During the dialogue output performance, the performance lamp L emits light in a dialogue output light emitting mode corresponding to the character color of the dialogue string (blue in this example), that is, in blue (FIGS. 30(l) to (p)).

[0393] When the dialogue output performance (Fig. 30(l)-(p)) ends (i.e., after the second dynamic display period), an end performance (specific image end performance, text information display end performance) is performed to end the display of the reach notice performance image 171 related to the reach notice performance and switch to a pattern changing screen (Fig. 30(q)-Fig. 31(t)). In this end performance, a concealing image 172 that conceals the reach notice performance image 171 is displayed in front of the reach notice performance image 171, and the pattern changing screen appears when the display of the concealing image 172 ends. In the end performance of this embodiment, the concealed image 172 is composed of a curtain and a character pulling it, and the character closes the curtain to conceal the reach notice performance image 171 (Fig. 30(q)-(r)), and then the character opens the curtain, gradually making the variable screen of the decorative pattern 164 (excluding the part hidden behind the mini pattern 165, etc.) visible (Fig. 30(r) -> Fig. 31(t)). Note that the display mode (display color and shape) of the dialogue character string does not change during the execution of this end performance (specific display processing for displaying character information in a specific display mode is not executed). Here, a white image is adopted as the concealed image 172, but this is not limited thereto, and for example, a display color suggesting reliability may be used, or other colors may be used. Also, the transmittance of the concealed image 172 may be greater than 0%. Also, when the concealed image 172 is made to be another color, it is desirable to adopt an image with a color or pattern at least different from the high brightness image. Also, concealed image 172 may be configured to be displayed in an area including the front side of reserved pedestal image 168 and reserved images X1-X4, Y1-Y4 so as to overlap them. Also, the display period of concealed image 172 may be configured to be different from the display period of the high-brightness image, or may be the same period, but if they are different periods, the display period of concealed image 172 may be configured to be longer than the display period of the high-brightness image, or conversely, may be configured to be shorter.

[0394] During the end performance, the performance lamp L emits light in the end light emission mode, for example, in orange (FIG. 30(q) to FIG. 31(s)).

[0395] In addition, when comparing the execution time of the high-brightness effects WO21, WO22 and the end-time effect in the reach preview effect, the high-brightness effect WO21 (Figures 29(a) to (f)) is approximately 5A milliseconds, the high-brightness effect WO22 (Figures 29(h) to 30(l)) is approximately 4A milliseconds, and the end-time effect is approximately 4A milliseconds, but the execution time of the end-time effect may be shorter than the execution time of the high-brightness effect WO22, or conversely, it may be longer.

[0396] As described above, in the reach notice performance, the high brightness performance (first high brightness performance) WO21 that displays the high brightness image (first high brightness image) 170c and the high brightness performance (second high brightness performance) WO22 that displays the high brightness image (second high brightness image) 170d can be executed, and the high brightness performance WO21 is executed at the first timing when the scene change (switching from the first scene image to the second scene image) accompanying the transition from the reach notice first half performance RC1 to the reach notice second half performance RC2 is performed, and the high brightness performance WO22 is executed at the second timing thereafter. Note that, at the first timing when the high brightness performance WO21 is performed, the dialogue character string (character image) having reliability information regarding the big win has not yet been displayed on the screen, and is displayed at the second timing thereafter.

[0397] In the reach notice performance, the display of a character image having jackpot reliability information is started before the high-brightness performance WO22, and an end performance (specific image end performance) can be executed when the display of the character image is ended (Fig. 30(q) to Fig. 31(t)). In addition, during the high-brightness performance WO22, a first light-emitting performance is executed in which the performance lamp (light-emitting means) L is illuminated in a character appearance light-emitting mode (first light-emitting mode) corresponding to the reliability information (e.g., display color) in the character image, and during the end performance (specific image end performance), a second light-emitting performance is executed in which the performance lamp (light-emitting means) L is illuminated in an end light-emitting mode (second light-emitting mode) different from the character appearance light-emitting mode (first light-emitting mode).

[0398] In the reach notice performance, a high brightness performance (high brightness performance when changing image) WO21 that can be executed when performing image change processing to switch from the image (first image) of the reach notice first half performance RC1 to the image (second image) of the reach notice second half performance RC2, and a high brightness performance (high brightness performance when the image is not changed) WO22 that can be executed when the image change processing is not performed can be executed, and the minimum transmittance (transparency) of the high brightness image is made different between the high brightness performance WO21 and the high brightness performance WO22. Note that here, the minimum transmittance is made different as an example of the transmittance performance of the high brightness image, but other transmittance performances, such as the range (size) of the high brightness image and the distribution of the transmittance, may be made different. In addition, the image change processing is not limited to switching from the image (first image) of the reach notice first half performance RC1 to the image (second image) of the reach notice second half performance RC2, but may be any processing that switches from a predetermined first image to a predetermined second image. That is, an image that is displayed before the high-brightness effect is executed but is not displayed after the execution corresponds to the first image, and an image that is not displayed before the high-brightness effect is executed but is displayed after the execution corresponds to the second image. In this way, if there are images (first image and second image) whose display can be switched before and after the high-brightness effect, it may be considered that the image change process is being executed.

[0399] The reach notice performance is an example of a character information display performance that displays character information (here, dynamically displays), and can execute a character information display start performance (a first specific performance performed when displaying character information starts) that starts displaying character information, and an end performance (a second specific performance performed when displaying character information ends) that ends displaying character information. After execution of the character information display start performance (during the first specific performance), a display mode change process (a specific display process that displays character information in a specific display mode) (FIG. 30(l)-(p)) that changes the display mode of character information is executed, and the display mode change process (specific display process) is not executed during execution of the end performance (second specific performance). However, it is not limited to this, and may be configured to execute the display mode change process (specific display process) even during execution of the end performance (second specific performance). In this case, the display mode change performance that started after execution of the character information display start performance (during the first specific performance) will be executed continuously during execution of the end performance (second specific performance). In addition, it may be configured to execute a display mode change effect different from the display mode change effect that started after the execution of the text information display start effect (during the first specific effect) during the execution of the end effect (second specific effect).

[0400] In addition, the reach preview performance includes a high-brightness performance (high-brightness performance when scenario switches) WO21 that is executed when the performance scenario switches, and a high-brightness performance (high-brightness performance when scenario does not switch) WO22 that is executed when the performance scenario does not switch. The high-brightness performance WO21 displays a high-brightness image 170c in a first display pattern, and the high-brightness performance WO22 displays a high-brightness image 170d in a second display pattern that is different from the first display pattern. The high-brightness performance WO21 (Figures 29(a) to (f)) has a longer execution time than the high-brightness performance WO22 (Figures 29(h) to 30(l)). As described above, the high-brightness image WO21 and the high-brightness image WO22 have different minimum transmittances (transmission performance), and the high-brightness image 170d of the high-brightness image WO22 has a larger minimum transmittance than the high-brightness image 170c of the high-brightness image WO21. The minimum transmittance of the high-brightness image 170d of the high-brightness image WO22 may be smaller than that of the high-brightness image 170c of the high-brightness image WO21, or may be substantially the same. Other transmission performances, such as the maximum range (size) and transmittance distribution of the high-brightness image, may be different between the high-brightness image WO21 and the high-brightness image WO22. In this case, the high-brightness image WO21 may be large and the high-brightness image WO22 may be small, or the high-brightness image WO21 may be small and the high-brightness image WO22 may be large.

[0401] In the reach notice performance, a first dynamic display performance in which the dialogue character string moves toward a predetermined display position at a first change speed (here, a movement involving rotation and shrinking) and a second dynamic display performance in which the dialogue character string is displayed at a second change speed (here, slower than the first change speed) different from the change speed (first change speed) during the first dynamic display performance, for example, slowly shrinking, can be executed. During the second dynamic display performance, a display mode change process (specific display process that displays the character information in a specific display mode) that changes the display mode (here, display color) of the dialogue character string (character information) is executed, and the display mode change process (specific display process) is not executed during the first dynamic display performance. Note that the display mode change process (specific display process) is executed within the outline of the dialogue character string (character information). Also, during the first dynamic display performance, a character information display start performance (first specific performance executed when starting to display the character information) that starts displaying the dialogue character string (character information) is executed. During the execution of the end effect (a second specific effect performed when the display of the character information is ended) that ends the display of the dialogue string (character information), the display mode (display color and shape) of the dialogue string does not change (specific display processing is not executed).

[0402] In the reach notice performance, there is a first dynamic display period in which the dialogue character string is dynamically displayed at a first change speed toward a predetermined display position, and a second dynamic display period in which the dialogue character string is dynamically displayed at a second change speed slower than the first change speed, and the second dynamic display period (Fig. 30(l)-(p)) is longer than the first dynamic display period (Fig. 29(f)-(h)). In addition, during the first dynamic display period, a character information display start performance (first specific performance) is executed when the dialogue character string (character information) starts to be displayed, and after the second dynamic display period, an end performance (second specific performance) is executed when the dialogue character string (character information) ends to be displayed. The second dynamic display period is longer than the time it takes for the mini pattern 165 to change in one cycle. In addition, the first dynamic display period is also longer than the time it takes for the mini pattern 165 to change in one cycle.

[0403] The reach notice performance is an example of a text information display performance that displays text information, and is capable of executing a text information display start performance (first specific performance) that is performed when the display of the text information begins, and an end performance (second specific performance) that is performed when the display of the text information ends. After the text information display start performance is executed, a display mode change process that changes the display mode of the text information (specific display process that displays the text information in a specific display mode) (Figures 30 (l) to (p)) is executed, and the display mode change process (specific display process) is not executed while the end performance is being executed.

[0404] In addition, the reach notice performance includes a high-brightness performance (high-brightness performance when changing image) WO21 that can be executed when image change processing is performed to change the reach notice performance image 171 from the first image to the second image, and a high-brightness performance (high-brightness performance when image is not changed) WO22 that can be executed when the reach notice performance image (predetermined image) 171 is not changed (image change processing is not performed), and the execution time of the high-brightness performance WO22 and the high-brightness performance WO21 is approximately the same, and the execution time of the high-brightness performances WO21 and WO22 is longer than one cycle of the variation of the mini pattern 165. The execution time of the high-brightness performance (high-brightness performance when changing image) WO21 may be longer than the execution time of the high-brightness performance (high-brightness performance when image is not changed) WO22, or vice versa.

[0405] Also, the minimum transmittance of the high-brightness image is different between high-brightness performance (high-brightness performance when image is changed) WO21 and high-brightness performance (high-brightness performance when image is not changed) WO22. That is, high-brightness image 170c in high-brightness performance WO21 has a minimum transmittance of 25%, whereas high-brightness image 170d in high-brightness performance WO22 has a minimum transmittance of 40%, meaning that high-brightness image 170d in high-brightness performance WO22 has a greater minimum transmittance than high-brightness image 170c in high-brightness performance WO21.

[0406] The various configurations in the reach notice performance described above are not limited to this reach notice performance, but can be similarly adopted in other various performances (notice performances and partial performances). For example, various configurations such as the high brightness performances WO21 and WO22 and the end performance in the reach notice performance may be adopted in the step-up notice performance described above, the button notice performances 1 and 2 described below, and the dialogue notice performance. In other words, if it is a (notice) performance accompanied by the execution of a high brightness performance or an end performance, the contents of the high brightness performances WO21 and WO22 and the end performance in this notice performance may be adopted in another performance. It goes without saying that the same can be adopted in the character information display start performance and the display mode change processing executed in conjunction with this.

[0407] [Button preview 1] 32 to 35 show an example of a button advance notice performance 1 executed during a reach fluctuation in a reach fluctuation pattern. This button advance notice performance (operation performance) 1 is a performance (related to the operation of the operation means by the player) that requests the player to operate the chance button (operation means) 11, and suggests the reliability of a big win, etc., by executing a predetermined post-operation performance based on the establishment of one or more conditions, including the case where the chance button 11 is operated during the operation valid period. There are multiple types of post-operation performances, for example, two types of post-operation performances, a post-operation success performance and a post-operation failure performance, and the post-operation success performance has a higher reliability of a big win than the post-operation failure performance.

[0408] Next, a specific example of the button advance notice performance 1 will be described by taking the case where the post-operation success performance is selected as the post-operation performance as an example, but first, an overview will be described with reference to Fig. 32. When the button advance notice performance 1 starts after the reach is established in the reach fluctuation pattern, the speaker starts outputting BGM3 related to this button advance notice performance 1 as BGM, and on the display screen DSa, the left decorative pattern 164a and the right decorative pattern 164b constituting the reach are left, and the center decorative pattern 164c which is fluctuating at high speed is hidden, and the reserved pedestal image 168 is displayed on the lower end side, and the mini pattern 165 is displayed on the upper end side, and the button advance notice performance image 173 related to the button introduction performance BA0 is displayed behind them (Figs. 32(a), (b)).

[0409] In the button preview performance image 173 of the button introduction performance BA0, for example, a character image 174 with a serious face and a character string image 175 such as "Make the character laugh" are displayed on the screen in that order, and the player who sees this can recognize that this is a performance that suggests the possibility of a big win depending on whether the character laughs or not. In addition, in this button introduction performance BA0 (FIGS. 32(a), (b)), for example, at the start, a predetermined introduction sound is output from the speaker as a sound effect, and a line sound corresponding to the character string image 175, that is, a button introduction voice of "Make the character laugh", is output in accordance with the display of the character string image 175. Furthermore, during this button introduction performance BA0 (FIGS. 32(a), (b)), at least a part of the performance lamps L (here, both the frame side lamp La and the board side lamp Lb) emits light in an introduction light-emitting mode (predetermined light-emitting mode) corresponding to this button introduction performance BA0, for example, in light blue.

[0410] Following the button introduction performance BA0 (FIGS. 32(a) and (b)), an operation prompting performance BA1 (FIGS. 32(c)-(d)) is performed, which displays an operation prompting image 176 that prompts the user to operate the operating means. Here, the operation prompting image 176 is composed of a button image (operation target image) 176a indicating the operation target, and an operation mode notification image 176b indicating the operation mode for the operation target, and is displayed approximately in the center of the screen in place of the character string image 175 of "Make the character laugh", for example. The operation mode notification image 176b is composed of an arrow indicating the pressing direction of the operation target and the character string "PUSH".

[0411] Here, the operation target in this embodiment is the chance button 11, but the chance button 11 mounted on the pachinko machine GM is configured to be pushed backwards in a substantially rectangular shape when viewed from the front, as shown in FIG. 1, and is not generally used. Therefore, in FIG. 32 and subsequent drawings, an operation prompting image 176 is used that assumes a more general chance butto...

Claims

[Claim 1] an image control means for issuing a display list that specifies display contents to be displayed on the image display means; an image generating means having a drawing circuit for generating image data for realizing the display contents based on the display list and basic data of an appropriate storage means; In a gaming machine capable of executing a performance including image display on the image display means, The image control means has a setting means for setting an appropriate abnormality determination time in a predetermined register of the image generating means, The image generating means includes: a monitoring means for monitoring a memory access time interval by the drawing circuit and / or a decoding execution time for decoding the basic data; a determination means for determining that an abnormality has occurred when the memory access time interval or the decode execution time exceeds the abnormality determination time, The presentation includes a character information display presentation that dynamically displays character information, In the character information display performance, a first dynamic display performance in which the character information is dynamically displayed at a first change speed, and a second dynamic display performance in which the character information is dynamically displayed at a second change speed different from the first change speed can be executed. During the second dynamic display performance, a specific display process is executed to display the character information in a specific display mode; The specific display process is not executed during the first dynamic display performance. A gaming machine characterized by:

Images