Display substrate, driving method thereof, manufacturing method thereof, and display device

Abstract

A display substrate and its driving method, a display device, the display substrate comprises a plurality of circuit units, a plurality of data signal lines 60 and a plurality of data connection lines 70, the data connection lines 70 include a first connection line 71 and a second connection line 72, at least one circuit unit includes a data connection electrode 81, at least one circuit unit includes a fan-out connection electrode 83, the second connection line 72 is connected to the first connection line 71 via the fan-out connection electrode 83, the first connection line 71 is connected to the data signal line 60 via the data connection electrode 81, there is a first distance between the data connection electrode 81 and the first connection line 71, there is a second distance between the fan-out connection electrode 83 and the first connection line 71, the first distance and the second distance are greater than 0.

Description

[Technical field]

[0001] This application claims priority to a PCT application filed on May 19, 2022, with application number PCT / CN2022 / 093952, and entitled "Display substrate and its manufacturing method, display device", and also claims priority to a Chinese patent application filed on July 25, 2022, with application number 202210874018.9, and entitled "Display substrate and its driving method, display device", the contents of which are understood to be incorporated herein by reference.

[0002] The present disclosure relates to, but is not limited to, the field of display technology, and in particular to a display substrate and a driving method and manufacturing method thereof, and a display device. [Background technology]

[0003] Organic Light Emitting Diodes (OLED) and Quantum-dot Light Emitting Diodes (QLED) are active light-emitting display devices, which have the advantages of autonomous light emission, wide viewing angle, high contrast ratio, low power consumption, extremely fast response speed, light weight, bendability, low cost, etc. With the continuous development of display technology, flexible displays, which use OLED or QLED as a light-emitting device and thin film transistors (TFT) for signal control, have become the main products in the current display field. Summary of the Invention [Means for solving the problem]

[0004] The following is a summary of the subject matter described in detail in the present text, which is not intended to limit the scope of protection of the claims.

[0005] In one aspect, the present disclosure provides a display substrate, comprising a plurality of circuit units, a plurality of data signal lines, and a plurality of data connecting lines, the data connecting lines including a first connecting line extending along a first direction and a second connecting line extending along a second direction, the data signal lines extending along the second direction, the first direction and the second direction intersect, at least one circuit unit includes a data connecting electrode, at least one circuit unit includes a fan-out connecting electrode, the second connecting line is connected to the first connecting line via the fan-out connecting electrode, the first connecting line is connected to the data signal line via the data connecting electrode, an orthogonal projection of the data connecting electrode on a display substrate plane and an orthogonal projection of the data signal line on the display substrate plane at least partially overlap, an orthogonal projection of the fan-out connecting electrode on the display substrate plane and an orthogonal projection of the second connecting line on the display substrate plane at least partially overlap, and at least one of the data signal lines is provided between the data connecting electrode and the fan-out connecting electrode connected to the same first connecting line.

[0006] In an exemplary embodiment, the data connection electrode and the fan-out connection electrode connected to the same first connection line are provided on both sides of the first connection line, respectively.

[0007] In an exemplary embodiment, at least one circuit unit includes a data connection block, the data connection electrode is connected to the first connection line via the data connection block, and an orthogonal projection of the data connection block on the display substrate plane and an orthogonal projection of the data signal line on the display substrate plane at least partially overlap.

[0008] In an exemplary embodiment, the first connecting line, the data connecting block and the data connecting electrode are an integrated structure connected to each other.

[0009] In an exemplary embodiment, at least one circuit unit includes a fan-out connection block, the fan-out connection electrode is connected to the first connection line via the fan-out connection block, and an orthogonal projection of the fan-out connection block on the display substrate plane and an orthogonal projection of the second connection line on the display substrate plane at least partially overlap.

[0010] In an exemplary embodiment, the first connection line, the fan-out connection block and the fan-out connection electrode are an integrated structure connected to each other.

[0011] In an exemplary embodiment, at least one circuit unit includes a virtual electrode, the position and shape of which in one circuit unit is the same as the position and shape of the fan-out connection electrode in the other circuit unit.

[0012] In an exemplary embodiment, the orthogonal projection of the virtual electrode in the display substrate plane and the orthogonal projection of the second connecting line in the display substrate plane at least partially overlap.

[0013] In an exemplary embodiment, the display substrate further includes a plurality of first power supply wirings extending along the first direction and a plurality of second power supply wirings extending along the second direction, at least one circuit unit includes a power supply connection electrode, the second power supply wirings are connected to the first power supply wirings via the power supply connection electrode, and an orthogonal projection of the power supply connection electrode on the display substrate plane and an orthogonal projection of the second power supply wirings on the display substrate plane at least partially overlap.

[0014] In an exemplary embodiment, at least one circuit unit includes a power connection block, the power connection electrode is connected to the first power wiring via the power connection block, and an orthogonal projection of the power connection block on the display substrate plane and an orthogonal projection of the second power wiring on the display substrate plane at least partially overlap.

[0015] In an exemplary embodiment, the first power wiring, the power connection block, and the power connection electrode are an integrated structure that are connected to each other.

[0016] In an exemplary embodiment, at least one circuit unit includes a virtual electrode, the position and shape of the virtual electrode in one circuit unit being the same as the position and shape of the power connection electrode in the other circuit unit.

[0017] In an exemplary embodiment, an orthogonal projection of the virtual electrode onto the display substrate plane and an orthogonal projection of the second power supply wiring onto the display substrate plane at least partially overlap.

[0018] In an exemplary embodiment, the first power supply wiring and the first connecting line are arranged on the same layer, at least one first power supply wiring and at least one first connecting line are provided in at least one circuit row, a first break opening is provided between the first connecting line and the first power supply wiring, and an orthogonal projection of the first break opening on the display substrate plane and an orthogonal projection of the second power supply wiring on the display substrate plane at least partially overlap, or an orthogonal projection of the first break opening on the display substrate plane and an orthogonal projection of the second connecting line on the display substrate plane at least partially overlap.

[0019] In an exemplary embodiment, a first width of the first break opening is less than or equal to a second width of the second power supply wiring or the second connecting line, the first width and the second width are sizes in the first direction, and an orthogonal projection of the first break opening on the display substrate plane is within the range of an orthogonal projection of the second power supply wiring or the second connecting line on the display substrate plane.

[0020] In an exemplary embodiment, the second power supply wiring and the second connecting line are installed on the same layer, at least one second power supply wiring and at least one second connecting line are provided in at least one circuit column, a second break opening is provided between the second connecting line and the second power supply wiring, and an orthogonal projection of the second break opening on the display substrate plane at least partially overlaps with an orthogonal projection of the first connecting line or the first power supply wiring on the display substrate plane.

[0021] In an exemplary embodiment, a third width of the second break opening is equal to a fourth width of the first connecting line or the first power wiring, the third width and the fourth width are sizes in the second direction, and a boundary of an orthogonal projection of the second break opening on the display substrate plane and a boundary of an orthogonal projection of the first connecting line or the first power wiring on the display substrate plane are aligned.

[0022] In an exemplary embodiment, the display substrate includes a display area and a binding area located on one side of the display area in the second direction, the binding area is provided with a binding power lead configured to subsequently supply a high level signal or a low level signal, and at least one second power wiring of the display area is connected to the binding power lead of the binding area.

[0023] In an exemplary embodiment, the display substrate further comprises a frame region located on the other side of the display area, the frame region is provided with a frame power lead configured to subsequently supply a high level signal or a low level signal, and a plurality of first power wirings of the display area are connected to the frame power lead of the frame region.

[0024] In an exemplary embodiment, at least one circuit unit includes at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a plurality of transistors, and in a plane perpendicular to a display substrate, the circuit unit includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on a base, the semiconductor layer including at least active layers of a plurality of transistors, the first conductive layer including at least gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer including at least a second plate of a storage capacitor, the third conductive layer including at least the first connecting line, and the fourth conductive layer including at least the data signal line and the second connecting line.

[0025] In an exemplary embodiment, the third conductive layer further includes a data connection electrode and a fan-out connection electrode respectively connected to the first connection line, the data signal line is connected to the data connection electrode through a first connection hole, and the second connection line is connected to the fan-out connection electrode through a second connection hole.

[0026] In an exemplary embodiment, the third conductive layer further includes a first power supply wiring extending along the first direction and a power supply connection electrode connected to the first power supply wiring, and the fourth conductive layer further includes a second power supply wiring extending along the second direction, and the second power supply wiring is connected to the power supply connection electrode via a third connection hole.

[0027] In an exemplary embodiment, a first break opening covered by the second power supply wiring or the second connecting line is provided between the first connecting line and the first power supply wiring, and a second break opening is provided between the second connecting line and the second power supply wiring, and a boundary of an orthogonal projection of the second break opening on the display substrate plane is aligned with a boundary of an orthogonal projection of the first connecting line or the first power supply wiring on the display substrate plane.

[0028] In an exemplary embodiment, the third conductive layer further includes a virtual electrode, and the second connecting line is connected to the virtual electrode through a connecting hole.

[0029] In an exemplary embodiment, the plurality of transistors includes at least a first transistor as a first initialization transistor, a second transistor as a compensation transistor, a third transistor as a driving transistor, a fourth transistor as a data writing transistor, a fifth transistor and a sixth transistor as light emission control transistors, and a seventh transistor as a second initialization transistor, the second transistor and the fourth transistor being located on either side of the third transistor in the second direction.

[0030] In an exemplary embodiment, the first transistor includes a first active layer, the second transistor includes a second active layer, the third transistor includes a third active layer, the fourth transistor includes a fourth active layer, the fifth transistor includes a fifth active layer, the sixth transistor includes a sixth active layer, and the seventh transistor includes a seventh active layer, the first active layer to the third active layer and the fifth active layer to the seventh active layer are an integrated structure connected to each other, and the fourth active layer is disposed separately.

[0031] In an exemplary embodiment, the fourth active layer is disposed on a side of the fifth active layer in the first direction, a first region of the fourth active layer is disposed on a side where the channel region of the fourth active layer is away from the third active layer, and a second region of the fourth active layer is disposed on a side where the channel region of the fourth active layer is closer to the third active layer.

[0032] In an exemplary embodiment, a first region of the fifth active layer is located between a second region of the fourth active layer and a second region of the sixth active layer.

[0033] In an exemplary embodiment, the storage capacitor includes a first plate and a second plate, wherein an orthogonal projection of the second plate on the base at least partially overlaps with an orthogonal projection of the first plate on the base, and an orthogonal projection of the second plate on the base at least partially overlaps with an orthogonal projection of a connection point of a first region of the third active layer, a second region of the fourth active layer, and a second region of the fifth active layer on the base.

[0034] In an exemplary embodiment, a convex portion is connected to the second plate, the convex portion being located at a corner of the second plate close to the fourth active layer, and an orthogonal projection of the convex portion on the base at least partially overlaps with an orthogonal projection of a connection point of a first region of the third active layer, a second region of the fourth active layer, and a second region of the fifth active layer on the base.

[0035] In an exemplary embodiment, the pixel driving circuit is connected to an emission control line and a first power supply line, the emission control line is configured to control turning on or off of the fifth transistor and the sixth transistor, the first power supply line is connected to the second plate via a first pole of the fifth transistor, and a positive projection of the first pole of the fifth transistor at the base and a positive projection of the emission control line at the base at least partially overlap.

[0036] In another aspect, the present disclosure further provides a display device, comprising the display substrate described above.

[0037] In another aspect, the present disclosure further provides a driving method for driving the above-mentioned display substrate, the display substrate comprising a plurality of circuit units, at least one circuit unit including a pixel driving circuit, the pixel driving circuit including at least a compensation transistor, a driving transistor and a data write transistor, a gate electrode of the compensation transistor is connected to a first scanning signal line, a first pole of the compensation transistor is connected to a gate electrode of the driving transistor, a second pole of the compensation transistor is connected to a second pole of the driving transistor, a gate electrode of the data write transistor is connected to a third scanning signal line, a first pole of the data write transistor is connected to a data signal line, and a second pole of the data write transistor is connected to a first pole of the driving transistor, and the driving method includes: In a frame refresh step, the first scanning signal line controls the turn-on of the compensation transistor, the third scanning signal line controls the turn-on of the data write transistor, and a data voltage outputted from the data signal line is supplied to a gate electrode of the driving transistor; In the step of holding a frame, the third scanning signal line controls turning on of the data writing transistor, and a data voltage outputted by the data signal line is supplied to a first electrode of the driving transistor.

[0038] In yet another aspect, the present disclosure further provides a method for manufacturing a display substrate, the display substrate comprising a plurality of circuit units, a plurality of data signal lines, and a plurality of data connecting lines, the data connecting lines including a first connecting line extending along a first direction and a second connecting line extending along a second direction, the data signal lines extending along the second direction, and the first direction and the second direction intersect, the manufacturing method comprising: the first and second connecting lines are connected to the first connecting line via the fan-out connecting electrode, the first connecting line is connected to the data signal line via the data connecting electrode, an orthogonal projection of the data connecting electrode on the display substrate plane at least partially overlaps with an orthogonal projection of the data signal line on the display substrate plane, an orthogonal projection of the fan-out connecting electrode on the display substrate plane at least partially overlaps with an orthogonal projection of the second connecting line on the display substrate plane, a first distance is between the data connecting electrode and the first connecting line, a second distance is between the fan-out connecting electrode and the first connecting line, the first distance and the second distance are greater than 0, and the first distance and the second distance are sizes in the second direction.

[0039] Other aspects will be understood after reading and understanding the drawings and detailed description.

[0040] The drawings are intended to provide an understanding of the technical solution of the present disclosure, to be a part of the specification, and to interpret the technical solution of the present disclosure together with the embodiments of the present disclosure, but are not intended to limit the technical solution of the present disclosure. [Brief description of the drawings]

[0041] [Figure 1] FIG. 2 is a structural schematic diagram of a display device. [Diagram 2] FIG. 2 is a schematic diagram showing the structure of a display substrate. [Diagram 3] FIG. 2 is a schematic planar structure diagram of a display region on a display substrate. [Figure 4]2 is a schematic diagram showing a cross-sectional structure of a display region on a display substrate. FIG. [Diagram 5] 3 is a schematic equivalent circuit diagram of a pixel driving circuit. FIG. [Figure 6A] FIG. 2 is a schematic planar structure diagram of a display substrate according to an exemplary embodiment of the present disclosure. [Figure 6B] FIG. 2 is a schematic diagram showing the layout of data connection lines according to an exemplary embodiment of the present disclosure. [Figure 7A] FIG. 13 is a schematic planar structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. [Figure 7B] FIG. 13 is a schematic diagram showing the layout of another data connection line according to an exemplary embodiment of the present disclosure. [Figure 8A] FIG. 13 is a schematic planar structure diagram of a further display substrate according to an exemplary embodiment of the present disclosure. [Figure 8B] FIG. 8B is an enlarged view of region C2 in FIG. 8A. [Figure 9A] FIG. 13 is a schematic planar structure diagram of a further display substrate according to an exemplary embodiment of the present disclosure. [Figure 9B] FIG. 9B is an enlarged view of region C2 in FIG. 9A. [Figure 10] FIG. 2 is a schematic planar structure diagram of power supply wiring according to an exemplary embodiment of the present disclosure. [Figure 11] FIG. 2 is a structural schematic diagram of a data connection line according to an exemplary embodiment of the present disclosure. [Figure 12] FIG. 2 is a structural schematic diagram of a circuit unit according to an exemplary embodiment of the present disclosure. [Figure 13] FIG. 13 is a schematic diagram showing the structure of a third conductive layer in FIG. [Figure 14] FIG. 13 is a schematic diagram showing the structure of a fourth conductive layer in FIG. [Figure 15] 1 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed in the E0 region. [Figure 16] 13 is a schematic diagram of a display substrate according to the present disclosure after a semiconductor layer pattern is formed in region F. FIG. [Figure 17] 1 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern is formed in the E0 region. [Figure 18]1 is a schematic diagram of a display substrate according to the present disclosure after a first conductive layer pattern is formed in region F. FIG. [Figure 19] 13 is a schematic diagram of the display substrate of the present disclosure after a second conductive layer pattern is formed in the E0 region. FIG. [Figure 20] 13 is a schematic diagram of the display substrate of the present disclosure after a second conductive layer pattern is formed in region F. FIG. [Figure 21] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth insulating layer pattern is formed in the E0 region. FIG. [Figure 22] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth insulating layer pattern is formed in region F. FIG. [Diagram 23] 13 is a schematic diagram of the display substrate of the present disclosure after a third conductive layer pattern is formed in the E0 region. FIG. [Figure 24] 13 is a schematic diagram of a display substrate according to the present disclosure after a third conductive layer pattern is formed in the E1 region. FIG. [Diagram 25] 13 is a schematic diagram of the display substrate of the present disclosure after a third conductive layer pattern is formed in the E2 region. FIG. [Figure 26] 13 is a schematic diagram of the display substrate of the present disclosure after a third conductive layer pattern is formed in the E3 region. FIG. [Figure 27] 13 is a schematic diagram of the display substrate of the present disclosure after a third conductive layer pattern is formed in the E4 region. FIG. [Figure 28] 13 is a schematic diagram of the display substrate of the present disclosure after a third conductive layer pattern is formed in region F. FIG. [Figure 29] 13 is a schematic diagram of the display substrate of the present disclosure after a first flat layer pattern is formed in the E0 region. FIG. [Diagram 30] 1 is a schematic diagram of a display substrate according to the present disclosure after a first flat layer pattern is formed in an E1 region. [Diagram 31] 13 is a schematic diagram of the display substrate of the present disclosure after a first flat layer pattern is formed in region E2. FIG. [Diagram 32] 13 is a schematic diagram of the display substrate of the present disclosure after a first flat layer pattern is formed in the E3 region. FIG. [Diagram 33] 13 is a schematic diagram of the display substrate of the present disclosure after a first flat layer pattern is formed in region E4. FIG. [Diagram 34] 13 is a schematic diagram of a display substrate according to the present disclosure after a first flat layer pattern is formed in region F. FIG. [Diagram 35] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern is formed in the E0 region. FIG. [Diagram 36] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern is formed in the E1 region. FIG. [Figure 37] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern is formed in the E2 region. FIG. [Figure 38] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern is formed in the E3 region. FIG. [Figure 39] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern is formed in the E4 region. FIG. [Diagram 40] 13 is a schematic diagram of the display substrate of the present disclosure after a fourth conductive layer pattern is formed in region F. FIG. [Diagram 41] FIG. 2 is a structural schematic diagram of a region where a first break opening is located according to an exemplary embodiment of the present disclosure. [Diagram 42] FIG. 4 is a structural schematic diagram of a region where a second break opening is located according to an exemplary embodiment of the present disclosure. [Diagram 43] FIG. 2 is an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. [Diagram 44] FIG. 4 is an operation timing diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0042] In order to clarify the objectives, technical solutions and advantages of the present disclosure, the embodiments of the present disclosure will be described in detail below with reference to the drawings. Note that the embodiments can be implemented in many different forms. As can be easily understood by those skilled in the art, the manner and content can be converted into various forms without departing from the spirit and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the description of the following embodiments. If there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other.

[0043] The proportions in the drawings in this disclosure may be used as a reference for the actual process, but are not limited thereto. For example, the ratio of the width and length of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of sub-pixels in each pixel are also not limited to the numbers shown in the drawings, and the drawings described in this disclosure are merely structural schematic diagrams, and one embodiment of the present disclosure is not limited to the shapes or values ​​shown in the drawings.

[0044] In this specification, ordinal numbers such as "first," "second," and "third" are used to avoid confusion of components and are not intended to be limiting in terms of quantity.

[0045] In this specification, for convenience, the positions of components are described with reference to the drawings using terms indicating orientation or positional relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., but this is for the purpose of explaining and simplifying the specification, and is not intended to indicate or suggest that the described device or element has a specific orientation and must be constructed and operated in a specific orientation. Therefore, it is not intended to limit the present disclosure. The positional relationship of the components is appropriately changed depending on the direction in which each component is described. Therefore, it is not limited to the terms described in the specification, and may be appropriately changed in some cases.

[0046] In this specification, unless otherwise specified and limited, the terms "attached", "coupled" and "connected" should be understood in a broad sense. For example, it may be a fixed connection, a detachable connection, or an integral connection. It may be a mechanical connection or an electrical connection. It may be a direct connection, an indirect connection via a linker, or an internal communication between two elements. Those skilled in the art can understand the specific meaning of the above technical terms in the present disclosure according to the specific situation.

[0047] In this specification, a transistor refers to an element including at least three terminals, a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between a drain electrode (drain electrode terminal, drain region, or drain electrode) and a source electrode (source electrode terminal, source region, or source electrode), and a current can flow through the drain electrode, the channel region, and the source electrode. In this specification, the channel region refers to a region through which a current mainly flows.

[0048] In this specification, the first pole may be a drain electrode and the second pole may be a source electrode, or the first pole may be a source electrode and the second pole may be a drain electrode. When using transistors with opposite polarity, or when the current direction during operation in the circuit changes, the functions of "source electrode" and "drain electrode" may be interchanged. Thus, in this specification, "source electrode" and "drain electrode" may be interchanged, and "source terminal" and "drain terminal" may be interchanged.

[0049] In this specification, "electrically connected" includes cases where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited as long as it is capable of transmitting and receiving electrical signals between the components being connected. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and other elements having various functions.

[0050] In this specification, "parallel" refers to a state in which the angle between two straight lines is between -10° and 10°, including a state in which the angle is between -5° and 5°, and "perpendicular" refers to a state in which the angle between two straight lines is between 80° and 100°, including a state in which the angle is between 85° and 95°.

[0051] In this specification, the terms "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film." Similarly, an "insulating film" may be changed to an "insulating layer."

[0052] The triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not intended to be exact, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and may have small deformations due to tolerances, and may have chamfers, arc edges, and deformations.

[0053] In this disclosure, "about" refers to a case where the boundary is not precisely defined, but rather allows for numerical values ​​within process and measurement error.

[0054] FIG. 1 is a structural schematic diagram of a display device. As shown in FIG. 1, the display device includes a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is respectively connected to the data driver, the scan driver, and the light-emitting driver, the data drivers are respectively connected to a plurality of data signal lines (D1 to Dn), the scan drivers are respectively connected to a plurality of scan signal lines (S1 to Sm), and the light-emitting driver is respectively connected to a plurality of light-emitting signal lines (E1 to Eo). The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers, and at least one sub-pixel Pxij may include a circuit unit and a light-emitting device connected to the circuit unit, and the circuit unit may include at least a pixel driving circuit, and the pixel driving circuit is respectively connected to the scan signal line, the light-emitting signal line, and the data signal line. In an exemplary embodiment, the timing controller provides a gray value and a control signal conforming to the standard of the data driver to the data driver, provides a clock signal, a scan start signal, etc. conforming to the standard of the scan driver to the scan driver, and provides a clock signal, a firing stop signal, etc. conforming to the standard of the light-emitting driver to the light-emitting driver. The data driver generates data voltages to be provided to the data signal lines D1, D2, D3, ..., Dn using the gray value and the control signal received from the timing controller. For example, the data driver may sample the gray value using a clock signal, and apply data voltages corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver may generate scan signals to be provided to the scan signal lines S1, S2, S3, ..., Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver may sequentially provide scan signals having a turn-on level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and may generate scan signals by sequentially transferring the scan start signal provided in the form of a turn-on level pulse to the next stage circuit under the control of a clock signal, where m may be a natural number.The light emitting driver may receive a clock signal, a firing stop signal, etc. from the timing controller to generate firing signals to be provided to the light emitting signal lines E1, E2, E3, ..., Eo. For example, the light emitting driver may sequentially provide firing signals having cut-off level pulses to the light emitting signal lines E1 to Eo. For example, the light emitting driver may be configured in the form of a shift register, and may generate firing signals by sequentially transferring the firing stop signal provided in the form of a cut-off level pulse to a next stage circuit under the control of a clock signal, where o may be a natural number. In an exemplary embodiment, the pixel array may be disposed on a display substrate.

[0055] 2 is a structural schematic diagram of a display substrate. As shown in FIG. 2, the display substrate may include a display area 100, a binding area 200 located on one side of the display area 100, and a frame area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area and may include a plurality of sub-pixels Pxij constituting a pixel array, and the plurality of sub-pixels Pxij are set to display moving images or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, the display substrate may adopt a flexible substrate, so that the display substrate may be deformable, such as curled, bent, folded, or rolled up.

[0056] In an exemplary embodiment, the binding region 200 may include a fan-out region, a folding region, a driving chip region, and a binding pin region, which are sequentially arranged along a direction away from the display region, and the fan-out region is connected to the display region 100 and includes at least a data fan-out line, and the plurality of data fan-out lines are configured to connect the data signal lines of the display region in a fan-out wiring manner. The folding region may include a composite insulating layer connected to the fan-out region and having a groove, and is configured to fold the binding region to the back surface of the display region. The driving chip region may include an integrated circuit (abbreviated as IC), and the integrated circuit is configured to be connected to the plurality of data fan-out lines. The binding pin region may include a binding pad (Bonding Pad) configured to be bound and connected to an external flexible printed circuit (abbreviated as FPC).

[0057] In an exemplary embodiment, the frame region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region, which are sequentially arranged along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit, and the gate driving circuit is connected to a first scanning line, a second scanning line, and a light emission control line of a pixel driving circuit in the display region 100. The power line region is connected to the circuit region and may include at least a frame power lead, and the frame power lead extends along a direction parallel to the edge of the display region and is connected to a cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks provided in the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove provided in the composite insulating layer, and the cutting groove is set so that a cutting device cuts along the cutting groove respectively after the manufacturing of all the film layers of the display substrate is completed.

[0058] In an exemplary embodiment, a first isolation dam and a second isolation dam may be installed in the fan-out region in the binding region 200 and the power line region in the frame region 300, and the first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display region to form a ring-shaped structure surrounding the display region 100, and the edge of the display region is the edge of one side of the binding region or frame region of the display region.

[0059] 3 is a schematic diagram of a plane structure of a display area on a display substrate. As shown in FIG. 3, the display substrate may include a plurality of pixel units P arranged in a matrix manner, and at least one pixel unit P may include a first sub-pixel P1 emitting a first color light, a second sub-pixel P2 emitting a second color light, and a third sub-pixel P3 and a fourth sub-pixel P4 emitting a third color light. Each sub-pixel may include a light-emitting device, which is connected to a pixel driving circuit of a corresponding circuit unit, and the pixel driving circuits are respectively connected to a scanning signal line, a data signal line and an emission signal line, and the pixel driving circuit is configured to receive a data voltage transmitted from the data signal line under the control of the scanning signal line and the emission signal line, and output a corresponding current to the light-emitting device, and the light-emitting device is configured to emit light with a corresponding brightness in response to the current output from the pixel driving circuit of the sub-pixel in which it is located.

[0060] In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixel may be a rectangle, a rhombus, a pentagon, or a hexagon, and the four sub-pixels may be arranged in a diamond manner to form an RGBG pixel array. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal parallel manner, a vertical parallel manner, a square manner, etc., but the present disclosure is not limited thereto.

[0061] In an exemplary embodiment, a pixel unit includes three sub-pixels, and the three sub-pixels may be arranged in a manner such as horizontal parallel, vertical parallel, or square, and the present disclosure is not limited thereto.

[0062] 4 is a cross-sectional structure schematic diagram of a display area in a display substrate, showing the structure of four sub-pixels in the display area. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display substrate may include a driving structure layer 102 disposed on a base 101, a light-emitting structure layer 103 disposed on a side of the driving structure layer 102 away from the base 101, and a sealing structure layer 104 disposed on a side of the light-emitting structure layer 103 away from the base 101. In some possible implementations, the display substrate may include other film layers, such as touch structure layers, and the present disclosure is not limited thereto.

[0063] In an exemplary embodiment, the base 101 may be a flexible base or a rigid base. The driving structure layer 102 may include a plurality of circuit units, and the circuit unit may include a pixel driving circuit, which is composed of at least a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 may include a plurality of sub-pixels, and the sub-pixel may include at least an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304, where the anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, and the cathode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 emits light of a corresponding color by driving the anode 301 and the cathode 304. The sealing structure layer 104 may include a first sealing layer 401, a second sealing layer 402, and a third sealing layer 403 which are stacked together, where the first sealing layer 401 and the third sealing layer 403 may be made of inorganic materials, and the second sealing layer 402 may be made of organic materials. The second sealing layer 402 is placed between the first sealing layer 401 and the third sealing layer 403 to form a stacked structure of inorganic material / organic material / inorganic material, which can prevent external water vapor from entering the light-emitting structure layer 103.

[0064] In an exemplary embodiment, the organic light-emitting layer may include an emissive layer (EML) and any one or more of a hole-injection layer (HIL), a hole-transport layer (HTL), an electron-blocking layer (EBL), a hole-blocking layer (HBL), an electron-transport layer (ETL), and an electron-injection layer (EIL). In an exemplary embodiment, the hole-injection layer, the hole-transport layer, the electron-blocking layer, the hole-blocking layer, the electron-transport layer, and the electron-injection layer of all the subpixels may be common layers connected to each other, and the emissive layers of adjacent subpixels may have a small amount of overlap or may be separated from each other.

[0065] 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may be a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. As shown in FIG. 5, the pixel driving circuit may include seven transistors (first transistor T1 to seventh transistor T7) and one storage capacitor C, and each pixel driving circuit is connected to seven signal lines (data signal line D, first scanning signal line S1, second scanning signal line S2, light emission signal line E, first initial signal line INIT1, second initial signal line INIT2, and first power supply line VDD).

[0066] In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. Among them, the first node N1 is respectively connected to a first pole of the third transistor T3, a second pole of the fourth transistor T4, and a second pole of the fifth transistor T5. The second node N2 is respectively connected to a second pole of the first transistor T3, a first pole of the second transistor T2, a gate electrode of the third transistor T3, and a second end of the storage capacitor C. The third node N3 is respectively connected to a second pole of the second transistor T2, a second pole of the third transistor T3, and a first pole of the sixth transistor T6.

[0067] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end of the storage capacitor C is connected to a second node N2, i.e., the second end of the storage capacitor C is connected to the gate electrode of the third transistor T3.

[0068] The gate electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor T1 is connected to the second node N2. When a turn-on level scanning signal is applied to the second scanning signal line S2, the first transistor T1 transfers a first initial voltage to the gate electrode of the third transistor T3 to initialize the charge amount of the gate electrode of the third transistor T3.

[0069] The gate electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When a turn-on level scanning signal is applied to the first scanning signal line S1, the second transistor T2 connects the gate electrode of the third transistor T3 to the second electrode.

[0070] The gate electrode of the third transistor T3 is connected to the second node N2, i.e., the gate electrode of the third transistor T3 is connected to the second end of the storage capacitor C, the first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS according to the potential difference between its gate electrode and first electrode.

[0071] The gate electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may also be called a switch transistor, a scanning transistor, etc. When a turn-on level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 inputs the data voltage of the data signal line D to the pixel driving circuit.

[0072] The gate electrode of the fifth transistor T5 is connected to the light emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The gate electrode of the sixth transistor T6 is connected to the light emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When a turn-on level light emitting signal is applied to the light emitting signal line E, the fifth transistor T5 and the sixth transistor T6 form a driving current path between the first power supply line VDD and the second power supply line VSS, thereby causing the light emitting device to emit light.

[0073] The gate electrode of the seventh transistor T7 is connected to the first scanning signal line S1, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light-emitting device. When a turn-on level scanning signal is applied to the first scanning signal line S1, the seventh transistor T7 delivers a second initial voltage to the first electrode of the light-emitting device to initialize the amount of charge stored in the first electrode of the light-emitting device or release the amount of charge stored in the first electrode of the light-emitting device.

[0074] In an exemplary embodiment, the light emitting device may be an OLED and include a first electrode (anode), an organic light emitting layer, and a second electrode (cathode) that are stacked together, or the light emitting device may be a QLED and include a first electrode (anode), a quantum dot light emitting layer, and a second electrode (cathode) that are stacked together.

[0075] In an exemplary embodiment, the second pole of the light-emitting device is connected to a second power supply line VSS, the signal on the second power supply line VSS is a continuously provided low-level signal, and the signal on the first power supply line VDD is a continuously provided high-level signal.

[0076] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. By adopting the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0077] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may adopt low temperature polysilicon film transistors, or oxide film transistors, or both low temperature polysilicon film transistors and oxide film transistors. The active layer of the low temperature polysilicon film transistor adopts low temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide film transistor adopts oxide semiconductor (Oxide). The low temperature polysilicon film transistor has advantages such as high mobility and fast charging, and the oxide film transistor has advantages such as low leakage current. The low temperature polysilicon film transistor and the oxide film transistor are integrated into one display substrate, i.e., the LTPS+Oxide (abbreviated as LTPO) display substrate, and the advantages of both can be utilized to realize low frequency driving, reduce power consumption, and improve display quality.

[0078] In an exemplary embodiment, taking the first transistor T1 to the seventh transistor T7 as an example, the operation process of the pixel driving circuit may include the following steps.

[0079] The first stage A1 is called a reset stage, in which the signal of the second scanning signal line S2 is a low level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high level signals. The signal of the second scanning signal line S2 is a low level signal, which turns on the first transistor T1, provides the first initial voltage of the first initial signal line INIT1 to the second node N2, initializes the storage capacitor C, and clears the original data voltage in the storage capacitor. The signals of the first scanning signal line S1 and the light-emitting signal line E are high level signals, which cuts off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6 and the seventh transistor T7, and the OLED does not emit light in this stage.

[0080] The second stage A2 is called a data writing stage or threshold compensation stage, in which the signal of the first scanning signal line S1 is a low level signal, the signals of the second scanning signal line S2 and the light emission signal line E are high level signals, and the data signal line D outputs a data voltage. In this stage, the second end of the storage capacitor C is low level, so the third transistor T3 is turned on. The signal of the first scanning signal line S1 is a low level signal, which turns on the second transistor T2, the fourth transistor T4 and the seventh transistor T7. With the second transistor T2 and the fourth transistor T4 turned on, the data voltage output from the data signal line D is provided to the second node N2 via the first node N1, the turned-on third transistor T3, the third node N3 and the turned-on second transistor T2, and the difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is stored in the storage capacitor C. The voltage of the second end (second node N2) of the storage capacitor C is Vd-|Vth|, where Vd is the data voltage output from the data signal line D, and Vth is the threshold voltage of the third transistor T3. When the seventh transistor T7 is turned on, the second initial voltage of the second initial signal line INIT2 is provided to the first pole of the OLED, which initializes (resets) the first pole of the OLED, clears the voltage previously stored therein, completes the initialization, and ensures that the OLED does not emit light. When the signal of the second scanning signal line S2 is a high level signal, the first transistor T1 is cut off. When the signal of the emission signal line E is a high level signal, the fifth transistor T5 and the sixth transistor T6 are cut off.

[0081] The third stage A3 is called a light-emitting stage, in which the signal of the light-emitting signal line E is a low-level signal, and the signals of the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal of the light-emitting signal line E is a low-level signal, which turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first pole of the OLED through the turned-on fifth transistor T5, the third transistor T3 and the sixth transistor T6, thereby driving the OLED to emit light.

[0082] In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd-|Vth|, the driving current of the third transistor T3 is expressed by the following formula. I=K*(Vgs-Vth) 2 =K*[(Vdd-Vd+|Vth|)-Vth] 2 =K*[Vdd-Vd] 2 In the formula, I is the driving current flowing through the third transistor T3, i.e., the driving current for driving the OLED, K is a constant, Vgs is the voltage difference between the gate electrode and the first electrode of the third transistor T3, Vth is the threshold voltage of the third transistor T3, Vd is the data voltage output from the data signal line D, and Vdd is the data voltage output from the first power supply line VDD.

[0083] With the development of OLED display technology, consumers' requirements for the display effect of display products are getting higher and higher, and extremely narrow frames have become a new trend in the development of display products, so narrowing the frame and even frameless design are increasingly being attached to the design of OLED display products. In a display substrate, the binding area generally includes a fan-out area, a bend area, a driving chip area, and a binding pin area, which are sequentially arranged along the direction away from the display area. Because the width of the binding area is smaller than the width of the display area, the signal lines of the integrated circuit and the binding pads in the binding area need to be introduced into the relatively wide display area through the fan-out area in a fan-out wiring manner. The larger the difference in width between the display area and the binding area, the more oblique fan-out lines will be in the fan-shaped area, and the greater the distance between the driving chip area and the display area, so the occupied space of the fan-shaped area is large, and the difficulty of designing the narrow width of the lower frame is high, and the lower frame is always maintained at about 2.0 mm. In another display substrate, a frame power lead is usually installed in the frame area, and the frame power lead is configured to continuously provide and transmit a low-voltage power signal. In order to reduce the voltage drop of the low-voltage power signal, the width of the frame power lead is large, which results in large widths of the frames on the left and right sides of the display device.

[0084] 6A is a schematic diagram of a plane structure of a display substrate according to an exemplary embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate may include a driving structure layer disposed on a base, a light-emitting structure layer disposed on a side of the driving structure layer away from the base, and a sealing structure layer disposed on a side of the light-emitting structure layer away from the base. As shown in FIG. 6A, in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a binding area 200 disposed on one side of the display area 100 in the second direction Y, and a frame area 300 disposed on the other side of the display area 100. In an exemplary embodiment, the driving structure layer of the display area 100 may include a plurality of circuit units, a plurality of data signal lines 60, and a plurality of data connection lines 70, which constitute a plurality of unit rows and a plurality of unit columns, and at least one of the circuit units may include a pixel driving circuit configured to output a corresponding current to a connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of sub-pixels constituting a pixel array, and at least one of the sub-pixels may include a light-emitting device, which is connected to a pixel driving circuit of a corresponding circuit unit, and which is configured to emit light at a corresponding brightness in response to a current output by the pixel driving circuit to which it is connected.

[0085] In an exemplary embodiment, at least one data signal line 60 is connected to a plurality of pixel driving circuits in one unit column, the data signal line 60 is configured to provide a data signal to the connected pixel driving circuits, and at least one data connection line 70 is connected corresponding to the data signal line 60, and the data connection line 70 is configured to connect the data signal line 60 to a corresponding out-line 80 in the binding region 200 via the data connection line 70.

[0086] In an exemplary embodiment, a subpixel as described in the present disclosure refers to an area partitioned according to a light emitting device. A circuit unit as described in the present disclosure refers to an area partitioned according to a pixel driving circuit. In an exemplary embodiment, the position of the orthogonal projection at the base of the subpixel and the position of the orthogonal projection at the base of the circuit unit may correspond, or the position of the orthogonal projection at the base of the subpixel and the position of the orthogonal projection at the base of the circuit unit may not correspond.

[0087] In an exemplary embodiment, a plurality of circuit units sequentially arranged along a first direction X can be referred to as unit rows, and a plurality of circuit units sequentially arranged along a second direction Y can be referred to as unit columns, where the plurality of unit rows and the plurality of unit columns constitute a circuit unit array arranged in an array, and the first direction X and the second direction Y intersect.

[0088] In an exemplary embodiment, the second direction Y (vertical direction) may be the extension direction of the data signal lines, and the first direction X (horizontal direction) may be perpendicular to the second direction Y.

[0089] In an exemplary embodiment, the binding area 200 may include a lead area 201, a bent area, a driving chip area, and a binding pin area, which are sequentially arranged along a direction away from the display area, the lead area 201 is connected to the display area 100, and the bent area is connected to the lead area 201. A plurality of lead lines 80 may be arranged in the lead area 201, and the plurality of lead lines 80 extend along a direction away from the display area, with first ends of some of the lead lines 80 corresponding to the data connection lines 70 in the display area 100, and first ends of other lead lines corresponding to the data signal lines 60 in the display area 100, and second ends of all the lead lines 80 extending along the second direction Y are connected to the integrated circuits in the driving chip area across the bent area, so that the integrated circuits apply data signals to the data signal lines through the lead lines and the data connection lines. Since the data connection lines are arranged in the display area, the length of the lead area in the second direction Y can be effectively reduced, and the width of the lower frame can be greatly reduced, which improves the screen occupancy rate and is favorable for realizing full-screen display.

[0090] In an exemplary embodiment, the plurality of data signal lines in the display area 100 may extend along the second direction Y and be arranged along the first direction X so that the numbers increase in sequence at set intervals. The plurality of data signal lines may be divided into a first data signal line group and a second data signal line group depending on whether they are connected to data connection lines, the plurality of data signal lines in the first data signal line group being connected to the data connection lines, and the plurality of data signal lines in the second data signal line group not being connected to the data connection lines. The plurality of lead-out lines in the lead area 201 may be divided into a first lead-out line group and a second lead-out line group depending on whether they are connected to data connection lines or data signal lines, the plurality of lead-out lines in the first lead-out line group being connected to the data connection lines, and the plurality of lead-out lines in the second lead-out line group being connected to the data signal lines.

[0091] In an exemplary embodiment, first ends of the plurality of data connection lines 70 provided in the display area 100 are connected to the plurality of data signal lines 60 of the first data signal line group through the first connection hole, and second ends of the plurality of data connection lines 70 extend toward the binding area 200, straddling the display area boundary B, and connected to the plurality of lead lines 80 of the first lead line group in the lead area 201, so that the plurality of data signal lines 60 of the first data signal line group in the display area 100 are indirectly connected to the lead lines 80 through the data connection lines 70. The plurality of data signal lines 60 of the second data signal line group extend toward the binding area 200, straddling the display area boundary B, and connected to the plurality of lead lines 80 of the second lead line group in the lead area 201, so that the plurality of data signal lines 60 of the second data signal line group in the display area 100 are directly connected to the lead lines 80. In the exemplary embodiment, the display area boundary B is the boundary between the display area 100 and the binding area 200 .

[0092] In the present disclosure, A extending along direction B means that A includes a main part and a secondary part connected to the main part, the main part is a line, a line segment, or an elongated object, the main part extends along direction B, and the length of the main part extending along direction B is greater than the length of the secondary part extending along other directions. In the following description, "A extending along direction B" always means "the main body part of A extends along direction B". In an exemplary embodiment, the second direction Y may be a direction from the display area toward the binding area, and the opposite direction of the second direction Y may be a direction from the binding area toward the display area.

[0093] In an exemplary embodiment, the outgoing wire 80 may be connected directly to the data signal line 60, and the outgoing wire 80 may be connected to the data connection line 70, or through a via, although the present disclosure is not limited thereto.

[0094] In an exemplary embodiment, the display area 100 may have a center line O, and the multiple data signal lines 60, the multiple data connection lines 70, and the multiple lead-out lines 80 in the lead area 201 in the display area 100 may be arranged symmetrically with respect to the center line O, and the center line O may be a straight line extending along the second direction Y, dividing the multiple unit columns in the display area 100 into two equal parts.

[0095] In an exemplary embodiment, the data connection line 70 may include a first connection line and a second connection line connected to each other, a first end of the first connection line is connected to the data signal line through a first connection hole, a second end of the first connection line extends along a first direction X or a direction opposite to the first direction X and then is connected to a first end of a second connection line, and a second end of the second connection line extends along a second direction Y toward the lead area and then is connected to a lead line.

[0096] In an exemplary embodiment, the plurality of second connecting lines may be arranged parallel to the data signal lines, and the plurality of first connecting lines may be arranged perpendicular to the data signal lines.

[0097] In an exemplary embodiment, the spacing between adjacent second connecting lines may be approximately the same, and the spacing between adjacent first connecting lines may be approximately the same, and the present disclosure is not limited thereto.

[0098] In an exemplary embodiment, m-1 data signal lines may be provided between two first connection holes adjacent in the first direction X, where m may be a positive integer equal to or greater than 1. In an exemplary embodiment, m may be 1, 2, 3, 4, 5, or 6. For example, in FIG. 6A, no data signal line is provided between two adjacent first connection holes.

[0099] In an exemplary embodiment, n data signal lines may be provided between adjacent second connecting lines in the first direction X, where n may be a positive integer equal to or greater than 1. In an exemplary embodiment, n may be 1, 2, 3, 4, 5, or 6. For example, in FIG. 6A, two data signal lines are provided between adjacent second connecting lines.

[0100] 6B is a schematic diagram of the arrangement of data connection lines according to an exemplary embodiment of the present disclosure, which is an enlarged view of the C1 area of ​​FIG. 6A, showing a structure of 16 data signal lines, 4 data connection lines and 16 lead lines. As shown in FIG. 6B, in an exemplary embodiment, the multiple data signal lines in the display area may include the first data signal line 60-1 to the sixteenth data signal line 60-16, the multiple data connection lines in the display area may include the first data connection line 70-1 to the fourth data connection line 70-4, and the multiple lead lines in the lead area 201 may include the first lead line 80-1 to the sixteenth lead line 80-16.

[0101] In an exemplary embodiment, the first data signal line group includes the first data signal line 60-1 to the fourth data signal line 60-4, the second data signal line group includes the remaining 12 data signal lines, and the first data signal line 60-1 to the sixteenth data signal line 60-16 may be sequentially arranged along the first direction X.

[0102] In an exemplary embodiment, the first group of outgoing lines includes the first outgoing line 80-1 to the fourth outgoing line 80-4, and the second group of outgoing lines includes the remaining 12 outgoing lines, and the multiple outgoing lines of the first group of outgoing lines may be sequentially arranged along the opposite direction to the first direction X, and the multiple outgoing lines of the second group of outgoing lines may be sequentially arranged along the first direction X, and two outgoing lines of the second group of outgoing lines are arranged between adjacent outgoing lines of the first group of outgoing lines. For example, a fourteenth drawer line 80-14 and a fifteenth drawer line 80-15 may be installed between the first drawer line 80-1 and the second drawer line 80-2, a twelfth drawer line 80-12 and a thirteenth drawer line 80-13 may be installed between the second drawer line 80-2 and the third drawer line 80-3, and a tenth drawer line 80-10 and an eleventh drawer line 80-11 may be installed between the third drawer line 80-3 and the fourth drawer line 80-4.

[0103] In an exemplary embodiment, the first connection hole may be in the circuit unit of the first unit column to the fourth unit column. The first data connection line 70-1 has a first end connected to the first data signal line 60-1 through the first connection hole in the display region 100, and a second end extending to the lead area 201 and then connected to the first lead line 80-1. The second data connection line 70-2 has a first end connected to the second data signal line 60-2 through the first connection hole in the display region 100, and a second end extending to the lead area 201 and then connected to the second lead line 80-2. The third data connection line 70-3 has a first end connected to the second data signal line 60-2 through the first connection hole in the display region 100, and a second end extending to the lead area 201 and then connected to the third lead line 80-3. The fourth data connection line 70-4 has a first end connected to the fourth data signal line 60-4 through a first connection hole in the display region 100, and a second end extending to the lead area 201 and then connected to the fourth lead line 80-4.

[0104] In an exemplary embodiment, the multiple data signal lines of the second data signal line group extend to the lead area 201 and are then connected to the multiple lead-out lines of the second lead-out line group.

[0105] In an exemplary embodiment, the distance between the edge B of the display area and the plurality of first connection holes to which the data connection lines are connected correspondingly to the data signal lines may be different. For example, the distance between the first connection hole to which the first data connection line 70-1 is connected to the first data signal line 60-1 and the edge B of the display area may be greater than the distance between the first connection hole to which the second data connection line 70-2 is connected to the second data signal line 60-2 and the edge B of the display area. Also, for example, the distance between the first connection hole to which the second data connection line 70-2 is connected to the second data signal line 60-2 and the edge B of the display area may be greater than the distance between the first connection hole to which the third data connection line 70-3 is connected to the third data signal line 60-3 and the edge B of the display area. Furthermore, for example, the distance between the first connection hole through which the third data connection line 70-3 is connected to the third data signal line 60-3 and the edge B of the display area may be greater than the distance between the first connection hole through which the fourth data connection line 70-4 is connected to the fourth data signal line 60-4 and the edge B of the display area.

[0106] In an exemplary embodiment, the data connecting line may include a first connecting line and a second connecting line connected in sequence. The first connecting line may be linearly shaped extending along a first direction X, and the second connecting line may be linearly shaped extending along a second direction Y. A first end of the first connecting line is connected to the data signal line through a first connecting hole, a second end of the first connecting line extends along the first direction X or a direction opposite to the first direction X and then connected to a first end of the second connecting line, and a second end of the second connecting line extends along the second direction Y toward the lead area and then connected to the lead line.

[0107] In an exemplary embodiment, multiple data signal lines may be provided between adjacent second connecting lines in the first direction X. For example, one data signal line may be provided between adjacent second connecting lines in the first direction X. Also, for example, two data signal lines may be provided between adjacent second connecting lines in the first direction X.

[0108] In an exemplary embodiment, the data output pin of an integrated circuit can utilize a reverse order design to achieve data signal output without sudden load changes and improve display quality.

[0109] In an exemplary embodiment, when the display resolution of the display substrate is M*N, if one data connecting line is inserted into a data signal lines (i.e., a data signal lines are installed between the second connecting lines adjacent to each other in the first direction X), the order of the data output pins (PINs) of the integrated circuit from left to right is as follows: [M / (a+1)]+1, [M / (a+1)]+2, 1, [M / (a+1)]+3, [M / (a+1)]+4, 2, [M / (a+1)]+5, [M / (a+1)]+6, 3 …[M-1], M, [M / (a+1)]…[M+1], [M+2], [2M-M / (a+1)+1]…2M, [2M-M / (a+1)-1], [2M-M / (a+1)].

[0110] For example, in the case of a display board with a resolution of 1080x2160, the number of data output pins of the integrated circuit is 2160. If one data connection line is inserted into two data signal lines, the order of the data output pins of the integrated circuit from left to right is as follows: D361, D362, D1, D363, D364, D2, D365, D366, D3, D367, D368, D4, D369, D370...D1073, D1074, D357, D1075, D1076, D358, D1 077, D1078, D359, D1079, D1080, D360...D1793, D1794, D2158, D1795, D1796, D2159, D1797, D1798, D2160, D1799, D1800.

[0111] In the exemplary embodiment, the reverse order design is only one implementation, and the actual design can adopt the implementation of the forward order design. For example, the cross-line design can make the order of pin output signals of the integrated circuit match the arrangement order of data signal lines in the display area.

[0112] 7A is a schematic planar structure diagram of another display substrate according to an exemplary embodiment of the present disclosure. As shown in FIG. 7A, the main structure of the display substrate according to this embodiment is substantially the same as the main structure of the display substrate shown in FIG. 6A, except that one data signal line is provided between two adjacent first connection holes according to this embodiment.

[0113] 7B is a schematic diagram of another data connection line arrangement according to an exemplary embodiment of the present disclosure, which is an enlarged view of region C1 in FIG. 7A, showing a structure of 16 data signal lines, 4 data connection lines and 16 lead-out lines. As shown in FIG. 7B, the first data signal line group includes four odd-numbered data signal lines (the first data signal line 60-1, the third data signal line 60-3, the fifth data signal line 60-5 and the seventh data signal line 60-7), and the second data signal line group includes the remaining 12 data signal lines, and the first data signal line 60-1 to the sixteenth data signal line 60-16 can be sequentially arranged along the first direction X.

[0114] In an exemplary embodiment, the first group of outgoing lines includes four odd-numbered outgoing lines (the first group of outgoing lines 80-1, the third group of outgoing lines 80-3, the fifth group of outgoing lines 80-5 and the seventh group of outgoing lines 80-7), and the second group of outgoing lines includes the remaining 12 outgoing lines, and the multiple outgoing lines of the first group of outgoing lines may be sequentially arranged along the opposite direction to the first direction X, and the multiple outgoing lines of the second group of outgoing lines may be sequentially arranged along the first direction X, and two outgoing lines of the second group of outgoing lines are arranged between adjacent outgoing lines of the first group of outgoing lines. For example, the multiple lead lines may include a second lead line 80-2, a fourth lead line 80-4, a sixth lead line 80-6, an eighth lead line 80-8, a ninth lead line 80-9, a seventh lead line 80-7, a tenth lead line 80-10, an eleventh lead line 80-11, a fifth lead line 805, a twelfth lead line 80-12, a thirteenth lead line 80-13, a third lead line 803, a fourteenth lead line 80-14, a fifteenth lead line 80-15, a first lead line 80-1 and a sixteenth lead line 80-16, which are sequentially arranged along the first direction X.

[0115] In an exemplary embodiment, a fourteenth lead-out line 80-14 and a fifteenth lead-out line 80-15 may be provided between the first lead-out line 80-1 and the third lead-out line 80-3, a twelfth lead-out line 80-12 and a thirteenth lead-out line 80-13 may be provided between the third lead-out line 80-3 and the fifth lead-out line 80-5, and a tenth lead-out line 80-10 and an eleventh lead-out line 80-11 may be provided between the fifth lead-out line 80-5 and the seventh lead-out line 80-7.

[0116] In an exemplary embodiment, the first connection hole is provided in the circuit unit of the odd-numbered unit column. The first data connection line 70-1 has a first end connected to the first data signal line 60-1 through the first connection hole in the display area 100, and a second end extending to the lead area 201 and then connected to the first lead line 80-1. The second data connection line 70-2 has a first end connected to the third data signal line 60-3 through the first connection hole in the display area 100, and a second end extending to the lead area 201 and then connected to the third lead line 80-3. The third data connection line 70-3 has a first end connected to the fifth data signal line 60-5 through the first connection hole in the display area 100, and a second end extending to the lead area 201 and then connected to the fifth lead line 80-5. The fourth data connection line 70-4 has a first end connected to the seventh data signal line 60-7 through a first connection hole in the display region 100, and a second end extending to the lead area 201 and then connected to the seventh lead line 80-7.

[0117] In an exemplary embodiment, the multiple data signal lines of the second data signal line group are connected to the multiple lead-out lines of the second lead-out line group after extending to the lead area 201. For example, the second data signal line 60-2, the fourth data signal line 60-4, the sixth data signal line 60-6, and the eighth data signal line 60-8 to the sixteenth data signal line 60-16 are connected to the corresponding lead-out lines.

[0118] In an exemplary embodiment, the distances between the edge B of the display area and the plurality of first connection holes, to which the data connection lines are correspondingly connected to the data signal lines, may be different.

[0119] In an exemplary embodiment, two data signal lines are installed between adjacent second connection lines in the first direction X, and a configuration can be formed in which the data connection lines are connected to the data signal lines of odd-numbered unit columns, and two data signal lines are installed between adjacent second connection lines.

[0120] In an exemplary embodiment, some of the second group of lead-out lines are straight lines parallel to the data signal lines, and some of the other lead-out lines are bent lines. For example, the tenth lead-out line 80-10 to the sixteenth lead-out line 80-16 may be straight lines, and the second lead-out line 80-2, the fourth lead-out line 80-4, and the sixth lead-out line 80-6 may be bent lines.

[0121] In an exemplary embodiment, the positions of the sub-pixels in the light-emitting structure layer may correspond to the positions of the circuit units in the driving structure layer. The odd-numbered unit column can be called the first unit column, and the circuit units in the odd-numbered unit column correspond to the red sub-pixels and the blue sub-pixels, i.e. the pixel driving circuits of the circuit units in the odd-numbered unit column are respectively connected to the red light-emitting device that emits red light and the blue light-emitting device that emits blue light. The even-numbered unit column can be called the second unit column, and the circuit units in the even-numbered unit column correspond to the green sub-pixels, i.e. the pixel driving circuits of the circuit units in the even-numbered unit column are respectively connected to the green light-emitting device that emits green light.

[0122] In an exemplary embodiment, the first connection line is connected to the data signal line of the first unit column through the first connection hole, and the first connection line is not connected to the data signal line of the second unit column. In the present disclosure, the first connection hole is provided in the odd-numbered unit column, i.e., the data signals of the red sub-pixel and the blue sub-pixel are transmitted through the data connection line, which not only facilitates the layout of the data connection line, but also utilizes the reverse order design to realize no sudden change in load, and improves the display quality.

[0123] In some possible exemplary embodiments, the data connection lines may be connected to the data signal lines of odd-numbered unit columns, and one data signal line may be provided between adjacent second connection lines in the first direction X, and the present disclosure is not limited thereto.

[0124] In the present disclosure, by providing a data connection line within the display area and connecting the lead-out line of the binding area to the data signal line via the data connection line, there is no need to provide a fan-shaped diagonal line in the lead area, which effectively shortens the length of the lead area, significantly reduces the width of the lower frame, improves the screen occupancy rate, and is advantageous for realizing full-screen display.

[0125] Fig. 8A is a schematic planar structure diagram of a further display substrate according to an exemplary embodiment of the present disclosure, and Fig. 8B is an enlarged view of region C2 of Fig. 8A. The driving structure layer of the display region 100 may include a plurality of circuit units constituting a circuit unit array, a plurality of data signal lines 60, a plurality of data connection lines 70, and a power supply wiring 90 having a net-like communication structure, and the layout and structure of the plurality of circuit units, the plurality of data signal lines 60, and the plurality of data connection lines 70 are substantially the same as those shown in Fig. 6A.

[0126] As shown in FIGS. 8A and 8B, in an exemplary embodiment, the data connection line 70 may include a first connection line 71 extending along a first direction X and a second connection line 72 extending along a second direction Y. The first connection line 71 and the second connection line 72 may be disposed on different conductive layers, and the first connection line 71 and the data signal line 60 may be disposed on different conductive layers. A first end of the first connection line 71 is connected to the data signal line 60 through a first connection hole K1, a second end of the first connection line 71 extends along the first direction X or the opposite direction to the first direction X, and then is connected to a first end of the second connection line 72 through a second connection hole K2, and a second end of the second connection line 72 extends along the second direction Y toward the lead area and then is connected to the lead line 80. The second connection line 72 may be disposed between the data signal lines 60 adjacent to each other in the first direction X.

[0127] In an exemplary embodiment, the power supply wiring 90 may include a plurality of first power supply wirings 91 extending along a first direction X and a plurality of second power supply wirings 92 extending along a second direction Y, where the plurality of first power supply wirings 91 may be arranged sequentially along the second direction Y and the plurality of second power supply wirings 92 may be arranged sequentially along the first direction X.

[0128] In an exemplary embodiment, the first power wiring 91 and the second power wiring 92 may be installed on different conductive layers, the second power wiring 92 may be installed between adjacent data signal lines 60, and at least one second power wiring 92 may be connected to at least one first power wiring 91 through a third connection hole K3, so that the multiple first power wirings 91 and the multiple second power wirings 92 form a power wiring 90 with a net-like connected structure.

[0129] In an exemplary embodiment, two data signal lines 60 and one second power supply wiring 92 may be provided between two second connection lines 72 adjacent to each other in the first direction X.

[0130] In an exemplary embodiment, the first power supply wiring 91 and the first connecting line 71 may be provided in the same layer and formed synchronously by the same patterning process, and the second power supply wiring 92 and the second connecting line 72 may be provided in the same layer and formed synchronously by the same patterning process.

[0131] In an exemplary embodiment, at least one circuit row may be provided with only one first power supply wiring 91, and the first connection line 71 may not be provided in the circuit row.

[0132] In an exemplary embodiment, at least one first power supply wiring 91 and at least one first connecting line 71 may be installed in at least one circuit row, and a first break opening DF1 is installed between the first power supply wiring 91 and the first connecting line 71, and the first break opening DF1 is configured to achieve insulation between the first power supply wiring 91 and the first connecting line 71.

[0133] In an exemplary embodiment, at least one circuit row may be provided with only one second power supply wiring 92, and the circuit row may not be provided with a second connection line 72.

[0134] In an exemplary embodiment, at least one second power supply wiring 92 and at least one second connecting line 72 may be installed in at least one circuit row, and a second break opening DF2 is installed between the second power supply wiring 92 and the second connecting line 72, and the second break opening DF2 is configured to achieve insulation between the second power supply wiring 92 and the second connecting line 72.

[0135] In an exemplary embodiment, the first connection holes K1 may be installed in circuit units of adjacent unit rows, and one second power supply wiring 92 may be installed between two first connection holes K1 adjacent to each other in the first direction X.

[0136] In an exemplary embodiment, the power supply line 90 may be a continuously provided low level signal, for example, the power supply line 90 may be the second power supply line VSS.

[0137] Fig. 9A is a schematic planar structure diagram of a further display substrate according to an exemplary embodiment of the present disclosure, and Fig. 9B is an enlarged view of region C2 of Fig. 9A. The driving structure layer of the display region 100 may include a plurality of circuit units constituting a circuit unit array, a plurality of data signal lines 60, a plurality of data connection lines 70, and a power supply wiring 90 having a net-like communication structure, and the layout and structure of the plurality of circuit units, the plurality of data signal lines 60, and the plurality of data connection lines 70 are substantially the same as those shown in Fig. 7A.

[0138] As shown in Figures 9A and 9B, the main structure of the display substrate according to this embodiment is substantially the same as the main structure of the display substrate shown in Figures 8A and 8B, except that one data signal line 60 and two second power supply wires 92 may be installed between two first connection holes K1 adjacent to each other in the first direction X in this embodiment.

[0139] 10 is a schematic diagram of a plane structure of a power wiring according to an exemplary embodiment of the present disclosure. As shown in FIG. 10, a display substrate may include a display area 100, a binding area 200 located on one side of the display area 100 in the second direction Y, and a frame area 300 located on the other side of the display area 100, in which a grid-shaped power wiring 90 may be installed in the display area 100, a binding power lead 410 may be installed in the binding area 200, and a frame power lead 510 may be installed in the frame area 300, and the power wiring 90 may be connected to the binding power lead 410 and the frame power lead 510, respectively.

[0140] In an exemplary embodiment, the binding power lead 410 of the binding region 200 and the frame power lead 510 of the frame region 300 may be an integral structure that is connected to one another.

[0141] In an exemplary embodiment, the power supply wiring 90 of the display area 100 may include a plurality of first power supply wirings 91 extending along a first direction X and a plurality of second power supply wirings 92 extending along a second direction Y, where the plurality of first power supply wirings 91 are sequentially arranged along the second direction Y, and one or both ends in the first direction X may be connected to a frame power supply lead 510, and the plurality of second power supply wirings 92 are sequentially arranged along the first direction X, and the ends of the second power supply wirings 92 away from the binding region may be connected to the frame power supply lead 510.

[0142] In an exemplary embodiment, one end of at least one second power supply wire 92 in the second direction Y may be connected to a binding power supply lead 410 .

[0143] In an exemplary embodiment, the first power wiring 91 and the second power wiring 92 may be disposed on different conductive layers, and at least one second power wiring 92 may be connected to at least one first power wiring 91 through a third connection hole, so that the first power wirings 91 and the second power wirings 92 have the same potential. In the present disclosure, by disposing the power wiring within the display area, a structure in which a low-voltage line is disposed in a sub-pixel (VSS in pixel) is realized, and the width of the frame power lead line can be greatly reduced, which is advantageous for narrowing the frame. In the present disclosure, by disposing the power wiring in a net-like interconnection structure, the resistance of the power wiring can be effectively reduced, the voltage drop of the low-voltage power signal can be effectively reduced, and low power consumption can be realized, as well as effectively improving the uniformity of the power signal in the display substrate, effectively improving the display uniformity, and improving the display quality and display effect.

[0144] 11 is a structural schematic diagram of a data connection line according to an exemplary embodiment of the present disclosure. As shown in FIG. 11, the data connection line is provided in a part of the display area, and the data connection line includes a first connection line extending along a first direction X and a second connection line extending along a second direction Y. Therefore, the display area can be divided into a first area 110, a second area 120, and a third area 130 based on the presence or absence of the data connection line and the extending direction of the data connection line. The first area 110 may be an area where the first connection line 71 is provided (may be called a connection line horizontal wiring area), the second area 120 may be an area where the second connection line 72 is provided (may be called a connection line vertical wiring area), and the third area 130 may be an area where the first connection line 71 and the second connection line 72 are not provided (may be called a normal area).

[0145] In an exemplary embodiment, the first region 110 may include a plurality of circuit units, where the orthogonal projection of the first connecting line 71 on the display substrate plane and the orthogonal projection of the pixel driving circuits in the plurality of circuit units of the first region 110 on the display substrate plane at least partially overlap, and the orthogonal projection of the pixel driving circuits in the plurality of circuit units of the first region 110 on the display substrate plane and the orthogonal projection of the second connecting line 72 on the display substrate plane do not overlap.

[0146] In an exemplary embodiment, the second region 120 may include a plurality of circuit units, and the orthogonal projection of the second connecting line 72 on the display substrate plane and the orthogonal projection of the pixel driving circuits in the plurality of circuit units of the second region 120 on the display substrate plane at least partially overlap, and the orthogonal projection of the pixel driving circuits in the plurality of circuit units of the second region 120 on the display substrate plane and the orthogonal projection of the first connecting line 71 on the display substrate plane do not overlap.

[0147] In an exemplary embodiment, the third region 130 may include a plurality of circuit units, and the orthogonal projections of the pixel driving circuits in the plurality of circuit units of the third region 130 on the display substrate plane do not overlap with the orthogonal projections of the first connecting line 71 and the second connecting line 72 on the display substrate plane.

[0148] In an exemplary embodiment, the division of each region shown in Fig. 11 is merely an example. The first region 110, the second region 120, and the third region 130 are divided based on the presence or absence of a data connecting line and the extending direction of the data connecting line, so the shapes of the three regions may be regular polygons or irregular polygons, and the display region may be divided into one or more first regions 110, one or more second regions 120, and one or more third regions 130, but the present disclosure is not limited thereto.

[0149] In an exemplary embodiment of the present disclosure, a display substrate is provided, comprising: a plurality of circuit units; a plurality of data signal lines; and a plurality of data connecting lines, the data connecting lines including a first connecting line extending along a first direction and a second connecting line extending along a second direction, the data signal lines extending along the second direction, the first direction and the second direction intersect, at least one circuit unit includes a data connecting electrode, at least one circuit unit includes a fan-out connecting electrode, the second connecting line is connected to the first connecting line via the fan-out connecting electrode, the first connecting line is connected to the data signal line via the data connecting electrode, an orthogonal projection of the data connecting electrode on a display substrate plane and an orthogonal projection of the data signal line on a display substrate plane at least partially overlap, an orthogonal projection of the fan-out connecting electrode on a display substrate plane and an orthogonal projection of the second connecting line on a display substrate plane at least partially overlap, and at least one of the data signal lines is provided between the data connecting electrode and the fan-out connecting electrode connected to the same first connecting line.

[0150] In an exemplary embodiment, the data connection electrode and the fan-out connection electrode connected to the same first connection line are provided on both sides of the first connection line, respectively.

[0151] In an exemplary embodiment, at least one circuit unit includes a virtual electrode, the position and shape of which in one circuit unit is the same as the position and shape of the fan-out connection electrode in the other circuit unit.

[0152] In an exemplary embodiment, the orthogonal projection of the virtual electrode in the display substrate plane and the orthogonal projection of the second connecting line in the display substrate plane at least partially overlap.

[0153] In an exemplary embodiment, the display substrate further includes a plurality of first power supply wirings extending along the first direction and a plurality of second power supply wirings extending along the second direction, at least one circuit unit includes a power supply connection electrode, the second power supply wirings are connected to the first power supply wirings via the power supply connection electrode, and an orthogonal projection of the power supply connection electrode on the display substrate plane and an orthogonal projection of the second power supply wirings on the display substrate plane at least partially overlap.

[0154] In an exemplary embodiment, at least one circuit unit includes a virtual electrode, the position and shape of the virtual electrode in one circuit unit being the same as the position and shape of the power connection electrode in the other circuit unit.

[0155] In an exemplary embodiment, an orthogonal projection of the virtual electrode onto the display substrate plane and an orthogonal projection of the second power supply wiring onto the display substrate plane at least partially overlap.

[0156] In an exemplary embodiment, the first power supply wiring and the first connecting line are arranged on the same layer, at least one first power supply wiring and at least one first connecting line are provided in at least one circuit row, at least one first break opening is provided between the first connecting line and the first power supply wiring, and an orthogonal projection of the first break opening on the display substrate plane and an orthogonal projection of the second power supply wiring on the display substrate plane at least partially overlap, or an orthogonal projection of the first break opening on the display substrate plane and an orthogonal projection of the second connecting line on the display substrate plane at least partially overlap.

[0157] In an exemplary embodiment, a first width of the first break opening is less than or equal to a second width of the second power supply wiring or the second connecting line, the first width and the second width are sizes in the first direction, and an orthogonal projection of the first break opening on the display substrate plane is within the range of an orthogonal projection of the second power supply wiring or the second connecting line on the display substrate plane.

[0158] In an exemplary embodiment, the second power supply wiring and the second connecting line are installed on the same layer, at least one second power supply wiring and at least one second connecting line are provided in at least one circuit column, a second break opening is provided between the second connecting line and the second power supply wiring, and an orthogonal projection of the second break opening on the display substrate plane at least partially overlaps with an orthogonal projection of the first connecting line or the first power supply wiring on the display substrate plane.

[0159] In an exemplary embodiment, a third width of the second break opening is equal to a fourth width of the first connecting line or the first power wiring, the third width and the fourth width are sizes in the second direction, and a boundary of an orthogonal projection of the second break opening on the display substrate plane and a boundary of an orthogonal projection of the first connecting line or the first power wiring on the display substrate plane are aligned.

[0160] In an exemplary embodiment, at least one circuit unit includes at least a pixel driving circuit, the pixel driving circuit including at least a storage capacitor and a plurality of transistors, and in a plane perpendicular to a display substrate, the circuit unit includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially disposed on a base, the semiconductor layer including at least active layers of a plurality of transistors, the first conductive layer including at least gate electrodes of a plurality of transistors and a first plate of a storage capacitor, the second conductive layer including at least a second plate of a storage capacitor, the third conductive layer including at least the first connecting line, and the fourth conductive layer including at least the data signal line and the second connecting line.

[0161] In an exemplary embodiment, the third conductive layer further includes a data connection electrode and a fan-out connection electrode respectively connected to the first connection line, the data signal line is connected to the data connection electrode through a first connection hole, and the second connection line is connected to the fan-out connection electrode through a second connection hole.

[0162] In an exemplary embodiment, the third conductive layer further includes a first power supply wiring extending along the first direction and a power supply connection electrode connected to the first power supply wiring, and the fourth conductive layer further includes a second power supply wiring extending along the second direction, and the second power supply wiring is connected to the power supply connection electrode via a third connection hole.

[0163] In an exemplary embodiment, the third conductive layer further includes a virtual electrode, and in at least one circuit unit, the second connection line is connected to the virtual electrode through a connection hole, and in at least one circuit unit, the second power supply wiring is connected to the virtual electrode through a connection hole.

[0164] In an exemplary embodiment, the driving structure layer may further include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, and a first planar layer, where the first insulating layer is disposed between the base and the semiconductor layer, the second insulating layer is disposed between the semiconductor layer and the first conductive layer, the third insulating layer is disposed between the first conductive layer and the second conductive layer, the fourth insulating layer is disposed between the second conductive layer and the third conductive layer, and the first planar layer is disposed between the third conductive layer and the fourth conductive layer.

[0165] FIG. 12 is a structural schematic diagram of a circuit unit according to an exemplary embodiment of the present disclosure, which is an enlarged view of the D region of FIG. 11, showing the structure of a circuit unit with four circuit rows and twelve circuit columns. FIG. 13 is a structural schematic diagram of the third conductive layer in FIG. 12. FIG. 14 is a structural schematic diagram of the fourth conductive layer in FIG. 12. As shown in FIG. 12, FIG. 13 and FIG. 14, in a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, a plurality of data signal lines 60, a plurality of first connecting lines 71, a plurality of second connecting lines 72, a plurality of first power wirings 91 and a plurality of second power wirings 92. The circuit unit may include at least a pixel driving circuit. The shape of the data signal line 60 may be a straight line extending along the second direction Y, and the data signal line 60 may be connected to the pixel driving circuits of the plurality of circuit units in the unit column in which it is located. The first connection line 71 and the first power supply wiring 91 may have a straight shape extending along the first direction X, and the second connection line 72 and the second power supply wiring 92 may have a straight shape extending along the second direction Y.

[0166] In an exemplary embodiment, in a plane parallel to the display substrate, the driving structure layer may include a first region 110, a second region 120, and a third region 130. The first region 110 may be a region where the first connecting line 71 is provided, the second region 120 may be a region where the second connecting line 72 is provided, and the third region 130 may be a region where the first connecting line 71 and the second connecting line 72 are not provided. The first region 110, the second region 120, and the third region 130 are all provided with the data signal line 60, the first power supply line 91, and the second power supply line 92.

[0167] In an exemplary embodiment, at least one circuit unit in the first region 110 may include a data connection electrode 81 and a data connection block 82, and there is a first distance L1 between the first connection line 71 and the data connection electrode 81, and the first distance L1 may be greater than 0. In an exemplary embodiment, the first distance L1 may be a distance between an edge of the first connection line 71 close to the data connection electrode 81 and an edge of the data connection electrode 81 close to the first connection line 71, and the first distance L1 is a size in the second direction Y. The data connection block 82 may be provided between the first connection line 71 and the data connection electrode 81, and may be connected to the first connection line 71 and the data connection electrode 81 respectively. The data signal line 60 may be connected to the data connection electrode 81 through a first connection hole K1, and the connection between the data signal line 60 and the first connection line 71 is realized. For example, a data connection electrode 81 and a data connection block 82 are provided in the circuit unit in the (M-2)th row and the (N-3)th column, and the data connection electrode 81 is connected to the first connection line 71 in the (M-1)th row via the data connection block 82.

[0168] In an exemplary embodiment, the orthogonal projections of the data connection electrodes 81 and the data signal lines 60 on the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the data connection electrodes 81 on the display substrate plane may be within the range of the orthogonal projection of the data signal lines 60 on the display substrate plane. In an exemplary embodiment, the orthogonal projections of the data connection blocks 82 and the data signal lines 60 on the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the data connection block 82 on the display substrate plane may be within the range of the orthogonal projection of the data signal lines 60 on the display substrate plane.

[0169] In an exemplary embodiment, at least one circuit unit in the first region 110 may include a fan-out connection electrode 83 and a fan-out connection block 84, and there is a second distance L2 between the first connection line 71 and the fan-out connection electrode 83, and the second distance L2 may be greater than 0. In an exemplary embodiment, the second distance L2 may be a distance between an edge of the first connection line 71 close to the fan-out connection electrode 83 and an edge of the fan-out connection electrode 83 close to the first connection line 71, and the second distance L2 is a size in the second direction Y. The fan-out connection block 84 may be provided between the first connection line 71 and the fan-out connection electrode 83, and may be connected to the first connection line 71 and the fan-out connection electrode 83, respectively. The second connection line 72 may be connected to the fan-out connection electrode 83 through a second connection hole K2, and the connection between the second connection line 72 and the first connection line 71 is realized. For example, a fan-out connection block 84 and a fan-out connection electrode 83 are provided in the circuit unit in the (M-1)th row and the (N+3)th column, and the fan-out connection electrode 83 is connected to the first connection line 71 in the (M-1)th row via the fan-out connection block 84. The fan-out connection electrode 83 is connected to the second connection line 72 via the second connection hole K2, and the data connection electrode 81 is connected to the data signal line 60 via the first connection hole K1, so that the data signal line 60 is connected to the second connection line 72 via the first connection line 71.

[0170] In an exemplary embodiment, the orthogonal projections of the fan-out connection electrodes 83 in the display substrate plane and the orthogonal projections of the second connection lines 72 in the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the fan-out connection electrodes 83 in the display substrate plane may be within the range of the orthogonal projection of the second connection lines 72 in the display substrate plane. In an exemplary embodiment, the orthogonal projections of the fan-out connection block 84 in the display substrate plane and the orthogonal projections of the second connection lines 72 in the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the fan-out connection block 84 in the display substrate plane may be within the range of the orthogonal projection of the second connection lines 72 in the display substrate plane.

[0171] In an exemplary embodiment, for a data connection electrode 81 and a fan-out connection electrode 83 connected to the same first connection line 71, at least one data signal line 60 may be installed between the data connection electrode 81 and the fan-out connection electrode 83, the data connection electrode 81 may be installed on the side opposite to the second direction Y of the first connection line 71, and the fan-out connection electrode 83 may be installed on the side of the first connection line 71 in the second direction Y, that is, the data connection electrode 81 and the fan-out connection electrode 83 are respectively installed on both sides of the first connection line 71 in the second direction Y, and correspondingly, the first connection hole K1 and the second connection hole K2 connected to the same first connection line 71 are respectively installed on both sides of the first connection line 71 in the second direction Y.

[0172] In an exemplary embodiment, at least one circuit unit in the third region 130 may include a power supply connection electrode 85 and a power supply connection block 86, and the power supply connection block 86 may be disposed between the first power supply wiring 91 and the power supply connection electrode 85 and connected to the first power supply wiring 91 and the power supply connection electrode 85, respectively. The second power supply wiring 92 may be connected to the power supply connection electrode 85 via a third connection hole K3, thereby realizing a connection between the first power supply wiring 91 and the second power supply wiring 92, and the multiple first power supply wirings 91 and the multiple second power supply wirings 92 form a power supply wiring with a net-like structure.

[0173] In an exemplary embodiment, the orthogonal projection of the power supply connecting electrode 85 on the display substrate plane and the orthogonal projection of the second power supply wiring 92 on the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the power supply connecting electrode 85 onto the display substrate plane may be within the range of the orthogonal projection of the second power supply wiring 92 onto the display substrate plane. In an exemplary embodiment, the orthogonal projection of the power connection block 86 on the display substrate plane and the orthogonal projection of the second power wiring 92 on the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the power connection block 86 on the display substrate plane may be within the range of the orthogonal projection of the second power wiring 92 on the display substrate plane.

[0174] In an exemplary embodiment, the power supply connection electrode 85 and the power supply connection block 86 may be disposed on the second direction Y side of the first power supply wiring 91 .

[0175] In an exemplary embodiment, at least one circuit unit in the first region 110 or the third region 130 may include a first break opening DF1, which may be installed between the first connecting line 71 and the first power wiring 91 in one unit row, thereby achieving insulation between the first connecting line 71 and the first power wiring 91.

[0176] In an exemplary embodiment, an orthogonal projection of the first break opening DF1 on the display substrate plane and an orthogonal projection of the second power supply wiring 92 or the second connecting line 72 on the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the first break opening DF1 on the display substrate plane may be within the range of the orthogonal projection of the second power supply wiring 92 or the second connecting line 72 on the display substrate plane.

[0177] In an exemplary embodiment, at least one circuit unit in the first region 110 or the third region 130 may include a second break opening DF2, which may be installed between the second connecting line 72 and the second power supply wiring 92 in one unit row, thereby achieving insulation between the second connecting line 72 and the second power supply wiring 92.

[0178] In an exemplary embodiment, an orthogonal projection of the second break opening DF2 on the display substrate plane and an orthogonal projection of the first connection line 71 or the first power supply wiring 91 on the display substrate plane at least partially overlap. In the exemplary embodiment, the boundary between the orthogonal projection of the second break opening DF2 on the display substrate plane and the orthogonal projection of the first connection line 71 or the first power supply wiring 91 on the display substrate plane is aligned.

[0179] In an exemplary embodiment, at least one circuit unit in the first region 110 may include a virtual electrode 87, and the second power supply wiring 92 may be connected to the virtual electrode 87 through a connection hole.

[0180] In an exemplary embodiment, the orthogonal projection of the virtual electrode 87 onto the display substrate plane and the orthogonal projection of the second power supply wiring 92 onto the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the virtual electrode 87 on the display substrate plane may be within the range of the orthogonal projection of the second power wiring 92 on the display substrate plane.

[0181] In an exemplary embodiment, at least one circuit unit in the second region 120 may include a virtual electrode 87, and the second connecting line 72 may be connected to the virtual electrode 87 through a connecting hole.

[0182] In an exemplary embodiment, the orthogonal projections of the virtual electrodes 87 in the display substrate plane and the second connecting lines 72 in the display substrate plane at least partially overlap. In an exemplary embodiment, the orthogonal projection of the virtual electrode 87 in the display substrate plane may be within the range of the orthogonal projection of the second connecting line 72 in the display substrate plane.

[0183] In an exemplary embodiment, the data connection electrode 81, the data connection block 82, the power connection electrode 85, the power connection block 86, the fan-out connection electrode 83, the fan-out connection block 84, the virtual electrode 87, the first connection line 71 and the first power wiring 91 may be arranged on a third conductive layer, and the data signal line 60, the second connection line 72 and the second power wiring 92 may be arranged on a fourth conductive layer.

[0184] In an exemplary embodiment, the position and shape of the virtual electrode 87 in the circuit unit may be substantially the same as the position and shape of the fan-out connection electrode 83 in the circuit unit. The position and shape of the virtual electrode 87 in the circuit unit may be substantially the same as the position and shape of the power connection electrode 85 in the circuit unit. Thus, the fan-out connection electrode 83, the power connection electrode 85 and the virtual electrode 87 have the same form and via connection structure. The same design of the relay connection region not only improves the uniformity of the subsequent etching process, but also allows different regions to achieve the same display effect in both transmitted light and reflected light, effectively avoids shading removal, effectively avoids poor appearance of the display substrate, and improves the display quality and display effect.

[0185] The manufacturing process of the display substrate will be described below by way of example. The "patterning process" described in this disclosure includes all or part of the processing processes such as coating of photoresist, mask exposure, development, etching, and stripping of photoresist. The term "thin film" refers to a layer of thin film fabricated by deposition, coating, or other processes on a base using a certain material. If the "thin film" does not require a patterning process in the entire manufacturing process, the "thin film" can also be called a "layer". If the "thin film" requires a patterning process in the entire manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The term "A and B are disposed in the same layer" described in this disclosure refers to A and B being formed simultaneously by the same patterning process. The "thickness" of the film layer is the size of the film layer in the direction perpendicular to the display substrate. In an exemplary embodiment of the present disclosure, "the orthogonal projection of B is located within the range of the orthogonal projection of A" or "the orthogonal projection of A contains the orthogonal projection of B" refers to the boundary of the orthogonal projection of B being within the boundary range of the orthogonal projection of A or the boundary of the orthogonal projection of A overlapping the boundary of the orthogonal projection of B.

[0186] In an exemplary embodiment, the manufacturing process of the display substrate may include the following operations.

[0187] (1) Forming a semiconductor layer pattern. In an exemplary embodiment, as shown in Figures 15 and 16, forming a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base, and patterning the semiconductor thin film through a patterning process to form a first insulating layer covering the base and a semiconductor layer disposed on the first insulating layer, where Figure 15 is an enlarged view of the E0 region in Figure 11, and Figure 16 is an enlarged view of the F region in Figure 11.

[0188] In an exemplary embodiment, the semiconductor layer of each circuit unit in the display area may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7, and the first active layer 11 to the third active layer 13 and the fifth active layer 15 to the seventh active layer 17 may be an integrated structure connected to each other, and the fourth active layer 14 may be disposed separately.

[0189] In an exemplary embodiment, the first active layer 11 and the second active layer 12 may be located on opposite sides of the third active layer 13 of the circuit unit in the second direction Y, and the fourth active layer 14, the fifth active layer 15, the sixth active layer 16 and the seventh active layer 17 may be located on the side of the third active layer 13 of the circuit unit in the second direction Y.

[0190] In an exemplary embodiment, the first active layer 11 may be shaped as an "n", the second active layer 12 and the fifth active layer 15 may be shaped as an "L", the third active layer 13 may be shaped as an "Ω", and the fourth active layer 14, the sixth active layer 16 and the seventh active layer 17 may be shaped as an "I".

[0191] In an exemplary embodiment, the active layer of each transistor may include a first area, a second area, and a channel area located between the first area and the second area. In an exemplary embodiment, the first area 11-1 of the first active layer 11, the first area 14-1 of the fourth active layer 14, the second area 14-2 of the fourth active layer 14, the first area 15-1 of the fifth active layer 15, and the first area 17-1 of the seventh active layer 17 may be disposed separately. The second area 11-2 of the first active layer 11 can be the first area 12-1 of the second active layer 12, the first area 13-1 of the third active layer 13 can be simultaneously the second area 14-2 of the fourth active layer 14 and the second area 15-2 of the fifth active layer 15, the second area 13-2 of the third active layer 13 can be simultaneously the second area 12-2 of the second active layer 12 and the first area 16-1 of the sixth active layer 16, and the second area 16-2 of the sixth active layer 16 can be the second area 17-2 of the seventh active layer 17.

[0192] In an exemplary embodiment, the fourth active layer 14 may be disposed separately on a side of the fifth active layer 15 in the first direction X, the first area 14-1 of the fourth active layer 14 may be disposed on a side of the channel area of ​​the fourth active layer 14 away from the third active layer 13, and the second area 14-2 of the fourth active layer 14 may be disposed on a side of the channel area of ​​the fourth active layer 14 closer to the third active layer 13. In an exemplary embodiment, the first area 14-1 of the fourth active layer 14 is configured to be connected to a data signal line via a fourth connection electrode to be formed subsequently, and the second area 14-2 of the fourth active layer 14 is configured to be connected to the first area 13-1 of the third active layer 13 via a third connection electrode to be formed subsequently.

[0193] In an exemplary embodiment, the second area 14-2 of the fourth active layer 14 may be located on the side of the first area 15-1 of the fifth active layer 15 in the first direction X, i.e., the first area 15-1 of the fifth active layer 15 may be located between the second area 14-2 of the fourth active layer 14 and the second area 16-2 of the sixth active layer 16 (which is also the second area 17-2 of the seventh active layer 17).

[0194] In an exemplary embodiment, the first area of ​​the third active layer can be a first pole of the third transistor (driving transistor), the second area of ​​the fourth active layer can be a second pole of the fourth transistor (data writing transistor), and the second area of ​​the fifth active layer can be a second pole of the fifth transistor, and the connection point where the first area of ​​the third active layer, the second area of ​​the fourth active layer and the second area of ​​the fifth active layer are connected to each other is a first node N1 of the pixel driving circuit.

[0195] In an exemplary embodiment, the semiconductor patterns in the E1, E2, E3 and E4 regions of FIG. 11 are substantially the same as the semiconductor pattern in the E0 region, with no semiconductor pattern being provided in the lead area of ​​the binding region.

[0196] (2) Form a first conductive layer pattern. In an exemplary embodiment, as shown in Figures 17 and 18, forming the first conductive layer pattern may include sequentially depositing a second insulating thin film and a first conductive thin film on the base on which the pattern is formed, and patterning the first conductive thin film by a patterning process to form a second insulating layer covering the semiconductor layer pattern and a first conductive layer pattern disposed on the second insulating layer, where Figure 17 is an enlarged view of the E0 region in Figure 11, and Figure 18 is an enlarged view of the F region in Figure 11. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer.

[0197] In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display area includes at least a first scanning signal line 21, a second scanning signal line 22, a third scanning signal line 23, a light emission control line 24, and a first plate 25 of a storage capacitor.

[0198] In an exemplary embodiment, the shape of the first plate 25 of the storage capacitor may be rectangular, with chamfers at the corners of the rectangle. There is an overlapping area between the orthogonal projection of the first plate 25 at the base and the orthogonal projection at the base of the third active layer of the third transistor T3. In an exemplary embodiment, the first plate 25 may simultaneously be one plate of the storage capacitor and the gate electrode of the third transistor T3.

[0199] In an exemplary embodiment, the first scanning signal line 21, the second scanning signal line 22, the third scanning signal line 23 and the light emission control line 24 may have a linear shape with a main portion extending along the first direction X. The first scanning signal line 21 and the second scanning signal line 22 may be located on opposite sides of the first electrode plate 25 of the circuit unit in the second direction Y, the second scanning signal line 22 may be located on the side of the first scanning signal line 21 of the circuit unit that is away from the first electrode plate 25, the third scanning signal line 23 and the light emission control line 24 may be located on the side of the first electrode plate 25 of the circuit unit in the second direction Y, and the third scanning signal line 23 may be located on the side of the light emission control line 24 of the circuit unit that is away from the first electrode plate 25.

[0200] In an exemplary embodiment, the first scanning signal line 21 may be provided with a gate block 21-1 protruding toward the second scanning signal line 22, and the area where the first scanning signal line 21 and the gate block 21-1 overlap with the second active layer can serve as the gate electrode of the second transistor T2 to form a second transistor T2 with a double gate structure.

[0201] In an exemplary embodiment, the overlapping area between the second scanning signal line 22 and the first active layer can be the gate electrode of the first transistor T1 of the double-gate structure. The overlapping area between the third scanning signal line 23 and the fourth active layer can be the gate electrode of the fourth transistor T4, and the overlapping area between the third scanning signal line 23 and the seventh active layer can be the gate electrode of the seventh transistor T7. The overlapping area between the emission control line 24 and the fifth active layer can be the gate electrode of the fifth transistor T5, and the overlapping area between the emission control line 24 and the sixth active layer can be the gate electrode of the sixth transistor T6.

[0202] In the exemplary embodiment, the first scanning signal line 21 is located on the opposite side of the second direction Y of the third transistor T3 of the circuit unit, and the third scanning signal line 23 is located on the side of the second direction Y of the third transistor T3 of the circuit unit, so that the second transistor T2 and the fourth transistor T4 are respectively located on both sides of the third transistor T3 in the second direction Y.

[0203] In an exemplary embodiment, the first scanning signal line 21 and the third scanning signal line 23 may be connected to the same signal source, that is, the output signals of the first scanning signal line 21 and the third scanning signal line 23 are the same.

[0204] In an exemplary embodiment, the first conductive layer pattern in regions E1, E2, E3, and E4 of FIG. 11 is substantially identical to the first conductive layer pattern in region E0.

[0205] In an exemplary embodiment, the first conductive layer pattern of the lead area in the binding region may include at least a plurality of first lead electrodes 210 .

[0206] In an exemplary embodiment, the first lead electrode 210 may have an elongated shape extending along the second direction Y, and the first lead electrode 210 is configured to be connected to the data signal lines of the odd-numbered unit rows to be formed subsequently.

[0207] The lead area shown in Fig. 18 is the first conductive layer pattern of the third region in the display region, and therefore has only the first lead electrodes connected to the data signal lines of the odd-numbered unit columns. As for the second region in the display region, since a second connection line is subsequently formed, the first conductive layer pattern of the second region may further include a fifth lead electrode, and the fifth lead electrode is set to be connected to the subsequently formed second connection line via a sixth lead electrode. Therefore, the second region includes not only a plurality of first lead electrodes, but also a plurality of fifth lead electrodes, and the number of lead electrodes in the second region is different from the number of lead electrodes in the third region.

[0208] In an exemplary embodiment, the fifth lead electrode and the first lead electrode may have substantially the same structure.

[0209] In an exemplary embodiment, the first conductive layer pattern in the binding area may further include a plurality of first lead-out lines (not shown), which may be straight or bent in shape, with first ends of the plurality of first lead-out lines connected to the first lead electrode 210 and the fifth lead electrode, and second ends of the plurality of first lead-out lines extending along a direction away from the display area to a folding area of ​​the binding area.

[0210] In an exemplary embodiment, after forming the first conductive layer pattern, the first conductive layer is used as a mask to convert the semiconductor layer into a conductor. The channel regions of the first transistor T1 to the seventh transistor T7 are formed in the semiconductor layer in the area blocked by the first conductive layer. The semiconductor layer in the area not blocked by the first conductive layer is converted into a conductor, that is, the first area and the second area of ​​the first active layer to the seventh active layer are all converted into a conductor.

[0211] (3) Form a second conductive layer pattern. In an exemplary embodiment, as shown in Figures 19 and 20, forming the second conductive layer pattern may include sequentially depositing a third insulating thin film and a second conductive thin film on the base on which the pattern is formed, and patterning the second conductive thin film by a patterning process to form a third insulating layer covering the first conductive layer, and a second conductive layer pattern disposed on the third insulating layer, where Figure 19 is an enlarged view of the E0 area in Figure 11, and Figure 20 is an enlarged view of the F area in Figure 11. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer.

[0212] In an exemplary embodiment, the second conductive layer pattern of each circuit unit in the display area includes at least a first initial signal line 31 , a second initial signal line 32 , a second plate of the storage capacitor 33 , a plate connection line 34 and a shield electrode 35 .

[0213] In an exemplary embodiment, the first initial signal line 31 and the second initial signal line 32 may have a linear shape whose main body portion can extend along the first direction X. The first initial signal line 31 may be located between the first scanning signal line 21 and the second scanning signal line 22 of the circuit unit, and the second initial signal line 32 may be located on the side of the third scanning signal line 23 of the circuit unit away from the light emission control line 24.

[0214] In an exemplary embodiment, the contour shape of the second plate 33 may be rectangular, and the corners of the rectangle may be chamfered. There is an overlapping area between the orthogonal projection at the base of the second plate 33 and the orthogonal projection at the base of the first plate 25. The second plate 33 is the other plate of the storage capacitor and is located between the first scanning signal line 21 and the emission control line 24 of the circuit unit. The first plate 25 and the second plate 33 constitute the storage capacitor of the pixel driving circuit.

[0215] In an exemplary embodiment, the plate connection line 34 may be disposed on the side of the second plate 33 in the first direction X or the opposite direction of the first direction X. The first end of the plate connection line 34 is connected to the second plate 33 of the circuit unit, and the second end of the plate connection line 34 extends along the first direction X or the opposite direction of the first direction X and then connected to the second plate 33 of the adjacent circuit unit, so that the second plates of the adjacent circuit units in one unit row are connected to each other. In an exemplary embodiment, the second plates of the multiple circuit units in one unit row can be connected to each other through the plate connection line to form an integrated structure. The second plate of the integrated structure can be multiplexed as a power signal connection line. Thereby, the multiple second plates in one unit row have the same potential, which contributes to improving the uniformity of the panel, avoiding display defects of the display substrate, and ensuring the display effect of the display substrate.

[0216] In an exemplary embodiment, an opening 36 is provided in the second plate 33, and the opening 36 may be located in the middle of the second plate 33, and the opening 36 may be rectangular, so that the second plate 33 forms a ring-shaped structure. The opening 36 exposes the third insulating layer covering the first plate 25, and the orthogonal projection of the first plate 25 at the base includes the orthogonal projection of the opening 36 at the base. In an exemplary embodiment, the opening 36 is configured to accommodate a first via to be formed subsequently. The first via is located in the opening 36 to expose the first plate 25, so that the second pole of the first transistor T1 to be formed subsequently is connected to the first plate 25.

[0217] In an exemplary embodiment, the second electrode plate 33 further includes a protrusion 37, which may be disposed at a corner of the second electrode plate 33 close to the fourth active layer and connected to the second electrode plate 33. The orthogonal projection of the protrusion 37 at the base and the orthogonal projection of the first area of ​​the third active layer, the second area of ​​the fourth active layer, and the second area of ​​the fifth active layer at the base at least partially overlap each other. Since the second electrode plate 33 is connected to a first power line to be formed later, the protrusion 37 is configured to cut off the connection point of the first area of ​​the third active layer, the second area of ​​the fourth active layer, and the second area of ​​the fifth active layer (i.e., the first node N1 of the pixel driving circuit), thereby preventing the potential of the first node N1 from being influenced from the outside and improving the display effect.

[0218] In an exemplary embodiment, the convex portion 37 may include a first convex portion connected to an edge portion of the second plate 33 on the side of the first direction X, and a second convex portion connected to an edge portion of the second plate 33 on the side of the second direction Y, and the first convex portion and the second convex portion are connected to each other at one end that is adjacent to each other.

[0219] In an exemplary embodiment, the shield electrode 35 may be located on a side of the first initial signal line 31 close to the first scanning signal line 21, and connected to the first initial signal line 31. The orthogonal projection at the base of the shield electrode 35 and the orthogonal projection at the base of the second active layer between the two gate electrodes of the second transistor T2 at least partially overlap. The shield electrode 35 is configured to block the influence of the data voltage jump on the key node, so as to prevent the data voltage jump from affecting the potential of the key node of the pixel driving circuit, and improve the display effect.

[0220] In an exemplary embodiment, the second conductive layer pattern in regions E1, E2, E3, and E4 of FIG. 11 is substantially identical to the second conductive layer pattern in region E0.

[0221] In an exemplary embodiment, the second conductive layer pattern of the lead area in the binding region may include at least a plurality of second lead electrodes 220 .

[0222] In an exemplary embodiment, the second lead electrode 220 may have an elongated shape extending along the second direction Y, and the second lead electrode 220 is configured to be connected to the data signal lines of the even-numbered unit rows formed subsequently.

[0223] The lead area shown in Fig. 20 is the second conductive layer pattern of the third region in the display region, and therefore has only the second lead electrodes connected to the data signal lines of the even-numbered unit columns. Since the second connection line is subsequently formed for the second region in the display region, the second conductive layer pattern of the second region may further include a fifth lead electrode, and the fifth lead electrode is set to be connected to the subsequently formed second connection line via a sixth lead electrode. Therefore, the second region includes not only a plurality of second lead electrodes, but also a plurality of fifth lead electrodes, and the number of lead electrodes in the second region is different from the number of lead electrodes in the third region.

[0224] In an exemplary embodiment, the fifth lead electrode connected to the subsequently formed second connecting line may be disposed on the first conductive layer, or may be disposed on the second conductive layer, or may be disposed on the first conductive layer and the second conductive layer according to odd-numbered unit columns and even-numbered unit columns, respectively, but the present disclosure is not limited thereto.

[0225] In an exemplary embodiment, the fifth lead electrode and the second lead electrode may have substantially the same structure.

[0226] In an exemplary embodiment, the second conductive layer pattern in the binding area may further include a plurality of second lead lines (not shown), which may be linear or bent in shape, with first ends of the plurality of second lead lines connected to the second lead electrode 220 and the fifth lead electrode, and second ends of the plurality of second lead lines extending along a direction away from the display area to the folding area of ​​the binding area.

[0227] In an exemplary embodiment, the second lead electrode 220 may be disposed between adjacent first lead electrodes 210 in the first direction X, the first lead electrode 210 may be disposed between adjacent second lead electrodes 220 in the first direction X, and ends of the plurality of first lead electrodes 210 close to the display area and ends of the plurality of second lead electrodes 220 close to the display area may be aligned.

[0228] (4) Form a fourth insulating layer pattern. In an exemplary embodiment, as shown in Fig. 21 and Fig. 22, the formation of the fourth insulating layer pattern may include depositing a fourth insulating thin film on the base on which the pattern is formed, and patterning the fourth insulating thin film by a patterning process to form a fourth insulating layer covering the second conductive layer, and a plurality of vias are provided in each circuit unit, Fig. 21 is an enlarged view of the E0 area in Fig. 11, and Fig. 22 is an enlarged view of the F area in Fig. 11.

[0229] In an exemplary embodiment, the multiple vias of each circuit unit in the display area include at least a first via V1, a second via V2, a third via V3, a fourth via V4, a fifth via V5, a sixth via V6, a seventh via V7, an eighth via V8, a ninth via V9, a tenth via V10, an eleventh via V11 and a twelfth via V12.

[0230] In the exemplary embodiment, the orthogonal projection at the base of the first via V1 is within the range of the orthogonal projection at the base of the opening 36 in the second plate 33. The fourth insulating layer and the third insulating layer in the first via V1 are etched to expose the surface of the first plate 25. The first via V1 is configured to connect the second pole of a subsequently formed first transistor T1 to the first plate 25 through the via.

[0231] In the exemplary embodiment, the orthogonal projection at the base of the second via V2 is within the range of the orthogonal projection at the base of the second plate 33. The fourth insulating layer in the second via V2 is etched to expose the surface of the second plate 33. The second via V2 is configured to connect a first pole of a subsequently formed fifth transistor T5 to the second plate 33 through the via.

[0232] In an exemplary embodiment, the orthogonal projection of the third via V3 at the base is within the range of the orthogonal projection at the base of the first area of ​​the fifth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the third via V3 are etched to expose the surface of the first area of ​​the fifth active layer. The third via V3 is configured to connect a first pole of a subsequently formed fifth transistor T5 to the first area of ​​the fifth active layer through the via.

[0233] In an exemplary embodiment, the orthogonal projection of the fourth via V4 at the base is within the range of the orthogonal projection at the base of the second area of ​​the sixth active layer (which is also the second area of ​​the seventh active layer). The fourth insulating layer, the third insulating layer and the second insulating layer in the fourth via V4 are etched to expose the surface of the second area of ​​the sixth active layer. The fourth via V4 is configured to connect the second pole of the sixth transistor T6 (which is also the second pole of the seventh transistor T7) to be subsequently formed to the sixth active layer through the via.

[0234] In an exemplary embodiment, the orthogonal projection of the fifth via V5 at the base is within the range of the orthogonal projection at the base of the first area of ​​the fourth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the fifth via V5 are etched to expose the surface of the first area of ​​the fourth active layer. The fifth via V5 is configured to connect a first pole of a subsequently formed fourth transistor T4 to the first area of ​​the fourth active layer through the via.

[0235] In an exemplary embodiment, the orthogonal projection of the sixth via V6 at its base is within the range of the orthogonal projection at the base of the first area of ​​the seventh active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the sixth via V6 are etched to expose the surface of the first area of ​​the seventh active layer. The sixth via V6 is configured to connect a first pole of a subsequently formed seventh transistor T7 to the first area of ​​the seventh active layer through the via.

[0236] In an exemplary embodiment, the orthogonal projection of the seventh via V7 at its base is within the range of the orthogonal projection at the base of the first area of ​​the third active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the seventh via V7 are etched to expose the surface of the first area of ​​the third active layer. The seventh via V7 is configured to connect the first pole of a subsequently formed third transistor T3 to the first area of ​​the third active layer through the via.

[0237] In an exemplary embodiment, the orthogonal projection of the eighth via V8 at the base is within the range of the orthogonal projection at the base of the second area of ​​the fourth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the eighth via V8 are etched to expose the surface of the second area of ​​the fourth active layer. The eighth via V8 is configured to connect the subsequently formed third transistor T3 to the first pole and the second area of ​​the fourth active layer through the via.

[0238] In an exemplary embodiment, the orthogonal projection of the base of the ninth via V9 is within the range of the orthogonal projection of the base of the second area of ​​the first active layer (which is also the first area of ​​the second active layer). The fourth insulating layer, the third insulating layer, and the second insulating layer in the ninth via V9 are etched to expose the surface of the second area of ​​the first active layer. The ninth via V9 is configured to connect the second pole of the first transistor T1 (which is also the first pole of the second transistor T2) to be subsequently formed to the first active layer through the via.

[0239] In an exemplary embodiment, the orthogonal projection of the base of the tenth via V10 is within the range of the orthogonal projection of the base of the first area of ​​the first active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer in the tenth via V10 are etched to expose the surface of the first area of ​​the first active layer. The tenth via V10 is configured to connect a first pole of a subsequently formed first transistor T1 to the first area of ​​the first active layer through the via.

[0240] In an exemplary embodiment, the orthogonal projection of the base of the eleventh via V11 is within the range of the orthogonal projection of the base of the first initial signal line 31. The fourth insulating layer in the eleventh via V11 is etched to expose the surface of the first initial signal line 31. The eleventh via V11 is configured to connect the first pole of the first transistor T1 to be formed subsequently to the first initial signal line 31 through the via. In the present disclosure, by providing the tenth via V10 and the eleventh via V11, the connection between the first initial signal line 31 and the first area of ​​the first active layer can be realized by using the first pole of the first transistor T1 to be formed subsequently. Compared with the manner in which the first initial signal line of the second conductive layer is directly connected to the first area of ​​the first active layer through a via, the present disclosure can reduce one patterning process, thereby reducing the manufacturing time and the manufacturing cost.

[0241] In the exemplary embodiment, the orthogonal projection at the base of the twelfth via V12 is within the range of the orthogonal projection at the base of the second initial signal line 32. The fourth insulating layer in the twelfth via V12 is etched to expose the surface of the second initial signal line 32. The twelfth via V12 is configured to connect a first pole of a subsequently formed seventh transistor T7 to the second initial signal line 32 through the via.

[0242] In the present disclosure, by providing the sixth via V6 and the twelfth via V12, the first pole of the seventh transistor T7 formed subsequently can be used to realize the connection between the second initial signal line 32 and the first area of ​​the seventh active layer. Compared with the method in which the second initial signal line of the second conductive layer is directly connected to the first area of ​​the seventh active layer through a via, the present disclosure can reduce one patterning process, thereby reducing the manufacturing time and the manufacturing cost.

[0243] In an exemplary embodiment, the via patterns in the E1, E2, E3 and E4 regions of FIG. 11 are substantially identical to the via pattern in the E0 region.

[0244] In an exemplary embodiment, the plurality of vias in the lead area in the binding region includes at least a thirteenth via V13 and a fourteenth via V14.

[0245] In an exemplary embodiment, the orthogonal projection at the base of the thirteenth via V13 is within the range of the orthogonal projection at the base of the first lead electrode 210. The fourth insulating layer and the third insulating layer in the thirteenth via V13 are etched to expose the surface of the first lead electrode 210. The thirteenth via V13 is configured to connect a subsequently formed third lead electrode to the first lead electrode 210 through the via.

[0246] In the exemplary embodiment, the orthogonal projection of the base of the fourteenth via V14 is within the range of the orthogonal projection of the base of the second lead electrode 220. The fourth insulating layer in the fourteenth via V14 is etched to expose the surface of the second lead electrode 220. The fourteenth via V14 is configured to connect a subsequently formed fourth lead electrode to the second lead electrode 220 through the via.

[0247] 22 is a via pattern on the fourth insulating layer in the third region of the display region. Since a fifth lead electrode is further provided in the second region of the display region, the vias in the lead area in the binding region may further include a fifteenth via, which exposes the surface of the fifth lead electrode and is configured to connect a sixth lead electrode to be formed subsequently to the fifth lead electrode through the fifteenth via.

[0248] (5) Forming a third conductive layer pattern. In an exemplary embodiment, as shown in Figures 23 to 28, forming the third conductive layer may include depositing a third conductive thin film on the base on which the pattern is formed, and patterning the third conductive thin film by a patterning process to form a third conductive layer disposed on the fourth insulating layer, where Figure 23 is an enlarged view of the E0 region of Figure 11, Figure 24 is an enlarged view of the E1 region of Figure 11, Figure 25 is an enlarged view of the E2 region of Figure 11, Figure 26 is an enlarged view of the E3 region of Figure 11, Figure 27 is an enlarged view of the E4 region of Figure 11, and Figure 28 is an enlarged view of the F region of Figure 11. In an exemplary embodiment, the third conductive layer may be referred to as a first source drain metal (SD1) layer.

[0249] In an exemplary embodiment, the third conductive layer patterns of the multiple circuit units in the display area all include a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a sixth connection electrode 46 and a seventh connection electrode 47.

[0250] In an exemplary embodiment, the shape of the first connection electrode 41 may be an elongated shape with a main body portion extending along the second direction Y, a first end of the first connection electrode 41 is connected to the first plate 25 through the first via V1, and a second end of the first connection electrode 41 is connected to the second area of ​​the first active layer (which is also the first area of ​​the second active layer) through the ninth via V9. In an exemplary embodiment, the first connection electrode 41 can have the same potential as the second pole of the first transistor T1 and the first pole of the second transistor T2 (i.e., the second node N2 of the pixel driving circuit) to the first plate 25, the second pole of the first transistor T1, and the first pole of the second transistor T2.

[0251] In an exemplary embodiment, the shape of the second connection electrode 42 may be an elongated shape with a main body portion extending along the second direction Y, and a first end of the second connection electrode 42 is connected to the second plate 33 through the second via V2, and a second end of the second connection electrode 42 is connected to the first area of ​​the fifth active layer through the third via V3. In an exemplary embodiment, the second connection electrode 42 may be the first pole of the fifth transistor T5, and the second plate 33 and the first pole of the fifth transistor T5 may have the same potential. The second connection electrode 42 is set to be connected to a first power line to be formed subsequently. The second connection electrode 42 may be a connection electrode that realizes the connection between the second plate 33 and the first power line to be formed subsequently. The first power line is connected to the second plate 33 through the second connection electrode 42.

[0252] In an exemplary embodiment, the second via V2 and the third via V3 are located on either side of the light-emitting control line 24 in the second direction Y, respectively, so that the second connection electrode 42 straddles the light-emitting control line 24, and the orthogonal projection of the second connection electrode 42 at the base and the orthogonal projection of the light-emitting control line 24 at the base at least partially overlap, forming a block for the fifth transistor T5.

[0253] In an exemplary embodiment, the third connection electrode 43 may have an elongated shape with a main body portion extending along the second direction Y, and a first end of the third connection electrode 43 is connected to a first area of ​​the third active layer through a seventh via V7, and a second end of the third connection electrode 43 is connected to a second area of ​​the fourth active layer through an eighth via V8. In an exemplary embodiment, the third connection electrode 43 can be the first pole of the third transistor T3 (also the second pole of the fourth transistor T4) and can have the same potential as the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5 (first node N1).

[0254] In an exemplary embodiment, the fourth connection electrode 44 may have a rectangular shape, and the fourth connection electrode 44 is connected to the first area of ​​the fourth active layer through the fifth via V5. The fourth connection electrode 44 may be a first pole of the fourth transistor T4, and the fourth connection electrode 44 is configured to be connected to a data signal line to be formed subsequently.

[0255] In an exemplary embodiment, the fifth connection electrode 45 may be rectangular in shape, and the fifth connection electrode 45 is connected to the second area of ​​the sixth active layer (which is also the second area of ​​the seventh active layer) through the fourth via V4. The fifth connection electrode 45 may be the second pole of the sixth transistor T6 (which is also the second pole of the seventh transistor T7), and the fifth connection electrode 45 is set to be connected to the subsequently formed anode connection electrode.

[0256] In an exemplary embodiment, the sixth connecting electrode 46 may be rectangular in shape, a first end of the sixth connecting electrode 46 is connected to the first area of ​​the first active layer through the tenth via V10, and a second end of the sixth connecting electrode 46 is connected to the first initial signal line 31 through the eleventh via V11. The sixth connecting electrode 46 may be the first pole of the first transistor T1, so that the first initial signal line 31 writes the first initial signal to the first pole of the first transistor T1.

[0257] In an exemplary embodiment, the shape of the seventh connecting electrode 47 may be rectangular, a first end of the seventh connecting electrode 47 is connected to the first area of ​​the seventh active layer through the sixth via V6, and a second end of the seventh connecting electrode 47 is connected to the second initial signal line 32 through the twelfth via V12. The seventh connecting electrode 47 may be the first pole of the seventh transistor T7, so that the second initial signal line 32 writes the second initial signal to the first pole of the seventh transistor T7.

[0258] As shown in FIG. 23, in an exemplary embodiment, the third conductive layer pattern of the multiple circuit units in the third region (E0 region) may further include a first power supply wiring 91, a power supply connection electrode 85, and a power supply connection block 86.

[0259] In an exemplary embodiment, the first power supply wiring 91 may have a linear shape with a main body portion extending along the first direction X, and may be disposed on a side of the second scanning signal line 22 away from the first scanning signal line 21. In an exemplary embodiment, the first power supply wiring 91 may be connected to a frame power supply lead in the frame region, and the frame power supply lead is configured to continue to provide a high voltage signal (VDD) or a low voltage signal (VSS).

[0260] In an exemplary embodiment, the power supply connecting electrode 85 may have a rectangular shape and may be disposed on a side of the first power supply wiring 91 closer to the first scanning signal line 21, and an orthogonal projection of the power supply connecting electrode 85 at a base ... of the first initial signal line 31 may at least partially overlap. In an exemplary embodiment, the power supply connecting electrode 85 is set to be connected to a second power supply wiring to be formed subsequently.

[0261] In an exemplary embodiment, the power supply connection block 86 is installed between the first power supply wiring 91 and the power supply connection electrode 85, a first end of the power supply connection block 86 is connected to the first power supply wiring 91, and a second end of the power supply connection block 86 is connected to the power supply connection electrode 85, thereby realizing a connection between the first power supply wiring 91 and the power supply connection electrode 85.

[0262] In an exemplary embodiment, the first power supply wiring 91, the power supply connecting electrode 85, and the power supply connecting block 86 of one circuit row in the third region may be an integrated structure in which they are connected to each other.

[0263] As shown in FIG. 24, in an exemplary embodiment, the third conductive layer pattern of the multiple circuit units in the first region (E1 region) may further include a first connecting line 71 and a virtual electrode 87.

[0264] In an exemplary embodiment, the first connection line 71 of the data connection line may have a linear shape with a main body extending along the first direction X, and may be disposed on a side of the second scanning signal line 22 away from the first scanning signal line 21. In an exemplary embodiment, the first connection line 71 is configured to be connected to a second connection line of the data connection line to be formed subsequently.

[0265] In an exemplary embodiment, the positions and shapes of the virtual electrodes 87 of the multiple circuit units in the first region may be substantially the same as those of the power connection electrodes 85 in the third region, with the difference being that the virtual electrodes 87 are individually installed and are not connected to the first connection lines 71 or other electrodes. In an exemplary embodiment, the shape and connection structure of the virtual electrodes 87 are substantially the same as those of the data connection electrodes, the fan-out connection electrodes and the power connection electrodes. Since the subsequently formed signal lines are connected to the virtual electrodes through the vias, the subsequently formed first flat layer has vias in each circuit unit, which not only improves the uniformity of the manufacturing process, but also allows different regions to have substantially the same relay connection structure, and different regions to achieve substantially the same display effect in both transmitted light and reflected light, effectively eliminating the shading situation, effectively avoiding the appearance defect of the display substrate, and improving the display quality and display effect.

[0266] As shown in FIG. 25, in the exemplary embodiment, the third conductive layer pattern of the multiple circuit units in the second region (E2 region) further includes a first power supply wiring 91 and a virtual electrode 87.

[0267] In an exemplary embodiment, the position and shape of the first power supply wiring 91 of the multiple circuit units in the second region may be approximately the same as the position and shape of the first power supply wiring 91 in the third region, and the position, shape and function of the virtual electrodes 87 of the multiple circuit units in the second region may be approximately the same as the position, shape and function of the power supply connection electrodes 85 in the first region.

[0268] As shown in FIG. 26, in an exemplary embodiment, the third conductive layer pattern of at least one circuit unit in the boundary region (E3 region) between the first region and the third region may further include a first connecting line 71, a data connecting electrode 81 and a data connecting block 82.

[0269] In an exemplary embodiment, the boundary region between the first region and the third region may include at least one circuit unit of the first region, at least one circuit unit of the third region, and a first connection unit, and the first connection unit may be a circuit unit that realizes a connection between the data signal line and the first connection line via a first connection hole.

[0270] In an exemplary embodiment, the first connection unit may include a first connection line 71, a data connection electrode 81, and a data connection block 82. The circuit unit in the first region may include the first connection line 71 and a virtual electrode 87 and is located to the right of the first connection unit. The circuit unit in the third region may include a first power supply line 91 and a virtual electrode 87 and is located to the left of the first connection unit.

[0271] In an exemplary embodiment, the data connection electrode 81 may be rectangular in shape and may be disposed on the side of the first connection line 71 away from the virtual electrode 87. There is a first distance L1 between the first connection line 71 and the data connection electrode 81, and the first distance L1 may be greater than 0. In an exemplary embodiment, the first distance L1 may be a distance between an edge of the first connection line 71 close to the data connection electrode 81 side and an edge of the data connection electrode 81 close to the first connection line 71, and the first distance L1 is a size in the second direction Y. The data connection block 82 may be rectangular in shape and may be disposed between the first connection line 71 and the data connection electrode 81. A first end of the data connection block 82 is connected to the first connection line 71, and a second end of the data connection block 82 is connected to the data connection block 82, thereby realizing a connection between the first connection line 71 and the data connection electrode 81. In an exemplary embodiment, the data connection electrode 81 is set to be connected to a data signal line to be formed subsequently.

[0272] In an exemplary embodiment, the data connection electrode 81 may be connected to the fourth connection electrode 44 in the pixel driving circuit.

[0273] In an exemplary embodiment, the fourth connection electrode 44 in the pixel driving circuit can be the data connection electrode 81, that is, the data connection electrode 81 and the fourth connection electrode 44 (the first pole of the fourth transistor) have a common structure. In the present disclosure, the first pole of the fourth transistor in the pixel driving circuit is used as the data connection electrode connected to the first connection line, thereby reducing the number of apertures in the first planar layer, which not only simplifies the process, but also contributes to the layout and is advantageous to improving the resolution.

[0274] In an exemplary embodiment, at least one first break opening DF1 may be provided in at least one circuit unit in the third region adjacent to the first connection unit. The first break opening DF1 interrupts the first connection line 71 and the first power supply line 91 in the same circuit row, and the first break opening DF1 is located on the first connection line 71 side in the first direction X and the first break opening DF1 is located on the first power supply line 91 side opposite to the first direction X.

[0275] As shown in FIG. 27, in an exemplary embodiment, the third conductive layer pattern of at least one circuit unit in the boundary region (E4 region) between the first region and the second region may further include a first connection line 71, a fan-out connection electrode 83 and a fan-out connection block 84.

[0276] In an exemplary embodiment, the boundary region between the first region and the second region may include at least one circuit unit of the first region, at least one circuit unit of the second region, and a second connection unit, and the second connection unit may be a circuit unit that realizes a connection between the first connection line and the second connection line via a second connection hole.

[0277] In an exemplary embodiment, the second connection unit may include a first connection line 71, a fan-out connection electrode 83, and a fan-out connection block 84. The circuit unit in the first region may include a first connection line 71 and a virtual electrode 87 and is located to the left of the first connection unit. The circuit unit in the second region may include a first power supply wiring 91 and a virtual electrode 87 and is located to the right of the second connection unit.

[0278] In an exemplary embodiment, the shape of the fan-out connection electrode 83 may be rectangular and may be disposed on the side of the first connection line 71 away from the second initial signal line 32. There is a second distance L2 between the first connection line 71 and the fan-out connection electrode 83, and the second distance L2 may be greater than 0. In an exemplary embodiment, the second distance L2 may be a distance between an edge of the first connection line 71 close to the fan-out connection electrode 83 and an edge of the fan-out connection electrode 83 close to the first connection line 71, and the second distance L2 is a size in the second direction Y. The shape of the fan-out connection block 84 may be rectangular and may be disposed between the first connection line 71 and the fan-out connection electrode 83, and a first end of the fan-out connection block 84 is connected to the first connection line 71 and a second end of the fan-out connection block 84 is connected to the fan-out connection electrode 83, thereby realizing a connection between the first connection line 71 and the fan-out connection electrode 83. In an exemplary embodiment, the fan-out connection electrode 83 is set to be connected to a second connection line to be formed subsequently.

[0279] In an exemplary embodiment, at least one first break opening DF1 may be provided in at least one circuit unit in the first region adjacent to the second connection unit. The first break opening DF1 interrupts the first connection line 71 and the first power supply line 91 in the same circuit row, and the side of the first break opening DF1 opposite to the first direction X is the first connection line 71, and the side of the first break opening DF1 in the first direction X is the first power supply line 91.

[0280] In an exemplary embodiment, at least two first break openings DF1 are provided at both ends of a single first connecting line 71, and one first break opening DF1 may be located near the boundary region between the first region and the third region, and the other first break opening DF1 may be located near the boundary region between the first region and the second region.

[0281] As shown in FIG. 28, in an exemplary embodiment, the third conductive layer pattern of the lead area in the binding region includes at least a plurality of third lead electrodes 230, a plurality of fourth lead electrodes 240, a binding high voltage wire 250 and a plurality of binding high voltage electrodes 260.

[0282] In an exemplary embodiment, the third lead electrode 230 may have an elongated shape extending along the second direction Y, the positions of the plurality of third lead electrodes 230 may correspond to the positions of the plurality of first lead electrodes 210, the orthogonal projection of the third lead electrode 230 at the base and the orthogonal projection of the first lead electrode 210 at the base at least partially overlap, and the third lead electrode 230 is connected to the first lead electrode 210 through a thirteenth via V13. In an exemplary embodiment, the plurality of third lead electrodes 230 are set to be connected to correspond to the data signal lines of the odd-numbered unit columns to be formed subsequently.

[0283] In an exemplary embodiment, the fourth lead electrode 240 may have an elongated shape extending along the second direction Y, the positions of the plurality of fourth lead electrodes 240 may correspond to the positions of the plurality of second lead electrodes 220, the orthogonal projection of the fourth lead electrode 240 at the base and the orthogonal projection of the second lead electrode 220 at the base at least partially overlap, and the fourth lead electrode 240 is connected to the second lead electrode 220 through a fourteenth via V14. In an exemplary embodiment, the plurality of fourth lead electrodes 240 are set to be connected to correspond to the data signal lines of the even-numbered unit columns to be formed subsequently.

[0284] In an exemplary embodiment, the binding high voltage line 250 may have an elongated shape extending along the first direction X, and the binding high voltage line 250 is configured to continuously provide a high level signal to a plurality of first power lines in the display area.

[0285] In an exemplary embodiment, the binding high voltage electrode 260 may have an elongated shape extending along the second direction Y, and the plurality of binding high voltage electrodes 260 may be sequentially disposed along the first direction X, with first ends of the plurality of binding high voltage electrodes 260 connected to the binding high voltage line 250 and second ends of the plurality of binding high voltage electrodes 260 extending toward the display area. In an exemplary embodiment, the plurality of binding high voltage electrodes 260 are configured to be connected to corresponding first power lines to be subsequently formed.

[0286] 28 is the third conductive layer pattern of the third region in the display region, and for the second region in the display region, since the fifth lead electrode is provided in the second region, the third conductive layer pattern of the second region may further include a sixth lead electrode, which is connected to the fifth lead electrode through the fifteenth via, and is set to be connected to the second connection line formed subsequently. Therefore, the second region includes not only a plurality of third lead electrodes and a plurality of fourth lead electrodes, but also a plurality of sixth lead electrodes, and the number of lead electrodes in the second region is different from the number of lead electrodes in the third region.

[0287] In an exemplary embodiment, the sixth lead electrode and the third lead electrode (fourth lead electrode) may have substantially the same structure.

[0288] (6) Forming a first flat layer pattern. In an exemplary embodiment, as shown in Fig. 29 to Fig. 34, forming the first flat layer pattern may include applying a first flat thin film to the base on which the pattern is formed, patterning the first flat thin film by a patterning process to form a first flat layer covering the third conductive layer, and providing a plurality of vias in the first flat layer, Fig. 29 is an enlarged view of the E0 region in Fig. 11, Fig. 30 is an enlarged view of the E1 region in Fig. 11, Fig. 31 is an enlarged view of the E2 region in Fig. 11, Fig. 32 is an enlarged view of the E3 region in Fig. 11, Fig. 33 is an enlarged view of the E4 region in Fig. 11, and Fig. 34 is an enlarged view of the F region in Fig. 11.

[0289] In the exemplary embodiment, the vias of the circuit units in the display area all include a twenty-first via V21, a twenty-second via V22, and a twenty-third via V23.

[0290] In the exemplary embodiment, the orthogonal projection of the base of the 21st via V21 is within the range of the orthogonal projection of the base of the second connecting electrode 42, and the first flat layer in the 21st via V21 is removed to expose the surface of the second connecting electrode 42. The 21st via V21 is configured such that a subsequently formed first power line is connected to the second connecting electrode 42 through the via.

[0291] In an exemplary embodiment, the orthogonal projection at the base of the 22nd via V22 is within the range of the orthogonal projection at the base of the fourth connecting electrode 44, and the first planar layer in the 22nd via V22 is removed to expose the surface of the fourth connecting electrode 44. The 22nd via V22 is configured so that a subsequently formed data signal line is connected to the fourth connecting electrode 44 through the via.

[0292] In an exemplary embodiment, the orthogonal projection at the base of the 23rd via V23 is within the range of the orthogonal projection at the base of the fifth connecting electrode 45, and the first planar layer in the 23rd via V23 is removed to expose the surface of the fifth connecting electrode 45. The 23rd via V23 is configured such that a subsequently formed anode connecting electrode is connected to the fifth connecting electrode 45 through the via.

[0293] As shown in FIG. 29, in the exemplary embodiment, the plurality of circuit units in the third region (E0 region) further includes a twenty-fourth via V24.

[0294] In an exemplary embodiment, the orthogonal projection of the 24th via V24 at its base is within the range of the orthogonal projection of the power supply connecting electrode 85 at its base, and the first flat layer in the 24th via V24 is removed to expose the surface of the power supply connecting electrode 85. The 24th via V24 is set so that a second power supply wiring to be formed subsequently is connected to the power supply connecting electrode 85 through the via. In an exemplary embodiment, the 24th via V24 may be referred to as a third connection hole.

[0295] As shown in FIGS. 30 and 31, in the exemplary embodiment, the plurality of circuit units in the first region (E1 region) and the plurality of circuit units in the second region (E2 region) further include a 25th via V25.

[0296] In an exemplary embodiment, the orthogonal projection at the base of the 25th via V25 is within the range of the orthogonal projection at the base of the virtual electrode 87, and the first flat layer in the 25th via V25 is removed to expose the surface of the virtual electrode 87. The 25th via V25 is configured such that a subsequently formed second power wiring is connected to the virtual electrode 87 through the via.

[0297] As shown in FIG. 32, in the exemplary embodiment, at least one circuit unit in the boundary region (E3 region) between the first region and the third region further includes a 26th via V26.

[0298] In an exemplary embodiment, the orthogonal projection at the base of the 26th via V26 is within the range of the orthogonal projection at the base of the data connection electrode 81, and the first planar layer in the 26th via V26 is removed to expose the surface of the data connection electrode 81. The 26th via V26 is configured so that a subsequently formed data signal line is connected to the data connection electrode 81 through the via.

[0299] In an exemplary embodiment, the twenty-sixth via V26 and the twenty-second via V22 may be a common structure of the same via. In an exemplary embodiment, the twenty-sixth via V26 may be referred to as a first connection hole.

[0300] As shown in FIG. 33, in the exemplary embodiment, at least one circuit unit in the boundary region (E4 region) between the first region and the second region further includes a 27th via V27.

[0301] In an exemplary embodiment, the orthogonal projection at the base of the 27th via V27 is within the range of the orthogonal projection at the base of the fan-out connection electrode 83, and the first flat layer in the 27th via V27 is removed to expose the surface of the fan-out connection electrode 83. The 27th via V27 is configured so that a subsequently formed second connection line is connected to the fan-out connection electrode 83 through the via. In an exemplary embodiment, the 27th via V27 may be referred to as a second connection hole.

[0302] In an exemplary embodiment, the 26th via V26 may be located on the side opposite to the second direction Y of the first connecting line 71, and the 27th via V27 may be located on the side of the first connecting line 71 in the second direction Y. That is, the first connecting hole (26th via V26) and the second connecting hole (27th via V27) connecting the same first connecting line 71 are respectively disposed on both sides of the first connecting line 71 in the second direction Y.

[0303] As shown in FIG. 34, in an exemplary embodiment, the plurality of vias in the lead area in the binding region includes at least a thirty-first via V31, a thirty-second via V32, and a thirty-third via V33.

[0304] In an exemplary embodiment, the orthogonal projection at the base of the 31st via V31 is within the range of the orthogonal projection at the base of the third lead electrode 230, and the first flat layer in the 31st via V31 is removed to expose the surface of the third lead electrode 230. The 31st via V31 is set so that data signal lines of odd-numbered columns in a display area to be subsequently formed are connected to the third lead electrode 230 through the via.

[0305] In an exemplary embodiment, the orthogonal projection at the base of the 32-th via V32 is within the range of the orthogonal projection at the base of the fourth lead electrode 240, and the first flat layer in the 32-th via V32 is removed to expose the surface of the fourth lead electrode 240. The 32-th via V32 is set so that data signal lines of even-numbered columns in a display area to be subsequently formed are connected to the fourth lead electrode 240 through the via.

[0306] In an exemplary embodiment, the orthogonal projection at the base of the 33rd via V33 is within the range of the orthogonal projection at the base of the binding high voltage electrode 260, and the first planar layer in the 33rd via V33 is removed to expose the surface of the binding high voltage electrode 260. The 33rd via V33 is configured such that a first power line in a subsequently formed display area is connected to the binding high voltage electrode 260 through the via.

[0307] 34 is a via pattern on the first flat layer in the third region of the display region. Since a sixth lead electrode is further provided in the second region of the display region, the vias in the lead area in the binding region may further include a thirty-fourth via, which exposes the surface of the sixth lead electrode and is configured so that a second connection line formed subsequently is connected to the sixth lead electrode through the via.

[0308] (7) Form a fourth conductive layer pattern. In an exemplary embodiment, as shown in FIG. 35 to FIG. 40, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the base on which the pattern is formed, and patterning the fourth conductive thin film by a patterning process to form a fourth conductive layer disposed on the first flat layer, where FIG. 35 is an enlarged view of the E0 region of FIG. 11, FIG. 36 is an enlarged view of the E1 region of FIG. 11, FIG. 37 is an enlarged view of the E2 region of FIG. 11, FIG. 38 is an enlarged view of the E3 region of FIG. 11, FIG. 39 is an enlarged view of the E4 region of FIG. 11, and FIG. 40 is an enlarged view of the F region of FIG. 11. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source drain metal (SD2) layer.

[0309] In an exemplary embodiment, the fourth conductive layer patterns of the multiple circuit units in the display area all include a first power line 51 , an anode connecting electrode 52 and a data signal line 60 .

[0310] In an exemplary embodiment, the shape of the first power line 51 may be a broken line whose main body extends along the second direction Y. On the one hand, the first power line 51 is connected to the second connection electrode 42 through the 21st via V21 in the display area, and on the other hand, the first power line 51 extends to the lead area and then is connected to the binding high voltage electrode 260 through the 33rd via V33 in the lead area. Since the second connection electrode 42 is respectively connected to the second plate and the first area of ​​the fifth active layer through the vias, the first power line 51 writes a power signal to the first pole of the fifth transistor T5, and the second plate of the storage capacitor and the first power line 51 have the same potential. Since the binding high voltage electrode 260 is connected to the binding high voltage line 250, the binding high voltage line 250 provides a high level signal to the first power line 51 through the binding high voltage electrode 260.

[0311] In an exemplary embodiment, the orthogonal projection at the base of the first power line 51 and the orthogonal projection at the base of the first connecting electrode 41 at least partially overlap, and the first power line 51 can effectively shield the influence of the data voltage jump on the key node of the pixel driving circuit, avoid the influence of the data voltage jump on the potential of the key node of the pixel driving circuit, and improve the display effect.

[0312] In an exemplary embodiment, the orthogonal projection at the base of the first power line 51 includes an orthogonal projection at the base of the first connection electrode 41, and the orthogonal projection at the base of the first power line 51 includes an orthogonal projection at the base of the second connection electrode 42.

[0313] In an exemplary embodiment, the first power supply line 51 may be of a non-equal width design, and the first power supply line 51 adopting a non-equal width design can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power supply line and the data signal line.

[0314] In an exemplary embodiment, the shape of the data signal line 60 may be a straight line whose main body portion extends along the second direction Y. On the one hand, the data signal line 60 is connected to the fourth connection electrode 44 through the 22nd via V22 in the display area, and on the other hand, after the data signal line 60 extends to the lead area, the data signal line 60 of the odd-numbered unit column is connected to the third lead electrode 230 through the 31st via V31, and the data signal line 60 of the even-numbered unit column is connected to the fourth lead electrode 240 through the 32nd via V32. Since the fourth connection electrode 44 is connected to the first area of ​​the fourth active layer through a via, it is possible for the data signal line 60 to write a data signal to the first pole of the fourth transistor T4.

[0315] In an exemplary embodiment, Fig. 40 shows the fourth conductive layer pattern of the third region in the display area, where the data signal line 60 is respectively connected to the third lead electrode 230 and the fourth lead electrode 240. For the second region in the display area, the fourth conductive layer pattern of the second region may further include a second connecting line, which extends to the lead area and then connects to the sixth lead electrode through the 34th via.

[0316] In an exemplary embodiment, the connection structure between the second connecting line and the lead electrode is substantially the same as the connection structure between the data signal line and the lead electrode, and the second connecting line can pull out the data signal lines of the odd-numbered unit columns via the first connecting line, or the second connecting line can pull out the data signal lines of the even-numbered unit columns via the first connecting line, which will not be described repeatedly here.

[0317] In the exemplary embodiment, the third lead electrode 230 is connected to the first lead electrode 210 through a via, and the first lead electrode 210 is connected to the first lead line, thereby realizing a connection between the data signal line 60 of the odd-numbered unit column and the first lead line located in the first conductive layer (GATE1). The fourth lead electrode 240 is connected to the second lead electrode 220 through a via, and the second lead electrode 220 is connected to the second lead line, thereby realizing a connection between the data signal line 60 of the even-numbered unit column and the second lead line located in the second conductive layer (GATE2).

[0318] In an exemplary embodiment, the multiple lead lines in the lead area may include multiple first lead lines provided in the first conductive layer (GATE1) and multiple second lead lines provided in the second conductive layer (GATE2), and the multiple first lead lines may be connected to the data signal lines 60 of the odd-numbered unit columns via the first lead electrode 210 and the third lead electrode 230, and the multiple second lead lines may be connected to the data signal lines 60 of the even-numbered unit columns via the second lead electrode 220 and the fourth lead electrode 240. In the present disclosure, by providing multiple lead lines in two conductive layers, the width of the lead lines can be increased while avoiding short circuits, thereby improving the reliability of data transmission.

[0319] In an exemplary embodiment, the multiple first lead-out lines may be connected to correspond to data signal lines of even-numbered unit columns, and the multiple second lead-out lines may be connected to correspond to data signal lines of odd-numbered unit columns, although the present disclosure is not limited thereto.

[0320] In an exemplary embodiment, the anode connecting electrode 52 may be rectangular in shape, and the anode connecting electrode 52 is connected to the fifth connecting electrode 45 through the twenty-third via V23. In an exemplary embodiment, the anode connecting electrode 52 is set to be connected to an anode to be formed subsequently. Since the fifth connecting electrode 45 is connected to the second area of ​​the sixth active layer (which is also the second area of ​​the seventh active layer) through a via, it is realized that the anode is connected to the second pole of the sixth transistor T6 (which is also the second pole of the seventh transistor T7) through the anode connecting electrode 52 and the fifth connecting electrode 45.

[0321] As shown in FIG. 35, in the exemplary embodiment, the fourth conductive layer pattern of the multiple circuit units in the third region (E0 region) may further include a second power supply wiring 92.

[0322] In an exemplary embodiment, the shape of the second power wiring 92 may be a straight line whose main body extends along the second direction Y, and the second power wiring 92 is connected to the power connection electrode 85 through the 24th via V24. The power connection electrode 85 is connected to the first power wiring 91 through the power connection block 86, so that the second power wiring 92 and the first power wiring 91 are connected to each other, and the first power wiring 91 extending along the first direction X and the second power wiring 92 extending along the second direction Y form a net-like interconnection structure. In the present disclosure, the power wiring having the net-like interconnection structure is provided, and the power wirings in the multiple unit rows and multiple unit columns have the same potential, thereby effectively reducing the resistance of the power wiring and reducing the voltage drop in transmitting the low-voltage signal, as well as effectively improving the uniformity of the low-voltage signal on the display substrate, effectively improving the display uniformity, and improving the display quality and display effect.

[0323] In the exemplary embodiment, the orthogonal projection of the power supply connecting electrode 85 at the base and the orthogonal projection of the second power supply wiring 92 at the base at least partially overlap. In an exemplary embodiment, the orthogonal projection of the power supply connection electrode 85 on the base may be within the range of the orthogonal projection of the second power supply wiring 92 on the base. In the exemplary embodiment, the orthogonal projections of the power connection block 86 at the base and the orthogonal projections of the second power wiring 92 at the base at least partially overlap. In an exemplary embodiment, the orthogonal projection of the power connection block 86 at its base may be within the range of the orthogonal projection of the second power wiring 92 at its base.

[0324] As shown in FIG. 36, in the exemplary embodiment, the fourth conductive layer pattern of the multiple circuit units in the first region (E1 region) may further include a second power supply wiring 92.

[0325] In the exemplary embodiment, the second power supply wire 92 is connected to the virtual electrode 87 through a twenty-fifth via V25.

[0326] In the exemplary embodiment, the position and shape of the virtual electrode 87 are substantially the same as the position and shape of the power connection electrode and the data connection electrode, so that the hole connection structures of the second power wirings 92 and the virtual electrodes 87 of the multiple circuit units in the first region are substantially the same as the hole connection structures of the circuit units in other regions, which not only can improve the uniformity of the manufacturing process, but also can enable different regions to achieve the same display effect in both transmitted light and reflected light, and effectively avoid shading elimination.

[0327] As shown in FIG. 37, in an exemplary embodiment, the fourth conductive layer pattern of at least one circuit unit in the second region (E2 region) may further include a second connecting line 72, and other circuit units may include a second power supply wiring 92.

[0328] In an exemplary embodiment, the shape of the second connection line 72 may be a straight line with its main body extending along the second direction Y, and the second connection line 72 is connected to the virtual electrode 87 via the 25th via V25.

[0329] In the exemplary embodiment, the second power supply wire 92 is connected to the virtual electrode 87 through a twenty-fifth via V25.

[0330] As shown in FIG. 38, in an exemplary embodiment, the data signal line 60 of at least one circuit unit in the boundary region (E3 region) between the first region and the third region is connected to the data connection electrode 81 via the 26th via V26. Since the data connection electrode 81 is connected to the first connection line 71 via the data connection block 82, the connection between the data signal line 60 and the first connection line 71 is realized.

[0331] In an exemplary embodiment, the orthographic projection of the data connection electrode 81 on the base and the orthographic projection of the data signal line 60 on the base overlap at least partially. In an exemplary embodiment, the orthographic projection of the data connection electrode 81 on the base may be within the range of the orthographic projection of the data signal line 60 on the base. In an exemplary embodiment, the orthographic projection of the data connection block 82 on the base and the orthographic projection of the data signal line 60 on the base overlap at least partially. In an exemplary embodiment, the orthographic projection of the data connection block 82 on the base may be within the range of the orthographic projection of the data signal line 60 on the base.

[0332] In an exemplary embodiment, the second power supply line 92 of other circuit units in the boundary region between the first region and the third region is connected to the virtual electrode 87 via the 25th via V25.

[0333] In an exemplary embodiment, the orthographic projection of the first break DF1 on the base located between the first connection line 71 and the first power supply line 91 and the orthographic projection of the second power supply line 92 on the base overlap at least partially, or the orthographic projection of the first break DF1 on the base and the orthographic projection of the second connection line 72 on the base overlap at least partially.

[0334] In an exemplary embodiment, the orthographic projection of the first break DF1 on the base may be within the range of the orthographic projection of the second power supply line 92 or the second connection line 72 on the base, that is, the first break DF1 is covered by the second power supply line 92 or the second connection line 72, and by shielding the first break DF1 with the second power supply line 92 or the second connection line 72, the difference in the film layers of different regions can be effectively eliminated, and the appearance defect of the display substrate can be further avoided.

[0335] As shown in FIG. 39, in an exemplary embodiment, the fourth conductive layer pattern of the second connection unit in the boundary region (E4 region) between the first region and the second region may further include a second connection line 72.

[0336] In an exemplary embodiment, the shape of the second connection line 72 may be a straight line whose main body portion extends along the second direction Y, and the second connection line 72 is connected to the fan-out connection electrode 83 through the 27th via V27. The fan-out connection electrode 83 is connected to the first connection line 71 through the fan-out connection block 84, thereby realizing an interconnection between the second connection line 72 and the first connection line 71. Since the first connection line 71 is connected to the data signal line, it is realized that the data signal line 60 is connected to the second connection line 72 through the first connection line 71.

[0337] In the exemplary embodiment, the second power supply wiring 92 of another circuit unit in the boundary region between the first region and the second region is connected to the virtual electrode 87 through a twenty-fifth via V25.

[0338] In an exemplary embodiment, the orthogonal projections of the fan-out connection electrodes 83 at their bases and the orthogonal projections of the second connection lines 72 at their bases at least partially overlap. In an exemplary embodiment, the orthogonal projection at the base of the fan-out connection electrode 83 may be within the range of the orthogonal projection at the base of the second connection line 72 . In the exemplary embodiment, the orthogonal projections at the base of the fan-out connection block 84 and the orthogonal projections at the base of the second connection lines 72 at least partially overlap. In an exemplary embodiment, the orthogonal projection at the base of the fan-out connection block 84 may be within the orthogonal projection at the base of the second connection line 72 .

[0339] In an exemplary embodiment, at least one second break opening DF2 may be provided in at least one circuit unit in the first region adjacent to the second connection unit. The second break opening DF2 interrupts the second connection line 72 and the second power supply line 92 in the same circuit row, and the side of the second break opening DF2 in the second direction Y is the second connection line 72, and the side of the second break opening DF2 opposite to the second direction Y is the second power supply line 92.

[0340] In the exemplary embodiment, an orthogonal projection of the second break opening DF2 on the base and an orthogonal projection of the first connection line 71 or the first power supply wiring 91 on the base at least partially overlap.

[0341] In an exemplary embodiment, the orthogonal projection at the base of the second break opening DF2 may be within the range of the orthogonal projection at the base of the first connecting line 71 or the first power wiring 91, and the first connecting line 71 or the first power wiring 91 may be laid under the second break opening DF2, which can effectively eliminate the difference in film layers in different regions and further avoid poor appearance of the display substrate.

[0342] As shown in FIG. 40, in an exemplary embodiment, the fourth conductive layer pattern of the lead area in the binding region includes at least a binding power lead 410 .

[0343] In an exemplary embodiment, the binding power lead 410 may have an elongated shape extending along the first direction X, and the binding power lead 410 is connected to each of the second power wirings 92 in the display area. In an exemplary embodiment, the binding power lead 410 is configured to continuously provide a high level signal to the second power wirings 92 in the display area, or configured to continuously provide a low level signal to the second power wirings 92 in the display area.

[0344] In an exemplary embodiment, a plurality of lead openings 420 may be provided on the binding power lead 410, and the fourth conductive thin film in the lead openings 420 is removed to expose the first planar layer. In an exemplary embodiment, the plurality of lead openings 420 are configured to release water vapor in the first planar layer.

[0345] In an exemplary embodiment, the binding high voltage wire 250 and the binding power lead 410 in the lead area may be connected to binding pads in the binding pin area after spanning the folding area and the driving chip area, and an external control device provides high voltage signals and low voltage signals to the binding high voltage wire 250 and the binding power lead 410, respectively, via the flexible substrate and the binding pads.

[0346] In an exemplary embodiment, a plurality of first power wirings in the display area may be connected to frame power lead wires in the frame area, and the connection structure between the first power wirings and the power lead frame is substantially the same as the connection structure between the second power wirings and the binding power lead described above, and will not be repeated here.

[0347] Fig. 41 is a structural schematic diagram of a region where a first break opening is located according to an exemplary embodiment of the present disclosure, which is an enlarged view of region C3 in Fig. 38. As shown in Fig. 41, the first break opening DF1 may be disposed between the first connecting line 71 and the first power wiring 91 in one unit row, thereby realizing insulation between the first connecting line 71 and the first power wiring 91.

[0348] In an exemplary embodiment, the first width B1 of the first break opening DF1 may be less than or equal to the second width B2 of the second power supply wiring 92 or the second connecting line 72, and the first width B1 and the second width B2 may be sizes in the first direction X.

[0349] In an exemplary embodiment, the orthogonal projection of the first break opening DF1 at the base may be within the range of the orthogonal projection at the base of the second power supply wiring 92 or the second connecting line 72, i.e., both of the two edges of the first break opening DF1 are within the coverage area of ​​the second power supply wiring 92 or the second connecting line 72.

[0350] Fig. 42 is a structural schematic diagram of a region where a second break opening is located according to an exemplary embodiment of the present disclosure, which is an enlarged view of region C4 in Fig. 38. As shown in Fig. 42, the second break opening DF2 may be installed between the second connecting line 72 and the second power supply wiring 92 in one unit row, thereby realizing insulation between the second connecting line 72 and the second power supply wiring 92.

[0351] In an exemplary embodiment, the third width B3 of the second break opening DF2 may be smaller than the fourth width B4 of the first connection line 71 or the first power wiring 91, and the third width B3 and the fourth width B4 may be sizes in the second direction Y.

[0352] In an exemplary embodiment, the orthogonal projection at the base of the second break opening DF2 may be within the range of the orthogonal projection at the base of the first connection line 71 or the first power wiring 91, i.e., both edges of the second break opening DF2 are within the coverage range of the first connection line 71 or the first power wiring 91.

[0353] In another exemplary embodiment, the width B3 of the second break opening DF2 is equal to the width B4 of the first connecting line 71 or the first power supply wiring 91, and the boundary of the orthogonal projection at the base of the second break opening DF2 and the boundary of the orthogonal projection at the base of the first connecting line 71 or the first power supply wiring 91 are approximately aligned, forming a structure like a “pattern complementary”.

[0354] In an exemplary embodiment, when subsequently forming the anode pattern, the orthogonal projections of the first break opening DF1 and the second break opening DF2 at the base do not overlap with the orthogonal projections of the anode at the base, i.e., the first break opening DF1 and the second break opening DF2 are both located outside the coverage area of ​​the anode.

[0355] Up to this point, the fabrication of the driving structure layer on the base is completed. In a plane parallel to the display substrate, the driving structure layer may include a plurality of circuit units. Each circuit unit may include a pixel driving circuit, and a first scanning signal line, a second scanning signal line, a third scanning signal line, a light emission control line, a data signal line, a first power line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving structure layer may include at least a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a first flat layer, and a fourth conductive layer, which are sequentially stacked on the base.

[0356] In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be, but is not limited to, one or more of glass and quartz. The flexible base may be, but is not limited to, one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyaryl ester, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fiber. In an exemplary embodiment, the flexible base includes a first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer, which are stacked together. The materials of the first flexible material layer and the second flexible material layer may be polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer may be silicon nitride (SiNx), silica (SiOx), or the like, to improve the water and oxygen resistance of the base. The material of the semiconductor layer may be amorphous silicon (a-si).

[0357] In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer and the fourth conductive layer may adopt metal materials, such as one or more of silver (Ag), copper (Cu), aluminum (Al) and molybdenum (Mo), or alloy materials of the above metals, such as aluminum-neodymium alloy (AlNd) or molybdenum-niobium alloy (MoNb), and may be a single layer structure or a multi-layer composite structure, such as Mo / Cu / Mo, etc. The first insulating layer, the second insulating layer, the third insulating layer and the fourth insulating layer may adopt one or more of silicon oxide (SiOx), silicon nitride (SiNx) and silicon oxynitride (SiON), and may be a single layer, a multi-layer or a composite layer. The first insulating layer is called a buffer layer, the second insulating layer and the third insulating layer are called gate insulating (GI) layers, and the fourth insulating layer is called an interlayer dielectric (ILD) layer. The first planar layer may adopt an organic material, such as a resin, etc. The active layer may employ materials such as amorphous indium gallium zinc oxide (a-IGZO), zinc oxynitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polycrystalline silicon (p-Si), hexathiophene or polythiophene, etc. That is, the present disclosure applies to transistors fabricated based on oxide technology, silicon technology or organic technology.

[0358] In an exemplary embodiment, after the fabrication of the driving structure layer is completed, the light emitting structure layer and the sealing structure layer may be fabricated on the driving structure layer in sequence, which will not be described again here.

[0359] In the display substrate, the display area includes a wiring area where data connection lines are provided and a normal area where no data connection lines are provided. When exposed to external light, the data connection lines in the wiring area have high reflectivity, but other metal lines in the normal area have low reflectivity, so that the appearance of the normal area and the appearance of the wiring area are obviously different, which causes the display substrate to have a problem of poor appearance, especially when the screen is off or a low gray scale is displayed.

[0360] As can be seen from the above-described structure and manufacturing process of the display substrate, in the present disclosure, the data connection line and the power supply line are provided in the display area, and the power supply line is provided in the normal area where the data connection line is not provided, so that the wiring area and the normal area have substantially the same wiring structure, and the different areas can achieve substantially the same display effect in both transmitted light and reflected light, effectively avoiding the appearance defect of the display substrate and improving the display quality and display effect. In the present disclosure, a virtual electrode is provided in the display area, and the shape and connection structure of the virtual electrode are substantially the same as those of the data connection electrode, the fan-out connection electrode and the power connection electrode, so that different positions of the display substrate have substantially the same relay connection structure, and the appearance defect of the display substrate can be further avoided. In the present disclosure, the first connection line is laid under the second break opening, and the second connection line is used to shield the first break opening, effectively eliminating the difference in the film layers of different areas, and the appearance defect of the display substrate can be further avoided.

[0361] In the present disclosure, the power supply wiring is arranged within the display area, thereby realizing a VSS in pixel structure, and the width of the frame power supply lead wire can be greatly reduced, and the width of the left and right frame can be greatly reduced, improving the screen occupancy rate and favoring the realization of full screen display. In the present disclosure, the power supply wiring is arranged in a net-like interconnection structure, which not only effectively reduces the resistance of the power supply wiring, effectively reduces the voltage drop of the low-voltage power supply signal, and realizes low power consumption, but also effectively improves the uniformity of the power supply signal on the display substrate, effectively improves the display uniformity, and improves the display quality and display effect. The manufacturing process according to the present disclosure is highly compatible with the conventional manufacturing process, is simple to realize, easy to implement, has high production efficiency, low production cost, and high yield rate.

[0362] The above structure and its manufacturing process in the present disclosure are merely exemplary. In the exemplary embodiment, the corresponding structure can be modified or the configuration process can be increased or decreased according to actual needs, and the present disclosure is not limited thereto.

[0363] In an exemplary embodiment, the display substrate of the present disclosure may be applied to a display device having a pixel driving circuit, such as an OLED, a quantum dot display (QLED), a light emitting diode display (Micro LED or Mini LED), or a quantum dot light emitting diode display (QDLED), and the present disclosure is not limited thereto.

[0364] 43 is an equivalent circuit schematic diagram of a pixel driving circuit according to an exemplary embodiment of the present disclosure. As shown in FIG. 43, the pixel driving circuit may include a storage capacitor C and a first transistor T1 to a seventh transistor T7. The pixel driving circuit is respectively connected to a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a third scanning signal line S3, an emission signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a first power supply line VDD, and a light emitting device OLED.

[0365] In an exemplary embodiment, a first end of the storage capacitor C is connected to the first power supply line VDD, and a second end (second node N2) of the storage capacitor C is connected to a gate electrode of a third transistor (driving transistor) T3. A gate electrode of the first transistor (first initialization transistor) T1 is connected to a second scanning signal line S2, a first pole of the first transistor T1 is connected to a first initial signal line INIT1, and a second pole of the first transistor is connected to a gate electrode of a third transistor T3. A gate electrode of the second transistor (compensation transistor) T2 is connected to a first scanning signal line S1, a first pole of the second transistor T2 is connected to a gate electrode of the third transistor T3, and a second pole of the second transistor T2 is connected to a second pole (third node N3) of the third transistor T3. A gate electrode of the third transistor (driving transistor) T3 is connected to a second end of the storage capacitor C, a first pole (first node N1) of the third transistor T3 is connected to a second pole of the fourth transistor T4, and a second pole of the third transistor T3 is connected to a first pole of a sixth transistor T6. The gate electrode of the fourth transistor (data write transistor) T4 is connected to the third scanning signal line S3, the first pole of the fourth transistor T4 is connected to the data signal line D, and the second pole of the fourth transistor T4 is connected to the first pole of the third transistor T3. The gate electrode of the fifth transistor (light emission control transistor) T5 is connected to the light emission signal line E, the first pole of the fifth transistor T5 is connected to the first power supply line VDD, and the second pole of the fifth transistor T5 is connected to the first pole of the third transistor T3. The gate electrode of the sixth transistor (light emission control transistor) T6 is connected to the light emission signal line E, the first pole of the sixth transistor T6 is connected to the second pole of the third transistor T3, and the second pole of the sixth transistor T6 is connected to the first pole of the light emitting device OLED. The gate electrode of the seventh transistor (second initialization transistor) T7 is connected to the third scanning signal line S3, the first pole of the seventh transistor T7 is connected to the second initialization signal line INIT2, and the second pole of the seventh transistor T7 is connected to the first pole of the light emitting device OLED.

[0366] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. By adopting the same type of transistors in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the yield rate of the product can be improved. In some possible implementations, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors.

[0367] In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may adopt low temperature polysilicon film transistors, or oxide film transistors, or both low temperature polysilicon film transistors and oxide film transistors. The active layer of the low temperature polysilicon film transistor adopts low temperature polysilicon (abbreviated as LTPS), and the active layer of the oxide film transistor adopts oxide semiconductor (Oxide). The low temperature polysilicon film transistor has advantages such as high mobility and fast charging, and the oxide film transistor has advantages such as low leakage current. The low temperature polysilicon film transistor and the oxide film transistor are integrated into one display substrate, i.e., the LTPS+Oxide (abbreviated as LTPO) display substrate, and the advantages of both can be utilized to realize low frequency driving, reduce power consumption, and improve display quality.

[0368] In an exemplary embodiment, the pixel driving circuit according to the exemplary embodiment of the present disclosure may have a high frequency display mode and a low frequency display mode. Figure 44 is an operation timing diagram of the pixel driving circuit according to the exemplary embodiment of the present disclosure, showing the operation timing of the low frequency display mode by taking the first transistor T1 to the seventh transistor T7 as an example where they are all P-type transistors. As shown in Figure 44, in the low frequency display mode, the operation timing of the pixel driving circuit may include a step timing of refreshing a frame and a step timing of holding a frame.

[0369] In an exemplary embodiment, in the step of refreshing a frame, the operation process of the pixel driving circuit may include the following:

[0370] In the reset period of the frame refreshing stage, the signal of the second scanning signal line S2 turns on the first transistor T1, provides the first initial voltage of the first initial signal line INIT1 to the second node N2, initializes the storage capacitor C, and clears the original data voltage in the storage capacitor. The signals of the first scanning signal line S1, the third scanning signal line S3, and the emission signal line E turn off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7.

[0371] In the data write period of the frame refresh step, the signals of the first scan signal line S1 and the third scan signal line S3 turn on the second transistor T2, the fourth transistor T4, and the seventh transistor T7. During this period, the second end of the storage capacitor C is at a low level, so the third transistor T3 turns on, and the second transistor T2 and the fourth transistor T4 turn on, and thus the data voltage output from the data signal line D is provided to the second end of the storage capacitor C through the turned-on third transistor T3 and the turned-on second transistor T2. By turning on the seventh transistor T7, the second initial voltage of the second initial signal line INIT2 is provided to the first pole of the OLED, which initializes (resets) the first pole of the OLED, clears the voltage previously stored therein, and completes the initialization. The signals of the second scan signal line S3 and the light-emitting signal line E turn off the first transistor T1, the fifth transistor T5, and the sixth transistor T6.

[0372] In the emission period of the frame refreshing step, the signal of the emission signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the OLED to emit light.

[0373] In an exemplary embodiment, in the stage of holding a frame, the operation process of the pixel driving circuit may include the following:

[0374] In the reset period of the frame holding stage, the signals of the first scanning signal line S1, the second scanning signal line S2, the third scanning signal line S3, and the light emission signal line E turn off the first transistor T1 to the seventh transistor T7.

[0375] In the data write period of the frame holding step, the signal of the third scan signal line S3 turns on the fourth transistor T4 and the seventh transistor T7. When the fourth transistor T4 is turned on, the data voltage output from the data signal line D is input to the first terminal of the third transistor T3. When the seventh transistor T7 is turned on, the second initial voltage of the second initial signal line INIT2 is provided to the first terminal of the OLED, which initializes (resets) the first terminal of the OLED, clears the voltage previously stored therein, and completes the initialization.

[0376] In the emission period of the frame holding step, the signal of the emission signal line E turns on the fifth transistor T5 and the sixth transistor T6, and the power supply voltage output from the first power supply line VDD provides a driving voltage to the first electrode of the OLED via the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6, thereby driving the OLED to emit light.

[0377] In an exemplary embodiment, the first scanning signal line S1 turns on the second transistor T2 only in the frame refreshing step, and the third scanning signal line S3 turns on the fourth transistor T4 in the frame refreshing step and the frame holding step, respectively. Therefore, in the data writing step of the frame holding step, a data voltage can be input to the first end of the third transistor T3, and the effect on the OLED emission brightness caused by the voltage jump of the first node N1 at the moment of entering the emission step (the fifth transistor T5 is turned on) can be weakened.

[0378] In an exemplary embodiment, in the case of a high frequency display mode, the pixel driving circuit may also perform frame refresh step timing in the frame hold step, although the present disclosure is not limited thereto.

[0379] The present disclosure further provides a method for driving the display substrate, which is configured to drive the display substrate. In an exemplary embodiment, the display substrate may include a plurality of circuit units, at least one of which may include a pixel driving circuit, the pixel driving circuit including at least a compensation transistor, a driving transistor, and a data writing transistor, a gate electrode of the compensation transistor is connected to a first scanning signal line, a first pole of the compensation transistor is connected to a gate electrode of the driving transistor, a second pole of the compensation transistor is connected to a second pole of the driving transistor, a gate electrode of the data writing transistor is connected to a third scanning signal line, a first pole of the data writing transistor is connected to a data signal line, and a second pole of the data writing transistor is connected to a first pole of the driving transistor, and the driving method includes: In a frame refresh step, the first scanning signal line controls the turn-on of the compensation transistor, the third scanning signal line controls the turn-on of the data write transistor, and a data voltage outputted from the data signal line is supplied to a gate electrode of the driving transistor; In the step of holding the frame, the third scanning signal line controls turning on of the data writing transistor, and a data voltage outputted by the data signal line is supplied to a first electrode of the driving transistor.

[0380] The present disclosure further provides a method for manufacturing a display substrate, for manufacturing the display substrate according to the above embodiment. In an exemplary embodiment, the display substrate comprises a plurality of circuit units, a plurality of data signal lines, and a plurality of data connecting lines, the data connecting lines including a first connecting line extending along a first direction and a second connecting line extending along a second direction, the data signal lines extend along the second direction, and the first direction and the second direction cross each other, and the manufacturing method includes: The method may include forming a data connection electrode in at least one circuit unit, forming a fan-out connection electrode in at least one circuit unit, forming a data signal line, a first connection line and a second connection line, the second connection line being connected to the first connection line via the fan-out connection electrode, the first connection line being connected to the data signal line via the data connection electrode, an orthogonal projection of the data connection electrode on the display substrate plane at least partially overlapping with an orthogonal projection of the data signal line on the display substrate plane, an orthogonal projection of the fan-out connection electrode on the display substrate plane at least partially overlapping with an orthogonal projection of the second connection line on the display substrate plane, a first distance between the data connection electrode and the first connection line, a second distance between the fan-out connection electrode and the first connection line, the first distance and the second distance being greater than 0, and the first distance and the second distance being sizes in the second direction.

[0381] The present disclosure further provides a display device, which comprises the above-mentioned display substrate. The display device may be a product or part having a display function, such as a mobile phone, a tablet, a television, a monitor, a laptop, a digital frame, a navigator, etc. The embodiments of the present invention are not limited thereto.

[0382] The above is an embodiment disclosed in the present disclosure, but the above content is an embodiment used to facilitate understanding of the present disclosure, and is not intended to limit the present invention. Those skilled in the art can make any modifications and changes to the embodiments and details without departing from the spirit and scope disclosed in the present disclosure, but the patent protection scope of the present invention is subject to the scope of the attached claims. [Explanation of symbols]

[0383] 11 first active layer, 12 second active layer, 13 third active layer, 14 4th active layer, 15 5th active layer, 16 6th active layer, 17 seventh active layer, 21 first scanning signal line, 21-1 gate electrode block, 22 second scanning signal line, 23 third scanning signal line, 24 light emission control line, 25 first electrode plate, 31 first initial signal line, 32 second initial signal line, 33 second electrode plate, 34 electrode plate connecting wire, 35 shield electrode, 36 opening, 37 protrusion, 41 first connection electrode, 42 second connection electrode, 43 third connection electrode, 44 fourth connection electrode, 45 fifth connection electrode, 46 sixth connection electrode, 47 seventh connection electrode, 51 first power line, 52 anode connecting electrode, 60 data signal line, 70 data connection line, 71 first connection line, 72 second connection line, 80 Lead wire, 81 Data connection electrode, 82 Data connection block, 83 fan-out connection electrode, 84 fan-out connection block, 85 power supply connection electrode, 86 power supply connection block, 87 virtual electrode, 91 first power supply wiring, 92 second power wiring, 100 display area, 101 base, 102 driving structure layer, 103 light emitting structure layer, 104 sealing structure layer, 110 first area, 120 second area, 130 third area, 200 binding area, 201 lead area, 210 first lead electrode, 220 second lead electrode, 230 third lead electrode, 240 fourth lead electrode, 250 binding high voltage wire, 260 binding high voltage electrode, 300 frame area, 301 anode, 302 pixel definition layer, 303 organic light-emitting layer, 304 cathode, 401 first sealing layer, 402 second sealing layer, 403 third sealing layer, 410 binding power lead, 420 lead opening, 510 Frame Power Lead

Claims

1. A display board comprising a plurality of circuit units, a plurality of data signal lines, and a plurality of data connection lines, wherein the data connection lines include a first connection line extending in a first direction and a second connection line extending in a second direction, the data signal lines extend in a second direction, the first direction and the second direction intersect, at least one circuit unit includes a data connection electrode, at least one circuit unit includes a fan-out connection electrode, the second connection line is connected to the first connection line via the fan-out connection electrode, and the first connection line is connected via the data connection electrode A display board connected to the data signal line, wherein the orthographic projection of the data connection electrode on the display board plane and the orthographic projection of the data signal line on the display board plane overlap at least partially, the orthographic projection of the fan-out connection electrode on the display board plane and the orthographic projection of the second connection line on the display board plane overlap at least partially, there is a first distance between the data connection electrode and the first connection line, there is a second distance between the fan-out connection electrode and the first connection line, the first distance and the second distance are greater than 0, and the first distance and the second distance are the size in the second direction.

2. The display board according to claim 1, wherein the data connection electrode and the fan-out connection electrode, both connected to the same first connection line, are provided on both sides of the first connection line, respectively.

3. At least one circuit unit includes a data connection block, the data connection electrodes are connected to the first connection line via the data connection block, and the orthographic projection of the data connection block on the display board plane and the orthographic projection of the data signal line on the display board plane overlap at least partially. Or, At least one circuit unit includes a fan-out connection block, the fan-out connection electrodes are connected to the first connection line via the fan-out connection block, and the orthographic projection of the fan-out connection block on the display board plane and the orthographic projection of the second connection line on the display board plane overlap at least partially. Or, The display board according to claim 1, wherein at least one circuit unit includes a virtual electrode, and the position and shape of the virtual electrode in one circuit unit is the same as the position and shape of the fan-out connection electrode in the other circuit unit.

4. The display board according to claim 1, further comprising a plurality of first power supply wires extending along the first direction and a plurality of second power supply wires extending along the second direction, wherein at least one circuit unit includes a power supply connection electrode, the second power supply wires are connected to the first power supply wires via the power supply connection electrode, and the orthographic projection of the power supply connection electrode on the display board plane and the orthographic projection of the second power supply wires on the display board plane at least partially overlap.

5. At least one circuit unit includes a power connection block, the power connection electrodes are connected to the first power wiring via the power connection block, and the orthographic projection of the power connection block on the display board plane and the orthographic projection of the second power wiring on the display board plane overlap at least partially. Or, The display board according to claim 4, wherein at least one circuit unit includes a virtual electrode, and the position and shape of the virtual electrode in one circuit unit are the same as the position and shape of the power connection electrode in the other circuit unit.

6. The display board according to claim 4, wherein the first power supply wiring and the first connection line are installed on the same layer, at least one first power supply wiring and at least one first connection line are provided in at least one circuit row, a first break is provided between the first connection line and the first power supply wiring, and the orthographic projection of the first break on the display board plane and the orthographic projection of the second power supply wiring on the display board plane overlap at least partially, or the orthographic projection of the first break on the display board plane and the orthographic projection of the second connection line on the display board plane overlap at least partially.

7. The display board according to claim 6, wherein the first width of the first break is less than or equal to the second width of the second power supply wiring or the second connection wire, the first width and the second width are sizes in the first direction, and the orthographic projection of the first break on the display board plane is within the range of the orthographic projection of the second power supply wiring or the second connection wire on the display board plane.

8. The display board according to claim 4, wherein the second power supply wiring and the second connection line are installed on the same layer, at least one second power supply wiring and at least one second connection line are provided in at least one circuit row, a second break is provided between the second connection line and the second power supply wiring, and the orthographic projection of the second break on the display board plane and the orthographic projection of the first connection line or the first power supply wiring on the display board plane at least partially overlap.

9. The display board according to claim 8, wherein the third width of the second break is equal to the fourth width of the first connection line or the first power supply wiring, the third width and the fourth width are the sizes in the second direction, and the orthographic boundary of the second break on the display board plane and the orthographic boundary of the first connection line or the first power supply wiring on the display board plane are aligned.

10. The display board according to claim 4, comprising a display area and a binding area located on one side of the display area in the second direction, wherein the binding area is provided with binding power leads configured to subsequently supply a high-level signal or a low-level signal, and at least one second power wiring of the display area is connected to the binding power leads of the binding area.

11. The display substrate according to claim 1, wherein at least one circuit unit includes at least a pixel driving circuit, the pixel driving circuit includes at least a storage capacitor and a plurality of transistors, and in a plane perpendicular to the display substrate, the circuit unit includes semiconductor layers, a first conductive layer, a second conductive layer, a third conductive layer and a fourth conductive layer sequentially mounted on a base, the semiconductor layers include active layers of at least a plurality of transistors, the first conductive layer includes gate electrodes of at least a plurality of transistors and a first plate of a storage capacitor, the second conductive layer includes at least a second plate of a storage capacitor, the third conductive layer includes at least the first connection line, and the fourth conductive layer includes at least the data signal line and the second connection line.

12. The third conductive layer further includes a data connection electrode and a fan-out connection electrode, each connected to the first connection line, wherein the data signal line is connected to the data connection electrode via a first connection hole, and the second connection line is connected to the fan-out connection electrode via a second connection hole. Or, The third conductive layer further includes a first power wiring extending along the first direction and a power connection electrode connected to the first power wiring, the fourth conductive layer further includes a second power wiring extending along the second direction, the second power wiring is connected to the power connection electrode via a third connection hole, Or, The display substrate according to claim 11, wherein the third conductive layer further includes a virtual electrode, and the second connecting line is connected to the virtual electrode via a connecting hole.

13. The display board according to claim 11, wherein the plurality of transistors include at least a first transistor as a first initialization transistor, a second transistor as a compensation transistor, a third transistor as a drive transistor, a fourth transistor as a data writing transistor, a fifth and sixth transistor as light emission control transistors, and a seventh transistor as a second initialization transistor, and the second and fourth transistors are respectively located on both sides of the third transistor in the second direction.

14. A display device comprising the display board described in claim 1.

15. A driving method for driving a display board according to claim 1, The display board comprises a plurality of circuit units, at least one of which includes a pixel driving circuit, the pixel driving circuit includes at least a compensation transistor, a driving transistor and a data writing transistor, the gate electrode of the compensation transistor is connected to a first scan signal line, the first pole of the compensation transistor is connected to the gate electrode of the driving transistor, the second pole of the compensation transistor is connected to the second pole of the driving transistor, the gate electrode of the data writing transistor is connected to a third scan signal line, the first pole of the data writing transistor is connected to a data signal line, the second pole of the data writing transistor is connected to the first pole of the driving transistor, and the driving method is, During the frame refresh stage, the first scan signal line controls the turn-on of the compensation transistor, the third scan signal line controls the turn-on of the data writing transistor, and the data voltage output by the data signal line is supplied to the gate electrode of the drive transistor. A driving method for driving a display board according to claim 1, comprising the steps of: during the stage of holding the frame, the third scanning signal line controls the turn-on of the data writing transistor, and the data voltage output by the data signal line is supplied to the first pole of the driving transistor.

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