Display substrate and display device

Abstract

It represents a display substrate and a display device. The display substrate includes a display region 100, the display region 100 includes a base 101, a driving circuit layer 102 and a light-emitting structure layer 103, the driving circuit layer 102 includes a plurality of circuit units, data signal lines 60, data connection lines 70, a low-voltage power supply line 80 and a power supply wiring 90, the light-emitting structure layer 103 includes a plurality of light-emitting devices, the circuit unit includes a pixel driving circuit, the data signal line 60 is configured to supply a data signal to the pixel driving circuit, the low-voltage power supply line 80 is configured to continuously supply a low-power supply voltage signal to the light-emitting device, the data connection line 70 is connected to the data signal line 60, and the power supply wiring 90 is connected to the low-voltage power supply line 80.

Description

【Technical Field】 【0001】 This application claims the priority of a Chinese patent application filed with the China National Intellectual Property Administration on June 15, 2022, with an application number of 202210670468.6 and an invention title of "Display Substrate and Display Device", the content of which should be understood as incorporated herein by reference. 【0002】 This specification relates to the field of display technologies, but is not limited thereto. Specifically, it relates to a display substrate and a display device. 【Background Art】 【0003】 Organic Light Emitting Diode (abbreviated as OLED) and Quantum-dot Light Emitting Diodes (abbreviated as QLED) are active light-emitting display devices, which have advantages such as self-luminescence, wide viewing angle, high contrast, low power consumption, extremely fast response speed, light weight, thin thickness, bendability, and low cost. With the development of display technologies, flexible display devices that use OLEDs or QLEDs as light-emitting devices and perform signal control with Thin Film Transistors (abbreviated as TFT) have become the mainstream products in the current display field. 【Summary of the Invention】 【0004】 The following is an overview of the subject matter described in this specification. This overview does not limit the scope of protection of the claims. 【0005】 In one aspect, the present disclosure provides a display substrate including a display region. The display region includes a driving circuit layer provided on a base, and a light-emitting structure layer provided on a side of the driving circuit layer away from the base. The driving circuit layer includes a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, a plurality of low-voltage power lines, and a plurality of power supply lines. The light-emitting structure layer includes a plurality of light-emitting devices. The circuit unit includes a pixel driving circuit. The data signal line is configured to supply a data signal to the pixel driving circuit. The low-voltage power line is configured to continuously supply a low-power voltage signal to the light-emitting device. The data connection line is connected to the data signal line, and the power supply line is connected to the low-voltage power line. 【0006】 In an exemplary embodiment, the data connection line includes a first connection line extending along a first direction and a second connection line extending along a second direction. The first connection line is connected to the second connection line. The power supply line includes a first power supply line extending along the first direction and a second power supply line extending along the second direction. The first power supply line is connected to the second power supply line. The first direction intersects the second direction. In a plane parallel to the base, the display region includes at least a first region where the first connection line is provided. In at least one circuit unit of the first region, the first connection line, the first power supply line, and the second power supply line are included. The shapes of the data signal line and the low-voltage power line are linear and extend along the second direction. The first connection line is connected to the data signal line. The second power supply line is installed between the low-voltage power line and the data signal line, and the second power supply line is connected to the low-voltage power line. 【0007】 In an exemplary embodiment, the driving circuit layer includes a plurality of conductive layers sequentially provided on the base. The first connection line and the second connection line are provided on the same conductive layer. The first connection line and the data signal line are provided on different conductive layers. In at least one circuit unit of the first region, the first connection line is connected to the data signal line through a first connection hole. 【0008】 In an exemplary embodiment, the driving circuit layer includes a plurality of conductive layers sequentially provided on a base. The first power supply line and the second power supply line are provided on the same conductive layer. The second power supply line and the low-voltage power supply line are provided on different conductive layers. In at least one circuit unit of the first region, the second power supply line is connected to the low-voltage power supply line through a second connection hole. 【0009】 In an exemplary embodiment, at least one circuit unit of the first region further includes a power connection electrode. The power connection electrode is installed on a side away from the data signal line of the second power supply line and is connected to the second power supply line. The orthographic projection of the power connection electrode on the base at least partially overlaps the orthographic projection of the low-voltage power supply line on the base. The power connection electrode is connected to the low-voltage power supply line through a second connection hole. 【0010】 In an exemplary embodiment, the first connection lines in the circuit units adjacent in the first direction are connected to each other, and the first power supply lines in the circuit units adjacent in the first direction are connected to each other. 【0011】 In an exemplary embodiment, in the first region, the second power supply lines in the circuit units adjacent in the second direction are installed at intervals, and the first connection line is installed between the second power supply lines adjacent in the second direction. 【0012】 In an exemplary embodiment, at least one circuit unit of the first region further includes a second compensation line extending along the second direction. The second compensation line is installed on a side away from the data signal line of the second power supply line. The second compensation line is connected to the first power supply line. The second compensation lines in the circuit units adjacent in the second direction are installed at intervals, and the first connection line is installed between the second compensation lines adjacent in the second direction. 【0013】 In an exemplary embodiment, in a plane parallel to the base, the display area further includes a second area where the second connection line is provided, at least one circuit unit in the second area includes the second connection line, and the second connection lines in the circuit units adjacent in the second direction are connected to each other. 【0014】 In an exemplary embodiment, at least one circuit unit in the second area includes two second connection lines, the two second connection lines include a first side connection line and a second side connection line, the first side connection line is installed between the low-voltage power line and the data signal line, and the second side connection line is installed on the side away from the data signal line of the low-voltage power line. 【0015】 In an exemplary embodiment, at least one circuit unit in the second area further includes a dummy connection electrode, the dummy connection electrode is installed on the side close to the first side connection line of the second side connection line and is connected to the second side connection line, and the orthographic projection of the dummy connection electrode on the base at least partially overlaps with the orthographic projection of the low-voltage power line on the base. 【0016】 In an exemplary embodiment, in at least one unit row including the circuit units in the first area and the circuit units in the second area, the second power supply wiring in the first area and the first side connection line in the second area are located on the same straight line extending along the second direction, the second compensation line in the first area and the second side connection line in the second area are located on the same straight line extending along the second direction, the power supply connection electrode in the first area and the dummy connection electrode in the second area are located on the same straight line extending along the second direction, and in at least one unit row including the circuit units in the first area and the circuit units in the second area, the power supply connection electrode in the first area and the dummy connection electrode in the second area are located on the same straight line extending along the first direction. 【0017】 In an exemplary embodiment, at least one circuit unit in the second region further includes at least two first compensation lines extending along the first direction, and the at least two first compensation lines include at least one first side compensation line and at least one second side compensation line. A first end of the first side compensation line is connected to the first side connection line, a second end of the first side compensation line extends along a direction close to the second side connection line, a first end of the second side compensation line is connected to the second side connection line, and a second end of the second side compensation line extends along a direction close to the first side connection line. 【0018】 In an exemplary embodiment, in at least one unit row including the circuit unit in the first region and the circuit unit in the second region, the first power supply line in the first region and the first side compensation line in the second region are located on the same straight line extending along the first direction, and the first connection line in the first region and the second side compensation line in the second region are located on the same straight line extending along the first direction. 【0019】 In an exemplary embodiment, in a plane parallel to the base, the display region further includes a third region that does not overlap with the orthographic projections of the first connection line and the second connection line on the base. At least one circuit unit in the third region includes the first power supply line and the second power supply line, and the second power supply line is connected to the low-voltage power supply line through a second connection hole. 【0020】 In an exemplary embodiment, at least one circuit unit in the third region further includes a power supply connection electrode. The power supply connection electrode is installed on a side away from the data signal line of the second power supply line and is connected to the second power supply line. The orthographic projection of the power supply connection electrode on the base at least partially overlaps with the orthographic projection of the low-voltage power supply line on the base, and the power supply connection electrode is connected to the low-voltage power supply line through the second connection hole. 【0021】 In an exemplary embodiment, the first power supply lines in the circuit units adjacent in the first direction are connected to each other, and the second power supply lines in the circuit units adjacent in the second direction are connected to each other. 【0022】 In an exemplary embodiment, at least one circuit unit in the third region further includes a first compensation line extending along the first direction and a second compensation line extending along the second direction. The first compensation lines in the circuit units adjacent in the first direction are connected to each other, the second compensation lines in the circuit units adjacent in the second direction are connected to each other, the first compensation line is connected to the second power supply line, the second compensation line is connected to the first power supply line, and the first compensation line is connected to the second compensation line. 【0023】 In an exemplary embodiment, in at least one unit row including the circuit units in the first region and the circuit units in the third region, the first connection line in the first region and the first compensation line in the third region are located on the same straight line extending along the first direction. In at least one unit column including the circuit units in the first region and the circuit units in the third region, the second compensation line in the first region and the second compensation line in the third region are located on the same straight line extending along the second direction. 【0024】 In an exemplary embodiment, in a plane parallel to the base, the display area further includes a second area where the second connection line is provided, and a third area that does not overlap with the orthographic projection of the first connection line and the second connection line on the base. In at least one unit row including the circuit units in the first area, the circuit units in the second area, and the circuit units in the third area, the first power supply wiring in the first area, the first side compensation line in the first compensation line in the second area, and the first power supply wiring in the third area are located on the same straight line extending along the first direction. The first connection line in the first area, the second side compensation line in the first compensation line in the second area, and the first compensation line in the third area are located on the same straight line extending along the first direction. The power supply connection electrode in the first area, the dummy connection electrode in the second area, and the power supply connection electrode in the third area are located on the same straight line extending along the first direction. In at least one unit column including the circuit units in the first area, the circuit units in the second area, and the circuit units in the third area, the second power supply wiring in the first area, the first side connection line in the second connection line in the second area, and the second power supply wiring in the third area are located on the same straight line extending along the second direction. The second compensation line in the first area, the second side connection line in the second connection line in the second area, and the second compensation line in the third area are located on the same straight line extending along the second direction. The power supply connection electrode in the first area, the dummy connection electrode in the second area, and the power supply connection electrode in the third area are located on the same straight line extending along the second direction. 【0025】 In an exemplary embodiment, the display substrate further includes a binding area located on the second direction side of the display area. The binding area includes at least a binding lead wire, a first power supply connection line, and a first power supply pin. The first end of the first power supply connection line is connected to the low-voltage power supply line through a via. The second end of the second power supply connection line extends in a direction away from the display area and is then connected to the first power supply pin. The first power supply pin is connected to the binding lead wire through a via. 【0026】 In an exemplary embodiment, the display substrate further includes an upper bezel region located on the opposite side of the display region in the second direction. The upper bezel region includes at least an upper bezel lead wire, a second power connection bar, a second power connection line, and a second power pin. The first end of the second power connection bar is connected to the low-voltage power line via a via. The second end of the second power connection bar is connected to the first end of the second power connection line. The second end of the second power connection line extends along a direction away from the display region and is then connected to the second power pin. The second power pin is connected to the upper bezel lead wire via a via. 【0027】 In an exemplary embodiment, the display substrate further includes side bezel regions located on one or both sides of the display region in the first direction. The side bezel regions include at least side bezel lead wires, a third power connection line, and a third power pin. The first end of the third power connection line is connected to the power wiring via a via. The second end of the third power connection line extends along a direction away from the display region and is then connected to the third power pin. The third power pin is connected to the side bezel lead wire via a via. 【0028】 In an exemplary embodiment, the driving circuit layer further includes a plurality of circuit units. The circuit units include pixel driving circuits. The pixel driving circuits include at least a storage capacitor and a plurality of transistors. In a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer sequentially provided on a base. The semiconductor layer includes at least the active layers of a plurality of transistors. The first conductive layer includes at least the gate electrodes of a plurality of transistors and the first electrode plate of the storage capacitor. The second conductive layer includes at least the second electrode plate of the storage capacitor. The third conductive layer includes at least the first and second electrodes of a plurality of transistors. The fourth conductive layer includes at least the data signal line and the low-voltage power line. The fifth conductive layer includes at least the data connection line and the power wiring. 【0029】 In an exemplary embodiment, the third conductive layer further includes a first power line, the first power line is configured to continuously supply a high power voltage signal to the pixel driving circuit, a front projection of a base of the low voltage power line at least partially overlaps with a front projection of a base of the first power line and has a first overlapping area, the front projection of the base of the first power line has a first area, and the first overlapping area is larger than 0.8 * the first area. 【0030】 In an exemplary embodiment, the second conductive layer further includes a second initial signal line, the second initial signal line is configured to supply a second initial signal to the pixel driving circuit, a front projection of a base of a first connection line in the data connection line at least partially overlaps with a front projection of a base of the second initial signal line and has a second overlapping area, the front projection of the base of the first connection line has a second area, and the second overlapping area is larger than 0.8 * the second area. 【0031】 In another aspect, the present disclosure further provides a display device including the above display substrate. 【0032】 Other aspects can be understood after reading and understanding the drawings and the detailed description. 【0033】 The drawings are for understanding the technical solutions of the present disclosure, and form a part of the specification. They are used together with the embodiments of the present application to explain the technical solutions of the present disclosure, and are not used to limit the technical solutions of the present disclosure. 【Brief Description of the Drawings】 【0034】 【Figure 1】 It is a structural schematic diagram of a display device. 【Figure 2】 It is a structural schematic diagram of a display substrate. 【Figure 3】 It is a planar structural schematic diagram of a display area of a display substrate. 【Figure 4】 It is a cross-sectional structural schematic diagram of a display area of a display substrate. 【Figure 5】 It is an equivalent circuit schematic diagram of a pixel driving circuit. 【Figure 6】It is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure. 【Figure 7】 It is a schematic layout diagram of data connection lines according to an exemplary embodiment of the present disclosure. 【Figure 8】 It is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure. 【Figure 9】 It is a schematic layout diagram of data connection lines and power supply lines according to an exemplary embodiment of the present disclosure. 【Figure 10】 It is a schematic diagram of area division of a display area according to an exemplary embodiment of the present disclosure. 【Figure 11】 Figures 11a to 11c are schematic structural diagrams of three regions according to an embodiment of the present disclosure. 【Figure 12】 It is a schematic diagram after forming a semiconductor layer pattern in an embodiment of the present disclosure. 【Figure 13】 Figures 13a and 13b are schematic diagrams after forming a first conductive layer pattern in an embodiment of the present disclosure. 【Figure 14】 Figures 14a and 14b are schematic diagrams after forming a second conductive layer pattern in an embodiment of the present disclosure. 【Figure 15】 It is a schematic diagram after forming a fourth insulating layer pattern in an embodiment of the present disclosure. 【Figure 16】 Figures 16a and 16b are schematic diagrams after forming a third conductive layer pattern in an embodiment of the present disclosure. 【Figure 17】 It is a schematic diagram after forming a first flat layer pattern in an embodiment of the present disclosure. 【Figure 18】 Figures 18a to 18d are schematic diagrams after forming a fourth conductive layer pattern in an embodiment of the present disclosure. 【Figure 19】 Figures 19a to 19c are schematic diagrams after forming a second flat layer pattern in an embodiment of the present disclosure. 【Figure 20】 Figures 20a to 20f are schematic diagrams after forming a fifth conductive layer pattern in an embodiment of the present disclosure. 【Figure 21】 Figures 21a to 21c are schematic diagrams after forming a third flat layer pattern in an embodiment of the present disclosure. 【Figure 22】 Figures 22a to 22d are schematic diagrams after forming the anode conductive layer pattern in the embodiments of the present disclosure. 【Figure 23】 It is a schematic plan view of the power supply wiring in an exemplary embodiment of the present disclosure. 【Figure 24】 It is a schematic connection diagram of the power supply wiring and the binding lead wire in an exemplary embodiment of the present disclosure. 【Figure 25】 It is a schematic connection diagram of the power supply wiring and the upper bezel lead wire in an exemplary embodiment of the present disclosure. 【Figure 26】 It is a schematic connection diagram of the power supply wiring and the side bezel lead wire in an exemplary embodiment of the present disclosure. 【DETAILED DESCRIPTION OF THE INVENTION】 【0035】 To make the objectives, technical solutions, and advantages of the present disclosure clearer, the embodiments of the present disclosure will be described in detail below with reference to the drawings. It should be noted that the embodiments can be implemented in many different forms. As can be easily understood by those skilled in the art, the methods and contents can be converted into various forms without departing from the gist and scope of the present disclosure. Therefore, the present disclosure should not be construed as being limited only to the descriptions of the following embodiments. If there is no conflict, the embodiments and features of the embodiments of the present disclosure can be combined with each other. 【0036】 The proportions of the drawings in the present disclosure may be used as a reference in the actual process, but are not limited thereto. For example, the ratio of the width to the length of the channel, the thickness and spacing of each film layer, and the width and spacing of each signal line may be adjusted according to actual needs. The number of pixels on the display substrate and the number of sub-pixels in each pixel are not limited to the numbers shown in the drawings. The drawings described in the present disclosure are only schematic structural diagrams, and one aspect of the present disclosure is not limited to the shapes or numerical values shown in the drawings. 【0037】 The ordinal numbers such as "first", "second", "third", etc. in this specification are for avoiding confusion of components and do not limit in terms of quantity. 【0038】 In this specification, for convenience, terms indicating orientation or positional relationships such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are used to describe the positions of components with reference to the drawings. This is for the purpose of explaining this specification and simplifying the description, and is not for indicating or suggesting that the described device or element must have a specific orientation and be configured and operated in a specific orientation. Therefore, it is not for restricting the present disclosure. The positional relationships of the components can be appropriately changed according to the directions for explaining each component. Therefore, not limited to the terms described in the specification, they can be appropriately changed in some cases. 【0039】 In this specification, unless otherwise clearly defined and limited, the terms "attach", "connect", and "couple" should be understood in a broad sense. For example, it may be a fixed connection, or a removable connection, or an integrated connection. It may be a mechanical connection, or an electrical connection. It may be a direct connection, or an indirect connection via a linker, or an internal communication between two elements. Those skilled in the art can understand the specific meanings of the above technical terms in the present disclosure according to specific situations. 【0040】 In this specification, a transistor refers to an element including at least three terminals: a gate electrode, a drain electrode, and a source electrode. A transistor has a channel region between the drain electrode (drain electrode terminal, drain region, or drain electrode) and the source electrode (source electrode terminal, source region, or source electrode), and current can flow through the drain electrode, the channel region, and the source electrode. Note that in this specification, the channel region refers to the region where current mainly flows. 【0041】 In this specification, the first electrode may be a drain electrode and the second electrode may be a source electrode, or the first electrode may be a source electrode and the second electrode may be a drain electrode. When using transistors with opposite polarities, or when the current direction during operation in a circuit changes, etc., the functions of the "source electrode" and the "drain electrode" may be converted with each other. Therefore, in this specification, the "source electrode" and the "drain electrode" can be converted with each other, and the "source terminal" and the "drain terminal" can be converted with each other. 【0042】 In this specification, "electrically connected" includes the case where components are connected via an element having a certain electrical function. The "element having a certain electrical function" is not particularly limited, as long as it can transmit and receive electrical signals between the connected components. Examples of the "element having a certain electrical function" include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, and elements having various other functions. 【0043】 In this specification, "parallel" refers to a state where the angle formed by two straight lines is -10° or more and 10° or less, so a state where the angle is -5° or more and 5° or less is also included. Also, "perpendicular" refers to a state where the angle formed by two straight lines is 80° or more and 100° or less, so a state with an angle of 85° or more and 95° or less is also included. 【0044】 In this specification, "film" and "layer" are interchangeable. For example, a "conductive layer" may be changed to a "conductive film". Similarly, an "insulating film" may also be changed to an "insulating layer". 【0045】 Triangles, rectangles, trapezoids, pentagons, hexagons, etc. in this specification are not strict, and may be approximate triangles, rectangles, trapezoids, pentagons, hexagons, etc., and there may be small deformations due to tolerances, chamfers, arc sides, and deformations may exist. 【0046】 "About" in this disclosure does not strictly limit the boundary, and refers to the case where numerical values within the error range of the process and measurement are allowed. 【0047】 FIG. 1 is a schematic structural diagram of a display device. As shown in FIG. 1, the display device includes a timing controller, a data driver, a scan driver, a light-emitting driver, and a pixel array. The timing controller is connected to the data driver, the scan driver, and the light-emitting driver respectively. The data driver is connected to a plurality of data signal lines (D1 to Dn) respectively. The scan driver is connected to a plurality of scan signal lines (S1 to Sm) respectively. The light-emitting driver is connected to a plurality of light-emitting signal lines (E1 to Eo) respectively. The pixel array may include a plurality of sub-pixels Pxij, where i and j may be natural numbers. At least one sub-pixel Pxij may include a circuit unit and a light-emitting unit connected to the circuit unit. The circuit unit may include a pixel driving circuit. The pixel driving circuit is connected to the scan signal line, the data signal line, and the light-emitting signal line respectively. In an exemplary embodiment, the timing controller provides a gray value and a control signal conforming to the data driver's standard to the data driver, provides a clock signal, a scan start signal, etc. conforming to the scan driver's standard to the scan driver, and provides a clock signal, an emission stop signal, etc. conforming to the light-emitting driver's standard to the light-emitting driver. The data driver uses the gray value and the control signal received from the timing controller to generate a data voltage to be provided to the data signal lines D1, D2, D3,..., Dn. For example, the data driver can sample the gray value using a clock signal and apply a data voltage corresponding to the gray value to the data signal lines D1 to Dn in units of pixel rows, where n may be a natural number. The scan driver can generate a scan signal to be provided to the scan signal lines S1, S2, S3,..., Sm by receiving a clock signal, a scan start signal, etc. from the timing controller. For example, the scan driver can sequentially provide a scan signal having a turn-on level pulse to the scan signal lines S1 to Sm. For example, the scan driver may be configured in the form of a shift register, and can generate a scan signal by sequentially transporting a scan start signal provided in the form of a turn-on level pulse under the control of a clock signal to the circuit of the next stage, where m may be a natural number.The light-emitting driver can generate emission signals to be provided to the emission signal lines E1, E2, E3, …, Eo by receiving a clock signal, an emission stop signal, etc. from the timing controller. For example, the light-emitting driver can sequentially provide emission signals having cutoff level pulses to the emission signal lines E1 to Eo. For example, the light-emitting driver may be configured in the form of a shift register, and can generate emission signals by sequentially transporting the emission stop signal provided in the form of a cutoff level pulse to the next-stage circuit under the control of the clock signal, where o may be a natural number. 【0048】 FIG. 2 is a schematic structural diagram of a display substrate. As shown in FIG. 2, the display substrate may include a display area 100, a binding area 200 located on the side of the display area 100, and a bezel area 300 located on the other side of the display area 100. In an exemplary embodiment, the display area 100 may be a flat area, include a plurality of sub-pixels Pxij constituting a pixel array, the plurality of sub-pixels Pxij are configured to display moving images or still images, and the display area 100 may be referred to as an active area (AA). In an exemplary embodiment, since the display substrate may employ a flexible substrate, the display substrate may be deformable, for example, curled, curved, folded, or rolled up. 【0049】 In an exemplary embodiment, the binding region 200 may include a fan-out region, a bend region, a driver chip region, and a binding pin region that are sequentially provided along a direction away from the display region. The fan-out region is connected to the display region 100 and includes at least data fan-out lines. The plurality of data fan-out lines are configured to be connected to the data signal lines of the display region by fan-out wiring. The bend region is connected to the fan-out region and may include a composite insulating layer provided with grooves, and is configured to bend the binding region to the back surface of the display region. The driver chip region may include an integrated circuit (abbreviated as IC), and the integrated circuit is configured to be connected to a plurality of data fan-out lines. The binding pin region may include a bonding pad, and the bonding pad is configured to be bonded and connected to an external flexible printed circuit (FPC, Flexible Printed Circuit, abbreviated as FPC). 【0050】 In an exemplary embodiment, the bezel region 300 may include a circuit region, a power line region, a crack dam region, and a cutting region that are sequentially installed along a direction away from the display region 100. The circuit region is connected to the display region 100 and may include at least a gate driving circuit. The gate driving circuit is connected to the first scanning line, the second scanning line, and the light emission control line of the pixel driving circuit in the display region 100. The power line region is connected to the circuit region and may include at least bezel power lead lines. The bezel power lead lines extend along a direction parallel to the edge of the display region and are connected to the cathode in the display region 100. The crack dam region is connected to the power line region and may include at least a plurality of cracks provided in the composite insulating layer. The cutting region is connected to the crack dam region and may include at least a cutting groove provided in the composite insulating layer. The cutting groove is configured such that after the preparation of all the film layers of the display substrate is completed, a cutting device cuts along the cutting groove respectively. 【0051】 In an exemplary embodiment, a first isolation dam and a second isolation dam may be provided in the fan-out region of the binding region 200 and the power line region of the bezel region 300. The first isolation dam and the second isolation dam may extend along a direction parallel to the edge of the display region, and may form an annular structure surrounding the display region 100. The edge of the display region is the edge on the side of the display region binding region or the bezel region. 【0052】 FIG. 3 is a schematic plan view of the display region of the display substrate. As shown in FIG. 3, the display substrate may include a plurality of pixel units P arranged in a matrix. At least one pixel unit P may include a first sub-pixel P1 that emits light of a first color, a second sub-pixel P2 that emits light of a second color, and a third sub-pixel P3 and a fourth sub-pixel P4 that emit light of a third color. Each sub-pixel may include a circuit unit, a pixel driving circuit, and a light-emitting device. The circuit unit may include at least a pixel driving circuit. The pixel driving circuit is respectively connected to a scanning signal line, a data signal line, and a light-emitting signal line. The pixel driving circuit is configured to receive a data voltage transmitted by the data signal line under the control of the scanning signal line and the light-emitting signal line, and output a current corresponding to the light-emitting device. The light-emitting device in each sub-pixel is respectively connected to the pixel driving circuit of the sub-pixel where it is located. The light-emitting device is configured to emit light of a corresponding luminance according to the current output by the pixel driving circuit of the sub-pixel where it is located. 【0053】 In an exemplary embodiment, the first sub-pixel P1 may be a red sub-pixel (R) that emits red light, the second sub-pixel P2 may be a blue sub-pixel (B) that emits blue light, and the third sub-pixel P3 and the fourth sub-pixel P4 may be green sub-pixels (G) that emit green light. In an exemplary embodiment, the shape of the sub-pixel may be rectangular, rhombic, pentagonal, or hexagonal. The four sub-pixels may be arranged in a diamond pattern to form an RGBG pixel arrangement. In other exemplary embodiments, the four sub-pixels may be arranged in a horizontal parallel, vertical parallel, or square pattern, etc., and the present disclosure is not limited here. 【0054】 In an exemplary embodiment, the pixel unit may include three sub-pixels, and the three sub-pixels may be arranged in a horizontal parallel, vertical parallel, or zigzag manner, etc., and the present disclosure is not limited herein. 【0055】 FIG. 4 is a schematic cross-sectional structure diagram of a display area of a display substrate, showing the structures of four sub-pixels in the display area. As shown in FIG. 4, in a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer 102 installed on a base 101, a light-emitting structure layer 103 installed on a side of the driving circuit layer 102 away from the base 101, and a package structure layer 104 installed on a side of the light-emitting structure layer 103 away from the base 101. In some possible embodiments, the display substrate may include other film layers such as a touch structure layer, etc., and the present disclosure is not limited herein. 【0056】 In an exemplary embodiment, the base 101 may be a flexible base or a rigid base. The driving circuit layer 102 of each sub-pixel may include a pixel driving circuit composed of a plurality of transistors and a storage capacitor. The light-emitting structure layer 103 of each sub-pixel may include at least an anode 301, a pixel definition layer 302, an organic light-emitting layer 303, and a cathode 304. The anode 301 is connected to the pixel driving circuit, the organic light-emitting layer 303 is connected to the anode 301, the cathode 304 is connected to the organic light-emitting layer 303, and the organic light-emitting layer 303 is driven by the anode 301 and the cathode 304 to emit light rays of a corresponding color. The package structure layer 104 may include a first package layer 401, a second package layer 402, and a third package layer 403 that are stacked and installed. The first package layer 401 and the third package layer 403 may adopt inorganic materials, the second package layer 402 may adopt organic materials, and the second package layer 402 is arranged between the first package layer 401 and the third package layer 403 to form an inorganic material / organic material / inorganic material stacked structure, which can ensure that water vapor from the outside does not penetrate into the light-emitting structure layer 103. 【0057】 In an exemplary embodiment, the organic light-emitting layer may include a light-emitting layer (EML) and any one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron blocking layer (EBL), a hole blocking layer (HBL), an electron transport layer (ETL), and an electron injection layer (EIL). In an exemplary embodiment, one or more of the hole injection layer, the hole transport layer, the electron blocking layer, the hole blocking layer, the electron transport layer, and the electron injection layer of all sub-pixels may be a common layer connected to each other, the light-emitting layers of adjacent sub-pixels may have overlapping portions, or may be isolated from each other. 【0058】 FIG. 5 is an equivalent circuit schematic diagram of a pixel driving circuit. In an exemplary embodiment, the pixel driving circuit may have a 3T1C, 4T1C, 5T1C, 5T2C, 6T1C, 7T1C, or 8T1C structure. FIG. 5 is an equivalent circuit schematic diagram of a pixel driving circuit. As shown in FIG. 5, the pixel driving circuit may include seven transistors (a first transistor T1 to a seventh transistor T7) and one storage capacitor C. The pixel driving circuit is connected to eight signal lines (a data signal line D, a first scanning signal line S1, a second scanning signal line S2, a light-emitting signal line E, a first initial signal line INIT1, a second initial signal line INIT2, a first power supply line VDD, and a second power supply line VSS), respectively. 【0059】 In an exemplary embodiment, the pixel driving circuit may include a first node N1, a second node N2, and a third node N3. The first node N1 is connected to the first pole of the third transistor T3, the second pole of the fourth transistor T4, and the second pole of the fifth transistor T5, respectively. The second node N2 is connected to the second pole of the first transistor, the first pole of the second transistor T2, the control pole of the third transistor T3, and the second end of the storage capacitor C, respectively. The third node N3 is connected to the second pole of the second transistor T2, the second pole of the third transistor T3, and the first pole of the sixth transistor T6, respectively. 【0060】 In an exemplary embodiment, the first end of the storage capacitor C is connected to the first power supply line VDD, and the second end of the storage capacitor C is connected to the second node N2, that is, the second end of the storage capacitor C is connected to the control pole of the third transistor T3. 【0061】 The control electrode of the first transistor T1 is connected to the second scanning signal line S2, the first electrode of the first transistor T1 is connected to the first initial signal line INIT1, and the second electrode of the first transistor is connected to the second node N2. When an on-level scanning signal is applied to the second scanning signal line S2, the first transistor T1 transmits a first initial voltage to the control electrode of the third transistor T3 to initialize the charge amount of the control electrode of the third transistor T3. 【0062】 The control electrode of the second transistor T2 is connected to the first scanning signal line S1, the first electrode of the second transistor T2 is connected to the second node N2, and the second electrode of the second transistor T2 is connected to the third node N3. When an on-level scanning signal is applied to the first scanning signal line S1, the second transistor T2 connects the control electrode and the second electrode of the third transistor T3. 【0063】 The control electrode of the third transistor T3 is connected to the second node N2, that is, the control electrode of the third transistor T3 is connected to the second terminal of the storage capacitor C. The first electrode of the third transistor T3 is connected to the first node N1, and the second electrode of the third transistor T3 is connected to the third node N3. The third transistor T3 may be called a driving transistor. The third transistor T3 determines the amount of driving current flowing between the first power supply line VDD and the second power supply line VSS based on the potential difference between the control electrode and the first electrode. 【0064】 The control electrode of the fourth transistor T4 is connected to the first scanning signal line S1, the first electrode of the fourth transistor T4 is connected to the data signal line D, and the second electrode of the fourth transistor T4 is connected to the first node N1. The fourth transistor T4 may be called a switching transistor, a scanning transistor, etc. When an on-level scanning signal is applied to the first scanning signal line S1, the fourth transistor T4 causes the data voltage of the data signal line D to be input to the pixel driving circuit. 【0065】 The control electrode of the fifth transistor T5 is connected to the light emission signal line E, the first electrode of the fifth transistor T5 is connected to the first power supply line VDD, and the second electrode of the fifth transistor T5 is connected to the first node N1. The control electrode of the sixth transistor T6 is connected to the light emission signal line E, the first electrode of the sixth transistor T6 is connected to the third node N3, and the second electrode of the sixth transistor T6 is connected to the first electrode of the light emitting device. The fifth transistor T5 and the sixth transistor T6 may be referred to as light emitting transistors. When an on-level light emission signal is applied to the light emission signal line E, the fifth transistor T5 and the sixth transistor T6 cause the light emitting device to emit light by forming a drive current path between the first power supply line VDD and the second power supply line VSS. 【0066】 The control electrode of the seventh transistor T7 is connected to the second scanning signal line S2, the first electrode of the seventh transistor T7 is connected to the second initial signal line INIT2, and the second electrode of the seventh transistor T7 is connected to the first electrode of the light emitting device. When an on-level scanning signal is applied to the second scanning signal line S2, the seventh transistor T7 transmits the second initial voltage to the first electrode of the light emitting device and initializes or discharges the amount of charge accumulated at the first electrode of the light emitting device. 【0067】 In an exemplary embodiment, the light emitting device is an OLED and may include a first electrode (anode) installed in a stacked manner, an organic light emitting layer, and a second electrode (cathode), or is a QLED and may include a first electrode (anode) installed in a stacked manner, a quantum dot light emitting layer, and a second electrode (cathode). 【0068】 In an exemplary embodiment, the second electrode of the light emitting device is connected to the second power supply line VSS, the signal of the second power supply line VSS is a low-level signal that is continuously supplied, and the signal of the first power supply line VDD is a high-level signal that is continuously supplied. 【0069】 In an exemplary embodiment, the first transistor T1 to the seventh transistor T7 may be P-type transistors or N-type transistors. By adopting transistors of the same type in the pixel driving circuit, the process flow can be simplified, the process difficulty of the display panel can be reduced, and the product yield can be improved. In some possible embodiments, the first transistor T1 to the seventh transistor T7 may include P-type transistors and N-type transistors. 【0070】 In an exemplary embodiment, for the first transistor T1 to the seventh transistor T7, a low-temperature poly-silicon thin-film transistor may be adopted, an oxide thin-film transistor may be adopted, or both a low-temperature poly-silicon thin-film transistor and an oxide thin-film transistor may be adopted. The active layer of the low-temperature poly-silicon thin-film transistor uses low-temperature poly-silicon (abbreviated as LTPS), and the active layer of the oxide thin-film transistor uses an oxide semiconductor (Oxide). The low-temperature poly-silicon thin-film transistor has advantages such as high mobility and fast charging, and the oxide thin-film transistor has advantages such as low leakage current. Integrating the low-temperature poly-silicon thin-film transistor and the oxide thin-film transistor on one display substrate, that is, an LTPS+Oxide (abbreviated as LTPO) display substrate, can utilize the advantages of both, achieve low-frequency driving, reduce power consumption, and improve display attributes. 【0071】 Taking the example that all of the first transistor T1 to the seventh transistor T7 are P-type transistors in an exemplary embodiment, the operation process of the pixel driving circuit may include the following steps. 【0072】 The first stage A1 is called the reset stage. The signal of the second scanning signal line S2 is a low-level signal, and the signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals. The signal of the second scanning signal line S2 is a low-level signal, turning on the first transistor T1 and the seventh transistor T7. By turning on the first transistor T1, the first initial voltage of the first initial signal line INIT1 is supplied to the second node N2, the storage capacitor C is initialized, and the original data voltage in the storage capacitor is cleared. By turning on the seventh transistor T7, the second initial voltage of the second initial signal line INIT2 is supplied to the first electrode of the OLED, initializing (resetting) the first electrode of the OLED, clearing the voltage previously stored therein to complete the initialization, and ensuring that the OLED does not emit light. The signals of the first scanning signal line S1 and the light-emitting signal line E are high-level signals, turning off the second transistor T2, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7. 【0073】 The second stage A2 is called the data writing stage or the threshold compensation stage. The signal on the first scanning signal line S1 is a low-level signal, the signals on the second scanning signal line S2 and the light emission signal line E are high-level signals, and the data signal line D outputs a data voltage. In this stage, since the second terminal of the memory capacitor C is at a low level, the third transistor T3 is turned on. The signal on the first scanning signal line S1 is a low-level signal, turning on the second transistor T2 and the fourth transistor T4. By turning on the second transistor T2 and the fourth transistor T4, the data voltage output from the data signal line D is supplied to the second node N2 through the first node N1, the turned-on third transistor T3, the third node N3, and the turned-on second transistor T2. The difference between the data voltage output from the data signal line D and the threshold voltage of the third transistor T3 is filled into the memory capacitor C, and the voltage of the second terminal (the second node N2) of the memory capacitor C is Vd - |Vth|, where Vd is the data voltage output by the data signal line D and Vth is the threshold voltage of the third transistor T3. The signal on the second scanning signal line S2 is a high-level signal, turning off the first transistor T1. The signal on the light emission signal line E is a high-level signal, turning off the fifth transistor T5 and the sixth transistor T6. 【0074】 The third stage A3 is called the light emission stage. The signal on the light emission signal line E is a low-level signal, and the signals on the first scanning signal line S1 and the second scanning signal line S2 are high-level signals. The signal on the light emission signal line E is a low-level signal, turning on the fifth transistor T5 and the sixth transistor T6. The power supply voltage output by the first power supply line VDD supplies a driving voltage to the first electrode of the OLED through the turned-on fifth transistor T5, the third transistor T3, and the sixth transistor T6 to drive the light emission of the OLED. 【0075】 In the driving process of the pixel driving circuit, the driving current flowing through the third transistor T3 (the driving transistor) is determined by the voltage difference between its gate electrode and the first electrode. Since the voltage of the second node N2 is Vd - |Vth|, the driving current of the third transistor T3 is given by the following formula. I = K * (Vgs - Vth) 2=K*[(Vdd - Vd + |Vth|) - Vth] 2 =K*[(Vdd - Vd] 2 【0076】 Here, I is the driving current flowing through the third transistor T3, that is, the driving current for driving the OLED. K is a constant. Vgs is the voltage difference between the gate electrode of the third transistor T3 and the first electrode. Vth is the threshold voltage of the third transistor T3. Vd is the data voltage output by the data signal line D. Vdd is the power supply voltage output by the first power supply line VDD. 【0077】 With the development of OLED display technology, consumers' requirements for the display effect of display products are becoming increasingly high. Since an extremely narrow bezel has become a new trend in the development of display products, bezel narrowing and thus bezel-less design are being increasingly emphasized in the design of OLED display products. On the display substrate, the binding area generally includes a fanout area, a bend area, a driver chip area, and a binding pin area that are sequentially provided along the direction away from the display area. Since the width of the binding area is smaller than that of the display area, the signal lines of the integrated circuit and the binding pads in the binding area need to be introduced into the wide display area in a fanout wiring manner through the fanout area. The greater the width difference between the display area and the binding area, and the more diagonal fanout lines in the fan-shaped area, the greater the distance between the driver chip area and the display area, resulting in a larger occupied space in the fan-shaped area, making it difficult to design a narrow lower bezel, and the lower bezel is maintained at about 2.0 mm. In other display substrates, usually, power supply lead lines are provided in the binding area and the bezel area, and the power supply lead lines are configured to transmit low-voltage power supply signals. To reduce the voltage drop of the low-voltage power supply signals, the width of the power supply lead lines increases, resulting in a wider bezel of the display device. 【0078】 Exemplary embodiments of the present disclosure provide a display substrate, adopting a structure in which data connection lines are located in a display area (abbreviated as Fanout in AA, FIAA), one end of a plurality of data connection lines is connected corresponding to a plurality of data signal lines in the display area, and the other end of the plurality of data connection lines extends to a binding area and is connected corresponding to an integrated circuit in the binding area. Since it is not necessary to provide fan-shaped hatching in the binding area, the width of the fanout area can be reduced, and the width of the lower bezel can be effectively reduced. 【0079】 Exemplary embodiments of the present disclosure provide a display substrate, including a display area, the display area including a driving circuit layer provided on a base and a light-emitting structure layer provided on a side of the driving circuit layer away from the base, the driving circuit layer including a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, a plurality of low-voltage power lines, and a plurality of power wirings, the light-emitting structure layer including a plurality of light-emitting devices, the circuit unit including a pixel driving circuit, the data signal line being configured to supply a data signal to the pixel driving circuit, the low-voltage power line being configured to continuously supply a low-power voltage signal to the light-emitting device, the data connection line being connected to the data signal line, and the power wiring being connected to the low-voltage power line. 【0080】 In an exemplary embodiment, the data connection line includes a first connection line extending along a first direction and a second connection line extending along a second direction, the power wiring includes a first power wiring extending along the first direction and a second power wiring extending along the second direction, the first connection line is connected to the second connection line, the first power wiring is connected to the second power wiring, and the first direction intersects the second direction. 【0081】 In an exemplary embodiment, in a plane parallel to the base, the display area includes at least a first area where the first connection line is provided, and in at least one circuit unit of the first area, the first connection line, the first power wiring, and the second power wiring are included, the first connection line is connected to the data signal line, and the second power wiring is connected to the low-voltage power line. 【0082】 In an exemplary embodiment, in a plane parallel to the base, the display region further includes a second region where the second connection line is provided, the second connection line is included in at least one circuit unit of the second region, and the second connection lines in the circuit units adjacent in the second direction are connected to each other. 【0083】 In an exemplary embodiment, in a plane parallel to the base, the display region further includes a third region that does not overlap with the orthographic projection of the first connection line and the second connection line on the base, the first power supply line and the second power supply line are included in at least one circuit unit of the third region, and the second power supply line is connected to the low-voltage power supply line through a second connection hole. 【0084】 In the present disclosure, that A extends along the B direction means that A may include a main part and a secondary part connected to the main part, the main part is a line, a line segment or a rod-shaped body, the main part extends along the B direction, and the length of the main part extending along the B direction is greater than the length of the secondary part extending along another direction. In the following description, "A extends along the B direction" always means that "the main body of A extends along the B direction". In an exemplary embodiment, the second direction Y may be a direction from the display region to the binding region, and the opposite direction of the second direction Y may be a direction from the binding region to the display region. 【0085】 FIG. 6 is a schematic plan view of a display substrate according to an exemplary embodiment of the present disclosure. In a plane perpendicular to the display substrate, the display substrate may include a driving circuit layer installed on a base, a light-emitting structure layer installed on a side away from the base of the driving circuit layer, and a package structure layer installed on a side away from the base of the light-emitting structure layer. As shown in FIG. 6, in a plane parallel to the display substrate, the display substrate may include at least a display area 100, a binding area 200 located on the Y side in the second direction of the display area 100, and a bezel area 300 located on the other side of the display area 100. In an exemplary embodiment, the driving circuit layer of the display area 100 may include a plurality of circuit units constituting a plurality of unit rows and a plurality of unit columns, at least one circuit unit may include a pixel driving circuit, and the pixel driving circuit is configured to output a current corresponding to a connected light-emitting device. The light-emitting structure layer of the display area 100 may include a plurality of sub-pixels constituting a pixel array, at least one sub-pixel may include a light-emitting device, the light-emitting device is connected to the pixel driving circuit of a corresponding circuit unit, and the light-emitting device is configured to emit light of a corresponding luminance in response to the current output by the connected pixel driving circuit. 【0086】 In an exemplary embodiment, the driving circuit layer of the display area 100 may further include a plurality of data signal lines 60 and a plurality of data connection lines 70. At least one data signal line 60 is connected to a plurality of pixel driving circuits within one unit row, the data signal line 60 is configured to supply a data signal to the connected pixel driving circuit, at least one data connection line 70 is connected corresponding to the data signal line 60, and the data connection line 70 is configured to connect the data signal line 60 to a lead-out line 210 within the binding area 200 via the data connection line 70. 【0087】 In an exemplary embodiment, the pixel unit described in the present disclosure means a region divided according to a light-emitting device, and the circuit unit described in the present disclosure means a region divided according to a pixel driving circuit. In an exemplary embodiment, the position of the orthographic projection of the sub-pixel on the base may correspond to the position of the orthographic projection of the circuit unit on the base, or the position of the orthographic projection of the sub-pixel on the base may not correspond to the position of the orthographic projection of the circuit unit on the base. 【0088】 In an exemplary embodiment, a plurality of circuit units sequentially arranged along the first direction X may be referred to as a unit row, and a plurality of circuit units sequentially arranged along the second direction Y may be referred to as a unit column. The plurality of unit rows and the plurality of unit columns constitute an array arrangement of circuit unit arrays, and the first direction X intersects the second direction Y. In an exemplary embodiment, the second direction Y may be the direction in which the data signal line extends (vertical direction), and the first direction X may be perpendicular to the second direction Y (horizontal direction). 【0089】 In an exemplary embodiment, the binding region 200 may include a lead wire region 201, a bend region, and a driver chip region that are sequentially arranged at least in a direction away from the display region. The lead wire region 201 is connected to the display region 100, the bend region is connected to the lead wire region 201, and the driver chip region is connected to the bend region. A plurality of lead-out wires 210 may be provided in the lead wire region 201. The plurality of lead-out wires 210 may extend along the second direction Y. The first ends of the plurality of lead-out wires 210 are connected to the integrated circuit in the composite circuit region, and the second ends of the plurality of lead-out wires 210 extend to the lead wire region 201 across the bend region and then are correspondingly connected to the data connection line 70. Thereby, the integrated circuit applies a data signal to the data signal line via the lead-out wire and the data connection line. Since the data connection line is provided in the display region, the length of the lead wire region in the second direction Y can be effectively shortened, the width of the lower bezel can be greatly shortened, the screen ratio can be improved, which is advantageous for realizing full-screen display. 【0090】 In an exemplary embodiment, the shape of the plurality of data signal lines provided in the display area 100 may be linear extending along the second direction Y, the shape of the plurality of data connection lines 70 provided in the display area 100 may be polygonal, and the data connection lines 70 may include a first connection line extending along the first direction X and a second connection line extending along the second direction Y. The first ends of the plurality of first connection lines (the first ends of the data connection lines 70) are connected to the plurality of data signal lines 60 correspondingly via connection holes, the second ends of the plurality of first connection lines are connected to the first ends of the second connection lines after extending along the first direction X or the opposite direction of the first direction X, and the second ends of the plurality of second connection lines (the second ends of the data connection lines 70) extend along the direction of the binding area 200 and cross the display area boundary B, and are connected to the plurality of lead lines 210 in the lead line area 201 correspondingly. In an exemplary embodiment, the display area boundary B may be the boundary between the display area 100 and the binding area 200. 【0091】 In an exemplary embodiment, the data connection lines 70 may be directly connected to the lead lines 210 or may be connected via vias, and the present disclosure is not limited here. 【0092】 In an exemplary embodiment, the plurality of second connection lines may be installed parallel to the data signal lines 60, and the plurality of first connection lines may be installed perpendicular to the data signal lines 60. 【0093】 In an exemplary embodiment, the intervals in the first direction X between adjacent second connection lines may be basically the same, and the intervals in the second direction Y between adjacent first connection lines may be basically the same, and the present disclosure is not limited here. 【0094】 In an exemplary embodiment, the display area 100 may have a center line O, and the plurality of data signal lines 60 and the plurality of data connection lines 70 in the display area 100 may be installed symmetrically with respect to the center line O and the plurality of lead lines 210 in the lead line area 201, and the center line O may be a straight line that equally divides the plurality of unit columns of the display area 100 and extends along the second direction Y. 【0095】 FIG. 7 is a schematic diagram of the arrangement of data connection lines of an exemplary embodiment of the present disclosure, which is an enlarged view of the C1 region in FIG. 6, showing the configuration of seven data signal lines, seven data connection lines, and seven lead-out lines. As shown in FIG. 7, in an exemplary embodiment, the plurality of data signal lines in the display area 100 may include the first data signal line 60-1 to the seventh data signal line 60-7, the plurality of data connection lines in the display area 100 may include the first data connection line 70-1 to the seventh data connection line 70-7, and the plurality of lead-out lines in the lead line area 201 may include the first lead-out line 210-1 to the seventh lead-out line 210-7. 【0096】 In an exemplary embodiment, the first data signal line 60-1 to the seventh data signal line 60-7, the first data connection line 70-1 to the seventh data connection line 70-7, and the first lead-out line 210-1 to the seventh lead-out line 210-7 may all be sequentially installed along the first direction X. The first end of the i-th data connection line 70-i is connected to the i-th data signal line 60-i through a connection hole in the display area 100, and the second end of the i-th data connection line 70-i extends to the lead line area 201 and is then connected to the i-th lead-out line 210-i, where i = 1 to 7. 【0097】 In an exemplary embodiment, the distances between the plurality of connection holes corresponding to connect the data connection line 70 and the data signal line 60 and the display area edge B may be different. For example, the distance between the connection hole connecting the first data connection line 70-1 and the first data signal line 60-1 and the display area edge B may be smaller than the distance between the connection hole connecting the second data connection line 70-2 and the second data signal line 60-2 and the display area edge B. Also, for example, the distance between the connection hole connecting the second data connection line 70-2 and the second data signal line 60-2 and the display area edge B may be larger than the distance between the connection hole connecting the third data connection line 70-3 and the third data signal line 60-3 and the display area edge B. 【0098】 FIG. 8 is a schematic plan view of another display substrate according to an exemplary embodiment of the present disclosure, and FIG. 9 is an enlarged view of the C2 region of FIG. 8. The driving circuit layer of the display region 100 may include a plurality of circuit units constituting a circuit unit array, a plurality of data signal lines 60, a plurality of data connection lines 70, and a power supply line 90 having a mesh communication structure. The layout and structure of the plurality of circuit units, the plurality of data signal lines 60, and the plurality of data connection lines 70 are basically the same as the layout and structure shown in FIG. 6 described above. 【0099】 In an exemplary embodiment, the data connection line 70 may include a first connection line 71 extending along the first direction X and a second connection line 72 extending along the second direction Y. The first connection line 71 and the second connection line 72 form a folded data connection line 70. The first connection line 71 and the second connection line 72 may be provided in the same conductive layer, and the first connection line 71 and the data signal line 60 may be provided in different conductive layers. The first end of the first connection line 71 is connected to the data signal line 60 through a first connection hole. The second end of the first connection line 71 extends along the first direction X or the opposite direction of the first direction X and is then directly connected to the first end of the second connection line 72. The second end of the second connection line 72 extends along the second direction Y and is then connected to the lead-out line 210. 【0100】 In an exemplary embodiment, the power supply line 90 may include a plurality of first power supply lines 91 extending along the first direction X and a plurality of second power supply lines 92 extending along the second direction Y. The plurality of first power supply lines 91 may be sequentially installed along the second direction Y, and the plurality of second power supply lines 92 may be sequentially installed along the first direction X. The first power supply line 91 and the second power supply line 92 are connected to each other to form a power supply line 90 having a mesh communication structure. The power supply line 90 is configured to be connected to a low-voltage power supply line in the driving circuit layer, and the low-voltage power supply line is configured to continuously supply a low-power voltage signal to a plurality of light-emitting devices in the light-emitting structure layer. 【0101】 In an exemplary embodiment, the first power supply wiring 91 and the second power supply wiring 92 may be provided in the same conductive layer, the first power supply wiring 91 and the low-voltage power supply line may be provided in different conductive layers, and the second power supply wiring may be connected to the low-voltage power supply line via the second connection hole, realizing the connection between the power supply wiring 90 of the mesh communication structure and the low-voltage power supply line. 【0102】 FIG. 10 is a region division schematic diagram of a display region of an exemplary embodiment of the present disclosure. As shown in FIG. 10, the data connection line is provided in a part of the display region, and since the data connection line includes a first connection line extending along the first direction X and a second connection line extending along the second direction Y, the display region can be divided into a first region 100A, a second region 100B, and a third region 100C based on the presence or absence of the data connection line and the extending direction of the data connection line. The first region 100A may be a region where the first connection line 71 is provided (fan-out line horizontal wiring region), and the second region 100B may be a region where the second connection line 72 is provided (fan-out line vertical wiring region). The third region 100C may be a region where the orthographic projections of the first connection line 71 and the second connection line 72 on the base do not overlap (normal region), that is, the third region 100C may be a region where the first connection line 71 and the second connection line 72 are not provided. 【0103】 In an exemplary embodiment, the first region 100A may include a plurality of circuit units, and the orthographic projection of the first connection line 71 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the plurality of circuit units of the first region 100A on the display substrate plane, and the orthographic projection of the pixel driving circuit in the plurality of circuit units of the first region 100A on the display substrate plane does not overlap with the orthographic projection of the second connection line 72 on the display substrate plane. 【0104】 In an exemplary embodiment, the second region 100B may include a plurality of circuit units, and the orthographic projection of the second connection line 72 on the display substrate plane at least partially overlaps with the orthographic projection of the pixel driving circuit in the plurality of circuit units of the second region 100B on the display substrate plane, and the orthographic projection of the pixel driving circuit in the plurality of circuit units of the second region 100B on the display substrate plane does not overlap with the orthographic projection of the first connection line 71 on the display substrate plane. 【0105】 In an exemplary embodiment, the third region 100C may include a plurality of circuit units, and the orthographic projection of the pixel driving circuit in the plurality of circuit units of the third region 100C on the display substrate plane does not overlap with the orthographic projections of the first connection line 71 and the second connection line 72 on the display substrate plane. 【0106】 In an exemplary embodiment, the division of each region shown in FIG. 10 is merely an exemplary illustration. Since the first region 100A, the second region 100B, and the third region 100C are divided based on the presence or absence of data connection lines and the extending direction of the data connection lines, the shapes of the three regions may be regular polygons or irregular polygons, and the display region may be divided into one or more first regions 100A, one or more second regions 100B, and one or more third regions 100C, and the present disclosure is not limited herein. 【0107】 FIG. 11a is a schematic structural diagram of the first region of an embodiment of the present disclosure, and the first region may include a plurality of circuit units. As shown in FIG. 11a, at least one circuit unit of the first region may include a data signal line 60, a first connection line 71, a second power line 80, a first power distribution line 91, a second power distribution line 92, a power connection electrode 93, and a second compensation line 120. The shapes of the first connection line 71 and the first power distribution line 91 may be linear with the main body extending along the first direction X, and the shapes of the data signal line 60, the second power line 80, the second power distribution line 92, and the second compensation line 120 may be linear with the main body extending along the second direction Y. The second power line 80 is configured to continuously supply a low power supply voltage signal (VSS) as the low voltage power line of the present disclosure, and the data signal line 60 is configured to supply a data signal. 【0108】 In an exemplary embodiment, in at least one circuit unit of the first region, the data signal line 60 and the second power supply line 92 may be disposed on the X side in the first direction of the second power supply line 80. The second power supply line 92 may be disposed between the second power supply line 80 and the data signal line 60. The second compensation line 120 may be disposed on the side of the second power supply line 80 away from the data signal line 60. The first power supply line 91 may be disposed on the Y side in the second direction of the circuit unit. The first connection line 71 may be disposed on the side opposite to the second direction Y of the circuit unit. 【0109】 In an exemplary embodiment, the first connection line 71 and the second connection line 72 may be provided in the same conductive layer, and the first connection line 71 and the data signal line 60 may be provided in different conductive layers. 【0110】 In an exemplary embodiment, in at least one circuit unit of the first region, the first connection line 71 extending along the first direction X is connected to the data signal line 60 extending along the second direction Y through the first connection hole K1, realizing the connection between the first connection line 71 and the data signal line 60. 【0111】 In an exemplary embodiment, in the first region, the first connection line 71 may be continuously disposed in a plurality of circuit units in one unit row, and the first connection lines 71 in the circuit units adjacent to each other in the first direction X are connected to each other. 【0112】 In an exemplary embodiment, the first power supply line 91 and the second power supply line 92 may be provided in the same conductive layer, and the second power supply line 92 and the second power supply line 80 may be provided in different conductive layers. 【0113】 In an exemplary embodiment, in at least one circuit unit of the first region, the second power supply line 92 extending along the second direction Y is connected to the second power supply line 80 extending along the second direction Y through the second connection hole K2, realizing the connection between the second power supply line 92 and the second power supply line 80. 【0114】 In an exemplary embodiment, in at least one unit row of the first region, a first power supply wiring 91 extending along a first direction X is directly connected to a plurality of second power supply wirings 92 extending along a second direction Y, constituting a power supply wiring of a mesh communication structure. 【0115】 In an exemplary embodiment, at least one circuit unit in the first region may further include a power connection electrode 93. The shape of the power connection electrode 93 may be rectangular. The power connection electrode 93 may be installed on a side away from the data signal line 60 of the second power supply wiring 92 and may be connected to the second power supply wiring 92. The orthographic projection of the power connection electrode 93 at the base overlaps at least partially with the orthographic projection of the second power supply line 80 at the base. Since the power connection electrode 93 is connected to the second power supply line 80 through a second connection hole K2, the connection between the mesh-shaped power lead wire and the second power supply line 80 is realized. 【0116】 In an exemplary embodiment, in the first region, the first power supply wiring 91 may be continuously installed in a plurality of circuit units in one unit row, and the first power supply wirings 91 in circuit units adjacent in the first direction X are connected to each other. 【0117】 In an exemplary embodiment, in the first region, the second power supply wiring 92 may be installed at intervals in a plurality of circuit units in one unit column. That is, the second power supply wirings 92 in circuit units adjacent in the second direction Y are installed at intervals. Thereby, the first connection line 71 is installed between the second power supply wirings 92 adjacent in the second direction Y, and the orthographic projection of the first connection line 71 at the base does not overlap with the orthographic projection of the second power supply wiring 92 at the base. 【0118】 In an exemplary embodiment, in the first region, a first power supply wiring 91 extending along a first direction X is directly connected to a plurality of second compensation lines 120 extending along a second direction Y. 【0119】 In an exemplary embodiment, in the first region, the second compensation line 120 may be installed at intervals in a plurality of circuit units of one unit row, that is, the second compensation lines 120 in the circuit units adjacent in the second direction Y are installed at intervals. Thereby, the first connection line 71 is installed between the second compensation lines 120 adjacent in the second direction Y, and the orthographic projection of the first connection line 71 on the base overlaps the orthographic projection of the second compensation line 120 on the base. 【0120】 FIG. 11b is a schematic structural diagram of the second region of an embodiment of the present disclosure, and the second region may include a plurality of circuit units. As shown in FIG. 11b, at least one circuit unit in the second region may include a data signal line 60, a second connection line 72, a second power supply line 80, and a first compensation line 110. The shape of the first compensation line 110 may be linear with the main body extending along the first direction X, and the shapes of the data signal line 60, the second connection line 72, and the second power supply line 80 may be linear with the main body extending along the second direction Y. The first end of the second connection line 72 is connected to a lead wire located in the lead wire region, and the second end of the second connection line 72 is connected to the first connection line 71 located in the display region. Thereby, the first connection line 71 and the second connection line 72 connected to each other constitute a broken-line data connection line. 【0121】 In an exemplary embodiment, two second connection lines 72 may be provided in at least one circuit unit in the second region. The two second connection lines 72 may include a first side connection line and a second side connection line. The first side connection line may be provided between the second power supply line 80 and the data signal line 60, and the second side connection line may be provided on the side of the second power supply line 80 away from the data signal line 60. 【0122】 In an exemplary embodiment, at least two first compensation lines 110 may be provided in at least one circuit unit of the second region. The at least two first compensation lines 110 may include at least one first side compensation line and at least one second side compensation line. The first end of the first side compensation line is connected to the first side connection line, the second end of the first side compensation line extends along a direction close to the second side connection line, the first end of the second side compensation line is connected to the second side connection line, and the second end of the second side compensation line extends along a direction close to the first side connection line. Thus, the two first compensation lines 110 in the circuit unit form an interdigitated structure. 【0123】 In an exemplary embodiment, at least one circuit unit in the second region may further include a dummy connection electrode 73. The shape of the dummy connection electrode 73 may be rectangular. The dummy connection electrode 73 is installed on the side away from the data signal line 60 of the second connection line 72 and may be connected to the second connection line 72. The orthographic projection of the dummy connection electrode 73 at the base at least partially overlaps with the orthographic projection of the second power line 80 at the base. 【0124】 In an exemplary embodiment, in the second region, the second connection line 72 may be continuously installed in a plurality of circuit units of one unit row, and the second connection lines 72 in the circuit units adjacent in the second direction Y are connected to each other. 【0125】 In an exemplary embodiment, in the second region, the first compensation lines 110 may be installed at intervals in a plurality of circuit units of one unit row. 【0126】 FIG. 11c is a schematic structural diagram of a third region of an embodiment of the present disclosure, and the third region may include a plurality of circuit units. As shown in FIG. 11c, at least one circuit unit in the third region may include a data signal line 60, a second power line 80, a first power wiring 91, a second power wiring 92, a power connection electrode 93, a first compensation line 110, and a second compensation line 120. The shapes of the first power wiring 91 and the first compensation line 110 may be linear with the main body extending along the first direction X, and the shapes of the data signal line 60, the second power line 80, the second power wiring 92, and the second compensation line 120 may be linear with the main body extending along the second direction Y. 【0127】 In an exemplary embodiment, in at least one circuit unit of the third region, the data signal line 60 may be provided on the first direction X side of the second power line 80, the second power wiring 92 may be provided between the second power line 80 and the data signal line 60, the second compensation line 120 may be provided on the side of the second power line 80 away from the data signal line 60, the first power wiring 91 may be provided on the second direction Y side of the circuit unit, and the first compensation line 110 may be provided on the side opposite to the second direction Y of the circuit unit. 【0128】 In an exemplary embodiment, in at least one circuit unit of the third region, the second power wiring 92 extending along the second direction Y is connected to the second power line 80 extending along the second direction Y through the second connection hole K2 to realize the connection between the second power wiring 92 and the second power line 80. 【0129】 In an exemplary embodiment, the first power wiring 91 and the second power wiring 92 may be installed in the same conductive layer. In at least one unit row of the third region, the first power wiring 91 extending along the first direction X is directly connected to a plurality of second power wirings 92 extending along the second direction Y to form a power wiring with a mesh communication structure. 【0130】 In an exemplary embodiment, in the third region, the first power wiring 91 may be continuously installed in a plurality of circuit units of one unit row, and the first power wirings 91 in the circuit units adjacent in the first direction X are connected to each other. 【0131】 In an exemplary embodiment, in the first region, the second power supply wiring 92 may be continuously installed in a plurality of circuit units of one unit row, and the second power supply wirings 92 in the circuit units adjacent in the second direction Y are connected to each other. 【0132】 In an exemplary embodiment, at least one circuit unit in the third region may further include a power connection electrode 93. The shape of the power connection electrode 93 may be rectangular. The power connection electrode 93 may be installed on the side away from the data signal line 60 of the second power supply wiring 92 and may be connected to the second power supply wiring 92. The orthographic projection of the power connection electrode 93 at the base at least partially overlaps with the orthographic projection of the second power supply line 80 at the base. Since the power connection electrode 93 is connected to the second power supply line 80 through the second connection hole K2, the connection between the mesh-shaped power lead wire and the second power supply line 80 is realized. 【0133】 In an exemplary embodiment, in the third region, the first compensation line 110 may be continuously installed in a plurality of circuit units of one unit row, and the first compensation lines 110 in the circuit units adjacent in the first direction X are connected to each other. 【0134】 In an exemplary embodiment, in the third region, the second compensation line 120 may be continuously installed in a plurality of circuit units of one unit row, and the second compensation lines 120 in the circuit units adjacent in the second direction Y are connected to each other. 【0135】 In an exemplary embodiment, the first power supply wiring 91, the second power supply wiring 92, the first compensation line 110, and the second compensation line 120 may be provided in the same conductive layer. 【0136】 In an exemplary embodiment, in at least one unit row of the third region, the first power supply wiring 91 extending along the first direction X is directly connected to a plurality of second compensation lines 120 extending along the second direction Y. 【0137】 In an exemplary embodiment, in at least one unit row of the third region, a second power supply wiring 92 extending along the second direction Y is directly connected to a plurality of first compensation lines 110 extending along the first direction X. 【0138】 In an exemplary embodiment, in at least one circuit unit of the third region, a first power supply wiring 91 and a first compensation line 110 extending along the first direction X are connected to a second power supply wiring 92 and a second compensation line 120 extending along the second direction Y, forming a "well" shaped structure. 【0139】 In an exemplary embodiment, in at least one unit row including the circuit unit in the first region, the circuit unit in the second region, and the circuit unit in the third region, the first power supply wiring 91 in the first region, the first side compensation line in the first compensation line 110 in the second region, and the first power supply wiring 91 in the third region may be located on the same straight line extending along the first direction X. The first connection line 71 in the first region, the second side compensation line in the first compensation line 110 in the second region, and the first compensation line 110 in the third region may be located on the same straight line extending along the first direction X. The power supply connection electrode 93 in the first region, the dummy connection electrode 73 in the second region, and the power supply connection electrode 93 in the third region may be located on the same straight line extending along the first direction X. In at least one unit column including the circuit unit in the first region, the circuit unit in the second region, and the circuit unit in the third region, the second power supply wiring 92 in the first region, the first side connection line in the second connection line 72 in the second region, and the second power supply wiring 92 in the third region may be located on the same straight line extending along the second direction Y. The second compensation line 120 in the first region, the second side compensation line in the second connection line 72 in the second region, and the second compensation line 120 in the third region may be located on the same straight line extending along the second direction Y. The power supply connection electrode 93 in the first region, the dummy connection electrode 73 in the second region, and the power supply connection electrode 93 in the third region may be located on the same straight line extending along the second direction. Therefore, the wirings in the first region, the second region, and the third region basically exhibit a similar form, which not only improves the uniformity of the manufacturing process, but also can obtain basically the same display effect in transmitted light and reflected light in different regions, effectively avoiding appearance defects of the display substrate and improving the display attributes and display quality. 【0140】 In an exemplary embodiment, in a plane perpendicular to the display substrate, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer, and a fifth conductive layer that are sequentially provided on a base. The semiconductor layer includes at least the active layers of a plurality of transistors, the first conductive layer includes at least the gate electrodes of a plurality of transistors and the first electrode plate of a storage capacitor, the second conductive layer includes at least the second electrode plate of the storage capacitor, the third conductive layer includes at least the first and second electrodes of a plurality of transistors, the fourth conductive layer includes at least a data signal line 60 and a second power supply line 80, and the fifth conductive layer includes at least a first connection line 71, a second connection line 72, a first power supply wiring 91, and a second power supply wiring 92. The first connection line 71 and the second connection line 72 are an integral structure connected to each other. The first connection line 71 is connected to the data signal line 60 through a first connection hole. The first power supply wiring 91 and the second power supply wiring 92 are an integral structure connected to each other. The second power supply wiring 92 is connected to the second power supply line 80 through a second connection hole. 【0141】 In an exemplary embodiment, the driving circuit layer may include at least a first insulating layer, a second insulating layer, a third insulating layer, a fourth insulating layer, a first planarizing layer, a second planarizing layer, and a third planarizing layer. The first insulating layer is provided between the base and the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first conductive layer. The third insulating layer is provided between the first conductive layer and the second conductive layer. The fourth insulating layer is provided between the second conductive layer and the third conductive layer. The first planarizing layer is provided between the third conductive layer and the fourth conductive layer. The second planarizing layer is provided between the fourth conductive layer and the fifth conductive layer. The third planarizing layer is provided on the side away from the base of the fifth conductive layer. 【0142】 Hereinafter, an exemplary description will be given through the manufacturing process of a display substrate. The "patterning process" as used in the present disclosure, for metal materials, inorganic materials, or transparent conductive materials, includes processes such as photoresist coating, mask exposure, development, etching, and photoresist stripping, and for organic materials, includes processes such as organic material coating, mask exposure, and development. Deposition can be any one or more of sputtering, evaporation, and chemical vapor deposition, coating can be any one or more of spraying, spin coating, and inkjet printing, and etching can be any one or more of dry etching and wet etching, and the present disclosure is not limited thereto. The "thin film" refers to a thin film formed by depositing, coating, or other methods of a certain material on a base substrate. If the "thin film" does not require a patterning process throughout the manufacturing process, the "thin film" can also be called a "layer". If the patterning process is required for the "thin film" throughout the manufacturing process, it is called a "thin film" before the patterning process and a "layer" after the patterning process. The "layer" after the patterning process includes at least one "pattern". The statement "A and B are provided in the same layer" as used in the present disclosure means that they are formed simultaneously by the same patterning process. The "thickness" of the film layer is the size in the direction perpendicular to the display substrate of the film layer. In the exemplary embodiments of the present disclosure, the statement "the orthographic projection of B is located within the range of the orthographic projection of A", or "the orthographic projection of A includes the orthographic projection of B" refers to that the boundary of the orthographic projection of B is within the boundary range of the orthographic projection of A, or the boundary of the orthographic projection of A overlaps with the boundary of the orthographic projection of B. 【0143】 In an exemplary embodiment, taking eight circuit units (two unit rows, four unit columns) as an example, the manufacturing process of the display substrate may include the following operations. 【0144】 (1) A semiconductor layer pattern is formed. In an exemplary embodiment, as shown in FIG. 12, forming a semiconductor layer pattern may include sequentially depositing a first insulating thin film and a semiconductor thin film on a base, patterning the semiconductor thin film by a patterning process, and forming a first insulating layer covering the base and a semiconductor layer provided on the first insulating layer. FIG. 12 is an enlarged view of the E0 region of FIG. 10. 【0145】 In an exemplary embodiment, the semiconductor layer of each circuit unit in the display region may include at least the first active layer 11 of the first transistor T1 to the seventh active layer 17 of the seventh transistor T7. The first active layer 11 to the sixth active layer 16 are an integrated structure connected to each other, and the sixth active layer 16 and the seventh active layer 17 of adjacent circuit units in each unit row are an integrated structure connected to each other. For example, the sixth active layer 16 of the circuit unit in the Mth row of each unit row is connected to the seventh active layer 17 of the circuit unit in the M + 1th row. 【0146】 In an exemplary embodiment, the first active layer 11, the second active layer 12, the fourth active layer 14, and the seventh active layer 17 in the circuit unit of the Mth row may be located on the side away from the circuit unit of the (M + 1)th row of the third active layer 13 of this circuit unit. The first active layer 11 and the seventh active layer 17 may be located on the side away from the third active layer 13 of the second active layer 12 and the fourth active layer 14. The fifth active layer 15 and the sixth active layer 16 in the circuit unit of the Mth row may be located on the side close to the circuit unit of the (M + 1)th row of the third active layer 13. 【0147】 In an exemplary embodiment, the shape of the first active layer 11 may be in an "n" shape, the shapes of the second active layer 12, the fifth active layer 15, and the sixth active layer 16 may be in an "L" shape, the shape of the third active layer 13 may be in an "Ω" shape, and the shapes of the fourth active layer 14 and the seventh active layer 17 may be in an "I" shape. 【0148】 In an exemplary embodiment, the active layer of each transistor may include a first region, a second region, and a channel region located between the first region and the second region. 【0149】 The first region 11-1 of the first active layer 11, the first region 14-1 of the fourth active layer 14, the first region 15-1 of the fifth active layer 15, and the first region 17-1 of the seventh active layer 17 may be provided individually. The second region 11-2 of the first active layer 11 may be used as the first region 12-1 (the second node N2) of the second active layer 12. The first region 13-1 of the third active layer 13 may be simultaneously used as the second region 14-2 of the fourth active layer 14 and the second region 15-2 (the first node N1) of the fifth active layer 15. The second region 13-2 of the third active layer 13 may be simultaneously used as the second region 12-2 of the second active layer 12 and the first region 16-1 (the third node N3) of the sixth active layer 16. The second region 12-2 of the sixth active layer 16 may be simultaneously used as the second region 17-2 of the seventh active layer 17. 【0150】 In an exemplary embodiment, the semiconductor patterns in the E1 region and the E2 region of FIG. 10 are basically the same as the semiconductor pattern in the E0 region. 【0151】 (2) Form the first conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 13a and 13b, forming the first conductive layer pattern may include sequentially depositing a second insulating thin film and a first conductive thin film on the base on which the pattern is formed, patterning the first conductive thin film by a patterning process, forming a second insulating layer covering the semiconductor layer pattern, and forming a first conductive layer pattern provided on the second insulating layer. FIG. 13a is an enlarged view of the E0 region of FIG. 10, and FIG. 13b is a plan schematic view of the first conductive layer in FIG. 13a. In an exemplary embodiment, the first conductive layer may be referred to as a first gate metal (GATE1) layer. 【0152】 In an exemplary embodiment, the first conductive layer pattern of each circuit unit in the display region includes at least a first scanning signal line 21, a second scanning signal line 22, a light emission control line 23, and a first electrode plate 24 of a memory capacitor. 【0153】 In an exemplary embodiment, the shape of the first electrode plate 24 of the memory capacitor may be rectangular, and chamfers may be provided at the corners of the rectangle. There is a region where the orthographic projection of the first electrode plate 24 on the base overlaps with the orthographic projection of the base of the third active layer of the third transistor T3. In an exemplary embodiment, the first electrode plate 24 may be simultaneously used as one electrode plate of the memory capacitor and the gate electrode of the third transistor T3. 【0154】 In an exemplary embodiment, the shapes of the first scanning signal line 21, the second scanning signal line 22, and the light emission control line 23 may be linear with the main body portions extending along the first direction X. The first scanning signal line 21 and the second scanning signal line 22 in the circuit unit of the M-th row may be located on the side away from the circuit unit of the (M + 1)-th row of the first electrode plate 24 of this circuit unit. The second scanning signal line 22 may be located on the side away from the first electrode plate 24 of the first scanning signal line 21 of this circuit unit. The light emission control line 23 may be located on the side close to the circuit unit of the (M + 1)-th row of the first electrode plate 24 of this circuit unit. 【0155】 In an exemplary embodiment, a gate block 21-1 protruding toward the second scanning signal line 22 side is provided on the first scanning signal line 21. The region where the first scanning signal line 21 and the gate block 21-1 overlap with the second active layer may be used as the gate electrode of the second transistor T2, and the second transistor T2 with a dual-gate structure may be formed. 【0156】 In an exemplary embodiment, the region where the first scanning signal line 21 overlaps with the fourth active layer 14 serves as the gate electrode of the fourth transistor T4. The region where the second scanning signal line 22 overlaps with the first active layer may be used as the gate electrode of the first transistor T1 with a dual-gate structure, and the region where the second scanning signal line 22 overlaps with the seventh active layer 17 serves as the gate electrode of the seventh transistor T7. The region where the light emission control line 23 overlaps with the fifth active layer 15 serves as the gate electrode of the fifth transistor T5, and the region where the light emission control line 23 overlaps with the sixth active layer 16 serves as the gate electrode of the sixth transistor T6. 【0157】 In an exemplary embodiment, the first conductive layer patterns in the E1 region and the E2 region of FIG. 10 are basically the same as the first conductive layer pattern in the E0 region. 【0158】 In an exemplary embodiment, after forming the first conductive layer pattern, the semiconductor layer is made conductive using the first conductive layer as a shield, and the semiconductor layer in the region shielded by the first conductive layer forms the channel regions of the first transistor T1 to the seventh transistor T7, and the semiconductor layer in the region not shielded by the first conductive layer is made conductive, that is, both the first region and the second region of the first active layer to the seventh active layer are made conductive. 【0159】 (3) Form a second conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 14a and 14b, forming the second conductive layer pattern may include sequentially depositing a third insulating thin film and a second conductive thin film on the base on which the pattern is formed, patterning the second conductive thin film by a patterning process, and forming a third insulating layer covering the first conductive layer and a second conductive layer pattern provided on the third insulating layer. FIG. 14a is an enlarged view of the E0 region of FIG. 10, and FIG. 14b is a planar schematic diagram of the second conductive layer of FIG. 14a. In an exemplary embodiment, the second conductive layer may be referred to as a second gate metal (GATE2) layer. 【0160】 In an exemplary embodiment, the second conductive layer patterns of each circuit unit in the display region include at least a first initial signal line 31, a second initial signal line 32, a second electrode plate 33, an electrode plate connection line 34, and a shield electrode 35. 【0161】 In an exemplary embodiment, the shapes of the first initial signal line 31 and the second initial signal line 32 may be linear with the main body extending along the first direction X. The first initial signal line 31 in the circuit unit of the Mth row may be located on the side away from the first scanning signal line 21 of the second scanning signal line 22 of this circuit unit, and the second initial signal line 32 may be located between the first scanning signal line 21 and the second scanning signal line 22 of this circuit unit. 【0162】 In an exemplary embodiment, the contour shape of the second electrode plate 33 may be rectangular, and chamfers may be provided at the corners of the rectangle. There is a region where the orthographic projection of the second electrode plate 33 on the base overlaps with the orthographic projection of the first electrode plate 24 on the base. The second electrode plate 33 serves as the other electrode plate of the storage capacitor, is located between the first scanning signal line 21 and the light emission control line 24 of the present circuit unit, and the first electrode plate 24 and the second electrode plate 33 constitute the storage capacitor of the pixel driving circuit. 【0163】 In an exemplary embodiment, the electrode plate connection line 34 may be provided on one side of the second electrode plate 33 on the X side of the first direction or on the side opposite to the first direction X. The first end of the electrode plate connection line 34 is connected to the second electrode plate 33 of the present circuit unit. After the second end of the electrode plate connection line 34 extends along the first direction X or the direction opposite to the first direction X, it is connected to the second electrode plate 33 of the adjacent circuit unit, and the second electrode plates 33 of the adjacent circuit units in one unit row are connected to each other. In an exemplary embodiment, the second electrode plates of a plurality of circuit units in one unit row can be formed into an integrated structure connected to each other by the electrode plate connection line. The second electrode plate of the integrated structure can be multiplexed as a power signal connection line, which ensures that the plurality of second electrode plates in one unit row have the same potential, is advantageous for improving the uniformity of the panel, can avoid display defects of the display substrate, and can ensure the display effect of the display substrate. 【0164】 In an exemplary embodiment, an opening 36 is provided in the second electrode plate 33, and the opening 36 may be located in the middle of the second electrode plate 33. The opening 36 may be rectangular, forming an annular structure for the second electrode plate 33. The opening 36 exposes the third insulating layer covering the first electrode plate 24, and the orthographic projection of the first electrode plate 24 on the base includes the orthographic projection of the opening 36 on the base. In an exemplary embodiment, the opening 36 is configured to accommodate a first via formed later. The first via is located within the opening 36 to expose the first electrode plate 24, and the second pole of the first transistor T1 formed later is connected to the first electrode plate 24. 【0165】 In an exemplary embodiment, the shield electrode 35 may be disposed between the first scanning signal line 21 and the second initial signal line 32 of the present circuit unit, and the shield electrode 35 is configured to be connected to a first power line formed later. The orthographic projection of the shield electrode 35 at the base overlaps at least partially with the orthographic projections of the second region of the first active layer and the first region of the second active layer at the base. The shield electrode 35 is configured to shield the influence on the key node caused by the data voltage jump, avoid the influence on the potential of the key node of the pixel driving circuit caused by the data voltage jump, and improve the display effect. 【0166】 In an exemplary embodiment, the second conductive layer patterns in the E1 region and the E2 region of FIG. 10 are basically the same as the second conductive layer in the E0 region. 【0167】 (4) Form a fourth insulating layer pattern. In an exemplary embodiment, as shown in FIG. 15, forming the fourth insulating layer pattern includes depositing a fourth insulating thin film on the base on which the pattern is formed, patterning the fourth insulating thin film by a patterning process, forming a fourth insulating layer covering the second conductive layer, and a plurality of vias may be provided in each circuit unit. FIG. 15 is an enlarged view of the E0 region of FIG. 10. 【0168】 In an exemplary embodiment, the plurality of vias in each circuit unit in the display region include at least the first via V1, the second via V2, the third via V3, the fourth via V4, the fifth via V5, the sixth via V6, the seventh via V7, the eighth via V8, the ninth via V9, the tenth via V10, and the eleventh via V11. 【0169】 In an exemplary embodiment, the orthographic projection of the first via V1 at the base is located within the range of the orthographic projection of the opening 36 of the second electrode plate 33 at the base. The fourth insulating layer and the third insulating layer in the first via V1 are removed by etching to expose the surface of the first electrode plate 24. The first via V1 is configured to connect the second pole of the first transistor T1 formed later to the first electrode plate 24 through the via. 【0170】 In an exemplary embodiment, the orthographic projection of the second via V2 at its base is located within the range of the orthographic projection of the base of the second electrode plate 33. The fourth insulating layer within the second via V2 is removed by etching to expose the surface of the second electrode plate 33. The second via V2 is configured such that a subsequently formed first power line is connected to the second electrode plate 33 through the via. In an exemplary embodiment, there may be a plurality of second vias V2 serving as power vias, and the plurality of second vias V2 may be sequentially arranged along the second direction Y to enhance the connection reliability between the first power line and the second electrode plate 33. 【0171】 In an exemplary embodiment, the orthographic projection of the third via V3 at its base is located within the range of the orthographic projection of the base of the first region of the fifth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the third via V3 are removed by etching to expose the surface of the first region of the fifth active layer. The third via V3 is configured such that a subsequently formed first power line is connected to the first region of the fifth active layer through the via. 【0172】 In an exemplary embodiment, the orthographic projection of the fourth via V4 at its base is located within the range of the orthographic projection of the base of the second region of the sixth active layer (which is also the second region of the seventh active layer). The fourth insulating layer, the third insulating layer, and the second insulating layer within the fourth via V4 are removed by etching to expose the surface of the second region of the sixth active layer. The fourth via V4 is configured such that the second pole of the subsequently formed sixth transistor T6 (which is also the second pole of the seventh transistor T7) is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) through the via. 【0173】 In an exemplary embodiment, the orthographic projection of the fifth via V5 at its base is located within the range of the orthographic projection of the base of the first region of the fourth active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the fifth via V5 are removed by etching to expose the surface of the first region of the fourth active layer. The fifth via V5 is configured such that the first pole of the subsequently formed fourth transistor T4 is connected to the first region of the fourth active layer through the via. 【0174】 In an exemplary embodiment, the orthographic projection at the base of the sixth via V6 is located within the range of the orthographic projection at the base of the second region of the first active layer (which is also the first region of the second active layer). The fourth insulating layer, the third insulating layer, and the second insulating layer within the sixth via V6 are removed by etching to expose the surface of the second region of the first active layer. The sixth via V6 is configured to connect the second pole of the first transistor T1 (which is also the first pole of the second transistor T2) formed later to the second region of the first active layer (which is also the first region of the second active layer) through the via. 【0175】 In an exemplary embodiment, the orthographic projection at the base of the seventh via V7 is located within the range of the orthographic projection at the base of the first region of the seventh active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the seventh via V7 are removed by etching to expose the surface of the first region of the seventh active layer. The seventh via V7 is configured to connect the first pole of the seventh transistor T7 formed later to the first region of the seventh active layer through the via. 【0176】 In an exemplary embodiment, the orthographic projection at the base of the eighth via V8 is located within the range of the orthographic projection at the base of the first region of the first active layer. The fourth insulating layer, the third insulating layer, and the second insulating layer within the eighth via V8 are removed by etching to expose the surface of the first region of the first active layer. The eighth via V8 is configured to connect the first pole of the first transistor T1 formed later to the first region of the first active layer through the via. 【0177】 In an exemplary embodiment, the orthographic projection at the base of the ninth via V9 is located within the range of the orthographic projection at the base of the first initial signal line 31. The fourth insulating layer within the ninth via V9 is removed by etching to expose the surface of the first initial signal line 31. The ninth via V9 is configured to connect the first pole of the first transistor T1 formed later to the first initial signal line 31 through the via. 【0178】 In an exemplary embodiment, the orthographic projection at the base of the tenth via V10 is located within the range of the orthographic projection at the base of the second initial signal line 32. The fourth insulating layer within the tenth via V10 is removed by etching to expose the surface of the second initial signal line 32. The tenth via V10 is configured to connect the first pole of the seventh transistor T7 to be formed later to the second initial signal line 32 through the via. 【0179】 In an exemplary embodiment, the orthographic projection at the base of the eleventh via V11 is located within the range of the orthographic projection at the base of the shield electrode 35. The fourth insulating layer within the eleventh via V11 is removed by etching to expose the surface of the shield electrode 35. The eleventh via V11 is configured to connect the first pole of the first transistor T1 to be formed later to the shield electrode 35 through the via. The first power line to be formed later... 【0180】 In an exemplary embodiment, the via patterns in the E1 region and the E2 region in FIG. 10 are basically the same as the via pattern in the E0 region. 【0181】 (5) Form a third conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 16a and 16b, forming the third conductive layer may include depositing a third conductive thin film on the base where the pattern is formed and patterning the third conductive thin film by a patterning process to form the third conductive layer provided on the fourth insulating layer. FIG. 16a is an enlarged view of the E0 region in FIG. 10, and FIG. 16b is a schematic plan view of the third conductive layer in FIG. 16a. In an exemplary embodiment, the third conductive layer may be referred to as the first source / drain metal (SD1) layer. 【0182】 In an exemplary embodiment, the third conductive layer pattern of a plurality of circuit units in the display region may include a first connection electrode 41, a second connection electrode 42, a third connection electrode 43, a fourth connection electrode 44, a fifth connection electrode 45, a first power line 46, and an initial connection line 47. 【0183】 In an exemplary embodiment, the shape of the first connection electrode 41 may be a stripe extending along the second direction Y. The first end of the first connection electrode 41 is connected to the first electrode plate 24 via the first via V1, and the second end of the first connection electrode 41 is connected to the second region of the first active layer (which is also the first region of the second active layer) via the sixth via V6. In an exemplary embodiment, the first connection electrode 41 may be the second pole of the first transistor T1 and the first pole of the second transistor T2. Thus, the first electrode plate 24, the second pole of the first transistor T1, and the first pole of the second transistor T2 have the same potential (the second node N2). 【0184】 In an exemplary embodiment, the shape of the second connection electrode 42 may be rectangular, and the fourth connection electrode 44 is connected to the first region of the fourth active layer via the fifth via V5. In an exemplary embodiment, the fourth connection electrode 44 may be the first pole of the fourth transistor T4, and the fourth connection electrode 44 is configured to be connected to a data signal line formed later. 【0185】 In an exemplary embodiment, the shape of the third connection electrode 43 may be rectangular, and the third connection electrode 43 is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the fourth via V4. In an exemplary embodiment, the third connection electrode 43 may be the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7. Thus, the second pole of the sixth transistor T6 and the second pole of the seventh transistor T7 have the same potential, and the third connection electrode 43 is configured to be connected to a first anode connection electrode formed later. 【0186】 In an exemplary embodiment, the shape of the fourth connection electrode 44 may be a stripe with a main body extending along the second direction Y. The first end of the fourth connection electrode 44 is connected to the first region of the seventh active layer via the seventh via V7, and the second end of the fourth connection electrode 44 is connected to the second initial signal line 32 via the tenth via V10. In an exemplary embodiment, the fourth connection electrode 44 may be the first pole of the seventh transistor T7, and the second initial signal line 32 realizes writing the second initial signal to the seventh transistor T7. 【0187】 In an exemplary embodiment, the shape of the fifth connection electrode 45 may be a polyline shape. The first end of the fifth connection electrode 45 is connected to the first region of the first active layer via the eighth via V8, and the second end of the fifth connection electrode 45 is connected to the first initial signal line 31 via the ninth via V9. Since the fifth connection electrode 45 may also be the first pole of the first transistor T1, it is realized that the first initial signal line 31 writes the first initial signal to the first pole of the first transistor T1. 【0188】 In an exemplary embodiment, the shape of the first power supply line 46 may be a linear shape with the main body extending along the second direction Y. On one side, the first power supply line 46 is connected to the second electrode plate 33 via the second via V2. On another side, it is connected to the fifth active layer via the third via V3. On still another side, it is connected to the shield electrode 35 via the eleventh via V11. Thereby, the first pole of the fifth transistor T5 has the same potential as the second electrode plate 33, and the first power supply line 46 is configured to continuously supply a high power supply voltage signal (VDD), and may be called a high voltage power supply line. Since the shield electrode 35 is connected to the first power supply line 46 and at least a part of the region of the shield electrode 35 is located between the first connection electrode 41 (serving as the second pole of the first transistor T1 and the first pole of the second transistor T2, i.e., the second node N2) and the second connection electrode 42 (serving as the second pole of the fourth transistor T4), the shield electrode 35 can effectively shield the influence on the key node of the pixel driving circuit caused by the data voltage jump, avoid the influence on the potential of the key node of the pixel driving circuit caused by the data voltage jump, and improve the display effect. 【0189】 In an exemplary embodiment, the first power supply line 46 of each circuit unit may have a non-uniform width design. The first power supply line 46 adopting the non-uniform width design can not only facilitate the layout of the pixel structure, but also reduce the parasitic capacitance between the first power supply line and the data signal line. 【0190】 In an exemplary embodiment, the shape of the initial connection line 47 is a broken line in which the main body portion extends along the second direction Y. The initial connection line 47 is installed on the side away from the first power line 46 of the first connection electrode 41. The initial connection line 47 is configured to be connected to the first initial signal line 31 or the second initial signal line 32 to form a mesh communication structure for transmitting the first initial signal or the second initial signal. 【0191】 In an exemplary embodiment, the initial connection line 47 in the odd-numbered circuit units may be connected to the fifth connection electrode 45, and the initial connection line 47 in the even-numbered circuit units may be connected to the fourth connection electrode 44. Or, the initial connection line 47 in the odd-numbered circuit units may be connected to the fourth connection electrode 44, and the initial connection line 47 in the even-numbered circuit units may be connected to the fifth connection electrode 45. 【0192】 In an exemplary embodiment, the initial connection lines 47 in the Nth column and the N + 2th column may be connected to the fifth connection electrodes 45 of a plurality of circuit units in the unit column. Since the fifth connection electrode 45 is connected to the first initial signal line 31 via a via, the mutual connection between the initial connection line 47 and the first initial signal line 31 is realized. By forming the initial signal lines of the mesh communication structure with the plurality of first initial signal lines 31 extending along the first direction X and the plurality of initial connection lines 47 extending along the second direction Y, not only can the resistance of the first initial signal line be effectively reduced and the voltage drop of the first initial signal be reduced, but also the uniformity of the first initial signal on the display substrate can be effectively improved, the display uniformity can be effectively improved, and the display attributes and display quality can be improved. 【0193】 In an exemplary embodiment, the initial connection lines 47 in the (N + 1)-th column and the (N + 3)-th column may be connected to the fourth connection electrodes 44 of a plurality of circuit units in the unit column. Since the fourth connection electrodes 44 are connected to the second initial signal lines 32 via vias, the interconnection between the initial connection lines 47 and the second initial signal lines 32 is realized. By forming the initial signal lines extending along the first direction X and the plurality of initial connection lines 47 extending along the second direction Y into an initial signal line of a mesh communication structure, the resistance of the second initial signal line can be effectively reduced, not only reducing the voltage drop of the second initial signal, but also effectively improving the uniformity of the second initial signal on the display substrate, effectively improving the display uniformity, and improving the display attributes and display quality. 【0194】 By forming the initial signal lines for transmitting the first initial signal into a mesh structure, forming the initial signal lines for transmitting the second initial signal into a mesh structure, and simultaneously realizing the mesh layout of the initial signal lines for transmitting the first initial signal and the initial signal lines for transmitting the second initial signal, the resistance of the first initial signal line and the second initial signal line can be effectively reduced, not only reducing the voltage drops of the first initial voltage and the second initial voltage, but also effectively improving the uniformity of the first initial voltage and the second initial voltage on the display substrate, effectively improving the display uniformity, and improving the display attributes and display quality. 【0195】 In some possible exemplary embodiments, the initial connection lines 47 may be arranged to be connected to the first initial signal lines 31 and the second initial signal lines 32 in an odd-row and even-row manner. For example, in the circuit units of odd rows, the initial connection lines 47 may be connected to the fifth connection electrodes 45, and in the circuit units of even rows, the initial connection lines 47 may be connected to the fourth connection electrodes 44, or in the circuit units of odd rows, the initial connection lines 47 may be connected to the fourth connection electrodes 44, and in the circuit units of even rows, the initial connection lines 47 may be connected to the fifth connection electrodes 45. 【0196】 In an exemplary embodiment, the third conductive layer patterns in the E1 region and the E2 region in FIG. 10 are basically the same as the third conductive layer pattern in the E0 region. 【0197】 (6) Form the fifth insulating layer and the first flat layer pattern. In an exemplary embodiment, as shown in FIG. 17, forming the fifth insulating layer and the first flat layer pattern includes depositing a fifth insulating thin film on the base on which the pattern is formed, then applying a first flat thin film, and patterning the first flat thin film and the fifth insulating thin film by a patterning process to form a fifth insulating layer covering the third conductive layer and a first flat layer provided on the fifth insulating layer, and a plurality of vias may be provided in the fifth insulating layer and the first flat layer. FIG. 17 is an enlarged view of the E0 region of FIG. 10. 【0198】 In an exemplary embodiment, the plurality of vias of the plurality of circuit units in the display region include at least the 21st via V21 and the 22nd via V22. 【0199】 In an exemplary embodiment, the orthographic projection of the 21st via V21 on the base is located within the range of the orthographic projection of the second connection electrode 42 on the base. The first flat layer and the fifth insulating layer within the 21st via V21 are removed to expose the surface of the second connection electrode 42. The 21st via V21 is configured to connect a data signal line to be formed later to the second connection electrode 42 through the via. 【0200】 In an exemplary embodiment, the orthographic projection of the 22nd via V22 on the base is located within the range of the orthographic projection of the third connection electrode 43 on the base. The first flat layer and the fifth insulating layer within the 22nd via V22 are removed to expose the surface of the third connection electrode 43. The 22nd via V22 is configured to connect an anode connection electrode to be formed later to the third connection electrode 43 through the via. 【0201】 In an exemplary embodiment, the via patterns in the E1 region and the E2 region of FIG. 10 are basically the same as the via pattern in the E0 region. 【0202】 (7) A fourth conductive layer pattern is formed. In an exemplary embodiment, as shown in FIGS. 18a to 18d, forming the fourth conductive layer pattern may include depositing a fourth conductive thin film on the base on which the pattern is formed, patterning the fourth conductive thin film by a patterning process, and forming a fourth conductive layer disposed on the first flat layer. FIG. 18a is an enlarged view of regions E0 and E2 in FIG. 10, FIG. 18b is a schematic plan view of the fourth conductive layer in FIG. 18a, FIG. 18c is an enlarged view of regions E1 and E2 in FIG. 10, and FIG. 18d is a schematic plan view of the fourth conductive layer in FIG. 18c. In an exemplary embodiment, the fourth conductive layer may be referred to as a second source / drain metal (SD2) layer. 【0203】 In an exemplary embodiment, the fourth conductive layer patterns of the plurality of circuit units in the display region all include a first anode connection electrode 51, a data signal line 60, and a second power supply line 80. 【0204】 In an exemplary embodiment, the shape of the first anode connection electrode 51 may be strip-shaped extending along the second direction Y, and the first anode connection electrode 51 is connected to the third connection electrode 43 via the 22nd via V22. In an exemplary embodiment, the first anode connection electrode 51 is configured to be connected to a second anode connection electrode formed later. In order to adapt to the connection with the anode formed later, the shapes and positions of the first anode connection electrodes 51 in the plurality of circuit units may be different. 【0205】 In an exemplary embodiment, the shape of the data signal line 60 may be linear with the main body extending along the second direction Y. The data signal line 60 is connected to the second connection electrode 42 via the 21st via V21, and the second connection electrode 42 is connected to the first region of the fourth active layer via a via, so that the data signal line 60 realizes writing a data signal to the first pole of the fourth transistor T4. 【0206】 In an exemplary embodiment, the shape of the second power supply line 80 may be a polyline shape in which the main body extends along the second direction Y. The second power supply line 80 serves as the low-voltage power supply line of the present disclosure and is configured to continuously supply a low power supply voltage signal (VSS) to a light-emitting device formed later. 【0207】 In an exemplary embodiment, the orthographic projection of the second power supply line 80 on the base overlaps at least partially with the orthographic projection of the first power supply line 46 on the base. Since both the first power supply line 46 and the second power supply line 80 transmit a constant voltage signal, they can be installed overlapping each other, effectively improving the transmittance and space utilization rate of the display substrate. 【0208】 In an exemplary embodiment, the region of the orthographic projection of the first power supply line 46 on the base has a first area, and the overlapping region between the orthographic projection of the second power supply line 80 on the base and the orthographic projection of the first power supply line 46 on the base has a first overlapping area, and the first overlapping area may be larger than 80% of the first area. 【0209】 In an exemplary embodiment, the orthographic projection of the first power supply line 46 on the base may be located within the range of the orthographic projection of the second power supply line 80 on the base. 【0210】 In an exemplary embodiment, the structures of the first anode connection electrode 51, the second power supply line 80, and the data signal line 60 in the first region, the second region, and the third region are basically the same. 【0211】 In an exemplary embodiment, the fourth conductive layer patterns in the second region (E2 region) and the third region (E0 region) of the display region are basically the same, and include only the first anode connection electrode 51, the data signal line 60, and the second power supply line 80. The fourth conductive layer patterns of the plurality of circuit units in the first region (E1 region) of the display region may further include data connection electrodes 61. 【0212】 In an exemplary embodiment, the data connection electrode 61 may be provided as part of the circuit unit in the first region, the shape of the data connection electrode 61 may be rectangular, the data connection electrode 61 is connected to the data signal line 60, and the data connection electrode 61 is configured to be connected to a subsequently formed first connection line. 【0213】 (8) Form a second flat layer pattern. In an exemplary embodiment, as shown in FIGS. 19a to 19c, forming the second flat layer pattern may include coating a second flat thin film on the base on which the pattern is formed, patterning the second flat thin film by a patterning process, forming a second flat layer covering the fourth conductive layer, and providing a plurality of vias in the second flat layer. FIG. 19a is an enlarged view of the E0 region of FIG. 10, FIG. 19b is an enlarged view of the E1 region of FIG. 10, and FIG. 19c is an enlarged view of the E2 region of FIG. 10. 【0214】 In an exemplary embodiment, each of the plurality of circuit units in the display region includes a 31st via V31. 【0215】 In an exemplary embodiment, the orthographic projection of the 31st via V31 on the base is located within the range of the orthographic projection of the first anode connection electrode 51 on the base, the second flat layer within the 31st via V31 is removed to expose the surface of the first anode connection electrode 51, and the 31st via V31 is configured to connect a subsequently formed second anode connection electrode to the first anode connection electrode 51 through the via. The positions of the 31st vias V31 in the plurality of circuit units may be different in order to adapt to the connection with a subsequently formed anode. 【0216】 As shown in FIG. 19a, in an exemplary embodiment, the plurality of circuit units in the third region (E0 region) of the display region may further include a 32nd via V32. 【0217】 In an exemplary embodiment, the orthographic projection at the base of the 32nd via V32 is located within the range of the orthographic projection at the base of the second power line 80, the second flat layer within the 32nd via V32 is removed to expose the surface of the second power line 80, and the 32nd via V32 is configured to connect a second power wiring formed later to the second power line 80 via the via. 【0218】 As shown in FIG. 19b, in an exemplary embodiment, the plurality of circuit units in the first region (E1 region) of the display region may further include the 32nd via V32 and the 33rd via V33. 【0219】 In an exemplary embodiment, the structure of the 32nd via V32 in the first region is basically the same as the structure of the 32nd via V32 in the third region. 【0220】 In an exemplary embodiment, the orthographic projection at the base of the 33rd via V33 is located within the range of the orthographic projection at the base of the data connection electrode 61, the second flat layer within the 33rd via V33 is removed to expose the surface of the data connection electrode 61, and the 33rd via V33 is configured to connect a first connection line formed later to the data connection electrode 61 via the via. 【0221】 As shown in FIG. 19c, in an exemplary embodiment, the plurality of circuit units in the second region (E2 region) of the display region include only the 31st via V31. 【0222】 (9) Form a fifth conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 20a to 20f, forming the fifth conductive layer pattern may include depositing a fifth conductive thin film on the base on which the pattern is formed, patterning the fifth conductive thin film by a patterning process, and forming a fifth conductive layer disposed on the second flat layer. FIG. 20a is an enlarged view of the E0 region of FIG. 10, FIG. 20b is a schematic plan view of the fifth conductive layer of FIG. 20a, FIG. 20c is an enlarged view of the E1 region of FIG. 10, FIG. 20d is a schematic plan view of the fifth conductive layer of FIG. 20c, FIG. 20e is an enlarged view of the E2 region of FIG. 10, and FIG. 20f is a schematic plan view of the fifth conductive layer of FIG. 20e. In an exemplary embodiment, the fifth conductive layer may be referred to as a third source / drain metal (SD3) layer. 【0223】 In an exemplary embodiment, the fifth conductive layer patterns of the plurality of circuit units in the display region all include a second anode connection electrode 53. 【0224】 In an exemplary embodiment, the shape of the second anode connection electrode 53 may be rectangular, and the second anode connection electrode 53 is connected to the first anode connection electrode 51 via a 31st via V31. In an exemplary embodiment, the second anode connection electrode 53 is configured to be connected to an anode formed later. In order to adapt to the connection with the later-formed anode, the shapes and positions of the second anode connection electrodes 53 in the plurality of circuit units may be different. 【0225】 As shown in FIGS. 20a and 20b, the fifth conductive layer patterns of the plurality of circuit units in the third region (E0 region) of the display region further include a first power supply wiring 91, a second power supply wiring 92, a power supply connection electrode 93, a first compensation line 110, and a second compensation line 120. 【0226】 In an exemplary embodiment, the shape of the first power supply wiring 91 may be linear with the main body portion extending along the first direction X, and the first power supply wirings 91 in the circuit units adjacent to each other in the first direction X in the third region are of an integral structure connected to each other. 【0227】 In an exemplary embodiment, the orthographic projection of the first power supply wiring 91 on the base overlaps at least partially with the orthographic projection of the first initial signal line 31 on the base, and the transmittance and space utilization rate of the display substrate can be effectively improved. 【0228】 In an exemplary embodiment, the region of the orthographic projection of the first power supply wiring 91 on the base has a third area, and the overlapping region between the orthographic projection of the first initial signal line 31 on the base and the orthographic projection of the first initial signal line 31 on the base has a third overlapping area, and the third overlapping area may be larger than 80% of the third area. 【0229】 In an exemplary embodiment, the shape of the second power supply wiring 92 may be linear with the main body extending along the second direction Y, and the second power supply wirings 92 in the circuit units adjacent to the second direction Y in the third region are of an integrated structure connected to each other. 【0230】 In an exemplary embodiment, the orthographic projection of the second power supply wiring 92 on the base overlaps at least partially with the orthographic projection of the second electrode plate 33 of the storage capacitor on the base. 【0231】 In an exemplary embodiment, the plurality of second power supply wirings 92 and the plurality of first power supply wirings 91 in the third region are of an integrated structure connected to each other, forming a mesh-shaped power supply lead wire. 【0232】 In an exemplary embodiment, the shape of the power supply connection electrode 93 may be rectangular, the power supply connection electrode 93 may be installed on the side away from the data signal line 60 of the second power supply wiring 92 (i.e., the side close to the second power supply line 80), and is connected to the second power supply wiring 92. The orthographic projection of the power supply connection electrode 93 on the base overlaps at least partially with the orthographic projection of the low-voltage power supply line 52 on the base. The power supply connection electrode 93 is connected to the second power supply line 80 via the 32nd via V32, realizing the connection between the mesh-shaped power supply lead wire and the second power supply line 80. 【0233】 In an exemplary embodiment, the shape of the first compensation line 110 may be linear with the main body extending along the first direction X, and the first compensation lines 110 in the circuit units adjacent to the first direction X in the third region are of an integral structure connected to each other. 【0234】 In an exemplary embodiment, the orthographic projection of the first compensation line 110 on the base overlaps at least partially with the orthographic projection of the second initial signal line 32 on the base, and the transmittance and space utilization rate of the display substrate can be effectively improved. 【0235】 In an exemplary embodiment, the region of the orthographic projection of the first compensation line 110 on the base has a fourth area, the overlapping region of the orthographic projection of the first compensation line 110 on the base and the orthographic projection of the second initial signal line 32 on the base has a fourth overlapping area, and the fourth overlapping area may be larger than 80% of the fourth area. 【0236】 In an exemplary embodiment, the shape of the second compensation line 120 may be linear with the main body extending along the second direction Y, and the second compensation lines 120 in the circuit units adjacent to the second direction Y in the third region are of an integral structure connected to each other. 【0237】 In an exemplary embodiment, the orthographic projection of the second compensation line 120 on the base overlaps at least partially with the orthographic projection of the initial connection line 47 on the base, and the transmittance and space utilization rate of the display substrate can be effectively improved. 【0238】 In an exemplary embodiment, the region of the orthographic projection of the second compensation line 120 on the base has a fifth area, the overlapping region of the orthographic projection of the second compensation line 120 on the base and the orthographic projection of the initial connection line 47 on the base has a fifth overlapping area, and the fifth overlapping area may be larger than 80% of the fifth area. 【0239】 In an exemplary embodiment, the plurality of first compensation lines 110 and the plurality of second compensation lines 120 in the third region are in an integrated structure connected to each other, forming a mesh-shaped compensation line. The first compensation line 110 and the second compensation line 120 are configured such that the fifth conductive layer pattern in the third region and the fifth conductive layer patterns in the first region and the second region exhibit a similar form, which not only improves the uniformity of the manufacturing process but also enables basically the same display effect to be obtained for transmitted light and reflected light in different regions, effectively avoiding appearance defects of the display substrate and improving the display attributes and display quality. 【0240】 In an exemplary embodiment, the plurality of first compensation lines 110 and the plurality of second power supply lines 92 are connected to each other, and the plurality of second compensation lines 120 and the plurality of first power supply lines 91 are connected to each other, thus realizing the mutual connection of the mesh-shaped power supply lead lines and the mesh-shaped compensation lines. 【0241】 In an exemplary embodiment, in the third region, at least one circuit unit may be provided with at least one first power supply line 91, at least one second power supply line 92, at least one first compensation line 110, and at least one second compensation line 120. The first power supply line 91 may be provided on the Y side of the second direction of the circuit unit, the first compensation line 110 may be provided on the side opposite to the second direction Y of the circuit unit, the second power supply line 92 may be provided on the X side of the first direction of the second power supply line 80, and the second compensation line 120 may be provided on the side opposite to the first direction X of the second power supply line 80. 【0242】 In an exemplary embodiment, the orthographic projection of the second compensation line 120 on the base overlaps at least partially with the orthographic projection of the dummy line on the base. 【0243】 As shown in FIGS. 20c and 20d, the fifth conductive layer pattern of the plurality of circuit units in the first region (E1 region) of the display region further includes a first connection line 71, a first power supply line 91, a second power supply line 92, a power supply connection electrode 93, and a second compensation line 120. 【0244】 In an exemplary embodiment, the shape of the first connection line 71 may be linear with the main body extending along the first direction X, and the first connection line 71 is connected to the data connection electrode 61 via the 33rd via V33. Since the data connection electrode 61 is connected to the data signal line 60, the connection between the first connection line 71 and the data signal line 60 is realized. 【0245】 In an exemplary embodiment, the orthographic projection of the first connection line 71 on the base overlaps at least partially with the orthographic projection of the second initial signal line 32 on the base. Since the first connection line 71 is located in the fifth conductive layer (SD3), the second initial signal line 32 is located in the second conductive layer (GATE2), and thick first and second planarization layers are provided therebetween, crosstalk does not occur between the first connection line 71 for transmitting data signals and the second initial signal line 32 for transmitting initial voltage signals. By arranging the first connection line 71 and the second initial signal line 32 overlappingly, the transmittance of the display substrate and the space utilization rate can be effectively improved. 【0246】 In an exemplary embodiment, the region of the orthographic projection of the first connection line 71 on the base has a second overlapping area, the overlapping region between the orthographic projection of the first connection line 71 on the base and the orthographic projection of the second initial signal line 32 on the base has a second area, and the second overlapping area may be larger than 80% of the second area. 【0247】 In an exemplary embodiment, the first connection lines 71 in the circuit units adjacent to each other in the first direction X in the first region are of an integral structure connected to each other. 【0248】 In an exemplary embodiment, in at least one unit row including the circuit units in the first region and the circuit units in the third region, the first connection line 71 in the first region and the first compensation line 110 in the third region may be located on the same straight line extending along the first direction X, the wirings in the first region and the third region exhibit similar forms, which not only improves the uniformity of the manufacturing process, but also can obtain basically the same display effect in transmitted light and reflected light in different regions, effectively avoiding appearance defects of the display substrate and improving the display attributes and display quality. 【0249】 In an exemplary embodiment, in at least one unit row including the circuit units in the first region and the circuit units in the third region, the first power supply wiring 91 in the first region and the first power supply wiring 91 in the third region may be located on the same straight line extending along the second direction Y, the power supply connection electrodes 93 in the first region and the power supply connection electrodes 93 in the third region may be located on the same straight line extending along the second direction Y, the first power supply wirings 91 in the circuit units adjacent to each other in the first direction X in the first region are in an integrated structure connected to each other, and the power supply connection electrode 93 is connected to the second power supply line 80 via the 32nd via V32. 【0250】 In an exemplary embodiment, in at least one unit row including the circuit units in the first region and the circuit units in the third region, the second power supply wiring 92 in the first region and the second power supply wiring 92 in the third region may be located on the same straight line extending along the second direction Y, the second compensation line 120 in the first region and the second compensation line 120 in the third region may be located on the same straight line extending along the second direction Y. The difference is that the second power supply wiring 92 and the second compensation line 120 in the circuit units adjacent to each other in the second direction Y in the first region are intermittent, that is, the second power supply wirings 92 in the circuit units adjacent to each other in the second direction Y are installed at intervals, and the second compensation lines 120 in the circuit units adjacent to each other in the second direction Y are installed at intervals. Thereby, the first connection line 71 is installed between the break points of the second power supply wiring 92 and the second compensation line 120. 【0251】 As shown in FIGS. 20e and 20f, the fifth conductive layer pattern of the plurality of circuit units in the second region (E2 region) of the display region further includes a second connection line 72, a dummy connection electrode 73, and a first compensation line 110. 【0252】 In an exemplary embodiment, the shape of the second connection line 72 may be linear with the main body portion extending along the second direction Y. The first end of the second connection line 72 is connected to a lead wire located in the lead wire region, and the second end of the second connection line 72 is connected to the first connection line 71 located in the display region. The first connection line 71 and the second connection line 72 connected to each other constitute a data connection line. 【0253】 In an exemplary embodiment, the second connection lines 72 in the circuit units adjacent to each other in the second direction Y in the second region are of an integral structure connected to each other. 【0254】 In an exemplary embodiment, in at least one unit row including the circuit units in the second region and the circuit units in the third region, the first side connection line in the second connection line 72 in the second region and the second power supply wiring 92 in the third region may be located on the same straight line extending along the second direction Y, and the second side connection line in the second connection line 72 in the second region and the second compensation line 120 in the third region may be located on the same straight line extending along the second direction Y. Thereby, the wirings in the second region and the wirings in the third region exhibit a similar form, which not only improves the uniformity of the manufacturing process, but also enables basically the same display effect to be obtained in transmitted light and reflected light in different regions, effectively avoiding appearance defects of the display substrate and improving the display attributes and display quality. 【0255】 In an exemplary embodiment, the shape of the dummy connection electrode 73 may be rectangular. The dummy connection electrode 73 is installed on the side away from the data signal line 60 of the second connection line 72 (i.e., the side close to the second power supply line 80), and may be connected to the second connection line 72. The orthographic projection of the dummy connection electrode 73 at its base overlaps at least partially with the orthographic projection of the low voltage power supply line 52 at its base. 【0256】 In an exemplary embodiment, in at least one unit row including the circuit units in the second region and the circuit units in the third region, the dummy connection electrode 73 in the second region and the power supply connection electrode 93 in the third region may be located on the same straight line extending along the first direction X. In at least one unit column including the circuit units in the second region and the circuit units in the third region, the dummy connection electrode 73 in the second region and the power supply connection electrode 93 in the third region may be located on the same straight line extending along the second direction Y. That is, the position and shape of the dummy connection electrode 73 in the circuit unit of the second region are basically the same as the position and shape of the power supply connection electrode 93 in the circuit unit of the third region. The difference is that the dummy connection electrode 73 is not connected to the second power line 80 via a via. The dummy connection electrode 73 is configured to present a similar form in the fifth conductive layer patterns of the second region and the third region, which can not only improve the uniformity of the manufacturing process, but also obtain basically the same display effect in transmitted light and reflected light in different regions, effectively avoid appearance defects of the display substrate, and improve the display attributes and display quality. 【0257】 In an exemplary embodiment, the shape of the first compensation line 110 may be a straight segment whose main body extends along the first direction X. The first end of the first compensation line 110 is connected to the second connection line 72, and the second end of the first compensation line 110 extends along the first direction X or the opposite direction of the first direction X. 【0258】 In an exemplary embodiment, at least two second connection lines 72 and two first compensation lines 110 may be provided in at least one circuit unit of the second region. The two second connection lines 72 may include a first-side connection line and a second-side connection line. The first-side connection line may be provided between the second power line 80 and the data signal line 60, and the second-side connection line may be provided on the side of the second power line 80 away from the data signal line 60. The at least two first compensation lines 110 may include at least one first-side compensation line and at least one second-side compensation line. The first end of the first-side compensation line is connected to the first-side connection line, the second end of the first-side compensation line extends along a direction close to the second-side connection line, the first end of the second-side compensation line is connected to the second-side connection line, and the second end of the second-side compensation line extends along a direction close to the first-side connection line. Thus, the two first compensation lines 110 in the circuit unit form an interdigital structure. 【0259】 In an exemplary embodiment, in at least one unit row including the circuit units of the second region and the circuit units of the third region, the first-side compensation line of the second region and the first power distribution line 91 of the third region may be located on the same straight line extending along the first direction X. The difference is that the first-side compensation line is installed at intervals in a plurality of circuit units of one unit row. 【0260】 In an exemplary embodiment, in at least one unit row including the circuit units of the second region and the circuit units of the first region, the second-side compensation line of the second region and the first connection line 71 of the first region may be located on the same straight line extending along the first direction X. The difference is that the second-side compensation line is installed at intervals in a plurality of circuit units of one unit row. 【0261】 In an exemplary embodiment, in at least one unit row including the circuit unit in the first region, the circuit unit in the second region, and the circuit unit in the third region, the first power supply wiring 91 in the first region, the first side compensation wiring in the first compensation wiring 110 in the second region, and the first power supply wiring 91 in the third region may be located on the same straight line extending along the first direction X. The first connection wiring 71 in the first region, the second side compensation wiring in the first compensation wiring 110 in the second region, and the first compensation wiring 110 in the third region may be located on the same straight line extending along the first direction X. The power supply connection electrode 93 in the first region, the dummy connection electrode 73 in the second region, and the power supply connection electrode 93 in the third region may also be located on the same straight line extending along the first direction X. 【0262】 In an exemplary embodiment, in at least one unit column including the circuit unit in the first region, the circuit unit in the second region, and the circuit unit in the third region, the second power supply wiring 92 in the first region, the first side connection wiring in the second connection wiring 72 in the second region, and the second power supply wiring 92 in the third region may be located on the same straight line extending along the second direction Y. The second compensation wiring 120 in the first region, the second side connection wiring in the second connection wiring 72 in the second region, and the second compensation wiring 120 in the third region may be located on the same straight line extending along the second direction Y. The power supply connection electrode 93 in the first region, the dummy connection electrode 73 in the second region, and the power supply connection electrode 93 in the third region may also be located on the same straight line extending along the second direction Y. 【0263】 (10) Form a third planar layer pattern. In an exemplary embodiment, as shown in FIGS. 21a to 21c, forming the third planar layer pattern may include applying a third planar thin film to the base on which the pattern is formed, patterning the third planar thin film by a patterning process to form a third planar layer covering the fifth conductive layer, and providing a plurality of vias in the third planar layer. FIG. 21a is an enlarged view of the E0 region in FIG. 10, FIG. 21b is an enlarged view of the E1 region in FIG. 10, and FIG. 21c is an enlarged view of the E2 region in FIG. 10. 【0264】 In an exemplary embodiment, the vias of each circuit unit in the display region include at least the 41st via V41. In an exemplary embodiment, the orthographic projection of the 41st via V41 at its base is located within the range of the orthographic projection of the second anode connection electrode 53 at its base. The third planarization layer within the 41st via V41 is removed to expose the surface of the second anode connection electrode 53. The 41st via V41 is configured to connect an anode formed later to the second anode connection electrode 53 through the via. In order to adapt to the connection with the anode formed later, the positions of the 41st vias V41 in a plurality of circuit units may be different. 【0265】 In an exemplary embodiment, the via patterns in the first region, the second region, and the third region are basically the same. 【0266】 So far, the driving circuit layer is manufactured and completed on the base. In a plane parallel to the display substrate, the driving circuit layer may include a plurality of circuit units. Each circuit unit may include a pixel driving circuit, a first scanning signal line, a second scanning signal line, a light emission control line, a data signal line, a first power supply line, a second power supply line, a first initial signal line, and a second initial signal line connected to the pixel driving circuit. In a plane perpendicular to the display substrate, the driving circuit layer may include a first insulating layer, a semiconductor layer, a second insulating layer, a first conductive layer, a third insulating layer, a second conductive layer, a fourth insulating layer, a third conductive layer, a fifth insulating layer, a first planarization layer, a fourth conductive layer, a second planarization layer, a fifth conductive layer, and a third planarization layer sequentially stacked and installed on the base. 【0267】 In an exemplary embodiment, the base may be a flexible base or a rigid base. The rigid base may be one or more of glass and quartz, but is not limited thereto. The flexible base may be one or more of polyethylene terephthalate, ethylene terephthalate, polyether ether ketone, polystyrene, polycarbonate, polyarylate, polyimide, polyvinyl chloride, polyethylene, and textile fibers, but is not limited thereto. In an exemplary embodiment, the flexible base may include a laminated first flexible material layer, a first inorganic material layer, a semiconductor layer, a second flexible material layer, and a second inorganic material layer. The materials of the first flexible material layer and the second flexible material layer can be materials such as polyimide (PI), polyethylene terephthalate (PET), or a surface-treated polymer soft film. The materials of the first inorganic material layer and the second inorganic material layer can be silicon nitride (SiNx) or silicon oxide (SiOx) for improving the hydrogen resistance of the substrate. The material of the semiconductor layer can be amorphous silicon (a-si). 【0268】 In an exemplary embodiment, the first conductive layer, the second conductive layer, the third conductive layer, the fourth conductive layer, and the fifth conductive layer may be made of one or more metal materials such as silver (Ag), copper (Cu), aluminum (Al), molybdenum (Mo), or alloy materials of these metals such as aluminum-neodymium alloy (AlNd) and molybdenum-niobium alloy (MoNb). They may have a single-layer structure or a multilayer composite structure such as Mo / Cu / Mo. The first insulating layer, the second insulating layer, the third insulating layer, the fourth insulating layer, and the fifth insulating layer may adopt one or more of silicon oxide (SiOx), silicon nitride (SiNx), and silicon oxynitride (SiON), and may be a single layer, a multilayer, or a composite layer. The first insulating layer can be called a buffer layer, the second and third insulating layers can be called gate insulating (GI) layers, the fourth insulating layer can be called an interlayer dielectric (ILD) layer, and the fifth insulating layer can be called a passivation layer (PVX). The first planarization layer, the second planarization layer, and the third planarization layer can use organic materials such as resin. The semiconductor layer can use materials such as amorphous indium gallium zinc oxide material (a-IGZO), zinc oxide nitride (ZnON), indium zinc tin oxide (IZTO), amorphous silicon (a-Si), polysilicon (p-Si), hexathiophene, or polythiophene. That is, the present disclosure is suitable for transistors manufactured based on oxide technology, silicon technology, or organic technology. 【0269】 In an exemplary embodiment, after the manufacturing of the driving circuit layer is completed, a light-emitting structure layer is manufactured on the driving circuit layer, and the manufacturing process of the light-emitting structure layer may include the following operations. 【0270】 (11) Form an anode conductive layer pattern. In an exemplary embodiment, as shown in FIGS. 22a to 22d, forming the anode conductive layer pattern may include depositing an anode conductive thin film on the base on which the pattern is formed, patterning the anode conductive thin film by a patterning process, and forming an anode conductive layer pattern disposed on the third planarization layer. FIG. 22a is an enlarged view of the E0 region of FIG. 10, FIG. 22b is an enlarged view of the E1 region of FIG. 10, FIG. 22c is an enlarged view of the E2 region of FIG. 10, and FIG. 22d is a planar schematic diagram of the anode conductive layer of FIG. 22a. 【0271】 In an exemplary embodiment, the anode conductive layer may adopt a single-layer structure such as indium tin oxide (ITO) or indium zinc oxide (IZO), or a multilayer composite structure such as ITO / Ag / ITO. 【0272】 In an exemplary embodiment, the anode conductive layer pattern may include the first anode 301R of the red light-emitting device, the second anode 301B of the blue light-emitting device, the third anode 301G1 of the first green light-emitting device, and the fourth anode 301G2 of the second green light-emitting device. The region where the first anode 301R is located may form a red sub-pixel R that emits red light, the region where the second anode 301B is located may form a blue sub-pixel B that emits blue light, the region where the third anode 301G1 is located may form a first green sub-pixel G1 that emits green light, and the region where the fourth anode 301G2 is located may form a second green sub-pixel G2 that emits green light. 【0273】 In an exemplary embodiment, the first anode 301A and the second anode 301B may be sequentially installed along the second direction Y, the third anode 301C and the fourth anode 301D may be sequentially installed along the second direction Y, and the third anode 301C and the fourth anode 301D may be installed on the first direction X side of the first anode 301A and the second anode 301B. Alternatively, the first anode 301A and the second anode 301B may be sequentially installed along the first direction X, the third anode 301C and the fourth anode 301D may be sequentially installed along the first direction X, and the third anode 301C and the fourth anode 301D may be installed on the second direction Y side of the first anode 301A and the second anode 301B. 【0274】 In an exemplary embodiment, the first anode 301R, the second anode 301B, the third anode 301G1, and the fourth anode 301G2 may each be connected to the second anode connection electrode 53 in the corresponding circuit unit via the 41st via V41. Since each anode is connected to the second region of the sixth active layer (which is also the second region of the seventh active layer) via the second anode connection electrode, the first anode connection electrode, and the third connection electrode in one circuit unit, the four anodes in one pixel unit are respectively connected corresponding to the pixel driving circuits of the four circuit units, realizing that the pixel driving circuit can drive the light emission of the light emitting device. 【0275】 In an exemplary embodiment, the shapes and positions of the two second anodes 301B respectively connected to the pixel driving circuits in the circuit unit of the Mth row and Nth column and the circuit unit of the (M + 1)th row and (N + 2)th column are the same. The shapes and positions of the two first anodes 301R respectively connected to the pixel driving circuits in the circuit unit of the Mth row and (N + 2)th column and the circuit unit of the (M + 1)th row and Nth column are the same. The shapes and positions of the two fourth anodes 301G2 respectively connected to the pixel driving circuits in the circuit unit of the Mth row and (N + 1)th column and the circuit unit of the (M + 1)th row and (N + 3)th column are the same. The shapes and positions of the two third anodes 301G1 respectively connected to the pixel driving circuits in the circuit unit of the Mth row and (N + 3)th column and the circuit unit of the (M + 1)th row and (N + 1)th column are the same. 【0276】 In an exemplary embodiment, the shapes and areas of the anodes of the four sub-pixels in one pixel unit may be the same or different. The positional relationship between the four sub-pixels in one pixel unit and the four circuit units in one circuit unit group may be the same or different. The shapes and positions of the first anode 301R, the second anode 301B, the third anode 301G1, and the fourth anode 301G2 in different pixel units may be the same or different, and the present disclosure is not limited herein. 【0277】 In an exemplary embodiment, at least one of the first anode 301A, the second anode 301B, the third anode 301C, and the fourth anode 301D may include a main body portion and a connection portion that are connected to each other. The shape of the main body portion may be rectangular, and an arc chamfer may be provided at the corner of the rectangle. The shape of the connection portion may be stripe-shaped extending along a direction away from the main body portion. The connection portion is connected to the second anode connection electrode 53 via the 41st via V41. 【0278】 As shown in FIG. 22a, in the third region, the orthographic projection of the bases of the main body portions of the first anode 301A and the second anode 301B at least partially overlaps with the orthographic projection of the bases of one first power supply wiring 91 and one first compensation line 110. The orthographic projection of the bases of the main body portions of the first anode 301A and the second anode 301B at least partially overlaps with the orthographic projection of the bases of one second power supply wiring 92 and two second compensation lines 120. The orthographic projection of the bases of the main body portions of the third anode 301C and the fourth anode 301D at least partially overlaps with the orthographic projection of the base of one second power supply wiring 92. 【0279】 As shown in FIG. 22b, in the first region, the orthographic projection of the bases of the main body portions of the first anode 301A and the second anode 301B at least partially overlaps with the orthographic projection of the bases of one first power supply wiring 91 and one first connection line 71. The orthographic projection of the bases of the main body portions of the first anode 301A and the second anode 301B at least partially overlaps with the orthographic projection of the bases of one second power supply wiring 92 and two second compensation lines 120. The orthographic projection of the bases of the main body portions of the third anode 301C and the fourth anode 301D at least partially overlaps with the orthographic projection of the base of one second power supply wiring 92. 【0280】 As shown in FIG. 22c, in the second region, the orthographic projections of the main body portions of the first anode 301A and the second anode 301B at the base overlap at least partially with the orthographic projections of the bases of the two first compensation lines 110, the orthographic projections of the main body portions of the first anode 301A and the second anode 301B at the base overlap at least partially with the orthographic projections of the bases of the three second connection lines 72, and the orthographic projections of the main body portions of the third anode 301C and the fourth anode 301D at the base overlap at least partially with the orthographic projection of the base of one second connection line 72. 【0281】 In an exemplary embodiment, as can be seen by comparing the orthographic projections of the bases of the first anode 301A and the second anode 301B in the first region, the second region, and the third region, the main body portions of both the first anode 301A and the second anode 301B have overlapping portions with two horizontal lines (straight lines extending along the first direction X), and the main body portions of both the first anode 301A and the second anode 301B have overlapping portions with three vertical lines (straight lines extending along the second direction Y). Therefore, the horizontal and vertical metal lines of the SD3 layer below the main body portions of the first anode 301A and the second anode 301B in the three regions are basically the same, the flatness of the first anode 301A and the second anode 301B in the three regions can be ensured, and the light-emitting performance of the red light-emitting devices and the blue light-emitting devices in the three regions can be basically ensured to be the same. 【0282】 In an exemplary embodiment, as can be seen by comparing the orthographic projections of the bases of the third anode 301C and the fourth anode 301D in the first region, the second region, and the third region, the orthographic projections of the main body portions of both the third anode 301C and the fourth anode 301D at the base have overlapping portions with one vertical line and no overlapping portions with horizontal lines. Therefore, the horizontal and vertical metal lines of the SD3 layer below the main body portions of the third anode 301C and the fourth anode 301D in the three regions are basically the same, the flatness of the third anode 301C and the fourth anode 301D in the three regions can be ensured, and the light-emitting performance of the first green light-emitting device and the second green light-emitting device in the three regions can be basically ensured to be the same. 【0283】 In an exemplary embodiment, the subsequent manufacturing process may include first forming a pixel definition layer pattern, then forming an organic light-emitting layer using a vapor deposition or inkjet printing process, and then forming a cathode on the organic light-emitting layer, and then forming a package structure layer. The package structure layer may include a first package layer, a second package layer, and a third package layer that are stacked and installed. The first package layer and the third package layer may employ inorganic materials, and the second package layer may employ organic materials. The second package layer is installed between the first package layer and the third package layer and can ensure that water vapor from the outside does not penetrate into the light-emitting structure layer. 【0284】 FIG. 23 is a schematic plan view of the power supply wiring of an embodiment of the present disclosure. As shown in FIG. 23, the display substrate may include a display area 100, a binding area 200 located on the Y side in the second direction of the display area 100, and a bezel area 300 located on the other side of the display area 100. The bezel area 300 may include an upper bezel area 310 located on the side opposite to the second direction Y of the display area 100 (away from the binding area 200) and side bezel areas 320 located on one or both sides in the first direction X of the display area 100. A power supply wiring 90 with a mesh communication structure is provided in the display area 100, a binding lead 510 is provided in the binding area 200, an upper bezel lead 520 is provided in the upper bezel area 310, and a side bezel lead 530 is provided in the side bezel area 320. The power supply wiring 90 is connected to the binding lead 510, the upper bezel lead 520, and the side bezel lead 530 respectively. 【0285】 In an exemplary embodiment, the binding lead 510 in the binding area 200, the upper bezel lead 520 in the upper bezel area 310, and the side bezel lead 530 in the side bezel area 320 may be an integral structure connected to each other. 【0286】 In an exemplary embodiment, the power supply wiring 90 of the display area 100 may include a plurality of first power supply wirings 91 extending along the first direction X and a plurality of second power supply wirings 92 extending along the second direction Y. The plurality of first power supply wirings 91 may be sequentially provided along the second direction Y. One or both ends in the first direction X extend to the side bezel area 320 and are then connected to the side bezel lead wire 530. The plurality of second power supply wirings 92 may be sequentially provided along the first direction X. One end in the second direction Y extends to the binding area 200 and is then connected to the binding lead wire 510. One end in the opposite direction of the second direction Y extends to the upper bezel area 310 and is then connected to the upper bezel lead wire 520. 【0287】 FIG. 24 is a connection schematic diagram of the power supply wiring and the binding lead wire in an exemplary embodiment of the present disclosure and is an enlarged view of the D1 area in FIG. 23. As shown in FIG. 24, the binding area 200 may include at least a binding lead wire 510, a first power supply connection wire 511, and a first power supply pin 512. 【0288】 In an exemplary embodiment, the binding lead wire 510 may be provided in the fourth conductive layer (SD2). The shape of the binding lead wire 510 may be a stripe shape extending along the first direction X. The binding lead wire 510 is configured to be connected to the power supply pad of the binding pin. 【0289】 In an exemplary embodiment, the first power supply connection wire 511 and the first power supply pin 512 may be provided in the fifth conductive layer (SD3). The first end of the first power supply connection wire 511 is connected to the second power supply wire 80 extending to the binding area 200 through a via opened in the second flat layer. The second end of the first power supply connection wire 511 extends in a direction away from the display area and is then directly connected to the first power supply pin 512. The first power supply pin 512 is connected to the binding lead wire 510 through a plurality of vias opened in the second flat layer. 【0290】 In an exemplary embodiment, the shape of the first power connection line 511 may be strip-shaped extending along the second direction Y, and the first power pin 512 may be connected to the second power line 80 via a plurality of first power connection lines 511. 【0291】 In an exemplary embodiment, the shape of the first power pin 512 may be strip-shaped extending along the first direction X. The binding lead line 510 located in the fourth conductive layer and the first power pin 512 located in the fifth conductive layer form a two-layer power wiring, minimizing the voltage drop of the power signal and realizing low power consumption. In the present disclosure, by connecting the power wiring in the display area and the binding lead line in the binding area, the width of the binding lead line can be significantly reduced, the width of the binding area can be significantly reduced, which is advantageous for realizing full-screen display. 【0292】 In an exemplary embodiment, the first power connection line 511 and the first power pin 512 may be an integrated structure connected to each other. 【0293】 FIG. 25 is a schematic connection diagram of the power wiring and the upper bezel lead line of an exemplary embodiment of the present disclosure, and is an enlarged view of the D2 area in FIG. 23. As shown in FIG. 25, the upper bezel area 310 may include at least an upper bezel lead line 520, a second power connection bar 521, a second power connection line 522, and a second power pin 523. 【0294】 In an exemplary embodiment, the bezel lead line 520 may be provided in the fourth conductive (SD2) layer, the shape of the upper bezel lead line 520 may be strip-shaped extending along the first direction X, and the upper bezel lead line 520 is configured to be connected to the binding lead line in the binding area via the side bezel lead line in the side bezel area. 【0295】 In an exemplary embodiment, the second power connection bar 521, the second power connection line 522, and the second power pin 523 may be provided in a fifth conductive layer (SD3). The first end of the second power connection bar 521 is connected to a second power line 80 that extends to the upper bezel region 310 through a via opened in the second flat layer. The second end of the second power connection bar 521 is connected to the first end of the second power connection line 522. The second end of the second power connection line 522 is connected to the second power pin 523 after extending in a direction away from the display region. The second power pin 523 is connected to the upper bezel lead line 520 through a plurality of vias opened in the second flat layer. In the present disclosure, by connecting the power wiring in the display region to the upper bezel lead line in the upper bezel region, the width of the upper bezel lead line can be significantly reduced, the width of the upper bezel region can be significantly reduced, which is advantageous for realizing a full-screen display. 【0296】 In an exemplary embodiment, the shape of the second power connection bar 521 may be a stripe shape extending along the first direction X, the shape of the second power connection line 522 may be a stripe shape extending along the second direction Y, the shape of the second power pin 523 may be a rectangle, and the second power connection bar 521 may be connected to the upper bezel lead line 520 through a plurality of second power connection lines 522 and a plurality of second power pins 523. 【0297】 In an exemplary embodiment, the second power connection bar 521, the second power connection line 522, and the second power pin 523 may be an integral structure connected to each other. 【0298】 FIG. 26 is a schematic connection diagram of the power wiring and the side bezel lead line of an exemplary embodiment of the present disclosure, and is an enlarged view of the D3 region in FIG. 23. As shown in FIG. 26, the side bezel region 320 may include at least a side bezel lead line 530, a third power connection line 531, and a third power pin 532. 【0299】 In an exemplary embodiment, the side bezel lead wire 530 may be provided in the fourth conductive (SD2) layer, the shape of the side bezel lead wire 530 may be stripe-shaped extending along the second direction Y, and the side bezel lead wire 530 is configured to be connected to the binding lead wire 510 in the binding region. 【0300】 In an exemplary embodiment, the third power connection line 531 and the third power pin 532 may be provided in the fifth conductive layer (SD3). The first end of the third power connection line 531 is connected to the power wiring 90 of the display region 100 through a via opened in the second flat layer. The second end of the third power connection line 531 extends along a direction away from the display region and is then directly connected to the third power pin 532. The third power pin 532 is connected to the side bezel lead wire 530 through a plurality of vias opened in the second flat layer. In the present disclosure, by connecting the power wiring in the display region and the side bezel lead wire in the side bezel region, the width of the side bezel lead wire can be significantly reduced, the width of the side bezel region can be significantly reduced, which is advantageous for realizing full-screen display. 【0301】 In an exemplary embodiment, the shape of the third power connection line 531 may be a broken line shape extending along the first direction X, the shape of the third power pin 532 may be a stripe shape extending along the second direction Y, and the power wiring 90 may be connected to the side bezel lead wire 530 through a plurality of the third power connection lines 531 and the third power pins 532. 【0302】 In an exemplary embodiment, the third power connection line 531 and the third power pin 532 may be an integral structure connected to each other. 【0303】 As can be seen from the structure and manufacturing process of the display substrate described above, in the present disclosure, by providing data connection lines in the display area, the lead-out lines in the binding area are connected to the data signal lines via the data connection lines, eliminating the need to provide fan-shaped diagonal lines in the lead line area, effectively shortening the length of the lead line area, significantly shortening the width of the lower bezel, improving the screen ratio, and facilitating the realization of full-screen display. 【0304】 In a display substrate, the display area includes a wiring area where data connection lines are provided and a normal area where no data connection lines are provided. Under the irradiation of external light, the data connection lines in the wiring area have high reflectivity, while the reflectivity of other metal lines in the normal area is weak. Therefore, the appearance of the normal area is significantly different from that of the wiring area, resulting in an appearance defect problem in the display substrate. Particularly when the screen is closed or in the case of low-tone display, the appearance defect becomes more obvious. In the embodiments of the present disclosure, by providing second compensation lines in the first area, first compensation lines in the second area, and both first compensation lines and second compensation lines in the third area, different areas basically have the same structure, obtaining basically the same display effect in transmitted light and reflected light in different areas, effectively avoiding the appearance defect of the display substrate, ensuring that the horizontal and vertical metal lines below the anode in the three areas are basically the same, ensuring that the flatness of the anode in the three areas is basically consistent, ensuring that the light-emitting performance of the light-emitting device is basically the same, avoiding color deviation at a large viewing angle, and improving the display attributes and display quality. 【0305】 By providing a first power wiring and a second power wiring that constitute a power wiring of a mesh communication structure within a display area, a VSS in pixel structure can be realized, effectively reducing the resistance of the power wiring, effectively reducing the voltage drop of a low-voltage power signal, and not only realizing low power consumption, but also effectively improving the uniformity of the power signal on the display substrate, effectively improving the display uniformity, and improving the display attributes and display quality. In the present disclosure, by connecting the power wiring to the power lead wires in the binding area and the bezel area, the width of the power lead wires can be significantly reduced, the width of the bezel can be significantly reduced, which is advantageous for realizing full-screen display. The manufacturing process of the present disclosure has good compatibility with the existing manufacturing process, the process is easy to realize and easy to implement, has high production efficiency, low manufacturing cost, and high yield rate. 【0306】 The above-described structure of the present disclosure and its manufacturing process are merely illustrative. In exemplary embodiments, according to actual needs, the corresponding structure can be changed, or the composition process can be added or reduced, and the present disclosure is not limited herein. The above-described structure of the present disclosure and its manufacturing process are merely illustrative. In exemplary embodiments, according to actual needs, the corresponding structure can be changed, or the composition process can be added or reduced, and the present disclosure is not limited herein. 【0307】 In exemplary embodiments, the display substrate of the present disclosure can be applied to a display device having a pixel driving circuit such as, for example, OLED, quantum dot display (QLED), light-emitting diode display (Micro LED or Mini LED), quantum dot light-emitting diode display (QDLED), etc., and the present disclosure is not limited herein. 【0308】 The present disclosure further provides a display device including the aforementioned display substrate. The display device may be any product or component having a display function, such as a mobile phone, a tablet, a television, a display, a notebook computer, a digital photo frame, a navigation device, etc., and the embodiments of the present invention are not limited thereto. 【0309】 The embodiments disclosed in the present disclosure are as described above. However, the described content is only the embodiments adopted for facilitating the understanding of the present disclosure and is not used for limiting the present disclosure. Those skilled in the art can make all modifications and changes in the embodiments and details without departing from the spirit and scope of the present disclosure. However, the scope of patent protection of the present disclosure shall be subject to the scope defined by the appended claims. 【Description of Reference Numerals】 【0310】 【Table 1】

Claims

[Claim 1] A display board, A display board, comprising a display area, the display area comprising a drive circuit layer provided on a base and a light-emitting structure layer provided on the side of the drive circuit layer away from the base, the drive circuit layer comprising a plurality of circuit units, a plurality of data signal lines, a plurality of data connection lines, a plurality of low-voltage power lines and a plurality of power wirings, the light-emitting structure layer comprising a plurality of light-emitting devices, the circuit units comprising pixel drive circuits, the data signal lines configured to supply data signals to the pixel drive circuits, the low-voltage power lines configured to continuously supply low power voltage signals to the light-emitting devices, the data connection lines connected to the data signal lines, and the power wiring connected to the low-voltage power lines. [Claim 2] The display board according to claim 1, wherein the data connection line includes a first connection line extending along a first direction and a second connection line extending along a second direction, the first connection line is connected to the second connection line, the power wiring includes a first power wiring extending along a first direction and a second power wiring extending along a second direction, the first power wiring is connected to the second power wiring, the first direction intersects the second direction, and in a plane parallel to the base, the display area includes a first area where at least the first connection line is provided, and in at least one circuit unit of the first area, the first connection line, the first power wiring and the second power wiring are included, the shape of the data signal line and the low voltage power line is linear extending along the second direction, the first connection line is connected to the data signal line, the second power wiring is installed between the low voltage power line and the data signal line, and the second power wiring is connected to the low voltage power line. [Claim 3] The drive circuit layer includes a plurality of conductive layers sequentially provided on the base, the first connection line and the second connection line are provided on the same conductive layer, the first connection line and the data signal line are provided on different conductive layers, and in at least one circuit unit of the first region, the first connection line is connected to the data signal line via a first connection hole. Or, The display board according to claim 2, wherein the drive circuit layer includes a plurality of conductive layers sequentially provided on the base, the first power wiring and the second power wiring are provided on the same conductive layer, the second power wiring and the low voltage power line are provided on different conductive layers, and in at least one circuit unit of the first region, the second power wiring is connected to the low voltage power line via a second connection hole. [Claim 4] The first region further includes a power connection electrode in at least one circuit unit, the power connection electrode being located on the side of the second power wiring away from the data signal line and connected to the second power wiring, the orthographic projection of the power connection electrode at its base at least partially overlapping with the orthographic projection of the low-voltage power line at its base, and the power connection electrode being connected to the low-voltage power line via a second connection hole. Or, The display board according to claim 2, wherein at least one circuit unit in the first region further includes a second compensation line extending along the second direction, the second compensation line being located on the side of the second power supply wiring away from the data signal line, the second compensation line being connected to the first power supply wiring, the second compensation lines in adjacent circuit units in the second direction being spaced apart, and the first connection line being located between adjacent second compensation lines in the second direction. [Claim 5] In the first region, the first connecting lines in adjacent circuit units in the first direction are connected to each other, and the first power supply wiring in adjacent circuit units in the first direction is connected to each other. Or, The display board according to claim 2, wherein in the first region, the second power supply wiring in adjacent circuit units in the second direction is installed with spacing between them, and the first connection line is installed between the second power supply wiring adjacent in the second direction. [Claim 6] The display board according to claim 2, wherein in a plane parallel to the base, the display area further includes a second area on which the second connection line is provided, the second connection line is included in at least one circuit unit of the second area, and the second connection lines in adjacent circuit units in the second direction are connected to each other. [Claim 7] The display board according to claim 6, wherein at least one circuit unit in the second region includes two second connection lines, the two second connection lines include a first side connection line and a second side connection line, the first side connection line is installed between the low voltage power line and the data signal line, and the second side connection line is installed on the side of the low voltage power line away from the data signal line. [Claim 8] The display board according to claim 7, wherein at least one circuit unit in the second region further includes a dummy connection electrode, the dummy connection electrode is located on the side of the second connection line closer to the first connection line and connected to the second connection line, and the orthographic projection of the dummy connection electrode at the base at least partially overlaps with the orthographic projection of the low-voltage power line at the base. [Claim 9] In at least one row of units including the circuit unit of the first region and the circuit unit of the second region, the second power supply wiring of the first region and the first side connection line of the second region are located on the same straight line extending along the second direction, the second compensation line of the first region and the second side connection line of the second region are located on the same straight line extending along the second direction, the power supply connection electrode of the first region and the dummy connection electrode of the second region are located on the same straight line extending along the second direction, and in at least one row of units including the circuit unit of the first region and the circuit unit of the second region, the power supply connection electrode of the first region and the dummy connection electrode of the second region are located on the same straight line extending along the first direction, the display board according to claim 8. [Claim 10] The display board according to claim 7, wherein at least one circuit unit in the second region further includes at least two first compensation lines extending along the first direction, and at least two first compensation lines include at least one first side compensation line and at least one second side compensation line, the first end of the first side compensation line being connected to the first side connection line, the second end of the first side compensation line extending along a direction toward the second side connection line, the first end of the second side compensation line being connected to the second side connection line, and the second end of the second side compensation line extending along a direction toward the first side connection line. [Claim 11] The display board according to claim 10, wherein in at least one unit row including the circuit unit of the first region and the circuit unit of the second region, the first power supply wiring of the first region and the first side compensation line of the second region are located on the same straight line extending along the first direction, and the first connection line of the first region and the second side compensation line of the second region are located on the same straight line extending along the first direction. [Claim 12] The display board according to claim 2, wherein in a plane parallel to the base, the display area further includes a third area that does not overlap with the orthographic projection of the first connection line and the second connection line on the base, and at least one circuit unit in the third area includes the first power supply wiring and the second power supply wiring, the second power supply wiring is connected to the low voltage power line via a second connection hole. [Claim 13] The display board according to claim 12, further comprising a power connection electrode in at least one circuit unit of the third region, wherein the power connection electrode is located on the side of the second power wiring away from the data signal line and is connected to the second power wiring, the orthographic projection of the power connection electrode at its base at least partially overlaps with the orthographic projection of the low voltage power line at its base, and the power connection electrode is connected to the low voltage power line via a second connection hole. [Claim 14] The display board according to claim 12, wherein at least one circuit unit in the third region further includes a first compensation line extending along the first direction and a second compensation line extending along the second direction, wherein the first compensation lines in adjacent circuit units in the first direction are connected to each other, the second compensation lines in adjacent circuit units in the second direction are connected to each other, the first compensation line is connected to the second power supply wiring, the second compensation line is connected to the first power supply wiring, and the first compensation line is connected to the second compensation line. [Claim 15] The display board according to claim 14, wherein in at least one unit row including the circuit unit of the first region and the circuit unit of the third region, the first connecting line of the first region and the first compensation line of the third region are located on the same straight line extending along the first direction, and in at least one unit row including the circuit unit of the first region and the circuit unit of the third region, the second compensation line of the first region and the second compensation line of the third region are located on the same straight line extending along the second direction. [Claim 16] In a plane parallel to the base, the display area further includes a second area on which the second connection line is provided, and a third area which does not overlap with the orthographic projection of the first connection line and the second connection line on the base, and in at least one unit row including a circuit unit in the first area, a circuit unit in the second area, and a circuit unit in the third area, the first power supply wiring in the first area, the first side compensation line in the first compensation line of the second area, and the first power supply wiring in the third area are located on the same straight line extending along the first direction, and the first connection line in the first area, the second side compensation line in the first compensation line of the second area, and the first compensation line in the third area are located on the same straight line extending along the first direction, and the power supply connection electrode in the first area, the dummy connection electrode in the second area, and the third The display board according to claim 2, wherein the power connection electrodes of the regions are located on the same straight line extending along a first direction, and in at least one row of units including a circuit unit of the first region, a circuit unit of the second region, and a circuit unit of the third region, the second power wiring of the first region, the first side connection line of the second connection line of the second region, and the second power wiring of the third region are located on the same straight line extending along the second direction, the second compensation line of the first region, the second side connection line of the second connection line of the second region, and the second compensation line of the third region are located on the same straight line extending along the second direction, and the power connection electrodes of the first region, the dummy connection electrodes of the second region, and the power connection electrodes of the third region are located on the same straight line extending along the second direction. [Claim 17] The display board further includes a binding region located on the second direction side of the display area, the binding region including at least a binding lead wire, a first power connection wire and a first power pin, the first end of the first power connection wire connected to the low voltage power line via a via, the second end of the second power connection wire extending away from the display area and then connected to the first power pin, the first power pin connected to the binding lead wire via a via, Or, The display board further includes an upper bezel region located on the side opposite to the second direction of the display area, the upper bezel region includes at least an upper bezel lead wire, a second power connection bar, a second power connection line, and a second power pin, the first end of the second power connection bar is connected to the low voltage power line via a via, the second end of the second power connection bar is connected to the first end of the second power connection line, the second end of the second power connection line extends along the direction away from the display area and is then connected to the second power pin, and the second power pin is connected to the upper bezel lead wire via a via. Or, The display board according to claim 2, further comprising a side bezel region located on one or both sides of the first direction of the display area, the side bezel region comprising at least a side bezel lead wire, a third power connection wire, and a third power pin, the first end of the third power connection wire being connected to the power wiring via a via, the second end of the third power connection wire being connected to the third power pin after extending in a direction away from the display area, and the third power pin being connected to the side bezel lead wire via a via. [Claim 18] The display substrate according to claim 1, wherein the pixel driving circuit includes at least a memory capacitor and a plurality of transistors, and in a plane perpendicular to the base, the driving circuit layer includes a semiconductor layer, a first conductive layer, a second conductive layer, a third conductive layer, a fourth conductive layer and a fifth conductive layer sequentially provided on the base, the semiconductor layer includes the active layers of at least a plurality of transistors, the first conductive layer includes the gate electrodes of at least a plurality of transistors and the first electrode plate of the memory capacitor, the second conductive layer includes at least the second electrode plate of the memory capacitor, the third conductive layer includes the first and second electrodes of at least a plurality of transistors, the fourth conductive layer includes at least the data signal line and the low voltage power supply line, and the fifth conductive layer includes at least the data connection line and the power supply wiring. [Claim 19] The third conductive layer further includes a first power line, the first power line is configured to continuously supply a high power voltage signal to the pixel driving circuit, the orthographic projection of the base of the low-voltage power line at least partially overlaps with the orthographic projection of the base of the first power line and has a first overlapping area, the orthographic projection of the base of the first power line has a first area, and the first overlapping area is greater than 0.8 * first area. Or, The display substrate according to claim 18, wherein the second conductive layer further includes a second initial signal line, the second initial signal line is configured to supply a second initial signal to the pixel driving circuit, the orthographic projection of the first connection line at the base of the data connection line at least partially overlaps with the orthographic projection of the second initial signal line at the base and has a second overlapping area, the orthographic projection of the first connection line at the base has a second area, and the second overlapping area is greater than 0.8 * second area. [Claim 20] A display device comprising the display board described in claim 1.

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