Differential voltage-mode driver for microwave assisted magnetic recording

Abstract

To provide an apparatus and method for enabling rapid transitions during microwave assisted magnetic recording (MAMR) of a storage medium.SOLUTION: In the differential vMode driver for MAMR, the MAMR sensor related circuitry 310 includes a MAMR _ P node 312, a MAMR _ N node 314, a damping element 316, a capacitive element 318, and a resistive element 320. The MAMR _ P and MAMR _ N nodes establish direct connection points between the MAMR sensor driver circuitry and the MAMR sensor. The MAMR _ P node serves as the field inflow terminal through which current ultimately flows from the power supply into the MAMR sensor (resistive element). The MAMR _ N node functions as a field drain terminal, where current drains away from the MAMR sensor and eventually towards ground. These nodes receive a controlled differential voltage produced by the MAMR sensor driver circuitry, which in turn establishes current flow for proper MAMR operation.SELECTED DRAWING: Figure 3

Description

[Background technology]

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS This disclosure claims priority to U.S. Provisional Patent Application No. 63 / 662,967, filed June 21, 2024, the disclosure of which is incorporated herein by reference in its entirety.

[0002] In the field of data storage technology, some hard disk drives (HDDs) utilize microwave-assisted magnetic recording (MAMR) using MAMR sensors (e.g., spin torque oscillators) to generate microwave fields when writing or erasing data. These microwave fields provide supplemental energy during the write / erase process, thereby temporarily reducing the energy barrier for magnetic switching. As a result, MAMR-enabled HDDs can use smaller write heads while magnetizing increasingly dense storage media that would be difficult to alter using conventional recording methods. Furthermore, MAMR technology enables HDDs to continue increasing areal densities while maintaining data integrity and readability.

[0003] HDDs using MAMR technology write data throughout their operation by positioning the head over a defined track on the rotating disk platter. First, the write head, assisted by a microwave field from the MAMR sensor, generates a magnetic field to align magnetic domains on the disk surface into a pattern representing binary data. Meanwhile, as the disk rotates at high speed, the head alternates between data sectors and servo sectors containing positioning information. Additionally, each rotation requires the read / write head to transition between writing data and reading servo sectors multiple times, which occurs frequently (e.g., approximately every 50–100 microseconds). MAMR circuitry controls the timing of magnetic field generation during these transitions, requiring only a few microseconds to complete the transition from write mode to servo read mode for the next sector. Because the MAMR sensor's demagnetization period can take up to 20 nanoseconds, the MAMR circuitry often cannot complete the demagnetization before the next transition to servo mode, resulting in additional read attempts and associated delays. Summary of the Invention

[0004] This Summary is provided to introduce subject matter that is further described in the Detailed Description and Drawings. As such, this Summary itself should not be considered to describe essential features, nor should it be used to limit the scope of the claimed subject matter.

[0005] In various aspects, an apparatus for facilitating high-speed transitions during microwave-assisted magnetic recording (MAMR) includes a driver circuit configured to provide a controlled bias current, the driver circuit having separate source and sink output terminals and responsive to a feedback signal. A MAMR sensor is coupled between the source and sink output terminals, through which the MAMR sensor receives the controlled bias current provided by the driver circuit, where the MAMR sensor is configured to generate a microwave field. The apparatus includes a common-mode feedback (CMFB) loop coupled to the source and sink output terminals of the driver circuit, the CMFB loop configured to detect a common-mode voltage (CMV) and provide a feedback signal to the driver circuit, thereby maintaining CMV regulation of the MAMR sensor. Additionally, a differential voltage regulation loop is coupled to the source and sink output terminals of the driver circuit, the differential voltage regulation loop configured to provide a feedback signal to maintain a voltage difference across the MAMR sensor at a reference value.

[0006] In some embodiments, a hard disk drive system that facilitates high-speed transitions during MAMR includes a write head including a MAMR sensor. The hard disk drive system also includes voltage-mode (vMode) driver circuitry configured to drive a differential voltage across the MAMR sensor. The vMode driver circuitry includes a driver circuit responsive to a feedback signal and having separate source and sink output terminals between which the MAMR sensor is coupled. A common-mode feedback (CMFB) loop is coupled to the source and sink output terminals of the driver circuit, the CMFB loop configured to detect a common-mode voltage (CMV) and provide a feedback signal to the driver circuit to maintain CMV regulation of the MAMR sensor. A differential voltage regulation loop is coupled to the source and sink output terminals of the driver circuit, the differential voltage regulation loop configured to provide a feedback signal to maintain a voltage difference across the MAMR sensor at a reference value.

[0007] In another aspect, a method for facilitating fast transitions during MAMR includes operations for controlling a MAMR sensor. The method includes providing a reference voltage difference that establishes target operating parameters. The method provides a bias current to a MAMR sensor of a magnetic media read / write channel through a driver circuit, enabling microwave field generation within a specified operating range. A common-mode feedback (CMFB) loop couples to drive the circuit to maintain the common-mode voltage (CMV) regulation of the MAMR sensor at approximately zero volts. Through a monitoring and adjustment process, the method maintains the voltage difference across the MAMR sensor at the reference value, thereby ensuring operational stability. The method switches the voltage difference across the MAMR sensor with rise and fall times of 20 nanoseconds or less, thereby enabling a rapid deactivation sequence that prevents residual magnetic field interference.

[0008] The details of one or more implementations are set forth in the accompanying drawings and the description below. Other features and advantages will be apparent from the description and drawings, and from the claims. [Brief explanation of the drawings]

[0009] The details of one or more implementations of a differential voltage-mode (vMode) driver for microwave-assisted magnetic recording (MAMR) of storage media are outlined in the accompanying figures and the detailed description below. In the figures, the left-most digit of a reference number indicates the figure in which the reference number first appears. When the same reference number is used in different places in the description and figures, it refers to the same element. [Figure 1] 1 illustrates an exemplary operating environment having devices in which a differential vMode driver may be implemented. [Figure 2] An exemplary configuration of a hard disk drive is illustrated in FIG. 1 with a MAMR-enabled write head. [Figure 3] FIG. 10 is an example schematic diagram of the circuitry of an example implementation of a differential vMode driver for MAMR. [Figure 4] 1 depicts an example method for differential vMode driving a MAMR sensor in accordance with one or more aspects. [Figure 5] 1 illustrates an exemplary system-on-chip (SoC) that may implement various aspects of a differential vMode driver for MAMR. [Figure 6] 1 illustrates an exemplary storage media controller in accordance with one or more aspects of a differential vMode driver for MAMR. DETAILED DESCRIPTION OF THE INVENTION

[0010] Hard disk drive (HDD) systems using microwave-assisted magnetic recording (MAMR) technology typically exhibit operational issues related to MAMR sensor deactivation or transition timing. Generally, HDDs using MAMR technology write data throughout their operation by positioning a head over a defined track on a rotating disk platter. First, the write head, assisted by a microwave field from the MAMR sensor, generates a magnetic field to align magnetic domains on the disk surface into a pattern representing binary data. Meanwhile, as the disk rotates at high speed, the head alternates between data sectors and servo sectors containing positioning information. Additionally, each rotation requires the read / write head to transition between writing data and reading servo sectors multiple times, which occurs frequently (e.g., approximately every 50–100 microseconds). MAMR circuitry controls the magnetic field generation during these transitions, requiring only a few microseconds to complete the transition from write mode to servo read mode for the next sector.

[0011] In some cases, MAMR sensors in hard disk drive write heads fail to fully deactivate before the write head moves to a new location. This failure can result in residual magnetic fields that persist during head movement, which can alter data stored on the disk surface as the head advances. Furthermore, servo pattern corruption reduces track location accuracy in drive system addressability, such as in high-density storage configurations with minimal track spacing that are susceptible to positioning errors. These positioning inaccuracies can initially cause isolated data corruption and ultimately lead to drive failure due to the system's inability to accurately locate tracks.

[0012] These deactivation timing issues are most evident during the write-to-servo transition, during which, after a write operation is completed, the write head must be deactivated to read servo positioning information from a dedicated disk area. Typically, this servo read process can take approximately 20 nanoseconds (ns) to complete, and each rotation requires the read / write head to transition between writing data and reading servo sectors multiple times, which occurs frequently (e.g., approximately every 50-100 microseconds). Because the MAMR sensor demagnetization period can take up to 20 ns, the MAMR circuitry often cannot complete demagnetization before the next transition to servo mode, resulting in corrupted servo patterns and positioning errors.

[0013] For example, in hard disk drives utilizing previous versions of MAMR technology, operational issues can occur during write head transition periods as the write head moves from one location to another on the media disk. Prior to this transition period, the write head should be fully deactivated to remove any residual magnetic fields. Without full deactivation, the write head retains lingering, unwanted residual magnetism that unintentionally alters data on the media disk. As a result, this alteration potentially corrupts data that was not intended to be altered.

[0014] This unwanted residual magnetism leads to a phenomenon known as pole erasure, in which a magnetic field exists even in the absence of an active write signal, gradually corrupting data on the media disk. Additionally, pole erasure creates problems when it affects the servo area because the servo pattern provides positioning information for the entire hard disk drive system. Repeated exposure to these residual fields degrades the servo positioning data as the magnetic pattern changes. Because the positioning system relies on accurate servo patterns to locate tracks, errors accumulate over time. Ultimately, the hard disk drive system cannot reliably locate specific data tracks, thereby leading to complete drive failure rather than isolated data corruption.

[0015] Sensor write heads in previous versions of MAMR technology typically use a closed-loop voltage system with a voltage feedback circuit that maintains voltage levels. These previous versions of write heads take longer (e.g., hundreds of nanoseconds) to deactivate than the time required to read / write servo positioning information (e.g., approximately 20 nanoseconds). As a result, this timing mismatch means that previous versions of MAMR write heads continue to generate residual magnetic fields long after they have been triggered to deactivate. The timing mismatch issue compromises the drive system's addressing mechanism, which enables the hard disk drive system to locate and access specific data, thereby creating reliability and data integrity issues. This impact is particularly acute in high-density recording scenarios, where track spacing is minimal and positioning accuracy specifications are very stringent.

[0016] In contrast to previous techniques, this disclosure describes aspects of a differential voltage mode (vMode) driver that enables control of the magnetic recording process of a MAMR sensor with very fast transition times. In various aspects, the MAMR control circuitry can include a vMode driver with a driver circuit, a common-mode feedback (CMFB) loop, and a differential voltage regulation loop. The CMFB loop is configured to detect the common-mode voltage (CMV) and provide a feedback signal to the driver circuit, thereby maintaining CMV regulation of the MAMR sensor. The differential voltage regulation loop is configured to provide a feedback signal and maintain the voltage difference of the MAMR sensor at a reference value. As described herein, the vMode driver and associated circuitry enable rapid deactivation and / or transition of the MAMR sensor with shorter demagnetization periods (e.g., less than 20 ns), which reduces residual magnetic fields that persist during head movement and prevents corruption of the servo pattern.

[0017] The following discussion describes the operating environment, techniques that may be employed in the operating environment, and hard disk drive systems in which components of the operating environment may be embodied. In the context of this disclosure, references to the operating environment are made by way of example only.

[0018] 1 illustrates an exemplary operating environment 100 having a computing device 102 (e.g., a host device) that can store or access data on various storage devices, such as magnetic media-based drives. Examples of computing device 102 may include a laptop computer 104, a desktop computer 106, and a server 108, any of which may be configured as part of a storage network or cloud storage. Additionally, examples of computing device 102 (not shown) may include tablet computers, set-top boxes, data storage appliances, wearable smart devices, televisions, content streaming devices, high-definition multimedia interface (HDMI®) media sticks, smart appliances, home automation controllers, smart thermostats, Internet-of-Things (IoT) devices, mobile-internet devices (MIDs), network-attached-storage (NAS) drives, aggregate storage systems, game consoles, automotive entertainment devices, automotive computing systems, and automotive control modules (e.g., engine or powertrain control modules), among others.

[0019] In general, computing device 102 may provide, communicate, or store data for any suitable purpose, such as contributing to the functionality of a particular type of device, providing a user interface, enabling network access, implementing gaming applications, playing media, providing navigation, editing content, or providing data storage. Alternatively or additionally, computing device 102 may store a variety of data, such as databases, user data, multimedia, applications, operating systems, etc. One or more computing devices 102 may be configured to provide remote data storage or services, such as cloud storage, archiving, backup, client services, record keeping, etc.

[0020] In an implementation, the computing device 102 includes a processor 110 and a computer-readable storage medium 112. The processor 110 may be implemented as any suitable type or number of processors, either single-core or multi-core (e.g., ARM or x86 processor cores), for executing instructions or commands of the computing device's 102 operating system or other programs. The computer-readable storage medium 112 (CRM 112) includes a memory medium 114 and a media drive 116. The memory medium or system memory of the computing device 102 may include any suitable type or combination of volatile or non-volatile memory. For example, the volatile memory of the computing device 102 may include various types of random-access memory (RAM), dynamic RAM (DRAM), or static RAM (SRAM), etc. Non-volatile memory may include read-only memory (ROM), electronically erasable programmable ROM (EEPROM), or flash memory (e.g., NOR flash or NAND flash), which, alone or in combination, may store data associated with applications and / or the operating system of computing device 102.

[0021] The media drive 116 of the computing device 102 may include one or more media drives or may be implemented as part of a data storage system associated with the computing device 102. In this example, the media drive 116 includes a hard disk drive system 118 (HDD system 118), which may store data and is described with reference to various aspects of the Differential vMode driver. Alternatively or additionally, the media drive 116 may be configured as any suitable type of data storage drive or system, such as a storage device, storage drive, storage array, or storage volume. Although described with reference to the computing device 102, the media drive 116 may also be implemented separately as a standalone device or as part of a larger storage collection, such as a data center, server farm, or virtualized storage system (e.g., cloud-based storage or service), in which aspects of the Differential vMode driver are implemented.

[0022] Computing device 102 may also include I / O ports 120, a graphics processing unit (GPU, not shown), and a data interface 122. Generally, I / O ports 120 allow computing device 102 to interact with other devices, peripherals, or a user. For example, I / O ports 120 may include or be coupled to a universal serial bus, a human interface device, audio input, or audio output, etc. The GPU processes and renders graphics-related data for computing device 102, such as user interface elements of an operating system or an application. In some cases, the GPU accesses a portion of local memory to render graphics or includes dedicated memory (e.g., video RAM) for rendering graphics for computing device 102.

[0023] The data interface 122 of the computing device 102 provides a connection to one or more networks and other devices connected to these networks. The data interface 122 may include a wired interface, such as an Ethernet or fiber optic interface, for communicating data over a local network, an intranet, or the Internet. Alternatively or additionally, the data interface 122 may include a wireless interface that facilitates communication over a wireless network, such as a wireless LAN, a wide-area wireless network (e.g., a cellular network), and / or a wireless personal-area network (WPAN). Any data communicated through the I / O ports 120 or the data interface 122 may be written to or read from a storage system of the computing device 102 in accordance with one or more aspects of a differential vMode driver for the MAMR of the storage medium.

[0024] Returning to the media drive 116, the computing device 102 may include the illustrated HDD system 118 and / or other types of storage media devices in which a differential vMode driver may be implemented. Although not shown, other configurations of the media drive 116 are also contemplated, such as solid-state drives (SSDs), magnetic tape drives, optical media drives, HDD / SSD hybrid drives, and other storage systems that write data to a storage medium (e.g., a magnetic storage medium or an optical storage medium). Alternatively or additionally, the computing device 102 may include an array of media drives in which aspects of a differential vMode driver may be implemented, or may function as a media drive aggregate device or host for multiple media drives.

[0025] In this example, HDD system 118 includes a head-disk assembly 124 (HDA 124) and a drive control module 126 for implementing or enabling the functionality of HDD system 118. In some cases, drive control module 126 is implemented as a printed circuit board assembly (PCBA) with semiconductor devices, logic, or other circuitry. HDA 124 includes one or more media disks 128 mounted on an integrated spindle and motor assembly 130. Spindle and motor assembly 130 may rotate media disks 128 below (or above) read / write heads 132 coupled to a head assembly (not shown) of HDA 124. Media disks 128 may be coated with a magnetically hard material (e.g., a particulate or thin-film surface) and may be written to or read from on one or both sides.

[0026] The read / write heads 132 of the HDD system 118 function as magnetic transducers that write data to and read data from magnetic storage media. These heads work in conjunction with associated amplification and control circuitry to perform data transfer operations across the disk surface. The read / write heads 132 integrate with other system components to enable advanced recording technologies, including microwave-assisted magnetic recording capabilities, which enhance storage density and performance. The read / write heads 132 may include a MAMR sensor 134.

[0027] Preamplifier / writer 138 may receive or store head selection, amplification, and sense current values ​​useful for writing data to or reading data from magnetic media. Read / write head 132 and / or preamplifier / writer 138 may be configured to function in concert with other components of hard disk drive system 118 to implement aspects of a differential vMode driver for MAMR of storage media.

[0028] In embodiments, the preamplifier / writer 138 can include MAMR sensor drive circuitry 136 for implementing MAMR, which generates a microwave field when writing or erasing data. The MAMR sensor drive circuitry 136 can be configured to drive a differential bias current through terminals of the MAMR sensor 134 of the write head. In some embodiments, the MAMR sensor drive circuitry 136 includes a driver circuit (e.g., a high-speed switching driver circuit) coupled to a power connection. Depending on the implementation, the power connection can include a power and ground pair or a positive and negative power pair.

[0029] The driver circuitry includes separate source and sink output terminals through which the driver circuitry provides a controlled differential bias current to the MAMR sensor 134. The MAMR sensor drive circuitry 136 also includes common-mode feedback (CMFB) loops independently coupled to the terminals of the MAMR sensor, the CMFB loops configured to maintain common-mode voltage (CMV) regulation of the MAMR sensor.

[0030] The read / write heads 132 may be operably coupled to a preamplifier / writer module 138 (preamp / writer 138) of the HDA 124, which includes preamplifier circuitry for amplifying the write or read signals of the read / write heads 132. As shown in FIG. 1 , the exemplary drive control module 126 of the HDD system 118 includes a storage media controller 140, a servo control unit 142, and a read / write channel 144 (read / write: R / W channel 144). Generally, the storage media controller 140 enables the computing device 102 to access the contents of the magnetic storage medium of the media drive 116, such as data or other services for the operating system, applications, or applications. The storage media controller 140 may also write and read data for the computing device 102 to and from the magnetic storage medium of the media drive 116. In some cases, the drive control module 126 directs or uses a servo control unit 142 to control mechanical operations, such as positioning of the read / write head 132 through the HDA 124 and rotational speed control through the spindle and motor assembly 130.

[0031] The servo control unit 142 directs the mechanical positioning of the read / write head 132 over a particular track on the media disk 128. The servo control unit 142 moves the read / write head 132 to a location across the magnetic media in the HDA 124. Additionally, the servo control unit 142 adjusts the rotational speed of the media disk 128 through the spindle and motor assembly 130. The read / write channel 144 may include digital-to-analog and analog-to-digital paths for converting write data into write signals or read signals into read data, respectively. For example, the read / write channel 144 may process and encode signals when data, such as sectors of user data, is written to the media disk 128 as a pattern of code words or bits. Alternatively or additionally, the read / write channel 144 may process and decode signals when encoded data, such as code words or bits, is read from multiple sectors of the media disk 128.

[0032] This signal processing, encoding, and / or decoding of the write or read signals may include signal conditioning, sampling, equalization, phase adjustment, detection, or error correction, etc. Drive control module 126 or components thereof may be implemented as one or more IC chips, systems-on-chips, systems-in-packages, or microprocessors with or implementing a hard disk drive controller. Drive control module 126 may also include drive electronics (not shown) and / or various interfaces, such as a host bus interface, a storage media interface, a spindle interface, or a preamp / writer interface.

[0033] The read / write channel 144 converts digital computer data into analog magnetic patterns and vice versa. When writing, the read / write channel 144 converts digital data into code words with error correction capabilities. The read / write channel 144 converts these digital code words into analog electrical signals that create magnetic patterns across a magnetic medium consisting of multiple disk sectors. Each sector of the disk medium may contain partitions that hold specific code words or data blocks according to the pattern of bits written to the magnetic medium. Digital-to-analog conversion involves timing to create the correct magnetic patterns. When reading, magnetic changes on the disk generate analog electrical signals. These signals undergo amplification before processing. The analog signals undergo a detection process that converts them into a digital bit stream. During analog-to-digital conversion, the read / write channel 144 uses synchronization marks to identify code word or block boundaries. After conversion, the read / write channel 144 then decodes these code words into the original user data.

[0034] Figure 2 illustrates at 200 an exemplary configuration of HDD system 118 shown in Figure 1. As shown in Figure 2, in an implementation, HDA 124 of HDD system 118 includes an integrated spindle and motor assembly 130, by which media disk 128 of magnetic media 202 is supported and / or moved. Servo control unit 142 directs movement of arm 204, thus positioning read / write head 132 (or multiple read / write heads 132) over a desired track 206 of magnetic media 202 on media disk 128.

[0035] Media disk 128 includes dedicated servo areas 210 (e.g., servo area 210) with positioning information recorded on magnetic medium 202. These servo areas (e.g., servo area 210) appear at intervals around each track 206 and provide reference markers that help read / write head 132 maintain alignment. The servo areas store patterns that encode track numbers, sector identifiers, and positioning offsets. When read / write head 132 passes over these servo areas, the resulting signals go to preamplifier / writer 138 for processing. Servo control unit 142 uses this position data (e.g., servo information) to calculate corrections and / or track the location of sectors across the disk surface. Accurate interpretation of the servo positioning information allows the system to access the specific sectors 208 where data resides.

[0036] Write-to-servo transitions occur periodically as read / write channel 144 converts data into error-corrected code words (or bits) that are written to sectors 208 of the magnetic media. While writing along track 206, servo control unit 142 temporarily suspends writing to evaluate position, so that write current to read / write heads 132 stops as they move over the servo area. During this pause, timing recovery circuitry can adjust the sampling phase to read the servo signals, which allows servo control unit 142 to reposition actuator arm 204 before continuing writing in subsequent sectors 208.

[0037] In general, read / write head 132 may include various numbers of head elements with combined or separate functions (e.g., dedicated R / W functions). For example, read / write head 132 may include one or more readers (read heads / elements) and one writer (write head / element). In other cases, read / write head 132 may include a dedicated write head (element) and one or more separate additional dedicated read heads (elements).

[0038] 2, the HDA 124 or spindle and motor assembly may be implemented with a single arm 204 or other suitable structure for positioning the read / write head 132. The HDA 124 and drive control module 126 may be implemented separately, on separate boards, and / or as separate PCBAs in the media drive. Signals or data communicated between the HDA 124 and drive control module 126 may be carried through a flexible printed cable or other suitable connection structure, such as traces, connectors, bond wires, or solder balls.

[0039] During operation, HDD system 118 alternates between two main functions: track seeking and track following. During track seeking, read / write head 132 moves from a current track (e.g., track 206) to a destination track. Subsequently, during track following, read / write head 132 maintains a position as close as possible to the track center while reading or writing information. Furthermore, by comparing the amplitude balancing between the inner and outer bits in the servo pattern, a positioning error signal (PES) is produced, which determines how accurately read / write head 132 is centered over track 206.

[0040] Writing data involves applying a magnetic field through write head 220 of read / write head 132 to align magnetic domains on media disk 128 into a pattern representing binary data. Additionally, erasing data acts as a special form of data writing in which existing data receives a new pattern that resets the magnetic domains to a different state. In Perpendicular Magnetic Recording (PMR) technology, the magnetic domains are aligned perpendicular to the disk surface, thus increasing storage density.

[0041] 2 also includes an illustration of exemplary sectors 208 configured to store data to be written to the magnetic medium 202 of the media disk 128. One or more of the read / write heads 132 may write data (e.g., user data or codewords) to respective sectors 208 (e.g., sectors of track 206) of the tracks 206 of the media disk 128. For illustrative purposes, the above media disk 128 is shown to include the tracks 206 after the sectors 208 of data have been written thereto by, for example, the read / write heads 132.

[0042] Generally, during a write operation, the read / write head 132 may be driven by a write current provided by the preamplifier / writer 138, whereby an electrical signal is used to generate and / or transfer to the media disk 128 a magnetic field having an associated polarity of the encoded bits. In response to the application of the magnetic or write field, the read / write head 132 may form a plurality of magnetizations corresponding to the encoded data (e.g., user data) within the magnetic grains of the sectors 208 of the media disk 128. The HDA 124 of the HDD system 118 may be configured to perform write operations according to any suitable recording technology, such as, for example, perpendicular magnetic recording (PMR), shingled magnetic recording (SMR), heat-assisted magnetic recording (HAMR), or MAMR.

[0043] One or more implementations of the techniques described herein use MAMR technology in conjunction with a write head 220 and / or a preamplifier / writer 138 of a read / write head 132 to write and erase data on a media disk 128. The MAMR-based write head 220 includes a write head assembly 222, a write coil 224, a write gap 226 (or opening), and a MAMR sensor 134. In an aspect, a MAMR sensor drive circuitry 136 is connected to the MAMR sensor 134 and is either part of or connected to the preamplifier / writer 138.

[0044] The write head assembly 222 may provide a structural framework that houses all other elements of the write head 220. Additionally, the write head assembly 222 may also provide mechanical stability while ensuring proper alignment of the magnetic components with respect to the surface of the media disk 128. In some cases, the write head assembly 222 incorporates shielding to prevent electromagnetic interference between adjacent components.

[0045] The write head assembly's write coil 224 can be configured as a tightly wound conductive structure (e.g., typically copper) that generates a primary magnetic field in response to the application of an electric current. When an electric current flows through the write coil 224, the resulting electromagnetic field propagates through the write gap 226. The write coil 224 then converts electrical energy into magnetic energy that changes magnetic domains on the disk surface during the writing process. The strength of the magnetic field generated by the write coil 224 varies proportionally with the amount of electric current applied.

[0046] The write gap 226 (or opening) creates a controlled discontinuity between the magnetic pole structures of the write head 220. This allows magnetic flux to escape from the internal components. The write gap 226 allows the magnetic field generated by the write coil 224 to extend outward toward the magnetic media 202 beneath the write head 220. During operation, the magnetic field projects through the write gap 226 with sufficient strength to magnetize domains on the media disk 128 below.

[0047] The dimensions of the write gap 226 can directly affect the field strength, concentration, and recording accuracy on the magnetic media 202. Therefore, the write gap 226 can be configured to balance several factors, including field projection characteristics and mechanical stability, while maintaining a constant distance from the recording surface of the media disk 128. When a current flows through the write coil 224, the resulting electromagnetic field 212 extends through the write gap 226 to the sector 208 of the media disk 128.

[0048] The MAMR sensor 134 functions as the microwave-generating element in the MAMR-based write head 220. The MAMR sensor 134 operates as a spin-torque oscillator, utilizing electron spin properties to generate a high-frequency assist field. Additionally, the MAMR sensor 134 can generate oscillations in the 20-40 GHz range when properly excited by a differential current from a current-mode (vMode) driver implementation of the MAMR sensor drive circuitry. Furthermore, the MAMR sensor 134 provides supplemental energy to the magnetic field from the write coil 224, enabling higher-density recording on magnetic media 202 that would otherwise resist magnetization. The MAMR sensor 134 includes a resistive element with microwave field generation in response to current flow.

[0049] Within the write gap 226, the MAMR sensor 134 can be positioned to optimize or control field interaction with the disk surface. The write gap 226 positions the MAMR sensor 134 so that both the main magnetic field and the microwave field can effectively couple before reaching the magnetic medium 202. Thus, during a write operation, fields from both the write coil 224 and the MAMR sensor 134 project simultaneously through the write gap 226. When the read / write head 132 transitions between writing data and reading servo areas 210, both the write coil 224 and the MAMR sensor 134 need to be quickly turned off to prevent residual fields from affecting the positioning information stored in these servo areas 210. However, with conventional approaches, the transition or demagnetization time between write and read modes of the MAMR sensor may not be fast enough.

[0050] In an embodiment, the MAMR sensor driver circuitry 136 functions as an electronic control system for the MAMR sensor 134. The MAMR sensor driver circuitry 136 can drive the sensor by delivering a controlled current or voltage to the MAMR sensor 134. As a result, the MAMR sensor 134 generates microwave oscillations, and the MAMR sensor driver circuitry 136 coordinates the timing of activation and deactivation with write operations. Various implementations of the MAMR sensor driver circuitry 136 can include a power conditioning component 232, a signal generation circuit 234, a control logic section 236, an interface circuit 238, and a feedback mechanism 240. The power conditioning component 232 can be configured to provide a stable electrical input to the MAMR sensor 134. The signal generation circuit 234 generates specific electrical patterns used for proper operation of the sensor. The control logic section 236 manages the timing of various operations of the MAMR-based write head 220.

[0051] The interface circuits 238 may serve as a communication pathway that translates control signals (e.g., write enable signals) from the drive control module 126 into specific electrical commands for the MAMR sensor 134. Additionally, these interface circuits establish connections with multiple systems, including the preamplifier / writer 138, the servo control unit 142, and timing systems, contributing to synchronized operation across the overall HDD system 118. The MAMR sensor driver circuitry 136 may also incorporate feedback mechanisms 240 that continuously monitor performance parameters. These feedback systems facilitate maintaining improved operation under varying conditions.

[0052] The architecture of the MAMR sensor driver circuitry 136 typically follows either a voltage-mode (e.g., vMode) or current-mode (e.g., iMode) approach. In a voltage-mode configuration, the circuitry controls a specific voltage level across the MAMR sensor 134. Conversely, a current-mode approach adjusts the amount of current flowing through the MAMR sensor 134. Each approach offers different characteristics in terms of response time, stability, and power efficiency. Regardless of the approach, the MAMR sensor driver circuitry 136 enables writing to magnetic materials while deactivating fast enough to prevent residual magnetic fields that could otherwise corrupt data on the magnetic media 202 of the media disk 128.

[0053] 3 is a schematic diagram of an example circuitry for a MAMR-based write head 220 and MAMR sensor driver circuitry 136. As shown, the MAMR sensor 134 is part of the write head 220. The MAMR sensor driver circuitry 136 is part of or connected to a preamp / writer 138. FIG. 3 also shows MAMR sensor-related circuitry 310, which may be part of the write head 220, the preamp / writer 138, and / or some other component, in whole or in part.

[0054] 3 as a resistive element coupled between a MAMR_P node 312 and a MAMR_N node 314. This resistive element functions as a spin torque oscillator and generates microwave oscillations when excited by a differential current from the MAMR sensor driver circuitry 136. The physical resistive properties of this element determine the voltage-current relationship developed across the MAMR sensor 134 during operation.

[0055] As shown in FIG. 3 , MAMR sensor-related circuitry 310 is electrically coupled to the MAMR sensor 134. The MAMR sensor-related circuitry 310 includes several interconnected components, such as a MAMR_P node 312, a MAMR_N node 314, a damping element 316, a capacitive element 318, and a resistive element 320. The MAMR_P node 312 and the MAMR_N node 314 establish a direct connection between the MAMR sensor driver circuitry 136 and the MAMR sensor 134. The MAMR_P node 312 serves as a field input terminal through which current ultimately flows from the power source into the MAMR sensor 134. Conversely, the MAMR_N node 314 serves as a field output terminal through which current ultimately flows out of the MAMR sensor 134 toward ground. These nodes receive a controlled differential voltage created by the MAMR sensor driver circuitry 136, which in turn establishes the current flow for proper MAMR operation.

[0056] Adjacent or adjacent to the MAMR sensor 134 is a damping element 316, which is a resistive element that suppresses high-frequency oscillations or resonances that would otherwise occur within the MAMR sensor driver circuitry 136. By placing a controlled impedance in the current path, the damping element 316 suppresses ringing effects during fast transitions, thereby preserving signal integrity during fast switching transitions. The damping element 316 also contributes to overall system stability by suppressing unwanted parasitic oscillations that would otherwise degrade write performance.

[0057] The MAMR sensor-related circuitry 310 may further include a single-ended capacitor on the capacitive element 318 coupled to the terminals of the MAMR sensor 134. The capacitive element 318 performs frequency compensation by creating a predetermined time constant for signal processing. Additionally, the single-ended capacitor also stabilizes the feedback signal by filtering out transient noise and passing the intended differential signal with minimal attenuation. Based on the coupling location and proper sizing, these capacitive devices can help improve overall system stability under steady-state conditions and during transient switching events.

[0058] Resistive element 320 is positioned between attenuation element 316 and terminals 312 / 314. Resistive element 320 serves to establish a voltage divider network that maintains appropriate signal levels throughout the sensor's operating range. Capacitive element 318 and resistive element 320 together create a combined resistive-capacitive effect that produces a well-defined frequency response characteristic at the interface of MAMR sensor 134 with MAMR sensor driver circuitry 136. This can enable signal integrity throughout the fast switching events used for proper MAMR operation while rejecting unwanted interference or noise components.

[0059] The MAMR sensor driver circuitry 136 includes a driver circuit 330, e.g., a driver circuit, a common-mode feedback (CMFB) loop 340, and a differential voltage regulation loop 360. In an embodiment, the driver circuit 330 functions as a power management component that delivers a controlled current to the MAMR sensor 134. The driver circuit 330 establishes a voltage differential while maintaining the rapid switching capability necessary to prevent residual magnetic fields during HDD operation. The driver circuit 330 includes polarity control switches 322A and 322B, a write / read enable signal (WR enable signal) 324, a MAMR current digital-to-analog converter (MAMR_IDAC) 326, a startup bias integrated digital-to-analog converter (IDAC) 328, a positive-negative driver (PNP driver) 332, a negative-negative driver (NPN driver) 334, a source output terminal 336, and a sink output terminal 338.

[0060] Polarity control switches 322A and 322B provide configurable paths within driver circuit 330 connecting source output terminal 336 and sink output terminal 338 to MAMR sensor 134. These switches allow for reversal of current direction through MAMR sensor 134 when operational requirements change. This feature accommodates alternative bias configurations without physical circuit modifications.

[0061] The driver circuit 330 is composed of two complementary sections, a PNP driver 332 and an NPN driver 334, positioned in the upper and lower portions, respectively, as depicted in the schematic diagram of Figure 3. These drivers help establish a voltage differential across the MAMR sensor 134 while maintaining the rapid switching speeds necessary for proper operation.

[0062] The PNP driver 332 occupies the top section of the schematic diagram in FIG. 3 and is connected to a power supply (not shown). The PNP driver 332 has a source output terminal 336 that delivers current to the MAMR_P node 312. As depicted, the configuration of the PNP driver 332 includes transistor elements arranged in a topology that allows operation at a full bias current, which is the maximum specified current magnitude for improved operating conditions of the MAMR sensor 134. The full bias current provides maximum drive capability for the MAMR sensor 134 with minimal response delay. As shown in FIG. 3, the PNP driver 332 includes current-sourcing components that establish a positive voltage reference at the MAMR_P node 312.

[0063] The PNP driver 332 also incorporates a startup bias IDAC 328 attached to the source output terminal 336. The startup bias IDAC 328 functions as an initialization component that establishes the startup conditions for the MAMR sensor 134 during the power-up sequence. The startup bias IDAC 328 enables the PNP driver 332 to quickly and reliably reach its improved operating point before the feedback loop is fully engaged. The startup bias IDAC 328 delivers a precisely calibrated current setting through a digital control input. It converts the digital value to an analog current reference that establishes the initial operating conditions for the complete bias current path. By preconditioning the source output terminal 336 with the appropriate current level, the startup bias IDAC 328 minimizes settling time during the transition from an inactive to an active state. This contributes to the overall circuit performance.

[0064] 3, provides a direct path to the negative power supply. NPN driver 334 has a sinking output terminal 338 that draws current from MAMR_N node 314. As depicted, NPN driver 334 has a transistor element configured to provide controlled current sinking capability.

[0065] In contrast to PNP driver 332, NPN driver 334 utilizes only a partial amount (e.g., a portion) of the total bias current through a technique known as fractional biasing. Specifically, NPN driver 334 operates on a complementary portion, mathematically expressed as a fraction of a full bias current, where "fraction" represents an intentionally selected percentage of the total current that is diverted from the main current path. As discussed below, this diverted current segment or portion corresponds to a "fractional" value and flows into CMFB loop 340, which helps provide high-bandwidth sensing of common-mode voltage without loading the main signal path.

[0066] Through this strategic current-splitting approach, driver circuit 330 achieves superior performance characteristics compared to conventional architectures that maintain the same current magnitude in both the source and sink paths. The reduced current load on NPN driver 334 creates a smaller capacitive load at the node. This helps provide faster transition times (e.g., 20 ns or less) while providing sufficient current for common-mode regulation at approximately zero volts. Together, PNP driver 332 and NPN driver 334 create a push-pull configuration that generates a differential voltage across MAMR sensor 134 while maintaining accurate common-mode regulation. The asymmetric biasing approach, with full current flowing through PNP driver 332 and partial current flowing through NPN driver 334, establishes electrical conditions that facilitate achieving fast transition times while ensuring stability over a variety of operating conditions.

[0067] FIG. 3 illustrates two digital control components as inputs to the driver circuit 330. The digital control components include a write / read enable signal (WR_EN) 324 and a MAMR current digital-to-analog converter (MAMR_IDAC) 326. The digital control components establish a connection between the drive control module 126 and the analog MAMR sensor driver circuitry 136, which powers the MAMR sensor 134. In an embodiment, the WR_EN signal 324 serves as the primary control input that synchronizes the MAMR sensor 134 with servo operation. The WR_EN signal 324 accurately indicates when the write head should be activated or deactivated. Thus, the WR_EN signal 324 triggers the driver circuit 330 to quickly adjust the current through the MAMR sensor 134 within a fast transition time window. In some implementations, the fast transition time window is less than 50 ns. In other implementations, it may be 20 ns or less. In yet other implementations, the fast transition time window may be 10 ns or less.

[0068] The MAMR_IDAC 326 provides a configurable or programmable current level to the driver circuit 330. In this manner, digital control over the magnitude of the current flowing through the MAMR sensor 134 is enabled. The MAMR_IDAC 326 facilitates calibration and adjustment of the microwave field strength generated by the MAMR sensor 134. The CMFB loop 340, occupying the lower left section of FIG. 3, establishes voltage regulation across the MAMR sensor 134. The CMFB loop 340 maintains the common-mode voltage (CMV) near zero volts. This creates balanced operating conditions for proper MAMR function. With direct connections to both the MAMR_P node 312 and the MAMR_N node 314, the CMFB loop 340 implements partial current sampling rather than monitoring the entire signal path. Through this approach, it prevents operational drift while enabling rapid transitions between write and servo operations. The CMFB loop 340 includes a voltage common-mode (VCM) gain stage 342 , a current sampling circuit 344 , a fractional bias circuit 346 , a dominant frequency pole 348 , and a feedback path 350 .

[0069] In an aspect, VCM gain stage 342 functions as the main amplifying element in CMFB loop 340. In addition to ground 356, this gain stage connects at its input to current sampling circuit 344 and at its output to dominant frequency pole 348. VCM gain stage 342 amplifies the difference between the detected common-mode voltage and a target reference level of approximately zero volts. Through the application of controlled gain, VCM gain stage 342 converts small voltage deviations into a substantial correction signal that drives the feedback. The amount of gain directly affects loop responsiveness.

[0070] A current sampling circuit 344 establishes a connection between the MAMR sensor nodes, MAMR_P node 312 and MAMR_N node 314, and the VCM gain stage 342. The current sampling circuit 344 extracts a representative portion of the current flowing through the MAMR sensor 134 without significantly loading the main signal path. Using a current mirror and scale technique, the current sampling circuit 344 provides an accurate representation of common-mode conditions while consuming minimal power. The partial sampling approach minimizes the effect of capacitive loading on the main signal path. This maintains signal integrity during high-speed transitions.

[0071] Fractional bias circuit 346 is integrated with NPN driver 334 and current sampling circuit 344 to implement a calculated current division. Fractional bias circuit 346 shunts a mathematically defined portion of the bias current away from NPN driver 334 and toward CMFB loop 340, thereby creating a reduced capacitive load at a critical node. Through a reduction in the current-dependent time constant, fractional bias circuit 346 significantly increases the available bandwidth compared to conventional approaches. The fractional value results from an optimization between the competing requirements of stability, power consumption, and transition speed.

[0072] A dominant frequency pole 348 exists at the junction connecting the VCM gain stage 342, fractional bias circuit 346, and NPN driver 334. The dominant frequency pole 348 establishes an intentional low-frequency cutoff point in the feedback path. This forces a controlled frequency response with, for example, approximately a 20 dB / decade rolloff. Based on its location, the dominant frequency pole 348 facilitates secondary poles occurring significantly beyond the unity gain bandwidth. This maintains sufficient phase margin across operating conditions. This frequency compensation approach eliminates the need for complex multi-pole networks while providing robust stability during rapid transitions.

[0073] Feedback path 350 establishes an interface connection between CMFB loop 340 and the remainder of MAMR sensor driver circuitry 136 (which are high-speed switching driver circuit 330 and differential voltage regulation loop 360). Feedback path 350 carries a correction signal that modulates the output voltage level in response to sensed common-mode conditions. With low-impedance signal routing with minimal parasitic effects, feedback path 350 maintains signal integrity while providing feedback. The continuous compensation provided by this relationship allows the common-mode voltage to be maintained near zero volts, regardless of changing operating conditions or component characteristics. This allows for a stable reference structure required for accurate differential voltage control.

[0074] In one or more implementations, the CMFB loop 340 also includes a polarity switch 354 that interfaces between the VCM gain stage 342 and the feedback path 350 within the CMFB loop 340. The polarity switch 354 implements complementary metal-oxide-semiconductor transmission gates that connect to both the positive and negative signal paths. Through an activation control signal, the polarity switch 354 reverses the direction of the correction signal when needed. This can accommodate alternative bias configurations or compensate for manufacturing variations in the MAMR sensor 134. During standard operation, the switch maintains the default signal routing, providing configuration flexibility without requiring physical circuit modifications.

[0075] 3, differential voltage regulation loop 360 regulates the voltage across MAMR sensor 134 by maintaining the difference in voltage between MAMR_P node 312 and MAMR_N node 314 at a set reference value. This loop includes input switch 362, operational amplifier (opamp) A 364A, opamp B 364B, reference network resistor 366, reference voltage ref_p 368, reference voltage ref_n 370, ground connection 372, summing junction 374, control block 378, output driver 380, current source 382, ​​and output node 384. These components work in conjunction to maintain differential voltage regulation of MAMR sensor 134.

[0076] At the front end of the differential voltage regulation loop 360, the differential voltage monitoring circuit incorporates an input switch 362 and signal conditioning components (not shown). The input switch 362 functions as a polarity control element connecting to both the MAMR_P node 312 and the MAMR_N node 314, which creates the initial sampling point for voltage acquisition. The input switch 362 enables or disables the connection of the feedback signal to the driver circuit 330. This allows for a reverse bias direction through a mechanism that swaps the polarity of the control signal. This configuration operates without requiring physical circuit modifications and serves as the signal entry point into the differential voltage regulation loop 360. Additionally, these bidirectional switches allow signal flow while providing isolation capability when needed.

[0077] Between the input switch 362 and operational amplifiers 364A and 364B, signal conditioning components shape the captured voltage signal through an impedance matching network and buffer stages. This shaping helps provide minimal loading effects to the MAMR sensor 134 during measurement while preventing signal degradation. The conditioned signal then proceeds to the non-inverting inputs of operational amplifier A 364A and operational amplifier B 364B, where comparison with a reference value occurs. Through this hierarchical signal path, the differential voltage monitoring circuit establishes a continuous acquisition channel with high fidelity and minimal latency. This helps provide rapid response to deviations from the target differential voltage during fast transitions.

[0078] As shown in FIG. 3, operational amplifier A 364A and operational amplifier B 364B form a differential gain stage that processes the signal passing through input switch 362. Op-amp A 364A, positioned at the top of the differential voltage regulation loop 360 circuit, compares the voltage at MAMR_P node 312 to a reference voltage ref_p 368. Simultaneously, operational amplifier B 364B, positioned at the bottom of the differential voltage regulation loop 360 circuit, compares the voltage at MAMR_N node 314 to a reference voltage ref_n 370. These comparisons generate individual error signals that quantify the deviation of each node from a desired reference level. Both error signals proceed to summing junction 374 for further processing. The reference value is the target voltage difference between the MAMR_P node 312 and the MAMR_N node 314 of the MAMR sensor 134. These nodes serve as the field input and output terminals, respectively. The differential voltage regulation loop 360 utilizes this reference value to establish operating conditions for microwave field generation by the MAMR sensor 134. This voltage difference allows the MAMR sensor 134 to quickly activate and deactivate.

[0079] Reference voltage generation occurs through components including reference voltage ref_p 368, reference voltage ref_n 370, reference network resistor 366, ground connection 372, and current source 382. The voltage digital-to-analog converter (VDAC) of current source 382 converts the digital control signal to an analog voltage level. Thus, current source 382 serves as the final source of the reference voltage that drives the overall reference voltage generation system. These reference voltage generation components establish a baseline voltage standard for comparison with the monitored voltage of MAMR sensor 134. Reference network resistor 366 forms a voltage divider network within differential voltage regulation loop 360. These resistive elements connect to reference voltage ref_p 368, reference voltage ref_n 370, and ground connection 372. This connection creates a stable reference point for the comparison operation. The resistive network maintains the appropriate signal level throughout the operating range of the MAMR sensor drive circuitry 136.

[0080] Reference voltage ref_p 368 serves as an upper threshold for comparison with the voltage at MAMR_P node 312. Reference voltage ref_p 368 defines an upper target bias voltage limit for operation of the MAMR sensor 134. It connects to the inverting input of operational amplifier A 364A. Reference voltage ref_n 370 serves as a lower threshold for comparison with the voltage at MAMR_N node 314. It establishes a lower target bias voltage limit for function of the MAMR sensor 134. Reference voltage ref_n 370 connects to the inverting input of operational amplifier B 364B. A ground connection 372 provides a common reference point for reference network resistor 366. This may provide a constant voltage measurement across the differential voltage regulation loop 360.

[0081] Some implementations incorporate a precision bandgap reference circuit that produces temperature-stable baseline voltages. Scaling amplifiers adjust these voltages to application-specific levels for biasing the MAMR sensors 134. Digital control lines connect to the current source 382. These control lines allow the reference levels to be programmably adjusted based on system requirements. This capability facilitates the calibration process during manufacturing. The HDD system 118 undergoes testing to determine refined parameters for each MAMR sensor 134.

[0082] Opamp A 364A and opamp B 364B within the differential voltage regulation loop 360 continuously compare the voltage across the MAMR sensor 134 to a reference value. Opamp A 364A compares the voltage at the MAMR_P node 312 to a reference voltage ref_p 368. Opamp B 364B compares the voltage at the MAMR_N node 314 to a reference voltage ref_n 370. These comparisons generate an error signal that drives a correction mechanism. The reference values ​​function independently of the common-mode voltage regulation performed by the CMFB loop 340. This isolation helps provide simultaneous management of differential-mode and common-mode aspects of the MAMR sensor 134's operation. Through the coordinated operation of a precision reference circuit, resistor network, and ground referencing, the reference voltage generator produces stable comparison thresholds. These thresholds allow the differential gain stage to detect deviations from the target differential voltage. This maintains proper bias conditions throughout all drive operations.

[0083] Summing junction 374 receives and combines the error signals generated by op amp A 364A and op amp B 364B. Summing junction 374 produces a single composite error signal representing the total deviation from the desired differential voltage across MAMR sensor 134. This combined error signal then passes to control block 378 for further processing. Control block 378 processes the composite error signal from summing junction 374. This processing may include gain adjustment, level shifting, and implementation of selected timing logic for the pre-charge operation. Control block 378 converts the error information into appropriate gate drive signals to control output driver 380, which helps provide fast voltage transitions. Control block 378 may include timing logic for the pre-charge operation, indicating that the pre-charge control circuitry exists as a subsystem within this block. The pre-charge function may be part of the main control path rather than a separate circuit block.

[0084] The pre-charge control circuit establishes initial conditions during startup or transition. The pre-charge control circuit responds to delays associated with charging parasitic capacitance from a zero-voltage state, which can extend settling time beyond the desired transition time. To reduce this delay, the pre-charge control circuit applies an initial voltage or current pulse that quickly charges the node to near its operating level before transitioning to regulation mode. This approach reduces settling time by eliminating a portion of the charge accumulation period. Implementations may include detection circuitry for the transition event, pulse generation logic for the pre-charge signal, and a transfer mechanism to transition from pre-charge mode to normal regulation mode.

[0085] In the output stage, output driver 380 functions as a controlled pull-down element in differential voltage regulation loop 360. Output driver 380 may be implemented as an NMOS transistor. The gate of this transistor connects to control block 378, while the source connects to ground and the drain connects to output node 384. Output driver 380 adjusts the current flow based on the error signal. The adjustment increases the current sink when the sensed voltage exceeds the target and decreases the current sink when the voltage falls below the target value.

[0086] Current source 382 provides a programmable bias current established through digital-to-analog conversion. This current source works in conjunction with output driver 380 to establish baseline operating conditions for MAMR sensor 134 and helps achieve fast transition times for proper operation. Current source 382 implements a voltage digital-to-analog converter (VDAC) function; that is, it converts digital control signals to analog current levels.

[0087] A digital control line connects to current source 382 to allow external circuitry to adjust the magnitude of the bias current based on operational requirements. This programmable capability is useful during the manufacturing calibration process when HDD system 118 undergoes testing to determine improved parameters for each MAMR sensor 134. Digital-to-analog conversion is extended to the reference voltage generator through a digital interface and scaling amplifier, which adjusts the voltage levels for reference voltage ref_p 368 and reference voltage ref_n 370. Through this digital-to-analog conversion implementation, differential voltage regulation loop 360 achieves calibration capability and adaptive operation throughout the operational life of HDD system 118. Output node 384 serves as the connection point between differential voltage regulation loop 360 and driver circuit 330. This node undergoes active voltage control through the combined action of output driver 380 and current source 382. Output node 384 completes the feedback loop by connecting back to driver circuit 330, which includes PNP driver 332 and NPN driver 334.

[0088] The frequency limiting function within the differential voltage regulation loop 360 helps to establish controlled attenuation of high frequency signals, prevent oscillations through phase margin management, and provide stable operation during rapid transitions. This function enables the differential voltage regulation loop 360 to maintain both the stability margin and fast response characteristics necessary for proper operation of the MAMR sensor 134. The frequency limiting element performs these functions through creating a dominant pole and a selected roll-off characteristic in the frequency response curve of the feedback loop.

[0089] These frequency-limiting elements may be implemented within Op Amp A 364A and Op Amp B 364B, or within Control Block 378, or a combination thereof. The dominant pole capacitor, which may exist as part of the internal architecture of the op amp and / or as a separate component within Control Block 378, establishes a selected resistive-capacitive time constant. The dominant pole capacitor works in conjunction with the resistive network components to produce a defined cutoff frequency, which in turn attenuates high frequency components of the error signal.

[0090] The resistive-capacitive network establishes a roll-off slope of approximately -20 dB per decade. The route to control block 378 via summing junction 374 allows the combined error signal to pass through these frequency shaping elements. Additionally, the interface between control block 378 and output driver 380 provides an alternative possible point for frequency limiting. Output driver gate capacitance 380 and the output resistance from control block 378 form another resistive-capacitive filtering stage. Through the implementation of one or more of these components, differential voltage regulation loop 360 achieves a balance of response speed and stability for improved performance.

[0091] Through the coordinated operation of all these components, differential voltage regulation loop 360 achieves fast transition times of approximately less than 50 ns, 20 ns or less, and / or 10 ns or less. Differential voltage regulation loop 360 operates in a continuous sense-compare-drive cycle. That is, differential voltage regulation loop 360 monitors the voltage across MAMR sensor 134, compares the monitored voltage to a reference value, and then makes appropriate corrections to maintain the target differential. This fast response prevents residual magnetic fields during writer demagnetization transitions, which protects against data corruption in high-density storage applications. Differential voltage regulation loop 360 operates in conjunction with CMFB loop 340, where the differential voltage regulation loop controls the differential voltage while the CMFB loop maintains the common-mode voltage near zero volts.

[0092] 2, various components of the MAMR sensor driver circuitry 136 were shown and briefly described. In the context of the MAMR sensor driver circuitry 136 shown in FIG. 3 and described above, the components with their respective descriptions are provided below. The power conditioning component 232 supplies current to the MAMR sensor 134. The power conditioning component 232 includes a MAMR_IDAC 326, a startup bias IDAC 328, a PNP driver 332, an NPN driver 334, a source output terminal 336, a sink output terminal 338, and a current source 382.

[0093] The power conditioning component 232 delivers a controlled current to the MAMR sensor 134. The MAMR_IDAC 326 programs the current magnitude. The startup bias IDAC 328 preconditions the source terminal during initialization. The PNP driver 332 operates at full bias current, while the NPN driver 334 operates at a complementary (fractional) bias level. This asymmetric current distribution creates a smaller capacitive load at critical nodes. The current source 382 provides programmable bias through digital-to-analog conversion. These components work together to establish a precision voltage difference with the ability to quickly switch between active and inactive states.

[0094] The signal generation circuit 234 generates the electrical pattern for sensor operation. The signal generation circuit 234 includes a differential voltage regulation loop 360, a reference voltage ref_p 368, a reference voltage ref_n 370, a reference resistor network 366, and a VDAC (in current source 382). The signal generation circuit 234 generates the electrical pattern for MAMR sensor operation. The differential voltage regulation loop 360 maintains the voltage across the MAMR sensor at a target value. The reference voltages ref_p 368 and ref_n 370 define upper and lower thresholds for the bias voltage. The reference resistor network 366 forms a voltage divider that sets the appropriate signal level. The VDAC converts the digital signal to an analog voltage with high precision. These components collectively establish a baseline voltage standard that defines the operating conditions for generating a microwave field by the MAMR sensor.

[0095] The control logic section 236 manages the operational timing. It includes a WR enable signal 324, a control block 378, a pre-charge circuit (within the control block), polarity control switches 322A / B, and a polarity switch 354. The control logic section 236 coordinates the operational timing. The WR enable signal 324 synchronizes the MAMR sensor with servo operation by indicating when the write head should be activated or deactivated. The control block 378 processes the error signals and converts them into gate drive signals for the output drivers. The pre-charge circuit initializes nodes to fixed voltage levels during startup and transitions. The polarity switches 322A / B and 354 allow the reversal of current direction through the MAMR sensor without physical circuit changes. These control elements work together to achieve fast switching times and match the MAMR field with the servo timing requirements of the HDD.

[0096] The interface circuit 238 forms the communication path. The input switch 362 includes the input switch 362, the driver circuit 330, a summing junction 374, and an output node 384. The interface circuit 238 establishes the communication path between the subsystems. The input switch 362 generates sampling points at the MAMR_P and MAMR_N nodes for voltage acquisition. The driver circuit 330 connects the source and sink terminals to the MAMR sensor. The summing junction 374 combines error signals from multiple operational amplifiers. The output node 384 connects the voltage regulation loop to the driver circuit. These interface components translate high-level control signals from the drive control module into specific electrical commands to the MAMR sensor 134. They form the connection between the different functional blocks while maintaining signal integrity throughout the path.

[0097] The feedback mechanism 240 monitors performance parameters. The feedback mechanism 240 includes a CMFB loop 340, a VCM gain stage 342, a current sampling circuit 344, a fractional bias circuit 346, an operational amplifier A 364A, an operational amplifier B 364B, a feedback path 350, a dominant frequency pole 348, and a frequency-limiting element. The feedback mechanism 240 monitors and adjusts system parameters. The CMFB loop 340 regulates the common-mode voltage to approximately zero volts. The VCM gain stage 342 amplifies the difference between the sensed voltage and a target level. The current sampling circuit 344 extracts a portion of the current from the MAMR sensor without loading the main signal path. The operational amplifiers 364A / B compare the sensed voltage to a reference value. The dominant pole 348 and frequency-limiting element establish a controlled attenuation of the high-frequency signal. These feedback components form a multiple-loop closed-loop system that continuously senses conditions, compares them to a reference, and makes corrections. This continuous adjustment ensures stable voltage regulation during the transition between write operations and servo positioning.

[0098] The following discussion describes differential vMode driver techniques for MAMR applications in HDDs that may reduce or prevent the possibility of on-disk data corruption due to slow write-activation / deactivation transitions of the write head's MAMR sensor. These techniques may be implemented using any of the environments and entities described herein, such as the MAMR-based write head 220, MAMR sensor drive circuitry 136, MAMR sensor-related circuitry 310, and drive control module 126. These techniques include the method illustrated in FIG. 4, which is shown as a set of operations performed by one or more entities.

[0099] These methods are not necessarily limited to the order of operations shown in the associated figures. Rather, any of the operations may be repeated, skipped, replaced, or reordered to implement various aspects described herein. Furthermore, these methods may be used in combination with each other, in whole or in part, regardless of whether performed by the same entity, separate entities, or any combination thereof. For example, aspects of the described methods may be combined to implement a differential vMode driver for MAMR applications in HDDs. In the following description, reference is made to the operating environment 100 of FIG. 1 and entities of FIGS. 2 and 3. Such references should not be construed to limit the described aspects to the operating environment 100, entities, configurations, or implementations, but rather as illustrating one of various examples. Alternatively or additionally, the operations of the methods may also be implemented by or in conjunction with the entities described with reference to the system-on-chip of FIG. 5 and / or the storage media controller of FIG. 6.

[0100] FIG. 4 depicts an exemplary method 400 for implementing a differential vMode driver for MAMR applications in an HDD, including operations performed by or in conjunction with the MAMR-based write head 220, the MAMR sensor drive circuitry 136, the MAMR sensor-related circuitry 310, and the drive control module 126.

[0101] At 402, the differential voltage regulation loop 360 performs reference voltage generation and provides a reference value for the voltage difference applied across the MAMR sensor 134. The differential voltage regulation loop 360 generates a reference voltage through reference voltage ref_p 368 and reference voltage ref_n 370, which establish upper and lower bias voltage thresholds for the MAMR sensor 134. The reference network resistors 366 form a voltage divider network that maintains the signal level. The current source 382 includes a VDAC that converts the digital control signal to an analog voltage level. This reference value can operate independently of the CMFB loop 340.

[0102] At 404, the driver circuit 330 supplies a bias current to the MAMR sensor 134 to contribute to its operation and facilitate fast switching. Typically, the bias current is based on the characteristics of the MAMR sensor 134. The driver circuit 330 delivers current through two sections: a PNP driver 332 and an NPN driver 334. The PNP driver 332 operates with the full bias current through a source output terminal 336. The NPN driver 334 operates with a fraction of the full bias current through a sink output terminal 338. This creates a smaller capacitive load at the node. The start-up bias IDAC 328 pre-conditions the source output terminal 336 with an appropriate current level. The MAMR_IDAC 326 controls the magnitude of the current flowing through the MAMR sensor 134.

[0103] At 406, the CMFB loop 340 maintains common-mode voltage regulation of the MAMR sensor 134, which helps provide stability around a reference point of approximately zero volts. The CMFB loop 340 regulates the common-mode voltage to approximately zero volts. A VCM gain stage 342 amplifies the difference between the detected common-mode voltage and zero volts. A current sampling circuit 344 extracts a portion of the current flowing through the MAMR sensor 134. A fractional bias circuit 346 shunts a portion of the bias current from the NPN driver 334 to the CMFB loop 340. A dominant frequency pole 348 establishes a low-frequency cutoff point in the feedback path. A feedback path 350 sends a correction signal to adjust the output voltage level based on the detected common-mode condition.

[0104] At 408, the differential voltage regulation loop 360 precisely maintains the voltage difference across the MAMR sensor 134 at a provided reference value. The differential voltage regulation loop 360 monitors the voltage between the MAMR_P node 312 and the MAMR_N node 314. Op-amp A 364A compares the voltage at the MAMR_P node 312 to a reference voltage ref_p 368. Op-amp B 364B compares the voltage at the MAMR_N node 314 to a reference voltage ref_n 370. These comparisons generate an error signal. A summing junction 374 combines these into a single composite error signal. A control block 378 converts this signal into a gate drive signal for an output driver 380. The output driver 380 adjusts the current flow based on the error signal. A frequency-limiting element at the output node 384 filters high-frequency components of the feedback signal.

[0105] At 410, the driver circuit 330 switches the voltage difference across the MAMR sensor 134 with very fast rise and fall times (e.g., transition time frames) of 50 ns, 20 ns, or less, and / or 10 ns or less. This helps provide timing control during write operations. The driver circuit 330 achieves the fast transitions through asymmetric biasing. The PNP driver 332 uses full current, while the NPN driver 334 uses partial current. A pre-charge circuit initializes the nodes in the differential voltage regulation loop 360 to fixed voltage levels. Single-ended capacitors in the capacitive element 318 connect to each terminal of the MAMR sensor 134 for frequency compensation. The damping element 316 damps high-frequency oscillations. While conventional systems require transition times of several hundred ns, this configuration can achieve transition times of approximately 20 ns or less.

[0106] At 412, the driver circuit 330 synchronizes the switching of the MAMR sensor 134 with a received write / read (WR) enable signal (e.g., the WR EN signal 324) from the drive control module 126. The WR EN signal 324 serves as a control input that synchronizes the MAMR sensor 134 with servo operation. It triggers the driver circuit 330 to adjust the current through the MAMR sensor 134 within a transition time window. This helps ensure that the MAMR sensor 134 is deactivated before the read / write head 132 moves from writing data to reading servo positioning information. The MAMR_IDAC 326 works in conjunction with the WR EN signal 324 to provide the appropriate current level during the active phase. System-on-Chip

[0107] 5 illustrates an exemplary system-on-chip (SoC) 500 that may implement various aspects of a differential vMode driver for MAMR of storage media. SoC 500 may be implemented in any suitable device, such as a smartphone, netbook, tablet computer, access point, network-attached storage, camera, smart appliance, printer, set-top box, server, solid-state drive (SSD), magnetic tape drive, hard disk drive (HDD), storage drive, array, memory module, storage media controller, storage media interface, head-disk assembly, magnetic media pre-amplifier, automotive computing system, or any other suitable type of device (e.g., others described herein). Although described with reference to an SoC, the entities in FIG. 5 may also be implemented as other types of integrated circuits or embedded systems, such as an application-specific integrated-circuit (ASIC), a memory controller, a storage controller, a communications controller, an application-specific standard product (ASSP), a digital signal processor (DSP), a programmable SoC (PSoC), a system-in-package (SiP), or a field-programmable gate array (FPGA).

[0108] The SoC 500 may be integrated with electronic circuitry, microprocessors, memory, input / output (I / O) control logic, communications interfaces, firmware, and / or software useful for providing the functionality of a computing device or magnetic storage system, such as any of the devices or components described herein (e.g., a hard disk drive). The SoC 500 may also include an integrated data bus or interconnect fabric (not shown) that couples various components of the SoC for data communication or routing between the components. The integrated data bus, interconnect fabric, or other components of the SoC 500 may be exposed or accessible through an external port, a parallel data interface, a serial data interface, a peripheral component interface, or any other suitable data interface. For example, components of the SoC 500 may access or control external storage media or magnetic writing circuitry through an external interface or an off-chip data interface.

[0109] In this example, SoC 500 is shown with various components, including input / output (I / O) control logic 502 and a hardware-based processor 504 (processor 504), such as a microprocessor, processor core, application processor, or DSP. SoC 500 also includes memory 506, which may include any type and / or combination of RAM, SRAM, DRAM, non-volatile memory, ROM, one-time programmable (OTP) memory, multiple-time programmable (MTP) memory, flash memory, and / or other suitable electronic data storage. In some aspects, code stored on processor 504 and memory 506 is implemented as part of a storage media controller or storage media interface to provide various functions related to a differential vMode driver for MAMR of a storage media. These functions may include read / write channel functions, resistance measurement, MAMR calibration, or reference voltage adjustment. In the context of the present disclosure, memory 506 stores data, code, instructions, or other information via non-transitory signals. It does not include carrier waves or transient signals. Alternatively or additionally, SoC 500 may include a data interface for accessing additional or expandable off-chip storage media, including magnetic memory or solid-state memory (e.g., flash memory or NAND memory).

[0110] The SoC 500 may also include firmware 508, applications, programs, software, and / or an operating system, which may be embodied as processor-executable instructions maintained on the memory 506 for execution by the processor 504 to implement the functions of the SoC 500. The SoC 500 may also include other communication interfaces, such as a transceiver interface, for controlling or communicating with local on-chip (not shown) or off-chip communication transceiver components. Alternatively or additionally, the transceiver interface may also include or implement a signal interface for communicating radio frequency (RF), intermediate frequency (IF), or baseband frequency signals off-chip to facilitate wired or wireless communication through a transceiver, physical layer transceiver (PHY), or media access controller (MAC) coupled to the SoC 500. For example, the SoC 500 may include a transceiver interface configured to provide differential vMode driver functionality to a network-attached storage (NAS) device, for example, that contributes storage over a wired or wireless network.

[0111] In this example, SoC 500 also includes read / write channel 144, storage media controller 140, servo control unit 142, and MAMR sensor drive circuitry 136, which may be implemented separately as shown or combined with the storage components or data interface. Alternatively or additionally, SoC 500 may include an interface to a preamplifier and / or spindle / motor assembly of a magnetic media disk drive. Any of these entities may be embodied as separate or combined components, as described with reference to various aspects described herein. Examples of these components and / or entities, or corresponding functionality, are described with reference to the respective components or entities of environment 100 of FIG. 1 or the respective configurations illustrated in FIGS. 2 and / or 3.

[0112] The MAMR sensor drive circuitry 136 may be implemented independently or in combination with any suitable component or circuitry to implement aspects described herein. For example, the MAMR sensor drive circuitry may be implemented as part of a DSP, processor / storage bridge, I / O bridge, graphics processing unit, memory controller, storage controller, or arithmetic logic unit (ALU), etc. The MAMR sensor drive circuitry 136 may also be provided integrated with other entities of the SoC 500, such as the processor 504, memory 506, storage medium interface, or firmware 508 of the SoC 500. Alternatively or additionally, the MAMR sensor drive circuitry 136 and / or other components of the SoC 500 may be implemented as hardware, firmware, fixed logic circuitry, or any combination thereof.

[0113] As another example, consider FIG. 6, which illustrates an exemplary storage media controller 600 in accordance with one or more aspects of a differential vMode driver for MAMR applications of HDDs. Generally, the storage media controller 600 enables the computing device 102 to access the contents of a magnetic storage medium, e.g., an operating system, an application, or data or other services for the application. The storage media controller may also write and read data for the computing device 102 to and from the magnetic storage medium with which the controller is associated. In various aspects, the storage media controller 600 or any combination of its components may be implemented as a storage drive controller (e.g., an HDD controller or HDD chipset), a storage media controller, a NAS controller, a storage media interface, a storage media endpoint, a storage media target, or a storage aggregate controller for magnetic storage media, solid-state storage media, or the like (e.g., a hybrid SSD / HDD storage system).

[0114] In some cases, storage media controller 600 is implemented similarly to or together with components of SoC 500, as described with reference to FIG. 5 . In other words, an instance of SoC 500 may be configured as a storage media controller, e.g., storage media controller 600, for managing magnetic storage media. In this example, storage media controller 600 includes input / output (I / O) control logic 602 and a processor 604, e.g., a microprocessor, microcontroller, processor core, application processor, or DSP. The storage media controller also includes a host interface 606 (e.g., a SATA, PCIe, NVMe, or fabric interface) and a storage media interface 608 (e.g., a magnetic media interface or a head-disk assembly (HDA) interface), which enable access to a host system (or fabric) and the storage media, respectively. In this example, the storage media interface includes separate instances of spindle interface 610 and preamp interface 612, which facilitate communication with, e.g., a head-disk assembly of a media drive.

[0115] In some aspects, storage media controller 600 implements aspects of a differential vMode driver for MAMR applications in HDDs when managing or enabling access to a storage medium coupled to storage media interface 608. Storage media controller 600 may provide a storage interface for a host system via host interface 606. Storage access commands are received from the host system through this interface. These commands include commands to write data to or read data from a magnetic storage medium. During operations associated with these commands, the vMode driver implementation achieves transition times of approximately 50, 30, 20, 10, and / or 5 nanoseconds for enhanced servo operation. As shown in FIG. 6 , storage media controller 600 includes servo control unit 142, read / write channel 144, and MAMR sensor drive circuitry 136 for implementing aspects of a differential vMode driver.

[0116] Servo control unit 142 is operably coupled to spindle interface 610 and may provide spindle or voice coil control for the magnetic media drive. In some embodiments, the firmware or logic of processor 604 and storage media controller 600 is implemented to provide multiple functions. These include MAMR sensor resistance measurement calibration, MAMR sensor current level adjustment, and various data writing or processing functions. All of these functions may be implemented in conjunction with a differential vMode driver for the MAMR of the storage media.

[0117] The MAMR sensor drive circuitry 136 of the storage media controller 600 may also be implemented separately as shown, or in combination with the processor 604, the read / write channel 144, or the storage media interface 608. Examples of these components and / or entities, or corresponding functionality, are described with reference to the respective components or entities of the environment 100 of FIG. 1 or the respective configurations illustrated in FIG. 2 and / or FIG. 3. The MAMR sensor drive circuitry 136, either in whole or in part, may be implemented as processor-executable instructions maintained by the controller's memory and executed by the processor 604 to implement various aspects and / or functionality of a differential vMode driver for MAMR applications of HDDs.

[0118] Although the subject matter described herein is described in language specific to structural features and / or methodological acts, it should be understood that the subject matter defined in the appended claims is not necessarily limited to the specific examples, features, or acts (including the order in which they are performed) described herein.

Claims

1. 1. An apparatus for facilitating high speed transitions during magnetic recording in microwave assisted magnetic recording (MAMR), the apparatus comprising: a driver circuit configured to provide a controlled bias current, the driver circuit having separate source and sink output terminals and responsive to a feedback signal; a MAMR sensor coupled between the source output terminal and the sink output terminal, the MAMR sensor receiving the controlled bias current provided by the driver circuit therethrough; a common mode feedback (CMFB) loop coupled to the source output terminal and the sink output terminal of the driver circuit, the CMFB loop configured to detect a common mode voltage (CMV) and provide a feedback signal to the driver circuit to maintain CMV regulation of the MAMR sensor; and a differential voltage regulation loop coupled to the source output terminal and the sink output terminal of the driver circuit, the differential voltage regulation loop configured to provide a feedback signal to maintain a voltage difference across the MAMR sensor at a reference value; An apparatus comprising:

2. 2. The apparatus of claim 1, wherein the source output terminal of the driver circuit comprises a positive-negative-positive (PNP) driver biased at a full controlled bias current, and the sink output terminal comprises a negative-negative-positive (NPN) driver biased at a fraction of the controlled bias current.

3. 10. The apparatus of claim 1, wherein the MAMR sensor includes one or more single-ended capacitors for frequency compensation that stabilize feedback signals from the CMFB loop and the differential voltage regulation loop.

4. 2. The apparatus of claim 1, wherein the CMFB loop is further configured to detect the CMV by sampling only a portion of a current through the MAMR sensor coupled between the source output terminal and the sink output terminal of the driver circuit.

5. The apparatus of claim 1 , wherein the CMFB loop is further configured to maintain the CMV tuning of the MAMR sensor at approximately zero volts.

6. The apparatus of claim 1 , wherein the differential voltage regulation loop is further configured to monitor the voltage difference across the MAMR sensor.

7. The apparatus of claim 1 , wherein a voltage digital-to-analog converter (VDAC) of the differential voltage regulation loop is configured to determine the reference value.

8. The apparatus of claim 1 , wherein the reference value is independent of the CMV adjustment performed by the CMFB loop.

9. 10. The apparatus of claim 1, further comprising a pre-charge circuit coupled to a node in the differential voltage regulation loop, the pre-charge circuit configured to initialize the node to a fixed voltage level.

10. 10. The apparatus of claim 1, further comprising a frequency-limiting element disposed at a node in the differential voltage regulation loop, the frequency-limiting element configured to filter high frequency components of feedback signals from the CMFB loop and the differential voltage regulation loop.

11. 11. The apparatus of claim 1, wherein the driver circuit is further configured to rapidly transition the voltage difference across the MAMR sensor based on a write / read (WR) enable signal.

12. 1. A hard disk drive system that facilitates high speed transitions during microwave assisted magnetic recording (MAMR) magnetic recording, the hard disk drive system comprising: a write head having a microwave-assisted magnetic recording (MAMR) sensor; and Voltage mode (vMode) driver circuitry configured to drive a differential voltage across the MAMR sensor. and the vMode driver circuitry comprises: a driver circuit configured to respond to a feedback signal, the driver circuit having separate source and sink output terminals with the MAMR sensor coupled therebetween; a common mode feedback (CMFB) loop coupled to the source output terminal and the sink output terminal of the driver circuit, the CMFB loop configured to detect a common mode voltage (CMV) and provide a feedback signal to the driver circuit to maintain CMV regulation of the MAMR sensor; and a differential voltage regulation loop coupled to the source output terminal and the sink output terminal of the driver circuit, the differential voltage regulation loop configured to provide a feedback signal to maintain a voltage difference across the MAMR sensor at a reference value; A hard disk drive system comprising:

13. 13. The hard disk drive system of claim 12, wherein the source output terminal of the driver circuit comprises a positive-negative-positive (PNP) driver biased at full bias current, and the sink output terminal comprises a negative-negative-positive (NPN) driver biased at a portion of the bias current.

14. the vMode driver circuitry further comprising a frequency-limiting element disposed at a node in the differential voltage regulation loop; the MAMR sensor includes one or more single-ended capacitors; the frequency-limiting element and the one or more single-ended capacitors are further configured to facilitate frequency compensation that stabilizes feedback signals from the CMFB loop and the differential voltage regulation loop.

13. The hard disk drive system of claim 12.

15. 13. The hard disk drive system of claim 12, wherein the CMFB loop is further configured to detect the CMV by sampling only a portion of a current through the MAMR sensor coupled between the source output terminal and the sink output terminal of the driver circuit.

16. 13. The hard disk drive system of claim 12, wherein the CMFB loop is further configured to maintain the CMV tuning of the MAMR sensor at approximately zero volts.

17. 17. The hard disk drive system of claim 12, wherein the vMode driver circuitry is further configured to rapidly transition the voltage difference across the MAMR sensor with rise and fall times of 10 nanoseconds or less.

18. 1. A method for facilitating fast transitions during magnetic recording in microwave-assisted magnetic recording (MAMR), the method comprising: providing a reference value for the voltage difference; providing, by a driver circuit, a bias current to a MAMR sensor of the magnetic media read / write channel; maintaining common mode voltage (CMV) regulation of the MAMR sensor by a common mode feedback (CMFB) loop coupled to the driver circuit; maintaining the voltage difference across the MAMR sensor at the reference value; and switching the voltage difference across the MAMR sensor with rise and fall times of 20 nanoseconds or less. A method comprising:

19. 20. The method of claim 18, wherein the switching of the voltage difference across the MAMR sensor occurs with a rise or fall time of 10 nanoseconds or less.

20. receiving a write / read (WR) enable signal; and synchronizing the switching of the voltage difference with the WR enable signal; 20. The method of claim 18 or 19, further comprising:

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