Display device and electronic apparatus

Abstract

To provide a display device which has high resolution and suppresses delay of an input signal to a pixel.SOLUTION: In the display device, a first layer, a second layer, and a third layer are formed in order from the bottom. The first layer includes a drive circuit and a plurality of first wirings, the second layer includes a plurality of first contact portions, and the third layer includes a pixel array and a plurality of second wirings. The pixel array includes a plurality of pixel circuits. Each of the plurality of second wirings is a wiring extending in parallel and in the column direction of the pixel array, and each of the plurality of pixel circuits is electrically connected to the plurality of second wirings. The drive circuit includes a plurality of output terminals arranged along a first direction. The plurality of first wirings are wirings extending perpendicularly to the first direction, and each of the plurality of output terminals is electrically connected to the plurality of first wirings. Each of the plurality of first wirings is electrically connected to the plurality of second wirings via the plurality of first contact portions.SELECTED DRAWING: Figure 3

Description

[Technical Field]

[0001] One embodiment of the present invention relates to a display device and an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. The technical field of the invention disclosed in this specification relates to an object, a driving method, or a manufacturing method. Alternatively, one embodiment of the present invention relates to a process, a machine, manufacture, or a composition of matter. Therefore, more specifically, examples of the technical field of one embodiment of the present invention disclosed in this specification include semiconductor devices, display devices, liquid crystal display devices, light-emitting devices, power storage devices, imaging devices, memory devices, signal processing devices, processors, electronic devices, systems, driving methods thereof, manufacturing methods thereof, and inspection methods thereof. [Background technology]

[0003] There is a demand for display devices applicable to XR such as VR (virtual reality) and AR (augmented reality). Such display devices are expected to provide users with, for example, a high sense of reality and a high sense of immersion. To provide users with a high sense of reality and a high sense of immersion, for example, it is necessary to improve the display quality of the display device, such as by increasing the resolution and color reproducibility.

[0004] Examples of display devices that can be applied to the display include liquid crystal display devices, and light-emitting devices equipped with light-emitting devices such as organic electroluminescence (EL) devices and light-emitting diodes (LEDs: Light Emitting Diodes). Patent Document 1 discloses a high-pixel, high-definition display device equipped with a light-emitting device that includes an organic EL device. [Prior art documents] [Patent documents]

[0005] [Patent Document 1] International Publication No. 2019 / 220278 Summary of the Invention [Problem to be solved by the invention]

[0006] As described above, devices for XR require display devices with high display quality. Furthermore, since display devices for XR need to be provided in, for example, eyeglass-type or goggle-type housings, it is preferable to reduce the size of the display device. Specifically, for example, in the case of devices for VR, the size (diagonal length) of the display device is preferably 1 inch or more and 2 inches or less. Furthermore, for example, in devices for AR, the size of the display device is preferably 3 inches or less, more preferably 2 inches or less, and even more preferably 1.5 inches or less.

[0007] On the other hand, display devices for XR devices require higher resolution to enhance the sense of realism and immersion. In this case, for example, the number of pixels within a given size can be increased by designing the display device to have a smaller pitch between pixels or between wires, or by reducing the pixel size. However, as the number of pixels in a display device increases, the amount of data per frame increases, and therefore there is a demand for faster driver circuits (such as source driver circuits and gate driver circuits) that drive the display device.

[0008] Furthermore, display devices for XR devices require a higher drive frequency to enhance the sense of realism and immersion. However, the higher the drive frequency, the shorter the input time per frame, which may reduce the amount of data that can be input to the display device within one frame.

[0009] An object of one embodiment of the present invention is to provide a display device with a reduced circuit area.An object of one embodiment of the present invention is to provide a display device with reduced power consumption.An object of one embodiment of the present invention is to provide a display device with high display quality.An object of one embodiment of the present invention is to provide a high-resolution display device with a high frame frequency.An object of one embodiment of the present invention is to provide a novel display device.An object of one embodiment of the present invention is to provide an electronic device including any of the above-described display devices.

[0010] Note that the problems of one embodiment of the present invention are not limited to the problems listed above. The problems listed above do not preclude the existence of other problems. Note that the other problems are problems not mentioned in this section, which will be described below. Problems not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be appropriately extracted from these descriptions. Note that one embodiment of the present invention solves at least one of the problems listed above and other problems. Note that one embodiment of the present invention does not necessarily solve all of the problems listed above and other problems. [Means for solving the problem]

[0011] (1) One aspect of the present invention is a display device having a first layer, a second layer located above the first layer, and a third layer located above the second layer. The first layer has a drive circuit and a plurality of first wirings, the second layer has a plurality of first contact portions, and the third layer has a pixel array and a plurality of second wirings. The pixel array has a plurality of pixel circuits arranged in a matrix, and the drive circuit has a function of controlling the plurality of pixel circuits. Each of the plurality of second wirings is parallel to each other and extends in the column direction of the pixel array, and each of the plurality of pixel circuits is electrically connected to the plurality of second wirings. The drive circuit also has a plurality of output terminals arranged along a first direction. The plurality of first wirings is extended perpendicular to the first direction, and each of the plurality of output terminals is electrically connected to the plurality of first wirings. Each of the plurality of first wirings is electrically connected to the plurality of second wirings via a plurality of first contact portions.

[0012] (2) Alternatively, in one aspect of the present invention, in the above (1), one of the plurality of first contact portions may be configured to be located inside the pixel array and inside the pixel circuit or outside the pixel circuit when viewed from above.

[0013] (3) Alternatively, in one aspect of the present invention, in the above (1) or (2), the first layer may have a semiconductor substrate made of silicon and a plurality of second contact portions. In particular, the drive circuit preferably has a plurality of transistors having silicon in their channel formation regions. Also, it is preferable that a plurality of low-resistance regions serving as a plurality of first wirings are located on the upper surface of the semiconductor substrate, a plurality of second contact portions are located between the plurality of first contact portions and the plurality of low-resistance regions, and each of the plurality of low-resistance regions has one of the source and drain of each of the plurality of transistors.

[0014] (4) Another embodiment of the present invention is a display device including a first layer and a third layer located above the first layer. The first layer includes a driver circuit region, and the third layer includes a pixel array. The pixel array includes a plurality of pixel regions, and the driver circuit region includes a plurality of local driver circuits. One of the plurality of local driver circuits corresponds to one of the plurality of pixel regions. The local driver circuit has a function of driving a plurality of pixels included in the corresponding pixel region. Note that, in a top view, the driver circuit region is located inside the pixel array, and some of the plurality of pixel regions do not overlap with the driver circuit region.

[0015] (5) Alternatively, in one embodiment of the present invention, in the above (4), each of the plurality of pixel regions may have a plurality of wirings. Furthermore, in the plurality of pixel regions, the plurality of pixels are preferably arranged in a matrix, the plurality of wirings are preferably arranged for each row of the matrix, and each of the plurality of wirings is preferably electrically connected to a pixel located in the same row. Furthermore, each of the plurality of wirings preferably has a contact portion, and the contact portion is preferably located inside the pixel or between adjacent pixels.

[0016] (6) Alternatively, in one embodiment of the present invention, in the above-described (4) or (5), the driver circuit region may include a controller and a voltage generation circuit. The controller preferably has a function of acquiring an image signal and an address signal including a destination of the image signal, both of which are input from outside, and a function of selecting a plurality of local driver circuits in response to the address signal and transmitting the image signal to the selected local driver circuit. The voltage generation circuit preferably has a function of generating voltages to be supplied to the plurality of local driver circuits or the pixels.

[0017] (7) Alternatively, in one aspect of the present invention, in any one of the above (4) to (6), each of the pixels included in the plurality of pixel regions may have a light-emitting device using an organic EL and a first transistor, and the plurality of local driver circuits may have a second transistor. In particular, it is preferable that the first transistor has a metal oxide in a channel formation region, and it is preferable that the second transistor has silicon in a channel formation region.

[0018] (8) Another embodiment of the present invention is a display device including a pixel array, a drive circuit, a first wiring, and a second wiring. The pixel array includes a first region and a second region, each including the same column. The first region includes a first pixel circuit, and the second region includes a second pixel circuit. The first pixel circuit and the second pixel circuit are located in the same column in the pixel array. The first wiring is a wiring extending in the first region along the column direction of the pixel array, and the second wiring is a wiring extending in the second region along the column direction of the pixel array. The drive circuit includes a demultiplexer, and the first pixel circuit is electrically connected to a first output terminal of the demultiplexer via the first wiring, and the second pixel circuit is electrically connected to a second output terminal of the demultiplexer via the second wiring.

[0019] (9) Alternatively, another aspect of the present invention is a display device having a pixel array, a drive circuit, first wiring, and second wiring, which differs from the configuration of (8) above. The pixel array has a first region and a second region, each including the same column, where the first region has a first pixel circuit and the second region has a second pixel circuit. The first pixel circuit and the second pixel circuit are located in the same column in the pixel array. The first wiring is a wiring that passes through the inside of the first region and extends along the column direction of the pixel array, and the second wiring is a wiring that passes through the insides of both the first region and the second region and extends along the column direction of the pixel array. The drive circuit also has a demultiplexer. The first pixel circuit is electrically connected to the first wiring, and a first output terminal of the demultiplexer is electrically connected to the first wiring. The second pixel circuit is electrically connected to the second wiring, and a second output terminal of the demultiplexer is electrically connected to the second wiring.

[0020] (10) Alternatively, another aspect of the present invention is a display device having a pixel array, a drive circuit, a first wiring, and a second wiring, which differs from the configurations of (8) and (9) above. The pixel array has a first region and a second region, each including a different column, and the first region has a first pixel circuit, and the second region has a second pixel circuit. The first pixel circuit and the second pixel circuit are located in different columns in the pixel array, and the first wiring is a wiring that extends within the first region along the column direction of the pixel array, and the second wiring is a wiring that extends within the second region along the column direction of the pixel array. The drive circuit has a demultiplexer, and the first pixel circuit is electrically connected to a first output terminal of the demultiplexer via the first wiring, and the second pixel circuit is electrically connected to a second output terminal of the demultiplexer via the second wiring.

[0021] (11) Alternatively, according to one aspect of the present invention, in any one of the above (8) to (10), the pixel circuit may further include a third wiring and a fourth wiring. The first pixel circuit may include a first transistor, and the second pixel circuit may include a second transistor. Preferably, the third wiring is a wiring extending in the row direction of the pixel array within the first region, and the fourth wiring is a wiring extending in the row direction of the pixel array within the second region. Preferably, one of the source or drain of the first transistor is electrically connected to the first wiring, and the gate of the first transistor is electrically connected to the third wiring. Preferably, one of the source or drain of the second transistor is electrically connected to the second wiring, and the gate of the second transistor is electrically connected to the fourth wiring.

[0022] (12) Alternatively, according to one aspect of the present invention, in the above (11), the pixel circuit may include a fifth wiring, a sixth wiring, a seventh wiring, and an eighth wiring. The first region may include a third pixel circuit, and the second region may include a fourth pixel circuit. The third pixel circuit may include a third transistor, and the fourth pixel circuit may include a fourth transistor. It is preferable that the third pixel circuit is located in a different column of the pixel array from the first pixel circuit, and the fourth pixel circuit is located in a different column of the pixel array from the second pixel circuit. It is also preferable that the fifth wiring is a wiring extending in the column direction of the pixel array within the first region, the sixth wiring is a wiring extending in the column direction of the pixel array within the second region, the seventh wiring is a wiring extending in the row direction of the pixel array within the first region, and the eighth wiring is a wiring extending in the row direction of the pixel array within the second region. Preferably, one of the source or drain of the third transistor is electrically connected to a fifth wiring, and the gate of the third transistor is electrically connected to a seventh wiring. Preferably, one of the source or drain of the fourth transistor is electrically connected to a sixth wiring, and the gate of the fourth transistor is electrically connected to an eighth wiring. Preferably, the fifth wiring is electrically connected to a third output terminal of the demultiplexer, and the sixth wiring is electrically connected to a fourth output terminal of the demultiplexer.

[0023] (13) Alternatively, in one aspect of the present invention, in any one of the above (8) to (12), the liquid crystal display device may include a first layer and a third layer located above the first layer. In particular, it is preferable that the first layer includes a driver circuit, and the third layer includes the pixel array.

[0024] (14) Another embodiment of the present invention is an electronic device including the display device described in any one of (1) to (13) above and a housing.

[0025] In this specification and the like, a semiconductor device is a device that utilizes semiconductor characteristics, and refers to a circuit including a semiconductor element (transistor, diode, photodiode, etc.), a device having such a circuit, etc. It also refers to any device that can function by utilizing semiconductor characteristics. For example, an integrated circuit, a chip including an integrated circuit, and an electronic component that houses a chip in a package are examples of semiconductor devices. Furthermore, memory devices, display devices, light-emitting devices, lighting devices, electronic devices, etc. may themselves be semiconductor devices or may include semiconductor devices.

[0026] Furthermore, when it is stated in this specification that X and Y are connected, it is understood that the following cases are disclosed in this specification: when X and Y are electrically connected, when X and Y are functionally connected, and when X and Y are directly connected. Therefore, it is not limited to a predetermined connection relationship, for example, a connection relationship shown in a figure or text, and it is understood that connections other than those shown in a figure or text are also disclosed in a figure or text. X and Y are understood to be objects (e.g., a device, an element, a circuit, wiring, an electrode, a terminal, a conductive film, a layer, etc.).

[0027] As an example of a case where X and Y are electrically connected, one or more elements (for example, a switch, a transistor, a capacitance element, an inductor, a resistance element, a diode, a display device, a light-emitting device, a load, etc.) that enable the electrical connection between X and Y can be connected between X and Y. The switch has a function of controlling on / off. In other words, the switch has a function of being in a conductive state (on state) or a non-conductive state (off state), and controls whether or not a current flows.

[0028] As an example of a case where X and Y are functionally connected, one or more circuits that enable the functional connection between X and Y (for example, logic circuits (inverters, NAND circuits, NOR circuits, etc.), signal conversion circuits (digital-analog conversion circuits, analog-digital conversion circuits, gamma correction circuits, etc.), potential level conversion circuits (power supply circuits (boosting circuits, step-down circuits, etc.), level shifter circuits that change the potential level of signals, etc.), voltage sources, current sources, switching circuits, amplifier circuits (circuits that can increase signal amplitude or current, operational amplifiers, differential amplifier circuits, source follower circuits, buffer circuits, etc.), signal generation circuits, memory circuits, control circuits, etc.) can be connected between X and Y. As an example, even if another circuit is sandwiched between X and Y, if a signal output from X is transmitted to Y, X and Y are considered to be functionally connected.

[0029] When it is explicitly stated that X and Y are electrically connected, this includes the case where X and Y are electrically connected (i.e., the case where X and Y are connected with another element or circuit between them) and the case where X and Y are directly connected (i.e., the case where X and Y are connected without another element or circuit between them).

[0030] Furthermore, for example, it can be expressed as follows: "X, Y, and the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor are electrically connected to each other, and are electrically connected in the order of X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y." Or, it can be expressed as follows: "The source (or first terminal, etc.) of the transistor is electrically connected to X, and the drain (or second terminal, etc.) of the transistor is electrically connected to Y, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are electrically connected in this order." Or, it can be expressed as follows: "X is electrically connected to Y via the source (or first terminal, etc.) and drain (or second terminal, etc.) of the transistor, and X, the source (or first terminal, etc.) of the transistor, the drain (or second terminal, etc.) of the transistor, and Y are provided in this connection order." By using expressions similar to these examples to define the order of connections in a circuit configuration, the source (or first terminal, etc.) and drain (or second terminal, etc.) of a transistor can be distinguished and the technical scope can be determined. Note that these expressions are merely examples and are not limiting. Here, X and Y are assumed to be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.).

[0031] Note that even when independent components are shown electrically connected in a circuit diagram, one component may have the functions of multiple components. For example, if part of a wiring also functions as an electrode, one conductive film has the functions of both wiring and an electrode. Therefore, the term "electrically connected" in this specification also includes such cases where one conductive film has the functions of multiple components.

[0032] Furthermore, in this specification and the like, a "resistance element" can be, for example, a circuit element having a resistance value higher than 0Ω, or a wiring having a resistance value higher than 0Ω. Therefore, in this specification and the like, a "resistance element" is intended to include a wiring having a resistance value, a transistor in which a current flows between the source and drain, a diode, a coil, and the like. Therefore, the term "resistance element" can sometimes be replaced with terms such as "resistance," "load," or "region having a resistance value." Conversely, the terms "resistance," "load," and "region having a resistance value" can sometimes be replaced with terms such as "resistance element." The resistance value can be, for example, preferably 1 mΩ or more and 10 Ω or less, more preferably 5 mΩ or more and 5 Ω or less, and even more preferably 10 mΩ or more and 1 Ω or less. Furthermore, for example, a resistance value can be replaced with a resistance value of 1 Ω or more and 1×10 9 It may be set to Ω or less.

[0033] Furthermore, in this specification, a "capacitive element" can refer to, for example, a circuit element having a capacitance value higher than 0 F, a wiring region having a capacitance value higher than 0 F, a parasitic capacitance, a gate capacitance of a transistor, etc. Furthermore, terms such as "capacitive element," "parasitic capacitance," and "gate capacitance" can sometimes be replaced with terms such as "capacitance." Conversely, the term "capacitance" can sometimes be replaced with terms such as "capacitive element," "parasitic capacitance," and "gate capacitance." Furthermore, the term "pair of electrodes" in "capacitance" can be replaced with "pair of conductors," "pair of conductive regions," "pair of regions," etc. The value of the capacitance can be, for example, 0.05 fF or more and 10 pF or less. It can also be, for example, 1 pF or more and 10 μF or less.

[0034] In this specification, a transistor has three terminals called a gate, a source, and a drain. The gate is a control terminal that controls the conduction state of the transistor. The two terminals that function as a source or a drain are input / output terminals of the transistor. One of the two input / output terminals serves as a source and the other as a drain depending on the conductivity type (n-channel or p-channel) of the transistor and the level of the potential applied to the three terminals of the transistor. Therefore, in this specification, the terms source and drain may be interchangeable. In addition, in this specification, when describing the connection relationship of a transistor, the terms "one of the source or drain" (or first electrode or first terminal) and "the other of the source or drain" (or second electrode or second terminal) are used. Note that, depending on the structure of the transistor, a backgate may be included in addition to the three terminals described above. In this case, in this specification, one of the gate or backgate of the transistor may be referred to as a first gate, and the other of the gate or backgate of the transistor may be referred to as a second gate. Furthermore, for the same transistor, the terms "gate" and "backgate" may be interchangeable. Furthermore, when a transistor has three or more gates, the gates may be referred to as a first gate, a second gate, a third gate, and so on in this specification and the like.

[0035] For example, in this specification, a transistor having a multi-gate structure with two or more gate electrodes can be used as an example of a transistor. In a multi-gate structure, the channel formation regions are connected in series, resulting in a structure in which multiple transistors are connected in series. Therefore, the multi-gate structure can reduce the off-state current and improve the breakdown voltage (reliability) of the transistor. Furthermore, when operating in the saturation region, the multi-gate structure can provide a voltage-current characteristic with a flat slope, whereby the current between the drain and source does not change significantly even when the voltage between the drain and source changes. By utilizing a voltage-current characteristic with a flat slope, an ideal current source circuit or an active load with a very high resistance value can be realized. As a result, a differential circuit or a current mirror circuit with excellent characteristics can be realized.

[0036] Furthermore, even when a single circuit element is shown on a circuit diagram, the circuit element may include multiple circuit elements. For example, when a circuit diagram shows one resistor, this includes two or more resistors electrically connected in series. For example, when a circuit diagram shows one capacitor, this includes two or more capacitors electrically connected in parallel. For example, when a circuit diagram shows one transistor, this includes two or more transistors electrically connected in series, with the gates of the transistors electrically connected to each other. Similarly, when a circuit diagram shows one switch, this includes two or more transistors electrically connected in series or parallel, with the gates of the transistors electrically connected to each other.

[0037] Furthermore, in this specification and the like, a node can be referred to as a terminal, a wiring, an electrode, a conductive layer, a conductor, an impurity region, etc. depending on the circuit configuration and / or device structure. Furthermore, a terminal, a wiring, etc. can be referred to as a node.

[0038] Furthermore, in this specification and the like, the terms "voltage" and "potential" can be interchanged as appropriate. "Voltage" refers to the potential difference from a reference potential. For example, if the reference potential is the ground potential (earth potential), then "voltage" can be interchanged with "potential." Note that ground potential does not necessarily mean 0 V. Furthermore, potential is relative, and as the reference potential changes, the potential applied to wiring, the potential applied to a circuit, etc., the potential output from a circuit, etc. also changes.

[0039] Furthermore, in this specification, the terms "high-level potential" and "low-level potential" do not refer to specific potentials. For example, when two wirings are both described as "functioning as wirings that supply a high-level potential," the high-level potentials provided by both wirings do not have to be equal to each other. Similarly, when two wirings are both described as "functioning as wirings that supply a low-level potential," the low-level potentials provided by both wirings do not have to be equal to each other.

[0040] "Current" refers to the phenomenon of charge transfer (electrical conduction). For example, a statement that "electrical conduction of a positively charged body is occurring" can be rephrased as "electrical conduction of a negatively charged body is occurring in the opposite direction." Therefore, in this specification, unless otherwise specified, "current" refers to the phenomenon of charge transfer (electrical conduction) associated with the movement of carriers. The carriers referred to here include electrons, holes, anions, cations, complex ions, etc., and the carriers differ depending on the system through which the current flows (e.g., semiconductor, metal, electrolyte, vacuum, etc.). Furthermore, the "direction of current" in wiring, etc., refers to the direction in which positively charged carriers move and is expressed as a positive current amount. In other words, the direction in which negatively charged carriers move is opposite to the direction of current flow and is expressed as a negative current amount. Therefore, in this specification, etc., unless otherwise specified regarding the positive or negative sign of the current (or the direction of current), a statement such as "current flows from element A to element B" can be rephrased as "current flows from element B to element A," etc. Furthermore, statements such as "current is input to element A" can be rephrased as "current is output from element A" or the like.

[0041] Furthermore, in this specification, the ordinal numbers "first," "second," and "third" are used to avoid confusion between components. Therefore, they do not limit the number of components. Furthermore, they do not limit the order of the components. For example, a component referred to as "first" in one embodiment of this specification may be a component referred to as "second" in another embodiment or in the claims. Furthermore, for example, a component referred to as "first" in one embodiment of this specification may be omitted in another embodiment or in the claims.

[0042] Furthermore, in this specification, terms indicating position, such as "above" and "below," may be used for convenience in describing the positional relationship between components with reference to the drawings. Furthermore, the positional relationship between components changes as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and can be rephrased appropriately depending on the situation. For example, the expression "an insulator located on the upper surface of a conductor" can be rephrased as "an insulator located on the lower surface of a conductor" by rotating the orientation of the drawing by 180 degrees.

[0043] Furthermore, the terms "above" and "below" do not limit the positional relationship of components to being directly above or below, and being in direct contact with each other. For example, the expression "electrode B on insulating layer A" does not require that electrode B be formed in direct contact with insulating layer A, and does not exclude the inclusion of other components between insulating layer A and electrode B.

[0044] Furthermore, in this specification, terms such as "row" and "column" may be used to describe components arranged in a matrix and their positional relationships. Furthermore, the positional relationships between components change as appropriate depending on the direction in which each component is depicted. Therefore, the terms are not limited to those used in the specification, and may be rephrased appropriately depending on the situation. For example, the expression "row direction" may be rephrased as "column direction" by rotating the orientation of the drawing by 90 degrees.

[0045] Furthermore, in this specification and the like, terms such as "film" and "layer" can be interchanged depending on the situation. For example, the term "conductive layer" may be interchanged with the term "conductive film." Or, for example, the term "insulating film" may be interchanged with the term "insulating layer." Or, in some cases or depending on the situation, terms such as "film" and "layer" may not be used and may be interchanged with other terms. For example, the terms "conductive layer" or "conductive film" may be interchanged with the term "conductor." Or, for example, the terms "insulating layer" and "insulating film" may be interchanged with the term "insulator."

[0046] Furthermore, in this specification and the like, terms such as "electrode," "wiring," and "terminal" do not functionally limit these components. For example, an "electrode" may be used as part of a "wiring," and vice versa. Furthermore, the terms "electrode" and "wiring" include cases where multiple "electrodes" or "wirings" are integrally formed. Furthermore, for example, a "terminal" may be used as part of a "wiring" or "electrode," and vice versa. Furthermore, the term "terminal" includes cases where multiple "electrodes," "wirings," "terminals," etc. are integrally formed. Therefore, for example, an "electrode" can be part of a "wiring" or "terminal," and a "terminal" can be part of a "wiring" or "electrode." Furthermore, terms such as "electrode," "wiring," and "terminal" may be replaced with terms such as "region" in some cases.

[0047] Furthermore, in this specification and the like, terms such as "wiring," "signal line," and "power line" may be interchangeable depending on the circumstances. For example, the term "wiring" may be changed to the term "signal line." For example, the term "wiring" may be changed to the term "power line." Vice versa, terms such as "signal line" and "power line" may be changed to the term "wiring." A term such as "power line" may be changed to the term "signal line." Vice versa, terms such as "signal line" may be changed to the term "power line." Furthermore, the term "potential" applied to a wiring may be changed to the term "signal" depending on the circumstances. Vice versa, terms such as "signal" may be changed to the term "potential."

[0048] In this specification and the like, the term "impurities" in semiconductors refers to, for example, elements other than the main components constituting the semiconductor layer. For example, an element with a concentration of less than 0.1 atomic % is an impurity. The presence of impurities can cause, for example, an increase in the defect level density of the semiconductor, a decrease in carrier mobility, and a decrease in crystallinity. When the semiconductor is an oxide semiconductor, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, Group 14 elements, Group 15 elements, and transition metals other than the main components, particularly, for example, hydrogen (also contained in water), lithium, sodium, silicon, boron, phosphorus, carbon, and nitrogen. Specifically, when the semiconductor is a silicon layer, impurities that change the semiconductor characteristics include, for example, Group 1 elements, Group 2 elements, Group 13 elements, and Group 15 elements (excluding oxygen and hydrogen).

[0049] In this specification, a switch refers to a device that can be in a conductive state (on state) or a non-conductive state (off state) and has the function of controlling whether or not a current flows. Alternatively, a switch refers to a device that has the function of selecting and switching a path through which a current flows. Therefore, a switch may have two or more terminals for passing a current in addition to a control terminal. As an example, an electrical switch, a mechanical switch, or the like can be used. In other words, the switch is not limited to a specific type as long as it can control a current.

[0050] Examples of electrical switches include transistors (e.g., bipolar transistors, MOS transistors, etc.), diodes (e.g., PN diodes, PIN diodes, Schottky diodes, MIM (Metal Insulator Metal) diodes, MIS (Metal Insulator Semiconductor) diodes, diode-connected transistors, etc.), and logic circuits combining these. When a transistor is used as a switch, the "conductive state" of the transistor refers to, for example, a state in which the source electrode and drain electrode of the transistor can be considered to be electrically short-circuited, and a state in which current can flow between the source electrode and drain electrode. The "non-conductive state" of the transistor refers to a state in which the source electrode and drain electrode of the transistor can be considered to be electrically disconnected. When a transistor is operated simply as a switch, the polarity (conductivity type) of the transistor is not particularly limited.

[0051] An example of a mechanical switch is a switch that uses MEMS (microelectromechanical systems) technology. This switch has a mechanically movable electrode, and the movement of the electrode controls whether the switch is conductive or non-conductive.

[0052] In this specification, etc., a device fabricated using a metal mask or an FMM (fine metal mask, high-resolution metal mask) may be referred to as an MM (metal mask) structure. In this specification, etc., a device fabricated without using a metal mask or an FMM may be referred to as an MML (metal maskless) structure.

[0053] In this specification, a structure in which different light-emitting layers are formed or different light-emitting layers are painted for each color light-emitting device (here, blue (B), green (G), and red (R)) may be referred to as an SBS (Side By Side) structure. In this specification, a light-emitting device that can emit white light may be referred to as a white light-emitting device. In addition, a white light-emitting device can be combined with a colored layer (e.g., a color filter) to form a full-color display device.

[0054] Light-emitting devices can be broadly divided into single structures and tandem structures. A single-structure device has one light-emitting unit between a pair of electrodes, and the light-emitting unit preferably includes one or more light-emitting layers. When two light-emitting layers are used to obtain white light emission, the two light-emitting layers can be selected so that the emission colors of the two light-emitting layers are complementary to each other. For example, by making the emission color of the first light-emitting layer and the emission color of the second light-emitting layer complementary to each other, a configuration in which the entire light-emitting device emits white light can be obtained. When three or more light-emitting layers are used to obtain white light emission, the emission colors of the three or more light-emitting layers can be combined to produce a configuration in which the entire light-emitting device emits white light.

[0055] A tandem-structured device preferably has two or more light-emitting units between a pair of electrodes, and each light-emitting unit preferably includes one or more light-emitting layers. To obtain white light, light from the light-emitting layers of the multiple light-emitting units may be combined to obtain white light. The configuration for obtaining white light is the same as that of the single-structured device. In a tandem-structured device, it is preferable to provide an intermediate layer such as a charge-generating layer between the multiple light-emitting units.

[0056] Furthermore, when comparing the above-mentioned white light-emitting device (single structure or tandem structure) with a light-emitting device having an SBS structure, the light-emitting device having an SBS structure can reduce power consumption compared to the white light-emitting device. If you want to keep power consumption low, it is preferable to use a light-emitting device having an SBS structure. On the other hand, the manufacturing process of a white light-emitting device is simpler than that of a light-emitting device having an SBS structure, so it is preferable because it can reduce manufacturing costs or increase manufacturing yields.

[0057] In this specification, "parallel" refers to a state in which two straight lines are arranged at an angle of -10° or more and 10° or less. Therefore, it also includes cases where the angle is -5° or more and 5° or less. Furthermore, "substantially parallel" or "roughly parallel" refers to a state in which two straight lines are arranged at an angle of -30° or more and 30° or less. Furthermore, "perpendicular" refers to a state in which two straight lines are arranged at an angle of 80° or more and 100° or less. Therefore, it also includes cases where the angle is 85° or more and 95° or less. Furthermore, "substantially perpendicular" or "approximately perpendicular" refers to a state in which two straight lines are arranged at an angle of 60° or more and 120° or less. [Effects of the Invention]

[0058] According to one embodiment of the present invention, a display device with a reduced circuit area can be provided. According to one embodiment of the present invention, a display device with reduced power consumption can be provided. According to one embodiment of the present invention, a display device with high display quality can be provided. According to one embodiment of the present invention, a high-resolution display device with a high frame frequency can be provided. According to one embodiment of the present invention, a novel display device can be provided. According to one embodiment of the present invention, an electronic device including any of the above-described display devices can be provided.

[0059] The effects of one embodiment of the present invention are not limited to the effects listed above. The effects listed above do not preclude the existence of other effects. The other effects are described below and are not mentioned in this section. Effects not mentioned in this section can be derived by a person skilled in the art from the description in the specification or drawings, and can be extracted as appropriate from these descriptions. One embodiment of the present invention has at least one of the effects listed above and other effects. Therefore, one embodiment of the present invention may not have the effects listed above in some cases. [Brief explanation of the drawings]

[0060] [Figure 1] FIG. 1 is a cross-sectional view showing a configuration example of a display device. [Figure 2] FIG. 2A is a schematic top view showing an example of the configuration of a circuit layer included in a display device, and FIG. 2B is a schematic top view showing an example of the configuration of the display device. [Figure 3] FIG. 3A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 3B is a cross-sectional view that schematically shows the example of the configuration of the display device. [Figure 4] FIG. 4A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 4B is a cross-sectional view that schematically shows an example of the configuration of a display device. [Figure 5] FIG. 5A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 5B is a schematic cross-sectional view that shows the example of the configuration of the display device. [Figure 6]6A to 6C are diagrams illustrating electrical connections between pixels and wirings included in a display device. [Figure 7] FIG. 7 is a schematic top view showing an example of the configuration of a display device. [Figure 8] 8A and 8B are schematic top views showing configuration examples of a display device. [Figure 9] 9A and 9B are schematic top views showing configuration examples of a display device. [Figure 10] 10A and 10B are schematic top views showing configuration examples of a display device. [Figure 11] FIG. 11 is a schematic top view showing an example of the configuration of a display device. [Figure 12] FIG. 12 is a schematic top view showing an example of the configuration of a display device. [Figure 13] FIG. 13 is a block diagram showing an example of the configuration of a display device. [Figure 14] FIG. 14 is a block diagram showing an example of the configuration of a display device. [Figure 15] FIG. 15 is a timing chart showing an example of the operation of the display device. [Figure 16] FIG. 16A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 16B is a perspective view that schematically shows an example of the configuration of a circuit included in the display device. [Figure 17] FIG. 17A is a block diagram showing an example of the configuration of a display device. [Figure 18] 18A to 18F are block diagrams illustrating an example of the operation of the display device. [Figure 19] FIG. 19 is a block diagram showing an example of the configuration of a display device. [Figure 20] FIG. 20 is a block diagram showing an example of the configuration of a display device. [Figure 21] FIG. 21 is a block diagram showing an example of the configuration of a display device. [Figure 22] FIG. 22 is a block diagram showing an example of the configuration of a display device. [Figure 23] FIG. 23 is a block diagram showing an example of the configuration of a display device. [Figure 24] FIG. 24 is a block diagram showing an example of the configuration of a circuit included in the display device. [Figure 25] FIG. 25 is a block diagram showing an example of the configuration of a display device. [Figure 26] FIG. 26A is a perspective view that schematically shows an example of the configuration of a display device, and FIG. 26B is a perspective view that schematically shows an example of the configuration of a circuit included in the display device. [Figure 27] FIG. 27 is a cross-sectional view showing a configuration example of a display device. [Figure 28] 28A and 28B are cross-sectional schematic views showing examples of the configuration of a transistor. [Figure 29] 29A and 29B are cross-sectional schematic views showing examples of the configuration of a transistor. [Figure 30] 30A to 30C are schematic diagrams showing configuration examples of light-emitting devices. [Figure 31] 31A and 31B are cross-sectional schematic views showing configuration examples of a display device. [Figure 32] 32A to 32C are cross-sectional views showing examples of the configuration of a display device. [Figure 33] 33A to 33D are cross-sectional views showing examples of the configuration of a display device. [Figure 34] FIG. 34A is a diagram illustrating the classification of IGZO crystal structures, FIG. 34B is a diagram illustrating the XRD spectrum of crystalline IGZO, and FIG. 34C is a diagram illustrating the micro-electron beam diffraction pattern of crystalline IGZO. [Figure 35] 35A and 35B are diagrams showing configuration examples of a display module. [Figure 36] 36A to 36F are diagrams showing configuration examples of electronic devices. [Figure 37] 37A and 37B are diagrams showing configuration examples of a display module. [Figure 38] 38A and 38B are diagrams showing configuration examples of electronic devices. [Figure 39]39A to 39C are diagrams showing configuration examples of electronic devices. [Figure 40] 40A to 40D are diagrams showing configuration examples of electronic devices. DETAILED DESCRIPTION OF THE INVENTION

[0061] In this specification and the like, a metal oxide refers to an oxide of a metal in a broad sense. Metal oxides are classified into oxide insulators, oxide conductors (including transparent oxide conductors), oxide semiconductors (also referred to as oxide semiconductors or simply as OSs), and the like. For example, when a metal oxide is contained in a channel formation region of a transistor, the metal oxide may be referred to as an oxide semiconductor. In other words, when a metal oxide can form a channel formation region of a transistor having at least one of an amplifying function, a rectifying function, and a switching function, the metal oxide can be referred to as a metal oxide semiconductor. Furthermore, an OS transistor can be rephrased as a transistor including a metal oxide or an oxide semiconductor.

[0062] In this specification and the like, nitrogen-containing metal oxides may also be collectively referred to as metal oxides. Nitrogen-containing metal oxides may also be referred to as metal oxynitrides.

[0063] In this specification and the like, the configurations shown in each embodiment can be combined as appropriate with the configurations shown in other embodiments to form one aspect of the present invention. In addition, when multiple configuration examples are shown in one embodiment, the configuration examples can be combined as appropriate with each other.

[0064] In addition, the content (or even part of the content) described in one embodiment can be applied, combined, or replaced with at least one of another content (or even part of the content) described in that embodiment and another content (or even part of the content) described in one or more other embodiments.

[0065] The contents described in the embodiments refer to the contents described in each embodiment using various figures or the contents described using text in the specification.

[0066] Furthermore, a figure (or even a part thereof) described in one embodiment can be combined with another part of that figure, another figure (or even a part thereof) described in that embodiment, and at least one figure (or even a part thereof) described in one or more other embodiments to form even more figures.

[0067] The embodiments described in this specification are described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways, and that various changes in form and details can be made without departing from the spirit and scope of the invention. Therefore, the present invention should not be interpreted as being limited to the description of the embodiments. Note that in the configuration of the invention of the embodiments, the same reference numerals are used in different drawings for the same parts or parts having similar functions, and repeated description thereof may be omitted. Also, in perspective views and the like, the description of some components may be omitted to ensure clarity of the drawings.

[0068] In this specification, when the same reference numeral is used for multiple elements, and particularly when it is necessary to distinguish between them, an identification symbol such as "_1", "[n]", "[m,n]" may be added to the reference numeral. Also, when an identification symbol such as "_1", "[n]", "[m,n]" is added to the reference numeral in the drawings, etc., the identification symbol may not be added if it is not necessary to distinguish between them in this specification.

[0069] In addition, in the drawings of this specification, the size, layer thickness, or region may be exaggerated for clarity. Therefore, the drawings are not necessarily limited to the scale. Note that the drawings are schematic illustrations of ideal examples, and are not limited to the shapes or values ​​shown in the drawings. For example, variations in signals, voltages, or currents due to noise, or variations in signals, voltages, or currents due to timing differences may be included.

[0070] (Embodiment 1) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0071] 1 is a cross-sectional view of a display device according to one embodiment of the present invention. The display device 10 includes a pixel layer PXAL, a wiring layer LINL, and a circuit layer SICL.

[0072] The wiring layer LINL is provided on the circuit layer SICL, and the pixel layer PXAL is provided on the wiring layer LINL. The pixel layer PXAL overlaps a region including a drive circuit region DRV (described later) and a region LIA (described later).

[0073] The circuit layer SICL has a substrate BS, a drive circuit region DRV, and a region LIA.

[0074] The substrate BS can be, for example, a semiconductor substrate (e.g., a single-crystal substrate) made of silicon or germanium. In addition to semiconductor substrates, the substrate BS can also be, for example, an SOI (Silicon-On-Insulator) substrate, a glass substrate, a quartz substrate, a plastic substrate, a sapphire glass substrate, a metal substrate, a stainless steel substrate, a substrate with stainless steel foil, a tungsten substrate, a substrate with tungsten foil, a flexible substrate, a laminated film, paper containing a fibrous material, or a base film. Examples of glass substrates include barium borosilicate glass, aluminoborosilicate glass, and soda-lime glass. Examples of flexible substrates, laminated films, and base films include the following: Plastics such as polyethylene terephthalate (PET), polyethylene naphthalate (PEN), polyethersulfone (PES), and polytetrafluoroethylene (PTFE). Another example is a synthetic resin such as acrylic resin. Other examples include polypropylene, polyester, polyvinyl fluoride, polyvinyl chloride, etc. Other examples include polyamide, polyimide, aramid, epoxy resin, inorganic vapor deposition film, paper, etc. If the manufacturing process of the display device 10 includes a heat treatment, it is preferable to select a material with high heat resistance for the substrate BS.

[0075] In this embodiment, the substrate BS is described as a semiconductor substrate made of silicon or the like. Therefore, the transistors included in the driver circuit region DRV can be transistors having silicon in their channel formation regions (hereinafter referred to as Si transistors).

[0076] The drive circuit region DRV and the region LIA are provided on a substrate BS.

[0077] The drive circuit region DRV has, as an example, a drive circuit for driving pixels included in a pixel layer PXAL, which will be described later. Note that a specific configuration example of the drive circuit region DRV will be described later.

[0078] As an example, wiring is provided in the region LIA. The wiring included in the region LIA may be electrically connected to wiring included in the wiring layer LINL. In this case, the display device 10 may be configured such that the circuit included in the drive circuit region DRV and the circuit included in the pixel layer PXAL are electrically connected by the wiring included in the region LIA and the wiring included in the wiring layer LINL. The display device 10 may be configured such that the circuit included in the drive circuit region DRV and the wiring or circuit included in the region LIA are electrically connected via the wiring included in the wiring layer LINL.

[0079] Furthermore, the region LIA may include, for example, a GPU (Graphics Processing Unit). Furthermore, if the display device 10 includes a touch panel, the region LIA may include a sensor controller that controls a touch sensor included in the touch panel. Furthermore, if a light-emitting device using an organic EL material (sometimes referred to as an organic EL element) is used as the display element of the display device 10, the region LIA may include an EL correction circuit that corrects variations in the luminance of the light emitted by a plurality of organic EL elements. Furthermore, if a liquid crystal element is used as the display element of the display device 10, the region LIA may include a gamma correction circuit.

[0080] The wiring layer LINL is provided on the circuit layer SICL.

[0081] The wiring layer LINL is provided with wiring, for example, and the wiring included in the wiring layer LINL functions as wiring that electrically connects, for example, a drive circuit included in the drive circuit region DRV provided below and a circuit included in the pixel layer PXAL provided above.

[0082] The pixel layer PXAL has, for example, a plurality of pixels, which may be arranged in a matrix in the pixel layer PXAL.

[0083] Each of the multiple pixels can express one or more colors. In particular, the multiple colors can be, for example, three colors: red (R), green (G), and blue (B). Alternatively, the multiple colors can be, for example, red (R), green (G), and blue (B) plus at least one color selected from cyan, magenta, yellow, and white. Each pixel expressing a different color is called a sub-pixel, and when white is expressed by multiple sub-pixels of different colors, the multiple sub-pixels are sometimes collectively referred to as a pixel. For convenience, in this specification and other descriptions, sub-pixels will be referred to as pixels.

[0084] 2A is an example of a top view of the display device 10, showing only the circuit layer SICL. The display device 10 shown in FIG. 2A has, as an example, a configuration in which a drive circuit region DRV is surrounded by a region LIA.

[0085] In FIG. 2A, the drive circuit region DRV includes, for example, a plurality of local driver circuits LD, a controller CON, and a voltage generating circuit PG.

[0086] The controller CON has, for example, a function of processing an input signal from outside the display device 10. The input signal may be, for example, an image signal, an address signal including a destination of the image signal, etc. The controller CON selects a local driver circuit LD included in the drive circuit region DRV in response to the address signal, and transmits the image signal to the selected local driver circuit LD.

[0087] Furthermore, since a plurality of local driver circuits LD are provided in the drive circuit region DRV, the controller CON may be configured to transmit image signals to the plurality of local driver circuits LD in parallel at the same time.

[0088] For example, the voltage generation circuit PG functions as a circuit that generates a power supply voltage for driving circuits included in the drive circuit region DRV (for example, a source driver circuit, a gate driver circuit, etc., which will be described later.) The voltage generation circuit PG may also have a function of generating a voltage to be supplied to pixels included in the pixel layer PXAL, which will be described later.

[0089] Each of the local driver circuits has a function of driving pixels included in the pixel layer PXAL, for example. That is, for example, each of the local driver circuits can be configured to include a source driver circuit and a gate driver circuit. Furthermore, since there are multiple local driver circuits, it is possible to determine the region of pixels included in the pixel layer PXAL to be driven by each local driver circuit.

[0090] For example, consider a case where the pixel array ALP included in the pixel layer PXAL in the display device 10 is divided into regions with m rows and n columns (m is an integer greater than or equal to 1, and n is an integer greater than or equal to 1). In this case, the number of local driver circuits included in the drive circuit region DRV is m×n. 2A shows, as an example, the local driver circuit LD[1,1], the local driver circuit LD[1,2], the local driver circuit LD[2,1], the local driver circuit LD[2,2], the local driver circuit LD[m-1,1], the local driver circuit LD[m-1,2], the local driver circuit LD[m,1], the local driver circuit LD[m,2], the local driver circuit LD[1,n-1], the local driver circuit LD[1,n], the local driver circuit LD[2,n-1], the local driver circuit LD[2,n], the local driver circuit LD[m-1,n-1], the local driver circuit LD[m-1,n], the local driver circuit LD[m,n-1], and the local driver circuit LD[m,n].

[0091] FIG. 2B shows pixel regions when the pixel array ALP included in the pixel layer PXAL is divided into regions of m rows and n columns. FIG. 2B is a top view of the display device 10, and shows only the drive circuit region DRV and the pixel array ALP. In particular, in FIG. 2B, the drive circuit region DRV is indicated by a solid line, and the pixel array ALP is indicated by a dashed line. As shown in FIG. 2B, in the top view, the position of the drive circuit region DRV overlaps the inside of the pixel array ALP. In addition, in FIG. 2B, the pixel array ALP is divided into pixel regions ARA[1,1] to ARA[m,n], as an example. In addition, in Figure 2B, as an example, the symbols for pixel area ARA[1,1], pixel area ARA[2,1], pixel area ARA[m-1,1], pixel area ARA[m,1], pixel area ARA[1,n], pixel area ARA[2,n], pixel area ARA[m-1,n], and pixel area ARA[m,n] are excerpted and shown.

[0092] As an example, if it is desired to divide the pixel array ALP into 32 regions, m = 4 and n = 8 can be applied to FIGS. 2A and 2B. Incidentally, if the resolution of the display device 10 is 8K4K, the number of pixels is 7680 × 4320 pixels. Furthermore, if the sub-pixels of the display device 10 are of three colors, red (R), green (G), and blue (B), the total number of sub-pixels is 7680 × 4320 × 3. Here, if the pixel array of the display device 10 with an 8K4K resolution is divided into 32 regions, the number of pixels per region is 960 × 1080 pixels. Furthermore, if the sub-pixels of the display device 10 are of three colors, red (R), green (G), and blue (B), the number of sub-pixels per region is 960 × 1080 × 3.

[0093] 2B, as an example, the local driver circuit LD[1,1] drives the pixels included in the pixel region ARA[1,1], and the local driver circuit LD[2,1] drives the pixels included in the pixel region ARA[2,1]. The local driver circuit LD[m-1,1] drives the pixels included in the pixel region ARA[m-1,1], and the local driver circuit LD[m,1] drives the pixels included in the pixel region ARA[m,1]. The local driver circuit LD[1,n] drives the pixels included in the pixel region ARA[1,n], and the local driver circuit LD[2,n] drives the pixels included in the pixel region ARA[2,n]. The local driver circuit LD[m-1,n] drives the pixels included in the pixel region ARA[m-1,n], and the local driver circuit LD[m,n] drives the pixels included in the pixel region ARA[m,n]. That is, although not shown in Fig. 2B, the local driver circuit LD[i,j] located in row i and column j (i is an integer between 1 and m, and j is an integer between 1 and n) drives the pixels included in the pixel area ARA[i,j]. Note that in Fig. 2B, as an example, the correspondence between the pixel area ARA and the local driver circuit LD that drives the pixels included in that pixel area ARA is shown by a thick arrow.

[0094] As shown in Fig. 2B, when the position of the drive circuit region DRV overlaps the inside of the pixel array ALP in top view, the wiring (e.g., source wiring, gate wiring, constant voltage line, etc.) electrically connecting the pixels of the pixel region ARA and the local driver circuit LD is provided as shown in Fig. 3A, for example. In other words, the display device of the present invention is configured such that the wiring electrically connecting the local driver circuit LD and the pixel region ARA corresponding to the local driver circuit LD is extended to the wiring layer LINL.

[0095] 3A, the wiring group GLS[1,1] functions as, for example, a plurality of gate wirings that electrically connect a plurality of pixels included in the pixel region ARA[1,1] to the gate driver circuit included in the local driver circuit LD[1,1]. The wiring group SLS[1,1] functions as, for example, a plurality of source wirings that electrically connect a plurality of pixels included in the pixel region ARA[1,1] to the source driver circuit included in the local driver circuit LD[1,1]. The wiring group GLS[2,1] functions as, for example, a plurality of gate wirings that electrically connect a plurality of pixels included in the pixel region ARA[2,1] to the gate driver circuit included in the local driver circuit LD[2,1]. The wiring group SLS[1,2] functions as, for example, a plurality of source wirings that electrically connect a plurality of pixels included in the pixel region ARA[1,2] to the source driver circuit included in the local driver circuit LD[1,2].

[0096] 3A, consider a case where each of pixel regions ARA[1,1] to ARA[m,n] has, for example, a plurality of pixels arranged in a matrix of s rows and t columns (s is an integer greater than or equal to 1, and t is an integer greater than or equal to 1). In this case, for example, each of wiring groups GLS[1,1] and GLS[2,1] has s gate wirings, and each of wiring groups SLS[1,1] and SLS[1,2] has t source wirings. In addition, in Figure 3A, wiring GL[1,1]_1, wiring GL[1,1]_2, and wiring GL[1,1]_s are selected and illustrated as wirings included in the wiring group GLS[1,1], wiring GL[2,1]_1, wiring GL[2,1]_2, and wiring GL[2,1]_s are selected and illustrated as wirings included in the wiring group GLS[2,1], wiring SL[1,1]_1, wiring SL[1,1]_2, and wiring SL[1,1]_t are selected and illustrated as wirings included in the wiring group SLS[1,1], and wiring SL[1,2]_1, wiring SL[1,2]_2, and wiring SL[1,2]_t are selected and illustrated as wirings included in the wiring group SLS[1,2].

[0097] Although not shown, the wiring layer LINL may be provided with wiring other than the gate wiring and the source wiring. For example, the wiring layer LINL may be provided with wiring for applying a constant voltage from the voltage generating circuit PG included in the circuit layer SICL to the pixels included in the pixel array ALP.

[0098] The wiring layer LINL may have a configuration including a plurality of layers. Specifically, for example, as shown in Fig. 3B, the wiring layer LINL may have a configuration in which different wirings are superimposed.

[0099] FIG. 3B shows a cross-sectional view of an example in which a circuit layer SICL, a wiring layer LINL, and a pixel layer PXAL are stacked. Note that in the pixel layer PXAL of FIG. 3B, only the pixel regions ARA[1,1], ARA[2,2], and ARA[3,3] are illustrated, each shown as a block diagram. Also, in FIG. 3B, the circuit layer SICL includes a local driver circuit LD[1,1] and a local driver circuit LD[2,2], each of which includes a transistor 300. The transistor 300 of FIG. 3 also includes a low-resistance region 314a and a semiconductor region 313, both of which will be described in detail in the fourth embodiment.

[0100] 3B, one of the source and drain of the transistor 300 in the local driver circuit LD[1,1] is electrically connected to the pixel region ARA[1,1] via a wiring GL[1,1]_1 (wiring SL[1,1]_1). Also, one of the source and drain of the transistor 300 in the local driver circuit LD[2,2] is electrically connected to the pixel region ARA[2,2] via a wiring GL[2,2]_1 (wiring SL[2,2]_1). Also, FIG. 3B shows a configuration in which the pixel region ARA[3,3] and the wiring GL[3,3]_1 (wiring SL[3,3]_1) are electrically connected.

[0101] 3B shows a configuration in which the wiring GL[1,1]_1 (wiring SL[1,1]_1) has a contact portion VA and a conductor ER. In addition, a conductor CD is formed on the low-resistance region 314a of the transistor 300. Therefore, the pixel region ARA[1,1] and the local driver circuit LD[1,1] are electrically connected by the contact portion VA, the conductor ER, and the conductor CD. Note that the conductor CD can be referred to as a contact portion because it electrically connects the wiring GL[1,1]_1 (wiring SL[1,1]_1) and the low-resistance region 314a of the transistor 300.

[0102] However, during design, for example, depending on the positional relationship of the wiring electrically connecting the local driver circuit LD and the pixel area ARA corresponding to the local driver circuit LD, the wiring may overlap with other wiring. In this case, as shown in FIG. 3B, by providing the overlapping wiring in different layers, the local driver circuit LD can be electrically connected to the pixel area ARA corresponding to the local driver circuit LD without physical contact between the different wiring. For example, FIG. 3B shows a configuration in which the wiring electrically connecting the pixel area ARA[1,1] and the local driver circuit LD[1,1] and the wiring electrically connecting the pixel area ARA[2,2] and the local driver circuit LD[2,2] are routed so as not to physically contact each other. Also, for example, FIG. 3B shows a configuration in which the wiring electrically connecting the pixel area ARA[2,2] and the local driver circuit LD[2,2] and the wiring electrically connected to the pixel area ARA[3,3] are routed so as not to physically contact each other.

[0103] Furthermore, in order to suppress signal delays and / or to suppress increases in power consumption due to parasitic resistance, etc., it is preferable that the wiring (gate wiring, source wiring, etc.) for transmitting signals from the local driver circuit LD to the pixels in the pixel area ARA be short. For this reason, it is preferable that the wiring electrically connecting the local driver circuit LD and the pixel area ARA in the display device 10 be designed to be short. One example of a design for this purpose is to design the wiring contact between the pixel area ARA and the wiring layer LINL to be in an optimal position for each pixel area ARA.

[0104] Furthermore, in Figures 3A and 3B, a configuration has been described in which the drive circuit region DRV of the circuit layer SICL and the pixel region ARA of the pixel layer PXAL are electrically connected via wiring in the wiring layer LINL. However, a display device of one embodiment of the present invention may also be configured such that the drive circuit region DRV of the circuit layer SICL and the pixel region ARA of the pixel layer PXAL are electrically connected via wiring in the region LIA in addition to the wiring in the wiring layer LINL.

[0105] For example, as shown in FIG. 4A, the wiring GL[1,1]_1 (wiring SL[1,1]_1) electrically connected between the local driver circuit LD[1,1] and the pixel region ARA[1,1] included in the display device 10 may be a wiring that electrically connects one of the source or drain of the transistor 300 to the pixel region ARA[1,1] in the following order: wiring in the wiring layer LINL, wiring included in the region LIA (wiring depicted by a thick dotted line), and wiring in the wiring layer LINL again. A cross-sectional view of the display device 10 in this case is also shown in FIG. 4B. As an example, the display device 10 in FIG. 4B is configured such that the path of the wiring GL[1,1]_1 (wiring SL[1,1]_1) electrically connected between the local driver circuit LD[1,1] and the pixel region ARA[1,1] in the drive circuit region DRV passes through a low-resistance region 314c provided on the substrate BS in the region LIA of the circuit layer SICL. When the substrate BS is a semiconductor substrate made of silicon, the low resistance region 314c can be formed by doping with an element that provides conductivity.

[0106] Furthermore, for example, as shown in FIG. 5A, the wiring GL[1,1]_1 (wiring SL[1,1]_1) electrically connected between the local driver circuit LD[1,1] and the pixel region ARA[1,1] included in the display device 10 may be a wiring that electrically connects one of the source or drain of the transistor 300 to the pixel region ARA[1,1] in the following order: wiring included in the region LIA (wiring drawn with a thick dotted line); wiring in the wiring layer LINL. A cross-sectional view of the display device 10 in this case is shown in FIG. 5B. The display device 10 in FIG. 5B includes, as an example, a low-resistance region 314c in which one of the source or drain of the transistor 300 is formed to extend into the region LIA. In other words, the low-resistance region 314c includes one of the source or drain of the transistor 300. The display device 10 is configured such that the local driver circuit LD[1,1] in the drive circuit region DRV and the pixel region ARA[1,1] are electrically connected by the low resistance region 314c, the wiring included in the wiring layer LINL, and the like.

[0107] <<Contact between pixel area ARA and wiring layer LINL>> Here, the position of the wiring contact between the pixel region ARA and the wiring layer LINL will be described. FIG. 6A is a schematic diagram illustrating, as an example, the pixel region ARA and multiple pixels PIX included in the pixel region ARA. Note that, as an example, the multiple pixels PIX are arranged in a matrix in the pixel region ARA. Also, FIG. 6A illustrates, as an example, a configuration in which each pixel PIX includes a transistor Tr, and other circuit elements are not illustrated. Also, as an example, in the pixel region ARA of FIG. 6A, a wiring group SLS (wirings SL_1, SL_2, and SL_3) extends in the X direction. Note that, although FIG. 6A illustrates three wirings included in the wiring group SLS, the number of wirings may be one, two, or four or more. Also, the wiring group GLS and the like are not illustrated. Also, in this specification, the X direction may be referred to as the row direction, and the Y direction may be referred to as the column direction.

[0108] 6A, the position of the contact portion of the wiring between the pixel region ARA and the wiring layer LINL is provided, for example, at the edge of the pixel region ARA. Note that in FIG. 6A, the contact portion of the wiring between the pixel region ARA and the wiring layer LINL is designated as the contact portion CNT. In this case, the local driver circuit LD is preferably located in the positive X direction with respect to the pixel region ARA. Conversely, if the local driver circuit LD is located in the negative X direction with respect to the pixel region ARA, the length of the wiring between the pixel region ARA and the local driver circuit LD corresponding to the pixel region ARA becomes longer, which may result in signal delays being more likely to occur and / or increased power consumption due to parasitic resistance, etc.

[0109] Furthermore, the position of the contact of the wiring between the pixel region ARA and the wiring layer LINL may be, for example, provided so as to be included inside the pixel PIX, as shown in FIG. 6B. In this case, it is preferable that the local driver circuit LD is located in the positive or negative Y direction with respect to the pixel region ARA. Note that, in FIG. 6B, each contact portion CNT is provided inside the pixel PIX of a different column in each wiring group SLS, but the contact portion CNT may be provided inside the pixel PIX of the same column in each wiring group SLS.

[0110] Also, while FIG. 6B shows an example in which the contact portion CNT is provided inside the pixel PIX, the contact portion CNT may be provided outside the pixel PIX (between adjacent pixels PIX) as shown in FIG. 6C.

[0111] In this specification and the like, the inside of the pixel PIX can be, for example, a region overlapping with the light-emitting region of a light-emitting device (light-emitting device 150a to light-emitting device 150c described later) included in the pixel PIX, and the outside of the pixel PIX can be, for example, the outside of this region. The inside of the pixel PIX can be, for example, a region overlapping with an EL layer (EL layer 141a to EL layer 141c described later) included in the pixel PIX, and the outside of the pixel PIX can be, for example, the outside of this region. The inside of the pixel PIX can be, for example, a region overlapping with an opening of an insulator (opening of the insulator 112 reaching a lower electrode included in the pixel PIX) (the opening of the conductor 121a to conductor 121c described later), and the outside of the pixel PIX can be, for example, the outside of this region. The inside of the pixel PIX can be, for example, a region overlapping with a lower electrode (conductor 121a to conductor 121c described later) included in the pixel PIX, and the outside of the pixel PIX can be, for example, the outside of this region.

[0112] In this specification and the like, the boundary between the inside and outside of a pixel PIX may be described as being included within the pixel PIX, and depending on the situation, the boundary between the inside and outside of a pixel PIX may be described as being included outside of the pixel PIX.

[0113] Furthermore, depending on the positional relationship between the pixel region ARA and the local driver circuit LD, the positions of the plurality of contact portions CNT may be a combination of the cases shown in Figures 6A to 6C. That is, the positions of the plurality of contact portions CNT may be configured such that some of them are located at the edge of the pixel region ARA, another part is located inside the pixel PIX, and the rest is located outside the pixel PIX.

[0114] <<Positional relationship between pixel area ARA and local driver circuit LD>> Here, the routing of the wiring that electrically connects the pixel area ARA and the local driver circuit LD according to the positional relationship between the pixel area ARA and the local driver circuit LD will be described.

[0115] FIG. 7 is a top view showing, in the display device 10, a pixel area ARA included in the pixel layer PXAL and a local driver circuit LD included in the circuit layer SICL and corresponding to the pixel area ARA.

[0116] In the pixel area ARA of FIG. 7, pixel circuits PIX are arranged in a matrix of v rows and w columns (v is an integer greater than or equal to 1, and w is an integer greater than or equal to 1), and in the pixel area ARA, wirings SLu_1 to SLu_w extend in the column direction as source wirings. In addition, in the lower layer including the wiring layer LINL of FIG. 7, wirings SLd_1 to SLd_w for electrical connection to the drive circuit SD extend in one direction. That is, each of the wirings SLd_1 to SLd_w extends approximately parallel or parallel to each other. In FIG. 7, each of the wirings SLd_1 to SLd_w is illustrated as a two-dot chain line.

[0117] 7, the drive circuit SD has a plurality of output terminals SDT. Here, it is assumed that each of the plurality of output terminals SDT is electrically connected to the wirings SLd_1 to SLd_w. Also, in FIG. 7, the arrangement direction of the plurality of output terminals SDT (the direction of the drive circuit SD) is arranged so as to be substantially perpendicular or perpendicular to each of the wirings SLd_1 to SLd_w. In other words, the plurality of output terminals SDT are arranged, for example, along one direction.

[0118] Here, the multiple output terminals SDT will be described. For example, if the driver circuit SD includes a demultiplexer and each output terminal of the demultiplexer is directly and electrically connected to each of the wirings SLd_1 to SLd_w, the output terminal SDT can be a terminal of a switch included in the demultiplexer. Furthermore, if the driver circuit SD includes multiple amplifiers and each output terminal of the amplifiers is directly and electrically connected to each of the wirings SLd_1 to SLd_w, the multiple output terminals SDT can be the output terminals of the amplifiers. Furthermore, if the output terminal of an amplifier is electrically connected to the source, drain, or gate of a transistor included in the amplifier, the multiple output terminals SDT can be the source, drain, or gate of the transistor. Furthermore, if the driver circuit SD includes multiple digital-to-analog conversion circuits (hereinafter referred to as DACs) and each output terminal of the DACs is directly and electrically connected to each of the wirings SLd_1 to SLd_w, the multiple output terminals SDT can be the output terminals of the DACs. Furthermore, when the output terminal of the DAC is electrically connected to the source, drain, or gate of a transistor included in the DAC, the multiple output terminals SDT can be the source, drain, or gate of the transistor.

[0119] Furthermore, the wirings SLd_1 to SLd_w are electrically connected to the wirings Slu_1 to Slu_w, respectively, via contact portions CNT. Note that the wirings SLd_1 and Slu_1 may be collectively referred to as wirings SL_1, the wirings SLd_2 and Slu_2 may be collectively referred to as wirings SL_2, and the wirings SLd_w and Slu_w may be collectively referred to as wirings SL_w.

[0120] 7, the pixel area ARA and the drive circuit SD included in the local driver circuit LD are arranged so that the wirings SLu_1 to SLu_w and the wirings SLd_1 to SLd_w are substantially perpendicular, preferably perpendicular. That is, in the top view of the display device 10 in FIG. 7, the drive circuit SD is positioned so that it is substantially parallel to or parallel to the column direction of the pixel area ARA of the display device 10. Therefore, the arrangement direction of the multiple output terminals SDT (the direction of the drive circuit SD) is substantially parallel to or parallel to the columns of the pixel area ARA.

[0121] When the drive circuit SD included in the local driver circuit LD corresponding to the pixel area ARA is positioned in the column direction of the pixel area ARA in a top view, as shown in FIG. 7, by routing the wirings SLd_1 to SLd_w, the length of the source wiring electrically connecting the pixel area ARA and the drive circuit SD can be minimized. By shortening the source wiring, the parasitic resistance and parasitic capacitance associated with the source line can be reduced, thereby reducing the time constant. This shortens the transmission time of a signal including image data from the drive circuit SD to the pixel circuit PIX included in the pixel area ARA. Therefore, a display device including the pixel area ARA and the local driver circuit LD can display images with a high frame frequency.

[0122] Note that the positional relationship between the pixel region ARA and the local driver circuit LD in the display device of one embodiment of the present invention is not limited to that shown in Fig. 7. For example, as shown in Fig. 8A , when the local driver circuit LD corresponding to the pixel region ARA is not located in the column direction of the pixel region ARA in a top view, specifically, when the wirings SLd_1 to SLd_w are routed in a direction approximately perpendicular, preferably perpendicular to the wirings SLu_1 to SLu_w, the local driver circuit LD and the wirings SLd_1 to SLd_w are not electrically connected to each other, the orientation of the driver circuit SD included in the local driver circuit LD (the arrangement direction of the multiple output terminals SDT) may be changed.

[0123] By changing the orientation of the drive circuit SD (the orientation of the arrangement of the plurality of output terminals SDT) inside the local driver circuit LD and routing the wirings SLd_1 to SLd_w in a direction that is substantially perpendicular, preferably perpendicular, to the orientation of the arrangement of the plurality of output terminals SDT, the wirings SLu_1 to SLu_w in the pixel region ARA and the wirings SLd_1 to SLd_w can be electrically connected to each other via the contact portions CNT in a top view. In other words, when the positional relationship between the pixel region ARA and the local driver circuit LD is as shown in FIG. 8A, the wirings SLu_1 to SLu_w and the wirings SLd_1 to SLd_w may or may not be substantially perpendicular in a top view.

[0124] When the drive circuit SD included in the local driver circuit LD corresponding to the pixel area ARA is not positioned in the column direction of the pixel area ARA when viewed from above, as shown in Figure 8A, the orientation of the drive circuit SD (the orientation of the arrangement of the multiple output terminals SDT) can be changed to an optimal direction, and the wiring SLd_1 to wiring SLd_w can be routed in a direction that is approximately perpendicular, preferably perpendicular, to the orientation of the arrangement of the multiple output terminals SDT, thereby making it possible to shorten as much as possible the length of the source wiring electrically connecting the pixel area ARA and the drive circuit SD.

[0125] Furthermore, the position of the contact portion CNT and the arrangement order of the wirings SLd_1 to SLd_w may be changed depending on the situation. For example, the configuration shown in FIG. 8A may be changed to the configuration shown in FIG. 8B. Specifically, the configuration shown in FIG. 8B changes the position of the contact portion CNT provided on each extension of the wirings SLu_1 to SLu_w and changes the arrangement order of the wirings SLd_1 to SLd_w compared to the configuration shown in FIG. 8A. By changing the configuration shown in FIG. 8A to the configuration shown in FIG. 8B, the difference between the longest wiring and the shortest wiring among the wirings SLd_1 to SLd_w can be minimized. In other words, the lengths of the wirings SLd_1 to SLd_w can be made closer to the average length of the wirings SLd_1 to SLd_w. This reduces the difference in length among the wirings SLd_1 to SLd_w, thereby suppressing variations in the transmission time of image data to each of the wirings SL_1 to SL_w.

[0126] 3B, 4B, or 5B may be used as cross-sectional views of the configurations shown in FIGS. 7 to 8B. In the case of FIG. 3B, the contact portion VA corresponds to, for example, the contact portion CNT in FIGS. 7 to 8B, and the conductor ER corresponds to, for example, any one of the wirings SLd_1 to SLd_w in FIGS. 7 to 8B. The conductor CD, the low-resistance region 314a of the transistor 300, and the region where the conductor CD and the low-resistance region 314a of the transistor 300 contact each other correspond to, for example, one of the output terminals SDT in FIGS. 7 to 8B. In the case of FIG. 5B, the contact portion VA and the conductor ER correspond to, for example, the contact portion CNT in FIGS. 7 to 8B. The conductor CD included in the circuit layer SICL may also be part of the contact portion CNT in FIGS. 7 to 8B. The low-resistance region 314c of the transistor 300 corresponds to, for example, any one of the wirings SLd_1 to SLd_w in FIGS. 7 to 8B. Moreover, the boundary between the low-resistance region 314a of the transistor 300 and a semiconductor region 313 (described later) corresponds to, for example, one of the plurality of output terminals SDT in FIGS. 7 to 8B.

[0127] In the above explanation using Figures 7 to 8B, the drive circuit SD, i.e., the source driver circuit, is used as an example, but by considering it in the same way as a gate driver circuit instead of a source driver circuit, for example, it is possible to reduce the time difference between each selection signal sent from the gate driver circuit to each wiring in the pixel area ARA.

[0128] 1, 2A, and 2B, the display device 10 can be configured such that the pixel array ALP of the display device 10 is divided into pixel regions ARA[1,1] to ARA[m,n], and each pixel region ARA can be driven in parallel by a local driver circuit LD[1,1] to a local driver circuit LD[m,n]. Furthermore, when rewriting a portion of an image on the display unit of the display device 10, only the necessary local driver circuit LD is driven to drive the pixels included in the pixel region ARA displaying that portion of the image. In other words, the pixels included in each of the pixel regions ARA[1,1] to ARA[m,n] of the display unit of the display device 10 can be driven independently. In this case, only the pixels included in the necessary pixel region ARA are driven, and the local driver circuits corresponding to the pixel regions ARA that do not need to be driven are put into a dormant state, thereby reducing power consumption. Furthermore, by dividing the pixel array ALP of the display device 10 into pixel regions ARA[1,1] to ARA[m,n], and driving each pixel region ARA in parallel and independently by the local driver circuits LD[1,1] to LD[m,n], the time required to rewrite an image displayed on the display unit of the display device 10 (e.g., the time per frame) can be shortened. Furthermore, by dividing the pixel array ALP and driving each pixel region ARA by a corresponding local driver circuit LD, the driving load on each divided unit (each pixel region ARA) is reduced, making it easier to increase the operating speed and reduce power consumption. Furthermore, by dividing the pixel array ALP, each divided unit (each pixel region ARA) can be driven at the same timing, making it possible to set a longer image writing time for each frame compared to when the pixel array ALP is not divided. For example, by dividing the pixel array ALP so that the multiple gate wirings extending to the pixel array ALP are divided into four, the image writing time can ideally be set to 1 / 4 of the time required when the pixel array ALP is not divided, or approximately that time, and the remaining time (3 / 4 of the time required when the pixel array ALP is not divided, or approximately that time) can be used for writing time.Therefore, the image writing time within one frame can be extended.

[0129] 1, 2A, and 2B, by arranging the local driver circuit LD at or near the center of the circuit layer SICL, when an image is displayed on the display unit of the display device 10, it is possible to reduce the difference in time required for input of image data signals given to each pixel in different pixel areas ARA. Similarly, it is possible to reduce the difference in time required for input of signals in different pixel areas ARA, not only for data signals but also for pixel selection signals transmitted to the pixel areas ARA. In other words, it is possible to suppress delays in signals transmitted from the drive circuit area to each pixel area ARA.

[0130] Note that the display device according to one embodiment of the present invention is not limited to the above-described configuration of the display device 10. The display device according to one embodiment of the present invention may have a modified configuration of the above-described display device 10 depending on the situation.

[0131] For example, the display device 10 described above has been described as including one drive circuit region DRV in the circuit layer SICL, but the circuit layer SICL may include two or more drive circuit regions DRV. The display device 10 in Fig. 9A is a schematic top view illustrating an example configuration in which the circuit layer SICL of the display device 10 includes two or more drive circuit regions DRV.

[0132] The display device 10 of Fig. 9A is configured such that a driving circuit region DRV is provided in a portion of the overlapping region of pixel regions ARA that are contained within a range of 2 rows and n columns of the pixel array ALP. Specifically, in the display device 10 of Fig. 9A, a driving circuit region DRV[1] is provided in a portion of the overlapping region ranging from pixel region ARA[1,1] to pixel region ARA[2,n], and a driving circuit region DRV[n / 2] is provided in a portion of the overlapping region ranging from pixel region ARA[m-1,1] to pixel region ARA[m,n]. In other words, n / 2 driving circuit regions DRV (driving circuit regions DRV[1] to drive circuit region [n / 2]) are provided in the circuit layer SICL. Note that the number of columns n shown in Fig. 9A is an even number.

[0133] 9A illustrates the pixel regions ARA[1,1], ARA[2,1], ARA[m-1,1], ARA[m,1], ARA[1,n], ARA[2,n], ARA[m-1,n], and ARA[m,n] as the pixel regions ARA. Also, FIG. 9A illustrates the drive circuit regions DRV[1] and DRV[n / 2] as the drive circuit regions DRV. 9A excerpts the local driver circuits LD from the local driver circuit LD[1,1], the local driver circuit LD[2,1], the local driver circuit LD[1,2], the local driver circuit LD[2,2], the local driver circuit LD[m-1,1], the local driver circuit LD[m,1], the local driver circuit LD[m-1,2], the local driver circuit LD[m,2], the local driver circuit LD[1,n-1], the local driver circuit LD[2,n-1], the local driver circuit LD[1,n], the local driver circuit LD[2,n], the local driver circuit LD[m-1,n-1], the local driver circuit LD[m,n-1], the local driver circuit LD[m-1,n], and the local driver circuit LD[m,n].

[0134] In addition, in the display device 10 of Figure 9A, a controller CON and a voltage generation circuit PG are illustrated in the center of each of the drive circuit areas DRV[1] to DRV[n / 2], but the positions and shapes of the controller CON and voltage generation circuit PG provided in the drive circuit areas DRV[1] to DRV[n / 2] are not particularly limited.

[0135] 9A is configured such that the pixels included in each of a plurality of pixel regions ARA contained in a range of 2 rows and n columns of the pixel array ALP are driven by a local driver circuit LD included in one drive circuit region DRV, but the range of the pixel region in the pixel array ALP corresponding to one drive circuit region DRV may be a range of 1 to m rows and n columns, or a range of m rows and 1 to n columns. Specifically, the range of the pixel region in the pixel array ALP corresponding to one drive circuit region DRV may be, for example, a range of 3 rows and n columns, or a range of m rows and 2 columns.

[0136] 9A, n, which indicates the number of columns, is an even number, but n may be an odd number. In this case, the configuration of the display device 10 in Fig. 9A may be, for example, such that the entire pixel array ALP is divided into a plurality of ranges of 2 rows and n columns and one range of 1 row and n columns, and a plurality of drive circuit regions DRV are provided so that one drive circuit region DRV corresponds to each range.

[0137] 9A is configured to drive the pixels included in each of a plurality of pixel regions ARA contained in a range of 2 rows and n columns of the pixel array ALP by a local driver circuit LD included in one drive circuit region DRV, but the range of the pixel region in the pixel array ALP corresponding to one drive circuit region DRV may be a range of 1 to m rows and 1 to n columns. Specifically, for example, as shown in FIG. 9B, one range may be divided into 2 rows i aAs a column, pixels in a plurality of pixel areas ARA included in one range may be driven by one driving circuit area DRV. a Each of n=i a ×p, m is an integer of 1 or more that satisfies 2×q. In this case, p×q driving circuit regions DRV (driving circuit regions DRV[1] to [p×q]) are provided in the circuit layer SICL.

[0138] In FIG. 9B, the pixel area ARA includes a pixel area ARA[1,1], a pixel area ARA[2,1], a pixel area ARA[m-1,1], a pixel area ARA[m,1], and a pixel area ARA[1,i a ] and pixel area ARA[2,i a ] and pixel area ARA[m-1,i a ] and pixel area ARA[m,i a ] and pixel area ARA[1,ni a +1] and pixel area ARA[2,ni a +1] and pixel area ARA[m-1,ni a +1] and pixel area ARA[m,ni a 9B excerpts the pixel regions ARA[1,n], ARA[2,n], ARA[m-1,n], and ARA[m,n] from the drive circuit region DRV, and excerpts the pixel regions ARA[1], DRV[p], DRV[p×q-p+1], and DRV[p×q] from the drive circuit region DRV. 9B excerpts the local driver circuit LD[1,1], LD[2,1], LD[m-1,1], LD[m,1], and LD[1,i a ] and the local driver circuit LD[2,i a ] and local driver circuit LD[m-1,i a ] and local driver circuit LD[m,i a ] and the local driver circuit LD[1,ni a +1] and the local driver circuit LD[2,nia +1] and local driver circuit LD[m-1,ni a +1] and the local driver circuit LD[m,ni a 10 shows an excerpt of local driver circuits LD[1,n], LD[2,n], LD[m-1,n], and LD[m,n].

[0139] 9B, the drive circuit regions DRV[1] to DRV[p×q] do not include a controller CON and a voltage generating circuit PG, but the drive circuit regions DRV[1] to DRV[p×q] may include a controller CON and a voltage generating circuit PG. The positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit regions DRV[1] to DRV[p×q] are not particularly limited.

[0140] 2B, 9A, 9B, and the like, the display device 10 is configured such that the drive circuit region DRV does not overlap the edge of the region including all of the pixel regions ARA[1,1] to ARA[m,n] of the pixel array ALP. However, a configuration in which a portion of the drive circuit region DRV overlaps a portion of the edge of the pixel array ALP may also be used. Specifically, for example, as shown in FIG. 10A, the display device 10 may be configured such that, in a top view, one drive circuit region DRV crosses the pixel array ALP in the column direction. Therefore, a portion of the edge of the region including all of the pixel regions ARA[1,1] to ARA[m,n] of the pixel array ALP overlaps the drive circuit region DRV (this also includes the case in which a portion of the edge of the pixel array ALP overlaps a portion of the edge of the drive circuit region DRV, as shown in FIG. 10A).

[0141] In this case, local driver circuits LD[1,1] to LD[m,n] are arranged in a matrix of m rows and n columns in the drive circuit region DRV, similar to the drive circuit region DRV shown in FIG. 2B.

[0142] In addition, in Figure 10A, the pixel area ARA is illustrated by selecting pixel area ARA[1,1], pixel area ARA[2,1], pixel area ARA[m-1,1], pixel area ARA[m,1], pixel area ARA[1,2], pixel area ARA[2,2], pixel area ARA[m-1,2], pixel area ARA[m,2], pixel area ARA[1,n-1], pixel area ARA[2,n-1], pixel area ARA[m-1,n-1], pixel area ARA[m,n-1], pixel area ARA[1,n], pixel area ARA[2,n], pixel area ARA[m-1,n], and pixel area ARA[m,n]. 10A excerpts the local driver circuits LD from the local driver circuit LD[1,1], the local driver circuit LD[2,1], the local driver circuit LD[m-1,1], the local driver circuit LD[m,1], the local driver circuit LD[1,2], the local driver circuit LD[2,2], the local driver circuit LD[m-1,2], the local driver circuit LD[m,2], the local driver circuit LD[1,n-1], the local driver circuit LD[2,n-1], the local driver circuit LD[m-1,n-1], the local driver circuit LD[m,n-1], the local driver circuit LD[1,n], the local driver circuit LD[2,n], the local driver circuit LD[m-1,n], and the local driver circuit LD[m,n].

[0143] Furthermore, in the display device 10 of Figure 10A, the controller CON and the voltage generating circuit PG are illustrated in the central part of the drive circuit region DRV, but the positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit region DRV are not particularly limited.

[0144] 10A is configured such that one drive circuit region DRV is provided across the pixel array ALP, the display device 10 may also be configured such that multiple drive circuit regions DRV are provided across the pixel array ALP. Specifically, for example, as shown in FIG. 10B, one range may be divided into m rows i bAs a column, pixels in a plurality of pixel areas ARA included in one range may be driven by one drive circuit area DRV. b Each of n=i b ×r is an integer equal to or greater than 1. In this case, the circuit layer SICL is provided with r driving circuit regions DRV (driving circuit regions DRV[1] to [r]).

[0145] In FIG. 10B, the pixel area ARA includes a pixel area ARA[1,1], a pixel area ARA[2,1], a pixel area ARA[m-1,1], a pixel area ARA[m,1], and a pixel area ARA[1,i b ] and pixel area ARA[2,i b ] and pixel area ARA[m-1,i b ] and pixel area ARA[m,i b ] and pixel area ARA[1,ni b +1] and pixel area ARA[2,ni b +1] and pixel area ARA[m-1,ni b +1] and pixel area ARA[m,ni b 10B excerpts the pixel regions ARA[1,n], ARA[2,n], ARA[m-1,n], and ARA[m,n]. Also, in FIG. 10B, the drive circuit regions DRV[1] and DRV[r] are excerpted as the drive circuit regions DRV. Also, in FIG. 10B, the local driver circuits LD[1,1], LD[2,1], LD[m-1,1], LD[m,1], and LD[1,i b ] and the local driver circuit LD[2,i b ] and local driver circuit LD[m-1,i b ] and local driver circuit LD[m,i b ] and the local driver circuit LD[1,ni b +1] and the local driver circuit LD[2,ni b +1] and local driver circuit LD[m-1,ni b+1] and the local driver circuit LD[m,ni b 10 shows an excerpt of local driver circuits LD[1,n], LD[2,n], LD[m-1,n], and LD[m,n].

[0146] 10B, the drive circuit regions DRV[1] to DRV[r] do not include a controller CON and a voltage generating circuit PG, but the drive circuit regions DRV[1] to DRV[r] may include a controller CON and a voltage generating circuit PG. The positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit regions DRV[1] to DRV[r] are not particularly limited.

[0147] The display device 10 in FIG. 10B includes the pixel array ALP in the mth row i b Although the display device 10 is configured such that the pixels included in each of the plurality of pixel regions ARA contained within the range of a column are driven by a local driver circuit LD included in one drive circuit region DRV, the ranges of pixel regions in the pixel array ALP corresponding to each of the plurality of drive circuit regions DRV may include different ranges. For example, when the number n of columns of the pixel array is odd, the display device 10 may be configured such that the entire pixel array ALP is divided into a plurality of ranges of m rows and 2 columns and one range of m rows and 1 column, and multiple drive circuit regions DRV are provided so that one drive circuit region DRV corresponds to each range.

[0148] 10A shows a configuration in which both opposing ends of the pixel array ALP overlap a portion of an end of the drive circuit region DRV, but a configuration in which one of the opposing ends of the pixel array ALP overlaps a portion of an end of the drive circuit region DRV may also be used. Specifically, for example, as shown in FIG. 11, a configuration in which one of the opposing ends of the pixel array ALP overlaps a portion of an end of one drive circuit region DRV may also be used.

[0149] Furthermore, a display device according to one embodiment of the present invention may be a combination of the above-described exemplary configurations of the display device 10. As an example, the exemplary configuration of the display device 10 in FIG. 2B may be combined with the exemplary configuration of the display device 10 in FIG. 11, as in the display device 10 in FIG. 12. The display device 10 in FIG. 12 is configured such that, in a top view, the circuit layer SICL has a driving circuit region DRVa overlapping one of the opposing ends of the pixel array ALP, and a driving circuit region DRVb overlapping a partial region inside the pixel array ALP. Specifically, in the display device 10 in FIG. 12, the driving circuit region DRVa overlaps the pixel regions ARA[1,1] to ARA[i c , n], and the driving circuit region DRVb drives the pixels in the pixel region ARA[i c +1,1] to the pixel area ARA[m,n] are driven. c can be an integer between 1 and m-1 inclusive.

[0150] In FIG. 12, the pixel area ARA includes a pixel area ARA[1,1], a pixel area ARA[2,1], and a pixel area ARA[i c ,1] and pixel area ARA[i c +1,1], pixel area ARA[m,1], pixel area ARA[1,2], pixel area ARA[2,2], and pixel area ARA[i c , 2], pixel area ARA[1, n-1], pixel area ARA[2, n-1], pixel area ARA[i c ,n-1], pixel area ARA[1,n], pixel area ARA[2,n], and pixel area ARA[i c ,n] and pixel area ARA[i c 10B, the local driver circuits LD are selected from the local driver circuit LD[1,1], the local driver circuit LD[2,1], and the local driver circuit LD[i c ,1], local driver circuit LD[1,2], local driver circuit LD[2,2], and local driver circuit LD[i c,2], local driver circuit LD[1,n-1], local driver circuit LD[2,n-1], and local driver circuit LD[i c ,n-1], local driver circuit LD[1,n], local driver circuit LD[2,n], and local driver circuit LD[i c ,n] and local driver circuit LD[i c +1,1] and the local driver circuit LD[i c +1,2], local driver circuit LD[m,1], local driver circuit LD[m,2], and local driver circuit LD[i c +1,n-1] and local driver circuit LD[i c 10, the local driver circuit LD[m-1,n], the local driver circuit LD[m,n], and the local driver circuit LD[m-1,n] are selectively illustrated.

[0151] 12, the drive circuit region DRVa and the drive circuit region DRVb may each have a controller CON and a voltage generating circuit PG, similar to the display device 10 of Fig. 2B. Furthermore, the positions and shapes of the controller CON and the voltage generating circuit PG provided in the drive circuit region DRVa and the drive circuit region DRVb are not particularly limited.

[0152] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0153] (Embodiment 2) In this embodiment, a structural example of a display device according to one embodiment of the present invention and an example of an operation method of the display device will be described.

[0154] <Display device configuration example 1> 13 illustrates a configuration example of a display device according to one embodiment of the present invention. For example, the display device 11 illustrated in FIG. 13 includes a pixel array ALP, as well as a driver circuit GD, driver circuits SDa[1] to SDa[h] (where h is an integer equal to or greater than 1), and driver circuits SDb[1] to SDb[h].

[0155] As an example, the drive circuit GD functions as a gate driver circuit that selects pixel circuits included in the pixel array ALP to which image data is to be written.

[0156] The drive circuits SDa[1] to SDa[h] and the drive circuits SDb[1] to SDb[h] function as source driver circuits that transmit image data to the pixel circuits included in the pixel array ALP, for example. Note that the drive circuits SDa[1] to SDa[h] and the drive circuits SDb[1] to SDb[h] may further include a demultiplexer (DeMUX) for selecting a source line to transmit image data.

[0157] As an example, the pixel array ALP has a plurality of pixel circuits, which are arranged in a matrix of V1+V2 rows and W columns (V1 is an integer greater than or equal to 1, V2 is an integer greater than or equal to 1, and W is a multiple of h greater than or equal to 1). Specifically, a plurality of pixel circuits PIXa are provided in the first to V1 rows of the pixel array ALP, and a plurality of pixel circuits PIXb are provided in the V1+1th to V1+V2th rows of the pixel array ALP. Note that in FIG. 13, for convenience, the plurality of pixel circuits arranged in the first to V1th rows of the pixel array ALP are referred to as pixel circuits PIXa[1,1] to PIXa[V1,W], and the plurality of pixel circuits arranged in the V1+1th to V1+V2th rows of the pixel array ALP are referred to as pixel circuits PIXb[1,1] to PIXb[V2,W]. Furthermore, the plurality of pixel circuits PIXa and the plurality of pixel circuits PIXb can have the same configuration.

[0158] It should be noted that the pixel array ALP in FIG. 13 excerpts pixel circuit PIXa[1,1], pixel circuit PIXa[1,W / h], pixel circuit PIXa[V1,1], pixel circuit PIXa[V1,W / h], pixel circuit PIXa[1,WW / h+1], pixel circuit PIXa[1,W], pixel circuit PIXa[V1,WW / h+1], pixel circuit PIXa[V1,W], pixel circuit PIXb[1,1], pixel circuit PIXb[1,W / h], pixel circuit PIXb[V2,1], pixel circuit PIXb[V2,W / h], pixel circuit PIXb[1,WW / h+1], pixel circuit PIXb[1,W], pixel circuit PIXb[V2,WW / h+1], and pixel circuit PIXb[V2,W].

[0159] Also, consider a configuration in which the pixel array ALP is divided and image signals are written to each divided region. Fig. 13 shows an example of the configuration of a display device in which the pixel array ALP is divided into 2 × h regions, namely, regions ALPa_C[1] to ALPa_C[h] and regions ALPb_C[1] to ALPb_C[h]. Note that the regions ALPa_C[1] to ALPa_C[h] are configured by dividing a matrix in which pixel circuits PIXa[1,1] to PIXa[V1,W] are arranged into W / h columns, and the regions ALPb_C[1] to ALPb_C[h] are configured by dividing a matrix in which pixel circuits PIXb[1,1] to PIXb[V2,W] are arranged into W / h columns. Therefore, each of the areas ALPa_C[1] to ALPa_C[h] is configured so that a plurality of pixel circuits PIXa are arranged in a matrix of V1 rows and W / h columns, and each of the areas ALPb_C[1] to ALPb_C[h] is configured so that a plurality of pixel circuits PIXb are arranged in a matrix of V2 rows and W / h columns.

[0160] In the region ALPa_C[1], wirings SLa[1] to SLa[W / h] extend for each column, and each of the wirings SLa[1] to SLa[W / h] is electrically connected to a plurality of pixel circuits PIXa arranged in each column of the region ALPa_C[1]. Similarly, in the region ALPb_C[1], wirings SLb[1] to SLb[W / h] extend for each column, and each of the wirings SLb[1] to SLb[W / h] is electrically connected to a plurality of pixel circuits PIXb arranged in each column of the region ALPb_C[1]. Therefore, for example, the wirings SLa[1] and SLb[1] extend to the same column in the pixel array ALP, and the wirings SLa[W / h] and SLb[W / h] extend to the same column in the pixel array ALP.

[0161] Each of the wirings SLa[1] to SLa[W / h] is electrically connected to the driver circuit SDa[1], and each of the wirings SLb[1] to SLb[W / h] is electrically connected to the driver circuit SDb[1].

[0162] Furthermore, in the region ALPa_C[h], wirings SLa[WW / h+1] to SLa[W] extend for each column, and each of the wirings SLa[WW / h+1] to SLa[W] is electrically connected to a plurality of pixel circuits PIXa arranged in each column of the region ALPa_C[h]. Similarly, in the region ALPb_C[h], wirings SLb[WW / h+1] to SLb[W] extend for each column, and each of the wirings SLb[WW / h+1] to SLb[W] is electrically connected to a plurality of pixel circuits PIXb arranged in each column of the region ALPb_C[h]. Therefore, for example, the wiring SLa[WW / h+1] and the wiring SLb[WW / h+1] are each extended to the same column in the pixel array ALP, and also, for example, the wiring SLa[W] and the wiring SLb[W] are each extended to the same column in the pixel array ALP.

[0163] Each of the wirings SLa[WW / h+1] to SLa[W] is electrically connected to the driver circuit SDa[h], and each of the wirings SLb[WW / h+1] to SLb[W] is electrically connected to the driver circuit SDb[h].

[0164] 13, wirings are also assumed to be provided for each column in the regions ALPa_C[2] to ALPa_C[h-1] and the regions ALPb_C[2] to ALPb_C[h-1]. One of the wirings in the regions ALPa_C[2] to ALPa_C[h-1] is electrically connected to one of the driver circuits SDa[2] to SDa[h-1] according to the divided region, and similarly, one of the wirings in the regions ALPb_C[2] to ALPb_C[h-1] is electrically connected to one of the driver circuits SDb[2] to SDb[h-1] according to the divided region.

[0165] <Example of a display device driving method> Here, an example of a method for driving the display device 11 shown in FIG. 13 will be described.

[0166] The display device 11A shown in Fig. 14 is a block diagram showing a part of the pixel array ALP of the display device 11 of Fig. 13, and shows an excerpt of the area ALPa_C[1], the area ALPb_C[1], the drive circuit SDa[1], and the drive circuit SDb[1]. Note that, in the display device 11A shown in Fig. 14, W / h is set to 4, as an example. That is, in the display device 11A shown in Fig. 14, pixel circuits PIXa are arranged in a matrix of V1 rows and 4 columns in the area ALPa_C[1], and pixel circuits PIXb are arranged in a matrix of V2 rows and 4 columns in the area ALPb_C[1].

[0167] In addition, each of the drive circuit SDa[1] and drive circuit SDb[1] provided in the display device 11A of Figure 14 has the function of selecting one of the four source wirings (corresponding to wirings SLa[1] to SLa[W / h] or wirings SLb[1] to SLb[W / h] in the display device 11 of Figure 13) and transmitting an image signal to that one source wiring.

[0168] 14 shows specific configuration examples of the drive circuit SDa[1] and the drive circuit SDb[1]. As an example, the drive circuit SDa[1] has a demultiplexer DMUa and a circuit OTH, and the drive circuit SDb[1] has a demultiplexer DMUb and a circuit OTH.

[0169] The demultiplexer DMUa includes, for example, switches SWa[1] to SWa[4], and the demultiplexer DMUb includes, for example, switches SWb[1] to SWb[4].

[0170] In addition, a first terminal of the switch SWa[1] is electrically connected to the wiring SLa[1], a second terminal of the switch SWa[1] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[1] is electrically connected to the wiring SGa[1]. A first terminal of the switch SWa[2] is electrically connected to the wiring SLa[2], a second terminal of the switch SWa[2] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[2] is electrically connected to the wiring SGa[2]. A first terminal of the switch SWa[3] is electrically connected to the wiring SLa[3], a second terminal of the switch SWa[3] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[3] is electrically connected to the wiring SGa[3]. A first terminal of the switch SWa[4] is electrically connected to the wiring SLa[4], a second terminal of the switch SWa[4] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[4] is electrically connected to the wiring SGa[4].

[0171] An input terminal of a circuit OTH included in the driver circuit SDa is electrically connected to a wiring DLa.

[0172] A first terminal of the switch SWb[1] is electrically connected to the wiring SLb[1], a second terminal of the switch SWb[1] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[1] is electrically connected to the wiring SGb[1]. A first terminal of the switch SWb[2] is electrically connected to the wiring SLb[2], a second terminal of the switch SWb[2] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[2] is electrically connected to the wiring SGb[2]. A first terminal of the switch SWb[3] is electrically connected to the wiring SLb[3], a second terminal of the switch SWb[3] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[3] is electrically connected to the wiring SGb[3]. A first terminal of the switch SWb[4] is electrically connected to the wiring SLb[4], a second terminal of the switch SWb[4] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[4] is electrically connected to the wiring SGb[4].

[0173] An input terminal of a circuit OTH included in the driver circuit SDb is electrically connected to a wiring DLb.

[0174] The switches SWa[1] to SWa[4] and the switches SWb[1] to SWb[4] may each be an electrical switch such as an analog switch or a transistor. Alternatively, the switches SWa[1] to SWa[4] and the switches SWb[1] to SWb[4] may each be a mechanical switch. Note that when the switches SWa[1] to SWa[4] and the switches SWb[1] to SWb[4] include transistors, the transistors may be, for example, OS transistors or transistors including Si in their channel formation regions.

[0175] In this embodiment, each of the switches SWa[1] to SWa[4] and the switches SWb[1] to SWb[4] is turned on when a high-level potential is input to the control terminal, and turned off when a low-level potential is input.

[0176] For example, the wirings SGa[1] to SGa[4] and the wirings SGb[1] to SGb[4] each function as a wiring that supplies a voltage for switching between a conductive state and a non-conductive state of a switch whose control terminal is electrically connected to the wiring. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0177] Therefore, for example, the demultiplexer DMUa can apply a high-level pulse voltage to any one of the wirings SGa[1] to SGa[4] to turn on the switch having the control terminal to which the pulse voltage is applied for only the time the pulse voltage is applied. Also, for example, the demultiplexer DMUa can sequentially turn on each of the switches SWa[1] to SWa[4] by sequentially applying a high-level pulse voltage to each of the wirings SGa[1] to SGa[4]. This allows the demultiplexer DMU to sequentially select the wirings SLa[1] to SLa[4] to which the image data is to be sent.

[0178] The circuit OTH included in each of the demultiplexers DMUa and DMUb may be, for example, a circuit including an amplifier (which may be a circuit having a pass transistor), a digital-to-analog conversion circuit (DAC), a latch circuit, etc.

[0179] For example, the circuit OTH can have the function of temporarily holding a potential (which may be a digital value) indicating image data sent from the wiring DLa (or wiring DLb) using a latch circuit, the function of converting the image data into an analog voltage using a digital-to-analog conversion circuit if the image data is a digital value, and the function of amplifying the analog voltage using an amplifier and supplying it to the demultiplexer DMU.

[0180] Therefore, the circuit OTH included in the driving circuit SDa converts the image data sent from the wiring DLa into an appropriate potential and outputs it to the output terminal of the circuit OTH. The potential output from the output terminal of the circuit OTH is supplied to the wiring (wiring SLa[1] to wiring SLa[4]) selected by the demultiplexer DMUa. Similarly, the circuit OTH included in the driving circuit SDb converts the image data sent from the wiring DLb into an appropriate potential and outputs it to the output terminal of the circuit OTH. The potential output from the output terminal of the circuit OTH is supplied to the wiring (wiring SLb[1] to wiring SLb[4]) selected by the demultiplexer DMUb.

[0181] 14, by providing a demultiplexer in each of the drive circuit SDa[1] and the drive circuit SDb[1], the number of circuits OTH can be reduced in each of the drive circuit SDa[1] and the drive circuit SDb[1]. In other words, the area of ​​each of the drive circuit SDa[1] and the drive circuit SDb[1] can be reduced.

[0182] The circuit configurations of the demultiplexer DMU and the circuit OTH described above are merely examples, and these circuit configurations may be changed as appropriate depending on the configuration of the display device 11A.

[0183] As a modification of the display device 11A, the number of source lines (lines SLa and SLb) that can be selected by each of the drive circuits SDa[1] and SDb[1] may be changed depending on the operating speed of the circuit OTH. The operating speed of the circuit OTH is determined, for example, by the driving frequency of the transistors included in the circuit OTH. By using transistors with a high driving frequency in the circuit OTH, the operating speed of the circuit OTH can be increased, thereby accelerating the processing and output of image data in the circuit OTH. In FIG. 14, the demultiplexers DMUa and DMUb each have four output terminals. However, the number of output terminals of the demultiplexers DMUa and DMUb may be changed depending on the operating speed of the circuit OTH. For example, if the operating speed of the circuit OTH is fast, the processing and output of image data by the circuit OTH can be accelerated, thereby shortening the time required for writing image data per column in the area ALPa_C[1] (area ALPb_C[1]). Furthermore, by shortening the image data write operation per column, the time required to write image data to the pixel circuits of one row in the region ALPa_C[1] (region ALPb_C[1]) can be shortened, and the number of image data write operations for the column can be increased by the shortened time. In other words, by shortening the image data write operation per column, the number of output terminals of each demultiplexer DMUa (demultiplexer DMUb) can be increased to five or more. Alternatively, for example, if the operating speed of the circuit OTH is slow, the number of output terminals of each demultiplexer DMUa and demultiplexer DMUb may be reduced to two, three, or the like. In other words, the number of source lines (lines SLa and SLb) that can be selected by each of the drive circuits SDa[1] and SDb[1] may be changed depending on the operating speed of the circuit OTH.

[0184] Fig. 15 is a timing chart showing an example of the operation of the display device 11A shown in Fig. 14. Specifically, the timing chart in Fig. 15 shows changes in the potentials of the lines GLa[1] to GLa[3], the lines SGa[1] to SGa[4], the lines GLb[1] to GLb[3], and the lines SGb[1] to SGb[4] from time T01 to time T17 and the surrounding times (note that in Fig. 15, "High" indicates a high-level potential, and "Low" indicates a low-level potential). The timing chart in Fig. 15 also shows image data transmitted to the lines DLa, DLb, the lines SLa[1] to SLa[4], and the lines SLb[1] to SLb[4] from time T01 to time T17 and the surrounding times.

[0185] [From time T01 to time T17 (first period)] Between time T01 and time T17, for example, image data to be written to pixel circuits PIXa included in pixel array ALP of the display device 11A is sequentially transmitted from line DLa to drive circuit SDa. Similarly, image data to be written to pixel circuits PIXb included in pixel array ALP of the display device 11A is transmitted from line DLb to drive circuit SDb.

[0186] Specifically, between time T01 and time T17, image data to be transmitted to area ALPa_C[1] and area ALPb_C[1], respectively, of the pixel array ALP of the display device 11A is alternately provided to the wiring DLa and the wiring DLb for each period.

[0187] For example, if each of the image data transmitted to the area ALPa_C[1] of the pixel array ALP is data Da, in the timing chart of Figure 15, the data Da is provided to the wiring DLa between time T01 and time T02, between time T03 and time T04, between time T05 and time T06, between time T07 and time T08, between time T09 and time T10, between time T11 and time T12, between time T13 and time T14, and between time T15 and time T16. Furthermore, for example, when each of the image data transmitted to the area ALPb_C[1] of the pixel array ALP is data Db, in the timing chart of FIG. 15, the data Db is provided to the wiring DLb between time T02 and time T03, between time T04 and time T05, between time T06 and time T07, between time T08 and time T09, between time T10 and time T11, between time T12 and time T13, between time T14 and time T15, and between time T16 and time T17.

[0188] In this case, it is preferable to use a one-input, two-output selector for inputting image data to the wiring DLa and wiring DLb. Specifically, for example, in a configuration in which the wiring DLa is electrically connected to one output terminal of a one-input, two-output selector and the wiring DLb is electrically connected to the other output terminal of the selector, when data Da and data Db are alternately input as image data to the input terminal of the selector, the output of the selector can be switched according to the input data.

[0189] Also, in the timing chart of Figure 15, data Da[1,1] is input to wiring DLa from time T01 to time T02, data Da[1,2] from time T03 to time T04, data Da[1,3] from time T05 to time T06, data Da[1,4] from time T07 to time T08, data Da[2,1] from time T09 to time T10, data Da[2,2] from time T11 to time T12, data Da[2,3] from time T13 to time T14, and data Da[2,4] from time T15 to time T16. Also, in the timing chart of Figure 15, data Db[1,1] is input to wiring DLb from time T02 to time T03, data Db[1,2] from time T04 to time T05, data Db[1,3] from time T06 to time T07, data Db[1,4] from time T08 to time T09, data Db[2,1] from time T10 to time T11, data Db[2,2] from time T12 to time T13, data Db[2,3] from time T14 to time T15, and data Db[2,4] from time T16 to time T17.

[0190] Note that [x, y] attached to data Da indicates the address of pixel circuit PIXa included in area ALPa_C[1] of pixel array ALP, to which data Da is written. Similarly, [x, y] attached to data Db indicates the address of pixel circuit PIXb included in area ALPb_C[1] of pixel array ALP, to which data Db is written.

[0191] In the drive circuit SDa, data Da provided to the wiring DLa is input to the circuit OTH. For example, the circuit OTH latches the input data Da and outputs the data Da to the output terminal of the circuit OTH. Note that the latching period can be, for example, the period from when the data Da is input to the wiring DLa until data Da to be written to a different pixel circuit is input to the wiring DLa. Similarly, in the drive circuit SDb, data Db provided to the wiring DLb is input to the circuit OTH. For example, the circuit OTH latches the input data Db and outputs the data Db to the output terminal of the circuit OTH. Note that the latching period can be, for example, the period from when the data Db is input to the wiring DLb until data Db to be written to a different pixel circuit is input to the wiring DLb.

[0192] Note that the circuits OTH included in each of the driver circuits SDa and SDb may have a function of performing processing such as digital-to-analog conversion on input data Da.

[0193] [From time T01 to time T09 (second period)] Between time T01 and time T09, for example, a high-level potential is input to the wiring GLa[1]. As a result, a high-level potential is applied from the wiring GLa[1] to the pixel circuits PIXa[1,1] to PIXa[1,4] arranged in the first row of the region ALPa_C[1] of the display device 11A. As a result, the pixel circuit PIXa[1,1] and the wiring SLa[1] are brought into a conductive state, the pixel circuit PIXa[1,2] and the wiring SLa[2] are brought into a conductive state, the pixel circuit PIXa[1,3] and the wiring SLa[3] are brought into a conductive state, and the pixel circuit PIXa[1,4] and the wiring SLa[4] are brought into a conductive state.

[0194] Furthermore, between time T01 and time T09, for example, a low-level potential is input to each of the wirings GLa[2] to GLa[V1], whereby the low-level potentials from the wirings GLa[2] to GLa[V1] are applied to the pixel circuits PIXa[2,1] to PIXa[V1,4] arranged in the second to V1 rows of the region ALPa_C[1] of the display device 11A. As a result, there is a non-conductive state between the pixel circuits PIXa[2,1] to PIXa[V1,1] located in the first column and the wiring SLa[1], there is a non-conductive state between the pixel circuits PIXa[2,2] to PIXa[V1,2] located in the second column and the wiring SLa[2], there is a non-conductive state between the pixel circuits PIXa[2,3] to PIXa[V1,3] located in the third column and the wiring SLa[3], and there is a non-conductive state between the pixel circuits PIXa[2,4] to PIXa[V1,4] located in the fourth column and the wiring SLa[4].

[0195] In other words, a high-level potential is applied to wiring GLa[1] and a low-level potential is applied to wiring GLa[2] to wiring GLa[V1], resulting in the selection of pixel circuits PIXa[1,1] to PIXa[1,4] to which image data is written.

[0196] [From time T01 to time T03 (third period)] Between time T01 and time T03, for example, a high-level potential is input to the line SGa[1]. As a result, a high-level potential is applied to the control terminal of the switch SWa[1] of the demultiplexer DMUa of the display device 11A, and the switch SWa[1] is turned on. As a result, a conductive state is established between the line SLa[1] and the output terminal of the circuit OTH.

[0197] Also, between time T01 and time T03, for example, a low-level potential is input to the wirings SGa[2] to SGa[4]. As a result, a low-level potential is applied to each control terminal of the switches SWa[2] to SWa[4] of the demultiplexer DMUa of the display device 11A, and each of the switches SWa[2] to SWa[4] is turned off. As a result, there is no conduction between each of the wirings SLa[2] to SLa[4] and the output terminal of the circuit OTH.

[0198] Furthermore, between time T01 and time T03, for example, data Da[1,1] is input as image data from the wiring DLa to the circuit OTH. The data Da[1,1] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Da[1,1] output from the output terminal of the circuit OTH is sent to the wiring SLa[1] via the switch SWa[1], which is in the on state. At this time, the pixel circuit PIXa[1,1] in the first column of the area ALPa_C is selected as the data write destination (because a high-level potential is input to the wiring GLa[1]), so the data Da[1,1] is written to the pixel circuit PIXa[1,1].

[0199] [From time T03 to time T05 (fourth period)] Between time T03 and time T05, for example, a high-level potential is input to the line SGa[2]. As a result, a high-level potential is applied to the control terminal of the switch SWa[2] of the demultiplexer DMUa of the display device 11A, and the switch SWa[2] is turned on. As a result, a conductive state is established between the line SLa[2] and the output terminal of the circuit OTH.

[0200] Also, between time T03 and time T05, for example, a low-level potential is input to the wiring SGa[1], the wiring SGa[3], and the wiring SGa[4]. As a result, a low-level potential is applied to the control terminals of the switches SWa[1], SWa[3], and SWa[4] of the demultiplexer DMUa of the display device 11A, and the switches SWa[1], SWa[3], and SWa[4] are turned off. As a result, there is no conduction between the wiring SLa[1], the wiring SLa[3], and the wiring SLa[4] and the output terminal of the circuit OTH.

[0201] Furthermore, between time T03 and time T05, as an example, data Da[1,2] is input as image data from the wiring DLa to the circuit OTH. The data Da[1,2] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Da[1,2] output from the output terminal of the circuit OTH is sent to the wiring SLa[2] via the switch SWa[2], which is in the on state. At this time, the pixel circuit PIXa[1,2] in the second column of the area ALPa_C is selected as the data write destination (because a high-level potential is input to the wiring GLa[1]), so the data Da[1,2] is written to the pixel circuit PIXa[1,2].

[0202] [From time T05 to time T07 (5th period)] Between time T05 and time T07, for example, a high-level potential is input to the line SGa[3]. As a result, a high-level potential is applied to the control terminal of the switch SWa[3] of the demultiplexer DMUa of the display device 11A, and the switch SWa[3] is turned on. As a result, a conductive state is established between the line SLa[3] and the output terminal of the circuit OTH.

[0203] Also, between time T05 and time T07, for example, a low-level potential is input to the wiring SGa[1], the wiring SGa[2], and the wiring SGa[4]. As a result, a low-level potential is applied to the control terminals of the switches SWa[1], SWa[2], and SWa[4] of the demultiplexer DMUa of the display device 11A, and the switches SWa[1], SWa[2], and SWa[4] are each turned off. As a result, there is no conduction between the wiring SLa[1], the wiring SLa[2], and the wiring SLa[4] and the output terminal of the circuit OTH.

[0204] Furthermore, between time T05 and time T07, as an example, data Da[1,3] is input as image data from the wiring DLa to the circuit OTH. The data Da[1,3] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Da[1,3] output from the output terminal of the circuit OTH is sent to the wiring SLa[3] via the switch SWa[3], which is in the on state. At this time, the pixel circuit PIXa[1,3] in the third column of the area ALPa_C is selected as the data write destination (because a high-level potential is input to the wiring GLa[1]), so the data Da[1,3] is written to the pixel circuit PIXa[1,3].

[0205] [From time T07 to time T09 (6th period)] Between time T07 and time T09, for example, a high-level potential is input to the line SGa[4]. As a result, a high-level potential is applied to the control terminal of the switch SWa[4] of the demultiplexer DMUa of the display device 11A, and the switch SWa[4] is turned on. As a result, a conductive state is established between the line SLa[4] and the output terminal of the circuit OTH.

[0206] Also, between time T07 and time T09, for example, a low-level potential is input to the wirings SGa[1] to SGa[3]. As a result, a low-level potential is applied to each control terminal of the switches SWa[1] to SWa[3] of the demultiplexer DMUa of the display device 11A, and each of the switches SWa[1] to SWa[3] is turned off. As a result, there is no conduction between each of the wirings SLa[1] to SLa[3] and the output terminal of the circuit OTH.

[0207] Furthermore, between time T07 and time T09, for example, data Da[1,4] is input as image data from the wiring DLa to the circuit OTH. The data Da[1,4] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Da[1,4] output from the output terminal of the circuit OTH is sent to the wiring SLa[4] via the switch SWa[4], which is in the on state. At this time, the pixel circuit PIXa[1,4] in the fourth column of the area ALPa_C is selected as the data write destination (because a high-level potential is input to the wiring GLa[1]), so the data Da[1,4] is written to the pixel circuit PIXa[1,4].

[0208] [From time T02 to time T10 (7th period)] Between time T02 and time T10, for example, a high-level potential is input to the wiring GLb[1]. As a result, a high-level potential is applied from the wiring GLb[1] to the pixel circuits PIXb[1,1] to PIXb[1,4] arranged in the first row of the region ALPb_C[1] of the display device 11A. As a result, the pixel circuit PIXb[1,1] and the wiring SLb[1] are brought into a conductive state, the pixel circuit PIXb[1,2] and the wiring SLb[2] are brought into a conductive state, the pixel circuit PIXb[1,3] and the wiring SLb[3] are brought into a conductive state, and the pixel circuit PIXb[1,4] and the wiring SLb[4] are brought into a conductive state.

[0209] Furthermore, between time T02 and time T10, for example, a low-level potential is input to each of the wirings GLb[2] to GLb[V1], whereby the low-level potentials from the wirings GLb[2] to GLb[V1] are applied to the pixel circuits PIXb[2,1] to PIXb[V1,4] arranged in the second to V1 rows of the region ALPb_C[1] of the display device 11A. As a result, there is a non-conductive state between the pixel circuits PIXb[2,1] to PIXb[V1,1] located in the first column and the wiring SLb[1], there is a non-conductive state between the pixel circuits PIXb[2,2] to PIXb[V1,2] located in the second column and the wiring SLb[2], there is a non-conductive state between the pixel circuits PIXb[2,3] to PIXb[V1,3] located in the third column and the wiring SLb[3], and there is a non-conductive state between the pixel circuits PIXb[2,4] to PIXb[V1,4] located in the fourth column and the wiring SLb[4].

[0210] In other words, a high-level potential is applied to wiring GLb[1] and a low-level potential is applied to wiring GLb[2] to wiring GLb[V1], resulting in the selection of pixel circuits PIXb[1,1] to PIXb[1,4] to which image data is written.

[0211] [From time T02 to time T04 (8th period)] Between time T02 and time T04, for example, a high-level potential is input to the line SGb[1]. As a result, a high-level potential is applied to the control terminal of the switch SWb[1] of the demultiplexer DMUb of the display device 11A, and the switch SWb[1] is turned on. As a result, conduction is established between the line SLb[1] and the output terminal of the circuit OTH.

[0212] Also, between time T02 and time T04, for example, a low-level potential is input to the wirings SGb[2] to SGb[4]. As a result, a low-level potential is applied to each control terminal of the switches SWb[2] to SWb[4] of the demultiplexer DMU of the display device 11A, and each of the switches SWb[2] to SWb[4] is turned off. As a result, there is no conduction between each of the wirings SLb[2] to SLb[4] and the output terminal of the circuit OTH.

[0213] Furthermore, between time T02 and time T04, as an example, data Db[1,1] is input as image data from the wiring DLb to the circuit OTH. The data Db[1,1] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Db[1,1] output from the output terminal of the circuit OTH is sent to the wiring SLb[1] via the switch SWb[1], which is in the on state. At this time, the pixel circuit PIXb[1,1] in the first column of the area ALPb_C is selected as the data write destination (because a high-level potential is input to the wiring GLb[1]), so the data Db[1,1] is written to the pixel circuit PIXb[1,1].

[0214] [From time T04 to time T06 (9th period)] Between time T04 and time T06, for example, a high-level potential is input to the line SGb[2]. As a result, a high-level potential is applied to the control terminal of the switch SWb[2] of the demultiplexer DMUb of the display device 11A, and the switch SWb[2] is turned on. As a result, conduction is established between the line SLb[2] and the output terminal of the circuit OTH.

[0215] Also, between time T04 and time T06, for example, a low-level potential is input to the wiring SGb[1], the wiring SGb[3], and the wiring SGb[4]. As a result, a low-level potential is applied to the control terminals of the switches SWb[1], SWb[3], and SWb[4] of the demultiplexer DMUb of the display device 11A, and the switches SWb[1], SWb[3], and SWb[4] are turned off. As a result, there is no conduction between the wiring SLb[1], the wiring SLb[3], and the wiring SLb[4] and the output terminal of the circuit OTH.

[0216] Furthermore, between time T04 and time T06, as an example, data Db[1,2] is input as image data from the wiring DLb to the circuit OTH. The data Db[1,2] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Db[1,2] output from the output terminal of the circuit OTH is sent to the wiring SLb[2] via the switch SWb[2], which is in the on state. At this time, the pixel circuit PIXb[1,2] in the second column of the area ALPb_C is selected as the data write destination (because a high-level potential is input to the wiring GLb[1]), so the data Db[1,2] is written to the pixel circuit PIXb[1,2].

[0217] [From time T06 to time T08 (10th period)] Between time T06 and time T08, for example, a high-level potential is input to the line SGb[3]. As a result, a high-level potential is applied to the control terminal of the switch SWb[3] of the demultiplexer DMUb of the display device 11A, and the switch SWb[3] is turned on. As a result, conduction is established between the line SLb[3] and the output terminal of the circuit OTH.

[0218] Also, between time T06 and time T08, for example, a low-level potential is input to the wiring SGb[1], the wiring SGb[2], and the wiring SGb[4]. As a result, a low-level potential is applied to the control terminals of the switches SWb[1], SWb[2], and SWb[4] of the demultiplexer DMUb of the display device 11A, and the switches SWb[1], SWb[2], and SWb[4] are turned off. As a result, there is no conduction between the wiring SLb[1], the wiring SLb[2], and the wiring SLb[4] and the output terminal of the circuit OTH.

[0219] Furthermore, between time T06 and time T08, as an example, data Db[1,3] is input as image data from the wiring DLb to the circuit OTH. The data Db[1,3] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is output to the output terminal of the circuit OTH. The data Db[1,3] output from the output terminal of the circuit OTH is sent to the wiring SLb[3] via the switch SWb[3], which is in the on state. At this time, the pixel circuit PIXb[1,3] in the third column of the area ALPb_C is selected as the data write destination (because a high-level potential is input to the wiring GLb[1]), so the data Db[1,3] is written to the pixel circuit PIXb[1,3].

[0220] [From time T08 to time T10 (11th period)] Between time T08 and time T10, for example, a high-level potential is input to the line SGb[4]. As a result, a high-level potential is applied to the control terminal of the switch SWb[4] of the demultiplexer DMUb of the display device 11A, and the switch SWb[4] is turned on. As a result, conduction is established between the line SLb[4] and the output terminal of the circuit OTH.

[0221] Furthermore, between time T08 and time T10, for example, a low-level potential is input to the wirings SGb[1] to SGb[3]. As a result, a low-level potential is applied to each control terminal of the switches SWb[1] to SWb[3] of the demultiplexer DMUb of the display device 11A, and each of the switches SWb[1] to SWb[3] is turned off. As a result, there is no conduction between each of the wirings SLb[1] to SLb[3] and the output terminal of the circuit OTH.

[0222] Furthermore, between time T08 and time T10, as an example, data Db[1,4] is input as image data from the wiring DLb to the circuit OTH. The data Db[1,4] undergoes digital-to-analog conversion, amplification, and other processes in the circuit OTH, and is then output to the output terminal of the circuit OTH. The data Db[1,4] output from the output terminal of the circuit OTH is sent to the wiring SLb[4] via the switch SWb[4], which is in the on state. At this time, the pixel circuit PIXb[1,4] in the fourth column of the area ALPb_C is selected as the data write destination (because a high-level potential is input to the wiring GLb[1]), and therefore the data Db[1,4] is written to the pixel circuit PIXb[1,4].

[0223] [From time T09 to time T17 (12th period)] Between time T09 and time T17, for example, a high-level potential is input to the line GLa[2]. As a result, a high-level potential is applied from the line GLa[2] to the pixel circuits PIXa[2,1] to PIXa[2,4] arranged in the second row of the area ALPa_C[2] of the display device 11A. As a result, the pixel circuit PIXa[2,1] and the line SLa[2] are brought into a conductive state, the pixel circuit PIXa[2,2] and the line SLa[2] are brought into a conductive state, the pixel circuit PIXa[2,3] and the line SLa[3] are brought into a conductive state, and the pixel circuit PIXa[2,4] and the line SLa[4] are brought into a conductive state.

[0224] Furthermore, between time T09 and time T17, for example, a low-level potential is input to each of the wirings GLa[1] and GLa[3] to GLa[V1]. As a result, low-level potentials are applied from the wirings GLa[1] and GLa[3] to GLa[V1] to the pixel circuits PIXa[1,1] to PIXa[1,4] and PIXa[3,1] to PIXa[V1,4] arranged in the first row and the third row to the V1 row of the region ALPa_C[1] of the display device 11A. As a result, the pixel circuit PIXa[1,1] located in the first column and the pixel circuit PIXa[3,1] to pixel circuit PIXa[V1,1] are in a non-conductive state with the wiring SLa[1], the pixel circuit PIXa[1,2] located in the second column and the pixel circuit PIXa[3,2] to pixel circuit PIXa[V1,2] are in a non-conductive state with the wiring SLa[2], the pixel circuit PIXa[1,3] located in the third column and the pixel circuit PIXa[3,3] to pixel circuit PIXa[V1,3] are in a non-conductive state with the wiring SLa[3], and the pixel circuit PIXa[1,4] located in the fourth column and the pixel circuit PIXa[3,4] to pixel circuit PIXa[V1,4] are in a non-conductive state with the wiring SLa[4].

[0225] In other words, a high-level potential is applied to wiring GLa[2] and a low-level potential is applied to wiring GLa[1] and wiring GLa[3] to wiring GLa[V1], thereby selecting pixel circuits PIXa[2,1] to PIXa[2,4] to which image data is written.

[0226] Furthermore, between time T09 and time T17, similar to the operations performed in the third to sixth periods, the demultiplexer DMUa sequentially selects the lines SLa[1] to SLa[4], and transmits data Da[2,1] to Da[2,4] to the lines SLa[1] to SLa[4] in each period. This causes data Da[2,1] to Da[2,4] to be written to the pixel circuits PIXa[2,1] to PIXa[2,4], respectively.

[0227] [Time T10 to time T17 (13th period)] For example, from time T10 to time T17 onward, a high-level potential is input to the wiring GLb[2]. As a result, a high-level potential is applied from the wiring GLb[2] to the pixel circuits PIXb[2,1] to PIXb[2,4] arranged in the second row of the region ALPb_C[2] of the display device 11A. As a result, the pixel circuit PIXb[2,1] and the wiring SLb[2] are brought into a conductive state, the pixel circuit PIXb[2,2] and the wiring SLb[2] are brought into a conductive state, the pixel circuit PIXb[2,3] and the wiring SLb[3] are brought into a conductive state, and the pixel circuit PIXb[2,4] and the wiring SLb[4] are brought into a conductive state.

[0228] Furthermore, between time T09 and time T17, for example, a low-level potential is input to each of the wirings GLb[1] and GLb[3] to GLb[V2]. As a result, low-level potentials are applied from the wirings GLb[1] and GLb[3] to GLb[V2] to the pixel circuits PIXb[1,1] to PIXb[1,4] and PIXb[3,1] to PIXb[V2,4] arranged in the first row and the third row to the second row of the region ALPb_C[1] of the display device 11A. As a result, the pixel circuit PIXb[1,1] located in the first column and the pixel circuits PIXb[3,1] to PIXb[V2,1] become non-conductive with the wiring SLb[1], the pixel circuit PIXb[1,2] located in the second column and the pixel circuits PIXb[3,2] to PIXb[V2,2] become non-conductive with the wiring SLb[2], the pixel circuit PIXb[1,3] located in the third column and the pixel circuits PIXb[3,3] to PIXb[V2,3] become non-conductive with the wiring SLb[3], and the pixel circuit PIXb[1,4] located in the fourth column and the pixel circuits PIXb[3,4] to PIXb[V2,4] become non-conductive with the wiring SLb[4].

[0229] In other words, a high-level potential is applied to wiring GLb[2] and a low-level potential is applied to wiring GLb[1] and wiring GLb[3] to wiring GLb[V2], resulting in the selection of pixel circuits PIXb[2,1] to PIXb[2,4] to which image data is written.

[0230] Furthermore, from time T10 to time T17 onwards, similar to the operations performed in the eighth to eleventh periods, the demultiplexer DMUb sequentially selects the lines SLb[1] to SLb[4], and transmits data Db[2,1] to Db[2,4] to the lines SLb[1] to SLb[4] in each period. This causes data Db[2,1] to Db[2,4] to be written to the pixel circuits PIXb[2,1] to PIXb[2,4], respectively.

[0231] For the third row and beyond of the region ALPa_C[1] of the pixel array ALP of the display device 11A, the driver circuit GD selects the third row and beyond of the region ALPa_C[1], and similarly to the operation described above, the demultiplexer DMUa sequentially selects the wirings SLa[1] to SLa[4] to transmit image data corresponding to each column to the wirings SLa[1] to SLa[4]. Similarly, for the third row and beyond of the region ALPb_C[1] of the pixel array ALP of the display device 11A, the driver circuit GD selects the third row and beyond of the region ALPb_C[1], and similarly to the operation described above, the demultiplexer DMUb sequentially selects the wirings SLb[1] to SLb[4] to transmit image data corresponding to each column to the wirings SLb[1] to SLb[4].

[0232] In the above-described operation example of the display device 11A, writing of data to pixel circuits included in the regions ALPa_C[1] and ALPb_C[1] of the pixel array ALP has been described, but image data can also be written to pixel circuits included in the regions ALPa_C[2] to ALPa_C[h] and the regions ALPb_C[2] to ALPa_C[h] of the pixel array ALP using a similar operation. Furthermore, the drive circuits SDa[1] to SDa[h] and drive circuits SDb[1] to SDb[h] that transmit image data to the regions ALPa_C[1] to ALPa_C[h] and the regions ALPb_C[1] to ALPa_C[h] can be driven in parallel and independently, thereby shortening the time required to rewrite an image displayed on the display unit of the display device 11 (e.g., the time per frame).

[0233] 13 can be combined with the display device 10 described in embodiment 1. As a combined configuration, for example, the pixel array ALP of the display device 11 of FIG. 13 can be the pixel area ARA of the display device 10 of embodiment 1, and each of the plurality of drive circuits SDa and drive circuits SDb of FIG. 13 can be included in the local driver circuit LD of the display device 10 of embodiment 1.

[0234] The display device 11B shown in FIG. 16A has a configuration in which the pixel region ARA in the display device 10 of embodiment 1 is divided into regions ALPa_C[1] to ALPa_C[h] and regions ALPb_C[1] to ALPb_C[h]. Note that FIG. 16A excerpts the regions ALPa_C[1] and ALPb_C[1]. Also, the source wirings electrically connected to the pixel circuits PIXa included in the region ALPa_C[1] are referred to as wirings SLa_1 to SLa_3, and the source wirings electrically connected to the pixel circuits PIXb included in the region ALPb_C[1] are referred to as wirings SLb_1 to SLa_3. Note that FIG. 16A excerpts the wirings SLa_1, SLa_2, SLa_3, SLb_1, SLb_2, and SLb_3.

[0235] As described above, each of the drive circuit SDa[1] and drive circuit SDb[1] shown in Fig. 13 is included in the local driver circuit LD of the display device 11B in Fig. 16A. At least one of the remaining drive circuits SDa[2] to SDa[h] and drive circuits SDb[2] to SDb[h] may be included in the local driver circuit LD that has the drive circuit SDa[1] and drive circuit SDb[1], or may be included in a local driver circuit LD that is different from the local driver circuit LD that has the drive circuit SDa[1] and drive circuit SDb[1].

[0236] FIG. 16B shows a specific example of a pixel area ARA included in the display device 11B of FIG. 16A.

[0237] In the region ALPa_C[1] of Fig. 16B, wirings SLa_1 to SLa_3 extend for each column, and in the region ALPb_C[1] of Fig. 16B, wirings SLb_1 to SLb_3 extend for each column. Note that Fig. 16B selectively shows wirings SLa_1, SLa_2, SLa_3, SLb_1, SLb_2, and SLb_3. In the pixel region ARA of Fig. 16B, wirings SLa_1 and SLb_1 extend in the same first column, wirings SLa_2 and SLb_2 extend in the same second column, and wirings SLa_3 and SLb_3 extend in the same third column.

[0238] 16B, a plurality of pixel circuits PIXa are arranged in a matrix in the region ALPa_C[1] of the pixel region ARA, and a plurality of pixel circuits PIXb are arranged in a matrix in the region ALPb_C[1] of the pixel region ARA. It is preferable that the number of pixel circuits PIXa and the number of pixel circuits PIXb included in the region ALPa_C[1] and the region ALPb_C[1] are equal. In the region ALPa_C[1], the plurality of pixel circuits PIXa are electrically connected by wirings SLa_1 to SLa_3 for each column, and in the region ALPb_C[1], the plurality of pixel circuits PIXb are electrically connected by wirings SLb_1 to SLb_3 for each column.

[0239] As shown in FIG. 16A, display device 11 of FIG. 13 can shorten the time required to write image data even in a high-resolution display device by combining it with display device 10 described in the first embodiment.

[0240] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0241] (Embodiment 3) In this embodiment, an example of wiring routing in a pixel array and an example of a demultiplexer that realizes the example of wiring routing in a display device of one embodiment of the present invention will be described.

[0242] <Example of display device configuration> For example, wiring for transmitting image data (sometimes referred to as image signals) to a pixel array of a display device is provided for each column of the pixel array. Furthermore, for example, wiring for transmitting selection signals to a pixel array of a display device is provided for each row of the pixel array. By determining the wiring for transmitting image data and the wiring for transmitting selection signals, the address of the pixel circuit to which the image data is written is determined.

[0243] However, when the resolution of a display device is high, the number of pixel circuits to which image data is input increases, which may increase the time required for writing data in the display device.

[0244] Therefore, consider a configuration in which the pixel array is divided into two and image signals are written to each divided area. Fig. 17A shows an example of the configuration of a display device in which the pixel array ALP is divided into two areas, area ALPa and area ALPb. Note that in Fig. 17A, area ALPa and area ALPb are divided so as to include the same columns.

[0245] 17 includes, as an example, a driver circuit GD and driver circuits SD[1] to SD[h] (here, h is an integer equal to or greater than 1) in addition to the pixel array ALP. Note that although the driver circuits SD[1] to SD[h] are illustrated as being included inside the pixel array ALP in FIG. 17, one embodiment of the present invention is not limited thereto, and the driver circuits SD[1] to SD[h] may be located outside the pixel array ALP as shown in FIG. 24, which will be described later.

[0246] For the drive circuit GD, the description of the drive circuit GD included in the display device 11 described in the second embodiment should be taken into consideration.

[0247] As an example, the drive circuits SD[1] to SD[h] function as source driver circuits that transmit image data to pixel circuits included in the pixel array ALP, similar to the drive circuits SDa[1] to SDa[h] and drive circuits SDb[1] to SDb[h] included in the display device 11 described in embodiment 2. Note that the drive circuits SDa[1] to SDa[h] and drive circuits SDb[1] to SDb[h] may further include a demultiplexer for selecting a source line to which image data is transmitted.

[0248] As an example, the pixel array ALP has a plurality of pixel circuits PIX, which are arranged in a matrix of V rows and W columns (V is a multiple of 2 that is 1 or greater, W is a multiple of h that is 1 or greater, and h is an integer that is 1 or greater) within the pixel array ALP. Also, the pixel array ALP in Fig. 17 shows a configuration in which pixel circuits PIX[1,1] to PIX[V,W] are arranged. It should be noted that the pixel array ALP in FIG. 17 shows an excerpt of pixel circuit PIX[1,1], pixel circuit PIX[V / 2,1], pixel circuit PIX[V / 2+1,1], pixel circuit PIX[V,1], pixel circuit PIX[1,W / h], pixel circuit PIX[V / 2,W / h], pixel circuit PIX[V / 2+1,W / h], pixel circuit PIX[V,W / h], pixel circuit PIX[1,WW / h+1], pixel circuit PIX[V / 2,WW / h+1], pixel circuit PIX[V / 2+1,WW / h+1], pixel circuit PIX[V,WW / h+1], pixel circuit PIX[1,W], pixel circuit PIX[V / 2,W], pixel circuit PIX[V / 2+1,W], and pixel circuit PIX[V,W].

[0249] Furthermore, the area ALPa includes the pixel circuits PIX[1,1] to PIX[V / 2,W] among the pixel circuits PIX[1,1] to PIX[V,W]. On the other hand, the area ALPb includes the pixel circuits PIX[V / 2+1,1] to PIX[V,W] among the pixel circuits PIX[1,1] to PIX[V,W].

[0250] In the region ALPa, wirings GL[1] to GL[V / 2] extend for each row. Each of the wirings GL[1] to GL[V / 2] is electrically connected to the driver circuit GD. Each of the wirings GL[1] to GL[V / 2] is electrically connected to a plurality of pixel circuits PIX arranged in each row. Similarly, in the region ALPb, wirings GL[V / 2+1] to GL[V] extend for each row. Each of the wirings GL[V / 2+1] to GL[V] is electrically connected to the driver circuit GD. Each of the wirings GL[V / 2+1] to GL[V] is electrically connected to a plurality of pixel circuits PIX arranged in each row.

[0251] Also, consider the display device 12, where the columns of the pixel array ALP are divided into h regions. Specifically, for example, the region ALPa has h regions, region ALPa_C[1] to region ALPa_C[h]. Each of the regions ALPa_C[1] to region ALPa_C[h] includes W / h columns of pixel circuits PIX. Similarly, the region ALPb has h regions, region ALPb_C[1] to region ALPb_C[h], and each of the regions ALPb_C[1] to region ALPb_C[h] includes W / h columns of pixel circuits PIX.

[0252] In the region ALPa_C[1], wirings SLa[1] to SLa[W / h] extend for each column, and each of the wirings SLa[1] to SLa[W / h] is electrically connected to a plurality of pixel circuits PIX arranged in each column of the region ALPa_C[1]. Similarly, in the region ALPb_C[1], wirings SLb[1] to SLb[W / h] extend for each column, and each of the wirings SLb[1] to SLb[W / h] is electrically connected to a plurality of pixel circuits PIX arranged in each column of the region ALPb_C[1]. Each of the wirings SLa[1] to SLa[W / h] and the wirings SLb[1] to SLb[W / h] is electrically connected to the drive circuit SD[1].

[0253] Furthermore, in the region ALPa_C[h], wirings SLa[WW / h+1] to SLa[W] extend for each column, and each of the wirings SLa[WW / h+1] to SLa[W] is electrically connected to a plurality of pixel circuits PIX arranged in each column of the region ALPa_C[h]. Similarly, in the region ALPb_C[h], wirings SLb[WW / h+1] to SLb[W] extend for each column, and each of the wirings SLb[WW / h+1] to SLb[W] is electrically connected to a plurality of pixel circuits PIX arranged in each column of the region ALPb_C[h]. Each of the wirings SL[WW / h+1] to SL[W] and the wirings SLb[WW / h+1] to SLb[W] is electrically connected to the drive circuit SD[h].

[0254] 17. Similarly, wiring is provided for each column in the areas ALPa_C[2] to ALPa_C[h-1] and the areas ALPb_C[2] to ALPb_C[h-1], which are not shown in Fig. 17. One of the wirings is electrically connected to one of the driving circuits SD[2] to SD[h-1] according to the divided area.

[0255] Here, an example of a method for driving the display device 12 shown in FIG. 17 will be described.

[0256] The display device 12A shown in Fig. 18A is a schematic diagram showing a part of the pixel array ALP of the display device 12 of Fig. 17, and shows an excerpt of the area ALPa_C[1], the area ALPb_C[1], the drive circuit SD[1], and the drive circuit SD[2]. Note that in the display device 12A shown in Fig. 18A, as an example, V is 6, W is 6, and W / h is 3. That is, in the display device 12A shown in Fig. 18A, pixel circuits PIX are arranged in a matrix of 6 rows and 6 columns.

[0257] The drive circuit SD[1] provided in the display device 12A of Fig. 18A has a function of selecting one of six source wirings (corresponding to wirings SLa[1] to SLa[3] and wirings SLb[1] to SLb[3] when referring to the display device 12 of Fig. 17) and transmitting an image signal to that one source wiring. Similarly, the drive circuit SD[2] provided in the display device 12A of Fig. 18A also has a function of selecting one of six source wirings (corresponding to wirings SLa[4] to SLa[6] and wirings SLb[4] to SLb[6] when referring to the display device 12 of Fig. 17) and transmitting an image signal to that one source wiring.

[0258] Consider the case where image data is written to one pixel in the display device 12A. For example, first, the drive circuit GD transmits a selection signal to the line GL[1] to select the pixel circuit PIX arranged in the first row. The drive circuit SD[1] then selects the line SLa[1] and transmits image data to the line SLa[1]. This causes the image data to be written to the pixel circuit PIX[1,1] (see FIG. 18B). Note that in FIGS. 18B to 18F, the pixel circuits PIX to which image data has been written are hatched.

[0259] Furthermore, because the drive circuit SD[2] can operate independently of the drive circuit SD[1], it can write image data to the pixel circuits PIX included in the area ALPa_C[2], just like the drive circuit SD[1], at the same time that image data is written to the pixel circuits PIX[1,1]. As an example, in FIG. 18B, the drive circuit SD[2] selects the line SLa[4] and transmits image data to the line SLa[4]. This causes the image data to be written to the pixel circuit PIX[1,4].

[0260] 18C shows an example in which, in the display device 12A, after image data is written to the pixel circuits PIX[1,1] and PIX[1,4], the drive circuit SD[1] selects the wiring SLa[2] to write image data to the pixel circuit PIX[1,2], and the drive circuit SD[2] selects the wiring SLa[5] to write image data to the pixel circuit PIX[1,5]. Also shown in FIG. 18C is an example in which, in the display device 12A, after image data is written to the pixel circuits PIX[1,2] and PIX[1,5], the drive circuit SD[1] selects the wiring SLa[3] to write image data to the pixel circuit PIX[1,3], and the drive circuit SD[2] selects the wiring SLa[6] to write image data to the pixel circuit PIX[1,6].

[0261] 18D, in the display device 12A, after image data is written to pixel circuits PIX[1,3] and PIX[1,6], the drive circuit GD transmits a selection signal to line GL[4] to select the pixel circuit PIX arranged in the fourth row. Then, the drive circuit SD[1] selects line SLb[1] and transmits image data to line SLb[1], and the drive circuit SD[2] selects line SLb[4] and transmits image data to line SLb[4]. This allows image data to be written to pixel circuits PIX[4,1] and PIX[4,4].

[0262] 18E shows an example in which, in the display device 12A, after image data is written to the pixel circuits PIX[4,1] and PIX[4,4], the drive circuit SD[1] selects the wiring SLa[2] to write image data to the pixel circuit PIX[4,2], and the drive circuit SD[2] selects the wiring SLa[5] to write image data to the pixel circuit PIX[4,5]. Also shown in FIG. 18E is an example in which, in the display device 12A, after image data is written to the pixel circuits PIX[4,2] and PIX[4,5], the drive circuit SD[1] selects the wiring SLa[3] to write image data to the pixel circuit PIX[4,3], and the drive circuit SD[2] selects the wiring SLa[6] to write image data to the pixel circuit PIX[4,6].

[0263] As described above, in the display device 12A, the pixel circuits PIX in the first row are selected by the drive circuit GD, and image data is sequentially transmitted to the wirings SLa[1] to SLa[3] by the drive circuit SD[1], and sequentially transmitted to the wirings SLa[4] to SLa[6] by the drive circuit SD[2], thereby writing image data to each of the pixel circuits PIX in the first row. Subsequently, the pixel circuits PIX in the fourth row are selected by the drive circuit GD, and image data is sequentially transmitted to the wirings SLb[1] to SLb[3] by the drive circuit SD[1], and sequentially transmitted to the wirings SLb[4] to SLb[6] by the drive circuit SD[2], thereby writing image data to each of the pixel circuits PIX in the fourth row.

[0264] Similarly, in the display device 12A, the pixel circuits PIX in the second row are selected by the drive circuit GD, and image data is sequentially transmitted to the wirings SLa[1] to SLa[3] by the drive circuit SD[1], and sequentially transmitted to the wirings SLa[4] to SLa[6] by the drive circuit SD[2], thereby writing image data to each of the pixel circuits PIX in the second row. Subsequently, the pixel circuits PIX in the fifth row are selected by the drive circuit GD, and image data is sequentially transmitted to the wirings SLb[1] to SLb[3] by the drive circuit SD[1], and sequentially transmitted to the wirings SLb[4] to SLb[6] by the drive circuit SD[2], thereby writing image data to each of the pixel circuits PIX in the fifth row.

[0265] Furthermore, in the display device 12A, the pixel circuits PIX in the third row are selected by the drive circuit GD, and image data is sequentially transmitted to the wirings SLa[1] to SLa[3] by the drive circuit SD[1], and sequentially transmitted to the wirings SLa[4] to SLa[6] by the drive circuit SD[2], thereby writing image data to each of the pixel circuits PIX in the third row. Subsequently, the pixel circuits PIX in the sixth row are selected by the drive circuit GD, and image data is sequentially transmitted to the wirings SLb[1] to SLb[3] by the drive circuit SD[1], and sequentially transmitted to the wirings SLb[4] to SLb[6] by the drive circuit SD[2], thereby writing image data to each of the pixel circuits PIX in the sixth row.

[0266] As a result, the display device 12A can write image data to each of the pixel circuits PIX[1,1] to PIX[6,6] as shown in FIG. 18F.

[0267] Here, as an example of a configuration applied to a conventional display device, a display device 13A is shown in Fig. 19. The display device 13A in Fig. 19 is shown to include a drive circuit SD[1] and a plurality of pixel circuits PIX. Note that the display device 13A shown in Fig. 19 has pixel circuits PIX arranged in a matrix of 6 rows and 6 columns, similar to the display device 12A in Fig. 18A.

[0268] Also, the drive circuit SD[1] provided in the display device 13A in FIG. 19 has a function of selecting one of the six source lines and transmitting an image signal to that one source line.

[0269] The display device 12A of Fig. 18A differs from the display device 13A of Fig. 19, which is an example of a conventional display device, in terms of the length of the source wiring extending in a row. Specifically, for example, the display device 12A of Fig. 18A has a configuration in which the multiple source wirings of the display device 13A of Fig. 19 are divided into regions of rows 1 to 3 and rows 4 to 6. That is, the source wiring connected to one of the output terminals of the drive circuit SD[1] (or drive circuit SD[2]) in the display device 12A of Fig. 18A is roughly half the length of the source wiring connected to one of the output terminals of the drive circuit SD[1] in the display device 13A of Fig. 19. Therefore, the parasitic resistance and parasitic capacitance of each source wiring in the display device 12A of Fig. 18A can be made smaller than the parasitic resistance and parasitic capacitance of each source wiring in the display device 13A of Fig. 19. Therefore, the time constant of the source wiring of display device 12A in FIG. 18A can be made smaller than the time constant of the source wiring of display device 13A in FIG. 19, thereby speeding up the operation of writing image data to display device 12A.

[0270] Therefore, as an example, as shown in the display device 12 of Figure 17, by dividing the pixel array ALP into two and driving the pixel circuits PIX included in each part of the divided areas with the drive circuit SD, image data can be written quickly to the pixel circuits PIX included in the display device 12, thereby shortening the writing time.

[0271] 17, the larger the area of ​​the display unit (i.e., the pixel array ALP), the larger the area of ​​the circuit layer SICL, making it easier to arrange the drive circuits SD[1] to SD[h]. Therefore, the configuration of the display device 12 in FIG. 17 is suitable for cases where the area of ​​the pixel array ALP is large.

[0272] Note that the display device of one embodiment of the present invention is not limited to the above-described configuration example of the display device 12. The display device of one embodiment of the present invention may be a modification of the above-described display device 12 depending on the situation.

[0273] For example, the display device 12 in Figure 17 is configured so that one drive circuit SD transmits image data to each of the pixel circuits in area ALPa_C and area ALPb_C included in the pixel array ALP, but it may also be configured so that one drive circuit SD transmits image data to pixel circuits in three or more areas.

[0274] Specifically, the display device 12 of Fig. 17 can be modified to have the configuration of a display device 12AA shown in Fig. 20. The display device 12AA, like the display device of Fig. 17, has a pixel array ALP including a plurality of pixel circuits PIX arranged in a matrix of V rows and W columns (here, V is a multiple of 2 × d and is equal to or greater than 1, W is a multiple of h and is equal to or greater than 1, d is an integer equal to or greater than 2, and h is an integer equal to or greater than 1). The display device 12AA also has a configuration in which the pixel array ALP is divided into a plurality of rows, and the pixel array ALP is divided into 2 × d regions, for example. Fig. 20 shows regions ALPa[1] to ALPa[d] and regions ALPb[1] to ALPb[d] as the regions divided into 2 × d regions. Furthermore, the display device 12AA has a configuration in which the regions ALPa[1] to ALPa[d] and the regions ALPb[1] to ALPb[d] are each further divided into a plurality of columns, and the regions ALPa[1] to ALPa[d] and the regions ALPb[1] to ALPb[d] are each divided into h regions, for example. 20 shows, as an example, an example in which the region ALPa[1] has the regions ALPa[1]_C[1] to ALPa[1]_C[h], the region ALPa[d] has the regions ALPa[d]_C[1] to ALPa[d]_C[h], the region ALPb[1] has the regions ALPb[1]_C[1] to ALPb[1]_C[h], and the region ALPb[d] has the regions ALPb[d]_C[1] to ALPb[d]_C[h].

[0275] In addition, in the display device 12AA of Figure 20, the pixel circuit PIX[1,1] included in the area ALPa[1]_C[1], the pixel circuit PIX[1,WW / h+1] included in the area ALPa[1]_C[h], the pixel circuit PIX[V / 2-V / 2d+1,1] included in the area ALPa[d]_C[1], and the pixel circuit PIX[V / 2-V / 2d+1,WW / h+1] included in the area ALPa[d]_C[h] are shown. In addition, in the display device 12AA of Figure 20, the pixel circuit PIX[V / 2+1,1] included in the area ALPb[1]_C[1], the pixel circuit PIX[V / 2+1,WW / h+1] included in the area ALPb[1]_C[h], the pixel circuit PIX[VV / 2d+1,1] included in the area ALPb[d]_C[1], and the pixel circuit PIX[VV / 2d+1,WW / h+1] included in the area ALPb[d]_C[h] are shown.

[0276] 20, wirings GL[1] to GL[V] extend in the row direction in the pixel array ALP. Note that, in FIG. 20, wirings GL[1], wirings GL[V / 2-V / 2d+1], wirings GL[V / 2+1], and wirings GL[VV / 2d+1] are selectively illustrated from among the wirings GL[1] to GL[V].

[0277] 20, 2×d source wirings are provided for each column in the pixel array ALP. Specifically, for example, wirings SLa[1]_[1] to SLa[d]_[1] and wirings SLb[1]_[1] to SLb[d]_[1] are provided for the first column of the pixel array ALP, and wirings SLa[1]_[WW / h+1] to SLa[d]_[WW / h+1] and wirings SLb[1]_[WW / h+1] to SLb[d]_[WW / h+1] are provided for the WW / h+1-th column of the pixel array ALP. In addition, Figure 20 illustrates an excerpt of wiring SLa[1]_[1], wiring SLa[d]_[1], wiring SLb[1]_[1], wiring SLb[d]_[1], wiring SLa[1]_[WW / h+1], wiring SLa[d]_[WW / h+1], wiring SLb[1]_[WW / h+1], and wiring SLb[d]_[WW / h+1].

[0278] Note that [x]_[y] attached to the wiring SLa (wiring SLb) indicates the column address of the pixel array ALP and the type of area ALPa (area ALPb) containing the electrically connected pixel circuit. Specifically, for example, wiring SLa[2]_[d-1] indicates that it is the wiring in the second column of the pixel array ALP and is electrically connected to the pixel circuit PIX included in the area ALPa[d-1]. Also, for example, wiring SLb[W]_[2] indicates that it is the wiring in the Wth column of the pixel array ALP and is electrically connected to the pixel circuit PIX included in the area ALPb[2].

[0279] 20, the pixel circuits PIX arranged in the first row of the pixel array ALP are electrically connected to the drive circuit GD via wiring GL[1]. The pixel circuits PIX arranged in the V / d+1th row of the pixel array ALP are electrically connected to the drive circuit GD via wiring GL[V / d+1]. The pixel circuits PIX arranged in the VV / d+1th row of the pixel array ALP are electrically connected to the drive circuit GD via wiring GL[VV / d+1].

[0280] 20, the pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPa[1]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLa[1]_[1]. The pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPa[d]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLa[d]_[1]. The pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPb[1]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLb[1]_[1]. The pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPb[d]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLb[d]_[1].

[0281] By configuring the display device 12AA shown in Fig. 20, it is possible to transmit image data to pixel circuits included in each of multiple regions using a single drive circuit SD. Specifically, for example, in the display device 12AA shown in Fig. 20, it is possible to transmit image data to pixel circuits included in each of the regions ALPa[1]_C[1] to ALPa[d]_C[1] and the regions ALPb[1]_C[1] to ALPb[d]_C[1] using the drive circuit SD[1].

[0282] Furthermore, for example, the display device 12 is configured such that the wiring SLa and wiring SLb are routed so as to be electrically connected to the driving circuits SD[1] to SD[h] between the area ALPa and the area ALPb, but the display device 12 may also be configured such that the wiring SLa and wiring SLb are each routed in the direction of one side of the pixel array ALP, and the wiring SLa and wiring SLb are electrically connected to the driving circuits SD[1] to SD[h].

[0283] 21 is configured, as an example, similar to the display device 12 of FIG. 17, except that the wirings SLa[1] to SLa[W] and the wirings SLb[1] to SLb[W] are routed toward the top of the drawing, which is the direction of one side of the pixel array ALP, and the wirings SLa[1] to SLa[W] and the wirings SLb[1] to SLb[W] are electrically connected to the drive circuits SD[1] to SD[h]. Specifically, the wirings SLa[1] to SLa[W] extend through the interior of the region ALPa and along the column direction of the pixel array ALP, and the wirings SLb[1] to SLb[W] extend through the interior of the region ALPa and the interior of the region ALPb and along the column direction of the pixel array ALP.

[0284] 21 is configured such that the wirings SLa[1] to SLa[W] and the wirings SLb[1] to SLb[W] are routed outside the pixel array ALP, not between the areas ALPa and ALPb, and therefore there is no need to route wiring for electrically connecting the wirings SLa[1] to SLa[W] and the wirings SLb[1] to SLb[W] to the drive circuits SD[1] to SD[h] inside the pixel array ALP of the display device 14. This may simplify the layout of the pixel array ALP.

[0285] In addition, in the display device 14 of Figure 21, like the display device 12A shown in Figure 18, the areas ALPa_C[1] and ALPb_C[1] are electrically connected to the driving circuit SD[1], and the areas ALPa_C[h] and ALPb_C[h] are electrically connected to the driving circuit SD[h], so the display device 14 of Figure 21 can write image data in the same operating method as the display device 12A shown in Figure 18.

[0286] Furthermore, the display device 14 in Figure 21 is configured so that one driving circuit SD transmits image data to each of the pixel circuits in the areas ALPa_C and ALPb_C included in the pixel array ALP, but it may also be configured so that one driving circuit SD transmits image data to pixel circuits in three or more areas.

[0287] Specifically, the display device 14 of FIG. 21 can be modified to have the configuration of a display device 14A shown in FIG. 22. The display device 14A has a pixel array ALP including a plurality of pixel circuits PIX arranged in a matrix of V rows and W columns (where V is a multiple of 2 and is 1 or greater, and W is a multiple of h and is 1 or greater), similar to the display device of FIG. 17. The display device 14A also has a configuration in which the pixel array ALP is divided into a plurality of rows, and the pixel array ALP is divided into d regions, for example. In FIG. 22, regions ALPa[1] to ALPa[d] are shown as the d regions divided into d regions. The display device 14A also has a configuration in which each of the regions ALPa[1] to ALPa[d] is further divided into a plurality of columns, and each of the regions ALPa[1] to ALPa[d] is divided into h regions, for example. Figure 22 shows, as an example, an example in which area ALPa[1] has areas ALPa[1]_C[1] to ALPa[1]_C[h], area ALPa[2] has areas ALPa[2]_C[1] to ALPa[2]_C[h], and area ALPa[d] has areas ALPa[d]_C[1] to ALPa[d]_C[h].

[0288] In addition, in the display device 14A of Figure 22, the pixel circuit PIX[1,1] included in the area ALPa[1]_C[1], the pixel circuit PIX[1,WW / h+1] included in the area ALPa[1]_C[h], the pixel circuit PIX[V / d+1,1] included in the area ALPa[2]_C[1], the pixel circuit PIX[V / d+1,WW / h+1] included in the area ALPa[2]_C[h], the pixel circuit PIX[VV / d+1,1] included in the area ALPa[d]_C[1], and the pixel circuit PIX[VV / d+1,WW / h+1] included in the area ALPa[d]_C[h] are shown.

[0289] 22, wirings GL[1] to GL[V] extend in the row direction in the pixel array ALP. Note that, in FIG. 22, wirings GL[1], GL[V / d+1], and GL[VV / d+1] are selectively illustrated among the wirings GL[1] to GL[V].

[0290] 22, the pixel array ALP has d source wirings extending for each column. Specifically, for example, the wirings SLa[1]_[1] to SLa[d]_[1] extend to the first column of the pixel array ALP, and the wirings SLa[1]_[WW / h+1] to SLa[d]_[WW / h+1] extend to the WW / h+1 column of the pixel array ALP. Note that FIG. 22 illustrates only the wirings SLa[1]_[1], SLa[2]_[1], SLa[d]_[1], SLa[1]_[WW / h+1], SLa[2]_[WW / h+1], and SLa[d]_[WW / h+1].

[0291] The [x]_[y] attached to the wiring SLa indicates the column address of the pixel array ALP and the type of the area ALPa that includes the electrically connected pixel circuit PIX. Specifically, for example, the wiring SLa[2]_[d-1] indicates that the wiring SLa[2]_[d-1] is the wiring for the second column of the pixel array ALP and is electrically connected to the pixel circuit PIX included in the area ALPa[d-1].

[0292] 22, the pixel circuits PIX arranged in the first row of the pixel array ALP are electrically connected to the drive circuit GD via wiring GL[1]. The pixel circuits PIX arranged in the V / d+1th row of the pixel array ALP are electrically connected to the drive circuit GD via wiring GL[V / d+1]. The pixel circuits PIX arranged in the VV / d+1th row of the pixel array ALP are electrically connected to the drive circuit GD via wiring GL[VV / d+1].

[0293] 22, the pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPa[1]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLa[1]_[1]. The pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPa[2]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLa[2]_[1]. The pixel circuit PIX arranged in the first column of the pixel array ALP and included in the region ALPa[d]_C[1] is electrically connected to the drive circuit SD[1] via the wiring SLa[d]_[1].

[0294] By configuring the display device 14A shown in FIG. 22, one drive circuit SD can transmit image data to pixel circuits included in each of three or more regions.

[0295] Furthermore, for example, the display device 12 is configured such that each of the wirings GL[1] to GL[V] is extended as a gate wiring, one per row, but the display device 12 may also be configured such that two gate wirings are extended per row.

[0296] The display device 12B shown in Fig. 23 illustrates a configuration example in which two gate lines are extended per row in the display device 12 of Fig. 17. Specifically, the display device 12B shown in Fig. 23 is a configuration example in which the region ALPa_C[1] and the region ALPb_C[1] of the pixel array ALP and the drive circuit SD[1] are respectively excerpted from the display device 12 of Fig. 17, and the lines GL[1]-1 to GL[V]-1 and the lines GL[1]-2 to GL[V]-2 each function as the gate lines of the display device 12B shown in Fig. 23. Note that W / h is set to 3 in the display device 12B of Fig. 23.

[0297] 23, the region ALPa_C[1] includes, for example, pixel circuits PIX[1,1] to PIX[V / 2,3], and the region ALPb_C[1] includes, for example, pixel circuits PIX[V / 2+1,1] to PIX[V,3]. In addition, since W / h is 3, the region ALPa_C[1] includes wirings SLa[1] to SLa[3] that extend for each column, and the region ALPb_C[1] includes wirings SLb[1] to SLb[3] that extend for each column.

[0298] The display device 12B in Figure 23 shows a configuration in which wiring GL[1]-1 and wiring GL[1]-2 are extended to the first row as a set of gate wiring, wiring GL[V / 2]-1 and wiring GL[V / 2]-2 are extended to the V / 2 row as a set of gate wiring, wiring GL[V / 2+1]-1 and wiring GL[V / 2+1]-2 are extended to the V / 2+1 row as a set of gate wiring, and wiring GL[V]-1 and wiring GL[V]-2 are extended to the V row as a set of gate wiring.

[0299] 23, each of the pixel circuits PIX included in the pixel array ALP has a transistor Tr as a write transistor for image data. A first terminal of the transistor Tr included in each of the pixel circuits PIX is electrically connected to a source wiring (one of wirings SLa[1] to SLa[3] and wirings SLb[1] to SLb[3]) of the column of the pixel circuit PIX, and a second terminal of the transistor Tr is electrically connected to a circuit element of the pixel circuit PIX.

[0300] The gates of the transistors Tr included in the pixel circuits PIX arranged in odd-numbered columns are electrically connected to one of the gate wirings (one of wirings GL[1]-1 to GL[V]-1) ​​of the row of the pixel circuits PIX, and the gates of the transistors Tr included in the pixel circuits PIX arranged in even-numbered columns are electrically connected to the other of the gate wirings (one of wirings GL[1]-2 to GL[V]-2) of the row of the pixel circuits PIX.

[0301] As shown in FIG. 23 , by configuring the display device 12B so that two gate lines extend per row, the transistors Tr included in the pixel circuits PIX arranged in a given row can be switched between on and off independently for odd-numbered and even-numbered columns. For example, the display device 12B can turn off the transistors Tr included in one of the pixel circuits PIX in an odd-numbered or even-numbered column and write image data to the other pixel circuit PIX in an odd-numbered or even-numbered column. In other words, the configuration of the display device 12B allows the amount of image data displayed in the pixel array ALP to be arbitrarily reduced, thereby increasing the frame frequency of the display device 12B. Furthermore, for example, while writing image data to the pixel circuits PIX in an odd-numbered column, the transistors Tr of the pixel circuits PIX in an even-numbered column can be turned on. In this way, part of one write period for the odd-numbered column and part of one write period for the even-numbered column can overlap, thereby shortening the image write time for the entire pixel array ALP of the display device 12B.

[0302] 23, the gates of the transistors Tr included in the pixel circuits PIX in odd columns are electrically connected to one side of the gate wirings for the row of the pixel circuits PIX (one of the wirings GL[1]-1 to GL[V]-1), and the gates of the transistors Tr included in the pixel circuits PIX in even columns are electrically connected to the other side of the gate wirings for the row of the pixel circuits PIX (one of the wirings GL[1]-2 to GL[V]-2). However, the configuration of the display device of one embodiment of the present invention is not limited to this. For example, the display device of one embodiment of the present invention may be configured such that, in four consecutive pixel circuits PIX in a certain row of the pixel array ALP, the gates of the transistors Tr included in the pixel circuits PIX in the first two consecutive columns are electrically connected to one side of the gate wirings for the row (one of the wirings GL[1]-1 to GL[V]-1), and the gates of the transistors Tr included in the pixel circuits PIX in the remaining two consecutive columns are electrically connected to the other side of the gate wirings for the row (one of the wirings GL[1]-2 to GL[V]-2). Furthermore, for example, a display device of one embodiment of the present invention may be configured such that, in a plurality of pixel circuits PIX included in one row of a pixel array ALP, the gate of a transistor Tr included in each selected from the plurality of pixel circuits PIX is electrically connected to one side of the gate wiring of that row (one of the wirings GL[1]-1 to GL[V]-1), and the gate of each transistor Tr included in the remaining pixel circuits PIX is electrically connected to the other side of the gate wiring of that row (one of the wirings GL[1]-2 to GL[V]-2).

[0303] Next, a configuration example of the drive circuit SD will be described. The display device 12C shown in Fig. 24 is a configuration example in which the area ALPa_C[1] and the area ALPb_C[1] of the pixel array ALP and the drive circuit SD[1] are respectively excerpted from the display device 12 of Fig. 17. Note that in the display device 12C shown in Fig. 24, W / h is set to 3.

[0304] 24, the pixel array ALP of the display device 12C includes, for example, pixel circuits PIX[1,1] to PIX[V / 2,3] in the region ALPa_C[1], and pixel circuits PIX[V / 2+1,1] to PIX[V,3] in the region ALPb_C[1]. Since W / h is 3, wirings SLa[1] to SLa[3] are provided for each column in the region ALPa_C[1], and wirings SLb[1] to SLb[3] are provided for each column in the region ALPb_C[1]. Furthermore, wirings GL[1] to GL[V / 2] are provided for each row in the region ALPa_C[1], and wirings GL[V / 2+1] to GL[V] are provided for each row in the region ALPb_C[1].

[0305] Moreover, the drive circuit SD[1] shown in FIG. 24 includes, as an example, a demultiplexer DMU and a circuit OTH.

[0306] For the demultiplexer DMU shown in Fig. 24, please refer to the description of the demultiplexer DMUa and demultiplexer DMUb explained in embodiment 2. Note that the demultiplexer DMU shown in Fig. 24 differs from the demultiplexer DMUa and demultiplexer DMUb in that it has six output terminals.

[0307] For the circuit OTH shown in FIG. 24, the description of the circuit OTH in Embodiment 2 can be referred to.

[0308] The demultiplexer DMU includes, for example, switches SWa[1] to SWa[3] and switches SWb[1] to SWb[3].

[0309] In addition, a first terminal of the switch SWa[1] is electrically connected to the wiring SLa[1], a second terminal of the switch SWa[1] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[1] is electrically connected to the wiring SGa[1]. A first terminal of the switch SWa[2] is electrically connected to the wiring SLa[2], a second terminal of the switch SWa[2] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[2] is electrically connected to the wiring SGa[2]. A first terminal of the switch SWa[3] is electrically connected to the wiring SLa[3], a second terminal of the switch SWa[3] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWa[3] is electrically connected to the wiring SGa[3]. A first terminal of the switch SWb[1] is electrically connected to the wiring SLb[1], a second terminal of the switch SWb[1] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[1] is electrically connected to the wiring SGb[1]. A first terminal of the switch SWb[2] is electrically connected to the wiring SLb[2], a second terminal of the switch SWb[2] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[2] is electrically connected to the wiring SGb[2]. A first terminal of the switch SWb[3] is electrically connected to the wiring SLb[3], a second terminal of the switch SWb[3] is electrically connected to the output terminal of the circuit OTH, and a control terminal of the switch SWb[3] is electrically connected to the wiring SGb[3].

[0310] The input terminal of the circuit OTH is electrically connected to the wiring DL.

[0311] The switches SWa[1] to SWa[3] and the switches SWb[1] to SWb[3] can be switches that can be applied to the switches SWa[1] to SWa[3] and the switches SWb[1] to SWb[3] described in embodiment 2. Therefore, for an operation example of the switches SWa[1] to SWa[3] and the switches SWb[1] to SWb[3] in this embodiment, refer to the description of the switches SWa[1] to SWa[4] and the switches SWb[1] to SWb[4] described in embodiment 2.

[0312] Similarly to the wirings SGa[1] to SGa[3] and the wirings SGb[1] to SGb[3] described in Embodiment 2, the wirings SGa[1] to SGa[4] and the wirings SGb[1] to SGb[4] function as wirings that supply a voltage for switching between a conductive state and a non-conductive state of a switch electrically connected to the control terminal of the wiring. Therefore, the voltage can be, for example, a high-level potential or a low-level potential.

[0313] As described above, the demultiplexer DMU can, for example, apply a high-level pulse voltage to any one of the wirings SGa[1] to SGa[3] and the wirings SGb[1] to SGb[3], thereby turning on the switch having the control terminal to which the pulse voltage is applied for only the time the pulse voltage is applied. Furthermore, for example, the demultiplexer DMU can sequentially turn on the switches SWa[1] to SWa[3] and the switches SWb[1] to SWb[3] by sequentially applying a high-level pulse voltage to each of the wirings SGa[1] to SGa[3] and the wirings SGb[1] to SGb[3]. This allows the demultiplexer DMU to sequentially select the wirings SLa[1] to SLa[3] and the wirings SLb[1] to SLb[3] as destinations for transmitting image data.

[0314] The display device according to one embodiment of the present invention is not limited to the configuration of the display device 12C. For example, the display device according to one embodiment of the present invention can have a configuration obtained by appropriately modifying the display device 12C.

[0315] For example, in the display device 12C, two output terminals of a demultiplexer DMU included in the drive circuit SD are electrically connected to two source lines (e.g., a pair of lines SLa[1] and SLb[1], a pair of lines SLa[2] and SLb[2], etc.) extending in the same column in the pixel array ALP, but the display device 12C may include a configuration in which the two output terminals of the demultiplexer DMU are not electrically connected to the two source lines extending in the same column. In other words, the display device 12C may include a configuration in which one of the lines SLa[x] or the lines SLb[x] (here, x is an integer between 1 and 3) is electrically connected to multiple output terminals of the demultiplexer, but the other of the lines SLa[x] or the lines SLb[x] is not electrically connected to the multiple output terminals of the demultiplexer.

[0316] 25 is a modified example of the display device 12C, and is a display device including a configuration in which one of the wirings SLa[x] or SLb[x] is electrically connected to a plurality of output terminals of the demultiplexer, and the other of the wirings SLa[x] or SLb[x] is not electrically connected to the plurality of output terminals of the demultiplexer. Specifically, the display device 12D is configured such that the demultiplexer DMU in the display device 12C does not include the switches SWb[1] and SWa[3].

[0317] 25, the display device 12D shows a configuration in which the region ALPa_C[1] includes pixel circuits PIX ranging from the first row, first column to the second column of the V / 2 row of the pixel array ALP, the region ALPa_C[2] includes pixel circuits PIX ranging from the first row, third column to the third column of the V / 2 row, the region ALPb_C[1] includes pixel circuits PIX ranging from the first column of the V / 2+1 row to the first column of the V row of the pixel array ALP, and the region ALPb_C[2] includes pixel circuits PIX ranging from the third column of the V / 2+1 row to the third column of the V row. In other words, the region ALPa_C[1] and the region ALPb_C[2], which are electrically connected to the drive circuit SD[1], include different columns in the pixel array ALP.

[0318] Note that the pixel array ALP in Figure 25 shows an excerpt of pixel circuit PIX[1,1], pixel circuit PIX[V / 2,2], pixel circuit PIX[1,3], pixel circuit PIX[V / 2,3], pixel circuit PIX[V / 2+1,1], pixel circuit PIX[V,1], pixel circuit PIX[V / 2+1,2], and pixel circuit PIX[V,3].

[0319] In the display device 12D of Fig. 25, the driving circuit SD[1] has the function of driving the pixel circuits PIX included in the region ALPa_C[1] and the region ALPb_C[2]. Note that when driving the pixel circuits PIX included in the region ALPa_C[2] and the region ALPb_C[1], it is preferable to drive them by a driving circuit SD other than the driving circuit SD[1]. In other words, it is preferable that each of the wiring SLa[3] and the wiring SLb[1] is electrically connected to a demultiplexer DMU of a driving circuit SD other than the driving circuit SD[1].

[0320] 25, the wiring SLa[3] and the wiring SLb[1] are not electrically connected to the driver circuit SD[1]. However, in a display device of one embodiment of the present invention, for example, in the display device 12D, one of the wiring SLa[2] and the wiring SLb[2] may not be electrically connected to the driver circuit SD[1]. Furthermore, in the display device 12 of FIG. 17, for example, the wirings SLa and SLb in the same column may be electrically connected to different driver circuits SD.

[0321] 17, the driver circuit SD[1] is electrically connected to the pixel circuits PIX in the regions ALPa_C[1] and ALPb_C[1], and the driver circuit SD[h] is electrically connected to the pixel circuits PIX in the regions ALPa_C[h] and ALPb_C[h]. However, one embodiment of the present invention is not limited to this. For example, in the display device 12, the driver circuit SD[1] may be electrically connected to the pixel circuits PIX in another region, instead of the region ALPa_C[1] and / or the region ALPb_C[1]. For example, the driver circuit SD[1] may be electrically connected to one of the regions ALPa_C[2] to ALPa_C[h] instead of the region ALPa_C[1]. The driver circuit SD[1] may be electrically connected to one of the regions ALPb_C[2] to ALPb_C[h] instead of the region ALPb_C[1]. In other words, the driving circuit SD[x] (where x is an integer greater than or equal to 1 and less than or equal to h) included in the display device 12 may be configured to be electrically connected to any one of the areas ALPa_C[1] to ALPa_C[h] and any one of the areas ALPb_C[1] to ALPb_C[h].

[0322] 17 can be combined with the display device 10 described in embodiment 1. As a combined configuration, for example, the pixel array ALP of the display device 12 of FIG. 17 can be the pixel area ARA of the display device 10 of embodiment 1, and the multiple drive circuits SD of FIG. 17 can be included in the local driver circuit LD of the display device 10 of embodiment 1.

[0323] A display device 12E shown in Fig. 26A has a configuration in which the pixel region ARA in the display device 10 of Embodiment 1 is divided into regions ARAa and ARAb. The source wirings electrically connected to the pixel circuits PIX included in the region ARAa are referred to as wirings SLa_1 to SLa_p (where p is an integer greater than or equal to 1), and the source wirings electrically connected to the pixel circuits PIX included in the region ARAb are referred to as wirings SLb_1 to SLa_p. Note that Fig. 26A selectively shows wirings SLa_1, SLa_2, SLa_3, SLa_p, SLb_1, SLb_2, SLb_3, and SLb_p.

[0324] As described above, the plurality of drive circuits SD shown in FIG. 17 are included in the local driver circuit LD of the display device 12E in FIG.

[0325] FIG. 26B shows a specific example of a pixel area ARA included in the display device 12E of FIG. 26A.

[0326] In the region ARAa of Fig. 26B, wirings SLa_1 to SLa_p extend for each column, and in the region ARAb of Fig. 26B, wirings SLb_1 to SLb_p extend for each column. Note that Fig. 26B selectively shows wirings SLa_1, SLa_2, SLa_3, SLb_1, SLb_2, and SLb_3. In the pixel region ARA of Fig. 26B, wirings SLa_1 and SLb_1 extend in the same first column, wirings SLa_2 and SLb_2 extend in the same second column, and wirings SLa_3 and SLb_3 extend in the same third column.

[0327] 26B, a plurality of pixel circuits PIX are arranged in a matrix. The number of pixel circuits PIX included in each of the regions ARAa and ARAb is preferably equal. In the region ARAa, the plurality of pixel circuits PIX are electrically connected by wirings SLa_1 to SLa_p for each column, and in the region ARAb, the plurality of pixel circuits PIX are electrically connected by wirings SLb_1 to SLb_p for each column.

[0328] As shown in FIG. 26, by combining the display device 12 of FIG. 17 with the display device 10 described in the first embodiment, it is possible to shorten the time required to write image data even in a display device with high resolution.

[0329] Note that this embodiment mode can be appropriately combined with other embodiment modes described in this specification.

[0330] (Fourth embodiment) In this embodiment, a structural example of a display device according to one embodiment of the present invention will be described.

[0331] <Example of display device configuration> 27 is a cross-sectional view illustrating an example of a display device according to one embodiment of the present invention. For example, a display device 10 illustrated in FIG. 27 has a structure in which a pixel circuit, a driver circuit, and the like are provided over a substrate 310.

[0332] The substrate 310 corresponds to, for example, the substrate BS described in the above embodiment, and therefore, the substrate 310 can be made of a material that can be applied to the substrate BS.

[0333] In this embodiment, the substrate 310 will be described as a semiconductor substrate made of silicon or the like.

[0334] The display device 10 includes a transistor 300, a transistor 500, and light-emitting devices 150a to 150c on a substrate 310.

[0335] The transistor 300 is provided over a substrate 310 and includes an element isolation layer 312, a conductor 316, an insulator 315, an insulator 317, a semiconductor region 313 formed of part of the substrate 310, and low-resistance regions 314a and 314b functioning as source and drain regions. Therefore, the transistor 300 is a transistor (a Si transistor) whose channel formation region contains silicon. Note that although FIG. 27 illustrates a structure in which one of the source and drain regions of the transistor 300 is electrically connected to a conductor 330, a conductor 356, and a conductor 366 (to be described later) through a conductor 328 (to be described later), the electrical connection structure of the semiconductor device of one embodiment of the present invention is not limited thereto. A semiconductor device of one embodiment of the present invention may have a structure in which the other of the source and the drain of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 through the conductor 328, or a structure in which the gate of the transistor 300 is electrically connected to the conductor 330, the conductor 356, and the conductor 366 through the conductor 328.

[0336] The transistor 300 can be made into a fin type by, for example, configuring the top surface and the side surfaces in the channel width direction of the semiconductor region 313 to be covered with a conductor 316 via an insulator 315 that functions as a gate insulating film. By configuring the transistor 300 as a fin type, the effective channel width can be increased, and the on-state characteristics of the transistor 300 can be improved. Furthermore, the contribution of the electric field of the gate electrode can be increased, and the off-state characteristics of the transistor 300 can be improved.

[0337] Note that the transistor 300 may be either a p-channel type or an n-channel type. Alternatively, a plurality of transistors 300 may be provided, and both p-channel and n-channel types may be used.

[0338] The region where the channel of the semiconductor region 313 is formed, the region nearby, the low-resistance region 314a that serves as the source region or the drain region, and the low-resistance region 314b preferably contain a semiconductor such as a silicon-based semiconductor, and preferably contain single-crystal silicon. Alternatively, they may be formed of a material containing Ge (germanium), SiGe (silicon germanium), GaAs (gallium arsenide), GaAlAs (gallium aluminum arsenide), GaN (gallium nitride), or the like. A configuration using silicon in which the effective mass is controlled by applying stress to the crystal lattice and changing the lattice spacing may also be used. Alternatively, the transistor 300 may be a HEMT (High Electron Mobility Transistor) by using GaAs and GaAlAs, or the like.

[0339] The conductor 316 functioning as the gate electrode can be made of a conductive material such as a semiconductor material, metal material, alloy material, or metal oxide material, such as silicon containing an element that imparts n-type conductivity, such as arsenic or phosphorus, or an element that imparts p-type conductivity, such as boron.

[0340] Since the work function is determined by the material of the conductor, the threshold voltage of the transistor can be adjusted by selecting the material of the conductor. Specifically, it is preferable to use a material such as titanium nitride or tantalum nitride as the conductor. Furthermore, in order to achieve both conductivity and embeddability, it is preferable to use a metal material such as tungsten or aluminum as the conductor in a stacked structure, and tungsten is particularly preferable in terms of heat resistance.

[0341] The element isolation layer 312 is provided to isolate a plurality of transistors formed on the substrate 310. The element isolation layer can be formed by using, for example, a local oxidation of silicon (LOCOS) method, a shallow trench isolation (STI) method, a mesa isolation method, or the like.

[0342] 27 is just an example, and the structure of the transistor 300 is not limited to this example, and an appropriate transistor may be used depending on the circuit configuration, driving method, etc. For example, the transistor 300 may have a planar structure instead of a fin structure.

[0343] In the transistor 300 shown in FIG. 27, an insulator 320, an insulator 322, an insulator 324, and an insulator 326 are stacked in this order from the substrate 310 side.

[0344] The insulators 320, 322, 324, and 326 can be formed using, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0345] In this specification, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen, aluminum oxynitride refers to a material whose composition contains more oxygen than nitrogen, and aluminum nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0346] The insulator 322 may function as a planarizing film that flattens steps caused by the insulator 320 and the transistor 300 covered by the insulator 322. For example, the top surface of the insulator 322 may be planarized by planarization treatment using a chemical mechanical polishing (CMP) method or the like to improve flatness.

[0347] The insulator 324 is preferably a barrier insulating film that prevents diffusion of water, hydrogen, impurities, and the like from the substrate 310 or the transistor 300 to a region above the insulator 324 (e.g., a region where the transistor 500, the light-emitting devices 150a to 150c, and the like are provided). Therefore, the insulator 324 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, and water molecules (i.e., through which the impurities are less likely to permeate). Depending on the situation, the insulator 324 is preferably made of an insulating material that has a function of suppressing the diffusion of impurities such as nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (e.g., NO, NO, and the like), and copper atoms (i.e., through which the oxygen is less likely to permeate). Alternatively, the insulator 324 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, and the like).

[0348] An example of a film having a barrier property against hydrogen is silicon nitride formed by a chemical vapor deposition (CVD) method. Here, diffusion of hydrogen into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0349] The amount of desorption of hydrogen can be analyzed using, for example, thermal desorption spectroscopy (TDS). For example, the amount of desorption of hydrogen from the insulator 324 is calculated as 10×10 per area of ​​the insulator 324 when the surface temperature of the film is in the range of 50° C. to 500° C. in TDS analysis. 15 atoms / cm 2 Less than or equal to 5 x 10 15 atoms / cm 2 The following is fine.

[0350] It is preferable that the insulator 326 has a lower dielectric constant than the insulator 324. For example, the relative dielectric constant of the insulator 326 is preferably less than 4, and more preferably less than 3. Furthermore, for example, the relative dielectric constant of the insulator 326 is preferably 0.7 times or less, and more preferably 0.6 times or less, the relative dielectric constant of the insulator 324. By using a material with a low dielectric constant as the interlayer film, the parasitic capacitance that occurs between wirings can be reduced.

[0351] Furthermore, conductors 328, 330, etc., which connect to a light-emitting device or the like provided above the insulator 326, are embedded in the insulators 320, 322, 324, and 326. The conductors 328, 330, etc., function as plugs or wiring. Furthermore, for conductors that function as plugs or wiring, multiple structures may be collectively assigned the same reference numeral. Furthermore, in this specification, the wiring and the plug connecting to the wiring may be integrated. That is, there are cases where a portion of the conductor functions as wiring, and cases where a portion of the conductor functions as a plug.

[0352] The materials for each plug and wiring (conductor 328, conductor 330, etc.) can be a conductive material such as a metal material, an alloy material, a metal nitride material, or a metal oxide material, and can be used in a single layer or a stacked layer. It is preferable to use a high-melting-point material such as tungsten or molybdenum that has both heat resistance and conductivity, and tungsten is preferred. Alternatively, it is preferable to form the wiring from a low-resistance conductive material such as aluminum or copper. Using a low-resistance conductive material can reduce the wiring resistance.

[0353] A wiring layer may be provided over the insulator 326 and the conductor 330. For example, in FIG. 27 , an insulator 350, an insulator 352, and an insulator 354 are stacked in this order over the insulator 326 and the conductor 330. A conductor 356 is formed in the insulator 350, the insulator 352, and the insulator 354. The conductor 356 functions as a plug or wiring connected to the transistor 300. Note that the conductor 356 can be formed using a material similar to that of the conductor 328 and the conductor 330.

[0354] Note that, for example, the insulator 350 is preferably an insulator having a barrier property against impurities such as hydrogen and water, similar to the insulator 324. Similarly to the insulator 326, the insulators 352 and 354 are preferably insulators having a relatively low dielectric constant in order to reduce parasitic capacitance between wirings. The insulators 352 and 354 function as interlayer insulating films and planarizing films. The conductor 356 preferably includes a conductor having a barrier property against impurities such as hydrogen and water. In particular, a conductor having a barrier property against hydrogen is formed in the opening of the insulator 350 having a barrier property against hydrogen. With this structure, the transistor 300 and the transistor 500 can be separated by a barrier layer, thereby suppressing diffusion of hydrogen from the transistor 300 to the transistor 500.

[0355] Note that, for example, tantalum nitride or the like is preferably used as the conductor having a barrier property against hydrogen. Stacking tantalum nitride and highly conductive tungsten can suppress diffusion of hydrogen from the transistor 300 while maintaining the conductivity of the wiring. In this case, a structure in which the tantalum nitride layer having a barrier property against hydrogen is in contact with the insulator 350 having a barrier property against hydrogen is preferable.

[0356] In addition, an insulator 360, an insulator 362, and an insulator 364 are stacked in this order on the insulator 354 and the conductor 356.

[0357] The insulator 360 is preferably an insulator having barrier properties against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 360 can be made of, for example, a material that can be used for the insulator 324.

[0358] The insulators 362 and 364 function as an interlayer insulating film and a planarizing film. As the insulators 362 and 364, it is preferable to use an insulator that has a barrier property against impurities such as water and hydrogen, similar to the insulator 324. Therefore, the insulator 362 and / or the insulator 364 can be made of a material that can be used for the insulator 324.

[0359] Openings are formed in the insulators 360, 362, and 364 in regions that overlap with part of the conductor 356, and the conductor 366 is provided to fill the openings. The conductor 366 is also formed over the insulator 362. For example, the conductor 366 functions as a plug or a wiring connected to the transistor 300. Note that the conductor 366 can be formed using a material similar to that of the conductors 328 and 330.

[0360] An insulator 512 is provided over the insulator 364 and the conductor 366. A substance that has a barrier property against oxygen and hydrogen is preferably used for the insulator 512. The insulator 512 can be, for example, silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, aluminum nitride, or the like.

[0361] An example of a film having a barrier property against hydrogen is silicon nitride formed by a CVD method. Here, hydrogen diffusion into a semiconductor element having an oxide semiconductor, such as the transistor 500, may degrade the characteristics of the semiconductor element. Therefore, it is preferable to use a film that suppresses hydrogen diffusion between the transistor 500 and the transistor 300. Specifically, the film that suppresses hydrogen diffusion is a film that releases a small amount of hydrogen.

[0362] For example, the insulator 512 can be made of the same material as the insulator 320. By using a material with a relatively low dielectric constant for these insulators, the parasitic capacitance generated between wirings can be reduced. For example, the insulator 512 can be made of a silicon oxide film, a silicon oxynitride film, or the like.

[0363] Transistor 500, which is an OS transistor, is, for example, provided over an insulator 512.

[0364] The transistor 500 will now be described in detail. 28A and 28B show an example of the structure of the OS transistor 500. Note that FIG. 28A is a cross-sectional view of the OS transistor in the channel length direction, and FIG. 28B is a cross-sectional view of the OS transistor in the channel width direction.

[0365] As shown in FIGS. 28A and 28B, an insulator 514 and an insulator 516 are formed on the insulator 512.

[0366] The insulator 514 is preferably a film having a barrier property that prevents hydrogen and impurities from diffusing from the substrate 310 or a region where circuit elements and the like below the insulator 512 are provided to the region where the transistor 500 is provided. Therefore, the insulator 514 can be made of silicon nitride formed by a CVD method, for example.

[0367] The insulator 516 can be made of, for example, the same material as the insulator 512 .

[0368] As shown in FIGS. 28A and 28B, the transistor 500 includes an insulator 516 on an insulator 514, a conductor 503 (conductor 503a and conductor 503b) disposed so as to be embedded in the insulator 514 or the insulator 516, an insulator 522 on the insulator 516 and on the conductor 503, an insulator 524 on the insulator 522, an oxide 530a on the insulator 524, an oxide 530b on the oxide 530a, a conductor 542a on the oxide 530b, an insulator 571a on the conductor 542a, and an oxide 572a on the oxide 572b. conductor 542b on oxide 530b, insulator 571b on conductor 542b, insulator 552 on oxide 530b, insulator 550 on insulator 552, insulator 554 on insulator 550, conductor 560 (conductor 560a and conductor 560b) located on insulator 554 and overlapping part of oxide 530b, and insulator 544 arranged on insulator 522, insulator 524, oxide 530a, oxide 530b, conductor 542a, conductor 542b, insulator 571a, and insulator 571b. 28A and 28B , insulator 552 contacts the upper surface of insulator 522, the side surface of insulator 524, the side surface of oxide 530a, the side surface and upper surface of oxide 530b, the side surface of conductor 542, the side surface of insulator 571, the side surface of insulator 544, the side surface of insulator 580, and the lower surface of insulator 550. Furthermore, the upper surface of conductor 560 is disposed so as to be at approximately the same height as the upper surfaces of insulator 554, insulator 550, insulator 552, and insulator 580. Furthermore, insulator 574 contacts at least a portion of the upper surface of conductor 560, insulator 552, insulator 550, insulator 554, and insulator 580.

[0369] Openings reaching the oxide 530b are provided in the insulator 580 and the insulator 544. The insulator 552, the insulator 550, the insulator 554, and the conductor 560 are disposed in the openings. In addition, the conductor 560, the insulator 552, the insulator 550, and the insulator 554 are provided between the insulator 571a and the conductor 542a and between the insulator 571b and the conductor 542b in the channel length direction of the transistor 500. The insulator 554 has a region in contact with the side surface of the conductor 560 and a region in contact with the bottom surface of the conductor 560.

[0370] The oxide 530 preferably includes an oxide 530a disposed on the insulator 524 and an oxide 530b disposed on the oxide 530a. By providing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities from structures formed below the oxide 530a to the oxide 530b.

[0371] Note that although the transistor 500 has a structure in which the oxide 530 has two layers, the oxide 530a and the oxide 530b, the present invention is not limited to this. For example, the transistor 500 can have a single layer of the oxide 530b or a stacked structure of three or more layers. Alternatively, each of the oxide 530a and the oxide 530b can have a stacked structure.

[0372] The conductor 560 functions as a first gate (also simply referred to as a gate) electrode, and the conductor 503 functions as a second gate (also referred to as a back-gate) electrode. The insulators 552, 550, and 554 function as a first gate insulator, and the insulators 522 and 524 function as a second gate insulator. The gate insulators may also be referred to as a gate insulating layer or a gate insulating film. The conductor 542a functions as either a source or a drain, and the conductor 542b functions as the other. At least a part of a region of the oxide 530 that overlaps with the conductor 560 functions as a channel formation region.

[0373] FIG. 29A shows an enlarged view of the vicinity of the channel formation region in FIG. 28A. When oxygen is supplied to the oxide 530b, a channel formation region is formed in the region between the conductor 542a and the conductor 542b. Therefore, as shown in FIG. 29A, the oxide 530b includes a region 530bc that functions as the channel formation region of the transistor 500, and regions 530ba and 530bb that are provided on either side of the region 530bc and function as source and drain regions. At least a portion of the region 530bc overlaps with the conductor 560. In other words, the region 530bc is located in the region between the conductor 542a and the conductor 542b. The region 530ba overlaps with the conductor 542a, and the region 530bb overlaps with the conductor 542b.

[0374] The region 530bc, which functions as a channel formation region, has a smaller oxygen vacancy (in this specification, oxygen vacancy in a metal oxide is referred to as V) than the regions 530ba and 530bb. O The region 530bc is a high-resistance region with a low carrier concentration due to its low oxygen vacancy or low impurity concentration. Therefore, the region 530bc can be said to be i-type (intrinsic) or substantially i-type.

[0375] A transistor using a metal oxide has impurities or oxygen vacancies (V O ) may cause fluctuations in electrical characteristics and reduce reliability. O ) hydrogen near the oxygen vacancy (V O ) with hydrogen (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in the oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in the oxide semiconductor, impurities, oxygen vacancies, and V OIt is preferable that H is reduced as much as possible.

[0376] The regions 530ba and 530bb that function as source and drain regions have oxygen vacancies (V O ) or high concentrations of impurities such as hydrogen, nitrogen, and metal elements, resulting in an increased carrier concentration and low resistance. That is, the regions 530ba and 530bb are n-type regions with a higher carrier concentration and lower resistance than the region 530bc.

[0377] Here, the carrier concentration of the region 530bc that functions as a channel forming region is 1×10 18 cm -3 Preferably, it is 1×10 or less. 17 cm -3 More preferably, it is less than 1×10 16 cm -3 More preferably, it is less than 1×10 13 cm -3 More preferably, it is less than 1×10 12 cm -3 The lower limit of the carrier concentration of the region 530bc that functions as a channel formation region is not particularly limited, but is preferably, for example, 1×10 -9 cm -3 It can be said that:

[0378] A region having a carrier concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc may be formed between region 530bc and regions 530ba or 530bb. That is, this region functions as a junction region between region 530bc and regions 530ba or 530bb. The junction region may have a hydrogen concentration equal to or lower than that of regions 530ba and 530bb and equal to or higher than that of region 530bc. The junction region may also have oxygen vacancies equal to or lower than those of regions 530ba and 530bb and equal to or higher than those of region 530bc.

[0379] 29A shows an example in which the regions 530ba, 530bb, and 530bc are formed in the oxide 530b, but the present invention is not limited to this. For example, each of the above regions may be formed not only in the oxide 530b but also in the oxide 530a.

[0380] Furthermore, it may be difficult to clearly detect the boundaries between the regions in the oxide 530. The concentrations of metal elements and impurity elements such as hydrogen and nitrogen detected in each region may vary continuously within each region, rather than gradually varying from region to region. In other words, it is sufficient that the concentrations of metal elements and impurity elements such as hydrogen and nitrogen decrease in the region closer to the channel formation region.

[0381] In the transistor 500, the oxide 530 including the channel formation region (the oxide 530a and the oxide 530b) is preferably a metal oxide that functions as a semiconductor (hereinafter also referred to as an oxide semiconductor).

[0382] The metal oxide functioning as a semiconductor preferably has a band gap of 2 eV or more, preferably 2.5 eV or more. By using such a metal oxide with a wide band gap, the off-state current of the transistor can be reduced.

[0383] For example, a metal oxide such as In-M-Zn oxide containing indium, element M, and zinc (element M is one or more elements selected from aluminum, gallium, yttrium, tin, copper, vanadium, beryllium, boron, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, etc.) may be used as oxide 530. Alternatively, In-Ga oxide, In-Zn oxide, or indium oxide may be used as oxide 530.

[0384] Here, it is preferable that the atomic ratio of In to element M in the metal oxide used for oxide 530b is greater than the atomic ratio of In to element M in the metal oxide used for oxide 530a.

[0385] In this way, by disposing the oxide 530a below the oxide 530b, it is possible to suppress the diffusion of impurities and oxygen from the structure formed below the oxide 530a into the oxide 530b.

[0386] Furthermore, since the oxide 530a and the oxide 530b have a common element other than oxygen (as a main component), the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced. Because the defect state density at the interface between the oxide 530a and the oxide 530b can be reduced, the effect of interface scattering on carrier conduction is reduced, and a high on-current can be obtained.

[0387] The oxide 530b preferably has crystallinity, and in particular, it is preferable to use c-axis aligned crystalline oxide semiconductor (CAAC-OS) as the oxide 530b.

[0388] CAAC-OS has a highly crystalline and dense structure, and is free of impurities and defects (e.g., oxygen vacancies (V O ) is a metal oxide with little crystallinity. In particular, by subjecting the formed metal oxide to heat treatment at a temperature (for example, 400°C or higher and 600°C or lower) at which the metal oxide does not polycrystallize, the CAAC-OS can be made to have a dense structure with higher crystallinity. In this way, the density of the CAAC-OS can be increased, thereby further reducing the diffusion of impurities or oxygen in the CAAC-OS.

[0389] On the other hand, since it is difficult to identify clear grain boundaries in CAAC-OS, it is said that the decrease in electron mobility due to grain boundaries is unlikely to occur. Therefore, metal oxides with CAAC-OS have stable physical properties. As a result, metal oxides with CAAC-OS are heat-resistant and highly reliable.

[0390] In a transistor using an oxide semiconductor, if impurities and oxygen vacancies exist in a region where a channel is formed in the oxide semiconductor, the electrical characteristics are likely to fluctuate and the reliability may be reduced. In addition, hydrogen near the oxygen vacancies may be introduced into the oxygen vacancies (hereinafter referred to as V O H.) and generate electrons that serve as carriers. Therefore, if oxygen vacancies are present in the region where a channel is formed in an oxide semiconductor, the transistor is likely to have normally-on characteristics (a channel exists and current flows through the transistor even when no voltage is applied to the gate electrode). Therefore, in the region where a channel is formed in an oxide semiconductor, impurities, oxygen vacancies, and V O It is preferable that H is reduced as much as possible. In other words, it is preferable that the region in the oxide semiconductor where a channel is formed has a reduced carrier concentration and is i-type (intrinsic) or substantially i-type.

[0391] In response to this problem, an insulator containing oxygen that is released by heating (hereinafter may be referred to as excess oxygen) is provided near the oxide semiconductor, and heat treatment is performed to supply oxygen from the insulator to the oxide semiconductor, thereby eliminating oxygen vacancies and V O H can be reduced. However, if an excessive amount of oxygen is supplied to the source region or the drain region, this may cause a decrease in the on-state current or a decrease in the field-effect mobility of the transistor 500. Furthermore, if the amount of oxygen supplied to the source region or the drain region varies across the substrate surface, the characteristics of the semiconductor device having the transistor will vary.

[0392] Therefore, in the oxide semiconductor, the region 530bc that functions as a channel formation region preferably has a reduced carrier concentration and is i-type or substantially i-type, whereas the regions 530ba and 530bb that function as source and drain regions preferably have a high carrier concentration and are n-type. O It is preferable to reduce H so that an excessive amount of oxygen is not supplied to the regions 530ba and 530bb.

[0393] Therefore, in this embodiment, in a state where the conductors 542a and 542b are provided on the oxide 530b, microwave treatment is performed in an atmosphere containing oxygen to remove oxygen vacancies in the region 530bc and V O The microwave treatment here refers to a treatment using a device with a power source that generates high-density plasma using microwaves, for example.

[0394] By performing microwave processing in an atmosphere containing oxygen, oxygen gas can be converted into plasma using microwaves or high frequency waves such as RF, and the oxygen plasma can be activated. At this time, microwaves or high frequency waves such as RF can also be irradiated onto the region 530bc. The V of the region 530bc can be activated by the action of the plasma, microwaves, etc. O H is split off, hydrogen H is removed from the region 530bc, and oxygen vacancy V Ocan be compensated with oxygen. O H→H+V O This reaction occurs, and the hydrogen concentration in the region 530bc can be reduced. O H can be reduced to lower the carrier concentration.

[0395] Furthermore, when microwave processing is performed in an atmosphere containing oxygen, the effects of microwaves, high frequency waves such as RF, oxygen plasma, etc. are shielded by the conductors 542a and 542b and do not reach the regions 530ba and 530bb. Furthermore, the effects of oxygen plasma can be reduced by the insulators 571 and 580 that cover the oxide 530b and the conductor 542. As a result, during microwave processing, V O Since there is no reduction in H and no excessive supply of oxygen, it is possible to prevent a decrease in the carrier concentration.

[0396] Furthermore, it is preferable to perform microwave treatment in an oxygen-containing atmosphere after forming the insulating film that becomes the insulator 552 or after forming the insulating film that becomes the insulator 550. By performing microwave treatment in an oxygen-containing atmosphere through the insulator 552 or the insulator 550 in this manner, oxygen can be efficiently injected into the region 530bc. Furthermore, by arranging the insulator 552 so as to be in contact with the side surface of the conductor 542 and the surface of the region 530bc, injection of more oxygen than necessary into the region 530bc can be suppressed, thereby suppressing oxidation of the side surface of the conductor 542. Furthermore, oxidation of the side surface of the conductor 542 can be suppressed during formation of the insulating film that becomes the insulator 550.

[0397] The oxygen implanted into the region 530bc can be in various forms, such as oxygen atoms, oxygen molecules, or oxygen radicals (atoms, molecules, or ions with an unpaired electron, also known as O radicals). The oxygen implanted into the region 530bc preferably takes one or more of the above forms, and oxygen radicals are particularly preferred. This can improve the film quality of the insulators 552 and 550, thereby improving the reliability of the transistor 500.

[0398] In this way, oxygen vacancies and V are selectively formed in the oxide semiconductor region 530bc. O By removing H, the region 530bc can be made i-type or substantially i-type. Furthermore, the supply of excess oxygen to the regions 530ba and 530bb, which function as source and drain regions, can be prevented, maintaining the n-type state of the regions before microwave treatment. This suppresses fluctuations in the electrical characteristics of the transistor 500 and reduces variations in the electrical characteristics of the transistor 500 within the substrate surface.

[0399] By adopting the above-described configuration, it is possible to provide a semiconductor device with less variation in transistor characteristics, a highly reliable semiconductor device, and a semiconductor device with good electrical characteristics.

[0400] 28B, in a cross-sectional view of the transistor 500 in the channel width direction, a curved surface may be formed between the side surface of the oxide 530b and the top surface of the oxide 530b. That is, the end portions of the side surface and the top surface may be curved (hereinafter also referred to as rounded).

[0401] The radius of curvature of the curved surface is preferably greater than 0 nm and smaller than the film thickness of the oxide 530b in the region overlapping with the conductor 542, or smaller than half the length of the region not having the curved surface. Specifically, the radius of curvature of the curved surface is greater than 0 nm and smaller than 20 nm, preferably greater than 1 nm and smaller than 15 nm, and more preferably greater than 2 nm and smaller than 10 nm. This shape can improve the coverage of the oxide 530b with the insulators 552, 550, and 554, and the conductor 560.

[0402] The oxide 530 preferably has a stacked structure of multiple oxide layers with different chemical compositions. Specifically, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to the metal element that is the main component is preferably greater than the atomic ratio of the element M to the metal element that is the main component in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530a, the atomic ratio of the element M to In is preferably greater than the atomic ratio of the element M to In in the metal oxide used for the oxide 530b. Furthermore, in the metal oxide used for the oxide 530b, the atomic ratio of In to the element M is preferably greater than the atomic ratio of In to the element M in the metal oxide used for the oxide 530a.

[0403] The oxide 530b is preferably a crystalline oxide such as CAAC-OS. Crystalline oxides such as CAAC-OS have few impurities and defects (such as oxygen vacancies), and have a highly crystalline and dense structure. This can prevent the source or drain electrode from extracting oxygen from the oxide 530b. This can reduce the extraction of oxygen from the oxide 530b even during heat treatment, making the transistor 500 stable against high temperatures (so-called thermal budget) in the manufacturing process.

[0404] Here, the conduction band minimum changes gradually at the junction between the oxides 530a and 530b. In other words, the conduction band minimum at the junction between the oxides 530a and 530b changes continuously or forms a continuous junction. To achieve this, it is advisable to reduce the defect level density of the mixed layer formed at the interface between the oxides 530a and 530b.

[0405] Specifically, when the oxide 530a and the oxide 530b contain a common element other than oxygen as a main component, a mixed layer with a low density of defect states can be formed. For example, when the oxide 530b is an In-M-Zn oxide, the oxide 530a may be an In-M-Zn oxide, an M-Zn oxide, an oxide of element M, an In-Zn oxide, an indium oxide, or the like.

[0406] Specifically, oxide 530a may be a metal oxide having an atomic ratio of In:M:Zn=1:3:4 or a similar composition, or an atomic ratio of In:M:Zn=1:1:0.5 or a similar composition. Oxide 530b may be a metal oxide having an atomic ratio of In:M:Zn=1:1:1 or a similar composition, or an atomic ratio of In:M:Zn=4:2:3 or a similar composition. Note that a similar composition includes a range of ±30% of the desired atomic ratio. Gallium is preferably used as element M.

[0407] When a metal oxide film is formed by sputtering, the atomic ratio is not limited to the atomic ratio of the formed metal oxide film, but may be the atomic ratio of a sputtering target used to form the metal oxide film.

[0408] 28A and other figures, providing an insulator 552 made of aluminum oxide or the like in contact with the top and side surfaces of the oxide 530 can cause indium in the oxide 530 to be unevenly distributed at and near the interface between the oxide 530 and the insulator 552. This results in an atomic ratio near the surface of the oxide 530 that is close to that of indium oxide or In-Zn oxide. The increased atomic ratio of indium near the surface of the oxide 530, particularly the oxide 530b, can improve the field-effect mobility of the transistor 500.

[0409] The oxide 530a and the oxide 530b have the above-described structure, which can reduce the defect state density at the interface between the oxide 530a and the oxide 530b. As a result, the influence of interface scattering on carrier conduction is reduced, and the transistor 500 can achieve a large on-state current and high frequency characteristics.

[0410] At least one of the insulators 512, 514, 544, 571, 574, 576, and 581 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from the substrate side or from above the transistor 500 into the transistor 500. Therefore, at least one of the insulators 512, 514, 544, 571, 574, 576, and 581 is preferably made of an insulating material that suppresses diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (such as NO, NO, and NO), and copper atoms (i.e., through which the above impurities are less likely to permeate). Alternatively, it is preferably made of an insulating material that suppresses diffusion of oxygen (e.g., at least one of oxygen atoms and oxygen molecules) (i.e., through which the above oxygen is less likely to permeate).

[0411] For the insulators 512, 514, 544, 571, 574, 576, and 581, it is preferable to use an insulator that has the function of suppressing diffusion of oxygen and impurities such as water and hydrogen. For example, aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium-gallium-zinc oxide, silicon nitride, or silicon nitride oxide can be used. For example, silicon nitride, which has a high hydrogen barrier property, is preferably used for the insulators 512, 544, and 576. Furthermore, for example, aluminum oxide or magnesium oxide, which has a high ability to capture and fix hydrogen, is preferably used for the insulators 514, 571, 574, and 581. This can suppress diffusion of impurities such as water and hydrogen from the substrate side to the transistor 500 side through the insulators 512 and 514. Alternatively, impurities such as water and hydrogen can be prevented from diffusing toward the transistor 500 from an interlayer insulating film disposed outside the insulator 581. Alternatively, oxygen contained in the insulator 524 and the like can be prevented from diffusing toward the substrate through the insulators 512 and 514. Alternatively, oxygen contained in the insulator 580 and the like can be prevented from diffusing upward from the transistor 500 through the insulator 574. In this way, the transistor 500 is preferably surrounded by the insulators 512, 514, 571, 544, 574, 576, and 581, which have the function of preventing the diffusion of impurities such as water and hydrogen and oxygen.

[0412] Here, it is preferable to use an oxide having an amorphous structure as the insulators 512, 514, 544, 571, 574, 576, and 581. For example, AlO x (x is any number greater than 0), or MgO yIt is preferable to use a metal oxide such as y (where y is any number greater than 0). In such metal oxides having an amorphous structure, oxygen atoms have dangling bonds, and the dangling bonds may have the property of capturing or fixing hydrogen. By using such a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, hydrogen contained in the transistor 500 or hydrogen present around the transistor 500 can be captured or fixed. In particular, it is preferable to capture or fix hydrogen contained in the channel formation region of the transistor 500. By using a metal oxide having an amorphous structure as a component of the transistor 500 or providing it around the transistor 500, a highly reliable transistor 500 and semiconductor device can be manufactured with excellent characteristics.

[0413] Furthermore, the insulators 512, 514, 544, 571, 574, 576, and 581 preferably have an amorphous structure, but may have a polycrystalline structure in part. The insulators 512, 514, 544, 571, 574, 576, and 581 may have a multilayer structure in which an amorphous layer and a polycrystalline layer are stacked. For example, they may have a stacked structure in which a polycrystalline layer is formed on an amorphous layer.

[0414] The insulators 512, 514, 544, 571, 574, 576, and 581 can be formed by, for example, a sputtering method. Sputtering does not require the use of hydrogen-containing molecules in a film formation gas, and therefore can reduce the hydrogen concentrations of the insulators 512, 514, 544, 571, 574, 576, and 581. Note that the film formation method is not limited to sputtering, and a chemical vapor deposition (CVD) method, a molecular beam epitaxy (MBE) method, a pulsed laser deposition (PLD) method, an atomic layer deposition (ALD) method, or the like may also be used as appropriate.

[0415] It may also be desirable to reduce the resistivity of insulators 512, 544, and 576. For example, it may be desirable to reduce the resistivity of insulators 512, 544, and 576 to approximately 1×10 13 By setting the resistivity to Ωcm, the insulators 512, 544, and 576 may be able to reduce charge-up of the conductors 503, 542, and 560 during treatment using plasma or the like in the manufacturing process of a semiconductor device. The resistivity of the insulators 512, 544, and 576 is preferably 1×10 10 Ωcm or more 1×10 15 Ωcm or less.

[0416] The insulators 516, 574, 580, and 581 preferably have a lower dielectric constant than the insulator 514. Using a material with a low dielectric constant as an interlayer film can reduce parasitic capacitance between wirings. For example, silicon oxide, silicon oxynitride, silicon oxide to which fluorine is added, silicon oxide to which carbon is added, silicon oxide to which carbon and nitrogen are added, silicon oxide having vacancies, or the like can be used as appropriate for the insulators 516, 580, and 581.

[0417] For example, the insulator 581 is preferably an insulator that functions as an interlayer film, a planarizing film, or the like.

[0418] The conductor 503 is arranged to overlap the oxide 530 and the conductor 560. Here, the conductor 503 is preferably provided by being embedded in an opening formed in the insulator 516. In addition, a part of the conductor 503 may be embedded in the insulator 514.

[0419] The conductor 503 includes a conductor 503a and a conductor 503b. The conductor 503a is provided in contact with the bottom surface and sidewall of the opening. The conductor 503b is provided so as to be embedded in a recess formed in the conductor 503a. Here, the height of the top of the conductor 503b is approximately the same as the height of the top of the conductor 503a and the height of the top of the insulator 516.

[0420] Here, the conductor 503a is preferably made of a conductive material that has the function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules (NO, NO, NO, etc.), copper atoms, etc. Alternatively, it is preferably made of a conductive material that has the function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0421] By using a conductive material that can reduce hydrogen diffusion for the conductor 503a, it is possible to prevent impurities such as hydrogen contained in the conductor 503b from diffusing into the oxide 530 via the insulator 524 or the like. Furthermore, by using a conductive material that can suppress oxygen diffusion for the conductor 503a, it is possible to prevent the conductor 503b from being oxidized and its conductivity from decreasing. Examples of conductive materials that can suppress oxygen diffusion include titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, and ruthenium oxide. Therefore, the conductor 503a may be a single layer or a multilayer of the above conductive materials. For example, the conductor 503a may be made of titanium nitride.

[0422] The conductor 503b is preferably made of a conductive material containing tungsten, copper, or aluminum as a main component, for example, tungsten.

[0423] The conductor 503 may function as a second gate electrode. In this case, the threshold voltage (Vth) of the transistor 500 can be controlled by changing the potential applied to the conductor 503 independently of the potential applied to the conductor 560. In particular, applying a negative potential to the conductor 503 can increase the Vth of the transistor 500 and reduce its off-state current. Therefore, applying a negative potential to the conductor 503 can reduce the drain current when the potential applied to the conductor 560 is 0 V compared to not applying a negative potential to the conductor 503.

[0424] Note that if the oxide 530 is highly pure and intrinsic, and impurities are removed from the oxide 530 as much as possible, it may be possible to make the transistor 500 normally off (to make the threshold voltage of the transistor 500 higher than 0 V) ​​without applying a potential to the conductor 503 and / or the conductor 560. In this case, it is preferable to connect the conductor 560 and the conductor 503 so that the same potential is applied to them.

[0425] The electrical resistivity of the conductor 503 is designed taking into consideration the potential applied to the conductor 503, and the film thickness of the conductor 503 is set to match this electrical resistivity. The film thickness of the insulator 516 is approximately the same as that of the conductor 503. Here, it is preferable to make the film thicknesses of the conductor 503 and the insulator 516 as thin as possible within the range permitted by the design of the conductor 503. By making the film thickness of the insulator 516 thin, the absolute amount of impurities such as hydrogen contained in the insulator 516 can be reduced, thereby reducing the diffusion of the impurities into the oxide 530.

[0426] Note that the conductor 503 is preferably larger than the area of ​​the oxide 530 that does not overlap with the conductors 542a and 542b when viewed from above. In particular, as shown in FIG. 28B , the conductor 503 preferably extends to an area outside the channel width direction ends of the oxides 530a and 530b. That is, outside the side surfaces of the oxide 530 in the channel width direction, the conductor 503 and the conductor 560 preferably overlap with each other via an insulator. With this structure, the channel formation region of the oxide 530 can be electrically surrounded by the electric field of the conductor 560, which functions as the first gate electrode, and the electric field of the conductor 503, which functions as the second gate electrode. In this specification, a transistor structure in which the channel formation region is electrically surrounded by the electric fields of the first and second gates is referred to as a surrounded channel (S-channel) structure.

[0427] In this specification and the like, a transistor with an S-channel structure refers to a transistor structure in which a channel formation region is electrically surrounded by the electric fields of one and the other of a pair of gate electrodes. The S-channel structure disclosed in this specification and the like differs from a fin structure and a planar structure. By adopting the S-channel structure, the transistor can be made more resistant to the short-channel effect, in other words, less susceptible to the short-channel effect.

[0428] By configuring the transistor 500 as a normally-off transistor and adopting the above-described S-Channel structure, the channel formation region can be electrically surrounded. Therefore, the transistor 500 can also be considered to have a GAA (Gate All Around) structure or an LGAA (Lateral Gate All Around) structure. By configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the channel formation region formed at or near the interface between the oxide 530 and the gate insulating film can be the entire bulk of the oxide 530. In other words, by configuring the transistor 500 as an S-Channel structure, a GAA structure, or an LGAA structure, the entire bulk can be used as a carrier path, making it a so-called bulk-flow type. The bulk-flow type transistor structure can increase the current density flowing through the transistor, which is expected to improve the on-state current or field-effect mobility of the transistor.

[0429] 28B, the conductor 503 is extended to function as a wiring. However, the present invention is not limited to this, and a conductor functioning as a wiring may be provided below the conductor 503. Furthermore, it is not necessary to provide one conductor 503 for each transistor. For example, the conductor 503 may be shared by multiple transistors.

[0430] Note that although the conductor 503 in the transistor 500 has a stacked structure of the conductor 503a and the conductor 503b, the present invention is not limited to this. For example, the conductor 503 may have a single layer structure or a stacked structure of three or more layers.

[0431] Insulator 522 and insulator 524 function as gate insulators.

[0432] The insulator 522 preferably has a function of suppressing the diffusion of hydrogen (e.g., at least one of hydrogen atoms, hydrogen molecules, etc.). The insulator 522 preferably has a function of suppressing the diffusion of oxygen (e.g., at least one of oxygen atoms, oxygen molecules, etc.). For example, the insulator 522 preferably has a function of suppressing the diffusion of one or both of hydrogen and oxygen more than the insulator 524.

[0433] The insulator 522 may be an insulator containing an oxide of one or both of aluminum and hafnium, which are insulating materials. Aluminum oxide, hafnium oxide, or an oxide containing aluminum and hafnium (hafnium aluminate) is preferably used as the insulator. When the insulator 522 is formed using such a material, the insulator 522 functions as a layer that suppresses oxygen release from the oxide 530 to the substrate and diffusion of impurities such as hydrogen from the periphery of the transistor 500 to the oxide 530. Therefore, the insulator 522 can suppress diffusion of impurities such as hydrogen into the transistor 500 and suppress generation of oxygen vacancies in the oxide 530. Furthermore, reaction of the conductor 503 with oxygen contained in the insulator 524 or the oxide 530 can be suppressed.

[0434] Alternatively, the insulator may contain, for example, aluminum oxide, bismuth oxide, germanium oxide, niobium oxide, silicon oxide, titanium oxide, tungsten oxide, yttrium oxide, or zirconium oxide. Alternatively, these insulators may be nitrided. Furthermore, the insulator 522 may be formed by stacking silicon oxide, silicon oxynitride, or silicon nitride on these insulators.

[0435] The insulator 522 may be a single layer or a multilayer of an insulator containing a so-called high-k material, such as aluminum oxide, hafnium oxide, tantalum oxide, or zirconium oxide. As transistors become smaller and more highly integrated, thinning of the gate insulator can lead to problems such as leakage current. Using a high-k material as the gate insulator can reduce the gate potential during transistor operation while maintaining the physical film thickness. Alternatively, the insulator 522 may be made of a material with a high dielectric constant, such as lead zirconate titanate (PZT), strontium titanate (SrTiO3), or (Ba,Sr)TiO3 (BST).

[0436] The insulator 524 in contact with the oxide 530 can be made of, for example, silicon oxide, silicon oxynitride, or the like as appropriate.

[0437] During the manufacturing process of the transistor 500, heat treatment is preferably performed with the surface of the oxide 530 exposed. The heat treatment may be performed, for example, at a temperature of 100° C. to 600° C., more preferably 350° C. to 550° C. Note that the heat treatment is performed in a nitrogen gas or inert gas atmosphere, or an atmosphere containing an oxidizing gas at 10 ppm or more, 1% or more, or 10% or more. For example, the heat treatment is preferably performed in an oxygen atmosphere. This supplies oxygen to the oxide 530, thereby eliminating oxygen vacancies (V O ) can be reduced. The heat treatment may be performed under reduced pressure. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas after the heat treatment in a nitrogen gas or inert gas atmosphere to compensate for the desorbed oxygen. Alternatively, the heat treatment may be performed in an atmosphere containing 10 ppm or more, 1% or more, or 10% or more of an oxidizing gas, and then the heat treatment may be performed in a nitrogen gas or inert gas atmosphere.

[0438] By subjecting the oxide 530 to oxygen addition treatment, oxygen vacancies in the oxide 530 are repaired by the supplied oxygen. In other words, OFurthermore, the reaction of the hydrogen remaining in the oxide 530 with the supplied oxygen can be removed as HO (dehydration). As a result, the hydrogen remaining in the oxide 530 recombines with the oxygen vacancies to form V O The formation of H can be suppressed.

[0439] The insulators 522 and 524 may each have a stacked structure of two or more layers. In this case, the stacked structure is not limited to a stacked structure made of the same material, and may be a stacked structure made of different materials. The insulator 524 may be formed in an island shape overlapping the oxide 530a. In this case, the insulator 544 is configured to contact the side surface of the insulator 524 and the top surface of the insulator 522.

[0440] The conductor 542a and the conductor 542b are provided in contact with the top surface of the oxide 530b. The conductor 542a and the conductor 542b function as a source electrode and a drain electrode of the transistor 500, respectively.

[0441] As the conductor 542 (conductor 542a and conductor 542b), for example, a nitride containing tantalum, a nitride containing titanium, a nitride containing molybdenum, a nitride containing tungsten, a nitride containing tantalum and aluminum, or a nitride containing titanium and aluminum is preferably used. In one embodiment of the present invention, a nitride containing tantalum is particularly preferable. Also, for example, ruthenium oxide, ruthenium nitride, an oxide containing strontium and ruthenium, or an oxide containing lanthanum and nickel may be used. These materials are preferable because they are conductive materials that are resistant to oxidation or that maintain conductivity even when absorbing oxygen.

[0442] Note that hydrogen contained in the oxide 530b and the like may diffuse into the conductor 542a or the conductor 542b. In particular, by using a nitride containing tantalum for the conductors 542a and 542b, hydrogen contained in the oxide 530b and the like is likely to diffuse into the conductor 542a or the conductor 542b, and the diffused hydrogen may bond with nitrogen contained in the conductor 542a or the conductor 542b. In other words, hydrogen contained in the oxide 530b and the like may be absorbed by the conductor 542a or the conductor 542b.

[0443] Furthermore, it is preferable that no curved surface be formed between the side surface of the conductor 542 and the top surface of the conductor 542. The conductor 542 without such a curved surface can increase the cross-sectional area of ​​the conductor 542 in the cross section in the channel width direction. This can increase the conductivity of the conductor 542 and the on-state current of the transistor 500.

[0444] The insulator 571a is provided in contact with the top surface of the conductor 542a, and the insulator 571b is provided in contact with the top surface of the conductor 542b. The insulator 571 preferably functions as a barrier insulating film against oxygen. Therefore, the insulator 571 preferably has a function of suppressing oxygen diffusion. For example, the insulator 571 preferably has a function of suppressing oxygen diffusion more than the insulator 580. The insulator 571 may be, for example, a nitride containing silicon, such as silicon nitride. The insulator 571 preferably has a function of capturing impurities such as hydrogen. In this case, the insulator 571 may be an insulator of a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. In particular, using aluminum oxide having an amorphous structure or aluminum oxide having an amorphous structure as the insulator 571 is preferable because hydrogen can be more effectively captured or fixed. This enables the manufacture of a highly reliable transistor 500 and a semiconductor device with favorable characteristics.

[0445] The insulator 544 is provided to cover the insulator 524, the oxide 530a, the oxide 530b, the conductor 542, and the insulator 571. The insulator 544 preferably has a function of capturing and fixing hydrogen. In this case, the insulator 544 preferably includes an insulator such as silicon nitride or a metal oxide having an amorphous structure, such as aluminum oxide or magnesium oxide. Alternatively, for example, the insulator 544 may be a stacked film of aluminum oxide and silicon nitride on the aluminum oxide.

[0446] By providing the insulator 571 and the insulator 544 as described above, the conductor 542 can be surrounded by an insulator having a barrier property against oxygen. That is, oxygen contained in the insulator 524 and the insulator 580 can be prevented from diffusing into the conductor 542. This can prevent the conductor 542 from being directly oxidized by the oxygen contained in the insulator 524 and the insulator 580, which increases the resistivity and reduces the on-state current.

[0447] The insulator 552 functions as part of the gate insulator. The insulator 552 is preferably a barrier insulating film against oxygen. Any of the insulators that can be used for the insulator 574 described above can be used as the insulator 552. The insulator 552 can be an insulator containing one or both of an oxide of aluminum and hafnium. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, aluminum oxide is used as the insulator 552. In this case, the insulator 552 contains at least oxygen and aluminum.

[0448] As shown in FIG. 28B, the insulator 552 is provided in contact with the top surface and side surfaces of the oxide 530b, the side surfaces of the oxide 530a, the side surfaces of the insulator 524, and the top surface of the insulator 522. That is, the regions of the oxide 530a, the oxide 530b, and the insulator 524 that overlap with the conductor 560 are covered with the insulator 552 in the cross section in the channel width direction. This allows the insulator 552, which has oxygen barrier properties, to block oxygen from being released from the oxides 530a and 530b during heat treatment or the like. This reduces the formation of oxygen vacancies (Vo) in the oxides 530a and 530b. This reduces the oxygen vacancies (Vo) and V formed in the region 530bc. O H can be reduced. Therefore, the electrical characteristics of the transistor 500 can be improved, and the reliability can be improved.

[0449] Conversely, even if the insulator 580, the insulator 550, or the like contains excessive amounts of oxygen, the oxygen can be prevented from being excessively supplied to the oxide 530a and the oxide 530b. Therefore, the region 530bc can prevent the regions 530ba and 530bb from being excessively oxidized, which would cause a decrease in the on-state current or the field-effect mobility of the transistor 500.

[0450] 28A , the insulator 552 is provided in contact with the side surfaces of the conductor 542, the insulator 544, the insulator 571, and the insulator 580. This reduces the oxidation of the side surface of the conductor 542 and the formation of an oxide film on the side surface. This reduces the on-state current or field-effect mobility of the transistor 500.

[0451] The insulator 552, together with the insulator 554, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 552 preferably has a small thickness. The thickness of the insulator 552 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 1.0 nm or less, 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 552 only needs to have at least a region with the above-described thickness. The thickness of the insulator 552 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 552 only needs to have at least a region with a thickness thinner than the insulator 550.

[0452] To deposit the insulator 552 to a thin thickness as described above, it is preferable to use the ALD method. The ALD method alternately introduces a first source gas (also called a precursor, precursor, or metal precursor) and a second source gas (also called a reactant, reactant, oxidizer, or non-metal precursor) for the reaction into a chamber, and then repeats the introduction of these source gases to deposit the film. ALD methods include thermal ALD, in which the reaction between the precursor and the reactant is carried out using only thermal energy, and PEALD (Plasma Enhanced ALD), which uses plasma-excited reactants. The PEALD method may be preferable because it utilizes plasma, which allows film deposition at lower temperatures.

[0453] The ALD method utilizes the self-regulating property of atoms and can deposit atoms one layer at a time, which has the advantages of enabling ultrathin film formation, film formation on structures with high aspect ratios, film formation with few defects such as pinholes, film formation with excellent coverage, film formation at low temperatures, etc. Therefore, the insulator 552 can be formed with good coverage on the side surfaces of an opening formed in the insulator 580 or the like and with the thin film thickness described above.

[0454] Some precursors used in ALD contain carbon and other impurities. Therefore, films formed by ALD may contain more carbon and other impurities than films formed by other film formation methods. Quantitative determination of impurities can be performed using secondary ion mass spectrometry (SIMS) or X-ray photoelectron spectroscopy (XPS).

[0455] The insulator 550 functions as part of the gate insulator. The insulator 550 is preferably disposed in contact with the upper surface of the insulator 552. The insulator 550 can be made of silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, silicon oxide doped with fluorine, silicon oxide doped with carbon, silicon oxide doped with carbon and nitrogen, silicon oxide having vacancies, or the like. Silicon oxide and silicon oxynitride are particularly preferred because they are stable against heat. In this case, the insulator 550 is an insulator containing at least oxygen and silicon.

[0456] Like the insulator 524, the insulator 550 preferably has a reduced concentration of impurities such as water and hydrogen. The thickness of the insulator 550 preferably has a lower limit of 1 nm or 0.5 nm and an upper limit of 15 nm or 20 nm. Note that the above-mentioned lower and upper limits can be combined. For example, the thickness of the insulator 550 is preferably 0.5 nm or more and 20 nm or less, and more preferably 1 nm or more and 15 nm or less. In this case, the insulator 550 only needs to have a region with the above-mentioned thickness in at least a portion thereof.

[0457] 28A and 28B show a configuration in which insulator 550 is a single layer, but the present invention is not limited to this and may have a laminated structure of two or more layers. For example, as shown in Fig. 29B, insulator 550 may have a two-layer laminated structure of insulator 550a and insulator 550b on insulator 550a.

[0458] As shown in FIG. 29B , when the insulator 550 has a two-layer stacked structure, the lower insulator 550a is preferably formed using an insulator that easily transmits oxygen, and the upper insulator 550b is preferably formed using an insulator that suppresses oxygen diffusion. This structure can suppress the diffusion of oxygen contained in the insulator 550a into the conductor 560. That is, it can suppress a decrease in the amount of oxygen supplied to the oxide 530. It can also suppress oxidation of the conductor 560 due to the oxygen contained in the insulator 550a. For example, the insulator 550a may be formed using a material that can be used for the insulator 550 described above, and the insulator 550b may be formed using an insulator containing one or both of aluminum and hafnium oxides. Examples of the insulator that can be used include aluminum oxide, hafnium oxide, an oxide containing aluminum and hafnium (hafnium aluminate), and an oxide containing hafnium and silicon (hafnium silicate). In this embodiment, hafnium oxide is used as the insulator 550b. In this case, the insulator 550b contains at least oxygen and hafnium. The thickness of the insulator 550b is preferably 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. The above-mentioned lower and upper limits can be combined. In this case, the insulator 550b only needs to have a region with the above-mentioned thickness in at least a portion.

[0459] When silicon oxide, silicon oxynitride, or the like is used for the insulator 550a, the insulator 550b may be an insulating material, such as a high-k material with a high dielectric constant. By forming the gate insulator as a layered structure of the insulators 550a and 550b, a layered structure that is thermally stable and has a high dielectric constant can be achieved. This allows the gate potential applied during transistor operation to be reduced while maintaining the physical thickness of the gate insulator. Furthermore, the equivalent oxide thickness (EOT) of the insulator functioning as the gate insulator can be reduced. This allows the dielectric strength of the insulator 550 to be increased.

[0460] The insulator 554 functions as part of the gate insulator. A barrier insulating film against hydrogen is preferably used as the insulator 554. This can prevent impurities such as hydrogen contained in the conductor 560 from diffusing into the insulator 550 and the oxide 530b. The insulator 554 can be any of the insulators that can be used for the insulator 576. For example, silicon nitride formed by a PEALD method can be used as the insulator 554. In this case, the insulator 554 contains at least nitrogen and silicon.

[0461] The insulator 554 may further have a barrier property against oxygen, which can prevent oxygen contained in the insulator 550 from diffusing into the conductor 560.

[0462] The insulator 554, together with the insulator 552, the insulator 550, and the conductor 560, needs to be provided in an opening formed in the insulator 580 or the like. To miniaturize the transistor 500, the insulator 554 preferably has a small thickness. The thickness of the insulator 554 is preferably 0.1 nm or more, 0.5 nm or more, or 1.0 nm or more, and preferably 3.0 nm or less, or 5.0 nm or less. Note that the above-described lower and upper limits can be combined. In this case, the insulator 554 only needs to have at least a region with the above-described thickness. The thickness of the insulator 554 is preferably thinner than the thickness of the insulator 550. In this case, the insulator 554 only needs to have at least a region with a thickness thinner than the insulator 550.

[0463] The conductor 560 functions as a first gate electrode of the transistor 500. The conductor 560 preferably includes a conductor 560a and a conductor 560b disposed over the conductor 560a. For example, the conductor 560a is preferably disposed so as to surround the bottom and side surfaces of the conductor 560b. As shown in FIGS. 28A and 28B, the height of the top surface of the conductor 560 roughly coincides with the height of the top of the insulator 550. Note that although the conductor 560 is shown as having a two-layer structure of the conductor 560a and the conductor 560b in FIGS. 28A and 28B, the conductor 560 may have a single-layer structure or a stacked structure of three or more layers other than the two-layer structure.

[0464] The conductor 560a is preferably made of a conductive material that has a function of suppressing the diffusion of impurities such as hydrogen atoms, hydrogen molecules, water molecules, nitrogen atoms, nitrogen molecules, nitrogen oxide molecules, copper atoms, etc. Alternatively, it is preferably made of a conductive material that has a function of suppressing the diffusion of oxygen (for example, at least one of oxygen atoms, oxygen molecules, etc.).

[0465] Furthermore, since conductor 560a has the function of suppressing oxygen diffusion, it is possible to suppress a decrease in conductivity due to oxidation of conductor 560b caused by oxygen contained in insulator 550. As a conductive material having the function of suppressing oxygen diffusion, it is preferable to use, for example, titanium, titanium nitride, tantalum, tantalum nitride, ruthenium, ruthenium oxide, or the like.

[0466] Furthermore, since the conductor 560 also functions as wiring, it is preferable to use a conductor with high conductivity. For example, the conductor 560b can be a conductive material containing tungsten, copper, or aluminum as a main component. The conductor 560b can have a layered structure. Specifically, for example, the conductor 560b can have a layered structure of titanium or titanium nitride and the above conductive material.

[0467] Furthermore, in the transistor 500, the conductor 560 is formed in a self-aligned manner so as to fill an opening formed in the insulator 580 or the like. By forming the conductor 560 in this manner, the conductor 560 can be reliably placed in the region between the conductor 542a and the conductor 542b without alignment.

[0468] 28B , in the channel width direction of the transistor 500, the height of the bottom surface of the conductor 560 in a region where the conductor 560 does not overlap with the oxide 530b is preferably lower than the height of the bottom surface of the oxide 530b when the bottom surface of the insulator 522 is used as the reference. When the conductor 560, which functions as a gate electrode, covers the side and top surfaces of the channel formation region of the oxide 530b via the insulator 550 or the like, the electric field of the conductor 560 can be easily applied to the entire channel formation region of the oxide 530b. Therefore, the on-state current of the transistor 500 can be increased, and the frequency characteristics can be improved. The difference between the height of the bottom surface of conductor 560 and the height of the bottom surface of oxide 530b in the region where oxide 530a and oxide 530b do not overlap with conductor 560, relative to the bottom surface of insulator 522, is preferably 0 nm or more, 3 nm or more, or 5 nm or more, and is preferably 20 nm or less, 50 nm or less, or 100 nm or less. Note that the above-mentioned lower limit and upper limit values ​​can be combined with each other.

[0469] The insulator 580 is provided on the insulator 544, and openings are formed in the regions where the insulator 550 and the conductor 560 are to be provided. The top surface of the insulator 580 may be planarized.

[0470] The insulator 580, which functions as an interlayer film, preferably has a low dielectric constant. Using a material with a low dielectric constant as the interlayer film can reduce parasitic capacitance between wirings. The insulator 580 is preferably formed using, for example, the same material as the insulator 516. In particular, silicon oxide and silicon oxynitride are preferred because they are thermally stable. In particular, materials such as silicon oxide, silicon oxynitride, and silicon oxide with vacancies are preferred because they can easily form a region containing oxygen that is released by heating.

[0471] The insulator 580 preferably has a low concentration of impurities such as water and hydrogen. For example, the insulator 580 may be formed using an oxide containing silicon, such as silicon oxide or silicon oxynitride, as appropriate.

[0472] The insulator 574 preferably functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580 and preferably has a function of capturing impurities such as hydrogen. The insulator 574 also preferably functions as a barrier insulating film that suppresses oxygen permeation. The insulator 574 may be an insulator made of a metal oxide having an amorphous structure, such as aluminum oxide. In this case, the insulator 574 contains at least oxygen and aluminum. By providing the insulator 574, which is in contact with the insulator 580 and has a function of capturing impurities such as hydrogen, in the region between the insulators 512 and 581, the insulator 574 can capture impurities such as hydrogen contained in the insulator 580 and maintain a constant amount of hydrogen in the region. In particular, using aluminum oxide having an amorphous structure as the insulator 574 is preferable because it may be able to more effectively capture or fix hydrogen. This enables the manufacture of a highly reliable transistor 500 and semiconductor device with excellent characteristics.

[0473] The insulator 576 functions as a barrier insulating film that suppresses diffusion of impurities such as water and hydrogen from above into the insulator 580. The insulator 576 is disposed over the insulator 574. The insulator 576 is preferably a nitride containing silicon, such as silicon nitride or silicon nitride oxide. For example, the insulator 576 may be formed using silicon nitride deposited by a sputtering method. A high-density silicon nitride film can be formed by depositing the insulator 576 by a sputtering method. Alternatively, the insulator 576 may be formed by stacking a silicon nitride film deposited by a PEALD method or a CVD method on the silicon nitride film deposited by a sputtering method.

[0474] One of the first and second terminals of the transistor 500 is electrically connected to a conductor 540a that functions as a plug, and the other of the first and second terminals of the transistor 500 is electrically connected to a conductor 540b. Note that the conductors 540a, 540b, and the like may function as wiring for electrically connecting to an upper light-emitting device 150 or the like. In the case of the display device 10 of FIG. 27, the conductors 540a, 540b, and the like may also function as wiring for electrically connecting to the transistor 300 or the like. Note that in this specification and the like, the conductors 540a and 540b will be collectively referred to as the conductor 540.

[0475] For example, conductor 540a is provided in a region overlapping with conductor 542a. Specifically, in the region overlapping with conductor 542a, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 28A , and conductor 540a is provided inside the openings. For example, conductor 540b is provided in a region overlapping with conductor 542b. Specifically, in the region overlapping with conductor 542b, openings are formed in insulators 571, 544, 580, 574, 576, and 581 shown in FIG. 28A , and conductor 540b is provided inside the openings.

[0476] 28A, an insulator 541a may be provided as an insulator having barrier properties against impurities between the conductor 540a and a side surface of the opening in a region overlapping with the conductor 542a. Similarly, an insulator 541b may be provided as an insulator having barrier properties against impurities between the conductor 540b and a side surface of the opening in a region overlapping with the conductor 542b. Note that in this specification and the like, the insulators 541a and 541b are collectively referred to as the insulator 541.

[0477] The conductors 540a and 540b are preferably made of a conductive material containing tungsten, copper, or aluminum as a main component. The conductors 540a and 540b may have a layered structure.

[0478] Furthermore, when the conductor 540 has a layered structure, it is preferable to use a conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen for the insulators 574, 576, 581, 580, 544, and the first conductor disposed near the insulator 571. For example, it is preferable to use tantalum, tantalum nitride, titanium, titanium nitride, ruthenium, ruthenium oxide, or the like. Furthermore, the conductive material that has the function of suppressing the permeation of impurities such as water and hydrogen may be used in a single layer or a layered structure. Furthermore, it is possible to suppress impurities such as water and hydrogen contained in layers above the insulator 576 from being mixed into the oxide 530 through the conductors 540a and 540b.

[0479] The insulators 541a and 541b may be a barrier insulating film that can be used for the insulator 544, etc. For example, the insulators 541a and 541b may be made of an insulator such as silicon nitride, aluminum oxide, or silicon nitride oxide. The insulators 541a and 541b are provided in contact with the insulators 574, 576, and 571, and thus can prevent impurities such as water and hydrogen contained in the insulator 580 from entering the oxide 530 through the conductors 540a and 540b. Silicon nitride is particularly suitable because it has a high blocking property against hydrogen. Furthermore, oxygen contained in the insulator 580 can be prevented from being absorbed by the conductors 540a and 540b.

[0480] When insulators 541a and 541b are formed into a layered structure as shown in FIG. 28A, it is preferable that the first insulator in contact with the inner wall of an opening such as insulator 580 and the second insulator inside it be made of a combination of a barrier insulating film against oxygen and a barrier insulating film against hydrogen.

[0481] For example, aluminum oxide formed by the ALD method can be used as the first insulator, and silicon nitride formed by the PEALD method can be used as the second insulator. With this structure, oxidation of the conductor 540 can be suppressed and hydrogen contamination of the conductor 540 can be reduced.

[0482] Although the transistor 500 has a structure in which the first insulator of the insulator 541 and the second conductor of the insulator 541 are stacked, the present invention is not limited to this. For example, the insulator 541 may be provided as a single layer or a stacked structure of three or more layers. Furthermore, the transistor 500 has a structure in which the first conductor of the conductor 540 and the second conductor of the conductor 540 are stacked, but the present invention is not limited to this. For example, the conductor 540 may be provided as a single layer or a stacked structure of three or more layers.

[0483] Note that the structure of the transistor included in the semiconductor device of one embodiment of the present invention is not limited to the transistor 500 illustrated in Figures 28A and 28B. The structure of the transistor included in the semiconductor device of one embodiment of the present invention may be changed depending on the situation.

[0484] Above the transistor 500, an insulator 111 is provided.

[0485] The insulator 111 is preferably an insulator that has a function of suppressing diffusion of oxygen and impurities such as water and hydrogen, and examples thereof include aluminum oxide, magnesium oxide, hafnium oxide, gallium oxide, indium gallium zinc oxide, silicon nitride, and silicon nitride oxide. For example, silicon nitride, which has a higher hydrogen barrier property, is preferably used for the insulator 111. Furthermore, for example, aluminum oxide or magnesium oxide, which has a high function of capturing and fixing hydrogen, is preferably used for the insulator 111.

[0486] A highly flat film is preferably used as the insulator 111. In this case, the insulator 111 can be made of an organic material such as an acrylic resin or polyimide.

[0487] Above the insulator 111, light emitting devices 150a to 150c are provided.

[0488] Here, light emitting devices 150a to 150c will be described.

[0489] Conductors 121a to 121c functioning as pixel electrodes of the light-emitting devices 150a to 150c, respectively, are provided over the insulator 111. Note that in Figure 27, there are regions on the insulator 111 where the conductors 121a to 121c are not provided. Note that in this specification and the like, the conductors 121a to 121c may be collectively referred to as the conductor 121.

[0490] The conductors 121a to 121c can be formed, for example, by forming a conductive film over the insulator 111 and performing a patterning process, an etching process, or the like on the conductive film.

[0491] The conductors 121a to 121c function as anodes of the light emitting devices 150a, 150b, and 150c included in the display device 10, respectively, as an example.

[0492] The conductors 121a to 121c can be made of, for example, indium tin oxide (sometimes referred to as ITO).

[0493] Furthermore, each of the conductors 121a to 121c may have a stacked structure of two or more layers instead of a single layer. For example, a conductor with high reflectivity to visible light may be used as the first-layer conductor, and a conductor with high light transmittance may be used as the top-layer conductor. Examples of conductors with high reflectivity to visible light include silver, aluminum, and an alloy film of silver (Ag), palladium (Pd), and copper (Cu) (Ag-Pd-Cu (APC) film). Examples of conductors with high light transmittance include the above-mentioned indium tin oxide. Examples of the conductors 121a to 121c include a stacked film of aluminum sandwiched between a pair of titanium films (a stacked film of Ti, Al, and Ti in this order), a stacked film of silver sandwiched between a pair of indium tin oxide films (a stacked film of ITO, Ag, and ITO in this order), etc.

[0494] The insulator 112 is provided over the insulator 111 and the conductor 121a. Note that in Figure 27, there are regions over the conductor 121a, the conductor 121b, and the conductor 121c where the insulator 112 is not provided. For example, an insulating film to be the insulator 112 is formed over the insulator 111 and the conductors 121a to 121c, and the insulating film is patterned by photolithography or the like to form openings that reach the conductors 121a to 121c in regions of the insulating film that overlap with the conductors 121a to 121c. This allows the insulator 112 to be provided.

[0495] For example, an insulating inorganic film can be used as the insulator 112. Examples of the insulating inorganic film that can be used include silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, aluminum oxide, aluminum oxynitride, aluminum nitride oxide, and aluminum nitride.

[0496] An organic film having an insulating layer may also be used as the insulator 112. Examples of organic films that can be used for the insulator 112 include polyimide.

[0497] Furthermore, the insulator 112 may have a multi-layer structure. Specifically, for example, the insulator 112 may have a multi-layer structure in which the first layer is the organic film described above and the second layer is the inorganic film described above.

[0498] An EL layer 141a is provided over the insulator 112 and the conductor 121a. An EL layer 141b is provided over the insulator 112 and the conductor 121b. An EL layer 141c is provided over the insulator 112 and the conductor 121c. In FIG. 27, there is a region on the insulator 112 where the EL layers 141a to 141c are not provided.

[0499] Preferably, the EL layers 141a to 141c each have a light-emitting layer that emits light of a different color. For example, the EL layer 141a may have a light-emitting layer that emits blue (B), the EL layer 141b may have a light-emitting layer that emits green (G), and the EL layer 141c may have a light-emitting layer that emits red (R). In this way, the display device 10 may have a structure (SBS structure) in which different light-emitting layers for each color are formed on multiple pixel electrodes (conductors 121a to 121c).

[0500] The combination of colors emitted by the light-emitting layers included in each of the EL layers 141a to 141c is not limited to the above, and may be, for example, cyan, magenta, yellow, etc. Although the above example shows three colors, the number of colors emitted by the light-emitting device 150 included in the display device 10 may be two colors, or four or more colors.

[0501] The EL layer 141a, the EL layer 141b, and the EL layer 141c may each have one or more of an electron injection layer, an electron transport layer, a hole injection layer, and a hole transport layer in addition to a layer containing a light-emitting organic compound (light-emitting layer).

[0502] In addition, the EL layer 141a, the EL layer 141b, and the EL layer 141c can be formed by a method such as a vapor deposition method (vacuum vapor deposition method, etc.), a coating method (dip coating method, die coating method, bar coating method, spin coating method, spray coating method, etc.), a printing method (inkjet method, screen (stencil printing) method, offset (lithographic printing) method, flexography (relief printing) method, gravure method, microcontact method, etc.).

[0503] When applying the above-mentioned coating method, printing method, or other film formation method, it is possible to use high molecular weight compounds (oligomers, dendrimers, polymers, etc.), medium molecular weight compounds (compounds in the intermediate range between low molecular weight and high molecular weight: molecular weight 400 to 4000), inorganic compounds (quantum dot materials, etc.), etc. As quantum dot materials, colloidal quantum dot materials, alloy-type quantum dot materials, core-shell type quantum dot materials, core-type quantum dot materials, etc. can be used.

[0504] For example, light emitting devices 150a to 150c in FIG. 27 can be configured with multiple layers such as layer 4420, light emitting layer 4411, and layer 4430, like light emitting device 150 shown in FIG. 30A.

[0505] The layer 4420 can have, for example, a layer containing a substance with a high electron injecting property (electron injecting layer) and a layer containing a substance with a high electron transporting property (electron transporting layer). The light-emitting layer 4411 contains, for example, a light-emitting compound. The layer 4430 can have, for example, a layer containing a substance with a high hole injecting property (hole injecting layer) and a layer containing a substance with a high hole transporting property (hole transporting layer).

[0506] A structure having layer 4420, light-emitting layer 4411, and layer 4430 provided between a pair of electrodes (conductor 121 and conductor 122 described later) can function as a single light-emitting unit, and in this specification, the structure of Figure 30A is called a single structure.

[0507] As shown in FIG. 30B, a configuration in which a plurality of light-emitting layers (light-emitting layer 4411, light-emitting layer 4412, light-emitting layer 4413) are provided between layer 4420 and layer 4430 is also a variation of the single structure.

[0508] A laminate having multiple layers such as layer 4420, light-emitting layer 4411, and layer 4430 may be referred to as a light-emitting unit. Multiple light-emitting units may be connected in series via an intermediate layer (charge generation layer). Specifically, as shown in FIG. 30C , multiple light-emitting units, such as light-emitting unit 4400a and light-emitting unit 4400b, may be connected in series via an intermediate layer (charge generation layer) 4440. In this specification, such a structure is referred to as a tandem structure. In this specification and the like, a tandem structure may also be referred to as a stack structure. By forming a light-emitting device in a tandem structure, a light-emitting element capable of emitting high-luminance light can be obtained. By forming a light-emitting device in a tandem structure, improvements in the light-emitting efficiency and lifespan of the light-emitting device can be expected. When the light-emitting device 150 of the display device 10 of Figure 27 has a tandem structure, the EL layer 141 can be configured to include, for example, layer 4420, light-emitting layer 4411, and layer 4430 of light-emitting unit 4400a, intermediate layer 4440, and layer 4420, light-emitting layer 4412, and layer 4430 of light-emitting unit 4400b.

[0509] Furthermore, when displaying white, the SBS structure described above can reduce power consumption compared to the single and tandem structures. Therefore, if you want to keep power consumption low, the SBS structure is preferable. On the other hand, the single and tandem structures are preferable because their manufacturing processes are easier than those of the SBS structure, allowing for lower manufacturing costs and higher manufacturing yields.

[0510] The light-emitting device 150 can emit light in red, green, blue, cyan, magenta, yellow, or white, depending on the material of the EL layer 141. Furthermore, the color purity can be further improved by providing the light-emitting device 150 with a microcavity structure.

[0511] A light-emitting element that emits white light preferably has a structure in which two or more light-emitting substances are contained in the light-emitting layer. To obtain white light emission, light-emitting substances are selected such that the respective emissions of the two or more light-emitting substances are in a complementary color relationship.

[0512] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), etc. Alternatively, it is preferable that the light-emitting layer contains two or more light-emitting materials, and the light emitted by each of the light-emitting materials contains spectral components of two or more colors of R, G, and B.

[0513] 27, a gap is provided between two EL layers between light-emitting devices of different colors. In this manner, it is preferable that the EL layers 141a, 141b, and 141c are provided so as not to be in contact with each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, resulting in unintended light emission (also known as crosstalk). This allows for increased contrast, resulting in a display device with high display quality.

[0514] The EL layers 141a to 141c can be formed by a method using photolithography. For example, an EL film to become the EL layers 141a to 141c is formed on the insulator 111 and the conductor 121, and then the EL film is patterned by photolithography to form the EL layers 141a to 141c. Alternatively, the conductor 122 may be formed on the EL film, and then the EL film, including the conductor 122, may be patterned by photolithography to form the EL layers 141a to 141c. In this case, the EL layers 141a to 141c have the same structure. Therefore, when it is desired to perform color display on the display device 10 formed using this formation method, the light-emitting devices 150a to 150c, which include the EL layers 141a to 141c, respectively, can be configured as light-emitting devices that emit white light, and the display device 10 can be configured to emit light from the light-emitting devices to the outside through a colored layer (color filter).

[0515] The EL layers 141a to 141c are formed by first depositing an EL film that will become the EL layer 141a on the insulator 111 and the conductor 121, and then forming the EL layer 141a by photolithography. The EL layers 141b and 141c are then formed in predetermined regions using a similar procedure. By using this method, the EL layers 141a to 141c can each have a different configuration, allowing the display device 10 to have an SBS structure.

[0516] Furthermore, the above-described method can shorten the distance between pixels. This allows the number of pixels included in the display unit to be increased, thereby increasing the resolution of the display device. For example, the distance between pixels is preferably 5 μm or less, and more preferably 1 μm or less.

[0517] The EL layers 141a to 141c may be formed by a method other than photolithography, such as nanoimprinting or lift-off. Alternatively, island-shaped thin films may be directly formed by a film formation method using a shielding mask such as a metal mask.

[0518] A conductor 122 is provided on the insulator 112, the EL layer 141a, the EL layer 141b, and the EL layer 141c.

[0519] The conductor 122 functions as, for example, a common electrode for each of the light-emitting devices 150a to 150c. In order to emit light from the light-emitting device 150 upward in the display device 10, the conductor 122 preferably includes a light-transmitting conductive material.

[0520] The conductor 122 is preferably a material that is highly conductive and has light-transmitting and light-reflecting properties (sometimes called a semi-transparent / semi-reflective electrode). For example, an alloy of silver and magnesium or indium tin oxide can be used as the conductor 122.

[0521] The insulator 113 functions as, for example, a passivation film that protects the light-emitting devices 150a, 150b, and 150c. Therefore, the insulator 113 is preferably made of a material that prevents the intrusion of water and the like. For example, the insulator 113 may be made of a material that can be used for the insulator 111. Specifically, aluminum oxide, silicon nitride, silicon nitride oxide, or the like may be used.

[0522] A resin layer 161 is provided on the insulator 113. Furthermore, a substrate 102 is provided on the resin layer 161.

[0523] For example, a light-transmitting substrate is preferably used as the substrate 102. By using a light-transmitting substrate for the substrate 102, light emitted from the light-emitting device 150a, the light-emitting device 150b, and the light-emitting device 150c can be emitted upward from the substrate 102.

[0524] As described above, by configuring the display device 10 of FIG. 27, it is possible to realize a display device having a resolution of preferably 1000 ppi or more, more preferably 3000 ppi or more, and even more preferably 5000 ppi or more.

[0525] <Example of sealing structure for display device> Next, a sealing structure for the light emitting devices 150a to 150c that can be applied to the display device 10 of FIG. 27 will be described.

[0526] Fig. 31A is a cross-sectional view showing an example of a sealing structure applicable to the display device 10 of Fig. 27. Specifically, Fig. 31A illustrates an edge of the pixel array ALP of the display device 10 of Fig. 27 and materials provided around the edge. Fig. 31A also illustrates only a portion of the pixel layer PXAL of the display device 10. Specifically, each of Figs. 31A illustrates the insulator 111, a plug connected to the transistor 500, and insulators, conductors, light-emitting devices 150a to 150c, and the like, located above the insulator 111.

[0527] 31A, an adhesive layer 164 is provided at or around an end of the pixel array ALP. Specifically, the display device 10 is configured so that the adhesive layer 164 is interposed between the insulator 112 and the substrate 102.

[0528] The adhesive layer 164 is preferably made of a material that suppresses the permeation of impurities such as moisture. By using such a material for the adhesive layer 164, the reliability of the display device 10 can be improved.

[0529] A structure in which the insulator 112 and the substrate 102 are bonded together via the resin layer 161 using the adhesive layer 164 is sometimes called a solid sealing structure. In addition, in the solid sealing structure, if the resin layer 161 has the function of bonding the insulator 112 and the substrate 102 together, similar to the adhesive layer 164, the adhesive layer 164 does not necessarily have to be provided.

[0530] On the other hand, a structure in which the insulator 112 and the substrate 102 are bonded together using the adhesive layer 164 and filled with an inert gas instead of the resin layer 161 is sometimes called a hollow sealing structure (not shown). Examples of the inert gas include nitrogen and argon.

[0531] 31A, two or more adhesive layers may be stacked. For example, as shown in FIG. 31B, an adhesive layer 165 may be further provided inside adhesive layer 164 (between adhesive layer 164 and resin layer 161). By stacking two or more adhesive layers, the permeation of impurities such as moisture can be further suppressed, thereby further improving the reliability of display device 10.

[0532] A desiccant may be mixed into the adhesive layer 165. This allows the desiccant to adsorb moisture contained in the adhesive layer 164, the resin layer 161 formed inside the adhesive layer 165, the insulator, the conductor, the EL layer, and the like, thereby improving the reliability of the ...

Claims

1. a first layer and a third layer located above the first layer, the first layer has a drive circuit region; the third layer has a pixel array; the pixel array has a plurality of pixel regions; the drive circuit region has a plurality of local driver circuits; one of the plurality of local driver circuits corresponds to one of the plurality of pixel areas; the local driver circuit has a function of driving a plurality of pixels included in the corresponding pixel region, In top view, the driving circuit region is located inside the pixel array, each of the plurality of pixel regions has a plurality of wirings; In the plurality of pixel regions, the plurality of pixels are arranged in a matrix, the plurality of wirings are located for each row of the plurality of pixels arranged in the matrix, one of the plurality of wirings is electrically connected to the pixels located in the same row; Each of the plurality of wirings has a contact portion, the contact portion is located inside the pixel or between the adjacent pixels, a part of the plurality of pixel regions does not overlap the drive circuit region; Display device.

2. In claim 1, the drive circuit area includes a controller and a voltage generating circuit; the controller has a function of acquiring an image signal and an address signal including a destination of the image signal, which are input from outside, and a function of selecting the plurality of local driver circuits in accordance with the address signal and transmitting the image signal to the selected local driver circuit; the voltage generation circuit has a function of generating a voltage to be supplied to the plurality of local driver circuits or the pixels; Display device.

3. In claim 1 or claim 2, the pixel included in each of the plurality of pixel regions has a light-emitting device using an organic EL and a first transistor; the plurality of local driver circuits each having a second transistor; the first transistor has a metal oxide in a channel formation region; the second transistor has silicon in a channel formation region; Display device.

4. 4. An electronic device comprising: the display device according to claim 1; and a housing.

Images