Gaming machine

Abstract

A single processor implements both the performance control means and the image control means, providing functionality equivalent to or better than that of a configuration with multiple processors. [Solution] The sub-control board 1200 includes one processor (sub-control CPU 1201) having multiple processor cores, a first storage device (sub-control ROM 1202) on which data is pre-written, and a second storage device (sub-control RAM 1203) on which data can be read and written. The second storage device is provided with a shared area 1231 that can be accessed by both a first process assigned to and operating on the first processor core and a second process assigned to and operating on the second processor core. When the first process detects the occurrence of a predetermined interrupt, it writes a flag indicating the occurrence of the interrupt to the shared area 1231, and the second process detects the occurrence of a predetermined interrupt by periodically monitoring the shared area 1231 and reading the flag.

Claims

[Claim 1] A gaming machine comprising: a main control board for controlling the progress of the game; a sub-control board for controlling the effects based on information from the main control board; the sub-control board having at least one processor having a plurality of processor cores capable of independently executing processes, a first storage device on which data is pre-written, and a second storage device on which data can be read and written; the second storage device is provided with a shared area accessible from both a first process assigned to and operating on the first processor core among the plurality of processor cores, and a second process assigned to and operating on a second processor core different from the first processor core among the plurality of processor cores; the first process, upon detecting the occurrence of a predetermined interrupt, writes a flag indicating the occurrence of the interrupt to the shared area; and the second process periodically monitors the shared area and detects the occurrence of the predetermined interrupt by reading the flag written to the shared area by the first process.

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