Storage system

Abstract

This improves the processing performance of management commands from storage administrators while minimizing the impact on host I / O processing. [Solution] The storage system includes a management system and one or more disk controllers that process read and write requests from a host device, wherein the management system monitors the processor load of the one or more disk controllers, receives management operation commands from a management terminal, and controls the amount of communication between the management system and the one or more disk controllers for internal commands corresponding to the management operation commands, based on the processor load.

Description

Technical Field

[0005]

[0001] The present invention relates to a storage system.

Background Art

[0002] As the background art of the present application, there is Patent Document 1. Patent Document 1 discloses that "the terminal device 20 according to the present invention includes a bandwidth information acquisition unit 203, a determination unit 204, a change unit 207, a compression unit 205, and a communication control unit 206. The bandwidth information acquisition unit 203 acquires bandwidth information indicating the bandwidth of the network 30. The determination unit 204 determines the transmission image format, which is the quality of the image to be transmitted to the network 30, based on the network bandwidth table and the bandwidth information, and determines the input image format with the minimum power consumption among the input image formats that can compress the image of the transmission image format from the CPU power consumption table. The change unit 207 changes the quality of the image captured by the external imaging device 101 to the captured image format."

[0003] A storage system including one or more storage controllers, each storage controller including a disk controller and a management controller that perform host I / O processing, is known. The management controller receives a management operation command (management operation request) from a storage administrator and performs the processing thereof. The management operation command includes, for example, setting of a volume or a pool, acquisition of information of a volume or a pool, update of the firmware of a disk controller, and the like.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] The management controller issues corresponding internal commands to the disk controllers in order to process management operation commands from the storage administrator. These internal commands may affect the host I / O processing performed by the disk controllers. By limiting the number of management commands issued, it is possible to avoid this impact on the host I / O processing performed by the disk controllers.

[0006] On the other hand, there is a need to improve the processing performance of management commands from storage administrators. Therefore, there is a demand for technology that can improve the processing performance of management commands while minimizing the impact on host I / O processing. [Means for solving the problem]

[0007] A storage system according to one embodiment of the present invention includes a management system and one or more disk controllers that process read and write requests from a host device, wherein the management system monitors the processor load of the one or more disk controllers, receives management operation commands from a management terminal, and controls the amount of communication between the management system and the one or more disk controllers for internal commands corresponding to the management operation commands, based on the processor load. [Effects of the Invention]

[0008] According to one aspect of the present invention, it is possible to improve the processing performance of management operation commands from a storage administrator while minimizing the impact on host I / O processing. [Brief explanation of the drawing]

[0009] [Figure 1] This document shows an example of the hardware configuration of a storage system and related devices according to one embodiment of this specification. [Figure 2] This is a block diagram showing the configuration details of the storage controller. [Figure 3] This flowchart shows an example of switch port bandwidth control using an FPGA. [Figure 4]This shows an example of temporary data stored in the FPGA's RAM for bandwidth limiting of the communication channel. [Figure 5] An example of a bandwidth limit reference table configuration is shown. [Figure 6] This flowchart shows an example of the internal command issuance process by the management controller. [Figure 7] An example of an internal command issuance reference table is shown below. [Figure 8] An example of an internal command issuance reference table is shown below. [Figure 9] This flowchart shows an example of controlling the amount of communication between the management controller and the management terminal. [Figure 10] This shows an example configuration of User LAN Bandwidth Control Reference Table 1. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. Where necessary for convenience, the descriptions will be divided into multiple sections or embodiments. Unless otherwise specified, these are not unrelated, and one may be a modification, detail, or supplementary explanation of part or all of the other. Furthermore, when referring to the number of elements, etc. (including number, numerical value, quantity, range, etc.), unless otherwise specified or clearly limited to a specific number in principle, the number is not limited to that specific number and may be greater than or less than that number.

[0011] A processor or arithmetic unit (AGS) performs predetermined functions by executing programs stored in main memory. Main memory stores programs executed by the AGS, as well as data necessary for program execution. The programs include the operating system (OS), which is not shown in the diagram. The AGS may include multiple chips and multiple packages.

[0012] The program is executed by an arithmetic unit to perform defined processing while using a storage device and a communication port (communication device). Therefore, in this embodiment, the description with the program as the subject may be the same as the description with the arithmetic unit as the subject. Alternatively, the processing executed by the program is the processing performed by the computer and the computer system on which the program operates.

[0013] The arithmetic unit operates as a functional unit (means) that realizes a predetermined function by operating according to the program. Furthermore, the arithmetic unit also operates as a functional unit (means) that realizes each of a plurality of processes executed by each program. The computer and the computer system are devices and systems including these functional units (means).

[0014] Using FIG. 1, a hardware configuration example of a storage system 100 and related devices according to an embodiment of this specification will be described. The host device 230 is connected to the storage system 100 via a switch (network) not shown. The host device 230 makes various requests such as read requests or write requests (I / O requests) to the storage system 100 in order to manage host data. The network can use protocols such as FC (Fibre Channel) or Ethernet, for example.

[0015] The management terminal 200 is connected to the storage system 100 via a switch (SW) 210. The switch 210 can use, for example, a LAN (Local Area Network) switch.

[0016] The system administrator issues management operation commands to the storage system 100 by operating the management terminal 200 to manage the storage system 100. The management operation commands include, for example, volume or pool settings, acquisition of volume or pool information, firmware update of a disk controller (also called an I / O controller), acquisition of dump data (including log data) in the storage system 100, and the like.

[0017] The storage system 100 is equipped with two storage controllers (STGC) 110A and 110B having the same functions for the purpose of system high reliability. The storage system 100 may be equipped with one or more storage drives as storage media for holding data (referred to as host data) from the host device 230. The storage drive may be, for example, an HDD (Hard Disk Drive) or an SSD (Solid State Drive).

[0018] In the configuration example of FIG. 1, a plurality of storage drives are connected to each of the two storage controllers 110A and 110B. Also, one storage drive connected to the storage controller 110A is designated by reference numeral 160A as an example, and one storage drive connected to the storage controller 110B is designated by reference numeral 160B as an example.

[0019] Hereinafter, examples of the two storage controllers 110A and 110B in the storage system 100 will be described. The number of storage controllers is not particularly limited. The storage system can include only one or three or more storage controllers.

[0020] The storage controller 110A includes a management controller (MGC) 120A and a disk controller (DKC) 130A. These are different hardware devices. The management controller 120A manages the storage system 100 according to instructions from the administrator. Specifically, the management controller 120A processes the above-described management operation commands from the management terminal 200.

[0021] The disk controller 130A processes I / O requests (read requests and write requests) from the host device 230. The disk controller 130A communicates with the host device 230A via a front-end interface (FEI / F) 131A and communicates with the storage drive 160A via a back-end interface (BEI / F) 132A.

[0022] The storage controller 110A further includes a switch 140A and an FPGA (Field Programmable Gate Array) 150A. Switch 140A is, for example, a LAN switch. Each LAN port of switch 140A is connected to the management controller 120A, the disk controller 130A, the LAN port of switch 140B of the storage controller 110B, and the LAN port of the external switch 210. The ports of the external switch 210 and switch 140A may be connected via the management port of the storage controller 110A.

[0023] FPGA150A may be connected to other devices via any protocol, such as SPI or I2C, to enable communication. FPGA150A is connected to FPGA150B of switch 140A, management controller 120A, disk controller 130A, and storage controller 110B. Management controller 120A and FPGA150A are included in the management system of storage controller 110A.

[0024] The storage controller 110B has a similar configuration to the storage controller 110A. Specifically, the storage controller 110B includes a management controller 120B and a disk controller 130B. One of the management controllers 120A and 120B is the active system and the other is the standby system. The active management controller, for example, management controller 120A, receives and processes management operation commands from the management terminal 200.

[0025] Disk controller 130B processes I / O requests (read requests and write requests) from host device 230. Both disk controllers 130A and 130B are operational. Disk controller 130B communicates with host device 230A via front-end interface 131B and with storage drive 160B via back-end interface 132B.

[0026] The storage controller 110B further includes a switch 140B and an FPGA 150B. Switch 140B is, for example, a LAN switch. Each LAN port of switch 140B is connected to the management controller 120B, the disk controller 130B, the LAN port of switch 140A of the storage controller 110A, and the LAN port of the external switch 210. The ports of the external switch 210 and switch 140B may be connected via the management port of the storage controller 110B.

[0027] FPGA150B may be connected to other devices so as to be able to communicate with them using any protocol, such as SPI or I2C. FPGA150B is connected to the switch 140B, the management controller 120B, the disk controller 130B, and the storage controller 110A. The management controller 120B and FPGA150B are included in the management system of the storage controller 110B.

[0028] Figure 2 is a block diagram showing the configuration details of storage controllers 110A and 110B. Figure 2 shows some of the components of each device, and each device includes components not shown. Storage controller 110A will be described below.

[0029] In the configuration example shown in Figure 2, the management controller 120A includes a processor 121A, memory 122A, and port 123A. These components are connected to a bus. Memory 122A is volatile or non-volatile memory, and may be, for example, DRAM. Memory 122A stores the program executed by the processor 121A and the data that the program references or processes.

[0030] The management controller 120A may include volatile memory and non-volatile memory (e.g., flash memory). Programs executed by the processor 121A and data referenced by it may be stored in non-volatile memory. Programs or data stored in non-volatile memory may be loaded into volatile memory or read by the processor 121A, and executed, processed, or referenced by the processor 121A. The management controller 120A may include other components not shown.

[0031] The disk controller 130A includes a main processor 133A, a management processor 134A, memory 135A, and port 136A. These components are connected to a bus. The main processor 133A is a CPU that provides various functions required by the storage system. The main processor 133A performs operations related to reading, writing, and holding host data, including host I / O processing.

[0032] The management processor 134 provides various functions for managing the disk controller 130A. For example, the management processor 134 provides functions such as hardware initialization, power management, temperature management, and starting the main processor 133A.

[0033] Memory 135A and 136A are volatile or non-volatile memories, and may be, for example, DRAM. Memory 136A stores programs executed by the management processor 136A and data referenced or processed by those programs. Memory 135A stores programs executed by the main processor 133A and data referenced or processed by those programs, and also includes a host data cache area.

[0034] The disk controller 130A may include volatile memory and non-volatile memory (e.g., flash memory). Programs executed by processors 133A and 134A, and data referenced by them, may be stored in non-volatile memory. Programs or data stored in non-volatile memory can be loaded into volatile memory or read by processors 133A and 134A, and executed, processed, or referenced by processors 133A and 134A. The disk controller 130A may include other components not shown.

[0035] Switch 140A includes multiple ports, one of which is indicated by symbol 141A as an example. Different ports 141A of switch 140A are connected to port 123A of management controller 120A, port 136A of disk controller 130A, port 141B of switch 140B of storage controller 110B, and a port of external switch 210, respectively. FPGA 150A is connected to other devices without going through the ports of switches 140A and 140B.

[0036] The storage controller 110B has a similar configuration to the storage controller 110A. The management controller 120B includes a processor 121B, memory 122B, and port 123B. The description of the management controller 120A may apply to the management controller 120B. The disk controller 130B includes a main processor 133B, a management processor 134B, memory 135B, 136B, and port 136B. The description of the disk controller 130A may apply to the disk controller 130B.

[0037] Switch 140B includes multiple ports, one of which is indicated by the symbol 141B as an example. Different ports 141B of switch 140B are connected to port 123B of management controller 120B, port 136B of disk controller 130B, port 141A of switch 140A of storage controller 110A, and a port of external switch 210, respectively. FPGA 150B is connected to other devices without going through the ports of switches 140A and 140B.

[0038] The following describes the processing of management operation commands from the storage administrator. The management terminal 200 sends management operation commands for managing the storage system 100 to the storage system 100 in accordance with the instructions from the administrator. The management operation commands may include, for example, the following commands.

[0039] Get / Set / Delete Pool: Get / set / delete pool information. Get / Set / Delete Volume: Get / set / delete volume information. Get / Set / Delete Snapshot: Get / set / delete snapshot information. Get / Set / Delete Server: Retrieves / sets / deletes information about the host device accessing the volume.

[0040] Get Performance Volume: Retrieves a list of volume performance information. Get Performance Cache: Retrieves a list of cache performance information. Dump: Obtain dump data Firmware Update: Update the storage controller firmware.

[0041] At least some management operation commands can specify multiple targets. For example, the management operation command "Get / Set / Delete Volume" can specify multiple target volumes. For instance, the management operation command "Get Volume" can retrieve information on all volumes. Note that pool and volume settings involve creating and modifying them.

[0042] Management operation commands from the management terminal 200 are sent to the management controller 120A. Here, we assume that management controller 120A is the active system and management controller 120B is the standby system. Furthermore, we assume that disk controllers 130A and 130B are both active systems for host I / O processing. Disk controllers 130A and 130B share management information for host I / O, such as information about volumes, pools, snapshots, caches, and host devices.

[0043] The processor 121A of the management controller 120A generates one or more internal commands from a single management operation command it receives, and sends each of the generated internal commands to the disk controller 130A via switch 140A, or to 130B via switches 140A and 140B.

[0044] The main processor 133A of disk controller 130A or the main processor 133B of disk controller 130B receives an internal command, executes the processing instructed by the command, and returns a response to the management controller 120A. When the processor 121A of the management controller 120A receives responses to all internal commands, it returns a response to the management operation command to the management terminal 200.

[0045] The management controller 120A can generate multiple internal commands from a single management operation command of several types. For example, from the management operation command "Get / Set / Delete Volume" specifying 10,000 volumes, internal commands can be generated for each predetermined number of volumes. The same applies to management operation commands related to pools, snapshots, and host devices (servers).

[0046] Internal commands may be generated from the management operation command "Dump" for predetermined data sizes or predetermined time intervals, and internal commands for each core may be generated from the management operation command "Firmware Update". Each processor in the storage system 100 may contain one or more cores, and processors containing multiple cores are capable of parallel processing using multiple cores. In the following description, the main processors 133A and 133B are assumed to contain multiple cores.

[0047] The management controller 120A issues internal commands to the main processors 133A and 133B, respectively, at a predetermined degree of parallelism. The degree of parallelism may be common to or different for the main processors 133A and 133B, and may be fixed or dynamically changed. The degree of parallelism indicates the upper limit of the number of internal commands that can be issued simultaneously. Issued internal commands are completed upon response from the main processors.

[0048] In one embodiment of this specification, the storage system 100 monitors the load status of the main processor 133A of disk controller 130A and the main processor 133B of disk controller 130B, and controls the amount of communication between the management controller 120A and the two disk controllers 130A and 130B according to the load status. As will be described later, the amount of communication can be controlled, for example, by limiting the bandwidth of the communication path and / or by the frequency of issuing internal commands (number of commands issued per unit time).

[0049] Communication volume control allocates less communication to main processors with higher loads and more communication to main processors with lower loads. This allows main processors with lower host I / O loads to process more internal commands, while main processors with higher host I / O loads process fewer internal commands. This reduces the impact of management operation command processing on host I / O processing while improving the processing performance of management operation commands.

[0050] One embodiment of this specification controls the amount of internal command communication by controlling the bandwidth of the communication path between the management controller 120A and the disk controllers 130A and 130B, and by controlling the frequency of internal commands issued to each of the disk controllers 130A and 130B. This allows for a more appropriate balance between the processing performance of management operation commands and the host I / O processing performance. Note that only one of the communication bandwidth control or internal command issuance control may be implemented.

[0051] First, communication bandwidth control between controllers will be described. In one embodiment of this specification, the communication bandwidth between controllers is controlled by controlling the bandwidth of the ports of switches 140A and 140B. The bandwidth control of the ports of switches 140A and 140B is performed by FPGAs 150A and 150B. This reduces the load on management controllers 120A and 120B. Alternatively, management controllers 120A and 120B may perform the bandwidth control of the ports of switches 140A and 140B.

[0052] Figure 3 shows a flowchart of an example of port bandwidth control for switches 140A and 140B using FPGAs 150A and 150B. FPGAs 150A and 150B each perform the processing shown in Figure 3. For the sake of clarity, the processing of FPGA 150A will be explained below. FPGA 150B performs the processing similarly.

[0053] When FPGA150A starts up, it executes circuit construction using the implementation program (S11). Next, FPGA150A sets a power consumption sampling interval (for example, 1 minute) for the management processor 134A of its own disk controller 130A (S12). The power consumption here is, for example, the power consumption of disk controller 130A. If information on the power consumption of the main processor 133A is available, that information may be sampled.

[0054] Next, FPGA150A obtains information on the rated power consumption from its own management processor 134A and stores it in FPGA150A's RAM (memory) (S13). Furthermore, FPGA150A obtains information on the rated power consumption of the disk controller 130B of another system from FPGA150B of another system and stores it in FPGA150's RAM (S14).

[0055] FPGA150A obtains power consumption information from its own system's management processor 134A and stores it in FPGA150A's RAM (S15). Furthermore, FPGA150A obtains power consumption information from another system's FPGA150B and stores it in FPGA150A's RAM (S16).

[0056] Figure 4 shows an example of temporary data 151 for communication channel bandwidth limiting, which is stored in the RAM of FPGA150A in the above steps. Temporary data 151 includes the rated power consumption and power consumption of the local and other systems, as well as the estimated processor utilization and limited bandwidth (limited communication bandwidth) of the local and other systems, which will be described later. Processor utilization represents the CPU load. The limited bandwidth is shown here as the percentage of the specified bandwidth (maximum bandwidth) that can be used, but it may be expressed in other units.

[0057] Returning to Figure 3, FPGA150A refers to the bandwidth limit reference table, which is one of the management tables, to determine the estimated processor utilization of the main processors 133A and 133B of the local and other systems, and stores it in the RAM of FPGA150A (S17). As shown in Figure 4, the temporary data 151 includes the estimated processor utilization of the local and other systems.

[0058] Figure 5 shows an example configuration of the bandwidth limiting reference table 152. The bandwidth limiting reference table 152 is pre-implemented on FPGA 150A. While this example describes FPGA 150A, FPGA 150B also maintains the same bandwidth limiting reference table.

[0059] The bandwidth limit reference table 152 includes a power consumption column 154, a bandwidth limit (between MGC and DKC) column 155, and an estimated processor utilization column 156. The power consumption column 154 shows the power consumption of disk controllers 130A and 130B. In the configuration example shown in Figure 5, the power consumption column 154 shows values ​​in descending order in 200W increments. Each record shows information for a specific power consumption range. For example, each record defines the bandwidth limit and estimated processor utilization for power consumption within a range that is less than or equal to the value shown in the power consumption column 154 and greater than the value in the record immediately below it. Note that records with more granular power consumption values ​​may also be included.

[0060] The Bandwidth Limitation (MGC-DKC) column 155 indicates the percentage of the specified bandwidth (maximum bandwidth) of the communication path between controllers that is available, as shown in the Power Consumption column 154. The higher the power consumption, the smaller the bandwidth percentage allocated. Therefore, the internal command processing performed by the main processor of a disk controller with high power consumption will be reduced. Conversely, the internal command processing performed by the main processor of a disk controller with low power consumption will be increased.

[0061] The estimated processor usage column 156 shows the estimated usage of main processors 133A and 133B, associated with the power consumption shown in the power consumption column 154. Higher power consumption corresponds to a higher estimated processor usage. Thus, power consumption is considered a variable representing processor usage (CPU load).

[0062] Note that the bandwidth limiting reference table 152 may be prepared for each disk controller. Alternatively, a function that provides similar information may be implemented instead of the bandwidth limiting reference table 152. Information on estimated processor utilization may be omitted.

[0063] Returning to Figure 3, FPGA150A refers to the bandwidth limit reference table 152 to determine the bandwidth limit ratios for its own system and other systems, and stores them in FPGA150A's RAM (S18). As shown in Figure 4, temporary data 151 includes the bandwidth limit ratios for its own system and other systems.

[0064] Next, FPGA150A sets a bandwidth limit on its own switch 140A between the management controller 120A and the disk controller 130A (S19). The bandwidth limit is set on the connection port of switch 140A to the disk controller 130A. Finally, FPGA150A waits for the sampling interval (S20) and returns to step S11.

[0065] As described above, the information used for bandwidth limiting between controllers is obtained from the management processor 134A and does not place a load on the main processor 133A. Therefore, the impact on host I / O due to bandwidth limiting can be avoided. Alternatively, instead of power consumption, the utilization rate of the main processor 133A may be obtained from the main processor 133A. The FPGA 150B also executes processing according to the flowchart above to control the bandwidth of the connection port of the disk controller 130B in the switch 140B.

[0066] Alternatively, only one of the two FPGAs 150A and 150B may calculate the bandwidth limiting ratio for the two disk controllers 130A and 130B and transmit the ratio of the bandwidth limiting ratio for the other system to the other. Furthermore, information on estimated processor utilization may be omitted. CPU load may be estimated from information different from power consumption. For example, disk controller temperature information may be referenced.

[0067] Next, we will explain how to control the amount of command communication based on the frequency of internal command issuance. The management controller 120A issues many internal commands to the main processor of disk controllers that are currently estimated to have a low load, and fewer internal commands to the main processor of disk controllers that are currently estimated to have a high load. This improves the processing performance of management operation commands while suppressing the impact on host I / O processing.

[0068] Figure 6 shows a flowchart of an example of the internal command issuance process by the management controller 120A. The processor 121A of the management controller 120A waits for a management operation command from the management terminal 200 (S31). When the processor 121A receives a management operation command, it determines its contents, including its type (S32).

[0069] Processor 121A accesses FPGA 150A in its own system and obtains information on the estimated processor utilization of both systems stored in temporary data 151 in the RAM of FPGA 150A (S33). Processor 121A starts a timer for a predetermined time (for example, 1 minute) (S34).

[0070] The processor 121A determines the internal command issuance rate by referring to the internal command issuance reference table, which is a management table (S35). Figures 7 and 8 show examples of the internal command issuance reference table. Figure 7 shows an example of the internal command issuance reference table 125 for normal management operation commands (normal commands). Figure 8 shows an example of the internal command issuance reference table 126 for pre-specified specific management operation commands (specific commands). The internal command issuance reference tables 125 and 126 are pre-stored in the non-volatile memory of the management controllers 120A and 120B.

[0071] The specific management operation commands that use the internal command issuance reference table 126 shown in Figure 8 are commands that use more communication bandwidth than other management operation commands, such as "Dump" and "Firmware Update." In other words, these are commands that use more communication bandwidth for the transmission of internal commands or their responses.

[0072] The internal command issuance reference table 125 in Figure 7 includes the estimated processor usage column 251 for DKC1, the estimated processor usage column 252 for DKC2, the internal command issuance rate column 253 for DKC1, and the internal command issuance rate column 254 for DKC2. DKC1 and DKC2 refer to disk controller 130A and disk controller 130B, respectively.

[0073] The DKC1 estimated processor usage column 251 shows the estimated processor usage of the main processor 133A of the disk controller 130A. The DKC2 estimated processor usage column 252 shows the estimated processor usage of the main processor 133B of the disk controller 130B. The DKC1 internal command issuance ratio column 253 shows the proportion of internal commands issued to the disk controller 130A for a single management operation command. The DKC2 internal command issuance ratio column 254 shows the proportion of internal commands issued to the disk controller 130B for a single management operation command.

[0074] The internal command issuance reference table 125 defines the internal command issuance ratio for combinations of the usage rates of the two main processors 133A and 133B. Figure 7 shows some example combinations of processor usage rates. The internal command issuance reference table 125 defines the internal command issuance ratio for all combinations of processor usage rates. The combinations of processor usage rates may be combinations of usage rate ranges. Instead of the internal command issuance reference table 125, a function that provides similar information may be implemented.

[0075] Referring to Figure 7, in main processors 133A and 133B, the proportion of internal commands issued to the main processor with higher utilization is higher than the proportion of internal commands issued to the main processor with lower utilization. Furthermore, the greater the difference in processor utilization, the greater the difference in the proportion of internal commands issued. By allocating internal commands in this way, it is possible to improve the processing performance of management operation commands while minimizing the impact on host I / O processing.

[0076] The internal command issuance reference table 126 shown in Figure 8 includes the DKC1 estimated processor usage column 261, the DKC2 estimated processor usage column 262, the DKC1 internal command issuance rate column 263, and the DKC2 internal command issuance rate column 264. Compared with the internal command issuance reference table 125 in Figure 7, the internal command issuance rate differs for the same combination of processor usage rates. Specifically, a larger proportion of internal commands are assigned to main processors with lower loads.

[0077] In the example shown in Figure 8, the ratio of internal command issuance to main processors with high utilization is -10% of the ratio for normal commands, while the ratio of issuance to main processors with low utilization is +10%. This allows for more appropriate suppression of the impact on host I / O processing performance and improvement of management operation command processing performance. Note that a common internal command issuance reference table 125 may be used for all internal commands, or three or more different internal command issuance reference tables may be prepared for different management operation commands (internal commands). Power consumption information may be used instead of processor utilization information.

[0078] Returning to Figure 6, the processor 121A of the management controller 120A sequentially issues internal commands to the main processors 133A and 133B of the disk controllers 130A and 130B of both systems, according to the determined internal command issuance ratio (S36). Depending on the target of the management operation command, the internal command may be issued to only one of the disk controllers. In this case, the processing of this flow is omitted, and the internal command is issued only to the target disk controller.

[0079] Processor 121A determines if all internal commands have been issued (S37). If all internal commands have been issued (S37:YES), it terminates the process. If there are any unissued internal commands remaining (S37:NO), processor 121A determines if the timer has finished (S38). If the timer has finished (S38:YES), the flow returns to step S33. If the timer has not finished (S38:NO), the flow returns to S36.

[0080] Next, the communication volume control between the management terminal 200 and the storage system 100 will be described. The storage system 100 limits the communication bandwidth between the management terminal 200 and the storage system 100 to suppress the influx of large amounts of management operation commands from the storage administrator and large amounts of data during firmware uploads. This reduces the impact on host I / O processing. Note that the communication volume control between the management terminal 200 and the storage system 100 may be omitted.

[0081] Figure 9 shows a flowchart of an example of communication volume control between the management controller 120A and the management terminal 200. The processor 121A of the management controller 120A waits for a management operation command from the management terminal 200 (S51). When the processor 121A receives a management operation command, it determines its contents, including its type (S52).

[0082] Next, processor 121A accesses FPGA 150A in its own system and obtains information on the estimated processor utilization rate of both systems from temporary data 151 stored in the RAM of FPGA 150A (S53). Next, processor 121A refers to the user LAN bandwidth control reference table, which is a management table, and controls the bandwidth of the user LAN, which is the communication path with the management terminal 200 (S54).

[0083] Figure 10 shows an example configuration of the User LAN Bandwidth Control Reference Table 127. The User LAN Bandwidth Control Reference Table 127 includes a Total Processor Utilization Column 271 and a Bandwidth Limit Column 272. The User LAN Bandwidth Control Reference Table 127 defines the relationship between the total processor utilization of all disk controllers (in this case, two disk controllers) and the communication bandwidth limit in the communication path with the management terminal 200. The Bandwidth Limit Column 272 shows the percentage of the specified bandwidth (maximum bandwidth) of the communication path between the management terminal 200 and the storage system 110 that is available. The larger the total processor utilization, the smaller the communication bandwidth allocated.

[0084] In the example in Figure 10, the total processor utilization column 271 for both systems shows values ​​in descending order of 5% increments. Each record shows information for a specific processor utilization range. For example, each record defines a bandwidth limit and estimated processor utilization for processor utilization in a range that is less than or equal to the value shown in the power consumption column 154 and greater than the value in the record immediately below it.

[0085] Furthermore, records of more detailed power consumption values ​​may be included, and functions that display similar information may be defined. A function may be defined that takes the processor utilization of a disk controller as a variable, which is different from the total processor utilization of all disk controllers. For example, the maximum processor utilization may be associated with the bandwidth limit value.

[0086] Returning to Figure 9, in step S54, the processor 121A of the management controller 120A calculates the sum of the current processor utilization rates of both systems and determines the associated bandwidth limit value in the user LAN bandwidth control reference table 127. The processor 121A sets the determined bandwidth limit value for the connection port of the switch 140A to the external switch 210A.

[0087] Next, processor 121A compares the sum of the processor utilization rates of both systems with a threshold (S55). The threshold may be, for example, 200% of the maximum value, or a smaller value. If the total processor utilization rate is greater than or equal to the threshold (S55: YES), processor 121A rejects a predefined specific management operation command and returns an error response (S56: YES). Processor 121A accepts management operation commands other than the specific management operation command (S56: NO). For example, normal reference commands are permitted, while configuration commands and commands with a large amount of data transfer (exceeding the threshold), such as firmware updates and dump data acquisition, are rejected.

[0088] For example, the following reference-based management command is permitted. Get Pool Get Volume Get Snapshot Get Server Get Performance Volume Get PerformanceCache

[0089] The following configuration management commands and commands with large data transfer volumes will be rejected. Set / Delete Pool Set / Delete Volume Set / Delete Snapshot Set / Delete Server Dump Firmware Update

[0090] If the combined processor utilization of both systems is below a threshold (S55:NO), or if the received management operation command is different from a specific management operation command (S56:NO), it is determined that the received management operation command will be processed. Processor 121A starts a timer for a predetermined time (e.g., 1 minute) (S57), and generates and issues an internal command.

[0091] If the timer expires before all internal commands have finished (S58: NO, S59: YES), the flow returns to step S53. Once all internal commands have been issued (S58: YES), this flow terminates.

[0092] As described above, controlling the user LAN bandwidth based on the processor utilization of the disk controller effectively suppresses the impact of management command processing on host I / O. Furthermore, rejecting certain management commands when the disk controller load exceeds a threshold effectively suppresses the impact of management command processing on host I / O. Note that either controlling the user LAN bandwidth based on processor utilization or allowing / rejecting management commands may be performed alone.

[0093] The present invention is not limited to the embodiments described above, and various modifications are included. For example, the embodiments described above are described in detail for the purpose of clearly illustrating the present invention, and are not necessarily limited to those having all the configurations described. Furthermore, it is possible to replace parts of the configuration of one embodiment with the configuration of another embodiment, and it is also possible to add configurations from other embodiments to the configuration of one embodiment. In addition, it is possible to add, delete, or replace parts of the configuration of each embodiment with other configurations.

[0094] Furthermore, each of the above-mentioned configurations, functions, and processing units may be implemented in hardware, either partially or entirely, by designing them as integrated circuits, for example. Alternatively, each of the above-mentioned configurations and functions may be implemented in software by having the processor interpret and execute programs that implement each function. Information such as programs, tables, and files that implement each function can be stored in memory, a recording device such as a hard disk or SSD (Solid State Drive), or a recording medium such as an IC card or SD card.

[0095] Furthermore, the control lines and information lines shown are those deemed necessary for explanatory purposes, and not all control lines and information lines are necessarily shown in the actual product. In practice, it is reasonable to assume that almost all components are interconnected. [Explanation of symbols]

[0096] 100 Storage Systems 120A, 120B Management Controller 121A, 121B processors 130A, 130B Disk Controllers 133A, 133B Main Processor 140A, 140B switches Ports 141A and 141B 150A, 150B FPGA 200 management terminals 210 switches

Claims

1. It is a storage system, Management system and Includes one or more disk controllers that process read and write requests from a host device, The aforementioned management system is The processor load of the one or more disk controllers is monitored, Receive management operation commands from the management terminal, A storage system that controls the amount of communication between the management system and the one or more disk controllers for internal commands corresponding to the management operation commands, based on the processor load.

2. A storage system according to claim 1, The management system is a storage system that obtains power consumption information from one or more disk controllers and determines the processor load based on the power consumption.

3. A storage system according to claim 1, The management system is a storage system that controls the communication bandwidth between the management system and the one or more disk controllers in controlling the amount of communication.

4. A storage system according to claim 1, The aforementioned one or more disk controllers are multiple disk controllers, The management system is a storage system that controls the ratio of issuing internal commands to the multiple disk controllers in controlling the amount of communication.

5. A storage system according to claim 4, The management system is a storage system that controls the communication bandwidth between the management system and each of the plurality of disk controllers in controlling the amount of communication.

6. A storage system according to claim 4, The management system further controls the proportion of internal commands issued to the multiple disk controllers based on the type of management operation command, and is a storage system.

7. A storage system according to claim 1, The management system is a storage system that controls the communication bandwidth between itself and the management terminal based on the processor load.

8. A storage system according to claim 1, The management system is a storage system that determines whether to allow or deny a management operation command based on the processor load and the type of management operation command from the management terminal.

9. A system control method, The aforementioned system, Management system and Includes one or more disk controllers that process read and write requests from a host device, The aforementioned method, The processor load of the one or more disk controllers is monitored, Receive management operation commands from the management terminal, A method for controlling the amount of communication between the management system and the one or more disk controllers for internal commands corresponding to the management operation commands, based on the processor load.

10. A program that causes a management system to execute a process, wherein the process is: The processor load of one or more disk controllers that process read and write requests from the host device is monitored. Receive management operation commands from the management terminal, A program that controls the amount of communication between the management system and the one or more disk controllers for internal commands corresponding to the management operation commands, based on the processor load.

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