Indication device

Abstract

To provide a display device that can improve yield. [Solution] According to the embodiment, the display device comprises a lower electrode, a partition wall surrounding the lower electrode, a laminated film disposed above the lower electrode, and a sealing layer made of an inorganic insulating material that covers the laminated film and is disposed above the partition wall. In a plan view, the sealing layer has a first side extending in a first direction, a second side extending in a second direction perpendicular to the first direction, and a third side extending in a direction different from the first and second directions and connecting the first and second sides. The angle between the first side and the third side is greater than 90 degrees and less than 180 degrees.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light-emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of improving the yield.

Means for Solving the Problems

[0005] Generally, according to the embodiment, the display device comprises a lower electrode, a partition wall surrounding the lower electrode, a laminated film disposed above the lower electrode, and a sealing layer made of an inorganic insulating material, covering the laminated film and disposed above the partition wall. In a plan view, the sealing layer has a first side extending in a first direction, a second side extending in a second direction perpendicular to the first direction, and a third side extending in a direction different from the first and second directions and connecting the first and second sides. The angle between the first and third sides is greater than 90 degrees and less than 180 degrees.

[0006] In another embodiment, the display device includes a first lower electrode, a second lower electrode, and a third lower electrode; a partition wall surrounding the first lower electrode, the second lower electrode, and the third lower electrode; a first laminated film disposed above the first lower electrode; a second laminated film disposed above the second lower electrode; a first sealing layer made of an inorganic insulating material, covering the first laminated film and disposed above the partition wall; and a second sealing layer made of an inorganic insulating material, covering the second laminated film and disposed above the partition wall. In a plan view, the first sealing layer has a fourth edge extending in a first direction; and the second sealing layer has a fifth edge extending in a second direction perpendicular to the first direction and a sixth edge extending in a direction different from the first and second directions and connected to the fifth edge. The first sealing layer and the second sealing layer form a region overlapping the third lower electrode. The interior angle of the region, which is the angle between the fourth side and the sixth side, is greater than 90 degrees and less than 180 degrees.

[0007] Furthermore, according to another embodiment, the display device includes a first lower electrode, a second lower electrode, and a third lower electrode; a partition wall surrounding the first lower electrode, the second lower electrode, and the third lower electrode; a first laminated film disposed above the first lower electrode; a second laminated film disposed above the second lower electrode; a first sealing layer made of an inorganic insulating material, covering the first laminated film and disposed above the partition wall; and a second sealing layer made of an inorganic insulating material, covering the second laminated film and disposed above the partition wall. In a plan view, the first sealing layer has a fourth side extending in a first direction and a seventh side extending in a direction different from a second direction perpendicular to the first direction and connected to the fourth side. The first sealing layer and the second sealing layer form a region that overlaps the third lower electrode. The interior angle of the region, which is the angle between the fourth side and the seventh side, is greater than 90 degrees and less than 180 degrees.

[0008] Furthermore, according to another embodiment, the device comprises a lower electrode, a partition wall surrounding the lower electrode, a laminated film disposed above the lower electrode, and a sealing layer made of an inorganic insulating material, covering the laminated film and disposed above the partition wall. In a plan view, the sealing layer has a first side extending in a first direction, a second side extending in a second direction perpendicular to the first direction, and an arc-shaped curved portion connecting the first side and the second side. [Brief explanation of the drawing]

[0009] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of the layout of subpixels that make up a single pixel. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic cross-sectional view of another example of a display device along line III-III in Figure 2. [Figure 5] Figure 5 is a schematic plan view showing an example of a configuration applicable to the partition wall and sealing layer according to the first embodiment. [Figure 6] Figure 6 is a schematic enlarged view of part VI in Figure 5. [Figure 7] Figure 7 is a schematic plan view for explaining another example of the sealing layer. [Figure 8] Figure 8 is a flowchart showing an example of a method for manufacturing a display device. [Figure 9A] Figure 9A is a schematic cross-sectional view showing the manufacturing process of the display device. [Figure 9B] Figure 9B is a schematic cross-sectional view showing the process following Figure 9A. [Figure 9C] Figure 9C is a schematic cross-sectional view showing the process following Figure 9B. [Figure 9D] Figure 9D is a schematic cross-sectional view showing the process following Figure 9C. [Figure 9E] Figure 9E is a schematic cross-sectional view showing the process following Figure 9D. [Figure 9F] Figure 9F is a schematic cross-sectional view showing the process following Figure 9E. [Figure 9G] Figure 9G is a schematic cross-sectional view showing the process following Figure 9F. [Figure 9H] Figure 9H is a schematic cross-sectional view showing the process following Figure 9G. [Figure 9I] Figure 9I is a schematic cross-sectional view showing the process following Figure 9H. [Figure 9J] Figure 9J is a schematic cross-sectional view showing the process following Figure 9I. [Figure 10A] Figure 10A is a schematic plan view showing the manufacturing process of the display device. [Figure 10B] Figure 10B is a schematic plan view showing the process following Figure 10A. [Figure 10C] Figure 10C is a schematic plan view showing the process following Figure 10B. [Figure 10D] Figure 10D is a schematic plan view showing the process following Figure 10C. [Figure 10E] Figure 10E is a schematic plan view showing the process following Figure 10D. [Figure 11]Figure 11 is a schematic enlarged view of section XI in Figure 10D. [Figure 12A] Figure 12A is a schematic plan view showing the manufacturing process of a comparative example of a display device. [Figure 12B] Figure 12B is a schematic plan view showing the process following Figure 12A. [Figure 12C] Figure 12C is a schematic plan view showing the process that follows Figure 12B. [Figure 13] Figure 13 is a schematic plan view of the display device according to the second embodiment. [Figure 14] Figure 14 is a schematic enlarged view of section XIV in Figure 13. [Figure 15] Figure 15 is a schematic plan view of the display device according to the third embodiment. [Figure 16] Figure 16 is a schematic enlarged view of section XVI in Figure 15. [Figure 17A] Figure 17A is a schematic plan view showing the manufacturing process of the display device according to the third embodiment. [Figure 17B] Figure 17B is a schematic plan view showing the process following Figure 17A. [Figure 17C] Figure 17C is a schematic plan view showing the process that follows Figure 17B. [Figure 18] Figure 18 is a schematic cross-sectional view of the display device along the line XVIII-XVIII in Figure 17C. [Figure 19] Figure 19 is a schematic cross-sectional view showing another example of a display device according to the fourth embodiment. [Figure 20] Figure 20 is a schematic plan view of the display device according to the fifth embodiment. [Figure 21] Figure 21 is a schematic cross-sectional view of the display device along the line XXI-XXI in Figure 20. [Figure 22] Figure 22 is a schematic enlarged view of section XXII in Figure 20. [Figure 23] Figure 23 is a schematic plan view of a display device according to a comparative example. [Figure 24] Figure 24 is a schematic plan view showing a modified example of the display device. [Modes for carrying out the invention]

[0010] The embodiments will be described below with reference to the drawings. Note that the disclosure is merely an example, and modifications that can be easily conceived by those skilled in the art while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part compared to the actual embodiment in order to clarify the explanation; however, these are merely examples and do not limit the interpretation of the present invention. In this specification and in each drawing, components that perform the same or similar functions as those described above in previously shown drawings are given the same reference numerals, and redundant detailed explanations may be omitted as appropriate. The drawings will include mutually orthogonal X, Y, and Z axes as needed to facilitate understanding. The direction along the X axis will be referred to as the first direction X, the direction along the Y axis as the second direction Y, and the direction along the Z axis as the third direction Z. Viewing the various elements parallel to the third direction Z is called a plan view.

[0011] Each embodiment of the display device is an organic electroluminescent display device equipped with an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as televisions, personal computers, in-vehicle equipment, tablet terminals, smartphones, mobile phone terminals, and wearable terminals.

[0012] [First Embodiment] Figure 1 shows an example configuration of a display device DSP according to this embodiment. The display device DSP includes an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a flexible resin film.

[0013] In this embodiment, the shapes of the substrate 10 and the display area DA in plan view are circular. However, the shapes of the substrate 10 and the display area DA in plan view are not limited to circular, and may be other shapes such as rectangles, squares, or ellipses.

[0014] The display area DA comprises a plurality of pixels PX arranged in a matrix in a first direction X and a second direction Y. Each pixel PX includes a plurality of sub-pixels SP that display different colors. In this embodiment, it is assumed that each pixel PX includes a blue sub-pixel SP1, a green sub-pixel SP2, and a red sub-pixel SP3. Each pixel PX may include sub-pixels SP of other colors, such as white, together with sub-pixels SP1, SP2, and SP3, or in place of any one of sub-pixels SP1, SP2, and SP3.

[0015] The display device DSP further includes a terminal section T located in the peripheral region SA. A flexible circuit board, for example, that supplies voltage and signals for driving the display device DSP, is connected to the terminal section T.

[0016] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0017] The display area DA is arranged with multiple scan lines G that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines S that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines G and power lines PL extend in the first direction X, and the signal lines S extend in the second direction Y.

[0018] The gate electrode of pixel switch 2 is connected to scan line G. One of the source and drain electrodes of pixel switch 2 is connected to signal line S, and the other is connected to the gate electrode of drive transistor 3 and capacitor 4. In drive transistor 3, one of the source and drain electrodes is connected to power line PL and capacitor 4, and the other is connected to display element DE.

[0019] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0020] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3 that constitute a single pixel PX. In the example in Figure 2, sub-pixels SP1 and SP3 are aligned in the second direction Y. Also, sub-pixels SP1 and SP3 are aligned with sub-pixel SP2 in the first direction X.

[0021] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP1 and SP3 are alternately arranged in the second direction Y, and columns in which multiple sub-pixels SP2 are repeatedly arranged in the second direction Y. These columns are arranged alternately in the first direction X. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0022] A rib layer 5 (inorganic insulating layer) is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively.

[0023] In the example in Figure 2, pixel apertures AP1, AP2, and AP3 are all rectangular. The area of ​​pixel aperture AP1 is larger than the area of ​​pixel aperture AP3. Also, the area of ​​pixel aperture AP2 is larger than the area of ​​pixel aperture AP1. Pixel aperture AP2 is a rectangle that is longer in the second direction Y than pixel apertures AP1 and AP3. However, the shapes of pixel apertures AP1, AP2, and AP3 are not limited to this example.

[0024] Sub-pixel SP1 comprises a lower electrode LE1 (first lower electrode), an upper electrode UE1, and an organic layer OR1, each overlapping with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2 (second lower electrode), an upper electrode UE2, and an organic layer OR2, each overlapping with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3 (third lower electrode), an upper electrode UE3, and an organic layer OR3, each overlapping with the pixel aperture AP3.

[0025] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0026] A conductive partition wall 6 is positioned above the rib layer 5. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3. The partition wall 6 overlaps the rib layer 5 overall and has a similar planar shape to the rib layer 5. The partition wall 6 is formed to surround the lower electrodes LE1, LE2, and LE3.

[0027] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line G, signal line S, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0028] The lower electrodes LE1, LE2, and LE3 are positioned on top of the organic insulating layer 12. The rib layer 5 is positioned on top of the organic insulating layer 12 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are each connected to the pixel circuit 1 of the circuit layer 11 through contact holes provided in the organic insulating layer 12.

[0029] The partition wall 6 includes a conductive lower section 61 positioned on the rib layer 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0030] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64.

[0031] Furthermore, in the example shown in Figure 3, the upper section 62 comprises a first top layer 65 and a second top layer 66 positioned on top of the first top layer 65. For example, the width of the second top layer 66 is slightly smaller than the width of the first top layer 65. However, it is not limited to this, and the first top layer 65 and the second top layer 66 may have equivalent widths.

[0032] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the lower part 61 of the partition wall 6.

[0033] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0034] In the following description, the multilayer structure containing the organic layer OR1, the upper electrode UE1, and the cap layer CP1 will be referred to as the multilayer film FL1 (first multilayer film), the multilayer structure containing the organic layer OR2, the upper electrode UE2, and the cap layer CP2 will be referred to as the multilayer film FL2 (second multilayer film), and the multilayer structure containing the organic layer OR3, the upper electrode UE3, and the cap layer CP3 will be referred to as the multilayer film FL3 (third multilayer film). The multilayer films FL1, FL2, and FL3 are located above the lower electrodes LE1, LE2, and LE3. The rib layer 5 is located below the partition wall 6 and the multilayer films FL1, FL2, and FL3.

[0035] Sub-pixels SP1, SP2, and SP3 are each provided with sealing layers SE11, SE12, and SE13, respectively. In this embodiment, sealing layer SE11 corresponds to the first sealing layer, sealing layer SE12 corresponds to the second sealing layer, and sealing layer SE13 corresponds to the third sealing layer.

[0036] The sealing layer SE11 continuously covers the display element DE1 (multilayer film FL1) and the surrounding partition wall 6. The sealing layer SE12 continuously covers the display element DE2 (multilayer film FL2) and the surrounding partition wall 6. The sealing layer SE13 continuously covers the display element DE3 (multilayer film FL3) and the surrounding partition wall 6.

[0037] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion of them extending into the peripheral area SA.

[0038] A cover member, such as a polarizing plate, touch panel, protective film, or cover glass, may be further placed on top of the resin layer RS2. Such a cover member may be bonded to the resin layer RS2 via an adhesive layer, such as OCA (Optical Clear Adhesive). The electrodes constituting the touch panel may be placed on top of the sealing layer SE2.

[0039] In the example shown in Figure 3, the ends of the sealing layers SE11 and SE12 are in contact (tightly attached) above the partition 6 between sub-pixels SP1 and SP2. Also, the ends of the sealing layers SE11 and SE13 are in contact (tightly attached) on the partition 6 between sub-pixels SP1 and SP3. Furthermore, although not shown, the ends of the sealing layers SE12 and SE13 are in contact (tightly attached) on the partition 6 between sub-pixels SP2 and SP3.

[0040] Focusing on the sealing layer SE12, the sealing layer SE12 has an overlapping portion SE121 located above the partition wall 6. The overlapping portion SE121 is in contact with the end of the sealing layer SE11. The overlapping portion SE121 may include a projection 121a that protrudes upward. Above the partition wall 6 between the sub-pixels SP1 and SP2, the projection 121a is located above the sealing layer SE11.

[0041] Furthermore, the superimposed portion SE121 may further include an extension portion 121b that extends toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0042] A laminated film FL2 may be placed between the partition wall 6 and the overlapping portion SE121. However, this laminated film FL2 may disappear during the manufacturing process. In this case, a gap will be created between the sealing layer SE12 and the partition wall 6.

[0043] Similarly, focusing on the sealing layer SE13, the sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6. The overlapping portion SE131 is in contact with the end of the sealing layer SE11. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6 between the sub-pixels SP1 and SP3, the projection 131a is located above the sealing layer SE11.

[0044] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0045] A laminated film FL3 is placed between the partition wall 6 and the overlapping portion SE131. If this laminated film FL3 disappears during the manufacturing process, a gap will be created between the sealing layer SE13 and the partition wall 6.

[0046] Figure 4 is a schematic cross-sectional view of another example of a display device DSP along the line III-III in Figure 2. In Figure 4, the shape of the overlapping portions SE121 and SE131 of the sealing layers SE12 and SE13 differs from the example in Figure 3.

[0047] Focusing on the sealing layer SE12, the protrusion 121a of the sealing layer SE12 may overlap with the sealing layer SE11. In the example in Figure 4, the protrusion 121a includes a portion 121c that overlaps with the sealing layer SE11. In the third direction Z, the partition wall 6, the sealing layer SE11, and the protrusion 121a of the sealing layer SE12 are arranged in this order. The portion 121c may or may not be in contact with the sealing layer SE11.

[0048] Similarly, focusing on the sealing layer SE13, the protrusion 131a of the sealing layer SE13 may overlap with the sealing layer SE11. In the example in Figure 4, the protrusion 131a includes a portion 131c that overlaps with the sealing layer SE11. In the third direction Z, the partition wall 6, the sealing layer SE11, and the protrusion 131a of the sealing layer SE13 are arranged in this order. The portion 131c may or may not be in contact with the sealing layer SE11.

[0049] Although not shown in Figures 3 and 4, focusing on the area above the partition wall 6 between sub-pixels SP2 and SP3, the superimposed portion SE131 may include a projection 131a that protrudes upward. The projection 131a is located above the sealing layer SE12. In the example in Figure 4, above the partition wall 6 between sub-pixels SP2 and SP3, the partition wall 6, the sealing layer SE12, and the projection 131a of the sealing layer SE13 are aligned in this order in the third direction Z.

[0050] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5 and the sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 is formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0051] The lower electrodes LE1, LE2, and LE3 each have a reflective layer made of, for example, silver, and a pair of conductive oxide layers covering the upper and lower surfaces of this reflective layer, respectively. Each conductive oxide layer can be made of a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0052] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0053] The organic layers OR1, OR2, and OR3 are composed of multiple thin films including an emissive layer. In one example, the organic layers OR1, OR2, and OR3 have a structure in which a hole injection layer, a hole transport layer, an electron blocking layer, an emissive layer, a hole blocking layer, an electron transport layer, and an electron injection layer are stacked in the third direction Z in sequence. However, the organic layers OR1, OR2, and OR3 may have other structures, such as a so-called tandem structure including multiple emissive layers.

[0054] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0055] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of a metallic material. For example, the metallic material for the bottom layer 63 can be molybdenum, titanium, titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). For example, the metallic material for the axial layer 64 can be aluminum, aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). The axial layer 64 may also be formed of an insulating material.

[0056] The first top layer 65 of the partition wall 6 is formed of, for example, a metallic material. The second top layer 66 of the partition wall 6 is formed of, for example, a conductive oxide. As the metallic material forming the first top layer 65, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the second top layer 66, for example, ITO or IZO can be used. The upper part 62 may consist of three or more layers, or it may be formed of a single layer. Furthermore, the upper part 62 may include a layer formed of an insulating material.

[0057] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line S through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0058] The organic layers OR1, OR2, and OR3 emit light in response to the application of voltage. Specifically, when a potential difference is formed between the lower electrode LE1 and the upper electrode UE1, the light-emitting layer of organic layer OR1 emits light in the blue wavelength range. When a potential difference is formed between the lower electrode LE2 and the upper electrode UE2, the light-emitting layer of organic layer OR2 emits light in the green wavelength range. When a potential difference is formed between the lower electrode LE3 and the upper electrode UE3, the light-emitting layer of organic layer OR3 emits light in the red wavelength range.

[0059] As another example, the light-emitting layers of organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by the light-emitting layers into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. Alternatively, the display device DSP may include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0060] Figure 5 is a schematic plan view showing an example of a configuration applicable to the partition wall 6 and sealing layers SE11, SE12, and SE13 according to this embodiment. In Figure 5, sealing layer SE11 has a diagonal pattern sloping downwards to the right, sealing layer SE12 has a dot pattern, and sealing layer SE13 has a diagonal pattern sloping upwards to the right. In addition, partition wall 6 has a dot pattern that is coarser than that of sealing layer SE12.

[0061] As shown in Figure 5, the sealing layer SE11 covers the sub-pixel SP1, the sealing layer SE12 covers the sub-pixel SP2, and the sealing layer SE13 covers the sub-pixel SP3. The sealing layers SE11 and SE13 are formed for each sub-pixel SP1 and SP3, respectively. The sealing layer SE12 is formed continuously over multiple sub-pixels SP2 aligned in the second direction Y, for example. The sealing layer SE12 may also be formed for each sub-pixel SP2. As explained using Figure 3, the sealing layers SE11, SE12, and SE13 are not spaced apart from each other.

[0062] The sealing layers SE11 and SE13 have, for example, a polygonal shape in plan view. In the example in Figure 5, the planar shape of the sealing layers SE11 and SE13 is octagonal. The sealing layer SE12 has a main body 12a that overlaps the sub-pixel SP2 and a plurality of extension portions 12b. The extension portions 12b extend from the main body 12a toward the outside of the sub-pixel SP2. Specifically, the plurality of extension portions 12b extend in the second direction Y and in the direction opposite to the second direction Y.

[0063] The outer portion 12b is located at the corner formed by the sealing layer SE11 and the sealing layer SE13. Note that the planar shapes of the sealing layers SE11, SE12, and SE13 are not limited to this example.

[0064] Figure 6 is a schematic enlarged view of section VI in Figure 5. In Figure 6, the focus is mainly on the sealing layer SE13, and other elements such as the sealing layers SE11 and SE12 are omitted.

[0065] In a plan view, the sealing layer SE13 has two sides L1, two sides L2, two sides L31, and two sides L32. In this embodiment, side L1 corresponds to the first side, side L2 corresponds to the second side, and side L31 corresponds to the third side.

[0066] Edge L1 corresponds to the edge facing the end of the sealing layer SE11. Specifically, edge L1 corresponds to the edge touching the end of the sealing layer SE11. Edges L2, L31, and L32 correspond to the edges facing the end of the sealing layer SE12. Specifically, edges L2, L31, and L32 correspond to the edges touching the end of the sealing layer SE12.

[0067] Edge L1 extends in the first direction, and edge L2 extends in the second direction. Edges L31 and L32 extend in directions different from the first direction X and the second direction Y. Edge L31 extends in a direction D1 that intersects the first direction X at an acute angle counterclockwise, for example. Edge L32 extends in a direction D2 that intersects the first direction X at an acute angle clockwise, for example.

[0068] Edges L31 and L32 connect edges L1 and L2. Here, "connected" includes not only cases where each element is directly connected, but also cases where it is connected through other elements. In the example in Figure 6, edges L31 and L32 are directly connected to edges L1 and L2, respectively.

[0069] Furthermore, focusing on the relationship with partition wall 6, sides L1, L2, L31, and L32 overlap with partition wall 6, respectively. In other words, sides L1, L2, L31, and L32 are located above the upper part 62 of partition wall 6. Also, from another perspective, sides L1, L2, L31, and L32 do not overlap with the opening of partition wall 6.

[0070] Here, we focus on the corner portion CN3 formed by sides L1 and L31, and define the angle between sides L1 and L31 as angle θ1. Focusing on the sealing layer SE13, angle θ1 corresponds to the interior angle of the sealing layer SE13. Angle θ1 is, for example, an obtuse angle. In other words, angle θ1 is greater than 90 degrees and less than 180 degrees (90 degrees < θ1 < 180 degrees). For example, angle θ1 is between 120 degrees and 150 degrees (120 degrees < θ1 < 150 degrees). More specifically, angle θ1 is 135 degrees.

[0071] Figure 7 is a schematic plan view illustrating another example of the sealing layer SE13. In Figure 7, a magnified view of the corner portion CN3 of the sealing layer SE13 is shown.

[0072] The sealing layer SE13 may further have a curved portion RL1. The curved portion RL1 has an arc shape (round shape). The curved portion RL1 connects side L1 and side L31. In other words, side L31 of the sealing layer SE13 is connected to side L1 via the curved portion RL1.

[0073] In this case, angle θ1 corresponds to the angle formed by the extension line L1E of side L1 and the extension line L3E of side L31. That is, angle θ1 includes not only the angle of the corner CN3 when side L1 and side L31 are directly connected, but also the angle of the corner CN3 when the extension line L1E of side L1 and the extension line L3E of side L31 are connected.

[0074] Although Figures 6 and 7 describe one corner portion CN3 of the sealing layer SE13, the other corner portions of the sealing layer SE13 are constructed in a similar manner.

[0075] Next, an example of a method for manufacturing a display device DSP will be described. Figure 8 is a flowchart of an example of a method for manufacturing a display device DSP. Figures 9A to 9J are schematic cross-sectional views showing the manufacturing process of a display device DSP. In Figures 9A to 9J, the focus is mainly on the display area DA, and elements below the organic insulating layer 12 are omitted.

[0076] In forming the DSP display device, first a circuit layer 11 and an organic insulating layer 12 are formed on the substrate 10 (step PR1 in Figure 8). Next, as shown in Figure 9A, lower electrodes LE1, LE2, and LE3 are formed on the organic insulating layer 12 (step PR2 in Figure 8).

[0077] Next, as shown in Figure 9B, a rib layer 5 is formed covering the lower electrodes LE1, LE2, and LE3 (step PR3 in Figure 8). At this point, the pixel apertures AP1, AP2, and AP3 are not yet provided on the rib layer 5. The rib layer 5 can be formed by CVD (Chemical Vapor Deposition).

[0078] After the formation of the rib layer 5, a process for forming the partition wall 6 is carried out (process PR4 in Figure 8). In process PR4, as shown in Figure 9C, the first layer BL1 for processing into the bottom layer 63, the second layer BL2 for processing into the axial layer 64, the third layer BL3 for processing into the first top layer 65, and the fourth layer BL4 for processing into the second top layer 66 are formed in order. Furthermore, a resist R1 is placed on top of the fourth layer BL4. The resist R1 is patterned to the shape of the partition wall 6. The first layer BL1, the second layer BL2, the third layer BL3, and the fourth layer BL4 can be formed, for example, by sputtering.

[0079] Subsequently, the first layer BL1, the second layer BL2, the third layer BL3, and the fourth layer BL4 are patterned using the resist R1 as a mask. In one example, the first layer BL1 is formed of titanium nitride, the second layer BL2 is formed of aluminum, the third layer BL3 is formed of titanium, and the fourth layer BL4 is formed of ITO. In this case, the patterning may include wet etching to remove the portion of the fourth layer BL4 exposed from the resist R1, dry etching to remove the portions of the first layer BL1, the second layer BL2, and the third layer BL3 exposed from the resist R1, and wet etching to reduce the width of the second layer BL2.

[0080] After step PR4, a partition wall 6 is formed in the display area DA, as shown in Figure 9D. After the formation of the partition wall 6, the resist R1 is removed (peeled off). In the wet etching process described above, which reduces the width of the second layer BL2, the second top layer 66 (fourth layer BL4) may also be slightly eroded. If this erosion occurs, the width of the second top layer 66 becomes smaller than the width of the first top layer 65.

[0081] Next, a process is carried out to create pixel apertures AP1, AP2, and AP3 (process PR5 in Figure 8). In this process PR5, a resist R2 is formed to cover the partition wall 6, as shown in Figure 9E. Furthermore, dry etching is performed on the rib layer 5 using the resist R2 as a mask. As a result, pixel apertures AP1, AP2, and AP3 that expose the lower electrodes LE1, LE2, and LE3 are formed on the rib layer 5, as shown in Figure 9F. After the dry etching, the resist R2 is removed (peeled off).

[0082] After step PR5, a process for forming the display element DE1 is carried out (step PR6 in Figure 8). In forming the display element DE1, first, as shown in Figure 9G, a laminated film FL1 and a sealing layer SE11 are formed. As shown in Figure 3, the laminated film FL1 includes an organic layer OR1 that contacts the lower electrode LE1 through the pixel aperture AP1, an upper electrode UE1 that covers the organic layer OR1, and a cap layer CP1 that covers the upper electrode UE1. The organic layer OR1, the upper electrode UE1, and the cap layer CP1 can be formed, for example, by vapor deposition. The sealing layer SE11 can be formed, for example, by CVD.

[0083] The laminated film FL1 and the sealing layer SE11 are formed not only in the display area DA but also in the peripheral area SA. The laminated film FL1 is divided into multiple parts by overhanging partition walls 6. The sealing layer SE11 continuously covers each divided part of the laminated film FL1 and the partition walls 6.

[0084] Next, the multilayer film FL1 and the sealing layer SE11 are patterned. In this patterning process, as shown in Figure 9G, a resist R3 is placed on top of the sealing layer SE11. The resist R3 covers the subpixel SP1 and a portion of the surrounding partition wall 6.

[0085] Subsequently, an etching process is performed using resist R3 as a mask. As a result, as shown in Figure 9H, the portions of the multilayer film FL1 and the sealing layer SE11 exposed from resist R3 are removed, and the display element DE1 is formed on the sub-pixel SP1. This etching process includes wet etching and dry etching performed sequentially on the sealing layer SE11, the cap layer CP1, the upper electrode UE1, and the organic layer OR1. After these etchings, resist R3 is removed (peeled off).

[0086] Furthermore, during wet etching of the multilayer film FL1, the portion of the multilayer film FL1 located above the partition wall 6 and below the sealing layer SE11 is also removed. This creates a gap between the sealing layer SE11 above the partition wall 6 and the partition wall 6. Since the multilayer film FL1 constituting the display element DE1 is completely surrounded by the sealing layer SE11 and the partition wall 6, it is not eroded by the wet etching described above.

[0087] Prior to the wet etching described above, a laminated film FL1 is also formed in the gap between the partition wall 6 and the sealing layer SE11. This laminated film FL1 in the gap is removed during the wet etching process by the etching solution penetrating from near the edge of the sealing layer SE11 downwards.

[0088] After step PR6, a process for forming the display element DE2 is carried out (step PR7 in Figure 8). The display element DE2 can be formed using the same procedure as the display element DE1. That is, in forming the display element DE2, the multilayer film FL2 and the sealing layer SE12 are formed over the entire display area DA and peripheral area SA. As shown in Figure 3, the multilayer film FL2 includes an organic layer OR2 that contacts the lower electrode LE2 through the pixel aperture AP2, an upper electrode UE2 that covers the organic layer OR2, and a cap layer CP2 that covers the upper electrode UE2.

[0089] The organic layer OR2, the upper electrode UE2, and the cap layer CP2 can be formed, for example, by vapor deposition. The sealing layer SE12 can be formed, for example, by CVD. The multilayer film FL2 is divided into multiple parts by overhanging partitions 6. The sealing layer SE12 continuously covers each divided part of the multilayer film FL2 and the partitions 6. By patterning the multilayer film FL2 and the sealing layer SE12, a display element DE2 is formed on the sub-pixel SP2, as shown in Figure 9I.

[0090] Above the partition wall 6 between sub-pixels SP1 and SP2, the ends of the sealing layers SE11 and SE12 are in contact. When sealing layer SE12 is formed to be in contact with sealing layer SE11, a protrusion 121a may be formed on the superimposed portion SE121 of sealing layer SE12, which is formed in a later process than sealing layer SE11. Furthermore, an extension 121b may be formed on sealing layer SE12 that extends toward the gap G1 formed between sealing layer SE11 and the upper part 62 of the partition wall 6.

[0091] Furthermore, a laminated film FL2 is also formed in the gap between the partition wall 6 and the sealing layer SE12. This laminated film FL2 in the gap is removed during wet etching by the etching solution penetrating from near the edge of the sealing layer SE12 downwards.

[0092] After step PR7, a process for forming the display element DE3 is carried out (step PR8 in Figure 8). The display element DE3 can be formed using the same procedure as the display elements DE1 and DE2.

[0093] In other words, in the formation of the display element DE3, the multilayer film FL3 and the sealing layer SE13 are formed over the entire display area DA and the peripheral area SA. As shown in Figure 3, the multilayer film FL3 includes an organic layer OR3 that contacts the lower electrode LE3 through the pixel aperture AP3, an upper electrode UE3 that covers the organic layer OR3, and a cap layer CP3 that covers the upper electrode UE3.

[0094] The organic layer OR3, the upper electrode UE3, and the cap layer CP3 can be formed, for example, by vapor deposition. The sealing layer SE13 can be formed, for example, by CVD. The multilayer film FL3 is divided into multiple parts by overhanging partitions 6. The sealing layer SE13 continuously covers each divided part of the multilayer film FL3 and the partitions 6. By patterning the multilayer film FL3 and the sealing layer SE13, a display element DE3 is formed on the sub-pixel SP3, as shown in Figure 9J.

[0095] Above the partition wall 6 between the sub-pixels SP1 and SP3, the ends of the sealing layers SE11 and SE13 are in contact. When the sealing layer SE13 is formed to be in contact with the sealing layer SE11, the sealing layer SE13, which is formed in a later process than the sealing layer SE11, may have a protruding portion 131a formed on the overlapping portion SE131. Furthermore, the sealing layer SE13 may have an extension portion 131b that extends toward the gap G1 formed between the sealing layer SE11 and the upper part 62 of the partition wall 6.

[0096] As shown in Figure 9J, a laminated film FL3 is formed in the gap between the partition wall 6 and the sealing layer SE13. Because the edges of the sealing layer SE11 and the sealing layer SE13 are in contact with each other, penetration of the etching solution from near the edge of the sealing layer SE13 downwards is suppressed during wet etching. As a result, the laminated film FL3 remains in the gap.

[0097] Furthermore, the gap is surrounded not only by the partition wall 6 and the overlapping portion SE131, but also by the extension portion 131b. This further suppresses the penetration of the etching solution into the gap.

[0098] Furthermore, if the sealing layer SE13 is formed above the partition wall 6 between the sub-pixels SP2 and SP3 so as to be in contact with the sealing layer SE12, the sealing layer SE13 formed in a later process than the sealing layer SE12 may have a protruding portion 131a on the superimposed portion SE131, and an extended portion 131b extending toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6.

[0099] Furthermore, in the examples shown in Figures 9I and 9J, the portion 121c of the sealing layer SE12 that overlaps with the sealing layer SE11 shown in Figure 4 and the portion 131c of the sealing layer SE13 that overlaps with the sealing layer SE11 are removed, but the patterning may be done so that portions 121c and 131c remain.

[0100] After step PR8, resin layer RS1, encapsulation layer SE2, and resin layer RS2 are formed in sequence (step PR9 in Figure 8). For the formation of resin layers RS1 and RS2, for example, an inkjet method can be used. For the formation of encapsulation layer SE2, for example, CVD can be used.

[0101] In this embodiment, it is assumed that the display elements DE1, DE2, and DE3 are formed in this order. In this case, display element DE1 corresponds to the first color display element, display element DE2 corresponds to the second color display element, and display element DE3 corresponds to the third color display element.

[0102] Here, we focus on the sealing layers SE11, SE12, and SE13 in steps PR6 to PR8 in Figure 8. Figures 10A to 10E are schematic plan views showing the manufacturing process of a DSP display device.

[0103] In step PR6 in Figure 8, as shown in Figure 10A, the sealing layer SE11 is formed over the entire display area DA. After step PR6 in Figure 8, the sealing layer SE11 is formed as shown in Figure 10B. As described above, the sealing layer SE11 has an octagonal shape.

[0104] In step PR7 of Figure 8, as shown in Figure 10C, the sealing layer SE12 is formed over the entire display area DA. After step PR7 of Figure 8, the sealing layer SE12 as shown in Figure 10D is formed. In the patterning of step PR7, a plurality of extension portions 12b are formed.

[0105] Figure 11 is a schematic enlarged view of section XI in Figure 10D. The sealing layer SE11 has an edge L4, and the sealing layer SE12 has edges L5, L61, and L62. In this embodiment, edge L4 corresponds to the fourth edge, edge L5 corresponds to the fifth edge, and edge L61 corresponds to the sixth edge.

[0106] Edge L4 extends in the first direction X. Edge L5 extends in the second direction Y. Edges L61 and L62 are part of the outer extension 12b. Edges L61 and L62 are connected to edge L5. Edges L61 and L62 extend in directions different from the first direction X and the second direction Y.

[0107] Edge L61 extends in a direction D1 that intersects the first direction X at an acute angle counterclockwise, for example. Edge L62 extends in a direction D2 that intersects the first direction X at an acute angle clockwise, for example. In the example in Figure 11, edges L61 and L62 are directly connected to edge L5, but edges L61 and L62 may also be connected to edge L5 via other edges.

[0108] Furthermore, focusing on the relationship with partition wall 6, edges L4, L5, L61, and L62 overlap with partition wall 6, respectively. In other words, edges L4, L5, L61, and L62 are located above the upper part 62 of partition wall 6.

[0109] Focusing on the sealing layer SE13, edge L4 corresponds to the edge adjacent to edge L1 (shown in Figure 6) of the sealing layer SE13. Also, edge L5 corresponds to the edge adjacent to edge L2 (shown in Figure 6) of the sealing layer SE13, edge L61 corresponds to the edge adjacent to edge L31 (shown in Figure 6) of the sealing layer SE13, and edge L62 corresponds to the edge adjacent to edge L32 (shown in Figure 6) of the sealing layer SE13.

[0110] Here, we define the angle between edge L4 and edge L61 as angle θ2. We also define the region enclosed by sealing layers SE11 and SE12 as region A3. In other words, sealing layers SE11 and SE12 form region A3. Region A3 corresponds to the region overlapping with the sub-pixel SP3 (lower electrode LE3). The planar shape of region A3 is octagonal.

[0111] Focusing on region A3, angle θ2 corresponds to the interior angle of region A3. Angle θ2 is, for example, an obtuse angle. In other words, angle θ2 is greater than 90 degrees and less than 180 degrees (90 degrees < θ2 < 180 degrees). For example, angle θ2 is greater than or equal to 120 degrees and less than or equal to 150 degrees (120 degrees < θ2 < 150 degrees). More specifically, angle θ2 is 135 degrees. In this case, the angle between sides L61 and L62 (the interior angle of the sealing layer SE12) is 90 degrees. Note that the other interior angles in region A3 are constructed in a similar manner to angle θ2.

[0112] In step PR8 in Figure 8, the sealing layer SE13 is formed over the entire display area DA, as shown in Figure 10E. After step PR8 in Figure 8, the sealing layer SE13 is formed as shown in Figure 5.

[0113] According to this embodiment, it is possible to improve the yield of the display device DSP.

[0114] Figures 12A to 12C are schematic plan views showing the manufacturing process of a display device according to a comparative example of this embodiment. In Figures 12A to 12C, as in Figures 10A to 10E, the focus is on the sealing layers SE11, SE12, and SE13.

[0115] In the comparative example, as shown in Figure 12A, a sealing layer SE11 is formed to cover the laminated film FL1 of the display element DE1. The sealing layer SE11 has a rectangular shape in plan view. Subsequently, a process for forming the display element DE2 is carried out. In the comparative example, as shown in Figure 12B, a sealing layer SE12 is formed to cover a plurality of subpixels SP2. Focusing on the corner portion CN5 formed by the sealing layer SE11 and the sealing layer SE12, the corner portion CN5 is formed at a right angle.

[0116] Subsequently, a process for forming the display element DE3 is carried out. In forming the display element DE3, as shown in Figure 12C, the multilayer film FL3 and the sealing layer SE13 are formed over the entire display area DA. Then, a resist is applied to process the multilayer film FL3 and the sealing layer SE13. When applying the resist, air bubbles are likely to form in the area that overlaps with the corner portion CN5.

[0117] If the process for forming the display element DE3 is carried out while air bubbles are present, the bubbles will burst during the reduced-pressure drying of the resist used to pattern the multilayer film FL3 and the sealing layer SE13, exposing area A5 (shown in Figure 12C), which should be covered by the resist. This could result in defects in the display area DA.

[0118] In contrast, as shown in Figure 11, in the DSP display device according to this embodiment, the interior angle (angle θ2) of region A3 formed by the sealing layers SE11 and SE12 is formed as an obtuse angle. Therefore, a sealing layer SE13 having an obtuse angle θ1 (interior angle) is formed.

[0119] This allows air to easily escape from the corner area CN5 when the resist is applied to pattern the multilayer film FL3 and the sealing layer SE13. In other words, in step PR8, air bubbles are less likely to form in the corner area CN5 (the inner corner of region A3), and the resist flows in easily.

[0120] As a result, the cracking of the resist in process PR8 can be suppressed. In other words, the area A5 that should be covered by the resist is less likely to be exposed. In this embodiment, the occurrence of malfunctions in the display device DSP can be suppressed and the yield of the display device DSP can be improved.

[0121] Next, other embodiments will be described. In the other embodiments described below, components similar to those in the first embodiment described above will be given the same reference numerals as in the first embodiment, and their detailed descriptions may be omitted or simplified.

[0122] [Second Embodiment] Figure 13 is a schematic plan view of the display device DSP according to this embodiment. Figure 14 is a schematic enlarged view of section XIV in Figure 13. In Figure 14, the focus is mainly on the sealing layers SE11 and SE12, and other elements such as the sealing layer SE13 are omitted. In this embodiment, the shapes of the sealing layers SE11 and SE12 differ from those of the first embodiment.

[0123] The sealing layer SE11 has a rectangular shape in plan view. As shown in Figure 14, the sealing layer SE11 has a side L4 extending in the first direction X. The sealing layer SE12 is formed continuously over a plurality of subpixels SP2 aligned, for example, in the second direction Y.

[0124] As shown in Figure 14, the sealing layer SE12 has a plurality of extension portions 12b. The shape of the extension portions 12b in this embodiment is different from the shape of the extension portions 12b in the first embodiment.

[0125] The sealing layer SE12 has edges L5, L61, and L62. The extension portion 12b includes an extension portion 12b containing edge L61 and an extension portion 12b containing edge L62. As shown in Figure 14, the sealing layer SE12 further has edge L63 in the extension portion 12b. Edge L63 extends in the first direction X along edge L4 of the sealing layer SE11. Edges L61 and L62 are connected to edge L63, respectively.

[0126] In this embodiment as well, the angle θ2 is, for example, an obtuse angle. In other words, the angle θ2 is greater than 90 degrees and less than 180 degrees (90 degrees < θ2 < 180 degrees). For example, the angle θ2 is 120 degrees or more and 150 degrees or less (120 degrees < θ2 < 150 degrees). More specifically, the angle θ2 is 135 degrees. The sealing layer SE13 in this embodiment has the same shape as the sealing layer SE13 in the first embodiment.

[0127] In this embodiment as well, the same effects as in the first embodiment can be obtained. In this embodiment as well, the angle θ2 is formed as an obtuse angle. This makes it easier for air to escape from the corner portion CN5 when the resist for patterning the laminated film FL3 and the sealing layer SE13 is applied. As a result, it is possible to suppress the resist from bursting in step PR8 in Figure 8. With this embodiment, it is possible to suppress the occurrence of malfunctions in the display device DSP and improve the yield of the display device DSP.

[0128] [Third Embodiment] Figure 15 is a schematic plan view of the display device DSP according to this embodiment. Figure 16 is a schematic enlarged view of section XVI in Figure 15. In Figure 16, the focus is mainly on the sealing layers SE11 and SE12, and other elements such as the sealing layer SE13 are omitted. In this embodiment, the shapes of the sealing layers SE11 and SE12 differ from those of the first embodiment.

[0129] As shown in Figure 15, the sealing layer SE12 is formed continuously across a plurality of subpixels SP2 aligned in the second direction Y. The sealing layer SE12 in this embodiment does not have an element corresponding to the extension portion 12b in the first embodiment. As shown in Figure 16, the sealing layer SE12 has a pair of sides L5 extending in the second direction.

[0130] As shown in Figure 16, the sealing layer SE11 has a main body 11a that overlaps the sub-pixel SP1 and a plurality (four) of extension portions 11b. The extension portions 11b are formed, for example, by patterning in process PR6. The extension portions 11b extend from the main body 11a toward the outside of the sub-pixel SP1. Specifically, the plurality of extension portions 11b extend in the second direction Y and in the direction opposite to the second direction Y.

[0131] Multiple extensions 11b are positioned above the partition wall 6. The sealing layer SE11 has two sides L4, two sides L71, and two sides L72. In this embodiment, side L4 corresponds to the fourth side, and side L71 corresponds to the seventh side.

[0132] Edge L4 corresponds to the edge adjacent to edge L1 (shown in Figure 6) of the sealing layer SE13, edge L71 corresponds to the edge adjacent to edge L31 (shown in Figure 6) of the sealing layer SE13, and edge L72 corresponds to the edge adjacent to edge L32 (shown in Figure 6) of the sealing layer SE13. The extension portion 11b includes an extension portion 11b containing edge L71 and an extension portion 11b containing edge L72. Edges L71 and L72 extend in directions different from the first direction X and the second direction Y.

[0133] Edge L71 extends in a direction D1 that intersects the first direction X at an acute angle counterclockwise, for example. Edge L72 extends in a direction D2 that intersects the first direction X at an acute angle clockwise, for example. Edges L71 and L72 are directly connected to edge L4, but they may also be connected to edge L4 via other edges.

[0134] Furthermore, focusing on the relationship with partition wall 6, edges L4, L71, and L72 overlap with partition wall 6, respectively. In other words, edges L4, L71, and L72 are located above the upper part 62 of partition wall 6.

[0135] Here, we define angle θ3 as the angle between side L4 and side L71. Focusing on region A3, angle θ3 corresponds to the interior angle of region A3. Angle θ3 is, for example, an obtuse angle. In other words, angle θ3 is greater than 90 degrees and less than 180 degrees (90 degrees < θ3 < 180 degrees). For example, angle θ3 is between 120 degrees and 150 degrees (120 degrees < θ3 < 150 degrees). More specifically, angle θ3 is 135 degrees. Note that the other interior angles in region A3 are constructed in a similar manner to angle θ3.

[0136] In this embodiment, the same effects as in the first embodiment can be obtained. In this embodiment, the angle θ3 is formed as an obtuse angle. This makes it easier for air to escape from the corner portion CN5 when the resist for patterning the laminated film FL3 and the sealing layer SE13 is applied. As a result, it is possible to suppress the resist from bursting in step PR8 in Figure 8. With this embodiment, it is possible to suppress the occurrence of malfunctions in the display device DSP and improve the yield of the display device DSP.

[0137] [Fourth Embodiment] Next, a fourth embodiment will be described. In the embodiments described above, it was assumed that the display elements DE1, DE2, and DE3 were formed in that order. In this embodiment, it is assumed that the display element DE2 is formed first, and the display elements DE1 and DE3 are formed afterward. In this embodiment, the display element DE2 corresponds to the first color display element, the display element DE1 corresponds to the second color display element, and the display element DE3 corresponds to the third color display element. Even in this case, the phenomenon of the resist popping described above may occur when the display element DE3 is formed.

[0138] Figures 17A to 17C are schematic plan views showing the manufacturing process of the DSP display device according to this embodiment.

[0139] As shown in Figure 17A, the sealing layer SE12 is formed in the display area DA. After the display element DE2 is formed, the sealing layer SE11 is formed as shown in Figure 17B. The sealing layer SE11 has a plurality of extension portions 11b. After the display element DE1 is formed, the sealing layer SE13 is formed as shown in Figure 17C.

[0140] Figure 18 is a schematic cross-sectional view of the display device DSP along the line XVIII-XVIII in Figure 17C.

[0141] In this embodiment as well, the ends of the sealing layers SE11 and SE12 are in contact with each other above the partition wall 6 between the sub-pixels SP1 and SP2. Furthermore, the ends of the sealing layers SE11 and SE13 are in contact with each other on the partition wall 6 between the sub-pixels SP1 and SP3. In addition, although not shown, the ends of the sealing layers SE12 and SE13 are in contact with each other on the partition wall 6 between the sub-pixels SP2 and SP3.

[0142] Focusing on the sealing layer SE11, the sealing layer SE11 has an overlapping portion SE111 located above the partition wall 6. The overlapping portion SE111 may include a protruding portion 111a (third protruding portion) that protrudes upward. Above the partition wall 6 between the sub-pixels SP1 and SP2, the protruding portion 111a is located above the sealing layer SE12.

[0143] Furthermore, the superimposed portion SE111 may further include an extension portion 111b that extends toward the gap G2 formed between the sealing layer SE12 and the upper part 62 of the partition wall 6. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0144] A laminated film FL1 may be placed between the partition wall 6 and the overlapping portion SE111. Note that this laminated film FL1 may disappear during the manufacturing process. In this case, a gap will be created between the sealing layer SE11 and the partition wall 6.

[0145] Similarly, focusing on the sealing layer SE13, the sealing layer SE13 has an overlapping portion SE131 located above the partition wall 6. The overlapping portion SE131 may include a projection 131a that protrudes upward. Above the partition wall 6 between the sub-pixels SP1 and SP3, the projection 131a is located above the sealing layer SE11.

[0146] Furthermore, the superimposed portion SE131 may further include an extension portion 131b that extends toward the gap formed between the sealing layer SE11 and the upper part 62 of the partition wall 6. This gap is created when the laminated film FL1 disappears during the manufacturing process.

[0147] A laminated film FL3 is placed between the partition wall 6 and the overlapping portion SE131. If this laminated film FL3 disappears during the manufacturing process, a gap will be created between the sealing layer SE13 and the partition wall 6.

[0148] Figure 19 is a schematic cross-sectional view showing another example of the display device DSP according to this embodiment. In Figure 19, the shape of the overlapping portions SE111 and SE131 of the sealing layers SE11 and SE13 differs from that of the example in Figure 18.

[0149] Focusing on the sealing layer SE11, the protruding portion 111a of the sealing layer SE11 may overlap with the sealing layer SE12. In the example in Figure 19, the protruding portion 111a includes a portion 111c that overlaps with the sealing layer SE12. In the third direction Z, the partition wall 6, the sealing layer SE12, and the protruding portion 111a of the sealing layer SE11 are arranged in this order.

[0150] Similarly, focusing on the sealing layer SE13, the protrusion 131a of the sealing layer SE13 may overlap with the sealing layer SE11. In the example in Figure 19, the protrusion 131a includes a portion 131c that overlaps with the sealing layer SE11. In the third direction Z, the partition wall 6, the sealing layer SE11, and the protrusion 131a of the sealing layer SE13 are arranged in this order.

[0151] Although not shown in Figures 18 and 19, focusing on the area above the partition wall 6 between sub-pixels SP2 and SP3, the superimposed portion SE131 may include a projection 131a that protrudes upward. The projection 131a is located above the sealing layer SE12. In the example in Figure 19, above the partition wall 6 between sub-pixels SP2 and SP3, the partition wall 6, the sealing layer SE12, and the projection 131a of the sealing layer SE13 are aligned in this order in the third direction Z.

[0152] In this embodiment as well, the same effects as in the third embodiment can be obtained. The order in which the display elements DE1, DE2, and DE3 are formed in this embodiment can also be applied to the first and second embodiments.

[0153] [Fifth Embodiment] Figure 20 is a schematic plan view of the display device DSP according to this embodiment. Figure 21 is a schematic cross-sectional view of the display device DSP along the line XXI-XXI in Figure 20. Figure 22 is a schematic enlarged view of section XXII in Figure 20. In this embodiment, the arrangement of the sealing layers SE11, SE12, and SE13 differs from that of the embodiments described above.

[0154] Specifically, above the partition wall 6, the sealing layers SE11, SE12, and SE13 are spaced apart from each other. In other words, the end of sealing layer SE12 is not in contact with the end of sealing layer SE11, and the end of sealing layer SE13 is not in contact with the ends of sealing layers SE11 and SE12, respectively.

[0155] The planar shape of the sealing layer SE11 is octagonal. The sealing layer SE12 is formed continuously over multiple subpixels SP2 aligned, for example, in the second direction Y. The planar shape of the sealing layer SE13 is rectangular.

[0156] In the example shown in Figure 21, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition 6. Also, the sealing layer SE11 on the partition 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition 6.

[0157] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0158] Focusing on the sealing layers SE11 and SE12, as shown in Figure 22, a slit SL1 is formed between the sealing layer SE11 and the sealing layer SE12. The slit SL1 extends in the second direction Y. The slit SL1 is located above the partition wall 6 between the sub-pixels SP1 and SP2.

[0159] As shown in Figure 22, the sealing layer SE11 has two sides L11, two sides L12, two sides L13, and two sides L14. In this embodiment, side L11 corresponds to the first side, side L12 corresponds to the second side, and side L13 corresponds to the third side.

[0160] Edge L11 extends in the first direction X, and edge L12 extends in the second direction Y. Edges L13 and L14 connect edges L11 and L12, respectively. Edges L13 and L14 extend in directions different from the first direction X and the second direction Y.

[0161] Here, we define the angle between side L11 and side L13 as angle θ7. Focusing on the sealing layer SE11, angle θ7 corresponds to the interior angle of the sealing layer SE11. Angle θ7 is, for example, an obtuse angle. In other words, angle θ7 is greater than 90 degrees and less than 180 degrees (90 degrees < θ1 < 180 degrees). For example, angle θ7 is between 120 degrees and 150 degrees (120 degrees < θ1 < 150 degrees). More specifically, angle θ7 is 135 degrees.

[0162] Slit SL1 has ends SLa and SLb. End SLa is located between side L14 of sealing layer SE11 and side L5 of sealing layer SE12, and end SLb is located between side L13 of sealing layer SE11 and side L5 of sealing layer SE12.

[0163] The width of the end SLa of slit SL1 increases in the first direction X as it moves in the second direction Y, and the width of the end SLb increases in the first direction X as it moves in the direction opposite to the second direction Y.

[0164] In this embodiment as well, the same effects as in the first embodiment can be obtained. Figure 23 is a schematic plan view of a display device DSP according to a comparative example of this embodiment. Figure 23 shows the state before the display element DE3 is formed.

[0165] In the comparative example, a slit SL2 is formed between the sealing layer SE11 and the sealing layer SE12. The comparative example differs from this embodiment in that the planar shape of the sealing layer SE11 is rectangular.

[0166] In this case, the width of the slit SL2 in the first direction X is approximately constant in the second direction Y. Therefore, when the process for forming the display element DE3 is carried out, air bubbles are likely to form near the opening at the end of the slit SL2.

[0167] If the process for forming the display element DE3 is carried out while air bubbles are present, the bubbles will burst during the reduced-pressure drying of the resist used to pattern the multilayer film FL3 and the sealing layer SE13, exposing area A5, which should be covered by the resist. This could potentially cause defects in the display area DA.

[0168] In contrast, as shown in Figure 22, in the DSP display device according to this embodiment, the angle θ7 of the corner portion of the sealing layer SE11 is formed at an obtuse angle, so that ends SLa and SLb are formed in the slit SL1.

[0169] This allows air to escape more easily from the ends SLa and SLb of the slit SL1 when forming the multilayer film FL3 and the sealing layer SE13. In other words, the resist flows easily into the slit SL1, and air bubbles are less likely to form.

[0170] As a result, the resist is prevented from bursting, and the area A5 that should be covered by the resist is less likely to be exposed. In this embodiment, the occurrence of malfunctions in the display device DSP can be suppressed, and the yield of the display device DSP can be improved.

[0171] With a display device DSP configured as described above, yield can be improved. In addition, various other desirable effects can be obtained from this embodiment.

[0172] Note that the shape of region A3 shown in Figure 11 is not limited to the example described above. Figure 24 is a schematic plan view showing a modified example of the display device. In the example in Figure 24, the corner of region A3 is formed in an arc shape. In other words, the sealing layer SE13 has an arc-shaped curved portion RL2 that connects side L1 and side L2. From another viewpoint, the corner of region A3 surrounded by sealing layers SE11 and SE12 is arc-shaped. Even in such a case, the same effects as in each of the embodiments described above can be obtained.

[0173] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention. Within the scope of the idea of ​​the present invention, a person skilled in the art can conceive of various modifications, and these modifications are also understood to fall within the scope of the present invention. For example, any modifications made by a person skilled in the art to add, delete, or modify components, or to add, omit, or change the conditions of the above-described embodiments, are also included within the scope of the present invention insofar as they retain the gist of the present invention.

[0174] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0175] 1...Pixel circuit, 2...Pixel switch, 5...Rib layer, 6...Partition, 10...Substrate, 11...Circuit layer, 12...Organic insulating layer, 61...Lower part, 62...Upper part, 111a...Protrusion, 111b...Extension, 111c...Part, 121a...Protrusion, 121b...Extension, 121c...Part, 131a...Protrusion, 131b...Extension, 131c...Part, A3...Area, DA...Display area, DE, DE1, DE2, DE3...Display Element, DSP...Display device, FL1,FL2,FL3...Laminated film, G1,G2...Gap, L1,L2,L4,L5,L31,L32,L61,L62,L71,L72...Side, LE1,LE2,LE 3...lower electrode, OR1,OR2,OR3...organic layer, RL1,RL2...curved portion, SE11,SE12,SE13...sealing layer, SP1,SP2,SP3...subpixel, UE1,UE2,UE3...upper electrode.

Claims

1. The lower electrode and A partition wall surrounding the lower electrode, A laminated film positioned above the lower electrode, It comprises an inorganic insulating material, a sealing layer that covers the laminated film and is positioned above the partition wall, The sealing layer, in plan view, A first side extending in the first direction, A second side extending in a second direction perpendicular to the first direction, It has a third side that extends in a direction different from the first and second directions and connects the first side and the second side, The angle between the first side and the third side is greater than 90 degrees and less than 180 degrees. Display device.

2. The first side, the second side, and the third side overlap the partition wall. The display device according to claim 1.

3. The aforementioned angle is between 120 degrees and 150 degrees. The display device according to claim 2.

4. The first side is directly connected to the third side. The display device according to claim 2.

5. The sealing layer further has an arc-shaped curved portion connecting the first side and the third side. The display device according to claim 2.

6. The planar shape of the sealing layer is octagonal. The display device according to claim 1.

7. The system further comprises an inorganic insulating layer positioned below the partition wall and the lower electrode, The aforementioned partition wall is The lower part, which is placed on the inorganic insulating layer, It has an upper part positioned above the lower part and protruding from the side surface of the lower part, The first side, the second side, and the third side are positioned above the upper part. The display device according to any one of claims 1 to 6.

8. First lower electrode, second lower electrode, and third lower electrode, A partition wall surrounding the first lower electrode, the second lower electrode, and the third lower electrode, A first laminated film positioned above the first lower electrode, A second laminated film positioned above the second lower electrode, A first sealing layer, formed of an inorganic insulating material, covers the first laminated film and is positioned above the partition wall, It comprises a second sealing layer formed of an inorganic insulating material, covering the second laminated film and positioned above the partition wall, The first sealing layer has a fourth side extending in a first direction in a plan view, The second sealing layer has, in a plan view, a fifth edge extending in a second direction perpendicular to the first direction, and a sixth edge extending in a direction different from the first and second directions and connected to the fifth edge. The first sealing layer and the second sealing layer form a region that overlaps with the third lower electrode. The interior angle of the region, which is the angle formed by the fourth side and the sixth side, is greater than 90 degrees and less than 180 degrees. Display device.

9. The fourth, fifth, and sixth sides overlap the partition wall. The display device according to claim 8.

10. First lower electrode, second lower electrode, and third lower electrode, A partition wall surrounding the first lower electrode, the second lower electrode, and the third lower electrode, A first laminated film positioned above the first lower electrode, A second laminated film positioned above the second lower electrode, A first sealing layer, formed of an inorganic insulating material, covers the first laminated film and is positioned above the partition wall, It comprises a second sealing layer formed of an inorganic insulating material, covering the second laminated film and positioned above the partition wall, The first sealing layer, in a plan view, has a fourth edge extending in a first direction and a seventh edge extending in a direction different from the second direction perpendicular to the first direction and connected to the fourth edge. The first sealing layer and the second sealing layer form a region that overlaps with the third lower electrode. The interior angle of the region, which is the angle between the fourth side and the seventh side, is greater than 90 degrees and less than 180 degrees. Display device.

11. The fourth and seventh sides overlap the partition wall. The display device according to claim 10.

12. The planar shape of the aforementioned region is octagonal. The display device according to claim 8 or 10.

13. The aforementioned interior angle is between 120 degrees and 150 degrees. The display device according to claim 8 or 10.

14. A third laminated film positioned above the third lower electrode, The present invention further comprises a third sealing layer, which is made of an inorganic insulating material, covers the third laminated film, and is positioned above the partition wall, The fourth and sixth sides are in contact with the third sealing layer above the partition wall. The display device according to claim 8.

15. A third laminated film positioned above the third lower electrode, The present invention further comprises a third sealing layer, which is made of an inorganic insulating material, covers the third laminated film, and is positioned above the partition wall, The fourth and seventh edges are in contact with the third sealing layer above the partition wall. The display device according to claim 10.

16. The third sealing layer overlaps the partition wall and has a protrusion located above the first sealing layer. The display device according to claim 14 or 15.

17. The protruding portion has a portion that overlaps with the first sealing layer. The display device according to claim 16.

18. The third sealing layer further has an extension that extends above the partition wall toward the gap formed between the first sealing layer and the partition wall. The display device according to claim 14 or 15.

19. The third laminated film is positioned above the partition wall, between the partition wall and the third sealing layer. The display device according to claim 14 or 15.

20. The lower electrode and A partition wall surrounding the lower electrode, A laminated film positioned above the lower electrode, It comprises an inorganic insulating material, a sealing layer that covers the laminated film and is positioned above the partition wall, The sealing layer, in plan view, A first side extending in the first direction, A second side extending in a second direction perpendicular to the first direction, It has an arc-shaped curved portion connecting the first side and the second side, Display device.

Images