Indication device

Abstract

To provide a display device that can improve yield. [Solution] Generally, according to the embodiment, the display device comprises a substrate having a display area for displaying an image and a dummy pixel area adjacent to the display area and including a plurality of dummy subpixels that do not display an image, and a partition wall positioned above the substrate and arranged in the dummy pixel area, including a plurality of lower electrodes positioned above the lower electrodes and a lower part positioned above the lower part and protruding from the side surface of the lower part, wherein each of the plurality of dummy subpixels has the lower electrode, the partition wall has a first opening that overlaps with the lower electrode, and at least a portion of the plurality of lower electrodes has a second opening that overlaps with the first opening.

Description

Technical Field

[0001] Embodiments of the present invention relate to a display device.

Background Art

[0002] In recent years, display devices applying organic light emitting diodes (OLEDs) as display elements have been put into practical use. In this type of display device, technologies for improving the yield are required.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Patent Document 5

Patent Document 6

Patent Document 7

Summary of the Invention

Problems to be Solved by the Invention

[0004] One object of the present invention is to provide a display device capable of improving the yield.

Means for Solving the Problems

[0005] Generally, according to the embodiment, the display device comprises a substrate having a display area for displaying an image and a dummy pixel area adjacent to the display area and including a plurality of dummy subpixels that do not display an image, and a partition wall positioned above the substrate and disposed in the dummy pixel area, including a plurality of lower electrodes, a lower part positioned above the lower electrodes, and an upper part positioned above the lower part and protruding from the side surface of the lower part, wherein each of the plurality of dummy subpixels has the lower electrode, the partition wall has a first opening overlapping the lower electrode, and at least a portion of the plurality of lower electrodes has a second opening overlapping the first opening.

[0006] Furthermore, according to the embodiment, the display device comprises a substrate having a display area for displaying an image and a peripheral area outside the display area; a partition wall having a conductive layer located above the substrate and disposed in the peripheral area; a lower part located above the conductive layer; and an upper part located above the lower part and protruding from the side surface of the lower part, and being disposed across the display area and the peripheral area, wherein the partition wall has a first opening that overlaps with the conductive layer, and the conductive layer has a second opening that overlaps with the first opening. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 shows an example of the configuration of a display device according to the first embodiment. [Figure 2] Figure 2 is a schematic plan view showing an example of a sub-pixel layout. [Figure 3] Figure 3 is a schematic cross-sectional view of the display device along the line III-III in Figure 2. [Figure 4] Figure 4 is a schematic plan view showing the inorganic insulating layer in a pixel. [Figure 5] Figure 5 is a schematic cross-sectional view of the display device along the VV line in Figure 4. [Figure 6] Figure 6 is a schematic cross-sectional view of the display device along the line VI-VI in Figure 4. [Figure 7]Figure 7 is a schematic cross-sectional view showing the structure around the slit. [Figure 8] Figure 8 is a schematic top view of the display device including the cover member. [Figure 9] Figure 9 is a plan view showing an enlarged view of the area enclosed by frame IX in Figure 8 of the display device according to the first embodiment. [Figure 10] Figure 10 is a schematic plan view showing two dummy pixels aligned in the X direction of the display device according to the first embodiment. [Figure 11] Figure 11 is a schematic cross-sectional view of the display device along the line XI-XI in Figure 10. [Figure 12] Figure 12 is a plan view with the opening enlarged. [Figure 13] Figure 13 is a schematic cross-sectional view of the display device along the line XIII-XIII in Figure 12. [Figure 14] Figure 14 is a schematic plan view of a display device according to a comparative example. [Figure 15] Figure 15 is a plan view showing an enlarged view of the area enclosed by frame IX in Figure 8 of the display device according to the second embodiment. [Figure 16] Figure 16 is a schematic plan view showing two dummy pixels aligned in the X direction of the display device according to the second embodiment. [Modes for carrying out the invention]

[0008] Several embodiments will be described with reference to the drawings. The disclosure is merely an example, and any modifications that a person skilled in the art could easily conceive of while maintaining the spirit of the invention are naturally included within the scope of the present invention. Furthermore, the drawings may schematically represent the width, thickness, shape, etc., of each part in order to clarify the explanation, but these are merely examples and do not limit the interpretation of the present invention. In addition, in this specification and each drawing, the same reference numerals are used for components that perform the same or similar functions as those described above with respect to previously shown drawings, and redundant detailed explanations may be omitted as appropriate.

[0009] In the drawings, for ease of understanding as necessary, the X-axis, Y-axis, and Z-axis orthogonal to each other are described. The direction along the X-axis is referred to as the X direction, the direction along the Y-axis is referred to as the Y direction, and the direction along the Z-axis is referred to as the Z direction. Further, viewing various elements parallel to the Z direction is referred to as a plan view.

[0010] The display device according to each embodiment is an organic electroluminescence display device including an organic light-emitting diode (OLED) as a display element, and can be mounted on various electronic devices such as a television, a personal computer, an in-vehicle device, a tablet terminal, a smartphone, a mobile phone terminal, and a wearable terminal.

[0011] [First Embodiment] FIG. 1 is a diagram showing a configuration example of a display device DSP according to the first embodiment. The display device DSP includes a display panel PNL including an insulating substrate 10. The substrate 10 has a display area DA for displaying an image and a peripheral area SA around the display area DA. The substrate 10 may be glass or a resin film having flexibility.

[0012] In the present embodiment, the shape of the substrate 10 in plan view is circular. However, the shape of the substrate 10 in plan view is not limited to a circle, and may be other shapes such as a rectangle, a square, or an ellipse.

[0013] The display area DA includes a plurality of pixels PX arranged in a matrix in the X direction and the Y direction. The pixel PX includes a plurality of sub-pixels SP that display different colors. In the present embodiment, a case where the pixel PX includes a green sub-pixel SP1, a blue sub-pixel SP2, and a red sub-pixel SP3 is assumed. However, the pixel PX may include sub-pixels SP of other colors such as white, together with or in place of the sub-pixels SP1, SP2, and SP3.

[0014] The DSP display device further includes a terminal section T located in the peripheral region SA. A flexible circuit board FLX, which supplies voltage and signals for driving the DSP display device, is connected to the terminal section T.

[0015] The sub-pixel SP comprises a pixel circuit 1 and a display element DE driven by the pixel circuit 1. The pixel circuit 1 comprises a pixel switch 2, a drive transistor 3, and a capacitor 4. The pixel switch 2 and the drive transistor 3 are switching elements composed of, for example, thin-film transistors.

[0016] The display area DA is arranged with multiple scan lines GL that supply scan signals to the pixel circuit 1 of each sub-pixel SP, multiple signal lines SL that supply video signals to the pixel circuit 1 of each sub-pixel SP, and multiple power lines PL. In the example in Figure 1, the scan lines GL and power lines PL extend in the X direction, and the signal lines SL extend in the Y direction.

[0017] The gate electrode of pixel switch 2 is connected to the scan line GL. The source electrode of pixel switch 2 is connected to the signal line SL. The drain electrode of pixel switch 2 is connected to the gate electrode of drive transistor 3 and capacitor 4. The source electrode of drive transistor 3 is connected to the power line PL and capacitor 4. The drain electrode of drive transistor 3 is connected to display element DE.

[0018] Note that the configuration of the pixel circuit 1 is not limited to the example shown. For example, the pixel circuit 1 may include more thin-film transistors and capacitors.

[0019] Figure 2 is a schematic plan view showing an example of the layout of sub-pixels SP1, SP2, and SP3. In the example in Figure 2, sub-pixels SP2 and SP3 are aligned with sub-pixel SP1 in the X direction. Furthermore, sub-pixels SP2 and SP3 are aligned in the Y direction.

[0020] When sub-pixels SP1, SP2, and SP3 are arranged in this manner, the display area DA forms columns in which sub-pixels SP2 and SP3 are alternately arranged in the Y direction, and columns in which multiple sub-pixels SP1 are repeatedly arranged in the Y direction. These columns are arranged alternately in the X direction. Note that the layout of sub-pixels SP1, SP2, and SP3 is not limited to the example in Figure 2.

[0021] A rib layer 5 is arranged in the display area DA. The rib layer 5 has pixel apertures AP1, AP2, and AP3 in the sub-pixels SP1, SP2, and SP3, respectively. In the example in Figure 2, pixel apertures AP1 and AP2 are larger than pixel aperture AP3. Note that the size and shape of pixel apertures AP1, AP2, and AP3 are not limited to the example shown.

[0022] Sub-pixel SP1 comprises a lower electrode LE1, an upper electrode UE1, and an organic layer OR1, which overlap with the pixel aperture AP1. Sub-pixel SP2 comprises a lower electrode LE2, an upper electrode UE2, and an organic layer OR2, which overlap with the pixel aperture AP2. Sub-pixel SP3 comprises a lower electrode LE3, an upper electrode UE3, and an organic layer OR3, which overlap with the pixel aperture AP3.

[0023] The portion of the lower electrode LE1, upper electrode UE1, and organic layer OR1 that overlaps with the pixel aperture AP1 constitutes the display element DE1 of the sub-pixel SP1. The portion of the lower electrode LE2, upper electrode UE2, and organic layer OR2 that overlaps with the pixel aperture AP2 constitutes the display element DE2 of the sub-pixel SP2. The portion of the lower electrode LE3, upper electrode UE3, and organic layer OR3 that overlaps with the pixel aperture AP3 constitutes the display element DE3 of the sub-pixel SP3. The display elements DE1, DE2, and DE3 may further include a cap layer, which will be described later. The rib layer 5 surrounds each of these display elements DE1, DE2, and DE3.

[0024] The lower electrode LE1 is connected to the pixel circuit 1 of the sub-pixel SP1 (see Figure 1) through the contact hole CH1. The lower electrode LE2 is connected to the pixel circuit 1 of the sub-pixel SP2 through the contact hole CH2. The lower electrode LE3 is connected to the pixel circuit 1 of the sub-pixel SP3 through the contact hole CH3.

[0025] A conductive partition wall 6 is positioned in the display area DA. The partition wall 6 is located above the rib layer 5 and overlaps with the rib layer 5 overall. In the example in Figure 2, the partition wall 6 has a planar shape similar to that of the rib layer 5. That is, the partition wall 6 has openings in the sub-pixels SP1, SP2, and SP3, respectively. From another perspective, the rib layer 5 and the partition wall 6 are grid-like in plan view and surround the display elements DE1, DE2, and DE3, respectively. The partition wall 6 also surrounds the pixel apertures AP1, AP2, and AP3. The partition wall 6 serves as wiring that supplies a common voltage to the upper electrodes UE1, UE2, and UE3.

[0026] The partition wall 6 has multiple slits SL6. In the example in Figure 2, each slit SL6 extends in the Y direction. For example, the sub-pixels SP1, SP2, and SP3 that constitute one pixel PX are arranged between two adjacent slits SL6 in the X direction. Furthermore, the partition wall 6 has a connecting section CT that connects the portions separated by the slits SL6. Note that the arrangement of the slits SL6 and the connecting section CT is not limited to the example in Figure 2. For example, there may be continuous slits SL6 between the two ends of the display area DA in the Y direction.

[0027] Figure 3 is a schematic cross-sectional view of the display device DSP along the line III-III in Figure 2. A circuit layer 11 is arranged on the substrate 10 described above. The circuit layer 11 includes various circuits and wiring such as the pixel circuit 1, scan line GL, signal line SL, and power line PL shown in Figure 1. The circuit layer 11 is covered with an organic insulating layer 12. The organic insulating layer 12 functions as a planarizing film that flattens the irregularities caused by the circuit layer 11.

[0028] The organic insulating layer 12 is covered by the inorganic insulating layer 13. The lower electrodes LE1, LE2, and LE3 are positioned on the inorganic insulating layer 13 and spaced apart from each other. The inorganic insulating layer 13 is in contact with the lower surfaces of each of the lower electrodes LE1, LE2, and LE3. The rib layer 5 is positioned on the inorganic insulating layer 13 and the lower electrodes LE1, LE2, and LE3. The ends of the lower electrodes LE1, LE2, and LE3 are covered by the rib layer 5. Although not shown in the cross-section of Figure 3, the lower electrodes LE1, LE2, and LE3 are connected to the pixel circuit 1 of the circuit layer 11 (the drain electrode of the drive transistor 3 shown in Figure 1) through openings provided in the inorganic insulating layer 13 (openings 13a and 13b shown in Figure 4) and contact holes CH1, CH2, and CH3 provided in the organic insulating layer 12, respectively.

[0029] The partition wall 6 includes a conductive lower section 61 positioned on the rib layer 5 and an upper section 62 positioned on top of the lower section 61. The upper section 62 has a greater width than the lower section 61. As a result, both ends of the upper section 62 protrude beyond the sides of the lower section 61. This shape of partition wall 6 is called an overhang.

[0030] In the example shown in Figure 3, the lower section 61 has a bottom layer 63 positioned on top of the rib layer 5 and an axial layer 64 positioned on top of the bottom layer 63. For example, the bottom layer 63 is formed to be thinner than the axial layer 64. In the example shown in Figure 3, both ends of the bottom layer 63 protrude from the sides of the axial layer 64. Also, the ends of the bottom layer 63 are located between the ends of the upper section 62 and the sides of the axial layer 64 in a plan view. The upper section 62 is positioned on top of the axial layer 64.

[0031] The organic layer OR1 covers the lower electrode LE1 through the pixel aperture AP1. The upper electrode UE1 covers the organic layer OR1 and faces the lower electrode LE1. The organic layer OR2 covers the lower electrode LE2 through the pixel aperture AP2. The upper electrode UE2 covers the organic layer OR2 and faces the lower electrode LE2. The organic layer OR3 covers the lower electrode LE3 through the pixel aperture AP3. The upper electrode UE3 covers the organic layer OR3 and faces the lower electrode LE3. The upper electrodes UE1, UE2, and UE3 are in contact with the side surface of the lower part 61 of the partition wall 6.

[0032] Display element DE1 includes a cap layer CP1 covering the upper electrode UE1. Display element DE2 includes a cap layer CP2 covering the upper electrode UE2. Display element DE3 includes a cap layer CP3 covering the upper electrode UE3. The cap layers CP1, CP2, and CP3 each serve as optical adjustment layers that improve the efficiency of light extraction from the organic layers OR1, OR2, and OR3, respectively.

[0033] In the following explanation, a multilayer containing an organic layer OR1, an upper electrode UE1, and a cap layer CP1 will be referred to as multilayer film FL1, a multilayer containing an organic layer OR2, an upper electrode UE2, and a cap layer CP2 will be referred to as multilayer film FL2, and a multilayer containing an organic layer OR3, an upper electrode UE3, and a cap layer CP3 will be referred to as multilayer film FL3.

[0034] Sub-pixels SP1, SP2, and SP3 are each fitted with sealing layers SE11, SE12, and SE13, which cover the stacked films FL1, FL2, and FL3, respectively. Sealing layer SE11 continuously covers the display element DE1 and the surrounding partition wall 6. Sealing layer SE12 continuously covers the display element DE2 and the surrounding partition wall 6. Sealing layer SE13 continuously covers the display element DE3 and the surrounding partition wall 6.

[0035] In the example shown in Figure 3, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP2 is separated from the sealing layer SE12 on the same partition wall 6. Also, the sealing layer SE11 on the partition wall 6 between sub-pixels SP1 and SP3 is separated from the sealing layer SE13 on the same partition wall 6. However, any two of the sealing layers SE11, SE12, and SE13 may be in contact above the partition wall 6.

[0036] For example, gaps are formed between the sealing layers SE11, SE12, SE13 and the upper part 62 of the partition wall 6. The laminated films FL1, FL2, FL3 may be placed in at least a portion of these gaps.

[0037] The sealing layers SE11, SE12, and SE13 are covered by the resin layer RS1. The resin layer RS1 is covered by the sealing layer SE2. The sealing layer SE2 is covered by the resin layer RS2. The resin layers RS1, RS2, and the sealing layer SE2 are provided continuously over at least the entire display area DA, with a portion extending into the peripheral area SA. The display panel PNL includes the components between the substrate 10 and the resin layer RS2 as described above.

[0038] A cover member CO is positioned above the display panel PNL. The cover member CO is bonded to the display panel PNL via an adhesive layer, such as OCA (Optical Clear Adhesive). A polarizing plate or other component may be positioned between the cover member CO and the display panel PNL.

[0039] The organic insulating layer 12 is formed of an organic insulating material such as polyimide. The rib layer 5, inorganic insulating layer 13, and sealing layers SE11, SE12, SE13, SE2 are formed of an inorganic insulating material such as silicon nitride (SiNx), silicon oxide (SiOx), or silicon oxynitride (SiON). In one example, the rib layer 5 and inorganic insulating layer 13 are formed of silicon oxynitride, and the sealing layers SE11, SE12, SE13, SE2 are formed of silicon nitride. The resin layers RS1, RS2 are formed of a resin material (organic insulating material) such as epoxy resin or acrylic resin.

[0040] The lower electrodes LE1, LE2, and LE3 each have a reflective layer and a pair of conductive oxide layers covering the upper and lower surfaces of the reflective layer, respectively. The reflective layer can be formed from a metallic material with excellent light reflectivity, such as silver. Each conductive oxide layer can be formed from a transparent conductive oxide such as ITO (Indium Tin Oxide), IZO (Indium Zinc Oxide), or IGZO (Indium Gallium Zinc Oxide).

[0041] The upper electrodes UE1, UE2, and UE3 are formed from a metallic material such as a magnesium-silver alloy (MgAg). For example, the lower electrodes LE1, LE2, and LE3 correspond to the anode, and the upper electrodes UE1, UE2, and UE3 correspond to the cathode.

[0042] The cap layers CP1, CP2, and CP3 have a laminated structure in which multiple transparent layers are stacked, for example. These transparent layers may include layers formed from inorganic materials and layers formed from organic materials. Furthermore, these transparent layers have different refractive indices. For example, the refractive indices of these transparent layers are different from those of the upper electrodes UE1, UE2, and UE3 and the sealing layers SE11, SE12, and SE13. Note that at least one of the cap layers CP1, CP2, and CP3 may be omitted.

[0043] The bottom layer 63 and axial layer 64 of the partition wall 6 are formed of, for example, a metallic material. Examples of metallic materials for the bottom layer 63 include molybdenum (Mo), titanium (Ti), titanium nitride (TiN), molybdenum-tungsten alloy (MoW), or molybdenum-niobium alloy (MoNb). Examples of metallic materials for the axial layer 64 include aluminum (Al), aluminum-neodymium alloy (AlNd), aluminum-yttrium alloy (AlY), or aluminum-silicon alloy (AlSi). At least one of the bottom layer 63 and the axial layer 64 may have a laminated structure of multiple layers. Furthermore, the axial layer 64 may include a layer formed of an insulating material.

[0044] For example, the upper part 62 of the partition wall 6 has a laminated structure consisting of a lower layer made of a metallic material and an upper layer made of a conductive oxide. As the metallic material forming the lower layer, for example, titanium, titanium nitride, molybdenum, tungsten, molybdenum-tungsten alloy, or molybdenum-niobium alloy can be used. As the conductive oxide forming the upper layer, for example, ITO or IZO can be used. The upper part 62 may also have a single-layer structure of metallic material. Furthermore, the upper part 62 may include a layer made of an insulating material.

[0045] A common voltage is supplied to the partition wall 6. This common voltage is supplied to the upper electrodes UE1, UE2, and UE3, which are in contact with the sides of the lower part 61. The lower electrodes LE1, LE2, and LE3 are supplied with pixel voltages corresponding to the video signal on the signal line SL through the pixel circuits 1 of the sub-pixels SP1, SP2, and SP3, respectively.

[0046] In one example, the organic layers OR1, OR2, and OR3 are configured to emit light of different colors. In another example, the light-emitting layers of the organic layers OR1, OR2, and OR3 may emit light of the same color (e.g., white). In this case, the display device DSP may include a color filter that converts the light emitted by each light-emitting layer contained in each of the organic layers OR1, OR2, and OR3 into light of the color corresponding to the sub-pixels SP1, SP2, and SP3. The display device DSP may also include a layer containing quantum dots that are excited by the light emitted by the light-emitting layers to generate light of the color corresponding to the sub-pixels SP1, SP2, and SP3.

[0047] Figure 4 is a schematic plan view showing the inorganic insulating layer 13 in pixel PX. The inorganic insulating layer 13 has multiple openings 13a and 13b. In Figure 4, the openings 13a and 13b are shown by dashed lines.

[0048] Aperture 13a is located between adjacent sub-pixels SP1 in the Y direction. In a plan view, aperture 13a overlaps with contact hole CH1 and a portion of lower electrode LE1. Aperture 13b is located between adjacent sub-pixels SP2 and SP3 in the Y direction at pixel PX. In a plan view, aperture 13b overlaps with contact holes CH2 and CH3, respectively, and a portion of lower electrodes LE2 and LE3, respectively, in a plan view.

[0049] Multiple openings 13a and 13b are provided across the entire display area DA. The inorganic insulating layer 13 may have only one of the openings 13a or 13b, or it may have additional openings.

[0050] Figure 5 is a schematic cross-sectional view of the display device DSP along the VV line in Figure 4. Note that in Figure 5, elements below the circuit layer 11 and elements above the sealing layers SE11, SE12, and SE13 are omitted.

[0051] The lower electrode LE1 is in contact with the organic insulating layer 12 through the opening 13a. The lower electrode LE1 covers a portion of the opening 13a, but does not completely cover it. The lower electrode LE1 is also in contact with the wiring WL included in the circuit layer 11 through a contact hole CH1 provided in the organic insulating layer 12. The wiring WL corresponds, for example, to the source electrode or drain electrode of the drive transistor 3 shown in Figure 1.

[0052] The rib layer 5 is in contact with the organic insulating layer 12 in the region ARa of the opening 13a that is not covered by the lower electrode LE1. The partition wall 6 covers the opening 13a.

[0053] As shown in an enlarged view at the bottom of Figure 5, the lower electrode LE1 has a metal layer ML, a first layer L1 covering the lower surface of the metal layer ML, and a second layer L2 covering the upper surface of the metal layer ML. The metal layer ML is a reflective layer formed of, for example, silver. The first layer L1 and the second layer L2 are conductive oxide layers formed of, for example, a transparent conductive oxide such as ITO.

[0054] In one example, the thickness of the second layer L2 is smaller than the thickness of the first layer L1 and the metal layer ML. Also, the thickness of the first layer L1 is less than or equal to the thickness of the metal layer ML. Note that the relationship between the thicknesses of the metal layer ML, the first layer L1, and the second layer L2 is not limited to the above example. For example, the thickness of the second layer L2 may be larger than the thickness of the first layer L1 and the metal layer ML.

[0055] Figure 6 is a schematic cross-sectional view of the display device DSP along the VI-VI line in Figure 4. In Figure 6, elements below the circuit layer 11 and elements above the sealing layers SE11, SE12, and SE13 are omitted. The lower electrode LE2 is in contact with the organic insulating layer 12 through the opening 13b. The lower electrode LE2 covers a portion of the opening 13b, but does not completely cover it. The lower electrode LE2 is in contact with the wiring WL included in the circuit layer 11 through a contact hole CH2 provided in the organic insulating layer 12.

[0056] Although not shown in the diagram, the lower electrode LE3 is configured similarly to the lower electrode LE2. That is, the lower electrode LE3 is in contact with the organic insulating layer 12 through the opening 13b. Furthermore, the lower electrode LE3 is in contact with the wiring WL through the contact hole CH3 provided in the organic insulating layer 12.

[0057] The rib layer 5 is in contact with the organic insulating layer 12 in the region ARb of the opening 13b that is not covered by the lower electrodes LE2 and LE3. The partition wall 6 covers the opening 13b.

[0058] The lower electrodes LE2 and LE3, like the lower electrode LE1, each have a metal layer ML, a first layer L1 covering the lower surface of the metal layer ML, and a second layer L2 covering the upper surface of the metal layer ML, respectively.

[0059] The inorganic insulating layer 13 prevents moisture contained in the organic insulating layer 12 from penetrating into the organic layers OR1, OR2, and OR3. This suppresses lighting failures of the display elements DE1, DE2, and DE3. In addition, the openings 13a and 13b serve to discharge moisture contained in the organic insulating layer 12 that evaporates due to the heat treatment performed during the manufacturing process of the display device DSP.

[0060] Figure 7 is a schematic cross-sectional view showing the structure around the slit SL6. Note that in Figure 7, elements below the organic insulating layer 12 and elements above the resin layer RS1 are omitted.

[0061] In the example shown in Figure 7, the slit SL6 is located between the lower electrodes LE1 and LE2. Also, the slit SL6 does not overlap with the lower electrodes LE1 and LE2 in a plan view. At the slit SL6, the rib layer 5 is in contact with the resin layer RS1.

[0062] Electronic devices equipped with a display device DSP may include optical sensors, such as illuminance sensors, to detect ambient light. Such optical sensors are positioned, for example, on the back side (the side of the substrate 10) of the display device DSP. If a slit SL6 is provided in the partition wall 6, ambient light can pass through the slit SL6 and reach the optical sensor.

[0063] Figure 8 is a schematic top view of a display device DSP including a cover member CO. In the example in Figure 8, the shape of the cover member CO in plan view is circular.

[0064] The cover member CO has a light-transmitting portion TL that overlaps with the display area DA, and a light-shielding portion BM that surrounds the light-transmitting portion TL. The light-transmitting portion TL is formed in a circular shape and completely covers the display area DA. That is, the light-transmitting portion TL covers the boundary E1, which is the boundary between the display area DA and the surrounding area SA and is formed in a circular shape.

[0065] The light-shielding portion BM overlaps with the surrounding region SA. The boundary E2 between the light-transmitting portion TL and the light-shielding portion BM is formed in a circular shape and overlaps with the surrounding region SA. In the example in Figure 8, the display panel PNL is completely covered by the cover member CO, but a portion of the display panel may not be covered by the cover member CO.

[0066] Figure 9 is a plan view showing an enlarged view of the area enclosed by frame IX in Figure 8 of the display device DSP according to the first embodiment.

[0067] The peripheral region SA comprises a dummy pixel region DMY and a frame region FA. The dummy pixel region DMY is adjacent to and surrounds the display region DA. The frame region FA is adjacent to and surrounds the dummy pixel region DMY.

[0068] The dummy pixel region DMY contains multiple dummy pixels DPX. For example, dummy pixel DPX includes dummy sub-pixels DP1, DP2, and DP3. Dummy sub-pixels DP1, DP2, and DP3 have a structure similar to the sub-pixels SP1, SP2, and SP3 shown in Figure 2, respectively.

[0069] Specifically, dummy sub-pixel DP1 has a lower electrode LE1, an organic layer OR1, an upper electrode UE1, and a sealing layer SE11. Dummy sub-pixel DP2 has a lower electrode LE2, an organic layer OR2, an upper electrode UE2, and a sealing layer SE12. Dummy sub-pixel DP3 has a lower electrode LE3, an organic layer OR3, an upper electrode UE3, and a sealing layer SE13.

[0070] However, the dummy sub-pixels DP1, DP2, and DP3 are configured not to emit light. Therefore, unlike the sub-pixels SP1, SP2, and SP3, the dummy sub-pixels DP1, DP2, and DP3 do not display an image.

[0071] Some of the multiple lower electrodes LE1, LE2, and LE3 located in the dummy pixel region DMY have apertures (apertures LE1a, LE2a, and LE3a shown in Figure 10). Details of these apertures will be described later.

[0072] In the example in Figure 9, two columns of multiple dummy pixels (DPX) arranged in the Y direction are arranged in the X direction. Note that there may be three or more such columns arranged in the X direction. Alternatively, only one such column may be present.

[0073] In the frame region FA, a conductive layer CL is arranged in the same layer as the lower electrodes LE1, LE2, and LE3, and is made of the same material as the lower electrodes LE1, LE2, and LE3. In this embodiment, the frame region FA has a first region AR1 that does not overlap with the conductive layer CL, and a second region AR2 that overlaps with the conductive layer CL. The first region AR1 surrounds the display region DA and the dummy pixel region DMY, and is adjacent to the dummy pixel region DMY. The second region AR2 surrounds the first region AR1 and is adjacent to the first region AR1.

[0074] The partition wall 6 is positioned across the display area DA, the dummy pixel area DMY, and the frame area FA. In the dummy pixel area DMY, the partition wall 6 surrounds the dummy sub-pixels DP1, DP2, and DP3, respectively. The shape and layout of the openings in the partition wall 6 (openings 611, 612, and 613 shown in Figure 10) for each of the dummy sub-pixels DP1, DP2, and DP3 are the same as the shape and layout of the openings in the partition wall 6 for each of the sub-pixels SP1, SP2, and SP3, respectively. The dummy pixel area DMY is also provided with a slit SL6 and a connecting section CT. In the example in Figure 9, the boundary E1 overlaps with the slit SL6.

[0075] In the first region AR1, the partition wall 6 has multiple openings 621 (third opening). These multiple openings 621 overlap with the inorganic insulating layer 13. In the example shown in Figure 9, the multiple openings 621 are aligned in the Y direction. Details of the openings 621 will be described later.

[0076] In the second region AR2, the partition wall 6 has a plurality of openings 631 and a slit 632 connecting the plurality of openings 631. In the example in Figure 9, the plurality of openings 631 are arranged in a matrix. The slit 632 extends in the X direction. Note that the partition wall 6 does not have to have a slit 632. That is, each of the plurality of openings 631 may be arranged independently without being connected.

[0077] Multiple contact portions CN are arranged in the second region AR2. In the example in Figure 9, the contact portions CN are arranged between openings 631 aligned in the Y direction. The partition wall 6 is connected to the conductive layer CL via the contact portions CN. The conductive layer CL is connected to the terminal portion T via power supply lines (not shown). The common voltage supplied from the terminal portion T is supplied to the upper electrodes UE1, UE2, and UE3 of the display region DA through the power supply lines, conductive layer CL, and partition wall 6.

[0078] The inorganic insulating layer 13 is arranged across the display area DA, the dummy pixel area DMY, and the frame area FA. Apertures 13a and 13b are also provided in the dummy pixel area DMY. The inorganic insulating layer 13 further has an aperture 13c. Aperture 13c is located in the first area AR1. In the example of Figure 9, aperture 13c is located between apertures 621 aligned in the Y direction.

[0079] In the example shown in Figure 9, the light-shielding portion BM of the cover member CO covers the second region AR2. Boundary E2 is located in the first region AR1. Multiple dummy pixels DPX and multiple apertures 621 are arranged between boundaries E1 and E2.

[0080] Note that the position of boundary E2 is not limited to the example shown in Figure 9. The position of boundary E2 varies depending on the positional accuracy and tolerance when attaching the cover member CO to the display panel PNL. Therefore, boundary E2 may be located in the second region AR2 or the dummy pixel region DMY.

[0081] Figure 10 is a schematic plan view showing two dummy pixel DPXs arranged in the X direction of the display device DSP according to the first embodiment. Here, of the two dummy pixel DPXs arranged in the X direction, the dummy pixel DPX on the display area DA side is set as dummy pixel DPX1, and the dummy pixel DPX on the frame area FA side is set as dummy pixel DPX2. Dummy pixel DPX1 corresponds to the dummy pixel DPX adjacent to the display area DA. Dummy pixel DPX2 corresponds to the dummy pixel DPX adjacent to the frame area FA.

[0082] The partition wall 6 has apertures 611, 612, and 613 (first apertures) that overlap with the lower electrodes LE1, LE2, and LE3, respectively, in the dummy pixel region DMY. The shape and layout of apertures 611, 612, and 613 are the same as the shape and layout of the apertures of partition wall 6 in the sub-pixels SP1, SP2, and SP3, respectively.

[0083] At least a portion of the lower electrodes LE1, LE2, and LE3 have an aperture that overlaps with one of the apertures 611, 612, or 613. In the example in Figure 10, the lower electrode LE1 included in dummy pixel DPX1 does not have an aperture that overlaps with aperture 611. The lower electrode LE1 included in dummy pixel DPX2 has an aperture LE1a that overlaps with aperture 611. The lower electrode LE2 included in each of dummy pixels DPX1 and DPX2 has an aperture LE2a that overlaps with aperture 612. The lower electrode LE3 included in each of dummy pixels DPX1 and DPX2 has an aperture LE3a that overlaps with aperture 613. In other words, of the lower electrodes LE1, LE2, and LE3, the lower electrode LE1 adjacent to the display area DA does not have an aperture LE1a that overlaps with aperture 611. Apertures LE1a, LE2a, and LE3a correspond to the second aperture.

[0084] Rib layer 5 covers the entire dummy pixel region DMY. Rib layer 5 also covers apertures 611, 612, 613 and apertures LE1a, LE2a, LE3a.

[0085] The inorganic insulating layer 13 covers the entire dummy pixel region DMY. In a plan view, the inorganic insulating layer 13 overlaps with apertures 611, 612, 613 and apertures LE1a, LE2a, LE3a. In the example in Figure 10, the inorganic insulating layer 13 completely covers apertures 611, 612, 613 and apertures LE1a, LE2a, LE3a.

[0086] Figure 11 is a schematic cross-sectional view of the display device DSP along the line XI-XI in Figure 10. In the peripheral region SA, the organic insulating layer 12 is covered by the inorganic insulating layer 13. The lower electrodes LE1, LE2, and LE3 are placed on the inorganic insulating layer 13 and covered by the rib layer 5. The rib layer 5 is in contact with the inorganic insulating layer 13 through openings LE1a, LE2a, and LE3a. The partition wall 6 is placed on top of the rib layer 5.

[0087] In dummy sub-pixel DP1, the organic layer OR1 is placed on top of the rib layer 5, the upper electrode UE1 covers the organic layer OR1, the cap layer CP1 covers the upper electrode UE1, and the sealing layer SE11 covers the cap layer CP1. In dummy sub-pixel DP2, the organic layer OR2 is placed on top of the rib layer 5, the upper electrode UE2 covers the organic layer OR2, the cap layer CP2 covers the upper electrode UE2, and the sealing layer SE12 covers the cap layer CP2. In dummy sub-pixel DP3, the organic layer OR3 is placed on top of the rib layer 5, the upper electrode UE3 covers the organic layer OR3, the cap layer CP3 covers the upper electrode UE3, and the sealing layer SE13 covers the cap layer CP3.

[0088] The rib layer 5 does not have pixel apertures AP1, AP2, AP3 that overlap with the lower electrodes LE1, LE2, LE3, respectively, in the dummy sub-pixels DP1, DP2, DP3. That is, the lower electrodes LE1, LE2, LE3 are completely covered by the rib layer 5. As a result, the rib layer 5 is interposed between the organic layers OR1, OR2, OR3 and the lower electrodes LE1, LE2, LE3, and the voltage required to cause them to emit light is no longer applied to the organic layers OR1, OR2, OR3.

[0089] Figure 12 is an enlarged plan view of the opening 621. In one example, the opening 621 is provided with recesses 622, 623, and 624. Recess 622 is formed in a concave shape in the X direction. Recesses 623 and 623 are formed in a concave shape in the Y direction.

[0090] Furthermore, the opening 621 may have even more recesses. Also, at least one of the recesses 622, 623, and 624 may be omitted from the opening 621. The opening 621 may be formed in a rectangular shape, for example.

[0091] The area of ​​the opening 621 is larger than the area of ​​each of the openings 611, 612, 613 and openings LE1a, LE2a, LE3a shown in Figure 10. However, the size of the opening 621 is not limited to this example. For example, multiple openings 621 having areas smaller than each of the openings 611, 612, 613 and openings LE1a, LE2a, LE3a may be arranged in the first region AR1.

[0092] Figure 13 is a schematic cross-sectional view of the display device DSP along the line XIII-XIII in Figure 12. In the frame region FA, the organic insulating layer 12 is covered by the inorganic insulating layer 13. The conductive layer CL is placed on top of the inorganic insulating layer 13 and is covered by the rib layer 5. The rib layer 5 is in contact with the inorganic insulating layer 13 in the first region AR1.

[0093] In the frame region FA, the laminated film FL3 is positioned on the rib layer 5 and the partition wall 6. The sealing layer SE13 continuously covers the laminated film FL3 positioned on the rib layer 5 and the laminated film FL3 positioned on the partition wall 6.

[0094] Next, the effects of the display device DSP according to this embodiment will be explained using the display device DSP of the comparative example shown in Figure 14.

[0095] Figure 14 is a schematic plan view of a DSP display device related to a comparative example. The plan view in Figure 14 corresponds to the plan view in Figure 9.

[0096] The lower electrodes LE1, LE2, and LE3 of the display device DSP in the comparative example do not have apertures LE1a, LE2a, and LE3a, respectively. Therefore, in the dummy pixel region DMY, apertures 611, 612, and 613 are covered by the lower electrodes LE1, LE2, and LE3, respectively.

[0097] Furthermore, the partition wall 6 of the display device DSP in the comparative example does not have an opening 621. In addition, the entire surface of the frame region FA is covered with a conductive layer CL. Therefore, the frame region FA does not include the first region AR1 shown in Figure 9. Thus, the second region AR2 is adjacent to the dummy pixel region DMY.

[0098] In this configuration, the region between boundary E1 and boundary E2, excluding the slit SL6, is covered by either the lower electrodes LE1, LE2, LE3, the conductive layer CL, or the partition wall 6. Furthermore, the lower electrodes LE1, LE2, LE3, the conductive layer CL, and the partition wall 6 all contain layers made of metal. Therefore, due to light reflection and other factors at the lower electrodes LE1, LE2, LE3, the conductive layer CL, and the partition wall 6, it is difficult to recognize boundaries E1 and E2.

[0099] This could lead to problems in the manufacturing process of the display device DSP, such as poor alignment accuracy when bonding the display panel PNL and the cover member CO. Furthermore, in the inspection process of the display device DSP, large measurement variations may occur when measuring the misalignment between the display panel PNL and the cover member CO after they have been bonded to the display panel PNL. Therefore, there is a risk of a decrease in the yield of the display device DSP.

[0100] In the region between boundaries E1 and E2, a slit SL6 is positioned where the lower electrodes LE1, LE2, and LE3, the conductive layer CL, and the partition wall 6 do not overlap. However, the area of ​​the slit SL6 is significantly smaller than the area of ​​the region. Therefore, the slit SL6 contributes little to improving the visibility of boundaries E1 and E2.

[0101] In this embodiment, at least a portion of the lower electrodes LE1, LE2, and LE3, which are positioned in the dummy pixel region DMY, have openings LE1a, LE2a, and LE3a that overlap with the openings 611, 612, and 613 of the partition wall 6. Therefore, the area of ​​the region between boundary E1 and boundary E2 that is not covered by the lower electrodes LE1, LE2, and LE3, the conductive layer CL, and the partition wall 6 is larger than the area of ​​the same region in the display device DSP according to the comparative example. This improves the visibility of boundaries E1 and E2. Consequently, the accuracy of the alignment between the display panel PNL and the cover member CO is improved. Furthermore, it becomes possible to suppress measurement variations in the amount of misalignment between the display panel PNL and the cover member CO. As a result, the yield of the display device DSP can be improved.

[0102] Furthermore, in this embodiment, an opening 621 in the partition wall 6 is formed in the first region AR1 where the conductive layer CL is not placed. As a result, the area of ​​the region between boundary E1 and boundary E2 that is not covered by the lower electrodes LE1, LE2, LE3, the conductive layer CL, and the partition wall 6 is further increased. Therefore, the effects of improved alignment accuracy and suppression of measurement variations mentioned above can be obtained.

[0103] The greater the area of ​​the region not covered by the lower electrodes LE1, LE2, LE3, the conductive layer CL, and the partition wall 6, the greater the effect can be obtained. Therefore, by widening the first region AR1 compared to the example in Figure 9 and further arranging multiple openings 621, the above effect can be further enhanced. In this case, it is desirable to place the conductive layer CL or partition wall 6 directly above the thin-film transistor included in the circuit layer 11. This makes it possible to suppress changes in the characteristics of the transistor due to light entering the transistor.

[0104] Incidentally, in the manufacturing process of the display device DSP, the lower electrodes LE1, LE2, and LE3 are patterned by etching. When multiple elements are formed simultaneously by etching in this way, the outermost parts of these elements may be excessively eroded. As a result, the lower electrodes LE1, LE2, and LE3 on the outermost edge of the display area DA may be excessively eroded by etching, potentially leading to a decrease in display quality.

[0105] In this embodiment, dummy pixels DPX having lower electrodes LE1, LE2, and LE3 are arranged in the dummy pixel region DMY adjacent to the display region DA. Therefore, excessive erosion of the outermost lower electrodes LE1, LE2, and LE3 in the display region DA is suppressed, and display quality can be improved. Furthermore, the lower electrodes LE1, LE2, and LE3 adjacent to the display region DA do not have openings LE1a, LE2a, and LE3a, respectively. Therefore, the above-mentioned erosion can be further suppressed.

[0106] Furthermore, in this embodiment, the region where openings 611, 612, 613 and openings LE1a, LE2a, LE3a overlap, as well as opening 621, is covered with an inorganic insulating layer 13. This makes it possible to suppress the penetration of moisture contained in the organic insulating layer 12 into layers above the inorganic insulating layer 13.

[0107] [Second Embodiment] Next, a display device DSP according to the second embodiment will be described. The same or similar elements as in the first embodiment are denoted by the same reference numerals, and redundant explanations will be omitted as appropriate.

[0108] Figure 15 is a plan view showing an enlarged view of the area enclosed by frame IX in Figure 8 of the display device DSP according to the second embodiment. Figure 16 is a schematic plan view showing two dummy pixel DPXs aligned in the X direction of the display device DSP according to the second embodiment.

[0109] As shown in Figures 15 and 16, in the display device DSP according to the second embodiment, the lower electrode LE2 of the dummy pixel DPX2 adjacent to the frame region FA does not have an aperture LE2a that overlaps with the aperture 612. Therefore, the aperture 612 adjacent to the frame region FA is covered by the lower electrode LE2. Also, the lower electrode LE3 of the dummy pixel DPX2 adjacent to the frame region FA does not have an aperture LE3a that overlaps with the aperture 613. Therefore, the aperture 613 adjacent to the frame region FA is covered by the lower electrode LE3.

[0110] Furthermore, as shown in Figure 15, in the display device DSP according to the second embodiment, the partition wall 6 located in the frame region FA does not have an opening 621. Also, the entire surface of the frame region FA is covered with a conductive layer CL. Therefore, the frame region FA does not include the first region AR1 shown in Figure 9. Thus, the second region AR2 is adjacent to the dummy pixel region DMY.

[0111] Furthermore, as shown in Figure 15, in the second region AR2, the partition wall 6 has a plurality of openings 631 connected by slits 632, and a plurality of openings 631 that are not connected by slits 632 and are arranged independently. The contact portion CN is positioned between the openings 631 aligned in the X direction. Note that the arrangement of the openings 631, slits 632, and contact portion CN may be the same as the example shown in Figure 9, or it may be different from the examples shown in Figures 9 and 15.

[0112] In the second embodiment, focusing on the multiple dummy pixels DPX arranged in the X direction, there is one lower electrode LE1, LE2, and LE3, each having an aperture LE1a, LE2a, and LE3a. Furthermore, the partition wall 6 does not have an aperture 621 located in the first region AR1. Therefore, in the second embodiment, the area of ​​the region between boundaries E1 and E2 that is not covered by the lower electrodes LE1, LE2, LE3, the conductive layer CL, and the partition wall 6 is smaller than the area of ​​the region in the first embodiment, but larger than the area of ​​the region in the comparative example. As a result, even with this configuration, boundaries E1 and E2 can be visually identified.

[0113] Furthermore, the DSP display device according to the second embodiment provides the same effects as the DSP display device according to the first embodiment described above.

[0114] All display devices that a person skilled in the art can implement by appropriately modifying the design based on the display devices described above as embodiments of the present invention also fall within the scope of the present invention insofar as they encompass the gist of the present invention.

[0115] Within the scope of the concept of the present invention, a person skilled in the art can conceive of various modifications, and such modifications are also understood to fall within the scope of the present invention. For example, modifications to the above-described embodiments in which a person skilled in the art has appropriately added, deleted, or modified components, or added, omitted, or modified processes, are also included within the scope of the present invention, as long as they retain the gist of the present invention.

[0116] Furthermore, any other effects and advantages brought about by the embodiments described above that are obvious from the description herein or that can be appropriately conceived by those skilled in the art are naturally considered to be brought about by the present invention. [Explanation of symbols]

[0117] DSP...Display device, DA...Display area, SA...Peripheral area, DMY...Dummy pixel area, FA...Frame area, DE1, DE2, DE3...Display elements, LE1, LE2, LE3...Lower electrodes, OR1, OR2, OR3...Organic layers, UE1, UE2, UE3...Upper electrodes, SE11, SE12, SE13, SE2...Sealing layers, 5...Rib layer, 6...Partition wall, 61...Lower part, 62...Upper part, 63...Bottom layer, 64...Axis layer, 13...Inorganic insulating layer, Cover member...CO, Light-transmitting part...TL, Light-shielding part...BM.

Claims

1. A substrate having a display area for displaying an image, and a dummy pixel area that surrounds the display area and is adjacent to the display area, including a plurality of dummy subpixels that do not display an image, A plurality of lower electrodes are located above the substrate and are arranged in the dummy pixel region, A partition wall is provided, which includes a lower part positioned above the lower electrode and an upper part positioned above the lower part and protruding from the side surface of the lower part, and is positioned across the display area and the dummy pixel area. Each of the plurality of dummy subpixels includes the lower electrode, The partition wall has a first opening that overlaps with the lower electrode, At least a portion of the plurality of lower electrodes has a second opening that overlaps with the first opening. Display device.

2. The cover member further comprises a light-transmitting portion that overlaps with the display area and a light-shielding portion that surrounds the light-transmitting portion, and is located above the partition wall. The display device according to claim 1.

3. The boundary between the light-transmitting portion and the light-shielding portion is located outside the display area in a plan view. The display device according to claim 2.

4. Of the plurality of lower electrodes, the lower electrode adjacent to the display area does not have the second opening. The display device according to claim 1.

5. The rib layer is arranged across the display area and the dummy pixel area, covers the lower electrode in the dummy pixel area, and further comprises a rib layer made of an inorganic material. The partition wall is positioned on the rib layer, The display device according to claim 1.

6. The rib layer covers the first and second openings in a plan view. The display device according to claim 5.

7. The device further comprises a conductive layer located in the same layer as the lower electrode and formed of the same material as the lower electrode, The substrate further has a frame region that surrounds the dummy pixel region and is adjacent to the dummy pixel region, on which the partition wall and the conductive layer are arranged. The frame region has a first region that does not overlap with the conductive layer. The partition wall has a third opening located in the first region. The display device according to claim 1.

8. The first region surrounds the dummy pixel region and is adjacent to the dummy pixel region. The display device according to claim 7.

9. The area of ​​the third opening is larger than the area of ​​the first opening and the second opening, The display device according to claim 7.

10. An organic insulating layer located between the substrate and the lower electrode, and distributed across the display area and the dummy pixel area, The system further comprises an inorganic insulating layer that covers the organic insulating layer and is in contact with the lower surface of the lower electrode. The display device according to claim 1.

11. The inorganic insulating layer covers the first opening and the second opening. The display device according to claim 10.

12. The rib layer is arranged across the display area and the dummy pixel area, covers the lower electrode in the dummy pixel area, contacts the inorganic insulating layer through the second opening, and is further made of an inorganic material. The partition wall is positioned on the rib layer, The display device according to claim 10.

13. The device further comprises a conductive layer located in the same layer as the lower electrode and formed of the same material as the lower electrode, The substrate further has a frame region that surrounds the dummy pixel region and is adjacent to the dummy pixel region, on which the partition wall and the conductive layer are arranged. The frame region has a first region that does not overlap with the conductive layer. The partition wall is located in the first region and has a third opening that is covered by the inorganic insulating layer. The display device according to claim 10.

14. The rib layer is arranged across the display area and the dummy pixel area, covers the lower electrode in the dummy pixel area, contacts the inorganic insulating layer through the third opening, and is further made of an inorganic material. The partition wall is positioned on the rib layer, The display device according to claim 13.

15. The partition wall has a plurality of slits arranged in the display area and the dummy pixel area and extending in one direction, The plurality of slits are arranged so as not to overlap with the lower electrode in a plan view. The display device according to claim 1.

16. The aforementioned dummy subpixel is, An organic layer placed on the rib layer, The upper electrode covering the organic layer, A cap layer covering the upper electrode, The cap layer further comprises a sealing layer made of an inorganic insulating material that covers the cap layer, The display device according to claim 5, 12, or 14.

17. A substrate having a display area for displaying an image and a peripheral area outside the display area, A conductive layer located above the substrate and positioned in the peripheral region, A partition wall is provided, comprising a lower portion disposed above the conductive layer and an upper portion disposed above the lower portion and protruding from the side surface of the lower portion, and extending across the display area and the peripheral area. The partition wall has a first opening that overlaps with the conductive layer, The conductive layer has a second opening that overlaps with the first opening. Display device.

18. The peripheral region includes a dummy pixel region that surrounds and is adjacent to the display region, containing a plurality of dummy subpixels that do not display an image, and a frame region that surrounds and is adjacent to the dummy pixel region. The first aperture and the second aperture are arranged in the dummy pixel region. The display device according to claim 17.

19. The frame region has a first region that does not overlap with the conductive layer. The partition wall has a third opening located in the first region. The display device according to claim 18.

20. The cover member further comprises a light-transmitting portion that overlaps with the display area and a light-shielding portion that surrounds the light-transmitting portion, and is located above the partition wall. The boundary between the light-transmitting portion and the light-shielding portion overlaps with the surrounding region in a plan view. The display device according to claim 17.

Images