Support for cryptographic operations on serial memory interfaces

Abstract

It provides a key cache that supports cryptographic operations related to the Serial Memory Interface (SMIF). [Solution] The processing device determines that the memory address corresponding to the encrypted data communicated via the Serial Memory Interface (SMIF) is within the range of the memory addresses corresponding to the calculated key stored in the key cache. In response to the determination that the memory address is within the range of the memory addresses corresponding to the calculated key, an exclusive OR (XOR) operation is performed on the encrypted data and the calculated key to generate the plaintext corresponding to the encrypted data.

Description

Technical Field

[0001] This disclosure generally relates to the field of cryptography, and more particularly, to a key cache for supporting cryptographic operations related to a serial memory interface (SMIF).

[0002] Background Art Serial communication refers to communication that transfers information bit by bit in sequence. A serial memory interface (SMIF) can refer to a multi-functional hardware block that performs serial communication. For example, an SMIF can implement serial peripheral interface (SPI) communication to external serial memory devices such as NOR (NOT-OR) flash, static random access memory (SRAM), and non-volatile SRAM. The serial peripheral interface (SPI) is a standard (with many variants) for synchronous serial communication mainly used in embedded systems for short-distance wired communication between integrated circuits.

[0003] Some SMIFs may support execute-in-place (XIP) access to memory. XIP can refer to a method of directly executing from a long-term storage device rather than copying a program into RAM. This is an extension that uses shared memory to reduce the total amount of memory required. The general effect of XIP is that writable memory is not consumed by program text, is reserved for dynamic data, and all instances of a program are executed from a single copy.

[0004] To easily identify the description of any particular element or act, the most significant digit of a reference number refers to the figure number in which that element is first introduced.

Brief Description of the Drawings

[0005] [Figure 1] Exemplary aspects of a computing device according to some embodiments of this disclosure are shown. [Figure 2] This disclosure illustrates various ways of generating a computed key according to several embodiments of this disclosure. [Figure 3] This disclosure illustrates various forms of input data for generating a computed key according to several embodiments of this disclosure. [Figure 4] This disclosure illustrates various embodiments that support cryptographic operations related to SMIF according to several embodiments of this disclosure. [Figure 5] This disclosure provides exemplary logic flows for supporting cryptographic operations on SMIF according to several embodiments of this disclosure.

[0006] Modes for carrying out the invention The following description includes numerous specific details, such as examples of particular systems, components, and methods, in order to provide a good understanding of the various embodiments of the technology described herein for supporting cryptographic operations related to SMIF. However, it will be apparent to those skilled in the art that at least some embodiments may be carried out without these specific details. In other cases, in order to avoid unnecessarily obscuring the technology described herein, well-known components, elements, or methods are not described in detail or are presented in simple block diagram form. Thus, the specific details described below are merely illustrative. Certain implementations may differ from these illustrative details and are still considered to be within the scope of this disclosure.

[0007] Existing serial interfaces such as SMIF cannot efficiently support cryptographic operations, such as those for XIP. Even though the same key is used to decrypt multiple bytes of data, the key may be recalculated for each byte of data, leading to excessive and unnecessary computation. For example, while block ciphers can generate a calculated key for each memory address accessed byte by byte (e.g., based on byte-by-byte instructions), the calculated key may be valid for a range of memory addresses. This leads to inefficient operation because resources are consumed to calculate the same key for each memory address within that range. These challenges and complexities often stem from the fact that existing systems cannot efficiently support cryptographic operations with sufficient or desirable memory resources. For example, existing systems may not have available or practical (e.g., secure, low-latency, etc.) memory (e.g., hardware cache) to facilitate the reuse of keys calculated for a range of memory addresses. These limitations significantly reduce the usefulness of existing systems with serial interfaces and can result in limited and inefficient systems, devices, and technologies.

[0008] Embodiments of this disclosure address the above and other problems by including a key cache along with logic to prevent recalculating the computed key when the computed key is still available. In some embodiments, these techniques can be used to reduce the number of times the ciphertext (e.g., the computed key) is generated in order to perform on-the-fly decryption. In many embodiments, the cache may include a hardware cache configured to store the computed key in order to enable more efficient generation of plaintext. For example, the computed key may remain the same for a range of memory addresses. Thus, embodiments disclosed herein may include a key cache for storing the computed key, as well as logic for reusing the computed key for each memory address within the range of memory addresses instead of recalculating the computed key. In other words, the computed key only needs to be generated once for the entire set of memory addresses that can be decrypted using the computed key.

[0009] In these and other ways, the components / technologies described herein can provide numerous technical advantages. For example, embodiments can improve the efficiency of cryptographic operations, such as decryption operations, by enabling the reuse of computed keys. In another example, embodiments can enable cryptographic operations when memory is accessed on a byte-by-byte instruction basis. In yet another example, embodiments can enable support for cryptographic operations in XIP operating mode. Thus, the computer-based technologies of this disclosure improve cryptographic operations with respect to serial interfaces compared to conventional methods. Furthermore, embodiments disclosed herein can be practically used to improve the functionality of computers and / or improve various technical fields, including cryptography, serial communications, XIP, and memory devices.

[0010] The exemplary examples and embodiments presented above are provided to introduce the reader to the overall subject matter described herein and are not intended to limit the scope of the ideas disclosed. The following sections describe various further features and examples with reference to the drawings, where similar figures in the drawings represent similar elements, but like the exemplary examples, they should not be used to limit this disclosure.

[0011] Figure 1 shows exemplary embodiments of a computing device 102 according to several embodiments. In the illustrated embodiments, the computing device 102 includes an SMIF 104, memory 106, a cache 108, an exclusive OR (XOR) logic 120, an encryption manager 110 having a block cipher 122, memory 126, and a processing device 128. The illustrated components of the computing device 102 can cooperate to support efficient cryptographic operations on data stored in memory 106 and accessed via SMIF 104. One or more components in Figure 1 may be identical or similar to one or more other components disclosed herein. Furthermore, embodiments described with respect to the various components of Figure 1 may be carried out by one or more other components from one or more other embodiments without departing from the scope of this disclosure. For example, one or more components of the computing device 102, such as a cache 108, an encryption manager 110, an XOR logic 120, and / or a block cipher 122, may be included in the SMIF 104 and / or processing device 128 without departing from the scope of this disclosure. Embodiments are not limited in this context.

[0012] According to embodiments described herein, the computing device 102 may utilize the cache 108 to perform cryptographic operations in a more efficient manner, such as by generating plaintext 124 in a more efficient manner. The cache 108 may include a hardware cache configured to store a computed key in order to enable more efficient generation of plaintext. In various embodiments, the computed key 118 may include ciphertext that can be XORed with the corresponding encrypted data to generate plaintext. For example, a cryptographic operation can be initiated to convert encrypted data 114 in memory 106 into plaintext 124. In some embodiments, this operation may be performed as part of an XIP access via SMIF 104, such as on-the-fly decryption. As part of this operation, the cryptographic manager 110 may determine whether the memory address of the encrypted data 114 falls within the range of memory addresses corresponding to the computed key 118. More generally, the encryption manager 110 may include logic (e.g., within the processing device) to determine whether the encrypted data 114 can be decrypted using a computed key stored in the cache 108 (e.g., via XOR logic 120), and whether a new computed key needs to be generated.

[0013] In some embodiments, the encryption manager 110 can determine, based on input data 116, whether the memory address of the encrypted data 114 falls within the range of memory addresses corresponding to the calculated key 118. For example, as will be described in more detail below with respect to Figure 3, the input data 116 may include data corresponding to the memory address of the encrypted data 114. In many embodiments, the encryption manager 110 can compare the memory address (e.g., SMIF address) or a portion thereof of the encrypted data 114 with data indicating the range of memory addresses corresponding to the calculated key 118. In various embodiments, the encryption manager 110 or another component may store data indicating the range of memory addresses corresponding to the calculated key 118. For example, in one embodiment, data indicating the range of memory addresses corresponding to the calculated key 118 may be stored in the cache 108.

[0014] If the memory address of the encrypted data 114 falls within the range of memory addresses corresponding to the calculated key 118, the encryption manager 110 can generate plaintext 124 by performing an exclusive OR operation on the calculated key 118 and the encrypted data 114 using the XOR logic 120. However, if the memory address of the encrypted data 114 does not fall within the memory range, the encryption manager 110 can have the block cipher 122 generate a new calculated key and store it in the cache 108 as the calculated key 118. Each newly calculated key can be generated by the block cipher 122 based on the input data 116 and the secret key 112. The new calculated key can be stored in the cache 108 as the calculated key 118. The encryption manager 110 can then generate plaintext 124 by performing an exclusive OR operation on the new calculated key 118 and the encrypted data 114 using the XOR logic 120. This process can be repeated as needed to access the encrypted data stored in memory 106.

[0015] In various embodiments, the block cipher 122 may include a symmetric key algorithm. In various such embodiments, the symmetric key algorithm can operate on 128-bit blocks of data (e.g., input data 116) using a 128-bit, 192-bit, or 256-bit encryption key (e.g., secret key 112) to generate 128-bit blocks of output data (e.g., computed key 118). In some embodiments, the symmetric key algorithm may include or utilize the Advanced Encryption Standard (AES). Thus, the block cipher 122 may include a forward block cipher of AES-128.

[0016] Memory 106 may be communicatively connected to other components of the computing device 102 via SMIF 104. More generally, SMIF 104 can implement at least some instances of serial communication in the computing device 102. For example, memory 106 may include a serial memory device such as dynamic random access memory (DRAM), and SMIF 104 can implement serial peripheral interface (SPI) communication with memory 106. Thus, in many embodiments, memory 106 may include or point to memory accessed by the computing device 102 via SMIF 104. On the other hand, memory 126 may point to memory of the computing device 102 that is not accessed via SMIF 104. In some embodiments, memory 106 may point to external memory, and memory 126 may point to internal memory. In some embodiments, one or more of the illustrated components of the computing device 102, such as components used to implement the technology disclosed herein, may be included in memory or an interface device such as SMIF. In some such embodiments, this memory or interface device may be included in a larger computing device or system, such as a microcontroller unit or a system-on-a-chip.

[0017] For the sake of simplicity or clarity, various components may be described and illustrated separately, but it should be noted that one or more of these components may be combined or shared without departing from the scope of this disclosure. For example, while a single processing device is shown in computing device 102 for simplicity, other embodiments may include multiple processing devices, storage devices, or other components. For example, SMIF 104, XOR logic 120, or block cipher 122 may include separate processing devices that implement different aspects of the technology described herein. Processing device 128 and / or other processing devices may include a composite instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, or a processor implementing a processor or combination of instruction sets. Furthermore, in many embodiments, the processing device 128 and / or other processing devices may include one or more special-purpose processing devices such as application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), digital signal processors (DSPs), network processors, system-on-a-chip (SOCs), and μ-controllers.

[0018] Figure 2 illustrates various embodiments for generating a computed key 216. The illustrated embodiments include one or more input caches 202, one or more secret key caches 204, one or more computed key caches 206, and a block cipher 208. The block cipher 208 can generate a computed key 216 based on the contents of one or more input caches 202 and one or more secret key caches 204. The computed key 216 can be stored in one or more computed key caches 206 for later use in efficient cryptographic operations on memory accessed via a serial interface such as SMIF. One or more components of Figure 2 may be identical or similar to one or more other components disclosed herein. For example, the computed key cache 206 may be identical or similar to cache 108. In another example, the block cipher 208 may be identical or similar to block cipher 122. In yet another example, input data 116 may be identical or similar to input data 210. Furthermore, embodiments described with respect to the various components of Figure 2 may be implemented by one or more other components from one or more other embodiments without departing from the scope of this disclosure. For example, the input cache 202, the secret key cache 204, the computed key cache 206, and / or the block cipher 208 may be implemented by the computing device 102 without departing from the scope of this disclosure. Embodiments are not limited in this context.

[0019] As previously stated, the techniques described herein enable more efficient cryptographic operations. This is achieved, at least in part, by incorporating a computed key cache 206. More specifically, the computed key cache 206 can be used to prevent the recalculation of the key for each memory address, such as when the CPU generates instructions byte by byte, resulting in more efficient cryptographic operations. For example, multiple memory addresses can utilize the same computed key, and the computed key cache 206 can be used to store and reuse the same computed key for each of the multiple memory addresses. In contrast, existing systems recalculate the same computed key each time they access one of the multiple memory addresses for which the computed key is valid.

[0020] In many embodiments, the computed key cache 206 includes a hardware cache. In many such embodiments, the hardware cache may be contained within a dynamic random access memory device. For simplicity, it will be understood that each of the caches 202, 204, and 206 is generally referred to as singular, even though they may be implemented as multiple caches. For example, the input cache 202 may store 16 bytes of data in four separate 4-byte caches. In another example, the computed key cache 206 may store 16 bytes of data in four separate 4-byte hardware caches. In one embodiment, the computed key cache 206 may include an indication of a range of memory addresses in which the computed key 216 is valid.

[0021] The block cipher 208 can generate a computed key 216 using the contents of the input cache 202 and the secret key cache 204. For example, the input data 210 may include encrypted data memory address information (EDMAI) 212. The EDMAI 212 may, among other things, include the memory address of the data to be decrypted (e.g., encrypted data 114). In some embodiments, the EDMAI 212 can be used to determine whether it is necessary to generate a new computed key. For example, as will be described in more detail below with respect to Figure 4, only a portion of the EDMAI 212 may be used to generate the computed key 216. This portion of the EDMAI 212 may correspond to a range of addresses to which the computed key 216 corresponds. For example, the portion of the EDMAI 212 used by the block cipher 208 to generate the computed key 216 may include n most significant bits in the memory address, while i least significant bits are ignored (e.g., i=4 and n=28 for a 32-bit address). Therefore, the range of memory addresses corresponding to the n most significant bits can indicate the range of memory addresses where the corresponding computed key is valid.

[0022] In some embodiments, the block cipher 208 may include a symmetric key algorithm that computes a key 216 based on input data 210 and a secret key 214. In various such embodiments, the symmetric key algorithm can operate on 128-bit blocks of input data (e.g., input data 210) using a 128-bit, 192-bit, or 256-bit encryption key (e.g., secret key 214) to generate 128-bit blocks of computed key data (e.g., computed key 216). In various embodiments, the computed key 216 may include ciphertext that can be XORed with the corresponding encrypted data to generate plaintext. In some embodiments, the symmetric key algorithm may include or utilize the Advanced Encryption Standard (AES). In some such embodiments, the block cipher 208 may include a forward block cipher of AES-128.

[0023] Figure 3 shows various forms of input data 304 for generating a computed key according to several embodiments. The illustrated embodiments include input caches 302a, 302b, 302c, and 302d (collectively referred to as input cache 302). The first input cache 302a includes fixed data 306a, the second input cache 302b includes fixed data 306b, the third input cache 302c includes fixed data 306c, and the fourth input cache 302d includes encrypted data memory address information (EDMAI) 308. The data in input cache 302 as a whole forms input data 304 including address bits 314 and extended address bits 312. As described above, the input data 304 can be used together with an encryption key to generate a computed key that can be XORed with the corresponding encrypted data to generate plaintext. One or more components of Figure 3 may be identical or similar to one or more other components disclosed herein. For example, input cache 302 may be identical or similar to input cache 202. In another example, input data 304 may be identical or similar to input data 116. Furthermore, embodiments described with respect to the various components of Figure 3 may be implemented by one or more other components from one or more other embodiments without departing from the scope of this disclosure. Embodiments are not limited in this context.

[0024] Although other sizes are possible without departing from the scope of the present disclosure, FIG. 3 is illustrated and described with respect to input data 304 that includes 128 bits or 16 bytes. Further, each input cache 302 stores 4 bytes. In some embodiments, the contents of the input caches 302 can be concatenated to generate the input data 304. Thus, the input data 304 includes four blocks of 4 bytes (or 32 bits). The first block corresponds to the contents of the input cache 302d and includes bits [31:0] of the input data 304, the second block corresponds to the contents of the input cache 302c and includes bits [63:32] of the input data 304, the third block corresponds to the contents of the input cache 302b and includes bits [95:64] of the input data 304, and the fourth block corresponds to the contents of the first input cache 302a and includes bits [127:96] of the input data 304. Thus, the 12 most significant bytes can include fixed data, and the 4 least significant bytes can include memory address information of the encrypted data.

[0025] The second, third, and fourth blocks of the input data 304 include fixed data. The fixed data can be utilized for, among other things, the configuration of the cipher block, the selection of the mode, ensuring an appropriate block size, etc. For example, the input data 304 can include a nonce value that pads the input data 304 to ensure that the input to the block cipher is 16 bytes. The first block of the first input cache 302a includes EDMAI 308 (e.g., address information). In various embodiments, the address information can include the memory address of the encrypted data for which decryption is requested. The address information within the input data 304 includes address bits 314 and extended address bits 312. The address bits 314 may be utilized in the generation of the computed key, while the extended address bits 312 need not be utilized in the generation of the computed key. Thus, the computed key can be the same for each memory address that includes the address bits 314.

[0026] In many embodiments, address bits 314 and extended address bits 312 can include or indicate the entire memory address of the encrypted data (e.g., the address of encrypted data 114 on memory 106). Furthermore, since the calculated key is the same for all values ​​of extended address bits 312, address bits 314 can indicate the range of memory addresses for which the calculated key is valid and can be used to decrypt data within that range of memory addresses. For example, if the CPU is attempting to read addresses 0x80000000 to 0x800000FF, 0x800000 is used by the block cipher to generate the calculated key, and the calculated key for 0x80000000 to 0x800000FF will be the same. In various embodiments, the 28 most significant bits of the memory address information of the encrypted data can be used to generate the calculated key and / or to determine whether the memory address corresponding to the encrypted data is within the range of memory addresses corresponding to the calculated key. In many embodiments, the determination of whether the memory address corresponding to the encrypted data is within the range of the memory addresses corresponding to the computed key, and / or whether a new computed key needs to be generated, may be performed via logic circuits, such as logic circuits included in the processing device.

[0027] Figure 4 shows various aspects that support cryptographic operations related to SMIF according to some embodiments. The illustrated embodiments include a forward block cipher 402, a first XOR gate 404a, a second XOR gate 404b, and a data input / output including a computed key 406, a secret key 408, input data 410, encrypted read data 412, encrypted write data 414, decrypted read data 416, and decrypted write data 418. In various embodiments, these components and the data input / output can be utilized to generate the computed key 406, the decrypted read data 416, and / or the encrypted write data 414. One or more components of FIG. 4 may be the same or similar to one or more other components disclosed herein. For example, the forward block cipher 402 may be the same or similar to the block cipher 208. In another example, the input data 410 may be the same or similar to the input data 116. Further, the aspects described with respect to the various components of FIG. 4 may be implemented by one or more other components from one or more other embodiments without departing from the scope of the present disclosure. For example, the encrypted read data 412 may be received from the memory 106 via the SMIF 104 without departing from the scope of the present disclosure. In another embodiment, the computed key 406 may be received from the cache 108 without departing from the scope of the present disclosure. The embodiments are not limited in this context.

[0028] In various embodiments, the forward block cipher 402 can generate the computed key 406 based on the secret key 408 and the input data 410. For example, the forward block cipher 402 can include the forward block cipher of AES-128 that obtains the secret key 408 as a 128-bit block and the input data 410 as a 128-bit block as an input to an encryption algorithm that outputs the computed key 406. In various embodiments, the computed key 406 may be stored in a cache such as a hardware cache.

[0029] In many embodiments, the decrypted read data 416 can be generated by passing the calculated key 406 and the encrypted read data 412 through an XOR gate 404a. For example, if it is determined that the calculated key 406 corresponds to the encrypted read data 412, the calculated key 406 can be XORed with the encrypted read data 412 by the XOR gate 404a to generate the decrypted read data 416. In some embodiments, the decrypted read data 416 may be further processed by a CPU or the like. In some embodiments, the encrypted write data 414 can be generated by passing the calculated key 406 and the decrypted write data 418 through an XOR gate 404b.

[0030] The configuration and layout of the components in Figure 4 are illustrative, and it should be understood that various alternative layouts and configurations can be used without departing from the scope of this disclosure. For example, some configurations can utilize a single XOR gate.

[0031] Figure 5 shows a logic flow 500 for supporting cryptographic operations on SMIF according to several embodiments. The logic flow 500 may be implemented by processing logic which may include hardware and / or control logic (e.g., circuits, dedicated logic, programmable logic, processors, processing devices, central processing units (CPUs), system-on-a-chip (SoCs), etc.), software (e.g., instructions that operate on / execute on the processing device), firmware (e.g., microcode), or a combination thereof. In some embodiments, at least a portion of the logic flow 500 may be implemented by one or more components of the computing device 102, SMIF 104, block cipher 122, XOR logic 120, cryptographic manager 110, and / or processing device 128. Embodiments are not limited in this context.

[0032] Referring to Figure 5, the logical flow 500 shows exemplary functionality used by various embodiments. While certain functional blocks ("blocks") are disclosed in the logical flow 500, such blocks are examples only. That is, the embodiments are well suited to the execution of various other blocks or variations of the blocks enumerated in the logical flow 500. It will be understood that the blocks in the logical flow 500 may be executed in an order different from the presented order, and that not all blocks in the logical flow 500 may be executed.

[0033] The logical flow 500 begins with a start block 502. From the start block 502, the logical flow 500 proceeds to a determination block 504, where it is determined whether the memory address of the encrypted data is within the memory address range of the calculated key. For example, the encryption manager 110 can determine whether the memory address of the encrypted data 114 is within the memory address range corresponding to the calculated key 118. In some embodiments, this determination can be made based on the input data 116, as described above. For example, the memory address of the encrypted data 114 or a portion thereof included in the input data 116 can be compared with data indicating the range of memory addresses corresponding to the calculated key 118.

[0034] If the memory address of the encrypted data is not within the memory range of the computed key, the logical flow 500 proceeds to block 506. In block 506, a new computed key is generated. For example, block cipher 208 may generate a computed key 216 based on the secret key 214 and the input data 210 corresponding to the encrypted data. The process proceeds to block 508, where the new computed key can be stored in the key cache. For example, the new computed key can replace a previous computed key, such as computed key 118, in cache 108.

[0035] Next, the logical flow 500 proceeds to block 510. Further referencing the decision block 504, if the memory address of the encrypted data is within the memory range of the calculated key, the logical flow 500 proceeds to block 510. In block 510, the encrypted data can be XORed with the calculated key in the key cache to generate plaintext. For example, the XOR gate 404a can be used to XOR the calculated key 406 with the encrypted read data 412 to generate the decrypted read data 416.

[0036] In the above description, some parts of the detailed description are presented with respect to algorithms and coded representations of operations on analog and / or digital signals or data bits in non-temporary storage media. These descriptions and representations of algorithms are means used by those skilled in the data processing technology to most effectively communicate the nature of the work to others skilled in the art. An algorithm is generally considered herein to be a self-consistent set of steps that produce a desired result. These steps require the physical manipulation of physical quantities. Typically, these quantities take the form of electrical or magnetic signals that can be stored, transferred, combined, compared, and other manipulated. Referring to these signals as bits, values, elements, symbols, characters, terms, numbers, etc., has sometimes proven convenient, primarily for reasons of common use.

[0037] References in the specification such as “an embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” mean that certain features, structures, steps, operations, or characteristics described in relation to those embodiments are included in at least one embodiment of the disclosure. Furthermore, the appearance of phrases such as “embodiment,” “one embodiment,” “an example embodiment,” “some embodiments,” and “various embodiments” in various parts of this specification does not necessarily all refer to the same embodiment.

[0038] This specification includes references to accompanying drawings that form part of the detailed description. The drawings illustrate exemplary embodiments. These embodiments, which may also be referred to herein as “examples,” are described in sufficient detail to enable a person skilled in the art to practice embodiments of the claimed subject matter described herein. Embodiments can be combined, other embodiments can be utilized, or structural, logical, and electrical modifications can be made without departing from the scope and spirit of the claimed subject matter. It should be understood that the embodiments described herein are not intended to limit the scope of the subject matter, but rather to enable a person skilled in the art to practice, manufacture, and / or use the subject matter.

[0039] However, it should be kept in mind that all these terms and similar terms should be associated with appropriate physical quantities and are merely convenient labels applied to those quantities. As is evident from the above description, unless otherwise specified, descriptions throughout the specification using terms such as “determine,” “execute,” “calculate,” and “store” are understood to refer to the operation and processing of a processing device, integrated circuit (IC) controller, or similar electronic device that manipulates data represented as physical (e.g., electronic) quantities in the controller’s registers and memory and converts it into other data also represented as physical quantities in the controller’s memory or registers or other non-temporary storage media of such information.

[0040] In this specification, the terms “example” or “exemplary” are used to mean an example, a real-world example, or an illustration. No aspect or design described herein as “example” or “exemplary” should necessarily be construed as being preferable or advantageous to any other aspect or design. Rather, the use of the terms “example” or “exemplary” is intended to concretely present a concept. As used in this application, the term “or” is intended to mean an inclusive “or” rather than an exclusive “or.” That is, unless otherwise specified or evident from the context, “X includes at least one of A or B” or “X includes A or B” is intended to mean any of the obvious inclusive sortings. That is, if X includes A, if X includes B, or if X includes both A and B, then “X includes at least one of A or B” or “X includes A or B” is satisfied in any of the aforementioned cases. Similarly, “X includes one or more of A and B” should be interpreted as the same as “X includes at least one of A or B.” In addition, the articles “a” and “an” used in this application and the attached claims should generally be interpreted as meaning “one or more” unless otherwise specified or the context makes it clear that they refer to a singular form. Furthermore, throughout this application, the use of the terms “an embodiment” or “one embodiment” or “an embodiment” or “one embodiment” is not intended to mean the same embodiment or representation unless otherwise stated.

[0041] Furthermore, embodiments described herein may relate to devices for performing the operations described herein (e.g., wireless communication equipment including at least one of terminal equipment, client equipment, stations (STAs), access points, routers, or coordinators). Such devices may be specifically configured for a particular purpose or may include firmware or hardware logic that can be selectively activated or reconfigured by the device. Such firmware may be stored in non-transient computer-readable storage media such as, but are not limited to, read-only memory (ROM), random access memory (RAM), EPROM, EEPROM, flash memory, or any type of medium suitable for storing electronic instructions. The term “computer-readable storage medium” should be interpreted as including one or more media for storing one or more instruction sets. Furthermore, the term “computer-readable medium” should be interpreted as including any medium capable of storing, encoding, or carrying instruction sets for machine execution, causing a machine to perform any one or more of the methods of these embodiments. Therefore, the term “computer-readable storage medium” shall be interpreted as including, but not limited to, solid-state memory, optical media, electromagnetic media, and any medium capable of storing an instruction set for machine execution, causing a machine to execute any one or more of the methods of this embodiment. Furthermore, “computer-readable medium” or “computer-readable storage medium” may be non-temporary.

[0042] The above description includes numerous specific details, such as examples of particular systems, components, and methods, to enhance the understanding of some embodiments of the present disclosure. It should be understood that the above description is intended as an illustration and not as a limitation. Many other embodiments will be apparent to those skilled in the art upon reading and understanding the above description. Therefore, the scope of the present disclosure should be determined by referring to the appended claims and together with the entire scope of equivalents given to such claims.

Claims

1. The processing device determines whether the memory address corresponding to the encrypted data communicated via the Serial Memory Interface (SMIF) is within the range of the memory addresses corresponding to the computed key stored in the key cache, In response to the determination that the memory address is within the range of the memory address, an exclusive OR (XOR) operation is performed on the encrypted data and the calculated key to generate plaintext corresponding to the encrypted data. Methods that include...

2. The method according to claim 1, wherein the key cache comprises a hardware cache.

3. The method according to claim 2, wherein the hardware cache is included in a dynamic random access memory chip.

4. The method according to claim 1, wherein the encrypted data is communicated via the SMIF as part of an Execute-in-Place (XIP) operation.

5. The method according to claim 1, wherein the calculated key includes a ciphertext.

6. The method according to claim 1, wherein the range includes 16 bytes of memory.

7. The method according to claim 1, wherein the calculated key is calculated based on a symmetric key algorithm.

8. The method according to claim 7, wherein the symmetric key algorithm includes the Advanced Encryption Standard algorithm.

9. The memory address includes a first memory address, the encrypted data includes first encrypted data, the calculated key includes a first calculated key, and the method is Determining that the second memory address corresponding to the second encrypted data communicated via the SMIF is outside the range of the memory addresses corresponding to the first calculated key stored in the key cache, The process involves calculating a second key based on the second encrypted data and generating the second calculated key, The second calculated key is stored in the key cache. The method according to claim 1, further comprising:

10. Cache and, A processing device connected to the aforementioned cache and It is equipped with, The processing device is It is determined that the memory address corresponding to the encrypted data communicated via SMIF is within the range of the memory addresses corresponding to the calculated key stored in the cache. In response to the determination that the memory address is within the range of the memory address, an exclusive OR (XOR) operation is performed on the encrypted data and the calculated key to generate the plaintext corresponding to the encrypted data. A microcontroller configured in such a way.

11. The microcontroller according to claim 10, wherein the cache comprises a hardware cache.

12. The microcontroller according to claim 11, wherein the hardware cache is included in a dynamic random access memory chip.

13. The microcontroller according to claim 10, wherein the encrypted data is communicated via the SMIF as part of an Execute-in-Place (XIP) operation.

14. The microcontroller according to claim 10, wherein the calculated key includes a ciphertext.

15. The microcontroller according to claim 10, wherein the range includes 16 bytes of memory.

16. The microcontroller according to claim 10, wherein the calculated key is calculated based on a symmetric key algorithm.

17. The microcontroller according to claim 16, wherein the symmetric key algorithm includes the Advanced Encryption Standard algorithm.

18. Hardware cache and Serial Memory Interface (SMIF) and It is equipped with, The aforementioned SMIF is, It is determined that the memory address corresponding to the encrypted data communicated via the SMIF is within the range of the memory addresses corresponding to the calculated key stored in the hardware cache. In response to the determination that the memory address is within the range of the memory address, an exclusive OR (XOR) operation is performed on the encrypted data and the calculated key to generate the plaintext corresponding to the encrypted data. A system-on-a-chip (SOC) device configured in such a way.

19. The SOC device according to claim 18, wherein the calculated key is calculated based on a symmetric key algorithm.

20. The SOC device according to claim 18, wherein the hardware cache is included in a dynamic random access memory chip.

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