Indication device

Abstract

To provide a novel display device. [Solution] The system comprises a pixel section and a drive circuit section located outside the pixel section. The pixel section comprises pixel electrodes arranged in a matrix and transistors electrically connected to the pixel electrodes. The transistors comprise a gate electrode, a gate insulating layer on the gate electrode, an oxide semiconductor layer on the gate insulating layer, and source electrodes and drain electrodes on the oxide semiconductor layer. The drive circuit section comprises first to third wirings formed in the same process as the gate electrode, and source electrodes. The device has a fourth to sixth wiring formed in the same process as the drain electrode, a seventh wiring formed in the same process as the pixel electrode, a first region where the second and fifth wirings intersect, and a second region where the third and sixth wirings intersect, the first and fourth wirings being connected via the seventh wiring, and the distance between wirings in the second region is longer than in the first region.

Description

[Technical Field]

[0001] This invention relates to a product, method, manufacturing method, process, machine, manufacture, or This invention relates to compositions of matter. In particular, the present invention relates to semiconductor equipment, for example. Regarding devices, display devices, light-emitting devices, electronic devices, methods for driving them, or methods for manufacturing them. In particular, the present invention relates to semiconductor devices, display devices, and electronic devices having oxide semiconductors, for example. , or relating to a light-emitting device.

[0002] A display device is a device that has display elements. It may include a drive circuit for driving pixels, etc. Note that the display device is located on a separate circuit board. This may include control circuits, power supply circuits, signal generation circuits, etc. [Background technology]

[0003] Display devices, such as liquid crystal displays, have seen the miniaturization of elements and wiring as a result of recent technological advancements. As progress has been made, mass production technology has also advanced significantly. In the future, we will aim to further improve manufacturing yield. Therefore, cost reduction is required.

[0004] If a surge voltage due to static electricity or other factors is applied to the display device, the elements will be destroyed, and the normal operation will not be possible. The display will become unavailable. As a result, there is a risk that the manufacturing yield will deteriorate. The display device is equipped with a protection circuit to divert surge voltage to another wire (for example) (See Patent Documents 1 to 7). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Application Laid-Open No. 2010-92036 [Patent Document 2] Japanese Patent Application Laid-Open No. 2010-92037 [Patent Document 3] Japanese Patent Application Laid-Open No. 2010-97203 [Patent Document 4] Japanese Patent Application Laid-Open No. 2010-97204 [Patent Document 5] Japanese Patent Application Laid-Open No. 2010-107976 [Patent Document 6] Japanese Patent Application Laid-Open No. 2010-107977 [Patent Document 7] Japanese Patent Application Laid-Open No. 2010-113346 [Summary of the Invention] [Problems to be Solved by the Invention]

[0006] In a display device, a configuration for improving reliability, typified by a protection circuit, is important. There is.

[0007] However, the protection circuit is formed in the manufacturing process of the display device, that is, in the manufacturing process of the transistors used in the display device. Therefore, the transistors during the manufacturing process are not connected to the protection circuit. That is, the transistors during the manufacturing process and the wiring connected to the transistors are likely to be damaged by static electricity or overcurrent that may occur during the manufacturing process of the transistors.

[0008]

[0009] When a display device is manufactured in a state where the transistors and the wiring connected to the transistors are likely to be damaged by static electricity or overcurrent that may occur during the manufacturing process of the transistors, there is a problem that the manufacturing yield is very poor.

[0009] Therefore, in one aspect of the present invention, a display device having a novel configuration capable of reducing electrostatic breakdown is provided. One of the objectives is to provide a suitable location. Alternatively, in one aspect of the present invention, reliability can be improved. One objective is to provide a display device with a novel configuration. Alternatively, in one aspect of the present invention, The objective is to provide a display device with a novel configuration that can reduce the effects of static electricity. Let it be one. Or, in one aspect of the present invention, the effect of malfunctions when using a touch sensor One of the objectives is to provide a display device with a novel configuration that can reduce [amount]. In one aspect of the present invention, it is possible to reduce fluctuations or degradation of the characteristics of the transistor. One objective is to provide a display device with a novel configuration. Alternatively, in one aspect of the present invention, A novel configuration table that can reduce fluctuations or degradation of the transistor threshold voltage. One of the objectives of this invention is to provide a device for demonstrating. Alternatively, in one aspect of the present invention, the transistor The objective is to provide a display device with a novel configuration that can reduce the normal-on state. This is one aspect of the present invention. Alternatively, in one aspect of the present invention, the manufacturing yield of transistors is improved. One of the objectives of this invention is to provide a display device with a novel configuration that can do the following. In one embodiment, a novel display device configuration is provided that can discharge the charge accumulated on the pixel electrodes. One of the objectives is to discharge the charge accumulated in the wiring. One of the objectives is to provide a display device with a novel configuration that can do so. In one embodiment, a novel display device configuration is provided that facilitates normal display. One of the tasks is to do the following.

[0010] Furthermore, the description of these problems does not preclude the existence of other problems. One embodiment does not need to solve all of these problems. This will become clear from the description in the specification, drawings, claims, etc., and the specification, drawings It is possible to extract issues other than those mentioned above from descriptions such as the surface and claims. [Means for solving the problem]

[0011] One aspect of the present invention comprises a pixel portion and a drive circuit portion disposed outside the pixel portion, The unit consists of pixel electrodes arranged in a matrix and transistors electrically connected to the pixel electrodes. A transistor has a gate electrode, a gate insulating layer on the gate electrode, and a gate The system comprises an oxide semiconductor layer on an insulating layer, and source electrodes and drain electrodes on the oxide semiconductor layer. The drive circuit section consists of a first to third wiring formed in the same process as the gate electrode, and a so Fourth to sixth wirings formed in the same process as the drain electrode and the pixel electrode, and The seventh wiring, formed in the same process as the pole, and the first region where the second wiring and the fifth wiring intersect. It has a second region where the third wiring and the sixth wiring intersect, and the first wiring and the fourth wiring It is connected via the seventh wiring, and the second region is characterized by being longer in distance than the first region. It is a distinctive display device. [Effects of the Invention]

[0012] According to one aspect of the present invention, a display device with a novel configuration that can reduce electrostatic discharge is provided. It can be provided. [Brief explanation of the drawing]

[0013] [Figure 1] A schematic top view of the display device and a circuit diagram illustrating the protection circuit. [Figure 2] A diagram illustrating a schematic top view of a display device. [Figure 3] A diagram illustrating a cross-section of a display device. [Figure 4] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 5] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 6] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 7] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 8] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 9] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 10] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 11] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 12] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 13] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 14] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 15] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 16] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 17] A cross-sectional diagram illustrating the method for manufacturing a display device. [Figure 18] A diagram illustrating a cross-section of a display device. [Figure 19] A diagram illustrating the cross-section of a transistor. [Figure 20] A diagram illustrating a cross-section of a display device. [Figure 21] A diagram illustrating the display device, a top view of the outer periphery of the display device, and a diagram illustrating the cross-section of the outer periphery of the display device. [Figure 22] A circuit diagram illustrating a pixel circuit that can be used in a display device. [Figure 23] A cross-sectional view of a transistor and a diagram illustrating oxide layer stacking. [Figure 24] A diagram illustrating a touch sensor. [Figure 25] A circuit diagram illustrating a touch sensor. [Figure 26] A cross-sectional diagram illustrating a touch sensor. [Figure 27] A diagram illustrating a display module using a display device according to one aspect of the present invention. [Figure 28] A diagram illustrating an electronic device using a display device according to one aspect of the present invention. [Figure 29] A diagram illustrating an electronic device using a display device according to one aspect of the present invention. [Figure 30] A diagram showing the micro-electron diffraction pattern of an oxide semiconductor. [Figure 31] A diagram illustrating a radiation image detection device. [Figure 32] A diagram illustrating a radiation detection element. [Figure 33] A top view and a cross-sectional view illustrating the TEG used in the example. [Figure 34] A diagram illustrating the dielectric breakdown voltage of each sample used in the examples. [Figure 35] A circuit diagram illustrating the protection circuit, and a schematic diagram illustrating the signal waveform. [Modes for carrying out the invention]

[0014] The embodiments will be described below with reference to the drawings. However, many of the embodiments differ. It is possible to implement it in any manner, without deviating from its purpose and scope. It will be readily apparent to those skilled in the art that the details can be modified in various ways. Therefore, the present invention The following embodiments are not to be interpreted as being limited to their contents.

[0015] Furthermore, in the drawings, the size, layer thickness, or area is exaggerated for clarity. There are cases where this is not the case. Therefore, it is not necessarily limited to that scale.

[0016] Furthermore, in this specification, the term "transistor" includes a gate, a drain, and a source. It is an element having at least three terminals. And there is a channel region between the drain (drain terminal, drain region or drain electrode) and the source (source terminal, source region or source electrode), and current can flow through the drain, the channel region and the source. Here, since the source and the drain vary depending on the structure or operating conditions of the transistor, etc., it is difficult to limit which is the source or the drain. Therefore, the part functioning as the source and the part functioning as the drain are called the source or the drain, and one of the source and the drain may be denoted as the first electrode, and the other of the source and the drain may be denoted as the second electrode. Also, it is noted that the ordinal numbers "first", "second", "third", etc. used in this specification are attached to avoid confusion of components and are not numerically limiting. In this specification, when it is said that A and B are connected, it includes not only the case where A and B are directly connected but also the case where they are electrically connected. Here, when A and B are electrically connected, it means that when there is an object having some electrical action between A and B, the electrical signals can be exchanged between A and B.

[0017] Also, in this specification, phrases indicating arrangements such as "above" and "below" are used for convenience in explaining the positional relationship between components with reference to the drawings. Also, the positional relationship between components appropriately changes according to the direction in which each component is depicted. Therefore, the description in the specification

[0018]

[0019]

[0020] [[ID=%]]

[0021] ​​​​​​​​​It is not limited to the same words or phrases, and can be appropriately rephrased depending on the situation.

[0021] Furthermore, the placement of each circuit block in the block diagram in the drawings is determined for explanatory purposes, specifying the positional relationship. This is what it does, and even if it is shown that different circuit blocks will achieve different functions, in reality In circuits and domains, they are designed to enable different functions to be realized within the same circuit or domain. In some cases, this may be the case. Also, the function of each circuit block in the block diagram in the drawing is explained for illustrative purposes. It identifies the function, and even if it is shown as a single circuit block, it is relevant to the actual circuit and domain. In this system, processing that would normally be done by a single circuit block is instead performed by multiple circuit blocks. In some cases, this may be the case.

[0022] Furthermore, a pixel is a single color element (for example, one of R (red), G (green), or B (blue)). This refers to a display unit that can control brightness. Therefore, in the case of a color display device... The smallest display unit of a color image consists of three pixels: a red pixel, a green pixel, and a blue pixel. It shall be so. However, the color elements for displaying a color image are not limited to three colors, but rather... You may use the above colors, or you may use colors other than RGB.

[0023] In this specification, embodiments of the present invention will be described with reference to the drawings. The descriptions of each embodiment will be given in the following order. 1. Embodiment 1 (Basic configuration of the display device) 2. Embodiment 2 (Regarding the method for manufacturing the display device) 3. Embodiment 3 (Regarding a modified display device) 4. Embodiment 4 (Regarding variations of the electrostatic discharge region) 5. Embodiment 5 (Regarding the configuration of the pixel section) 6. Embodiment 6 (Regarding the configuration of the transistor) 7. Embodiment 7 (Regarding the touch sensor and display module) 8. Embodiment 8 (Regarding Electronic Devices) 9. Embodiment 9 (Regarding the Radiation Image Detection Device) 10. Examples (Regarding dielectric breakdown voltage)

[0024] (Embodiment 1) In this embodiment, a display device according to one aspect of the present invention will be described with reference to Figures 1 to 3. conduct.

[0025] The display device shown in Figure 1(A) has a region having pixels of the display element (hereinafter referred to as the pixel portion 102). (u) and a circuit section ( ) located outside the pixel section 102 and having a circuit for driving the pixels. Below, referred to as the drive circuit section 104, and a circuit that has a function to protect the element (hereinafter referred to as the protection circuit 106) It has a terminal section 107 and a protection circuit 106. That's good too.

[0026] A portion or all of the drive circuit section 104 is formed on the same substrate as the pixel section 102. This is desirable. This allows for a reduction in the number of components and terminals. Drive circuit section 104 If part or all of it is not formed on the same substrate as the pixel section 102, the drive cycle Part or all of road section 104 is often implemented by COG or TAB. .

[0027] The pixel section 102 is arranged in X rows (where X is a natural number greater than or equal to 2) and Y columns (where Y is a natural number greater than or equal to 2). It has a circuit (hereinafter referred to as the pixel circuit section 108) for driving multiple display elements, and drives The circuit section 104 is a circuit that outputs a signal (scanning signal) to select pixels (hereinafter referred to as the gate driver). (referred to as B104a), which supplies signals (data signals) to drive the display elements of the pixels. It has a drive circuit such as a source driver (hereinafter referred to as source driver 104b).

[0028] The gate driver 104a has a shift register, etc. The gate driver 104a is A signal for driving the shift register is input via terminal 107, and the signal is output. For example, gate driver 104a receives input such as a start pulse signal and a clock signal. It outputs a pulse signal. The gate driver 104a receives the scanning signal via the wiring (and It has the function of controlling the potential of the scan lines (referred to as GL_1 to GL_X) below. Multiple drivers 104a are provided, and multiple gate drivers 104a are used to control the scan line GL_1 The signal to GL_X may be divided and controlled. Alternatively, the gate driver 104a may use an initialization signal. It has the function of supplying, however, the gate driver 10 4a can also supply another signal.

[0029] The source driver 104b has a shift register, etc. The source driver 104b Through terminal 107, in addition to signals for driving the shift register, the data signals are generated. A signal (image signal) is input. The source driver 104b uses the image signal to generate a pixel circuit. It has the function of generating data signals to be written to unit 108. Also, source driver 104b The data is generated according to the pulse signal obtained by inputting a start pulse, clock signal, etc. It has a function to control the output of the signal. In addition, the source driver 104b receives a data signal. It has a function to control the potential of the available wiring (hereinafter referred to as data lines DL_1 to DL_Y). Alternatively, the source driver 104b may have the capability to supply initialization signals. However, the source driver 104b may also supply other signals. It is also possible.

[0030] The source driver 104b is configured using, for example, multiple analog switches. The source driver 104b sequentially turns on multiple analog switches, The image signal can be time-divided and output as a data signal. It can also use shift registers, etc. You may use this to configure source driver 104b.

[0031] Each of the multiple pixel circuit sections 108 is one of the multiple scan lines GL to which a scan signal is applied. A pulse signal is input via and a data signal is provided via one of several data lines DL. Then the data signal is input. Also, each of the multiple pixel circuit sections 108 has a gate drive The writing and retention of data signals are controlled by IBA 104a. For example, row m The pixel circuit section 108 in the nth column is gated via the scan line GL_m (where m is a natural number less than or equal to X). A pulse signal is input from driver 104a, and the data line DL changes according to the potential of the scan line GL_m. A data signal is input from source driver 104b via _n (where n is a natural number less than or equal to Y). ru.

[0032] The protection circuit 106 shown in Figure 1(A) is, for example, a gate driver 104a and a pixel circuit section 1 It is connected to the scan line GL, which is the wiring between 08. Alternatively, the protection circuit 106 is connected to the source driver. It is connected to the data line DL, which is the wiring between the wire 104b and the pixel circuit section 108. Alternatively, The protection circuit 106 is connected to the wiring between the gate driver 104a and the terminal section 107. This is possible. Alternatively, the protection circuit 106 is between the source driver 104b and the terminal section 107. It can be connected to wiring. The terminal section 107 is used to supply power to the display device from an external circuit. This refers to the part that is equipped with terminals for inputting control signals and image signals.

[0033] The protection circuit 106, when a potential outside a certain range is applied to the wiring to which it is connected, This is a circuit that creates a conductive state between two wires.

[0034] As shown in Figure 1(A), the pixel section 102 and the drive circuit section 104 each have a protection circuit 106 By providing ESD (Electrostatic Discharge), This can improve the resistance of display devices to overcurrents generated by electrical discharge, etc. Furthermore, the configuration of the protection circuit 106 is not limited to this; for example, the gate driver 104a may be protected Configuration with protection circuit 106 connected, or with protection circuit 106 connected to source driver 104b It is also possible to use only this configuration. Alternatively, a configuration in which the protection circuit 106 is connected to the terminal section 107 is also possible. It can also be written as "completion".

[0035] Furthermore, in Figure 1(A), the gate driver 104a and the source driver 104b This shows an example of how the drive circuit section 104 is formed, but the configuration is not limited to this. If only the gate driver 104a is formed, and a separately prepared source driver circuit is formed... A substrate (for example, a drive circuit board formed from a single-crystal semiconductor film or a polycrystalline semiconductor film) is mounted. This configuration would also be good.

[0036] In other words, the protection circuit 106 is either the pixel section 102 or the drive circuit section 104. It is preferable that both sides be electrically connected.

[0037] The protection circuit 106 is configured, for example, using diode-connected transistors. This is possible. An example of the protection circuit 106 is shown in Figures 1(B) and 1(C).

[0038] The protection circuit 106 shown in Figure 1(B) has a diode connection between the wiring 110 and the wiring 116. The connected transistors 112 and 114 are connected. Wiring 110 is, for example, shown in Figure 1. The scan line GL and data line DL shown in A), or the drive circuit section 104 from terminal section 107. This is the wiring that is routed. In particular, the protection circuit 106 shown in Figure 1(B) is connected to the pixel section 102 and It is preferable to place it between the driver 104a.

[0039] Furthermore, the wiring 116 supplies power to, for example, the gate driver 104a shown in Figure 1(A). This is wiring to which the potential (VDD, VSS, or GND) of the power line is supplied for the purpose of power supply. This refers to a wiring (common wire) to which a common potential is supplied. One example is wiring 116 is a power line for supplying power to the gate driver 104a, in particular a low potential line. It is preferable to connect it to the supply wiring. This is because the scan line GL is in Therefore, the potential is low. Consequently, the potential of wiring 116 is also low. The ability to reduce the current that leaks from scan line GL to wiring 116 during normal operation is Yes, it's possible.

[0040] The protection circuit 106 shown in Figure 1(C) includes wiring 118, wiring 120, wiring 122, and Transistors 128, 130, and 132 are diode-connected to wire 124 and wire 126. Wires 134 are connected. Wires 118 and 120 are, for example, the source shown in Figure 1(A). The potential of the power lines (VDD, VSS, or GND) that supply power to driver 104b. ), or wiring to which sampling pulses, etc. Wirings 122, 124, 12 6 is, for example, the data line DL shown in Figure 1(A). In particular, the protection circuit shown in Figure 1(C) The path 106 is preferably provided between the pixel unit 102 and the source driver 104b.

[0041] By providing the protection circuit 106 in the display device shown in Figure 1(A) in this way, the pixel section 102 and the drive circuit section 104 have enhanced resistance to overcurrents generated by ESD and the like. It is possible.

[0042] Also, transistors 112 and 114 used in the protection circuit 106 shown in Figures 1(B) and (C) For semiconductor layers 128, 130, 132, and 134, oxide semiconductors are preferable. I. Transistors using oxide semiconductors are different from transistors using silicon or the like in the semiconductor layer. In comparison, it has higher resistance to electric fields because it does not have avalanche breakdown. The transistor structures of transistors 112, 114, 128, 130, 132, and 134 are as follows: For example, planar type and inverse staggered type can be used. Here, the protection shown in Figure 1(B) Using a modified example of circuit 106, we will explain the current and electron flow in the protection circuit.

[0043] A modified example of the protection circuit 106 in Figure 1(B) is shown in Figure 35(A).

[0044] The protection circuit 206 shown in Figure 35(A) consists of transistors 212, 214, 216, and 218. , and has wiring 208, 224, 226.

[0045] Either the source or drain of transistor 212 is connected to wiring 224. The source or drain of transistor 212, the other of which is the source of transistor 214. It is connected to one side of the drain and to the other side of the source or drain of transistor 214. It is connected to wiring 208, and one of the sources or drains of transistor 216 is , connected to the source or drain of transistor 214 and the other side of wiring 208, The source or drain of transistor 216, the other of which is the source of transistor 218. It is connected to one side of the drain and to the other side of the source or drain of transistor 218. It is connected to wiring 226.

[0046] Furthermore, transistors 212, 214, 216, and 218 have gates and sources, respectively. This is a transistor with a drain connected, that is, a diode-connected transistor. ru.

[0047] Note that wiring 224 is connected to wiring to which a high power supply potential VDD is supplied, and wiring 226 is low Wiring 208 is connected to the wiring to which the power supply potential VSS is supplied, and the wiring to which the signal potential SIG is supplied. It is connected to the wiring.

[0048] Furthermore, in Figure 35(A), transistors 212 and 214 Represented as group 220, transistors 216 and 218 make up transistor group 22 Represented as 2. Note that in Figure 35(A), transistor group 220 and transistor group While 222 provided examples of configurations with two transistors each, it is not limited to these. The transistor may consist of one or three or more transistors.

[0049] In the protection circuit 206 shown in Figure 35(A), the signal potential SIG is applied to the wiring 208. The current is, if certain conditions are met, transistor group 220 or transistor group 22 The current flows through 2 to the high power supply potential VDD or the low power supply potential VSS. Note that in Figure 35(A) In this diagram, the currents flowing through the high power supply potential VDD and the low power supply potential VSS are shown by solid arrows. The electron flows at the source potential VDD and the low power supply potential VSS are indicated by dashed arrows.

[0050] Here, using Figure 35(B), the flow to transistor group 220 and transistor group 222 is shown. We will explain electric current and electron flow.

[0051] The waveform shown in Figure 35(B) schematically represents the signal potential SIG applied to wiring 208. Yes. The signal potential SIG is such that ripple occurs during the rising and falling edges of the signal. The ripple can consist of two parts: a ripple on the high power supply potential side and a ripple on the low power supply potential side. In Figure 35(B), the ripple potential on the high power supply potential side is represented as HVDD, and the low power supply The ripple potential on the source potential side is represented as HVSS. The rising edge of the signal potential SIG If ripple occurs during the process, that is, if the signal potential SIG exceeds the high power supply potential VDD, When the potential is present, current flows through the transistor group 220. At this time, the current is supplied from the high power supply potential VDD side. An electron current flows on line 208. Also, a ripple occurs when the signal potential SIG falls. In that case, that is, when the signal potential SIG is at a potential lower than the low power supply potential VSS, the transistor Current flows through group 222. At this time, electron current flows from the low power supply potential VSS side to the wiring 208 side. It can be done.

[0052] In this way, by providing the protection circuit 206, it becomes possible to dissipate overcurrent. .

[0053] Furthermore, the protection circuits 106 and 206 are formed during the manufacturing process of the transistors in the display device. Therefore, during the transistor fabrication process, the protection circuits 106 and 206 will function as follows: It cannot fully demonstrate its capabilities. That is, during the transistor manufacturing process, the transistor The transistor, or the wiring connected to it, is resistant to overcurrents caused by ESD, etc. But that's not enough.

[0054] Overcurrents generated during the transistor manufacturing process can cause large potential differences between different wiring components. This is likely to occur in the case of the gate electrode or gate that make up the transistor. Wiring formed in the same process as the electrodes, and source electrode and drain electrode or source electrode and When the potential difference between the drain electrode and the wiring formed in the same process becomes large, the gate electrode also The gate electrode is formed in the same process as the wiring, and the source electrode and drain electrode or saw Electrostatic discharge can occur between the drain electrode and the wiring formed in the same process. In particular, the wiring formed in the same process as the gate electrode, and the source electrode and drain electrode are the same. In areas where wiring formed during the process intersects or is adjacent to other areas, electrostatic discharge (ESD) occurs. There is a high probability that this will happen.

[0055] Therefore, in one embodiment of the present invention, during the transistor manufacturing process, a transistor or To prevent electrostatic discharge (ESD) damage to the wiring connected to the transistor, etc. It forms an area where electrostatic discharge is acceptable (hereinafter referred to as the electrostatic discharge induction area) and occurs during the transistor fabrication process. By designing the structure to release any overcurrent into the electrostatic discharge induction region, reliability is high and manufacturing yield is reduced. It can provide a highly accurate display device.

[0056] Here, as an example of the display device shown in Figure 1(A), Figures 2(A), (B), and (C) show The specific configuration will be shown.

[0057] The display devices shown in Figures 2(A), (B), and (C) are the pixel units 1 of the display device shown in Figure 1(A). This shows an example of a top view of 02 and the drive circuit section 104. Furthermore, in this embodiment, Figures 2(A) and 2(B) show the configuration of a display device using liquid crystal elements (also called a liquid crystal display device). The explanation will be given using (C).

[0058] Figure 2(A) is a top view of a part of the drive circuit section 104, and Figure 2(B) is a top view of the drive circuit section 104 Figure 2(A) shows a different top view of a part of the pixel section 102, and Figure 2(C) shows a top view of the pixel section 102. These are shown. Note that in Figures 2(A), (B), and (C), the complexity of the drawings is avoided. Therefore, some components, such as the gate insulating layer, are omitted from the illustration.

[0059] In Figure 2(A), a conductive layer 304a functions as a gate electrode, and a gate insulating layer (Figure (Not shown in 2(A)) and a semiconductor layer 308a in which a channel region is formed, and a source electrode And conductive layers 310a and 310b that function as drain electrodes, and the transistor 13 It constitutes 1_3. The semiconductor layer 308a is provided on the gate insulating layer. Also, the gate electric Conductive layer 304b (first wiring and) formed in the same process as conductive layer 304a which functions as a pole (Also known as) the conductive layers 310a and 310b that function as source and drain electrodes. A conductive layer 310c (also called the fourth wiring) formed in one process, and a conductive layer 304b and conductive A translucent conductive layer 316a (also called the seventh wiring) is provided to connect layer 310c. The light-transmitting conductive layer 316a is connected to the conductive layer 304 at the openings 372a and 374a. It is connected to b and connected to the conductive layer 310c at the opening 374b.

[0060] In Figure 2(B), the conductive layer 304a, which functions as the gate electrode, is formed in the same process. The conductive layer 304c (also called the second wiring) and the gate insulating layer (not shown in Figure 2(B)). And, in the same process as the conductive layers 310a and 310b that function as source and drain electrodes The formed conductive layer 310d (also called the fifth wiring) and the light-transmitting conductive layer 316a The conductive layer 316b formed in the same process constitutes the electrostatic discharge induction region 360. The conductive layer 304c and the conductive layer 310d are connected at the openings 374c and 374d, and the conductive layer 316 The connection is made via b. Note that the second wiring is the conductive layer 304c and the fifth wiring is the conductive layer The region where layer 310d intersects is defined as the first region 380. The first region 380 is the conductive layer 30 An insulating layer, which functions as a gate insulating layer, is provided between 4c and the conductive layer 310d.

[0061] Furthermore, in Figure 2(B), the region adjacent to the electrostatic discharge induction region 360 described above is... Conductive layer 304d (third) formed in the same process as conductive layer 304a which functions as a electrode (Also called wiring) and conductive layers 310a, 310 that function as source and drain electrodes. As a region where conductive layer 310e (also called the sixth wiring) formed in the same process as b intersects A second region 382 is provided. The second region 382 consists of a conductive layer 304d and a conductive layer 3 Between 10e and the semiconductor layer 308b is a gate insulating layer (not shown in Figure 2(B)) and a semiconductor layer 308b. To do so, by forming a semiconductor layer 308b in the second region 382, ​​the conductive layer 304d and The distance between conductive layers 310e can be increased, so conductive layer 304d and conductive layer 310e Parasitic capacitance occurring between the conductive layer 304d and the conductive layer 310e can be reduced. As the distance increases, a large potential difference is generated between the conductive layer 304d and the conductive layer 310e. In such a case, the conductive layer 304d and the conductive layer 310e are prevented from short-circuiting due to electrostatic discharge. It is possible.

[0062] Thus, the distance between the conductive layers in the first region 380 and the second region 382 is different. Region 382 is further away from the first region 380 because the semiconductor layer 308b is formed there. long.

[0063] Furthermore, in Figure 2(C), the conductive layer 304e, which functions as a scan line, is approximately perpendicular to the signal line. It is provided extending in the direction (left and right in the diagram). Conductive layer 31 that functions as a signal line 0e is provided extending in a direction approximately perpendicular to the scan line (up and down in the figure). Capacitance line and The conductive layer 310g, which functions as a conductive layer, is provided extending in a direction parallel to the signal line. The conductive layer 304e, which functions as a probe, is the gate driver 104a (see Figure 1(A)). It is electrically connected to the conductive layer 310e which functions as a signal line and functions as a capacitance line. The conductive layer 310g is electrically connected to the source driver 104b (see Figure 1(A)). It is being done.

[0064] Furthermore, in Figure 2(C), transistor 131_1 is where the scan line and signal line intersect. It is located in the region. Transistor 131_1 has a conductive layer 3 that functions as a gate electrode. 04e, gate insulating layer (not shown in Figure 2(C)), channel formed on the gate insulating layer A semiconductor layer 308c in which a drain region is formed, and conductive materials that function as source and drain electrodes. The transistor is formed by layers 310e and 310f. The conductive layer 304e is used for scanning lines. It also functions as the gate voltage of transistor 131_1, and the region superimposed with semiconductor layer 308c is the gate voltage of transistor 131_1. It functions as a pole. In addition, the conductive layer 310e also functions as a signal line, and the semiconductor layer 308c The region that overlaps with it functions as the source or drain electrode of transistor 131_1. ru.

[0065] Furthermore, in Figure 2(C), the scan lines are at the edges of the semiconductor layer 308c in the top surface shape. It is located outside the main part. Therefore, the scan lines block light from light sources such as backlights. It functions as a film. As a result, light is irradiated onto the semiconductor layer 308c contained in the transistor. Furthermore, it is possible to suppress fluctuations in the electrical characteristics of the transistor.

[0066] Furthermore, in Figure 2(C), the conductive layer 310f is connected to the pixel electrode at the aperture 374e. It is electrically connected to a light-transmitting conductive layer 316c that functions as such.

[0067] Furthermore, in Figure 2(C), the conductive material that functions as a capacitance line in the capacitance element 133_1 Layer 310g and semiconductor layer 308d are in contact. Also, the capacitive element 133_1 is a gate A light-transmitting semiconductor layer 308d formed on an insulating layer, and a light-transmitting semiconductor layer that functions as a pixel electrode. A photosensitive conductive layer 316c and a hydrogen-containing insulating layer provided on the transistor 131_1. It is composed of a dielectric film formed by a film. In other words, the capacitive element 133_1 has light transmittance To possess.

[0068] As the capacitive element 133_1 is light-transmitting, the capacitive element 13 3_1 can be formed on a large scale (large area). Therefore, while increasing the opening ratio, It is possible to set the capacity to 55% or more, preferably 60% or more, and the charge capacity An enlarged display device can be obtained. For example, a display device with high resolution, such as a liquid crystal display. In a display device, the pixel area becomes smaller, and the area of ​​the capacitive element also becomes smaller. Therefore, In high-resolution display devices, the charge capacitance stored in capacitive elements decreases. However, However, since the capacitive element 133_1 shown in this embodiment is light-transmitting, the capacitive element is used as a pixel By providing it in this configuration, it is possible to increase the aperture ratio while obtaining sufficient charge capacitance in each pixel. Typically, high resolution refers to a pixel density of 200 ppi or more, and even 300 ppi or more. It can be suitably used in a display device.

[0069] Furthermore, the pixel portion 102 shown in Figure 2(C) is parallel to the conductive layer 310e, which functions as a signal line. The shape is such that the sides parallel to the conductive layer 304e, which functions as a scan line, are longer than the sides that are parallel to the conductive layer 304e. Furthermore, the conductive layer 310g, which functions as a capacitance line, and the conductive layer 310e, which functions as a signal line It is provided extending in a parallel direction. As a result, the conductive layer 310g occupies the pixel portion 102. Since the area can be reduced, the aperture ratio can be increased. Also, the capacitance line and The conductive layer 310g functions as a directly transparent conductive layer without using connecting electrodes. Because it is in contact with the semiconductor layer 308d, the aperture ratio can be further increased. In this configuration, the side parallel to the conductive layer 304e is compared to the side parallel to the conductive layer 310e. While I have described the long shape, it is not limited to this; for example, the side parallel to the conductive layer 310e In comparison, the side parallel to the conductive layer 304e may be shorter. In this case, it becomes possible to reduce the area of ​​the conductive layer 304e in the pixel, thereby increasing the aperture ratio. It is possible.

[0070] Furthermore, one aspect of the present invention allows for an increase in the aperture ratio even in high-resolution display devices. Therefore, it is possible to efficiently utilize the light from light sources such as backlights, and the power consumption of the display device is reduced. The force can be reduced.

[0071] Next, regarding the cross-sectional structure of the display device shown in Figures 2(A), (B), and (C), we will use Figure 3 to explain it. Give an explanation.

[0072] Note that Figure 3(A) is a cross-sectional view corresponding to the cross-section of the dashed line X1-Y1 shown in Figure 2(A). Figure 3(B) shows the cross-section of the dashed lines X2-Y2 and X3-Y3 shown in Figure 2(B), and The corresponding cross-sectional view is shown, and Figure 3(C) shows the cross-section of the dashed line X4-Y4 shown in Figure 2(C) The corresponding cross-sectional view is shown.

[0073] The display device shown in Figure 3 has a liquid crystal element 322 between a pair of substrates (substrate 302 and substrate 342). It is being held in place (see Figure 3(C)).

[0074] The liquid crystal element 322 consists of a conductive layer 316c on top of the substrate 302 and a layer that controls the orientation (hereinafter It has an alignment film (318, 352), a liquid crystal layer 320, and a conductive layer 350. The conductive layer 316c functions as one electrode of the liquid crystal element 322, and the conductive layer 350 is liquid crystal It functions as the other electrode of element 322. Also, in Figure 3, the liquid crystal element 322 is vertically charged. We will now explain the case of a field-type liquid crystal element.

[0075] The drive circuit section 104 shown in Figure 3(A) consists of a substrate 302 and a conductive material formed on the substrate 302. Layers 304a and 304b, substrate 302, and insulating layers formed on conductive layers 304a and 304b An edge layer 305, an insulating layer 306 formed on the insulating layer 305, and formed on the insulating layer 306 , a semiconductor layer 308a formed in a position overlapping with the conductive layer 304a, an insulating layer 306, and Conductive layers 310a and 310b formed on semiconductor layer 308a, and insulating layer 306 The conductive layer 310c, the semiconductor layer 308a, and the conductive layers 310a, 310b, and 310c are formed. An insulating layer 312 formed to cover, an insulating layer 314 formed on the insulating layer 312, and It has a conductive layer 316a formed on the edge layer 314.

[0076] In addition, in the drive circuit section 104 shown in Figure 3(A), the conductive layer 316a is the conductive layer 304 b has the function of wiring connecting conductive layer 310c. Conductive layer 304b is an insulating layer Through the openings formed in 305, 306, 312, and 314, the conductive layer 310c provides insulation. The conductive layer 316a connects through openings formed in layers 312 and 314. In Figure 3(A), when the conductive layer 304b and the conductive layer 316a are connected, the insulating layer 30 After creating openings in 6 and 312, the insulating layer 314 and the insulating layer 305 are opened together. This makes it easier to open the insulating layers 305, 306, 312, and 314 all at once. The number of times this is done increases. As a result, the depth of each opening (the amount of etching in the insulating layer) decreases. Therefore, etching becomes easier. However, one aspect of the present invention is not limited thereto. As shown in Figure 3(B) at the connection point between conductive layer 304c and conductive layer 316b, insulating layer 305 It is also possible to open 306, 312, and 314 all at once. This allows for a reduction in the area of ​​the opening.

[0077] The drive circuit section 104 shown in Figure 3(B) consists of a substrate 302 and a conductive material formed on the substrate 302. Layers 304c and 304d, substrate 302, and insulating layers formed on conductive layers 304c and 304d An edge layer 305, an insulating layer 306 formed on the insulating layer 305, and formed on the insulating layer 306 A semiconductor layer 308b is formed in a position overlapping with the conductive layer 304d, and a shape is formed on the insulating layer 306. The conductive layer 310d formed, the conductive layer 310e formed on the semiconductor layer 308b, and the insulating layer 306, and an insulating layer 312 formed to cover conductive layers 310d, 310e, and insulating layer It has an insulating layer 314 formed on 312. Furthermore, a conductive layer 3 16b is formed.

[0078] In addition, in the drive circuit section 104 shown in Figure 3(B), the conductive layer 316b is the conductive layer 304 c has the function of wiring connecting the conductive layer 310d. The conductive layer 316b is an insulating layer Openings formed in 305, 306, 312, and 314, and formed in insulating layers 312 and 314 It is connected to the conductive layer 310d through the opening. Note that in Figure 3(B), conductive layer 304 When c and conductive layer 316b are connected, insulating layers 305, 306, 312, and 314 are connected together. It is opened in this way. This makes it possible to reduce the area of ​​the opening region. However, this One aspect of the invention is not limited thereto, and the contact between the conductive layer 304b and the conductive layer 316a in Figure 3(A) Similar to the previous section, after providing openings in the insulating layers 306 and 312, insulating layer 314 and insulating layer 30 It is also possible to configure it so that 5 and are opened at once. This allows insulating layers 305, 306, 312, The number of times the openings are made increases compared to opening all 314s at once. As a result, one opening for each opening Because the etching depth (amount of etching in the insulating layer) is reduced, the etching process becomes easier.

[0079] Furthermore, an electrostatic discharge induction region 360 is formed in the drive circuit section 104 shown in Figure 3(B). The electrostatic discharge induction region 360 consists of a conductive layer 304c, insulating layers 305 and 306, and a conductive layer It is composed of 310d, insulating layers 312 and 314, and conductive layer 316b. The breakdown induction region 360 may be configured without insulating layers 305 and 306.

[0080] The conductive layer 304c of the electrostatic discharge induction region 360 is partially as shown in the top view of Figure 2(B). The teeth are formed in a comb-like shape. In addition, the conductive layer 304c is as shown in the cross-sectional view in Figure 3(B). It has multiple protrusions and is formed to facilitate short circuits with the conductive layer 310d.

[0081] The electrostatic discharge induction region 360 is, for example, a region between conductive layer 304c and conductive layer 310d where a large electric current is present. If a positional difference occurs, insulating layers 305 and 310d are formed between the conductive layer 304c and the conductive layer 310d. Destroy 06 and short circuit it.

[0082] Furthermore, the electrostatic discharge induction region 360 is particularly for connecting the conductive layer 316b to another conductive layer. It is effective when forming an opening. For example, when forming the opening by dry etching When formed using a dry etching apparatus, the electric field of plasma etc. generated in the dry etching apparatus The potential difference between conductive layer 304c and conductive layer 310d increases, forming an electrostatic discharge induction region 360. If not done, electrostatic discharge (ESD) damage can occur due to defects in the wiring patterns, etc., of the display device. It occurs in a specific pattern. However, the display device in one aspect of this embodiment induces electrostatic discharge. By forming region 360, overcurrents caused by ESD are induced in electrostatic discharge region 360. They can escape.

[0083] Furthermore, after forming an opening in the insulating layer, conductive layer 304c and conductive layer 310d Because the connection is made by 6b, electrostatic discharge occurs and conductive layer 304c and conductive layer 310d are short-circuited. Even in such cases, there is little to no impact on the display device.

[0084] In this way, by providing the electrostatic discharge induction region 360, the same process as the conductive layer 304c is used. Other conductive layers formed in the same manner (e.g., conductive layers 304a, 304b), or conductive layer 310 Other conductive layers formed in the same process as d (e.g., conductive layers 310a, 310b, 310c) This can prevent it from being destroyed.

[0085] Furthermore, the drive circuit section 104 shown in Figures 3(A) and (B) consists of a substrate 342 and on the substrate 342. A light-shielding layer is formed (hereinafter referred to as the light-shielding layer 344), and a layer is formed on the light-shielding layer 344 It has an insulating layer 348 and a conductive layer 350 formed on the insulating layer 348.

[0086] Furthermore, in the drive circuit section 104 shown in Figures 3(A) and (B), substrate 302 and substrate 342 A liquid crystal layer 320 is sandwiched between them, and alignment films 318 and 352 are in contact with the liquid crystal layer 320. These are formed on substrate 302 and substrate 342, respectively. Note that the liquid crystal layer 320 is a seal A material (not shown) can be used to seal between substrates 302 and 342. The material is preferably configured to come into contact with an inorganic material in order to suppress the intrusion of moisture from the outside. Furthermore, the liquid crystal layer 320 is made thicker (cell gear) using a spacer (not shown). It can maintain (also called a "top").

[0087] The pixel portion 102 shown in Figure 3(C) consists of a substrate 302 and a conductive layer 3 formed on the substrate 302. 04e, substrate 302, insulating layer 305 formed on conductive layer 304e, and insulating layer 30 5 An insulating layer 306 formed on top of and a conductive layer 304e formed on top of the insulating layer 306 and superimposed on the conductive layer 304e A semiconductor layer 308c formed at a certain position, and a semiconductor layer 308d formed on the insulating layer 306. And, conductive layers 310f and 310g formed on the insulating layer 306 and the semiconductor layer 308c, It is formed to cover the semiconductor layer 308c and the conductive layers 310f and 310g, and the semiconductor layer 3 An insulating layer 312 covering a portion of 08d, and a semiconductor layer 308d formed on the insulating layer 312. An insulating layer 314 formed on top, and a conductive layer 310g formed on the insulating layer 314 and connected to the conductive layer 310g. It has a conductive layer 316c.

[0088] Furthermore, the conductive layer 316c is separated from the conductive layer through openings formed in the insulating layers 312 and 314. It connects to 310g.

[0089] Furthermore, the pixel portion 102 shown in Figure 3(C) consists of a substrate 342 and a shield formed on the substrate 342. The photolayer 344 and the colored layer (hereinafter referred to as the colored layer 346) formed on the substrate 342. ) and an insulating layer 348 formed on the light-shielding layer 344 and the colored layer 346, and on the insulating layer 348 It has a conductive layer 350 formed thereon.

[0090] Furthermore, in the pixel section 102 shown in Figure 3(C), a liquid crystal layer is placed between the substrate 302 and the substrate 342. 320 is sandwiched, and alignment films 318 and 352 are in contact with the liquid crystal layer 320, on the substrate 302, And formed on the substrate 342, respectively.

[0091] For other components, please refer to the detailed instructions on how to manufacture the display device, which will be described later. do.

[0092] As described above, in the display device shown in this embodiment, the drive circuit portion has an electrostatic discharge induction region It has a region. The electrostatic discharge induction region is formed in the same process as the gate electrode and the source The thickness of the insulating film formed between the wiring, which is formed in the same process as the electrodes and drain electrodes, By making it thinner, that is, by shortening the distance between wirings, the insulating film between other wiring patterns is reduced. This can suppress electrostatic discharge. Furthermore, in the electrostatic discharge induction region, the gate electrode and Because the shape of the wiring formed in the same process is comb-shaped, it can prevent overcurrents that may be generated by ESD. It has a structure that makes it easy to flush.

[0093] Thus, one aspect of the present invention is a display device having an electrostatic discharge induction region in the drive circuit section. This makes it possible to provide a novel display device that can improve reliability.

[0094] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0095] (Embodiment 2) In this embodiment, the method for manufacturing the display device described in Figure 3 of Embodiment 1 is shown in Figure 4. Let us explain using Figure 17.

[0096] The display device described in Figure 3 of Embodiment 1 simultaneously operates the drive circuit unit 104 and the pixel unit 102. It can be manufactured. Therefore, in this embodiment, the drive circuit unit 104, the pixel The manufacturing method for each part 102 will be explained. The manufacturing method for the drive circuit part 104 will also be explained. Regarding this, see Figures 4(A), (B), Figures 5(A), (B), Figures 6(A), (B), and Figure Figures 7(A), (B), Figure 8(A), (B), Figure 9(A), (B), Figure 10(A), ( B), Figures 11(A) and (B), Figures 12(A) and (B), Figures 13(A) and (B), Figures 14(A), (B), Figures 15(A), (B), Figures 16(A), (B), and Figure 17( The method for manufacturing the pixel portion 102 is shown in A), (B), and Figures 4(C) and 5(C). ) and Figure 6(C), Figure 7(C), Figure 8(C), Figure 9(C), Figure 10(C), Figure Figure 11(C), Figure 12(C), Figure 13(C), Figure 14(C), Figure 15(C), Figure As shown in Figure 16(C) and Figure 17(C).

[0097] First, prepare the substrate 302. The substrate 302 can be made of aluminosilicate glass, aluminum Glass materials such as minobrosilicate glass and bariumborosilicate glass are used. Mass production is planned. Above, board 302 is 8th generation (2160mm x 2460mm), 9th generation (2400 mm × 2800 mm, or 2450 mm × 3050 mm), 10th generation (2950 mm) It is preferable to use mother glass such as (3400 mm x 3400 mm). The mother glass is processed at a certain temperature. Because the process is expensive and shrinks significantly with long processing times, when mass production is performed using mother glass... The heat treatment in the manufacturing process is preferably 600°C or lower, more preferably 450°C or lower. Furthermore, it is desirable to keep the temperature below 350°C.

[0098] Next, a conductive film is formed on the substrate 302, and the conductive film is processed to a desired region, thereby enabling conductivity Layers 304a, 304b, 304c, 304d, and 304e are formed. Note that conductive layer 304 The formation of a, 304b, 304c, 304d, and 304e is the first patterning in the desired region. A mask is formed using a etchant, and the areas not covered by the mask are etched to create a shape. It is possible.

[0099] The conductive layers 304a, 304b, 304c, 304d, and 304e are made of aluminum. A selection of metallic elements from chromium, copper, tantalum, titanium, molybdenum, and tungsten, This uses an alloy containing the aforementioned metal elements, or an alloy combining the aforementioned metal elements. It can be formed by . Also, conductive layers 304a, 304b, 304c, 304d, 30 4e may be a single-layer structure or a laminated structure of two or more layers. For example, on an aluminum film Two-layer structure with stacked titanium films, two-layer structure with stacked titanium films on titanium nitride film, titanium nitride A two-layer structure in which a tungsten film is laminated on a tantalum film, a tantalum nitride film or a tungsten nitride film. A two-layer structure with a tungsten film laminated on top, a titanium film, and an aluminum film on top of the titanium film. There are also three-layer structures, such as one in which layers are stacked and then a titanium film is formed on top of them. From titanium, tantalum, tungsten, molybdenum, chromium, neodymium, and scandium A film of selected elements, an alloy film combining multiple elements, or a nitride film may be used. For example, the conductive layers 304a, 304b, 304c, 304d, and 304e are spa It can be formed using the tarring method.

[0100] Next, on the substrate 302 and the conductive layers 304a, 304b, 304c, 304d, 304e Insulating layers 305 and 306 are formed on top of this (see Figures 4(A), (B), and (C)).

[0101] As the insulating layer 305, for example, a silicon oxynitride film, a silicon nitride film, an aluminum oxide film, etc. may be used, and it may be provided in a laminated or single-layer form using a PE-CVD apparatus. Also, when the insulating layer 305 has a laminated structure, as the first silicon nitride film, a silicon nitride film with few defects is used, and on the first silicon nitride film, as the second silicon nitride film, it is preferable to provide a silicon nitride film with a small hydrogen emission amount and an ammonia emission amount. As a result, hydrogen and nitrogen contained in the insulating layer 305 can be suppressed from moving or diffusing to the semiconductor layers 308a, 308b, and 308c formed later.

[0102] As the insulating layer 306, a silicon oxide film, a silicon oxynitride film, etc. may be used, and it may be provided in a laminated or single-layer form using a PE-CVD apparatus.

[0103] As the insulating layers 305 and 306, for example, as the insulating layer 305, a 300-nm-thick silicon nitride film is formed, and then, as the insulating layer 306, a 50-nm-thick silicon oxynitride film can be formed. It is preferable that the silicon nitride film and the silicon oxynitride film are formed continuously in a vacuum to suppress the incorporation of impurities. In addition, the insulating layers 305 and 306 in the region overlapping with the conductive layers 304a and 304e can function as the gate insulating layer of the transistor.

[0104] Note that silicon oxynitride is an insulating material in which the nitrogen content is greater than the oxygen content, while silicon oxynitride is an insulating material in which the oxygen content is greater than the nitrogen content.

[0105] ​​​​​​​​​​​​​By using the above configuration as the gate insulating layer, the following effects can be obtained, for example: It is possible. Silicon nitride films have a higher dielectric constant compared to silicon oxide films, and can achieve equivalent static Because a large film thickness is required to obtain capacitance, the gate insulating layer cannot be made physically thicker. Therefore, it suppresses the decrease in the dielectric breakdown voltage of the transistor, and further improves the dielectric breakdown voltage. This can suppress electrostatic discharge (ESD) in transistors.

[0106] Next, a semiconductor layer 307 is formed on the insulating layer 306 (see Figures 5(A), (B), and (C)). ).

[0107] For example, an oxide semiconductor can be used as the semiconductor layer 307. The oxide semiconductors applicable to 7 include at least indium (In), zinc (Zn), and M( In-M- It is preferable to include a layer represented by Zn oxide, or to include both In and Zn. This is preferable. Furthermore, it reduces variations in the electrical characteristics of transistors using the oxide semiconductor. Therefore, it is preferable to include a stabilizer along with them.

[0108] Stabilizers include gallium (Ga), tin (Sn), hafnium (Hf), and Examples include luminium (Al) or zirconium (Zr). Also, other stabilizers... Examples include lanthanides, such as lanthanum (La), cerium (Ce), and praseodymium. Pr), neodymium (Nd), samarium (Sm), europium (Eu), gadolinium (Gd), Terbium (Tb), Dysprosium (Dy), Holmium (Ho), Elvi These include um (Er), thulium (Tm), ytterbium (Yb), lutetium (Lu), etc. ru.

[0109] For example, oxide semiconductors include indium oxide, tin oxide, zinc oxide, and in-Zn oxide. Materials, Sn-Zn oxide, Al-Zn oxide, Zn-Mg oxide, Sn-Mg oxide, In -Mg oxide, In-Ga oxide, In-Ga-Zn oxide, In-Al-Zn oxide, In-Sn-Zn oxide, Sn-Ga-Zn oxide, Al-Ga-Zn oxide, Sn-A l-Zn oxide, In-Hf-Zn oxide, In-La-Zn oxide, In-Ce-Zn Oxides, In-Pr-Zn oxide, In-Nd-Zn oxide, In-Sm-Zn oxide, In-Eu-Zn oxide, In-Gd-Zn oxide, In-Tb-Zn oxide, In-D y-Zn oxide, In-Ho-Zn oxide, In-Er-Zn oxide, In-Tm-Zn Oxides, In-Yb-Zn oxide, In-Lu-Zn ​​oxide, In-Sn-Ga-Zn acid In-Hf-Ga-Zn oxide, In-Al-Ga-Zn oxide, In-Sn-A Using l-Zn oxide, In-Sn-Hf-Zn oxide, and In-Hf-Al-Zn oxide It is possible.

[0110] In this context, In-Ga-Zn oxide refers to an oxide whose main components are In, Ga, and Zn. This refers to oxides, and the ratio of In, Ga, and Zn is not specified. Other metal elements may be present. Also, in this specification, etc., In-Ga-Zn acid A film composed of these materials is sometimes also called an IGZO film.

[0111] Also, InMO3(ZnO) m Using materials represented as (m>0 and m is an integer) It is also acceptable. Here, M may represent one or more metal elements selected from Ga, Fe, Mn, and Co. In some cases, it may indicate a metal element or multiple n metal elements. Also, a material represented by In2SnO5(ZnO) (n > 0, and n is an

[0112] integer) may be used. Furthermore, the oxide semiconductor film may have a non - single crystal. The non - single crystal may have, for example, CAAC ( C Axis Aligned Crystal), polycrystal, microcrystal, or an amorphous part.

[0113] The oxide semiconductor may have CAAC. An oxide semiconductor having CAAC is referred to as CAAC - OS (C Axis Aligned Crystalline Oxide Semiconductor).

[0114] For CAAC - OS, there are cases where crystal parts can be confirmed in an observation image obtained by a transmission electron microscope (TEM: Transmission Elec tron Microscope). The crystal parts included in CAAC - OS are often sized to fit within a cube with a side length of 100 nm. Also, for CAAC - OS, there are cases where the boundaries between crystal parts cannot be clearly confirmed in an observation image by TEM. Also, for CAAC - OS, there are cases where grain boundaries (also referred to as grain boundaries) cannot be clearly confirmed in an observation image by TEM. Since CAAC - OS does not have distinct grain boundaries, impurities are less likely to segregate. Also, since CAAC - OS does not have distinct grain boundaries, the density of defect levels is less likely to increase. Also, since CAAC - OS does not have distinct grain boundaries, the decrease in electron mobility is small.

[0115] CAAC-OS may have multiple crystalline regions, and in these multiple crystalline regions, the c axis In some cases, the vectors are aligned in a direction parallel to the normal vector of the surface being formed or the surface normal vector. Furthermore, CAAC-OS uses X-ray diffraction (XRD). Using the apparatus, analysis was performed using the out-of-plane method, and the orientation-indicating 2θ was found to be 31 A peak near ° may appear. Also, CAAC-OS, in its electron diffraction pattern, Spots (bright spots) may be observed. In particular, when the beam diameter is 10 nmφ or less, Alternatively, electron diffraction patterns obtained using electron beams with a diameter of 5 nm or less are called ultra-micro electron diffraction patterns. It is called a line. In addition, CAAC-OS has the a-axis and b-axis directions between different crystal regions. The alignment may not be consistent. CAAC-OS, for example, is c-axis oriented and a-axis or / o The b-axis may not be aligned macroscopically.

[0116] Figure 30(A) shows an example of the micro-electron diffraction pattern of a sample containing CAAC-OS. Here, the sample is cut perpendicular to the surface on which CAAC-OS is formed, and the thickness is 40 nm. The sample is thinned to the extent of [a certain degree]. Here, an electron beam with a beam diameter of 1 nmφ is used on the sample. The beam is incident from a direction perpendicular to the cut surface. As shown in Figure 30(A), the ultra-micro electron beam of CAAC-OS... The folding pattern reveals that spots are observed.

[0117] The crystalline portion contained in CAAC-OS has a c-axis that is the normal vector to the surface on which CAAC-OS is formed. Alternatively, they are aligned so as to be parallel to the surface normal vector, and from a direction perpendicular to the ab plane. When viewed from a direction perpendicular to the c-axis, the metal atoms are arranged in a triangular or hexagonal shape. The structure is layered, or metal atoms and oxygen atoms are arranged in layers. The orientations of the a-axis and b-axis may be different. In this specification, "perpendicular" is not the only term used. In this case, the range of 80° to 100°, preferably 85° to 95°, is also included. This shall apply. Furthermore, when simply stating "parallel," the angle should be between -10° and 10°, preferably -5°. This also includes the range of 5° or less.

[0118] The c-axis of the crystalline portion contained in CAAC-OS is the normal vector of the surface formed in CAAC-OS. Alternatively, they align in a direction parallel to the surface normal vector, thus the shape of CAAC-OS ( Depending on the cross-sectional shape of the surface to be formed or the cross-sectional shape of the surface, they may face in different directions. Furthermore, the crystalline portion is formed when the film is deposited, or when crystallization treatment such as heat treatment is performed after film deposition. It is formed at times. Therefore, the c-axis of the crystalline portion is formed when CAAC-OS is formed. They align so as to be parallel to the normal vector of the face or surface.

[0119] CAAC-OS can sometimes be formed by reducing the concentration of impurities. Therefore, impurities are other than the main components of oxide semiconductors such as hydrogen, carbon, silicon, and transition metal elements. These are elements. In particular, elements such as silicon are more acidic than the metallic elements that make up oxide semiconductors. It has a strong bonding force with the element. Therefore, when the element removes oxygen from the oxide semiconductor, the oxide semiconductor It can disrupt the atomic arrangement of the body and reduce its crystallinity. Also, heavy metals such as iron and nickel... Argon, carbon dioxide, etc., have large atomic radii (or molecular radii), so oxide semiconductors It can disrupt the atomic arrangement of the material and reduce the crystallinity of oxide semiconductors. Therefore, CAAC -OS is an oxide semiconductor with a low impurity concentration. This can be a source of carrier activity.

[0120] Furthermore, in CAAC-OS, the distribution of the crystalline portion does not need to be uniform. For example, CAA In the formation process of C-OS, when crystal growth is performed from the surface side of the oxide semiconductor, the surface to be formed The proportion of the crystalline portion may be higher near the surface compared to the vicinity of the crystalline portion. Also, CAAC -When impurities are mixed into the OS, the crystallinity of the crystalline region decreases in the region where the impurities are mixed. It can happen.

[0121] Furthermore, CAAC-OS can be formed by reducing the defect level density. In semiconductor materials, oxygen vacancies are defect levels. Oxygen vacancies can also become trap levels. It can become a carrier source by capturing hydrogen, forming CAAC-OS. To achieve this, it is important to prevent oxygen vacancies from forming in the oxide semiconductor. Therefore, CA AC-OS is an oxide semiconductor with a low defect level density. Alternatively, CAAC-OS is an acid It is an oxide semiconductor with few elementary defects.

[0122] High-purity intrinsic or high This is essentially called high-purity intrinsic. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic are Therefore, because there are fewer carrier sources, it may be possible to lower the carrier density. Therefore, in a transistor using the said oxide semiconductor in the channel formation region, the threshold voltage is minus In some cases, the electrical properties that result in eggplants (also called normally-on) are rarely observed. Oxide semiconductors that are high-purity intrinsic or substantially high-purity intrinsic have a low defect level density. Furthermore, the trap level density may also be low. Therefore, the oxide semiconductor in question is used as a channel formation area. The transistors used in this region exhibit minimal fluctuations in electrical characteristics, resulting in highly reliable transistors. In some cases, this may occur. Furthermore, the charge trapped in the trap levels of an oxide semiconductor requires time to disappear. It can remain stationary for a long time, behaving almost like a fixed charge. Therefore, trapping is necessary. Transistors using oxide semiconductors with high ion density in the channel formation region have questionable electrical characteristics. This may be the case.

[0123] Furthermore, a transistor using CAAC-OS that is of high purity or substantially high purity Ta exhibits minimal fluctuations in electrical properties due to irradiation with visible or ultraviolet light.

[0124] CAAC-OS can be formed, for example, by a sputtering method using a DC power supply. It is possible.

[0125] The oxide semiconductor may, for example, have polycrystalline properties. This is called a polycrystalline oxide semiconductor. A polycrystalline oxide semiconductor contains multiple crystal grains.

[0126] In some cases, the crystal grains of polycrystalline oxide semiconductors can be identified by TEM observation. Yes, there are crystal grains contained in polycrystalline oxide semiconductors, for example, 2 nm in TEM observation images. Particle sizes of 300 nm or less, 3 nm to 100 nm, or 5 nm to 50 nm. This is often the case. Also, in polycrystalline oxide semiconductors, the crystal grains and crystal grains are visible in the TEM observation image. In some cases, the boundary can be confirmed. Also, polycrystalline oxide semiconductors can be observed using TEM. In some cases, grain boundaries can be identified.

[0127] Polycrystalline oxide semiconductors have multiple crystal grains, and the orientation of these multiple crystal grains differs. In some cases, polycrystalline oxide semiconductors are subjected to out-of-p When performing analysis using the lane method, one or more peaks may appear. For example, In crystalline IGZO films, the orientation is indicated by a peak around 31° at 2θ, or by multiple orientations. Multiple peaks may appear. Also, polycrystalline oxide semiconductors exhibit electron diffraction patterns. And sometimes spots are observed.

[0128] Polycrystalline oxide semiconductors can sometimes exhibit high electron mobility due to their high crystallinity. Therefore, transistors using polycrystalline oxide semiconductors in the channel formation region have high field efficiency. It has fruit mobility. However, polycrystalline oxide semiconductors may have impurities segregated at grain boundaries. Furthermore, grain boundaries in polycrystalline oxide semiconductors become defect levels. Because it can become a carrier source and trap level, polycrystalline oxide semiconductors are used for channel formation. The transistor used in the region is a transistor that uses CAAC-OS in the channel formation region. Compared to other transistors, this type can exhibit greater fluctuations in electrical characteristics and may result in less reliable transistors.

[0129] Polycrystalline oxide semiconductors are formed by high-temperature heat treatment or laser light treatment. It is possible.

[0130] The oxide semiconductor may, for example, have microcrystals. This is called a microcrystalline oxide semiconductor.

[0131] Microcrystalline oxide semiconductors can be clearly observed using TEM. In some cases, this may not be the case. The crystalline portion contained in microcrystalline oxide semiconductors is, for example, 1 nm to 100 nm. They are often less than m in size, or between 1 nm and 10 nm in size. In particular, they are between 1 nm and 1 Microcrystals smaller than 0 nm are called nanocrystals (nc). The oxide semiconductor used is called nc-OS (nanocrystalline oxide se It is called (miconductor). Also, nc-OS is a crystal in the TEM observation image. In some cases, the boundary between the part and the crystalline part cannot be clearly identified. Also, nc-OS is obtained by TEM In the observed image, there are no clear grain boundaries, so impurities are less likely to segregate. -OS does not have clear grain boundaries, so the defect level density is less likely to be high. Also, n c-OS lacks distinct grain boundaries, resulting in a smaller decrease in electron mobility.

[0132] nc-OS has atomic distribution in a minute region (for example, a region between 1 nm and 10 nm). The rows may have periodicity. Also, nc-OS has regularity between the crystalline parts. Therefore, macroscopically, periodicity is not observed in the atomic arrangement, or long-range order is not observed. In some cases, nc-OS can be distinguished from amorphous oxide semiconductors depending on the analytical method. In some cases, it may not be included. nc-OS uses an XRD instrument and has a beam diameter larger than the crystal portion. When X-ray analysis was performed using the out-of-plane method, a peak indicating orientation was detected. In some cases, this is not the case. Also, nc-OS uses a beam diameter larger than the crystal portion (for example, 20 nm). In electron diffraction patterns using electron beams of φ or greater, or 50 nmφ or greater, the halo pattern In some cases, a ring may be observed. Also, nc-OS has rings that are the same size as or smaller than the crystalline part. Ultra-micro electron beam lithography using electron beams with a beam diameter (e.g., 10 nmφ or less, or 5 nmφ or less) In the folding pattern, spots may be observed. Also, ultra-low electron diffraction of nc-OS. The pattern may sometimes show areas of high brightness forming a circular shape. Also, nc-OS In the case of extremely small electron diffraction patterns, multiple spots may be observed within the region in question.

[0133] Figure 30(B) shows an example of the micro-electron diffraction pattern of a sample containing nc-OS. Here, the sample is cut perpendicular to the surface on which nc-OS is formed, and the thickness is approximately 40 nm. The sample is thinned in this manner. In addition, here, an electron beam with a beam diameter of 1 nmφ is applied to the cross-section of the sample. The electron beam is incident from a perpendicular direction. From Figure 30(B), the micro-electron diffraction pattern of nc-OS is A region of high brightness was observed in a circular pattern, and multiple spots were observed within that region. It can be seen that...

[0134] Because nc-OS may have periodicity in the atomic arrangement in minute regions, it is amorphous. The defect level density is lower than that of oxide semiconductors. However, nc-OS has a crystalline structure between the crystalline regions. Because there is no regularity between them, the defect level density is higher compared to CAAC-OS.

[0135] Therefore, nc-OS may have a higher carrier density compared to CAAC-OS. Oxide semiconductors with high carrier density may have high electron mobility. Therefore, nc - Transistors using OS in the channel formation region may have high field-effect mobility. Yes. Also, nc-OS has a higher defect level density compared to CAAC-OS, so traps The pleth level density may also increase. Therefore, when nc-OS is used in the channel formation region, Compared to transistors using CAAC-OS in the channel formation region, this transistor exhibits different electrical characteristics. The transistor may exhibit large fluctuations in performance and be unreliable. However, nc-OS Because it can be formed even if it contains a relatively large amount of impurities, it is more effective than CAAC-OS. It becomes easier to form and may be suitable for use depending on the application. For example, AC nc-OS may be formed by a film deposition method such as sputtering using a power supply. The sputtering method using a C power supply makes it possible to deposit films with high uniformity on large substrates. Therefore, semiconductor devices having transistors that use nc-OS in the channel formation region have high productivity. It can be manufactured easily.

[0136] Oxide semiconductors may have amorphous regions, for example. This material is called an amorphous oxide semiconductor. Amorphous oxide semiconductors are, for example, materials in which the atomic arrangement is disordered. It does not have a crystalline portion. Alternatively, amorphous oxide semiconductors are amorphous, such as quartz. It has a state, and no regularity is observed in the atomic arrangement.

[0137] Furthermore, amorphous oxide semiconductor films exhibit, for example, halo patterns in electron diffraction patterns. In some cases, this may occur. Also, amorphous oxide semiconductor films can be analyzed, for example, by micro-electron diffraction patterns. In some cases, a spot may not be observed, and a halo pattern may be observed instead.

[0138] Amorphous oxide semiconductors can be formed by, for example, incorporating high concentrations of impurities such as hydrogen. In some cases, this can be achieved. Therefore, amorphous oxide semiconductors can, for example, have high impurity levels. It is an oxide semiconductor containing a certain concentration.

[0139] When oxide semiconductors contain high concentrations of impurities, defects such as oxygen vacancies can form in the oxide semiconductor. Defect levels may form. Therefore, amorphous oxide semiconductors with high impurity concentrations have a dense defect level structure. The degree is high. Also, amorphous oxide semiconductors have low crystallinity, so CAAC-OS and nc-OS Compared to that, the defect level density is higher.

[0140] Therefore, amorphous oxide semiconductors have an even higher carrier density compared to nc-OS. In some cases, transistors using amorphous oxide semiconductors in the channel formation region are In some cases, the electrical properties may be those of a normally-on atom. Therefore, the electrical properties of a normally-on atom are required. Amorphous oxide semiconductors can be suitably used in transistors. Due to the high defect level density, the trap level density may also be high. Therefore, amorphous oxidation Transistors that use solid semiconductors in the channel formation region include CAAC-OS and nc-OS. Compared to transistors used in the channel formation region, the electrical characteristics fluctuate significantly, resulting in lower reliability. It can sometimes form a transistor. However, amorphous oxide semiconductors contain relatively many impurities. Because it can be formed even by film deposition methods that can cause bleeding, the formation process becomes easier, and it can be used in a variety of applications. Depending on the circumstances, it may be suitable for use. For example, spin coating method, sol-gel method , immersion method, spray method, screen printing method, contact printing method, inkjet printing Amorphous oxide semiconductors are formed by film deposition methods such as the CVD method, roll coating method, and mist CVD method. This may also be done. Therefore, a transistor using amorphous oxide semiconductor in the channel formation region is available. Semiconductor devices can be manufactured with high productivity.

[0141] Furthermore, oxide semiconductors include CAAC-OS, polycrystalline oxide semiconductors, and microcrystalline oxide semiconductors. The mixed film may have two or more amorphous oxide semiconductors. For example, the mixed film may be amorphous Area of ​​crystalline oxide semiconductors, area of ​​microcrystalline oxide semiconductors, area of ​​polycrystalline oxide semiconductors, CAA The C-OS region may have two or more of the following regions. Furthermore, the mixed film may, for example... The regions of amorphous oxide semiconductors, microcrystalline oxide semiconductors, and polycrystalline oxide semiconductors. It may have a layered structure of two or more of the following regions: the CAAC-OS region, etc.

[0142] The oxide semiconductor may have a single crystal. It is called a crystalline oxide semiconductor.

[0143] Single-crystal oxide semiconductors have low impurity concentrations and low defect level density (few oxygen vacancies). Therefore, the carrier density can be lowered. Consequently, single-crystal oxide semiconductors can be channel-shaped. Transistors used in the region often exhibit normally-on electrical characteristics. Furthermore, single-crystal oxide semiconductors have a low defect level density, and therefore also a low trap level density. This can happen. Therefore, transistors that use single-crystal oxide semiconductors in the channel formation region are This can result in transistors with smaller variations in electrical characteristics and thus greater reliability.

[0144] Oxide semiconductors, for example, have high density when they have few defects. Also, oxide semiconductors are, for example... For example, higher crystallinity results in higher density. Also, oxide semiconductors contain impurities such as hydrogen. When the concentration of a substance is low, the density increases. For example, single-crystal oxide semiconductors are denser than CAAC-OS. The density can be high. Also, for example, CAAC-OS is denser than microcrystalline oxide semiconductors. The degree can be high. Also, for example, polycrystalline oxide semiconductors are more than microcrystalline oxide semiconductors. The density can be high. Also, for example, microcrystalline oxide semiconductors are denser than amorphous oxide semiconductors. The density can also be high.

[0145] Next, the semiconductor layer 307 is processed into a desired region, thereby creating island-shaped semiconductor layers 308a, 30 Form 8b, 308c, and 308d. Note that semiconductor layers 308a, 308b, and 308c are formed. The formation of 308d involves forming a mask in the desired region by a second patterning, and the mask It can be formed by etching the areas not covered by the coating. Therefore, we use dry etching, wet etching, or a combination of both. It can be used (see Figures 6(A), (B), (C)). Thus, island-shaped semiconductor layers 308d is formed by processing the semiconductor layer 307 into a desired region, This eliminates the need for additional steps, resulting in a reduction in the total number of steps, lowering costs, and allowing for a smoother process. You can increase your puts.

[0146] Next, it is preferable to perform a first heat treatment. The first heat treatment is performed at a temperature of 250°C or higher and 650°C or higher. At a temperature of 300°C or higher, preferably 300°C to 500°C, in an inert gas atmosphere, oxidizing gas The procedure should be carried out in an atmosphere containing 10 ppm or more of [the substance], or under reduced pressure. Also, the atmosphere of the first heat treatment... The atmosphere is heated in an inert gas atmosphere, and then an oxidizing gas is added to replenish the oxygen that has been removed. The procedure may be carried out in an atmosphere containing 10 ppm or more. The first heat treatment is performed on the semiconductor layer 308a The crystallinity of the oxide semiconductor used in 308b, 308c, and 308d is improved, and the insulating layer 3 Hydrogen and water are produced from 05, 306, and semiconductor layers 308a, 308b, 308c, and 308d. The impurities can be removed. Note that the first heating is performed before processing the oxide semiconductor into island shapes. The process may be performed.

[0147] In order to impart stable electrical characteristics to a transistor having an oxide semiconductor as a channel it is effective to reduce the impurity concentration in the oxide semiconductor and make the oxide semiconductor intrinsic or substantially intrinsic. Here, substantially intrinsic means that the carrier density of the oxide semiconductor is less than 1 ×10 ×10 17 / cm 3 , preferably less than 1×10 15 / cm 3 , and more preferably less than 1×10 . Even more preferably, it means less than 1×10 13 / cm 3 .

[0148] Also, in an oxide semiconductor, hydrogen, nitrogen, carbon, silicon, and metal elements other than the main component become impurities. For example, hydrogen and nitrogen form donor levels and increase the carrier density . Also, silicon forms impurity levels in the oxide semiconductor. The impurity levels may become traps and deteriorate the electrical characteristics of the transistor.

[0149] In order to make the oxide semiconductor intrinsic or substantially intrinsic, in the analysis by SIMS, the silicon concentration should be less than 1×10 ×10 19 atoms / cm 3 , preferably less than 5×10 18 at oms / cm 3 , and even more preferably less than 1×10 18 atoms / cm 3 . Also , the hydrogen concentration should be 2×10 20 atoms / cm 3 or less, preferably 5×10 19 ato ms / cm 3 or less, more preferably 1×10 19atoms / cm 3 The following are even more preferable kuha 5×10 18 atoms / cm 3 The following applies. Also, the nitrogen concentration is 5 × 10⁻⁶. 19 at oms / cm 3 Less than 5 × 10 18 atoms / cm 3 The following is more 1 x 10 18 atoms / cm 3 More preferably 5 × 10 17 atoms / cm 3 The following applies:

[0150] Furthermore, if an oxide semiconductor contains crystals, and if silicon or carbon is present in high concentrations, the oxide will be... This can reduce the crystallinity of semiconductors. To avoid reducing the crystallinity of oxide semiconductors... , silicon concentration 1 × 10 19 atoms / cm 3 Less than 5 × 10 18 ato ms / cm 3 Less than 1 × 10 18 atoms / cm 3 You should use "less than". Also, the carbon concentration is 1 × 10⁻⁶. 19 atoms / cm 3 Less than 5 × 10 18 at oms / cm 3 Less than 1 × 10 18 atoms / cm 3 If you set it to less than stomach.

[0151] Furthermore, as mentioned above, a transient using a highly purified oxide semiconductor in the channel formation region The off-current of the transistor is extremely small, and the off-current normalized by the channel width of the transistor is several It becomes possible to reduce the level from yA / μm to several zA / μm.

[0152] Next, conductive This forms layer 309 (see Figures 7(A), (B), and (C)).

[0153] The conductive layer 309 can be made of aluminum, titanium, chromium, nickel, etc. From copper, yttrium, zirconium, molybdenum, silver, tantalum, or tungsten A single elemental metal, or an alloy primarily composed of such metal, is used as a single-layer or layered structure. For example, a two-layer structure in which a titanium film is laminated on an aluminum film, or a titanium film on a tungsten film. A two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film, a two-layer structure in which a copper film is laminated on a copper-magnesium-aluminum alloy film. A titanium film or titanium nitride film, and aluminum layered on top of the titanium film or titanium nitride film. A three-layer structure is formed by laminating a titanium film or copper film, and then forming a titanium film or titanium nitride film on top of it. Layered structure, molybdenum film or molybdenum nitride film, and the molybdenum film or molybdenum nitride An aluminum film or copper film is laminated on top of the film, and then a molybdenum film or There are three-layer structures that form a molybdenum nitride film, etc. Indium oxide, tin oxide, or acid A transparent conductive material containing zinc oxide may be used. Furthermore, the conductive layer 309 may be, for example, a spa It can be formed using the tarring method.

[0154] Next, the conductive layer 309 is processed into the desired region, thereby creating conductive layers 310a, 310b, 31 0c, 310d, 310e, 310f, and 310g are formed. Note that conductive layers 310a and 3 The formation of 10b, 310c, 310d, 310e, 310f, and 310g is performed in the desired region. A mask is formed by patterning in step 3, and the areas not covered by the mask are etched. It can be formed by doing so (see Figures 8(A), (B), and (C)).

[0155] In this embodiment, the conductive layers 310a, 310b, 310f, and 310g are semiconductors. Although formed on layers 308a and 308c, between the insulating layer 306 and the semiconductor layers 308a and 308c It may be formed as follows.

[0156] Next, insulating layer 306, semiconductor layers 308a, 308c and conductive layers 310a, 310b, 3 An insulating layer 311 is formed to cover 10c, 310d, 310e, 310f, and 310g. (See Figures 9(A), (B), and (C)).

[0157] The insulating layer 311 is used as semiconductor layers 308a, 308b, 308c, and 308d. To improve the interfacial properties with oxide semiconductors, an inorganic insulating material containing oxygen can be used. Yes, it is possible. Furthermore, the insulating layer 311 can be formed, for example, using the PE-CVD method. can.

[0158] An example of the insulating layer 311 is a silicon oxide film with a thickness of 150 nm to 400 nm. Silicon oxide nitride films, aluminum oxide films, etc. can be used. Therefore, a silicon oxide-nitride film with a thickness of 300 nm is used as the insulating layer 311.

[0159] Next, the insulating layer 311 is processed to form openings 372a and 372b in the desired region. Furthermore, the insulating layer 311 becomes an insulating layer 312 in which openings 372a and 372b are formed. Furthermore, the formation of the insulating layer 312 and the openings 372a and 372b is performed in the desired region. A mask is formed by patterning, and the areas not covered by the mask are etched. This can be achieved by doing so. (See Figures 10(A), (B), and (C)).

[0160] Furthermore, the opening 372a is formed so that the insulating layer 305 is exposed. 2b is formed so that the semiconductor layer 308d is exposed. Formation of openings 372a and 372b For example, a dry etching method can be used. However, the opening 37 The formation method for 2a and 372b is not limited to this, but may include wet etching or A formation method combining dry etching and wet etching methods may also be used. When forming island-shaped semiconductor layers 308d, the semiconductor layer 307 is processed into a desired region. Instead of being formed by semiconductor layer 307, another semiconductor layer (for example, ITO) When forming by processing (etc.), it is also possible to omit the opening 372b. If the island-shaped semiconductor layer 308d and the insulating layer 313 are not brought into contact, an opening is formed. 372b can be omitted. Alternatively, it may be necessary to form an island-shaped semiconductor layer 308d. If there is no such requirement, it is also possible to omit the opening 372b.

[0161] Next, an insulating layer 313 is formed on the insulating layers 305, 312 and the semiconductor layer 308d (Figure 11(A), (B), (C)).

[0162] The insulating layer 313 is protected from external impurities, such as water, alkali metals, alkaline earth metals, etc. However, it is a film formed of a material that prevents diffusion into the oxide semiconductor layer, and furthermore, it contains hydrogen. Therefore, when hydrogen from the insulating layer 313 diffuses into the semiconductor layer 308d, Then hydrogen combines with oxygen, generating electrons, which are carriers. As a result, semiconductor layer 308 d becomes a conductive layer with high conductivity and light transmission.

[0163] In this embodiment, hydrogen is released from the insulating layer 313 in contact with the semiconductor layer 308d. The methods of implementation are illustrated with examples, but are not limited to these. For example, transistor channels A mask is placed over the area where hydrogen will form, and hydrogen is introduced into the area not covered by the mask. For example, hydrogen may be introduced into the semiconductor layer 308d using an ion doping device or the like. It is possible to apply a light-transmitting conductive film, for example, to the semiconductor layer 308d beforehand. ITO or the like may be formed. In that case, a light-transmitting conductive film may be formed at the opening 372 On top of the insulating layer 312 where b is not provided (that is, between the insulating layer 312 and the insulating layer 313) It may be formed.

[0164] An example of the insulating layer 313 is a hydrogen-containing insulating film with a thickness of 150 nm to 400 nm. For example, silicon nitride films, silicon nitride oxide films, etc., can be used. In this case, a silicon nitride film with a thickness of 150 nm is used as the insulating layer 313.

[0165] Furthermore, the silicon nitride film is preferably deposited at a high temperature to enhance its blocking properties. For example, the substrate temperature should be 100°C or higher and below the substrate's strain point, more preferably 300°C or higher. It is preferable to deposit the film by heating at a temperature of 0°C or lower. Furthermore, when depositing the film at a high temperature, semiconductors are used. Oxygen is desorbed from the oxide semiconductor used as body layers 308a, 308b, and 308c, and carrier Since a phenomenon of increased concentration may occur, the temperature should be set so that this phenomenon does not occur. ru.

[0166] Next, the insulating layer 313 is processed into the desired area, openings 374a, 374b, 37 4c, 374d, 374e are formed. In addition, the insulating layer 313 has openings 374a, 374 b, 374c, 374d, and 374e are formed in the insulating layer 314. 4, and openings 374a, 374b, 374c, 374d, 374e are located in the desired region. A mask is formed by patterning step 5, and the areas not covered by the mask are etched. It can be formed by [doing something] (see Figures 12(A), (B), and (C)).

[0167] Furthermore, the openings 374a and 374c are formed so that the conductive layers 304b and 304c are exposed. In addition, the openings 374b, 374d, and 374e are connected to the conductive layers 310c, 310d, and 31 Formed so that 0g is exposed. Note that in the region where the opening 374c is formed, Similar to the opening 372a, an opening is formed by removing a portion of the insulating layers 306 and 312. That's good too.

[0168] The method for forming the openings 374a, 374b, 374c, 374d, and 374e is as follows: For example, a dry etching method can be used. However, for openings 374a and 374 The method for forming b, 374c, 374d, and 374e is not limited to this, and wet A forming method combining the dry etching method and the wet etching method. That is also acceptable.

[0169] Next, the insulating layer 314 and the openings 374a, 374b, 374c, 374d, and 374e are covered. A conductive layer 315 is formed on the insulating layer 314 in the same manner (see Figures 13(A), (B), and (C)). ).

[0170] The conductive layer 315 includes indium oxide containing tungsten oxide, tungsten oxide, and Indium zinc oxide containing titanium oxide, indium oxide containing titanium oxide, and titanium oxide containing Indium tin oxide, indium tin oxide (hereinafter referred to as ITO), indium zinc oxide The materials used are transparent conductive materials such as indium tin oxide with added silicon dioxide. This is possible. Furthermore, the conductive layer 315 can be formed, for example, using a sputtering method. It is possible.

[0171] Next, the conductive layer 315 is processed into the desired region, thereby creating conductive layers 316a, 316b, 31 6c is formed. Note that the formation of conductive layers 316a, 316b, and 316c is performed in the desired region. A mask is formed by patterning 6, and the areas not covered by the mask are etched. It can be formed by [doing something] (see Figures 14(A), (B), and (C)).

[0172] The above process forms a drive circuit section 104 having transistors on the substrate 302, and The base part 102 and the other can be formed on the same substrate. Note that the manufacturing process shown in this embodiment In this process, the first to sixth patterns, i.e., six masks, are used for the drive circuit section, and the trap Converters, capacitive elements, and the like can be formed simultaneously.

[0173] Next, regarding the structure formed on the substrate 342 which is provided opposite the substrate 302, the following applies: Give an explanation.

[0174] First, prepare substrate 342. The materials used for substrate 342 are the same as those used for substrate 302. This can be done. Next, a light-shielding layer 344 and a colored layer 346 are formed on the substrate 342 (Figure 1 5(A), (B), (C)).

[0175] The light-shielding layer 344 only needs to have the function of blocking light in a specific wavelength band, and is made of metal. An organic insulating film containing a film or black pigment can be used.

[0176] The colored layer 346 only needs to have the function of transmitting light in a specific wavelength band, for example For example, a red (R) color filter that transmits light in the red wavelength band, and a green color filter that transmits light in the green wavelength band. A green (G) color filter that transmits light, and a blue (B) color filter that transmits light in the blue wavelength range. - Filters can be used. Each color filter is printed using various materials. These methods include inkjet methods and etching methods using photolithography technology. Form it at the desired location.

[0177] Next, an insulating layer 348 is formed on the light-shielding layer 344 and the colored layer 346 (Figure 16(A)). (See (B) and (C)).

[0178] For example, an organic insulating film such as an acrylic resin can be used as the insulating layer 348. By forming the insulating layer 348, for example, impurities contained in the colored layer 346 are removed. This can suppress diffusion towards the liquid crystal layer 320. However, the insulating layer 348 is not always It is not necessary to form it, and the structure may be one in which the insulating layer 348 is not formed.

[0179] Next, a conductive layer 350 is formed on the insulating layer 348 (see Figures 17(A), (B), and (C)). ). The conductive layer 350 can be made from the material shown for conductive layer 315.

[0180] The structure to be formed on the substrate 342 can be created through the above process.

[0181] Next, an insulating layer 31 formed on substrate 302 and substrate 342, more specifically on substrate 302. 4. Conductive layers 316a, 316b, 316c and conductive layer 350 formed on substrate 342 Alignment film 318 and alignment film 352 are formed on these, respectively. Alignment films 318 and 352 are made of rabine It can be formed using methods such as the photo-alignment method. After that, substrate 302 and substrate 342 A liquid crystal layer 320 is formed between them. The method for forming the liquid crystal layer 320 is the dispenser method (droplet Alternatively, the substrates 302 and 342 are bonded together and then liquid crystal is injected using capillary action. An injection method can be used.

[0182] By following the above steps, the display device shown in Figure 3 can be manufactured.

[0183] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0184] (Embodiment 3) In this embodiment, modified examples of the display device described in Embodiment 1 are shown in Figures 18 to 18. Let's explain using example 20.

[0185] Figure 18 shows a modified version of the structure shown in Figure 3 of Embodiment 1. Similar parts or parts with similar functions are denoted by the same reference numerals, and their details are described below. The explanation will be omitted.

[0186] Note that Figure 18(A) is a cross-section corresponding to the cross-section of the dashed line X1-Y1 shown in Figure 2(A). The diagram shows that Figure 18(B) is a cross-section of the dashed lines X2-Y2 and X3-Y3 shown in Figure 2(B). Figure 18(C) shows a cross-sectional view corresponding to the dashed line X4-Y4 shown in Figure 2(C). A cross-sectional view corresponding to a surface is shown.

[0187] The drive circuit section 104 shown in Figure 18(A) consists of a substrate 302 and a guide formed on the substrate 302. The conductive layers 304a and 304b, the substrate 302, and the conductive layers 304a and 304b are formed on the substrate 302 and the conductive layers 304a and 304b. An insulating layer 305, an insulating layer 306 formed on the insulating layer 305, and an insulating layer 306 formed on the insulating layer 306 And a semiconductor layer 308a formed in a position overlapping with the conductive layer 304a, and semiconductor layer 308a An insulating layer 370 formed on top, and a conductive layer formed on the insulating layer 370 and the semiconductor layer 308a The electrical layers 310a and 310b, the conductive layer 310c formed on the insulating layer 370, and the semiconductor layer 3 Insulating layer 312 formed to cover 08a and conductive layers 310a, 310b, and 310c And, an insulating layer 314 formed on the insulating layer 312, and a conductive layer 3 formed on the insulating layer 314 It has 16a and

[0188] In addition, in the drive circuit section 104 shown in Figure 18(A), the conductive layer 316a is the conductive layer 30 It functions as wiring connecting 4b and the conductive layer 310c. The conductive layer 304b is insulating. Through the openings formed in layers 305, 306, 312, 314, and 370, the conductive layer 310 c is connected by the conductive layer 316a through openings formed in the insulating layers 312 and 314. It can be done.

[0189] Furthermore, in the drive circuit section 104 shown in Figure 18(A), conductive layer 310a and conductive layer 3 10b is connected to the semiconductor layer 308a through an opening formed in the insulating layer 370.

[0190] The drive circuit section 104 shown in Figure 18(B) consists of a substrate 302 and a guide formed on the substrate 302. The conductive layers 304c and 304d, the substrate 302, and the conductive layers 304c and 304d are formed on the substrate 302 and the conductive layers 304c and 304d. An insulating layer 305 and a conductive layer 304d formed on the insulating layer 305 in a position overlapping with the conductive layer 304d An insulating layer 306 and a conductive layer 304d formed on the insulating layer 306 and in a position overlapping with the conductive layer 304d A semiconductor layer 308b is formed, and a conductive layer 304d is formed on the semiconductor layer 308b and superimposed on it. An insulating layer 370 formed on the surface, a conductive layer 310d formed on the insulating layer 306, and an insulating layer A conductive layer 310e formed on 370, an insulating layer 306, and conductive layers 310d and 310e An insulating layer 312 formed to cover the insulating layer 312, and an insulating layer 314 formed on the insulating layer 312, It has the following features. Furthermore, a conductive layer 316b is formed on the insulating layer 314.

[0191] In addition, in the drive circuit section 104 shown in Figure 18(B), the conductive layer 316b is the conductive layer 30 4c functions as wiring connecting conductive layer 310d. Conductive layer 316b is insulating. Openings formed in layers 305, 306, 312, 314, and 370, and insulating layers 312, 31 It is connected to the conductive layer 310d through an opening formed in 4.

[0192] In the drive circuit section 104 shown in Figure 18(B), the same applies as in the drive circuit section 104 shown in Figure 3. A static discharge induction region 360 is formed therein. The static discharge induction region 360 is in Embodiment 1 It has the same effect as the one shown.

[0193] Furthermore, in the drive circuit section 104 shown in Figure 18(B), the conductive layer 304d and the conductive layer 31 Between layers 0e, there is an insulating layer 305, an insulating layer 306, a semiconductor layer 308b, and an insulating layer 370. It has, in addition to insulating layer 305 and insulating layer 306, semiconductor layer 308b and insulating layer 370 By forming this layer, the distance between the conductive layer 304d and the conductive layer 310e can be increased. Therefore, it is possible to reduce the parasitic capacitance that may occur between the conductive layer 304d and the conductive layer 310e. It is possible. Also, by increasing the distance between conductive layer 304d and conductive layer 310e, This reduces the possibility of a short circuit between the electrical layer 304d and the conductive layer 310e.

[0194] The pixel portion 102 shown in Figure 18(C) consists of a substrate 302 and a conductive layer formed on the substrate 302. 304e, substrate 302, insulating layer 305 formed on conductive layer 304e, and insulating layer 3 An insulating layer 306 formed on 05, and a conductive layer 304e formed on the insulating layer 306 and superimposed on A semiconductor layer 308c formed at the position and a semiconductor layer 308 formed on the insulating layer 306 d, an insulating layer 370 formed on the semiconductor layer 308c, the insulating layer 370, and the semiconductor layer 3 Conductive layers 310f and 310g formed on 08c, insulating layer 370, and conductive layer 310f , an insulating layer 312 formed to cover 310g, and a layer formed on the insulating layer 312, and semi An insulating layer 314 formed on the conductive layer 308d, and a conductive layer formed on the insulating layer 314. It has a conductive layer 316c connected to 310g.

[0195] Furthermore, the conductive layer 316c is separated from the conductive layer through openings formed in the insulating layers 312 and 314. It connects to 310g.

[0196] Thus, the display devices shown in Figures 18(A), (B), and (C) are the same as those in Figures 3(A) and (B). The display device shown in (C) differs in that an insulating layer 370 is formed therein. The insulating layer 370 is After forming semiconductor layers 308a, 308b, 308c, and 308d, an insulating layer is formed, and the insulating layer It can be formed by processing the edge layer. The insulating layer 370 is used in the insulating layer 312. It can be formed by materials and methods that can be used.

[0197] By forming the insulating layer 370, it is possible to cover the semiconductor layers 308a and 308c. This is the result. In addition, the semiconductor layers 308a and 308c are separated by openings provided in the insulating layer 370. The conductive layers 310a, 310b, and 310f function as source and drain electrodes. Connects to 310g. When processing the conductive layer that functions as the source electrode and drain electrode. The semiconductor layers 308a and 308c are protected by the insulating layer 370. Therefore, the insulating layer 370 It functions as a so-called channel protection layer.

[0198] Furthermore, in the display devices shown in Figures 3(A), (B), and (C), as shown in Embodiment 2... It can be made with six masks. On the other hand, Figures 18(A), (B), and (C) In the display device shown, the number of masks increases by one, allowing it to be manufactured with seven masks. .

[0199] Furthermore, in transistors 131_3 and 131_1 shown in Figure 18, the insulating layer 370 is The shape covering the semiconductor layers 308a and 308c has been described, but it is not limited to this. For example, as shown in Figure 19, an insulating layer 370 is formed only in the channel formation region of the transistor. This configuration is also acceptable. However, as shown in Figure 18, the outside of the semiconductor layers 308a and 308c The surrounding area is also covered by the insulating layer 370, which prevents impurities from penetrating the semiconductor layers 308a and 308c. Since objects can be protected by the insulating layer 370, the structure shown in Figure 18 is preferable. This is a more suitable structure.

[0200] Next, we will provide the following explanation regarding the display device shown in Figure 20.

[0201] Figures 20(A) and (B) show modified examples of the structure shown in Figure 3(A) of Embodiment 1. Regarding the same parts or parts having similar functions as shown in the previous embodiment, A symbol is used, and a detailed explanation is omitted.

[0202] The drive circuit section 104 shown in Figure 20(A) is compared with the drive circuit section 104 shown in Figure 3(A). Therefore, the method of connecting conductive layer 304b and conductive layer 310c is different. Specifically, see Figure 20(A) In the drive circuit section 104 shown, a portion of the conductive layer 310c is superimposed on a portion of the conductive layer 304b. They are arranged in this manner. Furthermore, conductive layer 304b and conductive layer 310c are connected via conductive layer 316a. They are connected in this way. In this manner, a part of the conductive layer 310c is superimposed on a part of the conductive layer 304b. By providing this, the area of ​​the drive circuit can be reduced. For example, Figure 20(A When the drive circuit section 104 shown in Figure 1(A) is used in the gate driver 104a shown in Figure 1(A), This makes it possible to reduce the area of ​​the driver 104a.

[0203] The drive circuit section 104 shown in Figure 20(B) is compared with the drive circuit section 104 shown in Figure 3(A). The points where the insulating layer 370 is formed and the method of connecting the conductive layer 304b and the conductive layer 310c They are different. The insulating layer 370 has the same functions and effects as the insulating layer 370 shown in Figure 18. Regarding the method of connecting conductive layer 304b and conductive layer 310c, the connection method shown in Figure 20(A) and It has similar functions and effects.

[0204] As described above, in the display device shown in this embodiment, the drive circuit portion has an electrostatic discharge induction region It has a region. The electrostatic discharge induction region is formed in the same process as the gate electrode and the source The thickness of the insulating film formed between the wiring, which is formed in the same process as the electrodes and drain electrodes, By making it thinner, that is, by shortening the distance between wirings, the insulating film between other wiring patterns is reduced. This can suppress electrostatic discharge. Furthermore, in the electrostatic discharge induction region, the gate electrode and Because the shape of the wiring formed in the same process is comb-shaped, the overcurrent that can be generated by ESD It has a structure that makes it easy to flush.

[0205] Thus, one aspect of the present invention is a display device having an electrostatic discharge induction region in the drive circuit section. This makes it possible to provide a novel display device that can improve reliability.

[0206] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0207] (Embodiment 4) In this embodiment, a modified example of the electrostatic discharge induction region 360 described in Embodiment 1 is provided. This will be explained using Figure 21.

[0208] In Embodiment 1, the electrostatic discharge induction region 360 is formed in the drive circuit section 104. The configuration described above is an electrostatic discharge induction The configuration that forms the emission region will be described.

[0209] Figure 21(A) schematically shows the top view of the display device and the outer periphery of the display device, and Figure 2 1(B) schematically shows an enlarged top view of the electrostatic discharge induction region 362a shown in Figure 21(A). This is represented, and Figure 21(C) corresponds to the cross-sectional view relating to the cutting line X5-Y5 shown in Figure 21(B). do.

[0210] Figure 21(A) shows the pixel unit 102, the gate driver 104a, and the source driver 104 b and are formed on the display device 100. In addition, multiple are formed on the outer periphery of the display device 100. A guard ring 362 including wiring is formed. The guard ring 362 is designed to induce electrostatic discharge. It has region 362a.

[0211] As shown in Figure 21(A), a guard ring 362 is formed on the outer circumference of the display device 100. Therefore, in the manufacturing process of the display device 100, overcurrents caused by ESD, etc., may occur. This protects the display device 100. For example, if an event occurs during the manufacturing process of the display device 100. When an overcurrent occurs, the guard ring 362 acts as an antenna, and the overcurrent is transmitted to the guard ring 362. It can be applied. In this way, by forming the guard ring 362, the display device 10 The 0 can be protected from overcurrents caused by ESD, etc.

[0212] Figure 21(B) shows an enlarged view of the electrostatic discharge induction region 362a formed in the guard ring 362. This is a top view. Refer to Figures 21(A), (B), and (C) for the electrostatic discharge induction region 362a. The following explanation will be given regarding this matter.

[0213] The electrostatic discharge induction region 362a consists of the substrate 402 and the conductive layer 404 formed on the substrate 402. And, an insulating layer 405 formed on the substrate 402 and the conductive layer 404, and formed on the insulating layer 405 An insulating layer 406, a conductive layer 410 formed on the insulating layer 406, and the insulating layer 406 and An insulating layer 412 formed on the conductive layer 410, and an insulating layer 414 formed on the insulating layer 412. It has a conductive layer 416 formed on an insulating layer 414.

[0214] Furthermore, the substrate 402 is made of a material that can be used for the substrate 302 shown in the previous embodiment. It can be used by referencing the above. Also, the conductive layer 404 is the conductive layer 3 shown in the above embodiment. Materials that can be used in 04a can be used in conjunction with other materials. Also, insulating layer 405 This involves using a material that can be used for the insulating layer 305 as shown in the previous embodiment. This can be done. In addition, the insulating layer 406 is used in place of the insulating layer 306 shown in the previous embodiment. Materials capable of this can be used. In addition, the conductive layer 410 is as described in the previous embodiment. The materials that can be used for the conductive layer 310a shown can be used in conjunction with this. The insulating layer 412 is made using a material that can be used for the insulating layer 312 shown in the previous embodiment. It can be used in this way. In addition, the insulating layer 414 is the insulating layer 314 shown in the previous embodiment. Materials that can be used for this purpose can be used by assisting in the process. In addition, the conductive layer 416 is the same as above. The materials that can be used for the conductive layer 316a shown in the embodiment can be used by reference. Cut.

[0215] Furthermore, the electrostatic discharge induction region 362a has an opening 474a and an opening 474b. The opening 474a is formed by removing a portion of the insulating layers 405, 406, 412, and 414, and the conductive layer 404 is exposed. Also, in the opening 474b, a portion of the insulating layers 412 and 414 has been removed. The conductive layer 410 is exposed. Also, the openings 474a, 474b, and the insulating layer 414 The conductive layer 404 and the conductive layer 410 are connected by the conductive layer 416 formed on top of them.

[0216] In this embodiment, the conductive layer 416 is located above the electrostatic discharge induction region 362a. The description will focus on shapes that completely cover the area, but are not limited to this. For example, openings 474a, 47 Alternatively, the conductive layer 416 may be formed only on the portion where 4b is formed, or the conductive layer 41 A configuration in which 6 is not formed is also possible. The guard ring 362, and the guard ring 362 Since the electrostatic discharge induction region 362a is formed on the outer periphery of the display device 100, the display device It does not directly affect position 100. Therefore, the method of connecting conductive layer 404 and conductive layer 410 The implementer shall appropriately determine the optimal structure for the upper surface shape of conductive layer 404 and conductive layer 410, etc. You can choose this option.

[0217] Furthermore, the effect of the electrostatic discharge induction region 362a is as shown in the electrostatic discharge discharge of Embodiment 1 above. It has the same effect as the induced region 360.

[0218] Thus, in this embodiment, an electrostatic discharge induction region is formed on the outer periphery of the display device. By doing so, it is possible to provide a novel display device that can improve reliability.

[0219] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0220] (Embodiment 5) In this embodiment, the number of rotations that can be used in the pixel circuit section 108 shown in Figure 1(A) The circuit configuration will be explained using Figure 22. Note that the same functions as shown in the previous embodiment will be explained. Parts that possess the same symbol are denoted accordingly, and detailed explanations are omitted.

[0221] The pixel circuit section 108 shown in Figure 22(A) consists of a liquid crystal element 322 and a transistor 131_1 It has a capacitive element 133_1 and

[0222] The potential of one of the pair of electrodes of the liquid crystal element 322 is set appropriately according to the specifications of the pixel circuit section 108. The orientation state of the liquid crystal element 322 is set according to the data written to it. One of the pairs of electrodes of the liquid crystal element 322, which each of the multiple pixel circuit sections 108 has, is common to A potential (common potential) may be applied. Also, the liquid crystal element 322 of the pixel circuit section 108 of each row A different potential may be applied to one of the pair of electrodes.

[0223] For example, the driving method for a display device equipped with a liquid crystal element 322 is TN mode, STN mode Code, VA mode, ASM (Axially Symmetric Aligned Motor) icro-cell) mode, OCB (Optically Compensated Birefringence mode, FLC (Ferroelectric Liqu id Crystal) mode, AFLC (AntiFerroelectric Li) quid Crystal) mode, MVA mode, PVA (Patterned Ve (Critical Alignment) mode, IPS mode, FFS mode, or TBA You may also use modes such as (Transverse Bend Alignment). In addition, as a method of driving the display device, there is also ECB (Electric Ally Controlled Birefringence) mode, PDLC (P Olymer Dispersed Liquid Crystal (PNLC) mode, (Polymer Network Liquid Crystal) mode, guest host There are modes such as St Mode. However, this is not limited to these, and various types of liquid crystal elements and their driving methods exist. Various materials can be used.

[0224] Furthermore, a liquid crystal composition containing a liquid crystal exhibiting a blue phase and a chiral agent. The liquid crystal element may be constructed in this manner. The liquid crystal exhibiting the blue phase has a response speed of 1 msec or less. Because it is short and optically isotropic, orientation processing is unnecessary and it has low dependence on the viewing angle.

[0225] In the pixel circuit section 108 of row m and column n, the source and drain of transistor 131_1 One end of the wire is electrically connected to the data line DL_n, and the other end is connected to a pair of electrodes of the liquid crystal element 322. It is electrically connected to the other side. Also, the gate of transistor 131_1 is on the scan line GL_ It is electrically connected to m. Transistor 131_1 can be in an ON state or an OFF state. This provides a function to control the writing of data to the data signal.

[0226] One of the pair of electrodes of the capacitive element 133_1 is connected to a wiring to which a potential is supplied (hereinafter referred to as the potential supply wire). One end is electrically connected to VL, and the other end is electrically connected to the other of the pair of electrodes of the liquid crystal element 322. The potential value of the potential supply line VL is set appropriately according to the specifications of the pixel circuit 111. Capacitive element 133_1 has the function of a holding capacity that holds the written data. do.

[0227] For example, in a display device having the pixel circuit section 108 shown in Figure 22(A), the gate driver 10 4a sequentially selects the pixel circuit section 108 for each row and turns on transistor 131_1. Then, the data signal is written.

[0228] When data is written to the pixel circuit section 108, the transistor 131_1 turns off. This puts the image into a held state. By doing this sequentially for each row, the image can be displayed.

[0229] Furthermore, the pixel circuit section 108 shown in Figure 22(B) includes a transistor 131_2 and a capacitive element. It has 133_2, a transistor 134, and a light-emitting element 135.

[0230] The source and drain of transistor 131_2 are connected to the wiring to which the data signal is applied. It is electrically connected to the data line DL_n (hereinafter referred to as data line DL_n). Furthermore, transistor 131 The gate of _2 has an electrical signal applied to the wiring to which the gate signal is applied (hereinafter referred to as scan line GL_m). It connects to the network.

[0231] Transistor 131_2 is either on or off, which controls the data signal. It has a function to control data writing.

[0232] One of the pair of electrodes of the capacitive element 133_2 is connected to the wiring to which power is supplied (hereinafter referred to as the power line VL). It is electrically connected to (a), and the other is the source and slave of transistor 131_2. It is electrically connected to the other side.

[0233] The capacitive element 133_2 functions as a holding capacitor that retains the written data. .

[0234] One of the sources and drains of transistor 134 is electrically connected to the power line VL_a. Furthermore, the gate of transistor 134 is connected to the source and gate of transistor 131_2. It is electrically connected to the other side of the rain.

[0235] One of the anodes and cathodes of the light-emitting element 135 is electrically connected to the power line VL_b. The other end is electrically connected to the other end of the source and drain of transistor 134.

[0236] The light-emitting element 135 can be, for example, an organic electroluminescent element (also known as an organic EL element). (These can be used.) However, the light-emitting element 135 is not limited to these. Inorganic EL elements made of inorganic materials may also be used.

[0237] Furthermore, a high power supply potential VDD is applied to one of the power lines VL_a and VL_b. On the other hand, a low power supply potential VSS is provided.

[0238] In the display device having the pixel circuit section 108 shown in Figure 22(B), the gate driver 104a Then, sequentially select the pixel circuit section 108 for each row and turn on the transistor 131_2 to data Write the data for the signal.

[0239] When data is written to the pixel circuit section 108, the transistor 131_2 turns off. This puts it into a holding state. Furthermore, transistor 1 responds to the potential of the written data signal. The amount of current flowing between the source and drain of 34 is controlled, and the light-emitting element 135 controls the current flowing through it. It emits light with brightness corresponding to the amount of light. By doing this sequentially for each row, an image can be displayed.

[0240] In this specification, etc., display element, display device having a display element, light-emitting element A light-emitting device, which is a device having sub-elements and light-emitting elements, can use various forms, or various It may have elements. Examples of display elements, display devices, light-emitting elements, or light-emitting devices include EL (electroluminescent) elements (EL elements including organic and inorganic materials, organic EL) Elements (inorganic EL elements), LEDs (white LEDs, red LEDs, green LEDs, blue LEDs, etc.) ), transistor (a transistor that emits light in response to current), electron emission element, liquid crystal element, electric Ink cartridges, electrophoretic elements, grating light bulbs (GLVs), plasma displays PDP (Photographic Display Panel), MEMS (Micro-Electro-Mechanical Systems), Digital Ma Micromirror device (DMD), DMS (Digital Microshutter), MIR ASOL®, IMOD (Interference Modulation) element, pressure Electroceramic displays, carbon nanotubes, etc., are produced by electromagnetic interaction. Some display media have properties such as traceability, brightness, reflectivity, and transmittance that change. (EL element) An example of a display device using electron emission elements is an EL display. Examples of display devices include field emission displays (FEDs) or SEDs. Surface-conduction electrostatic display (SED) Examples include on-emitter displays. Examples include liquid crystal displays (transmissive liquid crystal displays, semi-transmissive liquid crystal displays, and transflective liquid crystal displays). Examples include projected liquid crystal displays (LCDs), direct-view LCDs, and projection-type LCDs. An example of a display device using electronic ink or electrophoretic elements is electronic paper. ru.

[0241] An example of an EL element is an anode, a cathode, and an EL layer sandwiched between the anode and cathode. Some elements possess this technology. One example of an EL layer is the use of light emission (fluorescence) from singlet excitons. This method utilizes the emission (phosphorescence) from triplet excitons, and the emission from singlet excitons. This includes methods that utilize fluorescence and methods that utilize light emission (phosphorescence) from triplet excitons. Things formed by organic matter, things formed by inorganic matter, things formed by organic matter Includes materials formed from inorganic substances, and materials containing polymer materials. , materials containing low molecular weight materials, or materials containing both high molecular weight and low molecular weight materials, etc. There are various types of EL elements. However, they are not limited to these, and a variety of other elements can be used as EL elements.

[0242] One example of a liquid crystal element is one in which the transmission or non-transmission of light is controlled by the optical modulation effect of the liquid crystal. There is such an element. This element can be constructed from a pair of electrodes and a liquid crystal layer. The optical modulation effect of liquid crystals is due to the electric field acting on the liquid crystal (horizontal electric field, vertical electric field, or diagonal electric field). It is controlled by (including the electric field in the direction). Specifically, an example of a liquid crystal element is a Matic LCD, Cholesteric LCD, Smectic LCD, Discotic LCD, Thermo hydroxychlorocrystalline liquid crystal, lyotropic liquid crystal, low molecular weight liquid crystal, polymer liquid crystal, polymer dispersed liquid crystal (PD) LC, ferroelectric liquid crystal, antiferroelectric liquid crystal, main-chain liquid crystal, side-chain polymer liquid crystal, banana-shaped liquid crystal, etc. We can list some examples.

[0243] One example of an electronic paper display method is one that uses molecules for display (optical anisotropy, dyeing). (e.g., molecular orientation), and phenomena that are represented by particles (e.g., electrophoresis, particle movement, particle rotation, phase change). (etc.), things that are displayed by the movement of one end of the film, or by the color development / phase change of molecules These are phenomena that are displayed by light absorption by molecules, or phenomena that occur when electrons and holes combine. Displays that emit light can be used. Specifically, electronic paper displays. Examples of methods include microcapsule electrophoresis, horizontal-transfer electrophoresis, and vertical-transfer electrophoresis. Gas electrophoresis, spherical twist balls, magnetic twist balls, cylindrical twist ball method, electrostatic toner - Electron powder fluid, magnetophoresis type, magnetic thermal type, electrowetting, light scattering (transparent / (Opacity change), Cholesteric liquid crystal / photoconductive layer, Cholesteric liquid crystal, Bistable nematic Liquid crystal, ferroelectric liquid crystal, dichroic dye / liquid crystal dispersion, movable film, color change / decolorization by leuco dye. Photochromic, electrochromic, electrodeposition, flexible Examples include electronic EL displays. However, this is not limited to these, and there are various electronic paper and display methods. Various materials can be used. Here, by using microcapsule electrophoresis... This can solve the aggregation and precipitation of electrophoretic particles. Electron powder fluid offers high-speed response and high reactivity. It offers advantages such as high emissivity, wide field of view, low power consumption, and memory capabilities.

[0244] The configuration shown in this embodiment may be used in appropriate combination with the configurations shown in other embodiments. It is possible.

[0245] (Embodiment 6) In this embodiment, the pixel portion 102 of the display device shown in Figure 1(A) of Embodiment 1, And the configuration of the transistors that can be used in the drive circuit section 104 is shown in Figure 23. The following is an explanation.

[0246] The transistor shown in Figure 23(A) has a conductive layer 304a formed on the substrate 302 and a base Insulating layers 305 and 306 formed on plate 302 and conductive layer 304a, and on insulating layer 306 The formed oxide laminate 390, the insulating layer 306 and the conductive layer formed on the oxide laminate 390 It has layers 310a and 310b. Also, the transistor shown in Figure 23(A) is the transistor. Formed on the radiator, more specifically on the oxide layer 390 and the conductive layers 310a and 310b. The configuration may also include insulating layers 312 and 314.

[0247] Furthermore, depending on the type of conductive film used in the conductive layers 310a and 310b, the oxide laminate 390 By removing oxygen from a portion of it, or by forming a mixed layer, an n-type region 392 is created in the oxide layer 390. It may form. In Figure 23(A), the n-type region 392 is in the oxide layer 390. It can be formed in the region near the interface that contacts the conductive layers 310a and 310b. Note that n-type region 39 Section 2 can function as both a source area and a drain area.

[0248] Furthermore, in the transistor shown in Figure 23(A), the conductive layer 304a functions as a gate electrode. The conductive layer 310a functions as a source electrode or drain electrode, and the conductive layer 310b functions as a source electrode. It functions as a drain electrode or a drain electrode.

[0249] Furthermore, the transistor shown in Figure 23(A) has an oxide product in the region superimposed with the conductive layer 304a. The distance between conductive layer 310a and conductive layer 310b of layer 390 is called the channel length. The layer formation region is the region in the oxide stack 390 that is superimposed on the conductive layer 304a and the conductive layer 31 This refers to the region sandwiched between 0a and the conductive layer 310b. Furthermore, a channel is defined as the channel formation region. In this context, it refers to the region where electric current primarily flows.

[0250] Here, the details of the oxide layer 390 will be explained in detail using Figure 23(B).

[0251] Figure 23(B) is an enlarged view of the oxide layer 390 shown in Figure 23(A). 90 has an oxide semiconductor layer 390a and an oxide layer 390b.

[0252] The oxide semiconductor layer 390a contains at least indium (In), zinc (Zn), and M(A In-MZ containing elements such as l, Ga, Ge, Y, Zr, Sn, La, Ce, or Hf. It is preferable to include a layer denoted as n oxide. Note that the oxide semiconductor layer 390a is the same as above. Oxide semiconductor material that can be used in the semiconductor layer 308a shown in the embodiment, or forming Methods and other techniques may be used as appropriate.

[0253] The oxide layer 390b is composed of one or more of the elements that make up the oxide semiconductor layer 390a. The energy at the lower end of the conduction band is 0.05 eV or more higher than that of the oxide semiconductor layer 390a, and 0.07 eV or greater, 0.1eV or greater or 0.15eV or greater, and 2eV or less, 1eV or less, 0.5 It is an oxide film with a vacuum level of 0.4 eV or less. In this case, it is used as a gate electrode. When an electric field is applied to the conductive layer 304a which functions as such, the lower end of the conduction band of the oxide stack 390 Channels are formed in the oxide semiconductor layer 390a, which has low energy. By having an oxide layer 390b between the semiconductor layer 390a and the insulating layer 312, The channel of the inverter is formed in the oxide semiconductor layer 390a that does not come into contact with the insulating layer 312. Yes, it is possible. Also, one or more elements that make up the oxide semiconductor layer 390a can be used to form the oxide layer 390b. As a result, interfacial dispersion occurs between the oxide semiconductor layer 390a and the oxide layer 390b. Disturbance is less likely to occur. Therefore, between the oxide semiconductor layer 390a and the oxide layer 390b As a result, the movement of carriers is not hindered, and the field-effect mobility of the transistor increases. Furthermore, it is difficult to form interface states between the oxide semiconductor layer 390a and the oxide layer 390b. If there is an interface state between the oxide semiconductor layer 390a and the oxide layer 390b, the interface becomes a channel. A second transistor with a different threshold voltage is formed, and the apparent transistor The threshold voltage may fluctuate. Therefore, by providing the oxide layer 390b... This can reduce variations in electrical characteristics such as the threshold voltage of transistors.

[0254] The oxide layer 390b is In-M-Zn oxide (Al, Ti, Ga, Ge, Y, Zr It is expressed as an element (such as Sn, La, Ce, or Hf), and is M greater than oxide semiconductor layer 390a. It contains an oxide layer with a high atomic ratio of [amount]. Specifically, as oxide layer 390b, it is an oxide semiconductor. The aforementioned elements are present in 1.5 times or more, preferably 2 times or more, and more preferably 3 times more than in layer 390a. An oxide layer containing the element at more than twice the atomic ratio is used. The aforementioned element is more strongly bonded with oxygen than indium. Because it bonds, it has the function of suppressing the occurrence of oxygen vacancies in the oxide layer. That is, oxide Layer 390b is an oxide layer that is less prone to oxygen vacancies than oxide semiconductor layer 390a.

[0255] In other words, the oxide semiconductor layer 390a and the oxide layer 390b contain at least indium and zinc. When the oxide layer 390b is an In-M-Zn oxide containing M, the In:M:Zn=x1 :y1:z1 [atomic ratio], oxide semiconductor layer 390a In:M:Zn=x2:y2:z If we set the atomic ratio to 2, then it is preferable that y1 / x1 is greater than y2 / x2. y1 / x1 is 1.5 times or more than y2 / x2, preferably 2 times or more, and more preferably 3 times It should be more than double. At this time, in the oxide semiconductor layer 390a, if y2 is x2 or more, The electrical characteristics of the transistor can be stabilized. However, y2 will be more than 3 times x2. As a result, the field-effect mobility of the transistor decreases, so y2 is less than three times x2. It is preferable.

[0256] Furthermore, when the oxide semiconductor layer 390a is an In-M-Zn oxide, the number of atoms of In and M The ratio is preferably such that when the sum of In and M is 100 atomic%, In is 25a A tomic% or greater, M less than 75 atomic, and more preferably In 34 atoms The ic% must be greater than or equal to 66 atomic%, and M must be less than 66 atomic%. In addition, the oxide layer 390b must be In-M- When it is a Zn oxide, the atomic ratio of In to M is such that the sum of In and M is 100 atoms. When set to c%, preferably In is less than 50 atomic%, and M is 50 atomic% or more. Furthermore, preferably, In is less than 25 atomic%, and M is 75 atomic%, or more. ru.

[0257] The oxide semiconductor layer 390a and the oxide layer 390b contain, for example, indium, zinc, and A gallium-containing oxide semiconductor can be used. Specifically, an oxide semiconductor layer 39 As for 0a, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=1:1:1, In-Ga-Zn oxide with an atomic ratio of In:Ga:Zn=3:1:2, or a similar configuration. An oxide having the following composition can be used, and as the oxide layer 390b, In:Ga:Zn =1:3:2 [atomic ratio] In-Ga-Zn oxide, In:Ga:Zn=1:6:4 [ In-Ga-Zn oxide with atomic ratio, In:Ga:Zn=1:9:6 [atomic ratio] n-Ga-Zn oxide, or an oxide having a composition close thereto, can be used.

[0258] Furthermore, the thickness of the oxide semiconductor layer 390a is 3 nm to 200 nm, preferably 3 nm. The wavelength should be between m and 100 nm, more preferably between 3 nm and 50 nm. The thickness of layer 390b is 3 nm to 100 nm, preferably 3 nm to 50 nm. do.

[0259] Next, the band structure of the oxide stack 390 will be explained using Figures 23(C) and (D). ru.

[0260] For example, if the oxide semiconductor layer 390a has an energy gap of 3.15 eV, then I Using n-Ga-Zn oxide, the oxide layer 390b has an energy gap of 3.5 eV. The In-Ga-Zn oxide is used. The energy gap is measured using a spectroscopic ellipsometer (H Measurements were taken using an ORIBA JOBIN YVON UT-300.

[0261] The energy of the vacuum level and the upper edge of the valence band in oxide semiconductor layer 390a and oxide layer 390b. The differences (also called ionization potentials) were 8 eV and 8.2 eV, respectively. Oh, the energy difference between the vacuum level and the upper end of the valence band can be determined by ultraviolet photoelectron spectroscopy (UPS:Ult). raviolet Photoelectron Spectroscopy) equipment (U Measurements were taken using LVAC·PHI's VersaProbe®.

[0262] Therefore, the vacuum levels of the oxide semiconductor layer 390a and the oxide layer 390b and the lower edge of the conduction band The energy differences (also called electron affinity) were 4.85 eV and 4.7 eV, respectively. Ta.

[0263] Figure 23(C) schematically shows a portion of the band structure of the oxide stack 390. The following describes the case where a silicon oxide film is provided in contact with the oxide laminate 390. EcI1, represented in 23(C), indicates the energy at the lower end of the conduction band of the silicon oxide film, and EcS1 The line indicates the energy at the lower end of the conduction band of the oxide semiconductor layer 390a, and EcS2 is the energy of the oxide layer 390a b represents the energy at the lower end of the conduction band, and EcI2 represents the energy at the lower end of the conduction band of the silicon oxide film. — indicates. Also, EcI1 corresponds to the insulating layer 306 in Figure 23(A), and EcI2 This corresponds to the insulating layer 312 in Figure 23(A).

[0264] As shown in Figure 23(C), in the oxide semiconductor layer 390a and the oxide layer 390b, The energy at the lower end of the conduction band changes smoothly because there is no barrier. In other words, it changes continuously. It can also be said that the oxide layer 390 is common with the oxide semiconductor layer 390a. It contains the element, and oxygen moves between the oxide semiconductor layer 390a and the oxide layer 390b. This can be attributed to the formation of a mixed layer.

[0265] From Figure 23(C), the oxide semiconductor layer 390a of the oxide stack 390 becomes a well. Furthermore, in a transistor using an oxide multilayer 390, the channel region is an oxide semiconductor layer 3 It can be seen that it is formed at 90a. Note that the energy at the lower end of the conduction band of the oxide stack 390 is Because it is changing continuously, the oxide semiconductor layer 390a and the oxide layer 390b are continuously bonded. It could also be said that it is.

[0266] Furthermore, as shown in Figure 23(C), near the interface between the oxide layer 390b and the insulating layer 312 Although trap levels may be formed due to impurities and defects, the oxide layer 390b is set This allows the oxide semiconductor layer 390a and the trap level to be separated. However, if the energy difference between EcS1 and EcS2 is small, the oxide semiconductor layer 390 Electrons in a may exceed the energy difference and reach the trap level. When a child is captured, a negative charge is generated at the insulating film interface, affecting the transistor's threshold voltage. The pressure shifts in the positive direction. Therefore, the energy difference between EcS1 and EcS2 If this is set to 0.1 eV or higher, preferably 0.15 eV or higher, the threshold voltage of the transistor This is preferable because it reduces pressure fluctuations and results in stable electrical characteristics.

[0267] Figure 23(D) schematically shows a part of the band structure of the oxide layer 390, and Figure 23(C) This is a modified example of the band structure shown. Here, a silicon oxide film is placed in contact with the oxide stack 390. The case where it is provided will be explained. Note that EcI1 shown in Figure 23(D) is the silicon oxide film This shows the energy at the lower edge of the conduction band, and EcS1 is the energy at the lower edge of the conduction band of the oxide semiconductor layer 390a. EcI2 shows the energy, and EcI2 shows the energy at the lower end of the conduction band of the silicon oxide film. I1 corresponds to the insulating layer 306 in Figure 23(A), and EcI2 corresponds to the insulating layer 306 in Figure 23(A). This corresponds to the insulating layer 312.

[0268] In the transistor shown in Figure 23(A), oxidation occurs during the formation of conductive layers 310a and 310b. The upper layer of the material stack 390, i.e., the oxide layer 390b, may be etched. The upper surface of the oxide semiconductor layer 390a is formed when the oxide semiconductor layer 390b is deposited. A mixed layer of a and oxide layer 390b may be formed.

[0269] For example, the oxide semiconductor layer 390a has an I ratio of In:Ga:Zn = 1:1:1. n-Ga-Zn oxide, or In-Ga with an atomic ratio of In:Ga:Zn=3:1:2 - It is a Zn oxide, and the oxide layer 390b has an atomic ratio of In:Ga:Zn=1:3:2 In-Ga-Zn oxide, or In:Ga:Zn=1:6:4 [atomic ratio] In- In the case of Ga-Zn oxide, the Ga content of oxide layer 390b is higher than that of oxide semiconductor layer 390a. Due to the high content, the upper surface of the oxide semiconductor layer 390a is a GaOx layer or an oxide semiconductor layer. A mixed layer containing more Ga than layer 390a may be formed.

[0270] Therefore, even when the oxide layer 390b is etched, EcI of EcS1 The energy at the lower end of the conduction band on side 2 increases, resulting in the band structure shown in Figure 23(D). There are cases where this is the case.

[0271] This embodiment can be appropriately combined with other embodiments shown herein. ru.

[0272] (Embodiment 7) In this embodiment, a touch can be combined with a display device according to one aspect of the present invention. The sensor and display module will be explained using Figures 24 to 26.

[0273] Figure 24(A) is an exploded perspective view showing an example configuration of the touch sensor 4500, and Figure 24(B) This is a plan view showing an example of the electrode configuration of the touch sensor 4500. Figure 25 is a touch This is a cross-sectional view showing an example configuration of sensor 4500.

[0274] The touch sensor 4500 shown in Figures 24(A) and (B) is mounted on the substrate 4910 in the X-axis direction. Multiple conductive layers 4510 arranged in a line, and multiple conductive layers arranged in the Y-axis direction intersecting the X-axis direction. A layer 4520 is formed. The touch sensor 4500 shown in Figures 24(A) and (B) is A plan view showing multiple conductive layers 4510 formed thereon, and a plan view showing multiple conductive layers 4520 are separated. They are displayed separately.

[0275] Furthermore, Figure 25 shows the conductive layer 4510 and conductive layer 452 of the touch sensor 4500 shown in Figure 24. This is an equivalent circuit diagram of the intersection with 0. As shown in Figure 25, conductive layer 4510 and conductive layer 45 At the intersection of the 20, a capacity of 4540 is formed.

[0276] Furthermore, the conductive layers 4510 and 4520 have a structure in which multiple quadrilateral conductive films are connected. The multiple conductive layers 4510 and the multiple conductive layers 4520 are the quadrilateral portion of the conductive film. They are arranged so that their positions do not overlap. The conductive layer 4510 and conductive layer 4520 intersect. In this portion, an insulating film is provided between the conductive layer 4510 and the conductive layer 4520 so that they do not come into contact. Yes, they are.

[0277] Furthermore, Figure 26 shows the conductive layer 4510 and conductive layer 452 of the touch sensor 4500 shown in Figure 24. This is a cross-sectional diagram illustrating an example of a connection structure with 0, and the conductive layer 4510 (conductive layer 4510a, 4 A cross-sectional view of the intersection of 510b, 4510c) and 4520 is shown as an example.

[0278] As shown in Figure 26, the conductive layer 4510 consists of the first conductive layer 4510a and the conductive layer 45 It is composed of 10b and a second conductive layer 4510c on the insulating layer 4810. The electrolytic layer 4510a and the conductive layer 4510b are connected by the conductive layer 4510c. 4520 is formed by the first conductive film layer. Conductive layers 4510, 4520 and electrode 47 An insulating layer 4820 is formed covering 10. For example, insulating layers 4810 and 4820 are... Then, a silicon oxidizride film can be formed. Note that the substrate 4910 and the conductive layer 4510 and An insulating film underlay may be formed between the electrodes 4710, for example, an insulating film. A silicon nitride film can be formed.

[0279] The conductive layer 4510 and the conductive layer 4520 are formed of a conductive material that is transparent to visible light. For example, as a conductive material with light transmission, indium tin oxide containing silicon oxide, acid Indium tin oxide, zinc oxide, indium zinc oxide, zinc oxide with added gallium, etc. ru.

[0280] The conductive layer 4510a is connected to the electrode 4710. The electrode 4710 is connected to the FPC. It forms a connection terminal. The conductive layer 4520, like the conductive layer 4510, is in contact with the other electrode 4710. The process continues. The electrode 4710 can be formed from, for example, a tungsten film.

[0281] An insulating layer 4820 is formed covering the conductive layers 4510, 4520, and 4710. In order to electrically connect electrode 4710 and FPC, an insulating layer 4810 and on electrode 4710 An opening is formed in the insulating layer 4820. The substrate 4920 is bonded onto the insulating layer 4820. It is attached with an adhesive or adhesive film. The substrate 4 By attaching the 910 to the color filter board of the display panel, the touch panel is configured. It can be done.

[0282] Next, regarding a display module that can use a display device according to one aspect of the present invention, Figure 2 We will use number 7 to explain.

[0283] The display module 8000 shown in Figure 27 consists of an upper cover 8001 and a lower cover 8002. In between, the touch panel 8004 connected to the FPC8003 and the FPC8005 are connected. Display panel 8006, backlight unit 8007, frame 8009, printed circuit board It has a board 8010 and a battery 8011.

[0284] The upper cover 8001 and the lower cover 8002 are the touch panel 8004 and the display panel. The shape and dimensions can be appropriately modified to match the size of the 8006.

[0285] The touch panel 8004 is a display panel using either a resistive or capacitive touch panel. It can be used superimposed on 8006. Also, the opposing substrate (sealing substrate) of the display panel 8006 It is also possible to give the board a touch panel function. It is also possible to install a light sensor in each pixel of 006 to create an optical touch panel.

[0286] The backlight unit 8007 has a light source 8008. The light source 8008 is a backlight It may also be configured to use a light-diffusing plate, which is provided at the end of the light unit 8007.

[0287] Frame 8009 provides protection for the display panel 8006, as well as the movement of the printed circuit board 8010. It has the function of an electromagnetic shield to block electromagnetic waves generated by the operation. The 8009 may also function as a heat sink.

[0288] The printed circuit board 8010 contains power supply circuits and signals for outputting video and clock signals. It has a power processing circuit. The power supply that provides power to the power supply circuit is an external commercial power supply. Alternatively, a separate power source, battery 8011, may also be used. Item 1 can be omitted when using commercial power.

[0289] Furthermore, the display module 8000 includes components such as polarizing plates, phase difference plates, and prism sheets. They may also be provided.

[0290] The configurations shown in this embodiment may be combined with the configurations shown in other embodiments as appropriate. It can be used.

[0291] (Embodiment 8) In this embodiment, an example of an electronic device will be described.

[0292] Figures 28(A) to 28(H) and 29(A) to 29(D) are diagrams showing electronic devices. These electronic devices consist of a housing 5000, a display unit 5001, a speaker 5003, and an LE. D lamp 5004, operation key 5005 (including power switch or operation switch), connection Terminal 5006, Sensor 5007 (force, displacement, position, velocity, acceleration, angular velocity, rotational speed, distance) Light, liquid, magnetism, temperature, chemicals, sound, time, hardness, electric field, electric current, voltage, power, radiation (including functions for measuring flow rate, humidity, gradient, vibration, odor, or infrared radiation), Microwave It can have 5008, etc.

[0293] Figure 28(A) shows a mobile computer, and in addition to the above, it also has a switch 5009 It may have an infrared port 5010, etc. Figure 28(B) shows a portable recording device equipped with a recording medium. A strip-type image playback device (for example, a DVD player), and in addition to those mentioned above, see Table 2. It may have a display unit 5002, a recording medium reading unit 5011, etc. Figure 28(C) is a Go It is a group-type display, and in addition to the above, it includes a second display unit 5002 and a support unit 5012 It may have earphones 5013, etc. Figure 28(D) is a portable gaming machine, and above In addition to those described above, it may also have a recording medium reading unit 5011, etc. Figure 28(E) It is a digital camera with a television receiving function, and in addition to the above, it has an antenna 5014, It may have a shutter button 5015, an image receiving unit 5016, etc. Figure 28(F) is a portable It is a band-type gaming machine, and in addition to the above, it also has a second display unit 5002 and a recording medium reading unit 5011. , etc. Figure 28(G) is a television receiver, and in addition to the above, It may have a tuner, an image processing unit, etc. Figure 28(H) shows a portable television receiver. It is a device that, in addition to the above-mentioned components, includes a charger 5017 capable of transmitting and receiving signals, etc. This is possible. Figure 29(A) is a display, and in addition to the above, support base 5018, It can have the following. Figure 29(B) is a camera, and in addition to the above, it has external connections. It may have a port 5019, a shutter button 5015, an image receiving unit 5016, etc. Figure 29(C) shows a computer, and in addition to the above, it has a pointing device 5 It may have ports such as 020, an external connection port 5019, a reader / writer 5021, etc. Figure 29(D) shows a mobile phone, and in addition to the above-mentioned components, it includes a transmitter, receiver, and mobile phone / transmitter. It can have a tuner for a 1-segment partial reception service for mobile terminals, etc.

[0294] The electronic devices shown in Figures 28(A) to 28(H) and Figures 29(A) to 29(D) are various It can have various functions. For example, various types of information (still images, videos, text images, etc.) Features include: a display function for the date and time, a touch panel function, and a calendar display. Functions that control processing through various software (programs), wireless communication functions , a function to connect to various computer networks using wireless communication, wireless communication function A function that uses this to send or receive various types of data, and a program recorded on a recording medium. Alternatively, it may have a function to read data and display it on the display unit, etc. Furthermore, multiple In electronic devices having a display unit, one display unit is primarily used to display image information, and another... A function that primarily displays text information on one display unit, or a function that takes parallax into consideration for multiple display units. It can have functions such as displaying three-dimensional images by displaying a single image. In electronic devices having an image receiving unit, functions for taking still images, functions for taking videos, and Functions to automatically or manually correct shadowed images, and to record captured images on a recording medium (external or camera). It can have functions such as saving to a built-in storage unit, displaying captured images on the display unit, etc. Furthermore, the electronic devices shown in Figures 28(A) to 28(H) and Figures 29(A) to 29(D) The functions that a vessel can possess are not limited to these; it can have a variety of functions.

[0295] The electronic device described in this embodiment has a display unit for displaying some kind of information. It is characterized by the following.

[0296] Next, we will explain some application examples of display devices.

[0297] Figure 29(E) shows an example of a display device being installed as an integral part of a building. ) consists of a housing 5022, a display unit 5023, a remote control device 5024 which is the operating unit, and a speaker 5 Includes 025, etc. The display device is wall-mounted and integrated with the building, and the installation space is It can be installed without requiring a large area.

[0298] Figure 29(F) shows another example in which a display device is installed within a building and integrated with the building itself. The display module 5026 is installed together with the unit bath 5027. Bathers will be able to view the display module 5026.

[0299] In this embodiment, walls and a unit bathroom were used as examples of buildings, but in this embodiment... The form is not limited to this, and display devices can be installed in various types of buildings.

[0300] Next, we will show an example in which the display device is integrated with the mobile unit.

[0301] Figure 29(G) shows an example of a display device installed in an automobile. Display module The wire 5028 is attached to the vehicle body 5029 and controls the operation of the vehicle body or the inside and outside of the vehicle. Information entered from the system can be displayed on demand. Note that the navigation function... It may have.

[0302] Figure 29(H) shows an example in which the display device is integrated with a passenger aircraft. Yes. Figure 29(H) shows a display module 503 on the ceiling 5030 above the seats of a passenger aircraft. This diagram shows the shape when in use with 1 installed. The display module 5031 is It is attached integrally with the ceiling 5030 via the hinge portion 5032, and the hinge portion 5032 The expansion and contraction of the display module 5031 allows passengers to view the display module 503. Item 1 has the function of displaying information through operation by passengers.

[0303] In addition, in this embodiment, examples of the moving body include an automobile body and an aircraft body but are not limited thereto, and can be installed on various things such as motorcycles, four-wheeled vehicles (including automobiles, buses, etc.), trains (including monorails, railways, etc.), ships, and the like.

[0304] In addition, in this specification and the like, in the drawings or sentences described in a certain embodiment, it is possible to extract a part thereof to constitute an aspect of the invention. Therefore, when a drawing or sentence describing a certain part is described, the content obtained by extracting a part of the drawing or sentence thereof is also disclosed as an aspect of the invention and is assumed to be able to constitute an aspect of the invention. Therefore, for example, in a drawing or sentence in which a single or plural number of active elements (such as transistors, diodes, etc.), wirings, passive elements (such as capacitive elements, resistive elements, etc.), conductive layers, insulating layers, semiconductor layers, organic materials, inorganic materials, parts, devices, operation methods, manufacturing methods, etc. are described, it is assumed that it is possible to extract a part thereof to constitute an aspect of the invention. For example, from a circuit diagram composed of N (N is an integer) circuit elements (such as transistors, capacitive elements, etc.), it is possible to extract M (M is an integer and M < N) circuit elements (such as transistors, capacitive elements, etc.) to constitute an aspect of the invention. As another example, from a cross-sectional view composed of N (N is an integer) layers, it is possible to extract M (M is an integer and M < N) layers to constitute an aspect of the invention. As yet another example, from a flowchart composed of N (N is an integer) elements, it is possible to extract M (M is an integer and M < N ) elements to constitute an aspect of the invention.

[0305] In this specification, etc., the figures or text described in a particular embodiment may differ from the actual figures or text. If at least one specific example is provided, derive the higher-level concept of that specific example. This will be easily understood by those skilled in the art. Therefore, in one embodiment, In any diagram or text, if at least one specific example is described, the higher level of that specific example... Concepts are also disclosed as one aspect of the invention, and constitute one aspect of the invention. It is possible.

[0306] Furthermore, in this specification, etc., at least the contents shown in the figure (or even just a part of the figure) This is disclosed as one aspect of the invention and can constitute one aspect of the invention. Therefore, if a certain content is described in a diagram, it can be described using text. Even if it is not disclosed, the content is disclosed as one aspect of the invention, and one aspect of the invention It is possible to construct it. Similarly, a diagram showing a part of the figure is also one embodiment of the invention. This is disclosed as such, and it can constitute one aspect of the invention.

[0307] The configurations shown in this embodiment may be combined with the configurations shown in other embodiments as appropriate. It can be used.

[0308] (Embodiment 9) In this embodiment, an example of a semiconductor device having the transistor shown in the above embodiment is used. Next, we will explain a radiation image detection device capable of acquiring medical radiation images. Planar radiation image detection devices that can directly convert data into digital data are generally flat It is called a panel detector (Flat Panel Detector; FPD).

[0309] As shown in Figure 31(A), the radiation image detection device 3601 is used when taking radiation images. It is installed on platform 3603, and is irradiated from radiation source 3605. The radiation passes through the subject 3609 and reaches the radiation image detection device 3601. Device 3601 detects radiation 3607 that has passed through the object 3609 using a radiation detection element. This allows you to obtain image data. Radiation that can be detected by the radiation image detection device 3601 Examples of radiation types 3607 include X-rays and gamma rays.

[0310] Figure 31(B) shows a block diagram of the radiation image detection device 3601. 3601 is a sensor array 3613 in which pixels 3611 are arranged in a matrix, and a gate It includes a line drive circuit 3615, a signal detection circuit 3617, and an A / D conversion circuit 3619. Note that the radiation image detection device 3601 uses a CPU (Central Processor) which is not shown in the diagram. ssing Unit), ROM (Read Only Memory), RAM (Ra It is controlled by (ndom Access Memory), etc. Also, radiographic imaging The output device 3601 is a correction circuit that corrects the data output from the A / D conversion circuit 3619. The A / D conversion circuit 3619 may have a storage device or the like for storing the data output from it.

[0311] Pixel 3611 includes a radiation detection element 3621, a capacitive element 3623, and a transistor 36 It consists of 25. Radiation energy is detected directly or indirectly in the radiation detection element 3621. It converts the - into an electric charge and stores the charge in the capacitive element 3623. By switching 3625, the charge accumulated in the capacitive element 3623 is transferred to the pixel 3611. By reading it out as an electrical signal, the output device 3631 can acquire a radiographic image. Cut.

[0312] The radiation detection element 3621 has a pair of electrodes and a conversion layer provided between the pair of electrodes. One of the pair of electrodes is connected to the power supply unit 3633. The other of the pair of electrodes is connected to a capacitor. The first electrode of element 3623 and the source electrode and drain electrode of transistor 3625 The second electrode of the capacitive element 3623 is connected to a common electrode which is at ground potential. The source electrode and the other drain electrode of transistor 3625 receive signals via the signal line DL. It is connected to the detection circuit 3617. The gate of transistor 3625 is via scan line GL. It is connected to the wire drive circuit 3615.

[0313] Next, the method for detecting radiation will be explained. From the power supply unit 3633 to the radiation detection element 36 With a voltage applied to the first electrode of 21, radiation is incident on the radiation detection element 3621. Then, the radiation detection element 3621 converts the radiation energy into electric charge, and the amount of incident radiation A corresponding charge is accumulated in the capacitive element 3623. Next, the gate line drive circuit 3615 By inputting a signal to scan line GL and sequentially turning on transistor 3625, the capacitive element The charge accumulated in child 3623 is transmitted to the signal detection circuit 3617 via signal line DL as an analog signal. It is output as follows. In the signal detection circuit 3617, after amplifying the analog signal, A / D In the conversion circuit 3619, A / D conversion is performed and a digital signal is generated. Digital signal However, the output is sent to an output device 3631 such as a display device, and the radiation image is displayed in the output device 3631. It will be displayed.

[0314] The radiation image detection device 3601 and the output device 3631 can be connected by a cable. Furthermore, a transmitting and receiving circuit is provided in both the radiation image detection device 3601 and the output device 3631. The image detected by the radiation image detection device 3601 is wirelessly output to the output device 3631. It is possible.

[0315] Radiation image detection devices include direct conversion type and indirect conversion type. The radiation detection element 3621 included in the image detection device uses a photoconductive material to detect radiation energy It directly converts to electric charge. A radiation detection element 3 included in an indirect conversion type radiation image detection device. 621 converts radiation energy into light using a fluorescent material, and this light is then used as a photodiode or similar light source. It is converted into electric charge using an electrical conversion element.

[0316] Next, the structure of each radiation detection element will be explained using Figure 32.

[0317] Figure 32(A) shows a cross-sectional view of a pixel in a radiation image detection device that uses a direct conversion method. Here, we will use X-rays as an example of radiation for the explanation.

[0318] On the substrate 3641, the transistor 3625 and the capacitive element 3623 shown in the above embodiment are placed. , and a radiation detection element 3621 is provided. The radiation detection element 3621 is a conductive film 36 It consists of 43, a conversion layer 3645, and a conductive film 3647. The conductive film 3643 connected to one of the electrode and drain electrode is a radiation detection element 3621 It functions as an electrode and an electrode for the capacitive element 3623.

[0319] The conductive film 3643 is a transparent conductive film that functions as a pixel electrode as shown in the above embodiment. Similar materials to those used for the film can be used as appropriate.

[0320] The conversion layer 3645 is formed using a material that absorbs radiation and generates an electric charge. Materials capable of absorbing radioactive materials and generating electric charge include amorphous selenium and lead iodide. Examples include mercury iodide, gallium arsenide, CdTe, and CdZn.

[0321] The conductive film 3647 is used for the gate electrode, source electrode, and drain electrode of transistor 3625. The electrodes and materials similar to those used for conductive film 3643 can be used as appropriate.

[0322] When a voltage is applied to the conductive film 3647, radiation is incident on the radiation detection element 3621. Then, charges (electrons and holes) are excited in the conversion layer 3645. These charges are then transferred to the conductive film According to the polarity of the voltage applied to 3647, it moves to the conductive film 3643 and to the capacitive element 3623. It stores energy.

[0323] The radiation detection element 3621 used in a direct conversion type radiation image detection device has a conductive film 364 By applying a high voltage to 7, it is possible to increase the linearity of the charge generated in the conversion layer 3645. As a result, the transfer of charge to radiation detection elements provided in adjacent pixels is reduced. As a result, it is possible to increase the resolution of the radiation image detection device.

[0324] Figure 32(B) shows a cross-sectional view of a pixel in a radiation image detection device using an indirect conversion method. .

[0325] On the substrate 3641, the transistor 3625 and the capacitive element 3623 shown in the above embodiment are placed. , and a radiation detection element 3621 is provided. Also, a thin A phosphor layer 3657, such as a tilator, is provided.

[0326] The radiation detection element 3621 consists of a conductive film 3651, a conversion layer 3653, and a conductive film 3655. The configured photodiode can be used. Source electrode of transistor 3625 And the conductive film 3651 connected to one of the drain electrodes is the electrode of the radiation detection element 3621 and It functions as an electrode for the capacitive element 3623.

[0327] The conductive film 3651 is a transparent conductive film that functions as a pixel electrode as shown in the above embodiment. Similar materials to those used for the film can be used as appropriate.

[0328] The conversion layer 3653 is formed using a material that absorbs light and generates an electric charge. Materials capable of generating electric charge include inorganic semiconductor materials such as silicon, and quinacrylamide. These include organic compounds such as don and phthalocyanine. Furthermore, the conversion layer 3653 is pn-type and pi-type. It is preferable to form an n-type junction. Also, amorphous silicon is used as the conversion layer 3653. When formed using this method, the visible light emitted by the phosphor layer 3657 can be detected with high sensitivity. Therefore, it is preferable.

[0329] The conductive film 3655 can be formed using the same material as the conductive film 3643.

[0330] The phosphor layer 3657 absorbs radiation energy when radiation is incident on it. It is formed using a material that emits visible light. It absorbs radiation energy and emits visible light. Possible materials include cesium iodide, cesium iodide with added thallium, and GOS( Examples include Gd2O2S:Tb) and sodium iodide with added thallium. Note that phosphors For layer 3657, columnar crystals grown in a direction connecting the radiation incident surface and the light emission surface are used. This allows for the suppression of lateral diffusion of light generated in the phosphor layer 3657. As a result, it is possible to increase the resolution of the radiation image detection device.

[0331] Furthermore, in order to prevent conductivity between conductive film 3651 and conductive film 3655, conductive film 3651 and conversion An insulating film 3652 is provided on layer 3653. Also, conductive film 3655 and insulating film 3652 By providing an insulating film 3654 on top, impurities from the outside diffuse into the conversion layer 3653. This can prevent it.

[0332] The phosphor layer 3657 absorbs incident radiation and emits visible light. When visible light is incident on the conversion layer 3653 with a voltage (reverse bias) applied, the Charges (electrons and holes) are excited in the conversion layer 3653. These charges are then transferred to the conductive film 3651. It moves to the next location and is stored in the capacitive element 3623.

[0333] The radiation detection element 3621 used in an indirect conversion type radiation image detection device has a phosphor layer 36 To detect the visible light converted in 57, a mark is made on the conductive film 3655 of the radiation detection element 3621. It is possible to lower the applied voltage.

[0334] In this explanation, we will use the radiation image detection device 3601 installed on platform 3603. As explained, it can be used as a cassette-type radiation image detection device as appropriate. Cut.

[0335] The configurations shown in this embodiment may be combined with the configurations shown in other embodiments as appropriate. It can be used. [Examples]

[0336] In this embodiment, the conductive layer (hereinafter referred to as the first conductive layer) is formed in the same process as the gate electrode. ) and a conductive layer formed in the same process as the source electrode and drain electrode (hereinafter referred to as the second conductive layer) By changing the configuration of the interlayer between the first conductive layer and the second conductive layer, The dielectric breakdown voltage of the interlayer film was evaluated.

[0337] First, the evaluation TEG (Test Element Group) pattern used in this embodiment The concept of "n" will be explained using Figure 33.

[0338] Figure 33(A) shows a top view of the evaluation TEG, and Figure 33(B) shows the same view as Figure 33(A). This is a cross-sectional view corresponding to the cross-sections along the dashed lines X6-Y6 and X7-Y7 shown.

[0339] The evaluation TEG of this embodiment includes a first conductive layer 504a formed on a substrate 502, and a first An interlayer film 506 formed on the conductive layer 504a, and a second conductive layer formed on the interlayer film 506 The conductive layer 510a, the insulating layer 512 formed on the second conductive layer 510a, and the insulating layer 512 It has an insulating layer 514 formed thereon.

[0340] Furthermore, the evaluation TEG includes a first measurement pad 504b connected to the first conductive layer 504a, The first measuring pad has a second measuring pad 510b connected to a second conductive layer 510a. D 504b is an opening where the upper interlayer film 506 and a portion of the insulating layers 512 and 514 have been removed. It has part 520. The second measuring pad 510b has upper insulating layers 512, 514 It has an opening 522 from which part has been removed. First measuring pad 504b and second measuring pad By applying a voltage to 510b, a layer is formed between the conductive layer 504a and the conductive layer 510a. The breakdown voltage of the interstitial film 506 can be measured.

[0341] Furthermore, the size of the region where the first conductive layer 504a and the second conductive layer 510a intersect is defined as follows: The size was set to 10 μm × 10 μm. The measuring instrument used was a Picore from Keithley. A meter (Model 6487) was used. The measurement conditions were as follows: applied voltage from 0V to + The voltage was boosted up to 500V in 10V steps.

[0342] In this embodiment, sample 1 and sample 2 were prepared using different materials for the interlayer film 506. It was made.

[0343] (Sample 1) The interlayer film 506 of sample 1 consists of two layers: a silicon nitride film and a silicon oxide nitride film. A layered structure was adopted.

[0344] (Sample 2) The interlayer film 506 in sample 2 consists of a silicon nitride film, a silicon oxide nitride film, and an oxide semiconductor film. A four-layer laminated structure consisting of a conductive film and an oxide film was adopted.

[0345] In other words, compared to sample 1, sample 2 has a structure in which oxide semiconductor films and oxide films are stacked. The film formation conditions for each film used in Sample 1 and Sample 2 are shown below.

[0346] (Silicon nitride film) As the silicon nitride film, three silicon nitride films with different conditions were stacked. The deposition conditions for the recon film are: Power (RF) = 2000W, Pressure = 100Pa, SiH4 The ratio of N2 / NH3 was set to 200 / 2000 / 100 sccm, and the film thickness was set to 50 nm. The conditions for forming the silicon film are: Power (RF) = 2000W, Pressure = 100Pa, Si The ratio of H4 / N2 / NH3 was set to 200 / 2000 / 2000 sccm, and the film thickness was set to 300 nm. The deposition conditions for the third silicon nitride film were: Power (RF) = 2000W, Pressure = 100P. a. SiH4 / N2 = 200 / 5000 sccm, film thickness = 50 nm. Note that the first no The first three silicon nitride films were all deposited using a PE-CVD apparatus at a substrate temperature of 350°C. did.

[0347] (Silicon oxide nitride film) The deposition conditions for silicon oxidizride films are: power (RF) = 100W, pressure = 100Pa. The SiH4 / N2O ratio was set to 20 / 3000 sccm, and the film thickness was set to 50 nm. The silicon film was deposited using a PE-CVD apparatus at a substrate temperature of 350°C.

[0348] (Oxide semiconductor film) As the oxide semiconductor film, a target with a composition of In:Ga:Zn=1:1:1 is used. The film was deposited by sputtering. The deposition conditions were: power (AC) = 5kW, pressure = 0 .6Pa, Ar / O2=100 / 100sccm (O2=50%), substrate temperature=170℃ The film thickness was set to 35 nm.

[0349] (Oxide film) As the oxide film, a target with the composition In:Ga:Zn=1:3:2 is used, spa The film was deposited using the taring method. The deposition conditions were: power (AC) = 5kW, pressure = 0.6P. a, Ar / O2 = 270 / 30 sccm (O2 = 10%), substrate temperature = 170℃, film thickness = The nm was set to 20nm.

[0350] Note that both Sample 1 and Sample 2 were subjected to a nitrogen atmosphere at 450°C before the formation of the insulating layer 512. After a 1-hour heat treatment, a further 1-hour heat treatment at 450°C in a nitrogen-oxygen mixed atmosphere is performed. went.

[0351] Figure 34 shows the dielectric breakdown voltage of the interlayer film 506 of sample 1 and sample 2. The vertical axis represents voltage, and the vertical axis represents current. Also, in Figure 34, the solid line 551 represents sample 1. The measurement results are shown, with the dashed line 552 indicating the measurement results for sample 2.

[0352] In sample 1 and sample 2, for example, 1.0 × 10 -6 When a current greater than A flows, Assuming that the interlayer film 506 has broken down, in sample 1, the interlayer film 50 at around 330V 6 is broken. On the other hand, in sample 2, the interlayer film 506 is broken at around 420V. ru.

[0353] As shown in this embodiment, the interlayer film between the first conductive layer 504a and the second conductive layer 510a By changing the structure, or the distance between the first conductive layer 504a and the second conductive layer 510a It was confirmed that the dielectric breakdown voltages were different. [Explanation of Symbols]

[0354] 100 display device 102 pixel section 104 Drive circuit section 104a Gate Driver 104b Source Driver 106 Protection circuit 107 Terminal section 108 Pixel Circuit Section 110 Wiring 111 Pixel Circuit 112 transistors 114 transistors 116 Wiring 118 Wiring 120 Wiring 122 Wiring 124 Wiring 126 Wiring 128 transistors 130 transistors 131_1 Transistor 131_2 Transistor 131_3 Transistor 132 transistors 133_1 Capacitive element 133_2 Capacitive element 134 transistors 135 Light-emitting element 206 Protection circuit 208 Wiring 212 transistors 214 transistors 216 transistors 218 transistors 220 transistor group 222 transistor group 224 Wiring 226 Wiring 302 circuit board 304a conductive layer 304b conductive layer 304c conductive layer 304d conductive layer 304e conductive layer 305 Insulating layer 306 Insulating layer 307 Semiconductor layer 308a Semiconductor layer 308b Semiconductor layer 308c semiconductor layer 308d semiconductor layer 309 Conductive layer 310a conductive layer 310b conductive layer 310c conductive layer 310d conductive layer 310e conductive layer 310f conductive layer 310g conductive layer 311 Insulating layer 312 Insulating layer 313 Insulating layer 314 Insulating layer 315 Conductive layer 316a conductive layer 316b conductive layer 316c conductive layer 318 Alignment film 320 liquid crystal layers 322 liquid crystal elements 342 circuit boards 344 Light blocking layer 346 colored layer 348 Insulating layer 350 conductive layer 352 Alignment film 360 Electrostatic Disruption Induction Area 362 Guard Ring 362a Electrostatic discharge induction area 370 Insulating layer 372a opening 372b opening 374a opening 374b opening 374c opening 374d opening 374e opening 380 areas 382 areas 390 Oxide Layer 390a Oxide Semiconductor Layer 390b Oxide layer 392 n-type region 402 circuit board 404 Conductive layer 405 Insulating layer 406 Insulating layer 410 Conductive layer 412 Insulating layer 414 Insulating layer 416 Conductive layer 474a Opening 474b Opening 502 circuit board 504a conductive layer 504b Measuring Pad 506 Interlaminar 510a conductive layer 510b Measuring Pad 512 Insulating layer 514 Insulating layer 520 opening 522 Opening 551 Solid line 552 Dashed line 3601 Radiation Image Detection Device 3603 units 3605 Radiation source 3607 Radiation 3609 Subject 3611 pixels 3613 Sensor Array 3615 Gate wire drive circuit 3617 Signal detection circuit 3619 A / D conversion circuit 3621 Radiation detection element 3623 Capacitive element 3625 Transistors 3631 Output device 3633 Power Supply 3641 circuit board 3643 Conductive film 3645 Conversion Layer 3647 Conductive film 3651 Conductive film 3652 Insulating film 3653 Conversion Layer 3654 Insulating film 3655 Conductive film 3657 Phosphor layer 4500 touch sensors 4510 Conductive layer 4510a conductive layer 4510b Conductive layer 4510c conductive layer 4520 Conductive layer 4540 capacity 4710 Electrode 4810 Insulating layer 4820 Insulating layer 4910 circuit board 4920 circuit board 5000 cabinets 5001 Display section 5002 Display section 5003 Speaker 5004 LED Lamp 5005 Operation Keys 5006 Connection terminal 5007 Sensor 5008 Microphone 5009 Switch 5010 Infrared Port 5011 Recording medium reading unit 5012 Support part 5013 Earphones 5014 Antenna 5015 Shutter button 5016 Image receiving unit 5017 charger 5018 Support stand 5019 External connection port 5020 Pointing Device 5021 Leader / Writer 5022 enclosure 5023 Display section 5024 Remote control device 5025 Speaker 5026 Display Module 5027 Unit Bathroom 5028 Display Module 5029 Car body 5030 Ceiling 5031 Display Module 5032 Hinge section 8000 Display Module 8001 Top cover 8002 Lower cover 8003 FPC 8004 Touch Panel 8005 FPC 8006 Display Panel 8007 Backlight Unit 8008 light source 8009 Frame 8010 Printed Circuit Board 8011 Battery

Claims

1. A display device having a scanning line driving circuit, The aforementioned scanning line drive circuit is In a plan view, the first conductive film has a first region, a second region, and a third region that branch off from a trunk region, In a plan view, the second conductive film has a fourth region, a fifth region, a sixth region, and a seventh region that branch off from a main region, The first oxide semiconductor film, A second oxide semiconductor film, It has, In a plan view, the first region, the second region, and the third region are each arranged to extend along the first direction. In a plan view, the fourth region, the fifth region, the sixth region, and the seventh region are each arranged to extend along a second direction opposite to the first direction. In a plan view, the first region is positioned between the fourth region and the fifth region, with a gap between them and the fourth and fifth regions, respectively. In a plan view, the second region is positioned between the fifth region and the sixth region, with a gap between them and the fifth and sixth regions, respectively. In a plan view, the third region is positioned between the sixth region and the seventh region, with a gap between them and the sixth and seventh regions, respectively. In a plan view, the first oxide semiconductor film is arranged to extend along a third direction intersecting the first and second directions, In a plan view, the second oxide semiconductor film is positioned at a distance from the first oxide semiconductor film and extends along the third direction. The source and drain of the first transistor are located in the fourth region. The source and drain of the first transistor are located in the first region. The source and drain of the second transistor are located in the first region. The source and drain of the second transistor are located in the fifth region. The source and drain of the third transistor are located in the fifth region. The source and drain of the third transistor are located in the second region. The source and drain of the fourth transistor are located in the second region. The source and drain of the fourth transistor are located in the sixth region. The source and drain of the fifth transistor are located in the sixth region. The source and drain of the fifth transistor are located in the third region. The source and drain of the sixth transistor are located in the third region. The source and drain of the sixth transistor are located in the seventh region. The source and drain of the seventh transistor are located in the fourth region. The source and drain of the seventh transistor are located in the first region. The source and drain of the eighth transistor are located in the first region. The source and drain of the eighth transistor are located in the fifth region. The source and drain of the ninth transistor are located in the fifth region. The source and drain of the ninth transistor are located in the second region. The source and drain of the tenth transistor are located in the second region. The source and drain of the 10th transistor are located in the 6th region. The source and drain of the eleventh transistor are located in the sixth region. The source and drain of the 11th transistor are located in the third region. The source and drain of the twelfth transistor are located in the third region. The source and the other drain of the 12th transistor are located in the 7th region. The channel formation regions of the first to sixth transistors are each located on the first oxide semiconductor film. A display device in which the channel-forming regions of the seventh to twelfth transistors are each located in the second oxide semiconductor film.

2. A display device having a scanning line driving circuit, The aforementioned scanning line drive circuit is In a plan view, the first conductive film has a first region, a second region, and a third region that branch off from a trunk region, In a plan view, the second conductive film has a fourth region, a fifth region, a sixth region, and a seventh region that branch off from a main region, The first oxide semiconductor film, A second oxide semiconductor film, It has, In a plan view, the first region, the second region, and the third region are each arranged to extend along the first direction. In a plan view, the fourth region, the fifth region, the sixth region, and the seventh region are each arranged to extend along a second direction opposite to the first direction. In a plan view, the first region is positioned between the fourth region and the fifth region, with a gap between them and the fourth and fifth regions, respectively. In a plan view, the second region is positioned between the fifth region and the sixth region, with a gap between them and the fifth and sixth regions, respectively. In a plan view, the third region is positioned between the sixth region and the seventh region, with a gap between them and the sixth and seventh regions, respectively. In a plan view, the first oxide semiconductor film is arranged to extend along a third direction intersecting the first and second directions, In a plan view, the second oxide semiconductor film is positioned at a distance from the first oxide semiconductor film and extends along the third direction. The source and drain of the first transistor are located in the fourth region. The source and drain of the first transistor are located in the first region. An eighth region of the first oxide semiconductor film is positioned between the source and drain of the first transistor. The source and drain of the second transistor are located in the first region. The source and drain of the second transistor are located in the fifth region. A ninth region of the first oxide semiconductor film is positioned between the source and drain of the second transistor. The source and drain of the third transistor are located in the fifth region. The source and drain of the third transistor are located in the second region. A tenth region of the first oxide semiconductor film is positioned between the source and drain of the third transistor. The source and drain of the fourth transistor are located in the second region. The source and drain of the fourth transistor are located in the sixth region. The eleventh region of the first oxide semiconductor film is positioned between the source and drain of the fourth transistor. The source and drain of the fifth transistor are located in the sixth region. The source and drain of the fifth transistor are located in the third region. A twelfth region of the second oxide semiconductor film is positioned between the source and drain of the fifth transistor. The source and drain of the sixth transistor are located in the third region. The source and drain of the sixth transistor are located in the seventh region. A thirteenth region of the second oxide semiconductor film is positioned between the source and drain of the sixth transistor. The source and drain of the seventh transistor are located in the fourth region. The source and drain of the seventh transistor are located in the first region. A 14th region of the second oxide semiconductor film is positioned between the source and drain of the seventh transistor. The source and drain of the eighth transistor are located in the first region. The source and drain of the eighth transistor are located in the fifth region. A 15th region of the second oxide semiconductor film is positioned between the source and drain of the eighth transistor. The source and drain of the ninth transistor are located in the fifth region. The source and drain of the ninth transistor are located in the second region. A 16th region of the first oxide semiconductor film is positioned between the source and drain of the 9th transistor. The source and drain of the tenth transistor are located in the second region. The source and drain of the 10th transistor are located in the 6th region. A 17th region of the first oxide semiconductor film is positioned between the source and drain of the 10th transistor. The source and drain of the eleventh transistor are located in the sixth region. The source and drain of the 11th transistor are located in the third region. The 18th region of the second oxide semiconductor film is positioned between the source and drain of the 11th transistor. The source and drain of the twelfth transistor are located in the third region. The source and the other drain of the 12th transistor are located in the 7th region. A display device in which a 19th region of the second oxide semiconductor film is positioned between the source and drain of the 12th transistor.

3. In claim 1 or claim 2, It has a third conductive film, A display device in which the gates of the first to twelfth transistors are each placed in the third conductive film.

4. In any one of claims 1 to 3, A display device wherein the first oxide semiconductor film and the second oxide semiconductor film each contain In, Zn, and M (where M is Al, Ti, Ga, Y, Zr, La, Ce, Nd, or Hf).

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