Loop counting circuit

Abstract

This provides a pseudo-random binary sequence (PRBS) cycle counting circuit with minimal error. [Solution] The lap counting circuit 2 is 2 k It has a period of -1 bits and counts the cycles of the bit sequence output every n bits. The first counter 21 is a (p+1)-base counter (p is 2) while it receives the first and second level selection signals. k The (p+1)-ary counter 22 operates as a division (quotient of a division with -1 as the dividend and n as the divisor) and a p-ary counter, counting the clock to obtain the first count value, and outputs a third-level first signal when the first count value becomes p and p-1 respectively while operating as a (p+1)-ary counter and a p-ary counter. The second counter 23 counts the third level of the first signal. The n-ary counter 22 counts the third level of the first signal. The comparator circuit 24 outputs a first-level selection signal while the third count value is less than r (where r is the remainder of the division), and outputs a second-level selection signal while the third count value is r or greater.

Description

[Technical Field]

[0001] The embodiments generally relate to a loop counting circuit. [Background technology]

[0002] Communication devices may include a pseudo-random binary sequence (PRBS) generation circuit to achieve purposes including the measurement and calibration of certain indicators. An example of an indicator is the bit error rate of the communication device, and an example of something to be calibrated is the coefficient of a waveform equalizer built into the communication device. The PRBS has a period determined by the mechanism of PRBS generation; that is, the same PRBS is generated every period. During the measurement and / or calibration process, the number of cycles is counted. A cycle counting circuit for counting the number of cycles may also be built into the communication device. [Prior art documents] [Patent Documents]

[0003] [Patent Document 1] U.S. Patent No. 10,884,706 [Patent Document 2] U.S. Patent Application Publication No. 2024 / 061590 [Non-patent literature]

[0004] [Non-Patent Document 1] Donald E. Knuth, "The Art of Computer Programming Volume 2 Seminumerical Algorithms Third Edition (Japanese Version)," Chapter 3. [Overview of the Initiative] [Problems that the invention aims to solve]

[0005] This invention provides a lap counting circuit that can count laps with less error. [Means for solving the problem]

[0006] A lap counter circuit according to one embodiment outputs based on the clock and 2 k The system includes a first counter, a second counter, an n-ary counter, and a comparator circuit, and counts the cycles of a bit sequence that has a period of -1 bits (where k is a positive integer) and is output every n bits (where n is a positive integer). The first counter, while receiving a first-level selection signal, is a (p+1)-ary counter (where p is 2 k The (p+1) counter operates as the quotient of a division operation with -1 as the dividend and n as the divisor. While receiving the second level selection signal, it operates as a p-adic counter, counting the clock to obtain the first count value. While operating as a (p+1)-adic counter, it outputs the first signal of the third level when the first count value becomes p, and when operating as a p-adic counter, it outputs the first signal of the third level. The second counter counts the third level of the first signal to obtain the second count value and outputs the first bit sequence indicating the second count value. The n-adic counter counts the third level of the first signal to obtain the third count value and outputs the second bit sequence indicating the third count value. The comparator circuit outputs the first level selection signal while the third count value is less than r (where r is the remainder of the division), and outputs the second level selection signal while the third count value is r or greater. [Brief explanation of the drawing]

[0007] [Figure 1] Figure 1 is a block diagram of a system including a perimeter counting circuit according to the first embodiment. [Figure 2] Figure 2 is a block diagram of the perimeter counting circuit and PRBS generation circuit of the first embodiment. [Figure 3] Figure 3 shows an example of a generated PRBS. [Figure 4] Figure 4 shows the change in the error of the lap count using the first type method for comparison and reference with the first embodiment. [Figure 5]FIG. 5 is a block diagram of the cycle counting circuit and the PRBS generation circuit according to the second embodiment. [Figure 6] FIG. 6 is a block diagram of the cycle counting circuit and the PRBS generation circuit according to the third embodiment. [Figure 7] FIG. 7 is a block diagram of the cycle counting circuit and the PRBS generation circuit according to the fourth embodiment. [Figure 8] FIG. 8 is a block diagram of the cycle counting circuit and the PRBS generation circuit according to the fifth embodiment. [Figure 9] FIG. 9 is a block diagram of the cycle counting circuit and the PRBS generation circuit according to the sixth embodiment. [Figure 10] FIG. 10 is a block diagram of the cycle counting circuit and the PRBS generation circuit according to the seventh embodiment. BEST MODE FOR CARRYING OUT THE INVENTION

[0008] Embodiments will be described below with reference to the drawings. In order to distinguish a plurality of components having substantially the same functions and configurations in one embodiment or different embodiments, additional numbers or characters may be added to the end of the reference numerals. In the embodiments following a described embodiment, the differences from the described embodiment are mainly described. The description of any embodiment applies also as the description of another embodiment unless explicitly or implicitly excluded.

[0009] In this specification and the claims, the statement that a first element is "connected to" a second element includes that the first element is connected to the second element directly or via an element that is always or selectively conductive.

[0010] 1. First Embodiment 1.1. Configuration FIG. 1 is a block diagram of a system including the cycle counting circuit according to the first embodiment. The system 100 may be included in a communication device. As shown in FIG. **********1, the system 100 includes a PRBS generation circuit 1, a cycle counting circuit 2, and a control circuit 3.

[0011] The control circuit 3 controls the PRBS generation circuit 1. The control circuit 3 outputs a clock CK and a reset signal RN.

[0012] The PRBS generation circuit 1 is a circuit that generates a PRBS. The PRBS generation circuit 1 is of a parallel type and outputs an n-bit PRBS. The n-bit PRBS mentioned here is the PRBS of a binary sequence segmented every n bits. It is known that the PRBS generation circuit includes a serial type and a parallel type. The serial type PRBS generation circuit outputs a 1-bit PRBS in synchronization with the edge of the clock (for example, rising edge). The parallel type PRBS generation circuit 1 outputs an n-bit PRBS in synchronization with the edge of the clock (for example, rising edge).

[0013] The method or algorithm for generating the PRBS may be of any kind. In one example, the PRBS generation circuit 1 is a Linear Feedback Shift Register (LFSR). In another example, the PRBS generation circuit 1 uses the Lagged Fibonacci method, the method described in Patent Document 1, the method described in Non-Patent Document 1, Xorshift, the method described in Patent Document 2, or the Mersenne Twister method to generate the PRBS.

[0014] The cycle counting circuit 2 is a circuit that counts the number of cycles of the PRBS, that is, how many cycles of the PRBS have been generated by the PRBS generation circuit 1. Unlike a completely random signal, the PRBS has a fixed period, and the same bit pattern is repeated each time a cycle has elapsed. The period of the PRBS itself does not change whether the generation method is series or parallel. However, generally, the period of the PRBS is not a multiple of the bit width used in the parallel generation method, i.e., the above n. In the case of a series type, for example, the PRBS period can be measured by counting the clock used for generation, and the number of cycles can be determined from the measurement result. In contrast, in the parallel type, even if the clock used for generation is counted, the PRBS period can only be measured in multiples of n, so ingenuity is required to determine the number of cycles.

[0015] Figure 2 is a block diagram of the circuit counting circuit and PRBS generation circuit of the first embodiment. As described above with reference to Figure 1, the PRBS generation circuit 1 may generate PRBS using any method or algorithm. In one example, the PRBS generation circuit 1 includes a register 11 and a feedback logic circuit 12. The following description is based on this example.

[0016] Register 11 is a circuit that temporarily stores an n-bit bit sequence, where n is a positive integer. Register 11 has n input terminals FI <n-1:0>n output terminals SO <n-1:0>It has a clock input terminal CK1 and a reset signal input terminal RN1. The notation "terminal α<β:γ>" indicates (β-γ+1) sets of terminals α_γ, α_γ+1, ..., α_β.

[0017] Register 11 stores the bit sequence given as input to it and outputs the stored bit sequence. Register 11 receives a reset signal RN at the reset signal input terminal RN1. When Register 11 receives a reset signal RN at a level that instructs a reset, it resets the stored bit sequence to a predetermined initial value. Register 11 operates as long as it receives a reset signal RN at a level that does not instruct a reset. In one example, a low level of the reset signal RN indicates a reset instruction, and a high level indicates operation. The following description is based on this example.

[0018] Register 11 is the input terminal FI <n-1:0>In each case, bit string DF <n-1:0>The bit strings and bits are transmitted by signals. That is, receiving a bit or a bit string is the same as receiving the signal that transmits the bit or bit string, and outputting a bit or a bit string is the same as outputting the signal that transmits the bit or bit string. The notation "bit string δ<β:γ>" indicates that the bit string δ has a width of (β-γ+1) bits and contains bits δ_γ, δ_γ+1, δ_γ+2, ..., δ_β-1, δ_β. Bit δ_β transmits the most significant (or β-position) bit of the bit string δ<β:γ>. Bit string δ_γ transmits the least significant (or γ-position) bit of the bit string δ<β:γ>. Bit string δ_Z is positioned higher in the bit string δ<β:γ> as Z is larger.

[0019] Register 11 is output terminal SO <n-1:0>In each case, the bit sequence DS held in register 11 <n-1:0>Outputs a bit string DS. <n-1:0>This is the output of the PRBS generation circuit 1, that is, it functions as an n-bit PRBS. The number of bits in the PRBS, i.e., n bits, is defined as one word of the PRBS. The numerical value n may hereafter be referred to as the number of bits n.

[0020] Register 11 receives the clock CK at the clock input terminal CK1. Register 11 synchronizes with the edge (e.g., rising edge) of the clock CK to the bit sequence DS. <n-1:0>Outputs.

[0021] The feedback logic circuit 12 has k input terminals SI <k-1:0>and n output terminals FO <n-1:0>It has k, where k is the period of PRBS, as shown in equation 2. k k is the degree of the power of 2 term contained in -1, and is a positive integer less than n. k is also simply called the degree of PRBS. The feedback logic circuit 12 has an input terminal SI <k-1:0>In each case, bit string DS <n-1:n-k>Receives bit string DS. <n-1:n-k>is a bit string DS <n-1:0>These are k consecutive bits, including the most significant bit. The feedback logic circuit 12 is a bit sequence DS. <n-1:n-k>From, bit string DF <n-1:0>This generates [something]. The method of generation can be anything. That is, the method of generation is based on the method by which the PRBS generation circuit 1 generates PRBS.

[0022] The feedback logic circuit 12 has n output terminals FO <n-1:0>In each case, bit string DF <n-1:0>Outputs.

[0023] The loop counting circuit 2 counts the number of loops of the PRBS. As mentioned above, the period of the PRBS is usually not divisible by n, so the bit string DS, which is the output of the PRBS generation circuit 1, is counted. <n-1:0>After the leading bit of PRBS appears in one of the bits, DS again <n-1:0>When the leading bit of the PRBS appears in any of the bits in the [context] (generally, the bit position is different from the previous time), it is regarded that the PRBS has made one cycle.

[0024] In a serial PRBS generation circuit, the period 2 k ^k - 1 of the k - th order PRBS generated is the same as the number of rising edges of the clock required for its generation. That is, the pattern of 2 k ^k - 1 bits is generated one bit at a time. Therefore, by counting the number of rising edges of the clock CK with a (2 k ^k - 1) - bit counter, the number of cycles can be easily counted. For that purpose, every time the value of the (2 k ^k - 1) - bit counter reaches its maximum, the number of cycles is incremented by 1. Such a method of counting the number of cycles is hereinafter referred to as the first - type method for comparison and reference.

[0025] In the first - type method, the (2 k ^k - 1) - bit counter needs to operate every time the clock rises, and depending on the magnitude of k, the area of the (2 k ^k - 1) - bit counter is large. As the operation of the communication device becomes faster, a modulation method with a long length (run - length) of consecutive 0 or 1 bits in the modulated data is adopted from the perspective of emphasizing transfer efficiency, and in order to ensure the run - length of the corresponding test pattern, k tends to increase. To address this, a second - type method is considered. The PRBS has the property that any consecutive k bits in one cycle do not appear again in the same cycle. When connecting the first and last bits of one cycle of the PRBS to form a ring, any consecutive k bits in this ring are different from any other consecutive k bits. Utilizing this property, in the second - type method, a pattern of a certain k bits (for example, the last - generated k bits) in one cycle of the PRBS is stored in advance as a fixed pattern, and the consecutive k bits of the newly generated PRBS, generated one bit at a time, are stored in a shift register or the like and compared with the above - mentioned fixed pattern. When the consecutive k bits of the newly generated PRBS match the above - mentioned fixed pattern, the number of cycles is incremented by 1.

[0026] However, as described below, in the case of a parallel type such as the PRBS generation circuit 1, if the method used in the serial type is applied, the number of cycles will not be correctly counted. As described above, the parallel type PRBS generation circuit 1 generates the PRBS in n-bit units. When the quotient when dividing the period 2 k -1 by this n is p and the remainder is r, the period of the PRBS is represented by Equation 1. 2 k -1 = np + r (Equation 1) Note that according to the rules of division, Equation 2 holds. 0 ≤ r < n (Equation 2) When counting the period of the generated PRBS using a counter in the same way as the first type method, a (p + 1)-ary counter is used instead of the (2 k -1)-ary counter used in the first type method. This is because if a p-ary counter is used, the number of cycles will increase before the cycle is completed. However, when using a (p + 1)-ary counter, as described below, an error will occur in the cycle counting. FIG. 3 shows an example of a PRBS generated by a certain method in the case of k = 7 and n = 20. In this example, p = 6 and r = 7. FIG. 3 shows from the first clock cycle to the 34th clock cycle. The first clock cycle is the period from when register 11 is reset until the clock CK first rises. Thereafter, the period until the next clock rises is counted as the second clock cycle, the third clock cycle, and so on.

[0027] In the example of FIG. 3, the PRBS generated in n-bit units is generated in order from the least significant bit to the most significant bit. The head of the PRBS in the first clock cycle is the 13th bit. This is because bits 0 to 12 are not input to the feedback logic circuit 12, and no matter what values are set, it will not affect the operation after the second clock cycle, so it can be reset to any value. Usually, bits 0 to 12 are all reset to 0 and treated as a 13-bit delay in the case of generation bit by bit.

[0028] In Figure 3, the clock cycles and bit positions occupied by the beginning of each period of the PRBS are listed as follows: First clock cycle: 13th bit 8th clock cycle: 0th bit 14th clock cycle: 7th bit 20th clock cycle: 14th bit 27th clock cycle: 1st bit 33rd clock cycle: 8th bit In this example, if we count the number of times the PRBS cycles by considering the (p+1) period of the clock CK as one cycle of the PRBS, an error of 13 (=nr) bits occurs with each count. Therefore, the error accumulates with each count, and this increases the difference between the actual number of times the PRBS cycles occur and the number of times the PRBS cycles are counted using the (p+1)-based counter. For example, 10 counts using the (p+1)-based counter result in an error of 130 bits, which is equivalent to one cycle of the PRBS (=2 k -1) exceeds. In the example in Figure 3, the bit width of one word of PRBS is n=20 and its period is 2 k Since -1=127 and are relatively prime, a specific word appears only every 20 cycles of PRBS. Therefore, with the second type of counting, counting can only be performed in units of 20 cycles, and the counting error ranges from 0 to 19. Loop counting circuit 2 addresses the occurrence of such errors.

[0029] Returning to Figure 2, the lap counting circuit 2 includes a (p+1)-adic / p-adic counter 21, an n-adic counter 22, a lap counter 23, and a remainder comparison circuit 24.

[0030] The (p+1)-adic / p-adic counter 21 is a circuit that counts the edges of the supplied clock and outputs a bit sequence indicating the counting result (count value). The (p+1)-adic / p-adic counter 21 has a selection input terminal SELI1, an enable output terminal EO1, a clock input terminal CK2, and a reset signal input terminal RN2.

[0031] The (p+1)-adic / p-adic counter 21 operates as either a (p+1)-adic counter or a p-adic counter, whichever is dynamically selected. The (p+1)-adic / p-adic counter 21 operates as a (p+1)-adic counter while receiving a digital signal at a certain level (e.g., a low level) DSEL at the selection input terminal SELI1. The (p+1)-adic / p-adic counter 21 operates as a p-adic counter while receiving a digital signal at a different level (e.g., a high level) DSEL at the selection input terminal SELI1. In one example, a low level of signal DSEL indicates operation as a (p+1)-adic counter, and a high level indicates operation as a p-adic counter. The following description is based on this example.

[0032] The (p+1)-adic / p-adic counter 21 receives the clock CK at the clock input terminal CK2. The (p+1)-adic / p-adic counter 21 counts the edges (e.g., rising edges) of the received clock CK. While the (p+1)-adic / p-adic counter 21 is operating as a (p+1)-adic counter, its count value is between 0 and p. While the (p+1)-adic / p-adic counter 21 is operating as a p-adic counter, its count value is between 0 and p-1.

[0033] The (p+1)-adic / p-adic counter 21 outputs an enable signal DE1 at the enable output terminal EO1 when the count value reaches its upper limit. That is, while the (p+1)-adic / p-adic counter 21 is operating as a (p+1)-adic counter, when the count value reaches p, it outputs an enable signal DE1 at a level indicating that the count value has reached its upper limit. In one example, the level indicating that the count value has reached its upper limit is a high level. The following description is based on this example. While the (p+1)-adic / p-adic counter 21 is operating as a p-adic counter, when the count value reaches p-1, it outputs a high-level enable signal DE1. When the (p+1)-adic / p-adic counter 21 reaches its upper limit, it resets the count value to 0 at the rising edge of the first clock CK after the count value has reached its upper limit.

[0034] The (p+1)-adv. / p-adv. counter 21 receives a reset signal RN at the reset signal input terminal RN2. When the (p+1)-adv. / p-adv. counter 21 receives a low-level reset signal RN, it resets the count value to 0. The (p+1)-adv. / p-adv. counter 21 continues counting while it receives a high-level reset signal RN.

[0035] The n-ary counter 22 is a circuit that counts the edges of the supplied clock and outputs a bit sequence indicating the count value. The n-ary counter 22 has an enable input terminal EI1 and j output terminals UO <j-1:0>It has a clock input terminal CK3 and a reset signal input terminal RN3.

[0036] The n-ary counter 22 receives the enable signal DE1 at the enable input terminal EI1 and the clock CK at the clock input terminal CK3. The n-ary counter 22 counts the rising edge of the clock CK only while it receives the high-level enable signal DE1. The n-ary counter 22 does not count while it receives the low-level enable signal DE1. The n-ary counter 22 has an output terminal UO <j-1:0>In this case, the bit string DU that indicates the count value <j-1:0>The output is as follows: The count value has a value between 0 and n-1, inclusive. When the n-ary counter 22 reaches its upper limit (i.e., n-1), it resets the count value to 0 at the rising edge of the first clock CK during the period after the count value has reached its upper limit and is receiving a high-level enable signal DE1.

[0037] The n-ary counter 22 receives a reset signal RN at the reset signal input terminal RN3. When the n-ary counter 22 receives a low-level reset signal RN, it resets the count value to 0 regardless of the value of the enable signal DE1. While the n-ary counter 22 receives a high-level reset signal RN, it performs counting based on the value of the enable signal DE1.

[0038] The loop counter 23 is a circuit that counts the edges of the supplied clock and outputs a bit sequence indicating the count value. The loop counter 23 has an enable input terminal EI2 and m output terminals QO <m-1:0>It has a clock input terminal CK4 and a reset signal input terminal RN4.

[0039] The loop counter 23 receives the enable signal DE1 at the enable input terminal EI2 and the clock CK at the clock input terminal CK4. The loop counter 23 counts the rising edge of the clock CK only while it is receiving the high-level enable signal DE1. The loop counter 23 does not count while it is receiving the low-level enable signal DE1. The loop counter 23 has an output terminal QO <m-1:0>In this case, the bit string DQ indicates the count value. <m-1:0>The output is as follows: The count value indicates the number of cycles of the PRBS since the reset signal RN transitioned from a level that signals a reset to a level that does not signal a reset.

[0040] The lap counter 23 receives a reset signal RN at the reset signal input terminal RN4. When the lap counter 23 receives a low-level reset signal RN, it resets the count value to 0 regardless of the value of the enable signal DE1. While the lap counter 23 receives a high-level reset signal RN, it continues counting based on the value of the enable signal DE1.

[0041] The remainder comparison circuit 24 is a circuit that outputs a level signal based on a comparison of bit sequences received at two inputs. The remainder comparison circuit 24 has j input terminals UI <j-1:0>, j input terminals VI <j-1:0>It also has an output terminal SELO.

[0042] The remainder comparison circuit 24 has an input terminal UI <j-1:0>In each case, the bit string DU <j-1:0>It receives. The remainder comparison circuit 24 receives input terminal VI. <j-1:0>In each case, bit string DV <j-1:0>Receive. Bit string DV <j-1:0>This indicates the value of the remainder r. In one example, the bit string DV <j-1:0>It is supplied from control circuit 3.

[0043] The remainder comparison circuit 24 outputs the signal DSEL at the output terminal SELO. The remainder comparison circuit 24 outputs the bit string DU <j-1:0>The value indicated by is bit string DV <j-1:0>The high-level signal DSEL is output while the value is greater than or equal to the value indicated by DU. The remainder comparison circuit 24 outputs the bit string DU <j-1:0>The value indicated by is bit string DV <j-1:0>While the value is less than the value indicated by [the specified parameter], a low-level signal DSEL is output.

[0044] 1.2.Operation In the PRBS loop counting operation by the loop counting circuit 2, the first count is defined as the period from when the count value changes from 0 to 1, and thereafter, each time the count value changes, the count is numbered as the second, third, and so on. Since counting is subject to error, the count does not necessarily coincide with the number of PRBS loops. The loop counting circuit 2 divides the count into groups of n bits in the output word of the PRBS generation circuit 1, and further divides each group of n loops into two sets: the first to the r-th loop and the (r+1)-th to the n-th loop. That is, during the first to the r-th loop of each n counting operation, the (p+1)-adic / p-adic counter 21 functions as a (p+1)-adic counter. During the second to the n-th loop of each n counting operation, the (p+1)-adic / p-adic counter 21 functions as a p-adic counter. Therefore, the (p+1)-adic / p-adic counter 21 alternately repeats r (p+1)-adic counting operations and (nr) p-adic counting operations. Consequently, the number of rising edges of the clock CK during the interval between r (p+1)-adic counting operations and (nr) p-adic counting operations (i.e., during each n counting operation), i.e., the number of words w in PRBS, is expressed by equation 3. w = (p+1)r + p(nr) = np + r (Equation 3) Therefore, the total number of bits in the PRBS output during n counting cycles is the product of w and n, and is expressed by equation 4. nw = n(np + r) (Equation 4) This number nw is n times the period of one PRBS (PRBS period), as shown in Equation 1. Therefore, in each of the n cycles of counting, the error in the cycle count relative to the PRBS period increases by (nr) bits in the negative direction for the first r counts, and decreases by r bits in the positive direction for the remaining (nr) counts. Thus, the error at the end of each n cycle counting is expressed in Equation 5. -r(nr)+(nr)r=0 (Equation 5) In other words, the error is reset to zero after each n-lap count is completed.

[0045] 1.3. Advantages (Effects) According to the first embodiment, the n-ary counter 22 increases the count value of the (p+1)-ary / p-ary counter 21 by 1 up to n each time the count value of the (p+1)-ary / p-ary counter 21 reaches its upper limit. The lap count counter 23 increases the lap count value by 1 each time the count value of the (p+1)-ary / p-ary counter 21 reaches its upper limit. The remainder comparison circuit 24 operates the (p+1)-ary / p-ary counter 21 as a (p+1)-ary counter while the value indicated by the output of the n-ary counter 22 is less than the remainder r, and operates the (p+1)-ary / p-ary counter 21 as a p-ary counter while the value indicated by the output of the n-ary counter 22 is greater than or equal to the remainder r. For every n lap counts, the (p+1)-ary / p-ary counter 21 functions as a (p+1)-ary counter for the first r lap counts and as a p-ary counter for the subsequent (nr) lap counts. As a result, in each of the n lap counts, the error in the lap count value relative to the PRBS period increases by (nr) bits in the negative direction for the first r counts, and decreases by r bits in the positive direction for the remaining (nr) counts. Therefore, after each n lap count, the error in the lap count value is reset to zero. In other words, the lap count circuit 2 can count laps with less error.

[0046] Figure 4 shows the change in the error of the lap count in the first type method for comparison and reference with the first embodiment. In Figure 4, the first type method is shown with a dashed line, and the first embodiment is shown with a solid line.

[0047] As shown in Figure 4, there is no difference between the first embodiment and the first type method in the short time elapsed since the start of operation. However, in the first type method, the error increases in the negative direction as time progresses. On the other hand, according to the first embodiment, even as time progresses, the error remains within 0 to -1.

[0048] 2. Second Embodiment The second embodiment differs from the first embodiment in terms of the method for detecting the circumference. The second embodiment relates to the case where r (remainder) is k (degree of PRBS) or greater.

[0049] 2.1. Structure Figure 5 is a block diagram of the lap counter circuit and PRBS generation circuit of the second embodiment. The lap counter circuit 2B of the second embodiment includes an n-ary counter 22, a lap counter 23, a remainder comparison circuit 24, a multiplexer (MUX) 31, a comparison register 32, and a comparison circuit 33.

[0050] The multiplexer 31 is a circuit that receives multiple inputs and outputs one based on the selected input from among the multiple inputs. The multiplexer 31 has k input terminals XI <k-1:0>, k input terminals YI <k-1:0>k output terminals ZO <k-1:0>It also has a selectable input terminal SELI2.

[0051] Multiplexer 31 has input terminal XI <k-1:0>In each case, bit string DF <n-1:n-k>Receives. Multiplexer 31 has input terminal YI <k-1:0>In each case, bit string DS <n-1:n-k>Receive. Multiplexer 31 has output terminal ZO <k-1:0>In each case, bit string DZ <k-1:0>Outputs.

[0052] Multiplexer 31 receives the signal DSEL at the selected input terminal SELI2. While receiving the low-level signal DSEL, multiplexer 31 continues to input terminal XI <k-1:0>The bit string received is bit string DZ <k-1:0>It outputs as follows. While the multiplexer 31 receives the high-level signal DSEL, it outputs to the input terminal YI <k-1:0>The bit string received is bit string DZ <k-1:0>Output as follows.

[0053] The comparison register 32 is a circuit that stores the bit sequence given as input to the comparison register 32 based on the enable signal, and also outputs the stored bit sequence. The comparison register 32 is a k-bit bit sequence database. <k-1:0>It can hold k input terminals ZI. The comparison register 32 has k input terminals ZI. <k-1:0>k output terminals BO <k-1:0>It has an enable input terminal EI3, a clock input terminal CK5, and a reset signal input terminal RN5.

[0054] The comparison register 32 is connected to input terminal ZI <k-1:0>In each case, bit string DZ <k-1:0>It receives the following. The comparison register 32 is output terminal BO. <k-1:0>In each case, bit string DB <k-1:0>Outputs.

[0055] The comparison register 32 receives the reset signal RN at the reset signal input terminal RN5. When the comparison register 32 receives a low-level reset signal RN, it resets the bit sequence stored in it to a predetermined initial value. The initial value of the comparison register 32 is set to the same value as the upper k bits (k consecutive bits including the most significant bit) of the initial value of register 11. In other words, the bit sequence DS held in register 11 is reset to the same value. <n-1:n-k>and the bit string DB held in the comparison register 32 <k-1:0>This means it will be reset to the same value. The comparison register 32 operates while it receives a high-level reset signal RN.

[0056] The comparison register 32 receives the clock signal CK at the clock input terminal CK5. The comparison register 32 also receives the enable signal DE2 at the enable input terminal EI3.

[0057] The operation of the comparison register 32 during its operating period, that is, during the period when it receives a high-level reset signal RN, is as follows: When the comparison register 32 receives a high-level enable signal DE2 during its operating period, it synchronizes with the rising edge of the clock CK to the bit sequence DZ <k-1:0>The value is internally taken in and stored. If the comparison register 32 receives a low-level enable signal DE2 during operation, the bit sequence DZ <k-1:0>The value is not taken internally, and the value that was previously stored internally is not changed. Regardless of whether the value of the enable signal DE2 is high or low, the comparison register 32 stores the internally stored value in the bit string DB during operation. <k-1:0>Output as follows.

[0058] The comparison circuit 33 is a circuit that outputs a signal of a certain level when the values ​​of two input bit sequences match. The comparison circuit 33 has k input terminals AI <k-1:0>k input terminals BI <k-1:0>It also has an enable output terminal EO2.

[0059] The comparison circuit 33 has an input terminal AI. <k-1:0>In each case, bit string DF <r-1:r-k>The comparison circuit 33 receives the input terminal BI. <k-1:0>In each case, bit string DB <k-1:0>Receive.

[0060] The comparison circuit 33 outputs an enable signal DE2 at the enable output terminal EO2. The comparison circuit 33 outputs an enable signal DE2 at the input terminal AI <k-1:0>The value of the bit string received and the input terminal BI <k-1:0>The comparison circuit 33 outputs a high-level enable signal DE2 while the values ​​of the bit sequences received match. <k-1:0>The value of the bit string received and the input terminal BI <k-1:0>While the values ​​of the bit strings received are different, a low-level enable signal DE2 is output.

[0061] The n-ary counter 22 receives the enable signal DE2 at the enable input terminal EI1. The loop counter 23 receives the enable signal DE2 at the enable input terminal EI2.

[0062] 2.2.Operation When counting the number of cycles of PRBS generated in parallel in n-bit increments, the second type method cannot detect each cycle of the PRBS, resulting in a maximum counting error of 19 times in the example shown in Figure 3. This is because the position of the leading bit of the PRBS period within one word of the n-bit PRBS shifts with each cycle. The cycle counting circuit 2B is a counting circuit that addresses the shift of the leading bit in the second type method.

[0063] The loop counting circuit 2B receives the bit string DF from the feedback logic circuit 12. <n-1:0>A bit string DF consisting of k consecutive bits starting from a position based on the remainder r. <r-1:r-k>The number of iterations of the PRBS is counted by comparing it with a certain bit string. Bit string DF <r-1:r-k>A certain bit sequence being compared is a fixed value in the initial lap count, and thereafter is updated each time a lap is counted.

[0064] In other words, the comparison circuit 33 has an input terminal AI. <k-1:0>The bit string DF received <r-1:r-k>The input terminal BI <k-1:0>The bit string DB that is received <k-1:0>It compares with the bit string DF. The comparison circuit 33 compares with the bit string DF. <n-1:n-k>and bit string DB <k-1:0>If they match, a high-level enable signal DE2 is output. The rising edge of the enable signal DE2 is counted by the lap counter 23, thereby counting the number of laps on the PRBS. The bit sequence DF follows. <r-1:r-k>This is sometimes referred to as the comparison bit string, and is a bit string DB. <k-1:0>This is sometimes referred to as the reference bit sequence.

[0065] Reference bit string DB <k-1:0>This is the output of the comparison register 32. The output of the comparison register 32 is reset to its initial value while the reset signal RN is low. When the reset signal RN goes high, the bit sequence DZ output by the multiplexer 31 is generated while the enable signal DE2 from the comparison circuit 33 is high. <k-1:0>The value is updated. Due to the nature of PRBS, the updated value is different from the value before the update, so the comparison result in the comparison circuit 33 does not match, and the value of the enable signal DE2 becomes low when the clock CK rises next. In this way, the reference bit sequence DB <k-1:0>This is updated each time the number of laps increases by one.

[0066] The cycle counting circuit 2B, as in the first embodiment, divides the counting cycles into n units of bits per word of PRBS, and further divides each n cycle into two groups: the 1st to the rth cycle and the (r+1)th to the nth cycle. The cycle counting circuit 2B switches the value input to the comparison register 32 between the 1st to the rth cycle and between the (r+1)th to the nth cycle. The selection of the value input to the comparison register 32 is performed by the multiplexer 31, and the selection by the multiplexer 31 is based on the signal DESL from the remainder comparison circuit 24.

[0067] The loop counter circuit 2B is reset upon receipt of a low-level reset signal RN, and then starts operating upon receipt of a subsequent high-level reset signal RN. At the start of operation, the bit sequence DU, which is the output of the n-ary counter 22, is reset. <j-1:0>Since it is reset to 0, the signal DSEL from the remainder comparator circuit 24 has a low level. The operation while the signal DSEL has a low level is the operation from the 1st to the rth cycle of the n-cycle count.

[0068] When the reset signal RN goes low, the value held in the comparison register 32 is reset to the same value as the upper k bits of the bit sequence held in register 11. This value is the initial value of the PRBS. When the reset signal RN goes high and PRBS are generated one after another, completing one cycle of PRBS, the leading bit of the PRBS is positioned (rk) bits higher than the leading bit of the PRBS that was held as the initial value in register 11 when the reset signal RN was low. The position of this leading bit is the bit sequence DF. <n-1:0>The middle (rk) bit string DF <r-k>This corresponds to bit string DF. <r-1:r-k>This is the reference bit sequence (i.e., bit sequence DB) which is the initial value of the comparison register 32. <k-1:0>) coincides with the timing of the clock cycle immediately preceding the output from the PRBS generation circuit 1. Due to this coincidence, the comparison circuit 33 outputs a high-level enable signal DE2. Therefore, the cycles of the PRBS are counted by the cycle counter 23 when the rising edge of the enable signal DE2 is counted.

[0069] When the comparison bit sequence and the reference bit sequence match less than r times in the comparison circuit 33, the signal DSEL is at a low level, and therefore the multiplexer 31 is at input terminal XI. <k-1:0>The system selects the input signal from the multiplexer 31. Therefore, when the enable signal DE2 goes high due to a match between the bit sequence to be compared and the reference bit sequence, the comparison register 32, at the timing when the clock CK rises next, selects the bit sequence from the multiplexer 31, i.e., the input terminal XI of the multiplexer 31. <k-1:0>The bit string DF received in <n-1:n-k>The stored value is updated to the value of DF. At this time, DF is stored in the comparison register 32 as the reference bit sequence. <n-1:n-k>The bit string DF to be compared <r-1:r-k>In contrast, the bit position at the output of the feedback logic circuit 12 is shifted by (nr) bits in the direction of advancing time.

[0070] Generally, since the period of the PRBS is not a multiple of n, when the PRBS completes another cycle after the comparison bit sequence and the reference bit sequence have matched, the value of the comparison bit sequence will be different from the reference bit sequence that matched last time. Therefore, when the two match, the reference bit sequence is rewritten to the value that will match next. There are two ways to rewrite it. One is to rewrite it to a value that is greater than one period of the PRBS and shifted by the closest multiple of n bits, and the other is to rewrite it to a value that is less than one period of the PRBS and shifted by the closest multiple of n bits. It is clear from Equation 1 that when the PRBS completes one cycle, the position of the leading bit of the n bits generated in the PRBS shifts by r bits in the direction of time progression from its original position. Therefore, by selecting a bit sequence that is shifted by (nr) bits in the direction of time progression from the comparison bit sequence, the reference bit sequence can be rewritten to a value that is greater than one period of the PRBS and shifted by the closest multiple of n bits.

[0071] When the reference bit sequence is overwritten, the comparison result in the comparator circuit 33 no longer matches, so the enable signal DE2 goes low, and the value of the reference bit sequence is held until the comparison result in the comparator circuit 33 matches again. This operation is repeated as long as the signal DSEL is low, that is, until the bit sequence being compared matches the reference bit sequence r times.

[0072] When the bit sequence to be compared matches the reference bit sequence r times, the signal DSEL becomes high level, so the multiplexer 31 switches to input terminal YI <k-1:0>The signal to be input is selected. Therefore, when the enable signal DE2 becomes high due to the matching of the bit sequence to be compared and the reference bit sequence, the comparison register 32, at the timing when the clock CK rises next, selects the bit sequence from the multiplexer 31, i.e., the input terminal YI of the multiplexer 31. <k-1:0>The bit string DS received in <n-1:n-k>The stored value is updated to the value of DS. At this time, the DS is stored in the comparison register 32 as the reference bit sequence. <n-1:n-k>The bit string DF to be compared <r-1:r-k>In contrast, the bit positions in the two words formed by connecting the output of the feedback logic circuit 12 as the upper word and the output of register 11 as the lower word are shifted by r bits in the direction of time delay.

[0073] When the PRBS completes one cycle, the position of the leading bit of the n-bit PRBS generated shifts by r bits in the time direction from its original position. Therefore, by selecting a bit sequence that is shifted by r bits in the time direction from the comparison bit sequence, the reference bit sequence can be rewritten to a value smaller than one period of the PRBS, and shifted by the closest multiple of n bits.

[0074] When the reference bit sequence is overwritten, the comparison result in the comparator circuit 33 no longer matches, so the enable signal DE2 goes low, and the value of the reference bit sequence is held until the comparison result in the comparator circuit 33 matches again. This operation is repeated as long as the signal DSEL is high.

[0075] The loop counting circuit 2B, while the n-ary counter 22 performs n counts, updates the reference bit string to the bit string in the PRBS located at a position shifted (nr) bits ahead of the comparison bit string each time the output of the loop counter 23 increases by 1 during the first r counts. For the next (nr) counts, it updates the reference bit string to the bit string in the PRBS located at a position shifted r bits behind the comparison bit string. Therefore, during the first r counts, the loop counting error increases negatively by (nr) bits, and for the next (nr) counts, the loop counting error decreases positively by r bits. The loop counting error at the end of the n-ary counter 22's n counts is expressed by equation 5, as in the first embodiment, and its value is 0. At this point, the reference bit string returns to the same value as the initial value of the comparison register 32. Therefore, the same operation is repeated when the n-ary counter 22 performs the next n counts, and the loop counting of the PRBS is performed continuously.

[0076] 2.3. Advantages According to the second embodiment, the number of laps can be counted with less error for the same reasons as in the first embodiment.

[0077] According to the second embodiment, the enable signal DE2, which functions as the target of loop counting, is output based on the agreement between the bit sequence to be compared and the reference bit sequence. The reference bit sequence is output from the comparison register 32, and the comparison register 32 updates the value it holds only while the enable signal DE2 is at a high level. Therefore, the comparison register 32 does not need to count the clock CK in order to generate the enable signal DE2. Thus, the power consumption of the comparison register 32 is suppressed, and consequently, a loop counting circuit with reduced power consumption is realized.

[0078] 3. Third Embodiment The third embodiment is similar to the second embodiment in terms of the method for detecting circumference. The third embodiment relates to the case where the number of bits n is a power of 2.

[0079] Figure 6 is a block diagram of the lap counter circuit and PRBS generation circuit of the third embodiment. The lap counter circuit 2C of the third embodiment is similar to the lap counter circuit 2B of the second embodiment. The lap counter circuit 2C includes a lap counter 23, a multiplexer 31, a comparison register 32, and a comparison circuit 33, but does not include a remainder comparison circuit 24. The lap counter circuit 2C does not include the n-ary counter 22 of the second embodiment, but instead includes an n-ary counter 41.

[0080] The n-ary counter 41 is a circuit that counts the edges of the supplied clock and outputs a signal having a level based on the counted value. The n-ary counter 41 has an enable input terminal EI4, a clock input terminal CK6, a reset signal input terminal RN6, and an output terminal EO3.

[0081] The n-ary counter 41 receives the enable signal DE2 at the enable input terminal EI4 and the clock CK at the clock input terminal CK6. The n-ary counter 41 counts the rising edges of the clock CK only while it receives the high-level enable signal DE2. The n-ary counter 41 does not count while it receives the low-level enable signal DE2. The count value is between 0 and n-1. When the n-ary counter 41 reaches its upper limit (i.e., n-1), it resets the count value to 0 at the timing of the first rising edge of the clock CK during the period after the count value reached the upper limit and the high-level enable signal DE2 was received. The n-ary counter 41 outputs the signal DSEL2 at the output terminal EO3. The n-ary counter 41 outputs the high-level signal DSEL2 while the count value is n-1. The n-ary counter 41 outputs the low-level signal DSEL2 while the count value is anything other than n-1.

[0082] The n-ary counter 41 receives a reset signal RN at the reset signal input terminal RN6. When the n-ary counter 41 receives a low-level reset signal RN, it resets the count value to 0. The n-ary counter 41 continues counting while it receives a high-level reset signal RN.

[0083] The comparison circuit 33 has an input terminal AI. <k-1:0>In each case, bit string DF <n-2:n-k-1>Receive.

[0084] The period of PRBS is 2 k Since it is -1, adding 1 to the period of PRBS will always result in a value that is a power of 2. In the third embodiment, since n is a power of 2, the sum of the period of PRBS and 1 is divisible by n, and the remainder r is n-1. For this reason, the count value of the n-ary counter 41 is greater than or equal to r only when the count value is n-1. For this reason, the n-ary counter 41 outputs a high-level signal DSEL2 only while the count value is n-1, thereby indicating the state of the multiplexer 31 when the count value of the n-ary counter 41 is greater than or equal to r, i.e., the bit sequence DS <n-1:n-k>A state in which this is selected is formed. Therefore, if n is a power of 2, the lap counting circuit 2C can count the number of laps in the same form as the lap counting circuit 2B of the second embodiment. For this reason, the same advantages as the second embodiment can be obtained with a simpler configuration than the lap counting circuit 2B of the second embodiment.

[0085] 4. Fourth Embodiment The fourth embodiment uses the same circumference detection method as the third embodiment and, like the third embodiment, concerns the case where the number of bits n is a power of 2. On the other hand, the fourth embodiment achieves the same circumference detection as the third embodiment by a different method.

[0086] Figure 7 is a block diagram of the lap counter circuit and PRBS generation circuit of the fourth embodiment. The lap counter circuit 2D of the fourth embodiment includes the same components as the lap counter circuit 2C of the third embodiment, namely, a lap counter 23, a multiplexer 31, a comparison register 32, a comparison circuit 33, and an n-ary counter 41. On the other hand, the multiplexer 31 has an input terminal YI <k-1:0>In this step, the initial value of the comparison register is received. The initial value of the comparison register is the value held by the comparison register 32 when the comparison register 32 receives a low-level reset signal RN, and is also the bit string DB. <k-1:0>This is the value that it possesses. In one example, the initial value of the comparison register is supplied by the control circuit 3.

[0087] The k consecutive bits, including the most significant bit of the value held in register 11, i.e., the bit sequence DS <n-1:n-k>The initial value and the value held in the comparison register 32, i.e., the bit string DB <k-1:0>The initial values ​​are the same. When the n-ary counter 41 has counted n times and the count value returns to 0, the value held in register 11, i.e., the bit string DS, <n-1:n-k>The value returns to its initial value. Therefore, when the n-ary counter 41 performs n counts and outputs a high-level signal DSEL2, the high-level signal DSEL2 causes the multiplexer 31 to select the initial value of the comparison register, and the value held in the comparison register 32 is reset to its initial value on the rising edge of the next clock CK. That is, as in the third embodiment, the bit sequence DS <n-1:n-k>The input terminal YI of the multiplexer 31 <k-1:0>When supplied, the initial bit sequence DS of register 11 is set every n lap measurements. <n-1:n-k>The same operation as supplying to the comparison register 32 is performed. Therefore, according to the fourth embodiment, the same advantages as the third embodiment can be obtained.

[0088] Input terminal YI <k-1:0>In this case, the combination of the multiplexer 31, which receives the initial value of the comparison register 32, and the comparison register 32 can be considered as a register with synchronous reset, using the selection input terminal SELI2 of the multiplexer 31 as the synchronous reset input terminal. Therefore, the input terminal YI <k-1:0>In this configuration, the combination of the multiplexer 31, which receives the initial value of the comparison register 32, and the comparison register 32 may be implemented as a single circuit with a synchronous reset register, using the select input terminal SELI2 of the multiplexer 31 as the synchronous reset input terminal.

[0089] 5. Fifth Embodiment The fifth embodiment is similar to the second embodiment in terms of the method for detecting circumference. The fifth embodiment relates to the case where the remainder r is less than the degree k.

[0090] Figure 8 is a block diagram of the perimeter counting circuit and PRBS generation circuit of the fifth embodiment. The perimeter counting circuit 2E of the fifth embodiment includes the same components as the perimeter counting circuit 2B of the second embodiment. On the other hand, some components receive different bit sequences than those of the second embodiment.

[0091] The comparison circuit 33 has an input terminal AI. <k-1:0>In each case, bit string DG <k-1:0>Receives bit string DG <k-1:0>The bit sequence DF is a contiguous r bit including the most significant bit. <r-1:0>The bit string DS includes the remaining least significant bit and the contiguous (kr) bits.<n-1:n-(k-r)> This includes the bit string DG. <k-1:0>This is the bit string DF from the (k-1)th to the (kr)th bit. <n-1:0>Each of the lower r bits is included, and the bit string DS is used from the (kr-1) to the 0th bit. <n-1:0>Each includes the most significant (kr) bit.

[0092] According to the fifth embodiment, in the case where the remainder r is less than the order k, the loop counter 23, multiplexer 31, comparison register 32, comparison circuit 33, and n-ary counter 22 operate in the same manner as in the second embodiment. Therefore, the same advantages as in the second embodiment can be obtained in the case where the remainder r is less than the order k.

[0093] 6. Sixth Embodiment The sixth embodiment is similar to the second embodiment in terms of the method for detecting circumference. The sixth embodiment relates to the case where the remainder r is of order k or higher of the PRBS.

[0094] Figure 9 is a block diagram of the lap counter circuit and PRBS generation circuit of the sixth embodiment. The lap counter circuit 2F of the sixth embodiment includes a lap counter 23, a comparison register 32, and a comparison circuit 33. On the other hand, some components receive different bit sequences than those of the second embodiment.

[0095] The comparison register 32 is connected to input terminal ZI <k-1:0>In each case, bit string DF <n-1:n-k>Receive.

[0096] As shown in Figure 4, the lap count value obtained by the first type method and the lap count value obtained by the first embodiment do not differ for a certain period after the start of counting. In particular, when the number of bits n is a power of 2, the number of bits of PRBS required to increase the lap count value by 1 differs by only one bit from one period of PRBS. Therefore, until (n-1) laps have been counted from the start of counting, the lap count value obtained by the first embodiment is no different from the lap count value obtained by the first type method. Based on this, the sixth embodiment does not include the multiplexer 31, the n-ary counter 22, and the remainder comparison circuit 24, which are useful in suppressing errors in the second embodiment. As a result, according to the sixth embodiment, when the upper limit of the number of laps to be counted is small, a lap counting circuit 2F is realized that produces only suppressed errors in the lap count value, similar to the second embodiment, and consumes even less power than the second embodiment.

[0097] 7. Seventh Embodiment The seventh embodiment is similar to the second embodiment in terms of the method for detecting circumference. The seventh embodiment, like the fifth embodiment, concerns the case where the remainder r is less than the order k of the PRBS.

[0098] Figure 10 is a block diagram of the perimeter counting circuit and PRBS generation circuit of the seventh embodiment. The perimeter counting circuit 2G of the seventh embodiment includes the same components as the perimeter counting circuit 2F of the sixth embodiment. On the other hand, some components receive different bit sequences than those of the sixth embodiment.

[0099] The comparison register 32 is connected to the input terminal ZI, as in the sixth embodiment. <k-1:0>In each case, bit string DF <n-1:n-k>Receive.

[0100] The comparison circuit 33, as in the fifth embodiment, has an input terminal AI. <k-1:0>In each case, bit string DG <k-1:0>Receive.

[0101] According to the seventh embodiment, in the case where the remainder r is less than the order k, the lap counter 23, the comparison register 32, and the comparison circuit 33 operate in the same way as in the sixth embodiment. Therefore, the same advantages as in the sixth embodiment can be obtained in the case where the remainder r is less than the order k. Furthermore, according to the seventh embodiment, when the upper limit of the number of laps to be counted is small, a lap count circuit 2F is realized that produces only suppressed errors in the lap count value, similar to the fifth embodiment, and consumes even more suppressed power than in the fifth embodiment.

[0102] While several embodiments of the present invention have been described, these embodiments are presented as examples only and are not intended to limit the scope of the invention. These embodiments can be carried out in a variety of other forms, and various omissions, substitutions, and modifications can be made without departing from the spirit of the invention. These embodiments and their variations are included in the scope and spirit of the invention, as well as in the claims and their equivalents. [Explanation of Symbols]

[0103] 100... System, 1...PRBS generation circuit, 2...Loop counting circuit, 3…Control circuit, 11... Register, 12…Feedback logic circuits, 21…(p+1)-ary / p-ary counter, 22...n-ary counter, 23...Lap counter, 24... Remainder comparator circuit, 31…Multiplexer, 32...Comparison register, 33...Comparison circuit.

Claims

1. Output based on the clock, and also 2 ｋ A loop counting circuit that counts the number of cycles of a bit sequence that has a period of -1 bits (where k is a positive integer) and is output every n bits (where n is a positive integer), While receiving the first level selection signal, the (p+1)-step counter (where p is 2) ｋ A first counter operates as the quotient of a division operation with -1 as the dividend and n as the divisor, and while receiving the second level selection signal, it operates as a p-adic counter, counts the clock to obtain a first count value, and outputs a third level first signal when the first count value becomes p while operating as a (p+1)-adic counter and when the first count value becomes p-1 while operating as a p-adic counter. A second counter that counts the third level of the first signal to obtain a second count value and outputs a first bit sequence indicating the second count value, An n-ary counter that counts the third level of the first signal to obtain a third count value and outputs a second bit sequence representing the third count value, A comparison circuit outputs the first level selection signal while the third count value is less than r (where r is the remainder of the division), and outputs the second level selection signal while the third count value is r or greater. A circuit that includes a loop counting circuit.

2. The n-ary counter, upon receiving the first signal of the third level while the third count value is n-1, sets the third count value to 0. The lap counter circuit according to claim 1.

3. Output 2 by the generation circuit ｋ A loop counting circuit that counts the number of cycles of an output bit sequence having a period of -1 bits (where k is a positive integer) and outputting every n bits (where n is a positive integer), The aforementioned generation circuit is A first register that receives a first bit sequence, holds the first bit sequence, and outputs the first bit sequence as the output bit sequence based on the clock, A logic circuit that generates the first bit sequence by performing a logic operation on a second bit sequence consisting of k consecutive bits including the most significant bit of the output bit sequence, Includes, A multiplexer that, while receiving a first-level selection signal, outputs a third bit sequence consisting of k consecutive bits including the most significant bit of the first bit sequence as the fourth bit sequence, and while receiving a second-level selection signal, outputs the second bit sequence as the fourth bit sequence. A second register that, while receiving a first signal of the third level, holds the fourth bit sequence and outputs the fourth bit sequence as a fifth bit sequence, and while receiving the first signal of the fourth level, outputs the fifth bit sequence without holding the fourth bit sequence, The k consecutive bits from the r-1 bit to the r-k bit of the first bit sequence (where r is 2) ｋ A first comparator circuit outputs the third level first signal when the sixth bit sequence, which consists of the remainder of a division with -1 as the dividend and n as the divisor, matches the fifth bit sequence, A first counter that counts the third level of the first signal to obtain a first count value and outputs a seventh bit sequence representing the first count value, An n-ary counter that counts the third level of the first signal to obtain a second count value and outputs an eighth bit sequence representing the second count value, A second comparator circuit outputs the first level selection signal while the second count value is less than r, and outputs the second level selection signal while the second count value is r or greater. A loop counting circuit equipped with a loop counting circuit.

4. The first register and the second register, which consist of a contiguous set of k bits including the most significant bit, are reset to the same value upon receiving a fifth-level reset signal. The lap counting circuit according to claim 3.

5. When the second register receives the clock that changes from the sixth level to the seventh level while it is receiving the first signal of the third level, it incorporates and holds the third bit sequence and outputs the value of the incorporated third bit sequence as the fifth bit sequence. When the second register receives the clock that changes from the sixth level to the seventh level while it is receiving the first signal of the fourth level, it outputs the value it holds as the fifth bit sequence without incorporating the third bit sequence. The loop counting circuit according to claim 4.

6. The n-ary counter, upon receiving the first signal of the third level while the second count value is n-1, sets the second count value to 0. The lap counting circuit according to claim 3.

7. Output 2 by the generation circuit ｋ A loop counting circuit that counts the number of cycles of an output bit sequence having a period of -1 bits (where k is a positive integer) and outputting every n bits (where n is a positive integer), The aforementioned generation circuit is A first register that receives a first bit sequence, holds the first bit sequence, and outputs the first bit sequence as the output bit sequence based on the clock, A logic circuit that generates the first bit sequence by performing a logic operation on a second bit sequence consisting of k consecutive bits including the most significant bit of the output bit sequence, Includes, A multiplexer that, while receiving a first-level selection signal, outputs a third bit sequence consisting of k consecutive bits including the most significant bit of the first bit sequence as the fourth bit sequence, and while receiving a second-level selection signal, outputs the second bit sequence as the fourth bit sequence. A second register that, while receiving a first signal of the third level, holds the fourth bit sequence and outputs the fourth bit sequence as a fifth bit sequence, and while receiving the first signal of the fourth level, outputs the fifth bit sequence without holding the fourth bit sequence, A comparison circuit outputs the first signal of the third level when the sixth bit sequence, consisting of k consecutive bits from the n-2 bit to the n-k-1 bit of the first bit sequence, matches the fifth bit sequence. A first counter that counts the third level of the first signal to obtain a first count value and outputs a seventh bit sequence representing the first count value, An n-ary counter that counts the third level of the first signal to obtain a second count value, outputs the selection signal of the second level while the second count value is n-1, and outputs the selection signal of the first level while the second count value is other than n-1, A loop counting circuit equipped with a loop counting circuit.

8. When the second register receives the clock that changes from the fifth level to the sixth level while it is receiving the first signal of the third level, it incorporates and holds the fourth bit sequence and outputs the value of the incorporated fourth bit sequence as the fifth bit sequence. When the second register receives the clock that changes from the fifth level to the sixth level while it is receiving the first signal of the fourth level, it outputs the value it holds as the fifth bit sequence without incorporating the fourth bit sequence. The loop counting circuit according to claim 7.

9. The n-ary counter, upon receiving the first signal of the third level while the second count value is n-1, sets the second count value to 0. The loop counting circuit according to claim 7.

10. Output 2 by the generation circuit ｋ A loop counting circuit that counts the number of cycles of an output bit sequence having a period of -1 bits (where k is a positive integer) and outputting every n bits (where n is a positive integer), The aforementioned generation circuit is A first register that receives a first bit sequence, holds the first bit sequence, and outputs the first bit sequence as the output bit sequence based on the clock, A logic circuit that generates the first bit sequence by performing a logic operation on a second bit sequence consisting of k consecutive bits including the most significant bit of the output bit sequence, Includes, A multiplexer that, while receiving a first-level selection signal, outputs a third bit sequence consisting of k consecutive bits including the most significant bit of the first bit sequence as the fourth bit sequence, and while receiving a second-level selection signal, outputs a fifth bit sequence indicating a fixed value as the fourth bit sequence. A second register that, while receiving a third-level first signal, holds the fourth bit sequence and outputs the fourth bit sequence as a sixth bit sequence, and while receiving a fourth-level first signal, outputs the sixth bit sequence without holding the fourth bit sequence; A comparison circuit outputs the first signal of the third level when the seventh bit sequence, consisting of k consecutive bits from the n-2 bit to the n-k-1 bit of the first bit sequence, matches the sixth bit sequence. A first counter that counts the third level of the first signal to obtain a first count value and outputs an eighth bit sequence representing the first count value, An n-ary counter that counts the third level of the first signal to obtain a second count value, outputs the selection signal of the first level while the second count value is other than n-1, and outputs the selection signal of the second level while the second count value is n-1, A loop counting circuit equipped with a loop counting circuit.

11. When the first register receives a fifth-level reset signal, it holds the first bit sequence with its initial value, The fifth bit sequence has the same value as a contiguous k bits including the most significant bit of the first bit sequence of the initial value. The lap counting circuit according to claim 10.

12. When the second register receives the clock that changes from the fifth level to the sixth level while it is receiving the first signal of the third level, it incorporates and holds the fourth bit sequence and outputs the value of the incorporated fourth bit sequence as the sixth bit sequence. When the second register receives the clock that changes from the fifth level to the sixth level while it is receiving the first signal of the fourth level, it outputs the value it holds as the sixth bit sequence without incorporating the fourth bit sequence. The lap counting circuit according to claim 10.

13. The n-ary counter, upon receiving the first signal of the third level while the second count value is n-1, sets the second count value to 0. The lap counting circuit according to claim 10.

14. Output 2 by the generation circuit ｋ A loop counting circuit that counts the number of cycles of an output bit sequence having a period of -1 bits (where k is a positive integer) and outputting every n bits (where n is a positive integer), The aforementioned generation circuit is A first register that receives a first bit sequence, holds the first bit sequence, and outputs the first bit sequence as the output bit sequence based on the clock, A logic circuit that generates the first bit sequence by performing a logic operation on a second bit sequence consisting of k consecutive bits including the most significant bit of the output bit sequence, Includes, A multiplexer that, while receiving a first-level selection signal, outputs a third bit sequence consisting of k consecutive bits including the most significant bit of the first bit sequence as the fourth bit sequence, and while receiving a second-level selection signal, outputs the second bit sequence as the fourth bit sequence. A second register that, while receiving a first signal of the third level, holds the fourth bit sequence and outputs the fourth bit sequence as a fifth bit sequence, and while receiving the first signal of the fourth level, outputs the fifth bit sequence without holding the fourth bit sequence, The r consecutive bits (where r is 2) that include the least significant bit of the first bit sequence. ｋ A first comparator circuit outputs the third level first signal when the sixth bit sequence, which includes the remainder of a division with -1 as the dividend and n as the divisor, starting from the most significant bit, and the sixth bit sequence, which includes the most significant bit of the output bit sequence and the following consecutive (k-r) bits starting from the least significant bit, matches the fifth bit sequence. A first counter that counts the third level of the first signal to obtain a first count value and outputs a seventh bit sequence representing the first count value, An n-ary counter that counts the third level of the first signal to obtain a second count value and outputs an eighth bit sequence representing the second count value, A second comparator circuit outputs the first level selection signal while the second count value is less than r, and outputs the second level selection signal while the second count value is r or greater. A loop counting circuit equipped with a loop counting circuit.

15. When the second register receives the clock that changes from the fifth level to the sixth level while it is receiving the first signal of the third level, it incorporates and holds the fourth bit sequence and outputs the value of the incorporated fourth bit sequence as the fifth bit sequence. When the second register receives the clock that changes from the fifth level to the sixth level while it is receiving the first signal of the fourth level, it outputs the value it holds as the fifth bit sequence without incorporating the fourth bit sequence. The loop counting circuit according to claim 14.

16. The n-ary counter, upon receiving the first signal of the third level while the second count value is n-1, sets the second count value to 0. The loop counting circuit according to claim 14.

17. 2 output by the generation circuit ｋ a cycle counting circuit that has a period of 2−1 (k is a positive integer) bits and counts the cycles of an output bit sequence output every n (n is a positive integer) bits The aforementioned generation circuit is A first register that receives a first bit sequence, holds the first bit sequence, and outputs the first bit sequence as the output bit sequence based on the clock, A logic circuit that generates the first bit sequence by performing a logic operation on a second bit sequence consisting of k consecutive bits including the most significant bit of the output bit sequence, Includes, A second register, while receiving a first signal of the first level, holds a third bit sequence consisting of k consecutive bits including the most significant bit of the first bit sequence and outputs the third bit sequence as a fourth bit sequence, and while receiving the first signal of the second level, outputs the fourth bit sequence without holding the third bit sequence. Bits r-1 to r-k (where r is 2) of the first bit sequence ｋ A first comparator circuit outputs the first signal of the first level when the fifth bit sequence, which consists of the remainder of a division with -1 as the dividend and n as the divisor, matches the fourth bit sequence. A first counter that counts the first level of the first signal to obtain a first count value and outputs a sixth bit sequence representing the first count value, A loop counting circuit equipped with a loop counting circuit.

18. When the second register receives the clock that changes from the third level to the fourth level while it is receiving the first signal of the first level, it incorporates and holds the third bit sequence and outputs the value of the incorporated third bit sequence as the fourth bit sequence. When the second register receives the clock that changes from the third level to the fourth level while it is receiving the first signal of the second level, it outputs the value it holds as the fourth bit sequence without incorporating the third bit sequence. The lap counting circuit according to claim 17.

19. Output 2 by the generation circuit ｋ A loop counting circuit that counts the number of cycles of an output bit sequence having a period of -1 bits (where k is a positive integer) and outputting every n bits (where n is a positive integer), The aforementioned generation circuit is A first register that receives a first bit sequence, holds the first bit sequence, and outputs the first bit sequence as the output bit sequence based on the clock, A logic circuit that generates the first bit sequence by performing a logic operation on a second bit sequence consisting of k consecutive bits including the most significant bit of the output bit sequence, Includes, A second register, while receiving a first signal of the first level, holds a third bit sequence consisting of k consecutive bits including the most significant bit of the first bit sequence and outputs the third bit sequence as a fourth bit sequence, and while receiving the first signal of the second level, outputs the fourth bit sequence without holding the third bit sequence. The r consecutive bits (where r is 2) that include the least significant bit of the first bit sequence. ｋ A first comparator circuit outputs the first signal of the first level when the fifth bit sequence, which includes the remainder of a division with -1 as the dividend and n as the divisor, starting from the most significant bit, and also includes a sequence of (k-r) bits starting from the least significant bit of the output bit sequence, matches the fourth bit sequence. A first counter that counts the first level of the first signal to obtain a first count value and outputs a sixth bit sequence representing the first count value, A loop counting circuit equipped with a loop counting circuit.

20. When the second register receives the clock that changes from the third level to the fourth level while it is receiving the first signal of the first level, it incorporates and holds the third bit sequence and outputs the value of the incorporated third bit sequence as the fourth bit sequence. When the second register receives the clock that changes from the third level to the fourth level while it is receiving the first signal of the second level, it outputs the value it holds as the fourth bit sequence without incorporating the third bit sequence. The lap counting circuit according to claim 19.

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