Indication device

Abstract

To provide a display device with reduced power consumption. 【Solution means】A pixel portion having a plurality of pixels including a first transistor, a second transistor, and a light-emitting element having a pair of electrodes, wherein the gate of the first transistor is electrically connected to a scanning line, one of the source or drain is electrically connected to a signal line, the other of the source or drain is electrically connected to the gate of the second transistor, one of the source or drain of the second transistor is electrically connected to a power supply line, the other of the source or drain is electrically connected to one of the pair of electrodes, and the first transistor has an oxide semiconductor layer with a hydrogen concentration of 5×10 / cm or less. And, During the period when the display device displays a still image, there is a period in which the output of the signals supplied to all the scanning lines included in the pixel portion is stopped. 19 3 ​​​​​​​

Description

[Technical Field]

[0001] This invention relates to a display device, or to an electronic device equipped with such a display device. [Background technology]

[0002] In recent years, liquid crystal display devices and electroluminescent elements have been developed. Flat panel displays, such as EL displays (hereinafter referred to as "EL displays") Ray is being mass-produced as the mainstream image display device.

[0003] In the case of active-matrix liquid crystal displays and EL displays, each pixel in the pixel section is traceable. A transistor is provided. And these transistors are made from silicon (Si) A semiconductor layer is used as the active layer.

[0004] In response to this, an image display device using a transistor with an oxide as the active layer has been proposed. (See, for example, Patent Document 1). [Prior art documents] [Patent Documents]

[0005] [Patent Document 1] Japanese Patent Publication No. 2006-165528 [Overview of the project] [Problems that the invention aims to solve]

[0006] Off-current is one of the indicators used to determine the electrical characteristics of a transistor. When the transistor is in the off state (also called the non-conductive state), between the source and drain This refers to the current that flows between the gate and the source. In an n-channel transistor, this is the current that flows between the gate and the source. When the applied voltage is below the threshold voltage (Vth), the current flowing between the source and drain It refers to a flow or current.

[0007] By using an amorphous oxide semiconductor thin film as the channel layer of a transistor, off-electricity can be achieved. The current is 10 μA (= 1 × 10⁻¹⁰). -5 A) Less than 0.1 μA (= 1 × 10⁻¹⁶ μA) -7 A) Not yet Patent Document 1 discloses that it can be made satisfactory. Furthermore, Patent Document 1 discloses amorphous acid By using a semiconductor thin film, the on / off ratio can be increased to 10 3 It is stated that it can be greater than However, in transistors exhibiting this level of electrical characteristics, the off-current is It cannot be said to be sufficiently low. In other words, further reduction in power consumption of image display devices is required. To meet the needs of the world, it is necessary to further reduce the off-current.

[0008] One aspect of the present invention is a plurality of pixels having transistors made of oxide semiconductors. The objective is to provide a display device that includes a pixel section and has reduced power consumption. Let's consider it one. [Means for solving the problem]

[0009] One aspect of the present invention relates to a method in which an oxide semiconductor is used in each pixel of the display unit of a display device. It is characterized by having at least one transistor. Transistor using this oxide semiconductor The sta has stable electrical characteristics, for example, its off-current is extremely low. In order to achieve low transistors, one aspect of the present invention is intrinsically or substantially intrinsically Oxide semiconductors (high-purity) in which the concentration of impurities that act as carrier donors has been reduced to an extremely low degree. It uses an oxide semiconductor. Typically, one aspect of the present invention is the hydrogen concentration contained in the film. 5 x 10 19 / cm 3 The following is a transistor using an oxide semiconductor.

[0010] One aspect of the present invention comprises a first transistor, a second transistor, and a pair of electrodes. The pixel section has a plurality of pixels, each containing a light-emitting element. In a gate, the gate is electrically connected to the scan line, and either the source or drain is electrically connected to the signal line. They are connected in a manner, with the source or drain of the other being electrically connected to the gate of the second transistor. The second transistor is connected to the power line, with either the source or drain of the transistor electrically connected to the power line. The source or drain is connected to the other of the pair of electrodes, The first transistor has a hydrogen concentration of 5 × 10 19 / cm 3 The oxide semiconductor layer is as follows: This is a device characterized by having [a certain feature].

[0011] Furthermore, in one aspect of the present invention, during the period during which the display device displays a still image, the pixel portion A display device having a period during which the output of signals supplied to all scan lines included is stopped. ru.

[0012] Furthermore, one aspect of the present invention includes a first transistor, a second transistor, and a pair of electrodes. A pixel section having multiple pixels including a light-emitting element, and a drive circuit for driving the pixel section. A unit that generates a control signal to drive the drive circuit unit and an image signal to supply to the pixels. A signal generation circuit, a storage circuit that stores the image signal for each frame period, and the storage circuit The difference between the image signals of consecutive frame periods, among the image signals stored for each frame period. A comparison circuit for detecting minutes, and when a difference is detected by the comparison circuit, the continuous frame period A selection circuit that selects and outputs an image signal of, and when a difference is detected by the comparison circuit, the control A display control circuit that supplies the control signal and the image signal output from the selection circuit to the drive circuit unit, and stops supplying the control signal to the drive circuit unit when no difference is detected by the comparison circuit And has. Then, the gate of the first transistor is electrically connected to the scanning line One of the source or drain is electrically connected to the signal line, and the other of the source or drain Is electrically connected to the gate of the second transistor, and the second transistor One of the source or drain is electrically connected to the power supply line, and the other of the source or drain Is electrically connected to one of the pair of electrodes, and the first transistor has an oxide semiconductor layer having a hydrogen concentration Of 5 × 10 / cm 19 / cm 3 Or less, and is a display device characterized by having an oxide semiconductor layer There is.

[0013] Also, one aspect of the present invention is a display device in which the control signal is a high power supply potential, a low power supply potential, a clock signal, A start pulse signal, or a reset signal.

[0014] Also, one aspect of the present invention is a display device further having a phosphorescent layer in the pixel.

[0015] Also, one aspect of the present invention is a display device in which the carrier concentration of the oxide semiconductor layer is 1 × 10 14 / cm 3 Less than.

[0016] Also, one aspect of the present invention is a display device in which the band gap of the oxide semiconductor layer is 2 eV or more Show device.

[0017] Furthermore, in one aspect of the present invention, the second transistor has a hydrogen concentration of 5 × 10 19 / cm 3 The following is a device having an oxide semiconductor layer.

[0018] Furthermore, in one aspect of the present invention, the second transistor has a polycrystalline silicon layer It is a device.

[0019] Furthermore, one aspect of the present invention is an electronic device comprising the display device.

[0020] Furthermore, due to its structure, it is difficult to distinguish between the source and drain of a transistor. Depending on the operation of the circuit, the high and low potentials may be reversed. Therefore, in this specification... The source and drain are not specifically designated, and the first electrode (or first terminal), the second electrode ( This is written as (the second terminal). For example, if the first electrode is the source, then the second electrode and The first electrode refers to the drain, and conversely, if the first electrode is the drain, then the second electrode is the source. It shall refer to.

[0021] In this specification, "aperture ratio" refers to the area of ​​light transmitted per unit area. This represents the ratio, and as the area occupied by the light-impermeable material increases, the aperture As the ratio decreases and the area occupied by light-transmitting material widens, the aperture ratio improves. In a display device, the area occupied by wiring superimposed on the pixel electrodes, capacitance lines, and the size of the transistors Reducing the size of the opening improves the aperture ratio.

[0022] In particular, in a self-emissive display device that includes a light-emitting element in each pixel, the observer can see the display device's surface. The ratio of the light-emitting area of ​​a light-emitting element, observable from a position facing the display, to the pixel area is called the aperture ratio. That's what they say.

[0023] Furthermore, in this specification, when it is stated that "A and B are connected," it means that A and B are connected. When they are electrically connected (that is, when another element or circuit is placed between A and B) (when connected) and when A and B are functionally connected (i.e., between A and B) (When A and B are functionally connected with another circuit in between) and when A and B are directly connected This includes cases where A and B are connected without any other elements or circuits in between. It shall be assumed.

[0024] Furthermore, the terms 1st, 2nd, 3rd, through Nth (where N is a natural number) used herein are defined as follows: This is added to avoid confusion of constituent elements and does not limit them numerically. For example, Even if referred to as the "first transistor" in this specification, it should not be confused with other components. Within that scope, it can be reinterpreted as "the second transistor." [Effects of the Invention]

[0025] According to one aspect of the present invention, a transistor using a high-purity oxide semiconductor is used in the display device. By using it in the base part, the off-current is 1 × 10 -13 It can be reduced to A or less. Therefore, it becomes possible to extend the data retention period, and the power consumption when displaying still images, etc. It can be suppressed.

[0026] Furthermore, the system determines whether an image is still or moving, and the operation of the drive circuit during the period when a still image is displayed. By stopping this process, the power consumption of the display device can be further reduced. [Brief explanation of the drawing]

[0027] [Figure 1] A diagram showing an example of a display device configuration. [Figure 2] An equivalent circuit diagram showing an example of pixel configuration. [Figure 3] A cross-sectional view showing an example of a transistor. [Figure 4] A diagram showing the relationship between the writing period and retention period for each pixel. [Figure 5] A cross-sectional view showing an example of pixel configuration. [Figure 6] Plan view and cross-sectional view showing an example of an illuminated display panel. [Figure 7] A diagram showing an example of a block diagram of a display device. [Figure 8] A diagram showing an example of a drive circuit. [Figure 9] A diagram showing the timing chart of the drive circuit. [Figure 10] A diagram showing an example of a drive circuit. [Figure 11] A diagram illustrating an example of the procedure for supplying and stopping signals to a drive circuit. [Figure 12] Plan view and cross-sectional view showing an example of an illuminated display panel. [Figure 13] Plan and cross-sectional views showing an example of a transistor. [Figure 14] A cross-sectional view showing an example of a transistor fabrication method. [Figure 15] A cross-sectional view showing an example of a transistor fabrication method. [Figure 16] A cross-sectional view showing an example of a transistor fabrication method. [Figure 17] A cross-sectional view showing an example of a transistor fabrication method. [Figure 18] A cross-sectional view showing an example of pixel configuration. [Figure 19] A diagram showing electronic equipment. [Figure 20] A diagram showing electronic equipment. [Figure 21] A diagram showing the source-drain band structure of a MOS transistor using an oxide semiconductor. [Figure 22] Figure 19 shows the state where a positive voltage is applied to the drain side. [Figure 23] This is an energy band diagram of the MOS structure of an oxide semiconductor MOS transistor, showing the case where (A) the gate voltage is positive and (B) the gate voltage is negative. [Figure 24] A diagram showing the source-drain band structure of a silicon MOS transistor. [Figure 25] A diagram showing the initial characteristics of the fabricated transistor. [Figure 26] A top view showing the fabricated transistor. [Figure 27] A diagram showing the electrical characteristics of the fabricated transistor. [Figure 28] A diagram illustrating an example of the procedure for supplying and stopping signals to a drive circuit. [Modes for carrying out the invention]

[0028] An embodiment according to one aspect of the present invention will be described in detail with reference to the drawings. However, this invention The present invention is not limited to the following description and may take any form without departing from the spirit and scope of the present invention. It will be easily understood by those skilled in the art that the details can be changed in various ways. The description of the present invention is not limited to the content of the description. In this context, symbols indicating the same object shall be common across different drawings.

[0029] In each of the embodiments and examples described below, unless otherwise specified, This specification may be implemented in combination with other embodiments and examples described herein as appropriate. It is Noh.

[0030] (Embodiment 1) In this embodiment, an example of a display device according to one aspect of the present invention will be described. In particular, the table An example of the pixel configuration provided in the pixel section of a display device will be explained with reference to Figures 1 to 6. ru.

[0031] Figure 1 shows an example of the configuration of a display device according to one aspect of the present invention. The display device has a pixel section 202 in which multiple pixels 201 are arranged in a matrix, on a substrate 2 It is provided on 00. And the display device is a circuit that drives multiple pixels 201 It has a scan line drive circuit 203 and a signal line drive circuit 204. The pixel 201 is a scan line drive Scan signals supplied by the first wiring 121 (scan line) electrically connected to circuit 203 The number determines whether each row is selected or not. Additionally, the scanning signal... The selected pixel 201 is electrically connected to the second wiring 1 of the signal line drive circuit 204. 22 (signal line) provides video voltage (video signal, image signal, video) from the second wiring 122. A signal (also called video data) is supplied. Furthermore, pixel 201 has a pair of electrodes. A light-emitting element is provided, and a power supply is connected to one electrode of this light-emitting element to provide potential. Lines 123 are electrically connected.

[0032] In Figure 1, the scan line drive circuit 203 and the signal line drive circuit 204 are located on the substrate 20. The present invention describes a configuration provided on 0, but is not limited to this configuration. either the scan line drive circuit 203 or the signal line drive circuit 204 is located on the substrate 200. It may also be a configuration in which only the pixel portion 202 is provided on the substrate 200. It may be possible.

[0033] Furthermore, in Figure 1, multiple pixels 201 are arranged in a matrix (stripe arrangement). The present invention is not limited to this configuration, although an example is shown. That is, pixel 201 In terms of layout configuration, we will adopt not only stripe arrangement, but also delta arrangement, Bayer arrangement, etc. It is possible.

[0034] Furthermore, the display method in the pixel section 202 may be a progressive method or an interlaced method, etc. It can be used. Also, when displaying in color, the color elements controlled by pixels are RG. It is not limited to the three colors B (R stands for red, G for green, and B for blue). For example, RGBW (W stands for white). (representing RGB), or RGB with one or more additional colors such as yellow, cyan, magenta, etc. Furthermore, the size of the display area for each dot of the color element may differ. However, this development This is not limited to color display devices, but also applies to monochrome display devices. It is also possible to do so.

[0035] Furthermore, in Figure 1, the number of the first wiring 121 and the second wiring 122 are, respectively, the number of pixels. The diagram shows a one-to-one correspondence between the number of rows and columns, but the present invention is not limited to this configuration. It is not determined. For example, between adjacent pixels, the first wiring 121 or the second wiring 122 is shared. A configuration in which a component drives pixel 201 is also possible.

[0036] Figure 2 is an equivalent circuit diagram showing an example of the configuration of pixel 201 in Figure 1. This is not limited to the pixel configuration shown in Figure 2.

[0037] Pixel 6400 contains a first transistor (hereinafter referred to as a switching transistor). (There is a 6401) and the second transistor (hereinafter referred to as the driving transistor) A 6402 and a light-emitting element 6404 are provided.

[0038] The first transistor 6401 has its gate electrically connected to scan line 6406, and the first One of the electrodes (source electrode and drain electrode) is electrically connected to signal line 6405, and the second The electrodes (the source electrode and the other drain electrode) are connected to the gate of the second transistor 6402. They are electrically connected. Also, the second transistor 6402 is connected to the first electrode (source electrode). The second electrode (and one of the drain electrodes) is electrically connected to the power line 6407, and the second electrode (source power) The other electrode (the pole and the drain electrode) is electrically connected to the first electrode (pixel electrode) of the light-emitting element 6404. It continues. Furthermore, the second electrode of the light-emitting element 6404 corresponds to the common electrode 6408. Also, in Figure 2, there is a capacitance between the gate of the second transistor 6402 and the power line 6407. Although the present invention is configured to include element 6410, it is not limited to this configuration. For example, Between the gate of transistor 6402 2 and the second electrode of transistor 6402 A configuration that includes a capacitive element may also be used.

[0039] The common electrode 6408 is electrically connected to the common potential line so that a low power supply potential is applied. It is configured. Furthermore, power line 6407 is configured to be supplied with a high power potential. The low power supply potential is defined as the low power supply potential set on power line 6407 relative to the high power supply potential. The potential is the potential that satisfies the high power supply potential. Specific examples of low power supply potentials include GND and 0V. It can be raised. Note that the potentials of the high power supply potential and the low power supply potential are the potential difference between the high power supply potential and the low power supply potential. Set each of them so that it is at least equal to or greater than the forward threshold voltage of the light-emitting element 6404. It is necessary.

[0040] In this embodiment, the transistor having an oxide semiconductor layer is the first transistor It is used as transistor 6401. In this case, the first transistor 6401 is n channel It is an n-channel type transistor. The second transistor, 6402, is an n-channel type transistor. Either a transistor or a p-channel transistor may be used. Also, the second Rangista 6402 may have a configuration using an oxide semiconductor layer as the active layer, or silicon A configuration using a silicon layer may also be used. When a silicon layer is used as the active layer, an amorphous silicon layer may be used. A silicon layer may be used, but a polycrystalline silicon layer is preferred. The second transistor, 6402, is an n-channel type transistor, and the oxide semiconductor layer We will now explain the case where this is used as the active layer.

[0041] Next, Figure 3 shows an example of a cross-sectional view of the first transistor 6401 in pixel 6400. The transistor 106 shown in Figure 3 corresponds to the first transistor 6401. It has a bottom-gate structure. Furthermore, the oxide semiconductor layer 103 which forms the channel region It has a first wiring 101 on the lower side that functions as a gate electrode, and an oxide semiconductor layer 103 between them. On the opposite side of the first wiring 101, sandwiched between them, is the first electrode (one of the source electrode and drain electrode). ) 102A, and a second electrode (the other of the source electrode and drain electrode) 102B It is also called an inverse staggered transistor.

[0042] A first wiring 101 is provided on the substrate 111 via an underlayment 112. Wiring 101 functions as the gate of transistor 106. And the first wiring 101 This could be the scan line itself that is electrically connected to the scan line drive circuit, or the scan line and the electric The wiring may be electrically connected.

[0043] Furthermore, a gate insulating film 113 is provided so as to cover the first wiring 101. An oxide semiconductor layer 103 is provided on the gate insulating film 113. A first electrode 102A and a second electrode 102B are provided on the body layer 103. Electrode 1 102A and electrode 2 102B are electrically connected to the oxide semiconductor layer 103. It is configured such that one side functions as the source electrode and the other as the drain electrode. Even if the first electrode 102A is the signal line itself that is electrically connected to the signal line drive circuit It is fine, or it may be wiring that is electrically connected to the signal line.

[0044] Furthermore, on the oxide semiconductor layer 103, the first electrode 102A, and the second electrode 102B, An oxide insulating layer 114 is provided, which functions as a passivation film. An opening is formed in layer 114, and in this opening, the fourth wiring 105 and the second electrical It is electrically connected to pole 102B. This fourth wiring 105 is connected to the second transistor. It is electrically connected to the gate of the ZISTA.

[0045] Next, the oxide semiconductor layer 103 will be described.

[0046] The oxide semiconductor layer 103 used in this embodiment is an oxide semiconductor transistor The amount of impurities that adversely affect electrical properties has been reduced to an extremely low level. It has been purified to a high degree. A typical example of an impurity that negatively affects electrical properties is hydrogen. Hydrogen is an impurity that can act as an electron donor in oxide semiconductors. If a large amount of hydrogen is present in an oxide semiconductor, the oxide semiconductor becomes N-type. Transistors using oxide semiconductors containing a large amount of hydrogen are normally-on This results in the inability to obtain a sufficient on / off ratio for the transistor. Therefore, in this specification, "high-purity oxide semiconductor" means that hydrogen in the oxide semiconductor is This refers to semiconductors that have been reduced to the greatest extent possible and are intrinsically or substantially intrinsically As an example of a semiconductor material, it contains a hydrogen concentration of at least 5 × 10⁻⁶ 19 / cm 3 Below Preferably 5 x 10 18 / cm 3 More preferably 5 × 10 17 / cm 3 Below Below, or 1 x 10 16 / cm 3 It is an oxide semiconductor with a carrier concentration of less than [value]. However, 1 x 10 14 / cm 3 Less than 1 × 10 12 / cm 3 Less than, more preferably is 1 x 10 11 / cm 3 Less than 6.0 × 10 10 / cm 3 Oxide semiconductors less than A film is used as the channel formation region to construct a transistor. Note that hydrogen in the oxide semiconductor layer Concentration measurement is performed using secondary ion mass spectrometry (SIMS). You can do this using Spectroscopy.

[0047] Furthermore, the energy gap of the oxide semiconductor layer 103 is 2 eV or more, preferably 2.5 eV. eV or higher, more preferably 3eV or higher.

[0048] In this way, high By using a pure oxide semiconductor layer in the channel formation region of the transistor, the off-current value is reduced. We can provide extremely small transistors.

[0049] For example, if the channel length of a transistor using a high-purity oxide semiconductor layer is 3 μm, Even if the width is 10mm, when the drain voltage is 1V and 10V, the gate When the voltage is in the range of -5V to -20V (off state), the drain current is 1 × 10⁻¹⁰ -1 3 It acts in such a way that it becomes less than or equal to A.

[0050] Here, the characteristics of a transistor using a high-purity oxide semiconductor layer are shown in Figures 21 to 21. We will explain using 27. Note that, for the sake of ease of understanding, we will assume an ideal situation in the following explanation. However, not all of these descriptions reflect reality. Also, the following explanation is merely... It should be noted that this is merely one consideration and does not affect the effectiveness of the invention.

[0051] Figure 21 shows the source-drain band of a transistor using a high-purity oxide semiconductor layer. This is a diagram showing the structure. The Fermi level of the highly purified oxide semiconductor is in an ideal state. In its normal state, it is located in the center of the forbidden band. In oxide semiconductors with reduced hydrogen concentration, minority carriers The number of holes (in this case) is zero or very close to zero.

[0052] In this case, the work function is φ m χ is the electron affinity of an oxide semiconductor, and the thermal equilibrium state of an oxide semiconductor. The carrier density (electron density) in state is N d The effective density of states in the conduction band of an oxide semiconductor is N c Therefore, the condition for the band structure to be flat at the metal-oxide semiconductor junction is φ m =χ-V t ln(N d / N c It will look like this.

[0053] Here, V t =k b T / q and k b : Boltzmann constant, T: temperature, q: elementary charge This equation φ m =χ-V t ln(N d / N c ) is the boundary, and if the right side is large, then O This results in a mixed contact. Here, φ m If =χ, then the Fermi level of the electrode metal at the junction surface. The conduction band levels of Bell and oxide semiconductors coincide. Oxide semiconductors have a band gap of 3. 0.5eV, electron affinity 4.3eV, intrinsic state (carrier density approximately 1 × 10⁻¹⁶) -7 / cm 3 )in Assuming that titanium (Ti) with a work function of 4.3 eV is used as the source and drain electrodes When using this method, no barrier is formed for electrons, as shown in Figure 21.

[0054] Figure 22 shows a transistor using an oxide semiconductor, where a positive voltage is applied to the drain side. This is a diagram showing the state after purification. Because oxide semiconductors have a large band gap, high purity is achieved. The intrinsic carrier density of oxide semiconductors that are non-intrinsic or substantially intrinsic is zero or very close to zero. In this state, a positive voltage is applied to the gate, and a voltage is applied between the source and drain. If so, it can be understood that carriers (electrons) are injected from the source side and can flow to the drain side. It can be done.

[0055] Figure 23(A) shows the energy band diagram of the MOS structure when the gate voltage is positive. This shows the case of a transistor using an oxide semiconductor. Note that in the figure, G E represents the gate electrode, GI represents the gate insulating film, and OS represents the oxide semiconductor. In addition, since highly purified oxide semiconductors have almost no thermally excited carriers, No carriers accumulate near the insulating film. However, as shown in Figure 22, carriers do not accumulate near the source side. The injected carrier can then propagate.

[0056] Figure 23(B) is the energy band diagram of the MOS structure when the gate voltage is negative. This shows the case in transistors using oxide semiconductors. A minority in oxide semiconductors Since the carriers (holes) are virtually zero, the current between the source and drain is infinitesimally zero. It will be close to that value.

[0057] Figure 24 shows the band diagram of a transistor using silicon semiconductors. The intrinsic carrier density of a semiconductor is 1.45 × 10⁻¹⁶. 10 / cm 3 (300K) and at room temperature Carriers are present even at room temperature. This is because thermally excited carriers exist even at room temperature. It means that it is present. In practical terms, it is silicon to which impurities such as phosphorus or boron have been added. Since a wafer is used, it is actually 1 x 10 14 / cm 3 The above carriers are silicon It exists in semiconductors and contributes to source-drain conduction. Furthermore, silicon semiconductors Since the band gap is 1.12 eV, a transistor using silicon semiconductors is warm The off-current will fluctuate significantly depending on the degree.

[0058] Thus, simply applying a broad-bandgap oxide semiconductor to a transistor... Instead, the amount of impurities such as hydrogen that form the donor is reduced as much as possible, and the carrier concentration is set to 1 × 10⁻⁶. 14 / cm 3 Less than 1 × 10 12 / cm 3 Less than 1 × 10 11 / c m 3 Less than 6.0 × 10 10 / cm 3 By making it less than, practical operation By eliminating carriers that are thermally excited by temperature, and only using carriers injected from the source side... This allows the transistor to operate. This enables the off-current to be 1 × 10⁻⁶. -13 A It can be reduced to the following level, and the off-current will hardly change with temperature changes, making it extremely stable. A working transistor can be obtained.

[0059] Next, the measurement of the off-current in the evaluation element (also called TEG) is described below.

[0060] 200 transistors with L / W = 3μm / 50μm are connected in parallel, and L / W = 3μm / The initial characteristics of a 10,000 μm transistor are shown in Figure 25. Here, Vg is set to -20V~ The voltage range is shown up to +5V. A top view is also shown in Figure 26(A), with a portion of it enlarged. The top view is shown in Figure 26(B). The area enclosed by the dotted line in Figure 26(B) is L / W = 3 μm / 5 This is a single-stage transistor with a thickness of 0 μm and a lob of 1.5 μm. The initial characteristics of the transistor are... To measure, the substrate temperature was set to room temperature, and the source-drain voltage (hereinafter referred to as drain voltage or Let Vd be 10V, and the source-gate voltage (hereinafter referred to as gate voltage or Vg) be 10V. (u) Source-drain current (hereinafter referred to as drain) when the voltage is varied from -20V to +20V. The characteristics of the change in current (or Id), i.e., the Vg-Id characteristics, were measured.

[0061] As shown in Figure 25, a transistor with a channel width W of 10,000 μm has a Vd of 1V and At 10V, the off-current is 1 × 10⁻⁶ -13 [A] The following applies to the measuring instrument (semiconductor parallel Meter analyzer, Agilent 4156C (manufactured by Agilent Corporation) Resolution (1 It is below 00fA.

[0062] Next, we will explain the method used to fabricate the measured transistor.

[0063] First, a silicon nitride layer is formed on the glass substrate as a base layer by the CVD method, and then the silicon nitride layer A silicon oxide nitride layer was formed on top. A gate electrode was formed on the silicon oxide nitride layer by sputtering. A tungsten layer was formed. Here, the tungsten layer was selectively etched to form the gate electrode. It formed a pole.

[0064] Next, a 100 nm thick silicon oxide nitride layer is applied to the gate electrode as a gate insulating layer by CVD. A sublayer was formed.

[0065] Next, an In-Ga-Zn-O-based metal oxide layer is applied to the gate insulating layer by sputtering. Using a GET (molar ratio, In2O3:Ga2O3:ZnO=1:1:2), thickness 5 A 0 nm oxide semiconductor layer was formed. Then, the oxide semiconductor layer was selectively etched. Island-shaped oxide semiconductor layers were formed.

[0066] Next, the oxide semiconductor layer was subjected to a first process in a clean oven under a nitrogen atmosphere at 450°C for 1 hour. Heat treatment was performed.

[0067] Next, a titanium layer (thickness 150n) is placed on the oxide semiconductor layer as the source electrode and drain electrode. m) was formed by sputtering. Here, the source electrode and drain electrode were selectively etched. Assuming that the channel length L of one transistor is 3 μm and the channel width W is 50 μm, By connecting 200 units in parallel, we achieved a ratio of L / W of 3 μm / 10,000 μm.

[0068] Next, a protective insulating layer is created in contact with the oxide semiconductor layer using reactive sputtering. A silicon oxide layer was formed with a thickness of 300 nm. Here, the silicon oxide layer, which is a protective insulating layer, was selectively... The material was etched to form openings on the gate electrode, source electrode, and drain electrode. Next, a second heat treatment was performed at 250°C for 1 hour under a nitrogen atmosphere.

[0069] Then, before measuring the Vg-Id characteristics, the samples were heated at 150°C for 10 hours.

[0070] A bottom-gate transistor was fabricated using the above process.

[0071] As shown in Figure 25, the off-current of the transistor is 1 × 10⁻⁶ -13 [A] is about the same as This is because the hydrogen concentration in the oxide semiconductor layer was sufficiently reduced during the above manufacturing process. The hydrogen concentration in the oxide semiconductor layer is 5 × 10⁻⁶. 19 atoms / cm 3 The following are preferred 5 x 10 18 atoms / cm 3 More preferably 5 × 10 17 / cm 3 The following, ta is 1 x 1016 atoms / cm 3 It shall be less than [amount]. Note that the hydrogen concentration in the oxide semiconductor layer is measured Secondary ion mass spectrometry (SIMS) This is done using ectroscopy.

[0072] Furthermore, while examples using In-Ga-Zn-O based oxide semiconductors were shown, the method is not particularly limited. Other oxide semiconductor materials, for example, In-Sn-Zn-O systems, Sn-Ga-Zn-O systems, Al-Ga-Zn-O series, Sn-Al-Zn-O series, In-Zn-O series, In-Sn-O Systems such as Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system, etc. It can be used. Furthermore, as an oxide semiconductor material, 2.5 to 10 wt% of AlOx can be mixed. In-Al-Zn-O systems containing added silicon, or In-Zn-O systems containing 2.5-10 wt% silicon. You can also use this.

[0073] Furthermore, the carrier concentration of the oxide semiconductor layer measured by the carrier measuring instrument is 1 × 10⁻⁶ 14 / cm 3 Less than 1 × 10 12 / cm 3 Less than 1 × 10 11 / c m 3 Less than 6.0 × 10 10 / cm 3 It is less than. That is, the carrier of the oxide semiconductor layer The concentration can be made as close to zero as possible. Furthermore, the specific method for measuring the carrier concentration is as follows: For example, a MOS capacitor is fabricated, and the CV measurement results of the MOS capacitor (CV One method is to determine the characteristics by evaluating them.

[0074] Furthermore, the channel length L of the transistor can be set to between 10 nm and 1000 nm. In this case, the operating speed of the circuit can be increased, and because the off-current value is extremely small, it is even lower It can also be used to reduce power consumption.

[0075] Furthermore, in the transistor's off state, the oxide semiconductor layer is treated as an insulator for circuit design. It is possible to do so.

[0076] Next, the temperature characteristics of the off-current for the transistors fabricated in this embodiment were evaluated. Temperature characteristics are considered in relation to the environmental resistance and performance maintenance of the final product in which the transistor is used. This is important in that regard. Naturally, the smaller the amount of change, the better, as it increases the degree of freedom in product design. .

[0077] Temperature characteristics were measured using a constant temperature bath at -30, 0, 25, 40, 60, 80, 100, and 12 The substrates on which transistors were formed at each temperature of 0°C were kept at a constant temperature, and the drain voltage was set to 6 The Vg-Id characteristics were obtained by varying the gate voltage (V) from -20V to +20V.

[0078] Figure 27(A) shows the Vg-Id characteristics measured at each of the above temperatures, superimposed. Figure 27(B) shows an enlarged view of the off-current region enclosed by the dotted line. The curve at the right end, indicated by the arrow, is the curve obtained at -30°C, and the curve at the left end is the curve obtained at 120°C. The curve showing the gain lies somewhere in between. The temperature dependence of the on-current is almost negligible. On the other hand, As is also evident in the enlarged view of Figure 27(B), the off-current is when the gate voltage is -20V Except for the immediate vicinity, the resolution of the measuring instrument is 1 × 10⁻⁶ at all temperatures. -12 [A] The following Furthermore, temperature dependence is not observed. That is, even at a high temperature of 120°C, the off-current is 1 × 10 -12 [A] The following conditions are maintained, taking into account that the channel width W is 10,000 μm. Then, 1 × 10 -16 The value is less than [A / μm], indicating that the off-current is very small. .

[0079] Transistors using highly purified oxide semiconductors (purified OS) are off-voltage. The temperature dependence of the flow is almost nonexistent. This is because, as shown in the band diagram of Figure 21, the oxide semi-semi As the purity of the conductor is increased, the conductivity type approaches the intrinsic type, and the Fermi level Because it is located in the center of the forbidden zone, it can be said that it does not exhibit temperature dependence. Also, this is oxidation The energy gap of the semiconductor is 3 eV or more, and there are very few thermally excited carriers. This is also due to the fact that the source and drain regions are in a degenerate state, and therefore temperature This is a factor that prevents the appearance of dependence. The operation of the transistor involves the acid from the degenerate source region. This is mostly due to carriers injected into the semiconductor, and the carrier density is temperature-dependent. The absence of this property explains the above characteristic (no temperature dependence of the off-current).

[0080] As described above, the channel width W of the transistor is 1 × 10 4 It is μm and the channel length is 3 Even with a μm element, the off-current is 10 -13 A or less, Subthreshold Sin Excellent electrical properties with a G value (S value) of 0.1V / dec. (gate insulating film thickness 100nm) This is how the purity is increased so that the oxide semiconductor contains as few impurities as possible. This improves the operation of the transistor. In other words, the above-mentioned acid A transistor having an oxide semiconductor layer can have an off-current of 10 aA or less per 1 μm channel width / μm (1×10 -17 A / μm), and preferably 1 aA / μm (1×10 - 18 A / μm) or less. By using a transistor with an extremely small current value (off-current value) in the off state as the first transistor 6401, the holding time of an electrical signal such as a video signal can be extended. For example, the writing interval is 10 seconds or more, preferably 30 seconds or more, and more preferably 1 minute or more and less than 10 minutes. By increasing the writing interval, the effect of suppressing power consumption can be enhanced.

[0081] On the other hand, for example, in a transistor having low-temperature polysilicon, the off-current is estimated to be equivalent to 1×10 -1 2 A / μm, and the design and so on are carried out based on this. Therefore, in a transistor having an oxide semiconductor, compared with a transistor having low-temperature polysilicon, when the holding capacitance is the same (about 0.1 pF), the voltage holding period can be extended by about 10 times. Also, in the case of a transistor having amorphous silicon, the off-current per 1 5 μm channel width is 1×10 A / μm or more. Therefore, when the holding capacitance is the same (about 0.1 pF), the transistor using a high-purity oxide semiconductor can extend the voltage holding period by 10 -13 times or more compared to the transistor using amorphous silicon. 4 times or more.

[0082] ​As an example, in a pixel with a transistor using low-temperature polysilicon, the display is 60f It is done at frames per second (16 msec per frame). This is the same even for still images. Therefore, if the rate is reduced (the writing interval is extended), the voltage of the pixels decreases and the display becomes affected. This is because it causes problems. On the other hand, a transistor having the aforementioned oxide semiconductor layer is used In this case, because the off-current is small, the hold period for one signal write is 10 5 Double that, 1600 It can be reduced to about a second. And even with a small number of image signal write cycles, the static display on the display unit can be maintained. It can display still images. Because the retention period can be extended, it is particularly useful when displaying still images. This reduces the frequency of writing signals. For example, displaying a single still image. The number of times the pixels are written during the period (approximately 1600 seconds) is calculated using low-temperature polysilicon. When using a lampistor, 10 5 While it is necessary to use the aforementioned oxide semiconductor layer If a transistor is used, it is possible to perform the operation in a single step.

[0083] Figure 4 shows the relationship between the writing period to the display unit and the retention period (also called the 1-frame period). This is shown. In Figure 4, periods 251 and 252 correspond to the retention period, and period 261, 262 corresponds to the writing period to the display unit. It is equipped with the aforementioned high-purity oxide semiconductor layer. Transistors can have a long retention period, which is especially useful when displaying still images. The number of times the pixels are written to can be significantly reduced. Therefore, the display switching is less frequent. When displaying still images, etc., power consumption can be reduced.

[0084] Furthermore, in still image display, the voltage applied to the gate of the drive transistor during the holding period is Considering the voltage retention rate, a refresh operation may be performed as needed. For example, the drive transistor A predetermined level relative to the voltage value (initial value) immediately after writing a signal to the gate of the sta. The refresh operation should be performed when the voltage drops to a predetermined level. The pressure should preferably be set to a level where no flickering is noticeable relative to the initial value. Specifically, If the display target is video, the value should be 1.0% lower than the initial value, preferably 0.3% lower. Each time this happens, it is preferable to perform a refresh operation (rewrite). If it is a character, every time it becomes 10% lower than the initial value, preferably 3% lower, then It is preferable to perform a refresh operation (rewrite).

[0085] Next, as an example of a method for driving the light-emitting element 6404, we will explain a method for performing analog grayscale driving. The forward voltage of the light-emitting element 6404 + the gate of the second transistor 6402 is connected to the gate of the second transistor 6402. A voltage greater than or equal to Vth is applied to the transistor 6402. Here, the forward current of the light-emitting element 6404 is applied. Voltage refers to the voltage required to achieve the desired brightness, and includes at least the forward threshold voltage. For example, a video signal (image signal) such that the second transistor 6402 operates in the saturation region. By inputting this, current can be supplied to the light-emitting element 6404. Note that the second transient To operate the 6402 in the saturation region, the potential of the power line 6407 must be set to the second transient It is best to set it higher than the gate potential of the 6402. By making the video signal analog, By supplying current to the light-emitting element 6404 according to the video signal, analog grayscale driving can be performed. ru.

[0086] Furthermore, the voltage input voltage drive method allows for area gradation display using multiple pixels, and different emission colors. Color representation using a combination of multiple pixels (e.g., R, G, B), (e.g., R+G, G +B, R+B, R+G+B, etc. are possible. In the case of a voltage input voltage drive method, the second The gate of transistor 6402 is either sufficiently turned on by the second transistor 6402, A signal is input that results in one of two states: either off or off. In other words, the second transistor 64 02 is operated in the linear region. Furthermore, the second transistor 6402 is operated in the linear region. To achieve this, the voltage of power line 6407 must be lower than the gate potential of the second transistor 6402. It is good to do this. Specifically, the threshold voltage of the second transistor 6402 is set to the potential of the power line. You just need to input a voltage signal that provides a potential greater than or equal to the added value into signal line 6405.

[0087] Furthermore, whether the light-emitting element 6404 is driven by analog gradation or by voltage input voltage, The off-current of the switching transistor 6401 is, for example, 1 × 10⁻⁶ -16 Suppressed to A or below Therefore, the gate potential of the second transistor 6402 is held for a long period. Furthermore, even with a small number of image signal write cycles, still images can be displayed on the display unit. This allows for a reduction in the frequency of writing to the data, thereby lowering power consumption. Furthermore, the pixel configuration shown in Figure 2 is not limited to this. For example, new pixels may be added to the pixels shown in Figure 2. Switches, resistors, capacitives, transistors, or logic circuits may be added.

[0088] In particular, one example of a light-emitting element is a light-emitting element that utilizes electroluminescence. It is possible that the light-emitting material of an electroluminescent light-emitting device is an organic compound. They are distinguished by whether they are inorganic compounds; generally, the former are organic EL elements, and the latter are inorganic EL It is called an L element.

[0089] An organic EL element consists of a pair of electrodes (anode and cathode) and an organic compound placed between the pair of electrodes. It has a layer containing a substance. The potential of the anode is made higher than the potential of the cathode, and the anode is placed on the layer containing the organic compound. Holes are injected from the cathode, and electrons are injected from the cathode. The electrons and holes (carriers) contain organic compounds. It emits light when it recombines in the layer.

[0090] Inorganic EL elements are classified into dispersed inorganic EL elements and thin-film inorganic EL elements depending on their element configuration. It is classified as follows: Dispersed inorganic EL elements have a light-emitting layer in which particles of light-emitting material are dispersed in a binder. It possesses a donor-acceptor level, and the luminescence mechanism utilizes donor-acceptor levels. This is acceptor-recombination type light emission. Thin-film inorganic EL elements sandwich the light-emitting layer between dielectric layers. Furthermore, it has a structure where it is sandwiched between electrodes, and the light emission mechanism involves the inner-shell electron transition of metal ions. The type of emission used is localized emission.

[0091] In this embodiment, an organic EL element is used as the light-emitting element, but the present invention The present invention is not limited to this configuration. In other words, the present invention uses an inorganic EL element as the light-emitting element. It is also possible to use it.

[0092] Next, the cross-sectional structure of a display device having a light-emitting element will be explained using Figure 5. Driving transistors 7001 and 7011 as illustrated in Figures 5(A), 5(B), and 5(C). 7021 may be a transistor using a high-purity oxide semiconductor layer, or silicon A transistor using layers may also be used. In this embodiment, the driving transistor 7 When a high-purity oxide semiconductor layer is used as the active layer for 001, 7011, and 7021, I will explain.

[0093] The light-emitting element illustrated in this embodiment has a pair of electrodes (a first electrode and a second electrode) between them. It has a structure in which an EL layer (electroluminescent layer) is sandwiched. First electrode and second One electrode functions as the anode and the other as the cathode.

[0094] The material used as the anode is a metal or alloy with a large work function (specifically, 4.0 eV or higher). Conductive compounds, or mixtures thereof are preferred. Specifically, indium oxide-acid Contains tin oxide (ITO: Indium Tin Oxide), silicon, or silicon dioxide. Indium oxide-tin oxide, indium oxide-zinc oxide (IZO:Indium Indium oxide (I) containing zinc oxide, tungsten oxide, and zinc oxide. Examples include WZO. Other examples include gold (Au), platinum (Pt), nickel (Ni), and tungsten. Gusten (W), chromium (Cr), molybdenum (Mo), iron (Fe), cobalt (Co) copper (Cu), palladium (Pd), or nitrides of metallic materials (e.g., titanium nitride), etc. These are some examples.

[0095] The material used as the cathode is a metal or alloy with a low work function (specifically, 3.8 eV or less). Electrically conductive compounds, or mixtures thereof are preferred. Specifically, the periodic table of elements. Elements belonging to Group 1 or Group 2, namely lithium (Li) and cesium (Cs), etc. Potassium metals, magnesium (Mg), calcium (Ca), strontium (Sr), etc. Examples include alkali metals and alkaline earth metals. Also, alloys containing alkali metals or alkaline earth metals ( For example, MgAg, AlLi can also be used. Also, europium (Eu), i... Rare earth metals such as terbium (Yb), or alloys containing rare earth metals, can also be used. . Furthermore, if an electron injection layer in contact with the second electrode is provided as part of the EL layer, the work function becomes large. Regardless of size, various conductive materials such as Al, Ag, and ITO are used as the second electrode. These conductive materials can be produced using sputtering, inkjet, and spin coating methods. It is possible to form a film using the following methods.

[0096] While the EL layer can be composed of a single layer, it is usually made up of a multilayer structure. The stacked structure of the EL layer is not particularly limited, and includes a layer containing a material with high electron transport properties (electron transport (a layer) or a layer containing a material with high hole transport properties (hole transport layer), containing a material with high electron injection properties Layer (electron injection layer), layer containing a material with high hole injection potential (hole injection layer), bipolar (electron A layer containing a substance (and a substance with high hole transport properties), a layer containing a light-emitting substance (light-emitting layer), etc., are appropriately combined. They can be combined to form a structure. For example, a hole injection layer, a hole transport layer, a light-emitting layer, an electron transport layer, and an electron It can be constructed by appropriately combining sub-injection layers, etc. It also functions as a charge generation layer. The configuration includes multiple EL layers separated by an intermediate layer, placed between the first electrode and the second electrode. That's good too.

[0097] Furthermore, in order to extract light from the light-emitting element, at least one of the first electrode or the second electrode This is formed from a light-transmitting conductive film. The light emitted by the light-emitting element formed on the substrate is extracted. When classifying light-emitting elements by direction, the side of the substrate where the light-emitting elements are formed is the upper side. Bottom emission, which is extracted from the surface opposite to the surface on which the light-emitting element of the substrate is formed, and surface emission, and double-sided emission, which is extracted from both the surface on which the light-emitting element of the substrate is formed and the surface opposite thereto, are three representative structures of light-emitting elements. The present invention can be applied to light-emitting elements having any emission structure. There are three representative structures of light-emitting elements: bottom emission, which is extracted from the surface opposite to the surface on which the light-emitting element of the substrate is formed, surface emission, and double-sided emission, which is extracted from both the surface on which the light-emitting element of the substrate is formed and the surface opposite thereto. The present invention can be applied to light-emitting elements having any emission structure. There are three representative structures of light-emitting elements: bottom emission, which is extracted from the surface opposite to the surface on which the light-emitting element of the substrate is formed, surface emission, and double-sided emission, which is extracted from both the surface on which the light-emitting element of the substrate is formed and the surface opposite thereto. The present invention can be applied to light-emitting elements having any emission structure. .

[0098] When the EL layer is laminated on the first electrode, the peripheral portion of the first electrode is covered with a partition wall. The partition wall may be formed using an organic resin film such as polyimide, acrylic resin, polyamide, or epoxy resin, an inorganic insulating film, or an organic polysiloxane. However, for example, it is preferable to form the partition wall using a photosensitive resin material. When a photosensitive resin material is used, the side wall of the opening of the partition wall becomes an inclined surface having a continuous curvature, and the process of forming a resist mask can be reduced. When a photosensitive resin material is used, the side wall of the opening of the partition wall becomes an inclined surface having a continuous curvature, and the process of forming a resist mask can be reduced. .

[0099] A color filter can also be formed between the substrate and the light-emitting element. The color filter may be formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using photolithography technology, or the like. When a color filter is formed between the substrate and the light-emitting element, the color filter may be formed by a droplet ejection method such as an inkjet method, a printing method, an etching method using photolithography technology, or the like.

[0100] In addition, an overcoat layer may be formed on the color filter, and then a protective insulating layer may be formed. When the overcoat layer is provided, the unevenness caused by the color filter can be flattened. When the protective insulating layer is formed, the phenomenon of impurities diffusing from the color filter to the light-emitting element can be prevented. When the overcoat layer is provided, the unevenness caused by the color filter can be flattened. When the protective insulating layer is formed, the phenomenon of impurities diffusing from the color filter to the light-emitting element can be prevented. .

[0101] When the light-emitting element is formed on the protective insulating layer, the overcoat layer, and the insulating layer on the transistor, the protective insulating layer, the overcoat layer, and the insulating layer are penetrated, and the source of the transistor is A contact hole reaching the electrode or the drain electrode is formed. In particular, when the contact hole is formed by laying out the contact hole at a position overlapping the above-described partition wall, reduction of the aperture ratio can be suppressed, which is preferable. and thus is preferable. Next, an example of the configuration of a pixel having a light-emitting element with a bottom emission structure will be described. A cross-sectional view of a cut surface including a driving transistor 7011 and a light-emitting element 7012 provided in the pixel is shown in FIG. 5(A).

[0102] ).

[0103] The driving transistor 7011 has an insulating layer, an oxide semiconductor layer, a source electrode and a drain electrode, a gate insulating layer, and a gate electrode on a substrate, and wiring layers are electrically connected to the source electrode and the drain electrode, respectively.

[0104] An insulating layer 7031 is formed to cover the driving transistor 7011, and a color filter 7033 having an opening is provided on the insulating layer 7031. A conductive film 7017 having translucency is formed on an overcoat layer 7034 and a protective insulating layer 7035 formed to cover the color filter 7033. The drain electrode of the driving transistor 7011 and the conductive film 7017 are electrically connected through an opening formed in the overcoat layer 7034, the protective insulating layer 7035, and the insulating layer 7031. The first electrode 7013 of the light-emitting element 7012 is provided in contact with the conductive film 7017. [[ID=,33]]<00,00924>

[0105] The light-emitting element 7012 includes an EL layer between the first electrode 7013 and the second electrode 7015. [[ID=4-3]]

[0106] Examples of the conductive film 7017 having translucency include indium oxide containing tungsten oxide. ​​​​​​​​​​Indium zinc oxide containing tungsten oxide, indium oxide containing titanium oxide, acid Titanium oxide-containing indium tin oxide, indium tin oxide (hereinafter referred to as ITO), By using a film made of indium zinc oxide, silicon oxide-added indium tin oxide, etc. It is possible.

[0107] This section describes the case where the first electrode 7013 of the light-emitting element 7012 is used as the cathode. To clarify, when the first electrode 7013 is used as the cathode, a metal with a small work function is preferable. In Figure 5(A), the film thickness of the first electrode 7013 is such that it transmits light (preferably 5). (Approximately nm to 30 nm) For example, an aluminum film or M with a thickness of 20 nm. A g-Ag alloy film is used for the first electrode 7013.

[0108] Furthermore, after laminating a translucent conductive film and an aluminum film, selective etching is performed. A light-transmitting conductive film 7017 and a first electrode 7013 may be formed in this case, Etching can be performed using the same mask, which is preferable.

[0109] Furthermore, the second electrode 7015 formed on the EL layer 7014 is made of a material with a large work function. A material is preferred. In addition, a shielding film 7016, such as a light-blocking metal, is placed on the second electrode 7015. A metal that reflects light is used. In this embodiment, an ITO film is used as the second electrode 7015. Using this method, a Ti film is used as the shielding film 7016.

[0110] Furthermore, the color filter 7033 is covered with an overcoat layer 7034, and then a protective insulating layer is added. It is covered with 7035. Note that in Figure 5(A), the overcoat layer 7034 is shown as having a thin film thickness. The overcoat layer 7034 planarizes the unevenness caused by the color filter 7033 and is.

[0111] Also, contact holes formed in the overcoat layer 7034 and the protective insulating layer 7035 and reaching the drain electrode 7030 are arranged at positions overlapping the partition wall 7019. .

[0112] In the case of the pixel structure shown in FIG. 5(A), the light emitted from the light-emitting element 7012 is as indicated by the arrow emitted toward the first electrode 7013 side, passes through the color filter 7033, and exits outside the display device. goes.

[0113] Note that a conductive film having translucency is used as the gate electrode, source electrode, and drain electrode of the driving transistor 7011, and as the channel formation region of the driving transistor 7011 it is preferable to use a highly pure oxide semiconductor layer having translucency. In this case, as shown in FIG. 5(A ), the light emitted from the light-emitting element 7012 not only passes through the color filter 7033 and is emitted, but also passes through the driving transistor 7011 and is emitted, and the aperture ratio can be improved. Furthermore, by using a highly pure oxide semiconductor layer having translucency as the channel formation region of the driving transistor 7011, the off-current of the driving transistor 7011 can be made extremely small, so that compared with the conventional case, the area of the electrode for forming the storage capacitance can be reduced. Therefore, the aperture ratio can be further improved. Next, the configuration of a pixel having a light-emitting element with a double-sided emission structure will be described. The drive provided in the pixel

[0114] ​​Figure 5(B) shows a cross-sectional view of the cross-section including the dynamic transistor 7021 and the light-emitting element 7022. vinegar.

[0115] The drive transistor 7021 has an insulating layer, an oxide semiconductor layer, a source electrode and on the substrate. It has a drain electrode, a gate insulating layer, and a gate electrode, and the source electrode and drain electrode respectively The wiring layers are electrically connected and provided.

[0116] Furthermore, an insulating layer 7041 is formed covering the drive transistor 7021, and an insulating layer 704 A color filter 7043 having an opening is provided on 1. A light-transmitting conductive film 7027 is an overcoat layer 7044 formed over the color filter 7043 and It is formed on the insulating layer 7045. Note that this is the drain electrode of the drive transistor 7021. The conductive film 7027 is overcoat layer 7044, insulating layer 7045, and insulating layer 7041 It is electrically connected through an opening formed therein. The first electrode 7023 of 7022 is provided in contact with it.

[0117] The light-emitting element 7022 has an EL layer 7024 between the first electrode 7023 and the second electrode 7025. To hold between two things.

[0118] This section describes the case where the first electrode 7023 of the light-emitting element 7022 is used as the cathode. To clarify, the light-transmitting conductive film 7027 is the same as the conductive film 7017 shown in Figure 5(A). It is sufficient to form it as shown, and the first electrode 7023 is the same as the first electrode 7013 shown in Figure 5(A) They can be formed in the same way, and the EL layer 7024 is the same as the EL layer 7014 shown in Figure 5(A). Since it only needs to be formed in this way, a detailed explanation will be omitted here.

[0119] The second electrode 7025 formed on the EL layer 7024 functions as an anode here. Materials with a large work function, such as transparent conductive materials like ITO, IZO, and ZnO, are preferred. In this embodiment, ITO is formed as the second electrode 7025.

[0120] Furthermore, the color filter 7043, the overcoat layer 7044, and the protective insulating layer 7045 are The pixel has a color filter 7033 and an overcoat layer 703, as illustrated in Figure 5(A). Layer 4 and the protective insulating layer 7035 may be formed in the same manner.

[0121] In the case of the element structure shown in Figure 5(B), the light emitted from the light-emitting element 7022 is indicated by the arrow. The first electrode 7023 side and the second electrode 7025 side are injected in this manner, and the first electrode 70 The light from side 23 passes through color filter 7043 and exits the display device.

[0122] Note that in Figure 5(B), the gate electrode, source electrode, and drain electrode are translucent. This shows an example of constructing a drive transistor 7021 using a conductive film. Therefore, light emission A portion of the light emitted from element 7022 is directed to the color filter 7043 and the driving transistor. It will be launched after passing through 7021.

[0123] Furthermore, the overcoat layer 7044 and the protective insulating layer 7045 are formed, and the drain The contact hole reaching electrode 7040 is positioned to overlap with partition wall 7029. The layout involves overlapping the contact hole reaching the drain electrode with the partition wall 7029. This makes the aperture ratio on the second electrode 7025 side and the aperture ratio on the first electrode 7023 side almost the same. It is possible.

[0124] However, if both display surfaces of a double-sided injection-type light-emitting element are to be full-color displays, then the second Since the light from electrode 7025 does not pass through color filter 7043, a separate color filter is required. It is preferable to provide a sealing substrate equipped with a luter above the second electrode 7025.

[0125] Next, the configuration of a pixel having an upper surface emission light-emitting structure will be described. Figure 5(C) shows a cross-sectional view of the cross-section including the dynamic transistor 7001 and the light-emitting element 7002. vinegar.

[0126] The drive transistor 7001 has an insulating layer, an oxide semiconductor layer, a source electrode and on the substrate. It has a drain electrode, a gate insulating layer, and a gate electrode, and the source electrode and drain electrode respectively The wiring layers are electrically connected and provided.

[0127] Furthermore, an insulating layer 7051 is formed covering the drive transistor 7001, and an insulating layer 705 An insulating layer 7053 having an opening is provided on 1. The first electrode 7003 is an insulating layer It is formed on an insulating layer 7055 that covers 7053. The drain electrode of sta 7001 and the first electrode 7003 are insulated by insulating layer 7055 and insulating layer 70 It is electrically connected through the opening formed in 51.

[0128] The insulating layer 7053 is made of polyimide, acrylic resin, benzocyclobutene resin, and poly Resin materials such as amides and epoxy can be used. In addition to the above resin materials, low dielectric materials can also be used. Low-k materials, siloxane resins, PSG (phosphorus glass), BPSG (phosphorus glass) Boron glass, etc., can be used. Multiple insulating films formed from these materials can be used. The insulating layer 7053 may be formed by lamination. The method for forming the insulating layer 7053 is particularly Without limitation, depending on the material, sputtering, SOG, spin coating, dip, sputtering, etc. Ray coating, droplet ejection method (inkjet method, screen printing, offset printing, etc.), dock You can use a turner knife, roll coater, curtain coater, knife coater, etc. By forming the insulating layer 7053, for example, the irregularities caused by the drive transistor are made flat. It can be made possible. Also, it is formed in the insulating layer 7055 and the insulating layer 7053, and the drain electrode 7 The contact hole reaching 050 is positioned to overlap with partition wall 7009.

[0129] The light-emitting element 7002 has an EL layer 7004 between the first electrode 7003 and the second electrode 7005. It is held between them. In the light-emitting element 7002 illustrated in Figure 5(C), the first electrode 700 Let's explain the case where 3 is used as the cathode.

[0130] If the first electrode 7003 is made of the same material as the first electrode 7013 shown in Figure 5(A), However, in the light-emitting element with an upper surface emission structure shown in Figure 5(C), the first electrode 7003 is transparent It is preferable that the electrode does not have photochromic properties and instead has high reflectivity. By using electrodes, the efficiency of light extraction can be increased.

[0131] The first electrode 7003 may be, for example, an aluminum film or an aluminum film with aluminum as the main component. A composite alloy film, or an aluminum film laminated with a titanium film, is preferred. (Figure 5(C)) The first electrode 7003 uses a laminated film in which a Ti film, an aluminum film, and another Ti film are stacked in that order. ru.

[0132] Furthermore, the EL layer 7004 can be formed in the same manner as the EL layer 7014 shown in Figure 5(A), Furthermore, the second electrode 7005 can be formed in the same manner as the second electrode 7025 shown in Figure 5(B). Therefore, a detailed explanation will be omitted here.

[0133] In the case of the element structure shown in Figure 5(C), the light emitted from the light-emitting element 7002 is indicated by the arrow. The injection is directed toward the second electrode 7005.

[0134] When using the structure in Figure 5(C) to perform full-color display, for example, the light-emitting element 7002 is set to green. The light-emitting elements are configured such that one adjacent light-emitting element is red, and the other is blue. This will be used as a light-emitting element. In addition to the three types of light-emitting elements, there will also be four types of light-emitting elements, including a white light element. A light-emitting display device capable of full-color display may be manufactured.

[0135] Furthermore, if all of the multiple light-emitting elements arranged in the structure of Figure 5(C) are white light-emitting elements, A sealing substrate having a color filter or the like is placed above each light-emitting element, including sub-element 7002. A light-emitting display device capable of full-color display may be manufactured with the following configuration. By forming a material that exhibits light emission and combining it with color filters and color conversion layers, full color - It can be displayed.

[0136] Furthermore, if necessary, an optical film such as a circular polarizer may be provided.

[0137] Next, the appearance of a light-emitting display panel (also called a light-emitting panel) which corresponds to one form of display device, and The cross-section will be explained using Figure 6. Figure 6(A) shows a transistor formed on the first substrate. A plan view of a panel in which the zista and light-emitting element are sealed between the second substrate and the panel with a sealing material. Therefore, Figure 6(B) corresponds to the cross-sectional view at HI in Figure 6(A).

[0138] Pixel section 4502, signal line driving circuit 4503a, 45 provided on the first substrate 4501 03b, and the scan line drive circuits 4504a and 4504b are surrounded by a sealing material 450 5 is provided. Also, the pixel section 4502, the signal line driving circuits 4503a, 4503b, and A second substrate 4506 is provided on top of the scan line drive circuits 4504a and 4504b. Therefore, the pixel unit 4502, signal line driving circuits 4503a, 4503b, and scan line driving circuit 4 504a and 4504b consist of a first substrate 4501, a sealing material 4505, and a second substrate 4506. This seals the pixel section 4502 and signal line together with the filler material 4507. Drive circuits 4503a, 4503b and scan line drive circuits 4504a, 4504b are exposed to the outside air. A protective film that is highly airtight and minimizes degassing to prevent exposure (laminated film, purple) It is preferable to package (encapsulate) the product with an externally cured resin film or other cover material.

[0139] Furthermore, the first substrate 4501 is provided with a pixel section 4502 and a signal line driving circuit 4503a. , 4503b, and the scan line driving circuits 4504a and 4504b have multiple transistors. In Figure 6(B), the transistor 4510 included in the pixel section 4502 and the signal line drive Transistor 4509, included in the operating circuit 4503a, is shown as an example. Insulating layers 4542-4545 are provided on 09 and 4510. Also, insulating layer 454 The source power of transistor 4510 is supplied through the contact hole provided in 2-4545. The electrode or drain electrode 4848 and the first electrode layer 4517 of the light-emitting element 4511 are electrically connected. It continues.

[0140] In this embodiment, the transistor 4509 included in the signal line drive circuit 4503a , and as transistor 4510 included in pixel section 4502, a high-purity oxide semiconductor layer Each transistor has the following characteristics.

[0141] On the insulating layer 4542, the oxide semiconductor layer of the transistor 4509 for the drive circuit A conductive layer 4540 is provided in a position that overlaps with the channel formation region. The conductive layer 4540 is oxidized. By placing it in a position that overlaps with the channel formation region of the material semiconductor layer, BT stress test ( Change in threshold voltage of transistor 4509 before and after bias and temperature stress testing. The amount can be reduced. Note that in this specification, BT stress test (bias / temperature) A TRESS test is a test in which a high gate voltage is applied to a transistor in a high-temperature atmosphere. This refers to... Also, the conductive layer 4540 has the same potential as the gate electrode of transistor 4509. It's fine if it's different, and it can also function as a second gate electrode. Also, The potential of the conductive layer 4540 may be GND, 0V, or floating.

[0142] The light-emitting element 4511 consists of a first electrode layer 4517, an electroluminescent layer 4512, and a second electrode. Although it is a layered structure of layer 4513, it is not limited to the configuration shown here. From the light-emitting element 4511 The configuration of the light-emitting element 4511 can be appropriately changed to match the direction of the light being extracted.

[0143] The partition wall 4520 is formed using an organic resin film, an inorganic insulating film, or an organic polysiloxane. In particular, a photosensitive material is used, and the side walls of partition wall 4520 are formed with a continuous curvature. It is preferable to form it into a surface.

[0144] Even if the electroluminescent layer 4512 consists of a single layer, it is configured to be stacked with multiple layers. It doesn't matter whether it's done or not.

[0145] To prevent oxygen, hydrogen, moisture, carbon dioxide, etc. from entering the light-emitting element 4511, the second electrode A protective film may be formed on layer 4513 and partition wall 4520. The protective film may be a silicon nitride film. It can form silicon nitride oxide films, DLC films, and the like.

[0146] Also, signal line drive circuits 4503a, 4503b, scan line drive circuits 4504a, 4504 b, or the various signals and potentials applied to the pixel section 4502, FPC4518a, 451 It is supplied from 8b.

[0147] The connection terminal electrode 4515 has the same conductivity as the first electrode layer 4517 of the light-emitting element 4511. It is formed from a film. Also, the terminal electrode 4516 is the same as transistors 4509 and 4510. It is formed from the same conductive film as the source electrode and drain electrode.

[0148] The connecting terminal electrode 4515 connects to the terminals of FPC4518a and the anisotropic conductive film 4519. They are electrically connected via [a certain means].

[0149] The substrate located in the direction of light extraction from the light-emitting element 4511 must be translucent. In that case, glass plate, plastic plate, polyester film or acrylic film A translucent material such as lum is used.

[0150] Furthermore, in addition to inert gases such as nitrogen and argon, UV-curable resin can also be used as the filler 4507. Oils or thermosetting resins can be used, such as PVC (polyvinyl chloride), acrylic, Polyimide, epoxy resin, silicone resin, PVB (polyvinyl butyral) or EV A (ethylene vinyl acetate) can be used. For example, nitrogen can be used as a filler. That's all you need to do.

[0151] Additionally, a polarizing plate or circular polarizing plate (including elliptical polarizing plate) may be placed on the emission surface of the light-emitting element as needed. You may also appropriately provide optical films such as phase difference plates (λ / 4 plate, λ / 2 plate) and color filters. Furthermore, an anti-reflective coating may be provided on the polarizing plate or circular polarizing plate. For example, by the surface irregularities An anti-glare treatment can be applied to diffuse reflected light and reduce glare.

[0152] Furthermore, the present invention is not limited to the configuration shown in Figure 6. That is, the signal line drive circuit 4503a, 4503b and the scan line drive circuits 4504a and 4504b are mounted on a separately prepared board. The drive circuit may be implemented using a crystalline semiconductor film or a polycrystalline semiconductor film. Furthermore, the signal line drive circuit alone or partially, or the scan line drive circuit alone or partially, may be used separately. It may be implemented by creating a temporary structure.

[0153] (Embodiment 2) This embodiment describes a configuration that further reduces the power consumption of the display device. In addition to suppressing power consumption in the pixel section of the display device, the drive circuit section of the display device This section describes a configuration for suppressing power consumption.

[0154] Figure 7 shows an example of a block diagram of a display device. However, the present invention is not the configuration shown in Figure 7. It is not limited to that.

[0155] The display device 1000 shown in Figure 7 consists of a display panel 1001, a signal generation circuit 1002, and a memory circuit. It has a path 1003, a comparison circuit 1004, a selection circuit 1005, and a display control circuit 1006. Furthermore, the display panel 1001 has a drive circuit section 1007 and a pixel section 1008. The circuit section 1007 includes a gate line drive circuit 1009A and a signal line drive circuit 1009B. Furthermore, the gate line drive circuit 1009A and the signal line drive circuit 1009B have multiple pixels. It has the function of driving the pixel unit 1008.

[0156] The transistors constituting the pixel section 1008 are those described in Embodiment 1. In other words, as a switching transistor, an n-channel having a high-purity oxide semiconductor layer A Nell-type transistor is used. The driving transistor has a high-purity oxide semiconductor layer. The configuration may use a silicon layer, or the configuration may use a silicon layer, but in this embodiment In this case, the driving transistor is also an n-channel type transistor with a high-purity oxide semiconductor layer. This section explains when to apply the generator.

[0157] In this embodiment, one of the transistors constituting the pixel section 1008 is a switch As a transistor for tuning, an n-channel type transistor having a high-purity oxide semiconductor layer By using a sta, the retention time of data such as image signals can be extended. Therefore, the frequency of writing signals when displaying still images, etc., can be reduced. This allows for lower power consumption of display devices.

[0158] Furthermore, in this embodiment, when displaying a still image, all signals included in the pixel are... The drive circuit section is moved to stop the output of the signal supplied to the scan line and / or all scan lines. By doing so, power consumption can be suppressed not only in the pixel section but also in the drive circuit section. In other words, during the period in which the display device displays a still image, all signals included in the pixel section This implementation includes a period during which the output of signals supplied to the line and / or all scan lines is stopped. In this configuration, as one way to achieve low power consumption in the drive circuit section, the display device 1000 is the signal generation circuit 1002, memory circuit 1003, comparison circuit 1004, and selection circuit 10 05. It has a display control circuit 1006.

[0159] The signal generation circuit 1002 includes the gate line drive circuit 1009A and the signal line drive circuit 1009 It has the function of generating the signals (control signals) necessary to drive B. Circuit 1002 outputs a control signal to the drive circuit unit 1007 via wiring, and wiring The image signal (also called video voltage, video signal, or video data) is stored in the memory circuit 100 via the memory circuit 100. It has the function of outputting to 3. In other words, the signal generation circuit 1002 has the function of driving circuit section 1007 A control signal for driving the pixels, and a circuit for generating and outputting image signals to be supplied to the pixel section. That is the case.

[0160] Specifically, the signal generation circuit 1002 uses the gate line drive circuit 1009A as a control signal. , and the signal line drive circuit 1009B has a high power supply potential Vdd and a low power supply potential Vss The gate line drive circuit 1009A is supplied with a start pulse SP for the gate line drive circuit. The clock signal CK is supplied, and the signal line drive circuit 1009B has a stand for the signal line drive circuit. The signal generation circuit 1002 supplies a pulse SP and a clock signal CK. The signal generation circuit 1002 also generates moving images. Alternatively, it outputs image signal data for displaying a still image to the memory circuit 1003.

[0161] Furthermore, moving images are created by rapidly switching between multiple images that are time-divided into multiple frames. This refers to an image that is recognized as a moving image by the eye at an interval. Specifically, it refers to an image that is displayed 60 times per second (60 By switching between multiple images (frames), the flicker is reduced, and the image is perceived as moving by the human eye. A still image is a series of images. Unlike a moving image, a still image consists of multiple frames. Although it operates by rapidly switching between multiple time-divided images over a period of time, the continuous frame period For example, an image signal that does not change between the nth frame and the (n+1)th frame. It means that.

[0162] Furthermore, the signal generation circuit 1002 also has the function of generating image signals, latch signals, etc. It may also be the case that the signal generation circuit 1002 is the gate line drive circuit 1009A and / or This is a signal line drive circuit 1009B that stops the output of the pulse signal of each drive circuit. It may also have a function to output a set signal Res signal. In addition, each signal is a first cross The signal may be composed of multiple signals, such as a second clock signal and a second clock signal. .

[0163] Note that high power supply potential Vdd is a potential higher than the reference potential, while low power supply potential is a base This refers to a potential below the quasi-potential. Note that both high and low power supply potentials refer to the transistor's potential. It is desirable that the potential be sufficient for operation.

[0164] Voltage, by definition, is the potential difference between a given potential and a reference potential (for example, ground potential). This is often the case. Therefore, voltage, potential, and potential difference can be rephrased as potential, voltage, and voltage, respectively. It is possible to do so.

[0165] Furthermore, the output of the image signal from the signal generation circuit 1002 to the memory circuit 1003 is an analog signal. In the case of the number, the signal is converted to a digital signal via an A / D converter, etc., and stored in the memory circuit 100. The configuration should output to port 3.

[0166] The memory circuit 1003 stores multiple frames of image signals related to multiple frames. It has a frame memory 1010. The frame memory is, for example, DRAM (Dynamic Random Access Memory), SRAM (Static Random This can be implemented using memory elements such as Access Memory.

[0167] Furthermore, if the frame memory 1010 is configured to store image signals for each frame period, Often, there are no particular limitations on the number of frame memories. Also, frame memory 1 The image signal of 010 is selectively read out by the comparison circuit 1004 and the selection circuit 1005. It is.

[0168] The comparison circuit 1004 compares the image signals of consecutive frame periods stored in the memory circuit 1003. This circuit selectively reads out images, compares them, and detects the difference. If a difference is detected by comparing the image signals in the comparison circuit 1004, the difference is detected. In the consecutive frame period, it is determined to be a moving image. On the other hand, in the comparison circuit 1004 If no difference is detected by comparing the image signals, the continuous sequence in which no difference was detected During the frame period, it is determined to be a still image. That is, the difference in the comparison circuit 1004. The detection of this determines the image signal for displaying the moving image, which is the image signal for displaying the moving image. A determination is made as to whether it is a still image or an image signal for displaying a still image. Furthermore, the detection of differences obtained through this comparison will only detect differences when they exceed a certain level. You can also configure it so that it is considered to have been sent.

[0169] The selection circuit 1005 includes a set of switches, such as switches formed by transistors. When the image signal for displaying a moving image is determined by the detection of the difference in the comparison circuit, The display control circuit selects the image signal from the frame memory 1010 in which the image signal is stored. This is a circuit for outputting to 1006. Note that the image between frames compared by the comparison circuit 1004 If no difference in image signals is detected, the image displayed between consecutive frames is a still image. In this case, for the latter image signal during the consecutive frame period, the display control circuit 100 The solution is to configure it so that it does not output to port 6.

[0170] The display control circuit 1006 receives the image signal, high power supply potential Vdd, low power supply potential Vss, and starts. Regarding the control signals for pulse SP, clock signal CK, and reset signal Res, the drive circuit This is a circuit for switching the supply or cessation of power to section 1007. Specifically, comparison circuit 10 If 04 determines that it is a moving image, that is, if the difference in image signals over a continuous frame period is extracted. Then, an image signal is supplied from the selection circuit 1005 to the display control circuit 1006. The image signal is supplied to the drive circuit 1007 via the display control circuit 1006. The signal will be supplied to the drive circuit unit 1007 via the display control circuit 1006. On the other hand, The comparison circuit 1004 determines that it is a still image, that is, it extracts the difference in image signals over a continuous frame period. If not output, the image signal will not be supplied from the selection circuit 1005, so the display control circuit 1 No image signal is supplied to the drive circuit section 1007 from 006. Also, the control signal drive circuit section The control circuit 1006, which indicates the supply to 1007, will stop.

[0171] Furthermore, if an image is determined to be a still image, and the period during which it is determined to be a still image is short, The signal may be configured so that the high power supply potential Vdd and low power supply potential Vss are not shut off. In this case, by frequently stopping and restarting the high power supply potential Vdd and the low power supply potential Vss... This is preferable because it can reduce the increase in power consumption.

[0172] Furthermore, the stopping of the image signal and control signal is possible by holding the image signal at each pixel of the pixel unit 1008. It is desirable to perform this over a period of time, and to supply the image signal again after the retention period at each pixel. The display control circuit 1006 will resupply the image signal and control signal that it previously supplied. This configuration would be ideal.

[0173] Furthermore, signal supply refers to supplying a predetermined potential to the wiring. Also, signal stopping and This stops the supply of a predetermined potential to the wiring, and stops the supply of a predetermined fixed potential to the wiring, for example, low-voltage wiring. This refers to electrically connecting to the wiring supplied with the source potential Vss. Alternatively, it refers to stopping the signal. This involves disconnecting the electrical connection to the wiring that is supplied with a predetermined potential, thereby creating a floating state. cormorant.

[0174] As described above, the video signals are compared to determine whether it is a moving image or a still image, and the clock signal and start By selectively restarting or stopping the supply of control signals such as pulses to the drive circuit, the drive Power consumption in circuit section 1007 can be suppressed.

[0175] Next, the gate line drive circuit 1009A and signal line drive circuit 1009B of the drive circuit section 1007. Figure 8 shows an example of the configuration of the shift registers that make up the system.

[0176] The shift register shown in Figure 8(A) is a first pulse output circuit 10_1 to the Nth pulse It has an output circuit 10_N (where N is a natural number greater than or equal to 3). The shift resistance shown in Figure 8(A) The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the first circuit have the first wiring First clock signal CK1 from 11, second clock signal CK2 from second wiring 12, The third clock signal CK3 is transmitted from wire 13 of 3, and the fourth clock signal C is transmitted from wire 14 of 4. K4 is supplied. Also, in the first pulse output circuit 10_1, the 5th wiring 15 is supplied. The start pulse SP1 (the first start pulse) is input. Also, the nth pulse from the second stage onward is input. In the pulse output circuit 10_n (where n is a natural number between 2 and N), the pulse output circuit one stage prior to it... These signals (called the preceding signal OUT(n-1)(SR)) are input. Also, the first pulse In output circuit 10_1, the signal from the third pulse output circuit 10_3, which is two stages later, is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward, the (n+2) second stage after the second stage The signal from the pulse output circuit 10_(n+2) (the subsequent signal OUT(n+2)(SR) (u) is input. Therefore, from the pulse output circuit of each stage, the subsequent stage and / or the stage two stages prior The first output signal (OUT(1)(SR)~OUT(N) for input to the pulse output circuit. (SR), a second output signal (OUT(1)~OUT(N)) input to another wire, etc. The output is as shown in Figure 8(A), the last two stages of the shift register are Since the subsequent signal OUT(n+2)(SR) is not input, one example is the separate sixth distribution The second start pulse SP2 is from wire 17, and the third start pulse SP is from the seventh wire 18. Alternatively, a configuration in which 3 is input to each of them is also acceptable. Or, a signal generated separately inside the shift register. It may also be a number. For example, the (N+1)th pulse output that does not contribute to the pulse output to the pixel part. A force circuit 10_(N+1) and a (N+2) pulse output circuit 10_(N+2) are provided (dummy (Also called the first stage), the second start pulse (SP2) and the third start pulse from the dummy stage The configuration may also be used to generate a signal equivalent to a pulse (SP3).

[0177] The first clock signal (CK1) to the fourth clock signal (CK4) are as shown in Figure 9. This is a signal that alternates between an H signal and an L signal at regular intervals. Also, the first clock signal (C The clock signals K1) through the fourth clock signal (CK4) are sequentially delayed by 1 / 4 of a period. In this configuration, the first clock signal (CK1) to the fourth clock signal (CK4) are used. It controls the drive of the pulse output circuit, etc. The clock signal CK is the input drive cycle Depending on the route, it may also be referred to as GCK or SCK, but here we will explain it as CK.

[0178] Each of the first pulse output circuit 10_1 to the Nth pulse output circuit 10_N is a first input Input terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input It has a power terminal 25, a first output terminal 26, and a second output terminal 27 (see Figure 8(B)). .

[0179] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 ~Electrically connected to one of the fourth wires 14. For example, in Figures 8(A) and (B) In this configuration, the first pulse output circuit 10_1 has a first input terminal 21 that connects to the first wiring 11 and electrical They are connected, and the second input terminal 22 is electrically connected to the second wiring 12, and the third input terminal Child 23 is electrically connected to the third wiring 13. Also, the second pulse output circuit 10_ 2 is such that the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 is The third wiring 13 is electrically connected, and the third input terminal 23 is electrically connected to the fourth wiring 14. It continues.

[0180] Also, in Figures 8(A) and (B), the first pulse output circuit 10_1 is connected to the fourth input terminal A start pulse is input to terminal 24, and the subsequent signal OUT(3)(SR) is input to the fifth input terminal 25. When this is input, the first output signal OUT(1)(SR) is output from the first output terminal 26. The second output signal OUT(1) is output from the second output terminal 27.

[0181] Next, an example of a specific circuit configuration for a pulse output circuit will be explained in Figure 8(C).

[0182] In Figure 8(C), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate is the fourth It is electrically connected to input terminal 24. The second transistor 32 has the first terminal connected to the power supply. It is electrically connected to wire 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. The gate is then electrically connected to the gate of the fourth transistor 34. The transistor 33 has its first terminal electrically connected to the first input terminal 21, and its second terminal is connected to the first It is electrically connected to the output terminal 26 of the fourth transistor 34, with the first terminal connected to the power supply. The second terminal is electrically connected to the first output terminal 26, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power line 52, and its second terminal is connected to the second It is electrically connected to the gate of transistor 32 and the gate of the fourth transistor 34. The gate is electrically connected to the fourth input terminal 24. The sixth transistor 36 is One terminal is electrically connected to the power line 51, and the second terminal is connected to the gate of the second transistor 32. It is electrically connected to the gate of the fourth transistor 34, and the gate is connected to the fifth input terminal 25. They are electrically connected. The seventh transistor 37 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the second terminal of the eighth transistor 38, and the gate is It is electrically connected to the third input terminal 23. The eighth transistor 38 has the first terminal The gate of the second transistor 32 and the gate of the fourth transistor 34 are electrically connected. The gate is electrically connected to the second input terminal 22. The ninth transistor 39 is , the first terminal is the second terminal of the first transistor 31 and the second terminal of the second transistor 32 The second terminal is electrically connected to the gate of the third transistor 33 and the 10th transistor It is electrically connected to the gate of station 40, and the gate is electrically connected to the power line 51. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, and the second The terminal is electrically connected to the second output terminal 27, and the gate is the second of the ninth transistor 39. The terminals are electrically connected. The 11th transistor 41 has its first terminal connected to the power line 52. Electrically connected, the second terminal is electrically connected to the second output terminal 27, and the gate is the second The gate of transistor 32 and the gate of the fourth transistor 34 are electrically connected. ru.

[0183] In Figure 8(C), the gate of the third transistor 33 and the tenth transistor 40 The connection point between the gate and the second terminal of transistor 39 (number 9) is defined as node NA. The gate of the second transistor 32, the gate of the fourth transistor 34, the fifth transistor The second terminal of transistor 35, the second terminal of the sixth transistor 36, and the first terminal of the eighth transistor 38. The connection point between the terminal and the gate of the 11th transistor 41 is defined as node NB.

[0184] In Figure 8(C), if the pulse output circuit is the first pulse output circuit 10_1, the first input The first clock signal CK1 is input to input terminal 21, and the second clock signal CK1 is input to the second input terminal 22. A lock signal CK2 is input, and a third clock signal CK3 is input to the third input terminal 23. Then, the start pulse SP1 is input to the fourth input terminal 24, and the fifth input terminal 25 The subsequent signal OUT(3)(SR) is input, and the first output terminal 26 is OUT(1)( SR) is output, and OUT(1) is output from the second output terminal 27.

[0185] Here, the timing of a shift register equipped with multiple pulse output circuits as shown in Figure 8(C) The chart is shown in Figure 9. Note that if the shift register is a gate line drive circuit, During period 9, 61 is the vertical retrace period, and 62 corresponds to the gate selection period.

[0186] Figures 8 and 9 show an example of a drive fabricated using multiple n-channel transistors. In a dynamic circuit, supplying or stopping the potential of each wire when displaying still images and moving images. The procedure will be explained below.

[0187] First, when stopping the operation of the drive circuit unit 1007, the display control circuit 1006 first... The start pulse SP is stopped. Then, after the start pulse SP is stopped, the pulse output is After reaching the final stage of the fast register, each clock signal CK is stopped. Then the power supply The high power supply potential Vdd and low power supply potential Vss are shut off (see Figure 11(A)). When restarting the operation of the dynamic circuit unit 1007, the display control circuit 1006 first adjusts the power supply voltage. The high power supply potential Vdd and the low power supply potential Vss are supplied to the drive circuit section 1007. Then, A lock signal CK is supplied, followed by the resumption of the supply of the start pulse SP (see Figure 11(B)). (see).

[0188] Next, we fabricated the device using multiple n-channel transistors, as shown as an example in Figures 8 and 9. In the drive circuit described above, the operation of switching from still image display to moving image display, or the drive transistor An operation that rewrites the voltage applied to the gate of the terminal (hereinafter also referred to as a refresh operation). For details on the procedure for supplying or stopping the potential of each wire to the drive circuit section, see Figure 28. Refer to the explanation. Figure 28 shows the wiring that supplies a high power supply potential (VDD) to the shift register. Wiring that supplies low power supply potential (VSS), wiring that supplies start pulse (SP), and Wiring that supplies the first clock signal (CK1) or the fourth clock signal (CK4) This figure shows the change in potential of the wiring before and after the frame period (T1).

[0189] In the display device of this embodiment, the drive circuit unit is constantly operating to display moving images and still images. Furthermore, without constantly operating the drive circuit for refresh operations, the display of still images This can be demonstrated. Therefore, as shown in Figure 28, a high power supply is applied to the shift register. Potential (VDD), first clock signal (CK1) to fourth clock signal (CK4), and The period during which control signals such as start pulses are supplied, and the period during which control signals are not supplied. Yes, it exists. Note that the period T1 shown in Figure 28 is the period during which the control signal is supplied, i.e., the moving image. This corresponds to the period during which the display is shown and the period during which the refresh operation is performed. Also, period T2 shown in Figure 28 This corresponds to the period during which no control signal is supplied, i.e., the period during which a still image is displayed.

[0190] In Figure 28, the period during which the high power supply potential (VDD) is supplied is not limited to period T1, but also to period T It is provided over a period spanning from 1 to period T2. Also, in Figure 28, the first cross During the period when the clock signal (CK1) to the fourth clock signal (CK4) is supplied, the power supply potential is high. It is provided from the time VDD is supplied until before the high power potential (VDD) is shut off. It is.

[0191] Also, as shown in Figure 28, the first clock signal (CK1) to the fourth clock signal (C K4) is a signal that is initially high-potential before the start of period T1, and then becomes a clock signal with a fixed period. The oscillation begins, and after period T1 ends, it becomes a low-potential signal before oscillating as the clock signal. The configuration should be set up to terminate the process.

[0192] As described above, in the display device of this embodiment, a high power supply is supplied to the shift register during period T2. Potential (VDD), first clock signal (CK1) to fourth clock signal (CK4), and The supply of control signals such as the start pulse will be stopped. In between, it operates by controlling the conduction or non-conductivity of each transistor and is controlled by a shift register. The output pulse signal also stops. Therefore, the power consumed in the shift register, and to reduce the power consumed in the pixel section driven by the shift register. This becomes possible.

[0193] Please note that the above refresh operation may result in a degradation of the image quality of the displayed still images. And it is preferable to do this periodically. The display device of this embodiment has a driving element for each pixel As a switching element that controls the voltage applied to the gate of a transistor, the above-mentioned high-purity A transistor equipped with a certain degree of oxide semiconductor is used. This makes it possible to reduce the off-current to an extreme degree. Because it can be reduced, the voltage applied to the gate of the driving transistor of each pixel It is possible to reduce voltage fluctuations. In other words, the operation of the shift register during still image display. Even if the system is down for an extended period, the degradation of image quality can be reduced. For example, Even if the period is only 3 minutes, it is possible to maintain the quality of the displayed still image. For example, a display device that rewrites 60 times per second and one that refreshes once every 3 minutes. Compared to a display device that performs the operation, power consumption can be reduced to approximately 1 / 10000. It is possible.

[0194] The above-mentioned shutdown of the high power supply potential (VDD) refers to the shutdown of the low power supply potential (V) as shown in Figure 28. This means making it equipotential with SS. Note that stopping the high power supply potential (VDD) is done when the high power supply potential is The potential of the supplied wiring may be left in a floating state.

[0195] Furthermore, increasing the potential of the wiring to which the high power supply potential (VDD) is supplied, i.e., during period T1 Before increasing the power supply potential from the low power supply potential (VSS) to the high power supply potential (VDD), the wiring It is preferable to control the potential change so that it is gradual. The gradient of the potential change in the wiring. If the voltage is steep, the change in potential becomes noise, causing an invalid pulse to be output from the shift register. It is possible that the shift register in question is a shift register in a gate line drive circuit. In that case, the malicious pulse becomes a signal that turns on the transistor. The pulse changes the voltage applied to the gate of the drive transistor, which affects the image of the still image. This is because it may change. Considering the above, in Figure 28, the high power supply potential (V This diagram illustrates an example where the rising edge of a signal (DD) is gentler than its falling edge. In particular, in the display device of this embodiment, when a still image is displayed in the pixel section... The supply of high power potential (VDD) to the shift register is stopped and restored as appropriate. This is the configuration. In other words, changes in the potential of the wiring that supplies the high power potential (VDD) become noise. If the noise affects the pixel area, it directly leads to a degradation of the displayed image. Therefore, in this implementation... In a display device of this form, changes in the potential of the wiring (especially an increase in potential) are considered noise. It is important to control the process to prevent it from entering the pixel area.

[0196] Note that the explanation of Figures 8 and 9 describes the configuration of a drive circuit that does not supply a reset signal Res. As shown above, the configuration for supplying the reset signal Res is shown and explained in Figure 10.

[0197] The shift register shown in Figure 10(A) is a first pulse output circuit 10_1 to the Nth pulse It has a shift output circuit 10_N (where N is a natural number greater than or equal to 3). The shift rate shown in Figure 10(A) The first pulse output circuit 10_1 to the Nth pulse output circuit 10_N of the ZISTA are: The first clock signal CK1 is transmitted from wiring 11, and the second clock signal CK2 is transmitted from the second wiring 12. The third clock signal CK3 is transmitted from the third wire 13, and the fourth clock signal is transmitted from the fourth wire 14. CK4 is supplied. Also, in the first pulse output circuit 10_1, from the fifth wiring 15 The start pulse SP1 (the first start pulse) is input. Also, the nth pulse from the second stage onward In the pulse output circuit 10_n (where n is a natural number between 2 and N), the pulse output cycle of the preceding stage A signal from the road (called the preceding signal OUT(n-1)(SR)) is input. Also, the first part In the pulse output circuit 10_1, the signal from the third pulse output circuit 10_3, which is two stages later, is input. Similarly, in the nth pulse output circuit 10_n from the second stage onward, the (n+ 2) The signal from the pulse output circuit 10_(n+2) (the subsequent signal OUT(n+2)(SR) The following is input: Therefore, the pulse output circuit of each stage outputs the subsequent and / or two stages prior. The first output signal OUT((1)(SR)~OUT(N) for input to the pulse output circuit (SR), a second output signal (OUT(1)~OUT(N)) input to another wire, etc. The following is output. In addition, each stage's pulse output circuit receives a reset signal Res from the sixth wire 16. It will be supplied.

[0198] Note that the pulse output circuit shown in Figure 10 differs from the pulse output circuit shown in Figure 8 in that it is a lysé The point is that it has a sixth wiring 16 that supplies a signal Res, and the points regarding other parts are as described above. The explanation is the same as in Figure 8.

[0199] Each of the first pulse output circuits 10_1 to the Nth pulse output circuits 10_N is connected to the first input Terminal 21, second input terminal 22, third input terminal 23, fourth input terminal 24, fifth input It has terminal 25, a first output terminal 26, a second output terminal 27, and a sixth input terminal 28. (See Figure 10(B)).

[0200] The first input terminal 21, the second input terminal 22, and the third input terminal 23 are connected to the first wiring 11 It is electrically connected to one of the fourth wires 14. For example, Figure 10(A), (B) In this configuration, the first pulse output circuit 10_1 has a first input terminal 21 that is connected to the first wiring 11. The second input terminal 22 is electrically connected to the second wiring 12, and the third input Terminal 23 is electrically connected to the third wiring 13. Also, the second pulse output circuit 10 _2 is such that the first input terminal 21 is electrically connected to the second wiring 12, and the second input terminal 22 The third wire 13 is electrically connected, and the third input terminal 23 is electrically connected to the fourth wire 14. It is connected.

[0201] Furthermore, in Figures 10(A) and (B), the first pulse output circuit 10_1 is connected to the fourth input A start pulse is input to terminal 24, and the subsequent signal OUT(3)(S) is input to the fifth input terminal 25. When R) is input, the first output signal OUT(1)(SR) is output from the first output terminal 26. Then, the second output signal OUT(1) is output from the second output terminal 27, and the sixth input terminal 2 This indicates that the reset signal Res is being input from point 8.

[0202] Next, an example of a specific circuit configuration for a pulse output circuit will be explained in Figure 10(C).

[0203] In Figure 10(C), the first transistor 31 has its first terminal electrically connected to the power line 51. The second terminal is electrically connected to the first terminal of the ninth transistor 39, and the gate is It is electrically connected to input terminal 24 of 4. The second transistor 32 has the first terminal electrically connected. It is electrically connected to the source line 52, and the second terminal is electrically connected to the first terminal of the ninth transistor 39. The gate is connected and electrically connected to the gate of the fourth transistor 34. The transistor 33 has its first terminal electrically connected to the first input terminal 21, and its second terminal is connected to the first It is electrically connected to the output terminal 26 of 1. The fourth transistor 34 is electrically connected to the first terminal. The second terminal is electrically connected to the power line 52, and the second terminal is electrically connected to the first output terminal 26. The fifth transistor 35 has its first terminal electrically connected to the power line 52, and its second terminal is The gates of transistors 32 and 4 and 34 are electrically connected. The gate is electrically connected to the fourth input terminal 24. The sixth transistor 36 is The first terminal is electrically connected to the power line 51, and the second terminal is connected to the gate of the second transistor 32. and is electrically connected to the gate of the fourth transistor 34, and the gate is connected to the fifth input terminal 25 It is electrically connected to the power line 51. The seventh transistor 37 has its first terminal electrically connected to the power line 51. It is connected to the gate, and the second terminal is electrically connected to the second terminal of the eighth transistor 38, The third input terminal 23 is electrically connected to the eighth transistor 38, the first terminal This is electrically connected to the gate of the second transistor 32 and the gate of the fourth transistor 34. The gate is electrically connected to the second input terminal 22. The ninth transistor 39 The first terminal is the second terminal of the first transistor 31 and the second terminal of the second transistor 32. The child is electrically connected, and the second terminal is connected to the gate of the third transistor 33 and the 10th transistor. The gate of the zista 40 is electrically connected, and the gate is electrically connected to the power line 51. The tenth transistor 40 has its first terminal electrically connected to the first input terminal 21, and Terminal 2 is electrically connected to the second output terminal 27, and the gate is the ninth transistor 39 It is electrically connected to two terminals. Transistor 41, the 1st terminal is connected to the power line 52 The second terminal is electrically connected to the second output terminal 27, and the gate is the second The gate of transistor 32 and the gate of the fourth transistor 34 are electrically connected. It is there. Also, the gate of the second transistor 32, the gate of the fourth transistor 34, and the fifth The second terminal of transistor 35, the second terminal of the sixth transistor 36, and the eighth transistor The first terminal of transistor 38 and the gate of transistor 41 (number 11) supply the reset signal Res. It is electrically connected to wiring 53 for this purpose. The reset signal Res is the second transistor The gate of transistor 32, the gate of the fourth transistor 34, the gate of the fifth transistor 35 2 terminals, the second terminal of the sixth transistor 36, the first terminal of the eighth transistor 38, and By supplying a signal at a high power supply potential level to the gate potential of the 11th transistor 41, This is a signal used to forcibly reduce the output from the pulse output circuit to a low power supply potential level. be.

[0204] In Figure 10(C), the gate of the third transistor 33 and the tenth transistor 40 The connection point between the gate and the second terminal of transistor 39 (number 9) is defined as node NA. , the gate of the second transistor 32, the gate of the fourth transistor 34, the fifth transistor The second terminal of transistor 35, the second terminal of the sixth transistor 36, and the terminal of the eighth transistor 38. The connection point between terminal 1 and the gate of transistor 41 is defined as node NB.

[0205] In Figure 10(C), if the pulse output circuit is the first pulse output circuit 10_1, then the first The first clock signal CK1 is input to input terminal 21, and the second input terminal 22 is input to the second When the clock signal CK2 is input, the third clock signal CK3 is input to the third input terminal 23. As a result, a start pulse SP is input to the fourth input terminal 24, and to the fifth input terminal 25. The subsequent signal OUT(3)(SR) is input, and the first output terminal 26 is OUT(1)( SR) is output, OUT(1) is output from the second output terminal 27, and the sixth input terminal A reset signal, Res, is input to port 28.

[0206] Furthermore, the timing of a shift register equipped with multiple pulse output circuits as shown in Figure 10(C) The chart is the same as the timing chart shown in Figure 9.

[0207] Figure 10 shows an example of a drive fabricated using multiple n-channel transistors. In the circuit, when displaying still images and moving images, the supply or stop of potential for each wire. I will explain the procedure.

[0208] First, when stopping the operation of the drive circuit unit 1007, the display control circuit 1006 first... Stop the start pulse SP. Then, after the start pulse SP stops, the pulse output shifts. After reaching the final stage of the tracer, each clock signal CK is stopped. Then, reset. The signal Res is supplied. Then, the high power supply potential Vdd and the low power supply potential Vss of the power supply voltage are supplied. It stops (see Figure 11(C)). Also, to restart the operation of the drive circuit 1007, The display control circuit 1006 drives the high power supply potential Vdd and the low power supply potential Vss of the power supply voltage. It is supplied to circuit section 1007. Next, the reset signal Res is supplied. Then, the clock The signal CK is supplied, and then the supply of the start pulse SP is resumed (see Figure 11(D)).

[0209] As explained in Figure 10, in addition to the configurations shown in Figures 8 and 9, a configuration is also provided to supply a reset signal. This reduces malfunctions caused by signal delays during switching between still and moving images. It is suitable because it allows for this.

[0210] Furthermore, when displaying a still image, it is provided on the transistors that make up the drive circuit. The common potential electrode may be disconnected from the common potential line and placed in a floating state. After using still image mode, when restarting the drive circuit, connect the common potential electrode to the common potential line. This prevents malfunctions of the transistors in the drive circuit.

[0211] Figure 12(A) shows an example of such a display panel 1800, and Figure 12(B) shows a cross-section thereof. This is a diagram illustrating the surface structure. The display panel 1800 is provided with drive circuits 1802, 1804 and a pixel section 1806. A common potential electrode 1808 is arranged superimposed on the region where the drive circuit 1802 is provided. The connection / disconnection between the common potential electrode 1808 and the common potential terminal 1812 is controlled. A switch element 1810 is provided.

[0212] As shown in Figure 12(B), the common potential electrode 1808 is connected to the transistor 1803 of the drive circuit. It is arranged on top. The common potential electrode 1808 is provided on the transistor 1803. As a result, transistor 1803 is electrostatically shielded, preventing threshold voltage fluctuations and parasitic channels from forming. It prevents it from happening.

[0213] The switching element 1810 can use the same configuration as the transistor 1803. Yes, it is possible. These elements have extremely low leakage current when off, so the display panel will not move. It contributes to stabilizing the operation. That is, when displaying as a still image, the switch element Even when the sub-electrode 1810 is turned off and the common potential electrode is in a floating state, the potential remains the same. It has the effect of keeping things constant.

[0214] Thus, transistors made of oxide semiconductors with a wide bandgap are used. In addition, by providing a common potential electrode to shield against the external electric field, the operation of the drive circuit is stopped. Still images can be displayed even in this state. Furthermore, the potential of the common potential electrode can be controlled by the drive circuit. By appropriately controlling the system according to the operation, the operation of the display panel can be stabilized. .

[0215] As explained above, each pixel is equipped with a transistor made of high-purity oxide semiconductor. This allows the period during which the voltage can be held by the holding capacity to be longer compared to conventional methods, and static This allows for lower power consumption when displaying still images, etc. Furthermore, when displaying still images... , the output of signals supplied to all signal lines and / or all scan lines included in the pixel area is stopped. By operating the drive circuit section to stop it, the power consumption of not only the pixel section but also the drive circuit section is reduced. It can also suppress force.

[0216] (Embodiment 3) This embodiment shows an example of the structure of the first transistor 6401 described in Embodiment 1. An example of a method for producing the same will be described. Specifically, using a high-purity oxide semiconductor... This section describes an example of a transistor structure and an example of a method for manufacturing it.

[0217] First, Figures 13(A) and 13(B) show examples of the planar and cross-sectional structures of a transistor. Figure 13(A) is a plan view of transistor 410 with a top gate structure, and Figure 13(B) is This is a cross-sectional view along the line C1-C2 in Figure 13(A).

[0218] The transistor 410 has an insulating layer 407, an oxide semiconductor layer 412, and a first Electrode 415a (one of the source electrode and drain electrode), second electrode (source electrode and drain electrode) The first has a rain electrode (the other side) 415b, a gate insulating layer 402, and a gate electrode 411. The first electrode 415a and the second electrode 415b are connected to the first wiring 414a and the second wiring 41 4b is provided in contact with and electrically connected to it.

[0219] Note that the transistor 410 shown in Figure 13(A) is a single-gate transistor. Although shown, the present invention is not limited to this configuration, and may have multiple gate electrodes, A transistor with a multi-gate structure having multiple channel formation regions may also be used.

[0220] Next, using Figures 14(A) to (E), we will proceed to the process of fabricating transistor 410. I will explain.

[0221] First, an insulating layer 407, which will serve as the base film, is formed on the substrate 400.

[0222] There are no major restrictions on the type of substrate that can be used as substrate 400, but it must at least withstand subsequent heat treatment. It is necessary to have a certain degree of heat resistance. If the temperature of the subsequent heat treatment is high... It is preferable to use a substrate with a strain point of 730°C or higher. A specific example of substrate 400 is a glass substrate. Plates, crystallized glass substrates, ceramic substrates, quartz substrates, sapphire substrates, plastic substrates Examples include aluminosilicate glass. Examples include aluminoborosilicate glass and bariumborosilicate glass.

[0223] The insulating layer 407 consists of a silicon oxide layer, a silicon oxide nitride layer, an aluminum oxide layer, Alternatively, it is preferable to use an oxide insulating layer such as an aluminum oxide nitride layer. Plasma CVD and sputtering methods can be used as formation methods, but In order to prevent a large amount of hydrogen from being contained in the marginal layer 407, the insulating layer is formed by sputtering. It is preferable to form a film of 407. In this embodiment, the insulating layer 407 is spa A silicon oxide layer is formed by the taring method. Specifically, the substrate 400 is transported to the processing chamber. Afterward, sputtering gas containing high-purity oxygen from which hydrogen and moisture have been removed is introduced, and silicon and This uses a silicon oxide target and applies a silicon oxide insulating layer 407 on the substrate 400. A film layer is formed. The substrate 400 may be at room temperature or heated during film formation.

[0224] As a specific example of film formation conditions, use quartz (preferably synthetic quartz) as the target, Board temperature 108°C, distance between substrate 400 and target (TS distance) 60 mm, pressure 0 0.4 Pa, 1.5 kW high-frequency power supply, oxygen and argon (oxygen flow rate 25 sccm: argon) A silicon oxide film is formed by RF sputtering under a flow rate of 25 sccm (1:1) atmosphere. A film is formed. The film thickness is 100 nm. The target is quartz (preferably synthetic quartz). Alternatively, a silicon target can be used. Furthermore, oxygen and Oxygen gas may be used instead of the argon mixed gas. Here, the insulating layer 407 is formed. The sputtering gas used in this process has an impurity concentration of hydrogen, water, hydroxyl groups, or hydrides in ppm. A high-purity gas, preferably at the ppb level, is used.

[0225] Furthermore, when forming the insulating layer 407, residual moisture in the processing chamber is removed while forming the insulating layer 407 By forming a film, the insulating layer 407 is made free from hydrogen, hydroxyl groups, or moisture. This is preferable.

[0226] To remove residual moisture from the processing chamber, an adsorption-type vacuum pump can be used. For example, Cryopumps, ion pumps, and titanium sublimation pumps can be used. Furthermore, as an exhaust method, it is preferable to add a cold trap to the turbopump. The treatment chamber, which has been evacuated using a lyopump, contains hydrogen atoms and hydrogen atoms in water (H2O), etc. Because compounds and other substances are exhausted, the insulating layer 407 formed in the processing chamber is designed to minimize the amount of hydrogen atoms removed. It is less likely to get stuck, which is preferable.

[0227] Sputtering methods include RF sputtering, which uses a high-frequency power supply for sputtering, and DC sputtering method using a DC power supply, pulsed DC sputtering method where a pulsed bias is applied. There is the sputtering method. RF sputtering is mainly used when depositing insulating films, DC Sputtering is primarily used for depositing metal films.

[0228] There are also multi-point sputtering systems that can set up multiple targets made of different materials. The apparatus can deposit multiple layers of different material films in the same chamber, or multiple layers of different material films in the same chamber. It is also possible to deposit films by simultaneously discharging different materials.

[0229] Furthermore, a sputtering method using a magnetron sputtering system equipped with a magnetic mechanism inside the chamber is also used. ECR uses a tater device or plasma generated using microwaves instead of glow discharge. A sputtering apparatus using the sputtering method can be used.

[0230] Furthermore, as a film deposition method using the sputtering method, the target material and sputtering occur during film deposition. Reactive sputtering involves chemically reacting with Tagas components to form thin films of these compounds. There are also methods such as the spooling method and the bias sputtering method, which applies voltage to the substrate during film deposition.

[0231] Furthermore, the insulating layer 407 is not limited to a single-layer structure, but may also be a multilayer structure. For example, substrate 400 From the side, a silicon nitride layer, a silicon nitride oxide layer, an aluminum nitride layer, or aluminum nitride oxide layer. A laminated structure consisting of a nitride insulating layer such as nium and the oxide insulating layer may also be used.

[0232] For example, a layer containing high-purity nitrogen from which hydrogen and moisture have been removed between the silicon oxide layer and the substrate. A putter gas is introduced, and a silicon nitride layer is deposited using a silicon target. In this case, as with the silicon oxide layer, the silicon nitride layer is processed while removing residual moisture in the processing chamber. It is preferable to form a film. Also, when forming a silicon nitride layer, the substrate is added during film formation. It can be heated.

[0233] When a silicon nitride layer and a silicon oxide layer are laminated as the insulating layer 407, silicon nitride The layer and the silicon oxide layer are deposited in the same processing chamber using a common silicon target. This is possible. First, a sputtering gas containing nitrogen is introduced, and the silicon installed in the processing chamber is... A silicon nitride layer is formed using a target, and then a sputtering gas containing oxygen is introduced. Switch to the same silicon target and deposit a silicon oxide layer. When used, the silicon nitride layer and the silicon oxide layer are formed continuously without exposure to the atmosphere. This prevents impurities such as hydrogen and moisture from adsorbing onto the silicon nitride layer surface. Cut.

[0234] Next, an oxide semiconductor layer is formed on the insulating layer 407 by sputtering.

[0235] In order to minimize the presence of hydrogen, hydroxyl groups, and moisture in the oxide semiconductor layer, before film formation... As a process, the substrate 400 on which the insulating layer 407 has been formed is placed in the preheating chamber of the sputtering apparatus. Preheating is preferred to remove impurities such as hydrogen and moisture adsorbed on the substrate 400 and exhaust the waste. Furthermore, a cryopump is preferred as the exhaust means to be installed in the preheating chamber. Heating is preferably performed on the substrate 400 before the formation of the gate insulating layer 402, which will be formed later. Furthermore, the substrate with the first electrode 415a and the second electrode 415b formed on it, which will be formed later. It is preferable to perform the same procedure for 400. However, these preheating processes can be omitted. That's fine.

[0236] Furthermore, before depositing the oxide semiconductor layer by sputtering, argon gas is introduced. Reverse sputtering is performed to generate plasma and remove dust adhering to the surface of the insulating layer 407. It is also preferable to remove it. Reverse sputtering is a method in which no voltage is applied to the target side, and an argon atmosphere is used. By applying a voltage to the substrate side using a high-frequency power supply under gas pressure, a plasma is formed near the substrate. This is a method for modifying the surface. Note that nitrogen, helium, and oxygen can be used instead of an argon atmosphere. You may also use the following:

[0237] The target for the oxide semiconductor layer is a metal oxide with zinc oxide as the main component. A can be used. Other examples of metal oxide targets include In, Ga , and metal oxide targets containing Zn (composition ratio: In2O3:Ga2O3:Zn) Using O=1:1:1 [mol%] and In:Ga:Zn=1:1:0.5 [atom%] It can be present. Also, as a target for metal oxides containing In, Ga, and Zn, In:Ga:Zn=1:1:1[atom%], or In:Ga:Zn=1:1:2[a A target with a composition ratio of tom% can also be used. In addition, SiO2 is added by weight. Targets containing between % and 10% by weight can also be used. The filling rate is 90% or more and 100% or less, preferably 95% or more and 99.9% or less. By using a high-performance metal oxide target, the deposited oxide semiconductor layer can be made into a dense film. It is possible.

[0238] Furthermore, when depositing oxide semiconductor layers, a rare gas (typically argon) atmosphere is used, and an oxygen atmosphere is used. This can be done under ambient air, or under a noble gas (typically argon) and oxygen atmosphere. Here, The sputtering gas used when depositing oxide semiconductor layers is hydrogen, water, hydroxyl groups, or hydrides. High-purity gas from which the concentration of impurities has been removed to the ppm level, preferably the ppb level. Use.

[0239] The oxide semiconductor layer holds the substrate in a processing chamber that is kept under reduced pressure, and the residual water in the processing chamber Sputtered gas, from which hydrogen and moisture have been removed while removing particles, is introduced, and metal oxides are targeted. The film is then formed on the substrate 400. To remove residual moisture in the processing chamber, an adsorption-type filter is used. It is preferable to use an empty pump. For example, a cryopump, an ion pump, or a titanium sub-pump. It is preferable to use a remanufacturing pump. Also, as an exhaust means, a turbo pump is preferred. A cold trap may be added. A treatment room evacuated using a cryopump. For example, hydrogen atoms, compounds containing hydrogen atoms such as water (H2O) (more preferably carbon atoms) Compounds containing the same substance are also exhausted, and therefore the oxide semiconductor layer formed in the processing chamber is contained within it. The concentration of impurities can be reduced. Also, the substrate can be kept at room temperature during oxide semiconductor layer deposition. Alternatively, it may be heated to a temperature below 400°C.

[0240] Examples of film deposition conditions for an oxide semiconductor layer include: substrate temperature (room temperature), and the distance between the substrate and the target. Distance 110mm, pressure 0.4Pa, DC power supply 0.5kW, oxygen and argon ( The conditions include an atmosphere with an oxygen flow rate of 15 sccm and an argon flow rate of 30 sccm. When using a pulsed DC power supply, powdery substances (particles, dust) generated during film formation are removed. (Also known as) This is preferable because it reduces the thickness distribution and makes the film thickness distribution uniform. The film thickness should be between 2 nm and 200 nm, preferably between 5 nm and 30 nm. The appropriate thickness varies depending on the oxide semiconductor material used, and the appropriate thickness should be determined according to the material. You can just select it.

[0241] Specific examples of the oxide semiconductor layer formed by the above method include quaternary metal oxides such as In-Sn-Ga-Zn-O, ternary metal oxides such as In-Ga-Zn-O, In -Sn-Zn-O, In-Al-Zn-O, Sn-Ga-Zn-O, Al-Ga-Zn- O, Sn-Al-Zn-O, binary metal oxides such as In-Zn-O, Sn-Zn-O , Al-Zn-O, Zn-Mg-O, Sn-Mg-O, In-Mg-O, In-O, S n-O, Zn-O and other oxide semiconductor layers can be used. Further, the above oxide semiconductor layer may contain Si. Further, these oxide semiconductor layers may be amorphous or crystalline. Or, they may be non-single crystal or single crystal . In this embodiment, an amorphous In-Ga-Zn-O film is formed by a sputtering method using In-Ga-Zn-O as a target .

[0242] Also, as the oxide semiconductor layer, a thin film represented by InMO3(ZnO) m (m>0) can also be used . Here, M is one or a plurality of metal elements selected from Ga, Al, Mn, and Co. For example, as M, Ga, Ga and Al, Ga and Mn, or Ga and Co can be cited. Among the oxide semiconductor films represented by InMO3(ZnO) m (m>0), the oxide semiconductor having a structure containing Ga as M can be called the above-mentioned In-G [ a-Zn-O oxide semiconductor.

[0243] Next, the oxide semiconductor layer is formed into island-shaped oxide semiconductor layers 4 by the first photolithography process Process to 12 (see Figure 14(A)). Note that island-shaped oxide semiconductor layers 412 are formed. A resist mask may be formed by an inkjet method. Since the wet process does not require the use of a photomask, manufacturing costs can be reduced.

[0244] Note that etching of the oxide semiconductor layer can be done using either dry etching or wet etching. Often, both can be used.

[0245] When performing dry etching, parallel plate type RIE (Reactive Ion Etc The hing method, or ICP (Inductively Coupled Plasma): A conductively coupled plasma etching method can be used. The desired processing shape can be etched. To enable etching, the etching conditions (amount of power applied to the coil-type electrode, amount of power applied to the electrode on the substrate side) The amount of power being applied, the electrode temperature on the substrate, etc., are adjusted as appropriate.

[0246] Etching gases used in dry etching include chlorine-containing gases (chlorine-based gases, e.g. For example, chlorine (Cl2), boron chloride (BCl3), silicon chloride (SiCl4), carbon tetrachloride (C) A gas containing fluorine (such as Cl4) is preferred, but a fluorine-containing gas (fluorinated gas, for example, carbon tetrafluoride (C)) is preferred. F4), sulfur hexafluoride (SF6), nitrogen trifluoride (NF3), trifluoromethane (CHF3) ) etc., hydrogen bromide (HBr), oxygen (O2), and helium (He) and aluminum in these gases. Gases with added noble gases such as argon (Ar) can also be used.

[0247] The etching solution used for wet etching is a solution of phosphoric acid, acetic acid, and nitric acid. Ammonia hydrochloride (for example, 31% hydrogen peroxide by weight: 28% ammonia by weight in volume ratio) A solution (mixed in a ratio of 5:2:2 water) can be used. 7N (manufactured by Kanto Chemical Co., Ltd.) may also be used. Etching conditions (etching solution, etching time) The intervals, temperature, etc., should be adjusted as appropriate according to the oxide semiconductor material.

[0248] Furthermore, when performing wet etching, the etching solution is used along with the etched material. It is removed by washing. The waste etching solution containing the removed material is purified and contains The material may be reused. The material contained in the oxide semiconductor layer can be extracted from the waste liquid after etching. By recovering and reusing materials (for example, rare metals such as indium), resources can be used effectively. It can be put to good use.

[0249] In this embodiment, a solution of phosphoric acid, acetic acid, and nitric acid is used as the etching solution. The oxide semiconductor layer is processed into island-shaped oxide semiconductor layers 412 by an etching method.

[0250] Next, the oxide semiconductor layer 412 is subjected to a first heat treatment. The temperature of the first heat treatment is 40 The temperature should be between 0°C and 750°C, preferably above 400°C and below the strain point of the substrate. A substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor layer is subjected to a nitrogen atmosphere. After heating at 50°C for 1 hour, the oxide semiconductor is kept away from the atmosphere. This prevents the re-importation of water and hydrogen into the layer. This first heat treatment removes the oxide semiconductor layer 412 It can remove hydrogen, water, and hydroxyl groups, etc.

[0251] Furthermore, the heat treatment device is not limited to electric furnaces, but also includes heat conduction from heat sources such as resistance heating elements or The device may include an apparatus that heats the object to be processed by thermal radiation. For example, GRTA(Ga s Rapid Thermal Anneal) equipment, LRTA (Lamp Rapi) d Thermal Anneal) RTA (Rapid Thermal A A nneal) device can be used. The LRTA device uses halogen lamps, metal halide lamps. Id lamps, xenon arc lamps, carbon arc lamps, high-pressure sodium lamps, high A device that heats the object to be processed by radiation of light (electromagnetic waves) emitted from lamps such as pressurized mercury lamps. It is a device that performs heat treatment using high-temperature gas. This can be done using an inert gas (typically a noble gas such as argon) or nitrogen gas. ru.

[0252] For example, as a first heat treatment, in an inert gas heated to a high temperature of 650°C to 700°C The substrate is moved and placed inside, heated for several minutes, then the substrate is moved again and heated to a high temperature inert gas. GRTA can be performed by removing the contents from the inside. Using GRTA allows for high-temperature heating in a short time. Processing becomes possible.

[0253] It is preferable that the atmosphere during the first heat treatment does not contain water, hydrogen, etc. i. Or, introducing nitrogen, helium, neon, argon, etc. into the heating treatment device. The purity of the sucrose should be 6N (99.9999%) or higher, preferably 7N (99.99999%) or higher. It is preferable that the impurity concentration be 1 ppm or less, preferably 0.1 ppm or less. It's nice.

[0254] Furthermore, depending on the conditions of the first heat treatment or the material of the oxide semiconductor layer, the first heat treatment Due to the process, the island-like oxide semiconductor layer 412 may crystallize, and in some cases, it may become microcrystalline or polycrystalline. For example, it can be a microcrystalline oxide semiconductor layer with a crystallinity of 80% or more. Even after the first heat treatment, the island-like oxide semiconductor layer 412 does not crystallize, and amorphous oxide It can also form a semiconductor layer. In addition, a microcrystalline region (particle size 1 nm) may be present within the amorphous oxide semiconductor layer. The oxide semiconductor layer contains a mixture of elements up to 20 nm (typically between 2 nm and 4 nm). In some cases, this may be the case.

[0255] Furthermore, the first heat treatment of the oxide semiconductor layer is performed before processing it into an island-shaped oxide semiconductor layer. The oxide semiconductor layer may also be treated. In this case, after the first heat treatment, the base The board is removed, and the photolithography process is performed.

[0256] In the first heat treatment, impurities such as hydrogen, water, and hydroxyl groups are removed from the oxide semiconductor layer. The primary objective is to remove oxygen vacancies in the oxide semiconductor layer during this heat treatment. This may occur. Therefore, an oxidation treatment should be performed after the first heat treatment. This is preferable. A specific example of the oxidation treatment is to continue the treatment in an oxygen atmosphere after the first heat treatment. Alternatively, a method of heat treatment in an atmosphere containing nitrogen and oxygen (nitrogen:oxygen volume ratio = 4:1). These include methods such as plasma treatment in an oxygen atmosphere.

[0257] Heat treatments that have the effect of dehydrating and dehydrogenating oxide semiconductor layers are used for oxide semiconductor layers. After film formation, the source electrode and drain electrode are stacked on the oxide semiconductor layer, and then the source electrode and This can be done either after forming a gate insulating layer on the drain electrode.

[0258] Next, a conductive film is formed on the insulating layer 407 and the oxide semiconductor layer 412. The film can be formed by puttering or vacuum deposition. Suitable materials for the conductive film include Al and Cu. Metallic materials such as Cr, Ta, Ti, Mo, W, and Y, and alloy materials having said metallic materials as components. Examples include conductive metal oxides. Examples of conductive metal oxides include adipose-derived oxides. Indium (In2O3), tin oxide (SnO2), zinc oxide (ZnO), indium oxide Tin oxide alloy (In2O3-SnO2, abbreviated as ITO), indium oxide zinc oxide alloy Gold (In2O3-ZnO) or the aforementioned metal oxide material with silicon or silicon oxide It can be used if it contains Si, Ti, Ta, W, Mo, Cr, Nd, A is a film to which elements such as Sc and Y are added to prevent the formation of hillocks and whiskers that occur in Al films. l material may also be used, in which case the heat resistance can be improved.

[0259] Furthermore, the conductive film may have a single-layer structure or a laminated structure of two or more layers. For example A single-layer structure of an aluminum film containing silicon, and a two-layer structure of a titanium film laminated on an aluminum film. Layered structure, an aluminum film is stacked on top of a Ti film, and then another Ti film is stacked on top of that. One example is a layered structure. Also, a metal layer such as Al or Cu, and layers of Cr, Ta, Ti, Mo, W... Any configuration in which high-melting-point metal layers are laminated together is possible.

[0260] Next, a resist mask is formed on the conductive film by a second photolithography process, and then selected After etching is performed to form the first electrode 415a and the second electrode 415b, the resin Remove the stock mask (see Figure 14(B)). The first electrode 415a is the source electrode and the dot It functions as one of the rain electrodes, and the second electrode 415b is the other of the source electrode and drain electrode. It functions as a method. Here, the ends of the first electrode 415a and the second electrode 415b are tapered Etching to create the desired shape improves the coverage of the gate insulating layer that is laminated on top. Preferred. Furthermore, the resist for forming the first electrode 415a and the second electrode 415b The screen may be formed by an inkjet method. This eliminates the need for photomasks, thus reducing manufacturing costs.

[0261] In this embodiment, the first electrode 415a and the second electrode 415b are used in the sputtering method. This further forms a titanium film with a thickness of 150 nm.

[0262] Furthermore, during etching of the conductive film, the oxide semiconductor layer 412 is removed, and the insulating layer beneath it is removed. It is necessary to adjust the materials and etching conditions appropriately so that layer 407 is not exposed. Therefore, in this embodiment, the oxide semiconductor layer 412 is an In-Ga-Zn-O system. Using an oxide semiconductor, a titanium film as the conductive film, and ammonia peroxide as the etchant. By using (a mixture of ammonia, water, and hydrogen peroxide solution), the oxide semiconductor layer 412 While some parts are designed to prevent etching, the present invention is not limited to this configuration. Next, a portion of the oxide semiconductor layer 412 is etched by a second photolithography process. Furthermore, it can also be an oxide semiconductor layer having grooves (recesses).

[0263] For exposure during the resist mask formation process in the second photolithography step, ultraviolet light or KrF A laser beam or ArF laser beam can be used. On the oxide semiconductor layer 412, adjacent numbers The gap between the lower end of electrode 1 and the lower end of electrode 2 determines the transient that is later formed. The channel length L of the filter is determined. Note that when performing exposure with a channel length L = less than 25 nm This refers to ultra-ultraviolet light, which has extremely short wavelengths ranging from a few nanometers to tens of nanometers. Using olet, exposure is performed during the resist mask formation in the second photolithography step. Exposure with ultra-ultraviolet light has high resolution and a large depth of field. Therefore, later formation It is also possible to set the transistor channel length L to between 10 nm and 1000 nm. In this case, the operating speed of the transistor can be increased, and the off-current value is extremely small. This allows for lower power consumption of transistors.

[0264] Next, the insulating layer 407, the oxide semiconductor layer 412, the first electrode 415a, and the second electrode 415 A gate insulating layer 402 is formed on b (see Figure 14(C)).

[0265] The gate insulating layer 402 is formed using plasma CVD or sputtering, etc. Cone layer, silicon nitride layer, silicon oxide nitride layer, silicon nitride oxide layer, or aluminum oxide layer The um layer can be formed as a single layer or in multiple layers.

[0266] When forming the gate insulating layer 402, it is preferable to ensure that it does not contain hydrogen. Therefore, sputtering, which allows for the reduction of hydrogen in the atmosphere during film formation, is used. It is preferable to form an insulating layer 402. A silicon oxide film is formed by sputtering. When forming a film, use a silicon target or a quartz target as the target, spa The procedure is carried out using oxygen or a mixture of oxygen and argon as the tatting gas.

[0267] Furthermore, the gate insulating layer 402 is acid-treated in order from the first electrode 415a side and the second electrode 415b side. A structure can also be formed by stacking a silicon oxide layer and a silicon nitride layer. For example, the first G A silicon oxide layer (SiO₂) with a thickness of 5 nm to 300 nm is used as the insulating layer. x (x>0)) A second gate insulating layer is formed on the first gate insulating layer with a thickness of 50 nm or more and 200 nm. Silicon nitride layer (SiN) of m or less y (y>0)) is stacked to create a gate insulation layer with a film thickness of 100 nm. It may also be used as a marginal layer. In this embodiment, the pressure is 0.4 Pa, the high-frequency power supply is 1.5 kW, and oxygen and Under an argon atmosphere (oxygen flow rate 25 sccm: argon flow rate 25 sccm = 1:1), R A silicon oxide layer with a thickness of 100 nm is formed using the F sputtering method.

[0268] Next, a resist mask is formed by a third photolithography step and selectively etched. By performing a process to remove a portion of the gate insulating layer 402, the first electrode 415a, the second Openings 421a and 421b are formed that reach electrode 415b (see Figure 14(D)). Furthermore, when forming a resist mask using the inkjet method, a photomask is not used. Therefore, manufacturing costs can be reduced.

[0269] Next, after forming a conductive film on the gate insulating layer 402 and the openings 421a and 421b, The photolithography process in step 4 produces the gate electrode 411, the first wiring 414a, and the second wiring. It forms 414b.

[0270] The material of the gate electrode 411, the first wiring 414a, and the second wiring 414b is molybdenum. Titanium, chromium, tantalum, tungsten, aluminum, copper, neodymium, scandium Formed by using metal materials such as these, or alloy materials mainly composed of these, in a single layer or in multiple layers. This is possible. Two layers: gate electrode 411, first wiring 414a, and second wiring 414b. Specific structural examples include a structure in which a molybdenum layer is laminated on an aluminum layer, and a structure in which a molybdenum layer is laminated on a copper layer. A structure in which ribdenum layers are stacked, or a titanium nitride layer or tantalum nitride layer is stacked on a copper layer. Examples include a structure in which a molybdenum layer is laminated on a titanium nitride layer. Also, 3 Specific examples of layered structures include a tungsten layer or a tungsten nitride layer, and aluminum and A silicon alloy or aluminum and titanium alloy layer, and a titanium nitride or titanium layer. A structure in which the and are stacked can be cited. Furthermore, a conductive film with light transmission can be used for the gate electrode layer. It can also be formed. A specific example of a translucent conductive film is a translucent conductive film. Examples include films made of oxides.

[0271] In this embodiment, the gate electrode 411, the first wiring 414a, and the second wiring 414b are used as follows: A titanium film with a thickness of 150 nm is formed using the sputtering method.

[0272] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. The process is carried out at a temperature between 00°C and 400°C, for example, between 250°C and 350°C. A second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. This may be done after forming a protective insulating layer or a planar insulating layer on the transistor 410.

[0273] Furthermore, heating treatment in air at temperatures between 100°C and 200°C for 1 hour to 30 hours is also performed. This can be done by heating while maintaining a constant heating temperature, or at room temperature. Furthermore, the process involves raising the temperature to a heating temperature between 100°C and 200°C, and then lowering the temperature from the heating temperature to room temperature. This process may be repeated several times. Alternatively, this heat treatment may be performed under reduced pressure before the formation of the oxide insulating layer. It is also acceptable to perform the heat treatment under reduced pressure, as this shortens the heating time. .

[0274] Through the above process, a high-purity acid is produced with reduced concentrations of hydrogen, water, hydrides, and hydroxides. A transistor 410 having a ionized semiconductor layer 412 can be formed (Figure 14(E)). See reference. ) Transistor 410 is the first transistor 6401 described in Embodiment 1. It can be applied as such.

[0275] Furthermore, even if a protective insulating layer or a planarizing insulating layer for planarization is provided on transistor 410 Good. As protective insulating layers, silicon oxide layer, silicon nitride layer, silicon oxide nitride layer, silicon A silicon oxide layer or an aluminum oxide layer can be formed as a single layer or in a laminated configuration. Furthermore, as the planar insulating layer, polyimide, acrylic resin, benzocyclobutene resin, Heat-resistant organic materials such as riamide and epoxy resin can be used. In addition to organic materials, low-dielectric materials (low-k materials), siloxane resins, and PSG (Lingga) are also used. Lath, BPSG (Limboron glass), etc. can also be used. A planar insulating layer may be formed by stacking multiple insulating films.

[0276] Here, siloxane-based resin refers to a Si- resin formed using siloxane-based material as the starting material. This corresponds to a resin containing O-Si bonds. Siloxane resins use organic groups as substituents (for example) Alkyl groups, aryl groups, and fluoro groups may also be used. Furthermore, organic groups may contain fluoro groups. It's okay to do so.

[0277] The method for forming the planar insulating layer is not particularly limited and can be sputtered or SOG depending on the material. Spin coating, dip coating, spray coating, droplet ejection (inkjet method, screen coating) Printing, offset printing, etc.), doctor knife, roll coater, curtain coater, knife A coating machine or similar device can be used.

[0278] As mentioned above, when forming an oxide semiconductor layer, residual moisture in the reaction atmosphere is removed. This makes it possible to reduce the concentration of hydrogen and hydrides in the oxide semiconductor layer.

[0279] The transistor having the oxide semiconductor layer described in this embodiment constitutes the display unit of the display device. By using it in the pixels that make up the structure, the off-current can be reduced. Therefore, the retaining capacitance This allows for a longer period during which the voltage can be maintained, thereby reducing power consumption when displaying still images, etc. This is possible. Furthermore, by stopping the control signal when displaying still images, low power consumption is achieved. It can be optimized. Furthermore, it can switch between still images and moving images without malfunction. .

[0280] (Embodiment 4) This embodiment shows an example of the structure of the first transistor 6401 described in Embodiment 1. An example of a method for producing the same will be described. Specifically, using a high-purity oxide semiconductor... An example of transistor structure and an example of its fabrication method will be explained using Figure 15. ru.

[0281] Figures 15(A) to (E) show examples of the cross-sectional structure of a transistor. Figure 15(E) shows Transistor 390 is a bottom-gate structure, also known as an inverse staggered transistor. U. This transistor 390 is the first transistor 6401 etc described in Embodiment 1. It can be used for this purpose. Note that transistor 390 is a single-gate transistor. Although this shows, the present invention is not limited to this configuration, and may have multiple gate electrodes. It may also be a transistor with a multi-gate structure having multiple channel formation regions.

[0282] The transistor 390 is fabricated on the substrate 394 using Figures 15(A) to (E) below. I will explain the method.

[0283] First, a conductive film is formed on the substrate 394, and then a first photolithography process is performed. A gate electrode 391 is formed. The end of the formed gate electrode is tapered, and stacked on top of it. This is preferable because it improves the coverage of the gate insulating layer. It may also be formed by the inkjet method. If the resist mask is formed by the inkjet method, it becomes a photomask. Because it does not use [a specific ingredient / method], manufacturing costs can be reduced.

[0284] Here, the material of the substrate 394 is the same as that of the substrate 400 described in Embodiment 3. This can be adopted. Also, the material and film formation method of the gate electrode 391 are as follows: A gate electrode similar to the one described in section 3 (gate electrode 411) can be used.

[0285] An insulating film, which serves as an underlayer, may be provided between the substrate 394 and the gate electrode 391. The underlayer has the function of preventing the diffusion of impurity elements from the substrate 394, and is a silicon nitride film. One selected from silicon oxide film, silicon nitride film, or silicon oxynitride film. It can be formed by a single-layer structure or a laminated structure consisting of multiple films selected from these.

[0286] Next, a gate insulating layer 397 is formed on the gate electrode 391.

[0287] The gate insulating layer 397 is formed using plasma CVD or sputtering, etc. Silicon oxide layer, silicon nitride layer, silicon oxide nitride layer, silicon oxide nitride layer, or aluminum oxide layer The aluminum layer can be formed as a single layer or in multiple layers. To prevent the inclusion of large amounts of hydrogen, the gate insulating layer 397 is formed using the sputtering method. It is preferable to form a film. When forming a silicon oxide film by sputtering, A silicon target or quartz target is used as the target, and an acid is used as the sputtering gas. This is done using either a nitrate or a mixed gas of oxygen and argon.

[0288] The gate insulating layer 397 consists of a silicon nitride layer and a silicon oxide layer, in that order from the gate electrode 391 side. A layered structure can also be used. For example, sputtering can be used as the first gate insulating layer. By law, a silicon nitride layer (SiN) with a thickness of 50 nm to 200 nm. y (y>0)) The first gate insulating layer is then layered with a second gate insulating layer with a thickness of 5 nm to 300 nm. silicon oxide layer (SiO x (x>0)) are stacked to form a gate insulating layer with a thickness of 100 nm and That's all you need to do.

[0289] Next, an oxide semiconductor layer 393 with a thickness of 2 nm to 200 nm is placed on the gate insulating layer 397. It forms (see Figure 15(A)).

[0290] Here, the material and film formation method of the oxide semiconductor layer 393 are the same as those described in Embodiment 3. A semiconductor layer (an island-shaped oxide semiconductor layer 412) similar to the one used can be employed.

[0291] For example, an example of film deposition conditions when forming an oxide semiconductor layer 393 by sputtering. The distance between the substrate and the target is 100 mm, the pressure is 0.6 Pa, and the current is DC. The conditions include a power supply of 0.5kW and an oxygen atmosphere (oxygen flow rate ratio of 100%). When using a DC power supply, powdery material (also known as particles or dust) generated during film formation is produced. This is preferable because it reduces (the aforementioned) and results in a uniform film thickness distribution. The film thickness should be between 2 nm and 200 nm, preferably between 5 nm and 30 nm. The appropriate thickness will vary depending on the oxide semiconductor material used, and will be adjusted as needed depending on the material. You just need to select the thickness.

[0292] Furthermore, before depositing the oxide semiconductor layer 393, argon gas was introduced to generate plasma. This involves performing reverse sputtering to remove debris adhering to the surface of the gate insulating layer 397. It is preferable.

[0293] Furthermore, hydrogen, hydroxyl groups, and moisture are present in the gate insulating layer 397 and the oxide semiconductor layer 393 as much as possible. To prevent contamination, as a pretreatment before film formation, in the preheating chamber of the sputtering apparatus A substrate 394 on which the gate electrode 391 is formed, or a substrate up to the gate insulating layer 397 is formed. The substrate 394 is preheated to remove impurities such as hydrogen and moisture adsorbed on the substrate 394 and exhaust the waste. It is preferable to do so. The preheating temperature should be 100°C or higher and 400°C or lower, preferably 1 The temperature should be between 50°C and 300°C. Furthermore, the exhaust means installed in the preheating chamber should be cryopreserved. A pump is preferred. In addition, this preheating is performed on the first electrode 39 before the protective insulating layer 396 is formed. The same procedure may be performed on the substrate 394 on which electrodes 5a and the second electrode 395b have been formed.

[0294] Next, the oxide semiconductor layer is transformed into island-shaped oxide semiconductor layer 3 by a second photolithography process. Process to form 99 (see Figure 15(B)). Note: Processing method for island-shaped oxide semiconductor layer 399 Regarding this, the processing method for forming the island-shaped oxide semiconductor layer 412 described in Embodiment 3 It is possible to adopt something similar to the law.

[0295] Furthermore, before forming the conductive film in the next step, reverse sputtering is performed to form the oxide semiconductor layer 399 and the gate It is preferable to remove any resist residue or other material adhering to the surface of the insulating layer 397.

[0296] Next, a conductive film is formed on the gate insulating layer 397 and the oxide semiconductor layer 399. For the film deposition method, sputtering or vacuum deposition methods may be used. Furthermore, the material for the conductive film is... For example, elements selected from Al, Cr, Cu, Ta, Ti, Mo, W, or these Alloys composed of elements, or alloys combining multiple elements, can be used. It can also be made from one of the following: manganese, magnesium, zirconium, beryllium, or thorium. One or more materials selected from the above may be used. Alternatively, a transparent conductive film may be used. This is also acceptable. A specific example of a transparent conductive film is one made of a transparent conductive oxide. A membrane is one example.

[0297] Furthermore, the conductive film may be a single-layer structure or a laminated structure of two or more layers. For example, A single-layer structure of an aluminum film containing ricon, and a two-layer structure in which a titanium film is laminated on top of an aluminum film. A Ti film is constructed, and an aluminum film is layered on top of the Ti film, and then another Ti film is layered on top of that. Examples include a three-layer structure formed by thin-film deposition.

[0298] Next, a resist mask is formed on the conductive film by a third photolithography process, and then selected After etching is performed to form the first electrode 395a and the second electrode 395b, then the resist Remove the mask (see Figure 15(C)). Here, when etching the conductive film, acid To prevent the monized semiconductor layer 399 from being removed and the gate insulating layer 397 underneath from being exposed, It is necessary to adjust the materials and etching conditions as appropriate. Therefore, in this embodiment, acid As the oxide semiconductor layer 399, an In-Ga-Zn-O based oxide semiconductor is used, and as the conductive film Using a titanium film, ammonia hydrochloride (ammonia, water, hydrogen peroxide) is used as the etchant. By using the mixed solution, a portion of the oxide semiconductor layer 399 is not etched. However, the present invention is not limited to this configuration. That is, a third photolithography process Depending on the process, a portion of the oxide semiconductor layer 399 is etched, and an oxide semiconductor having grooves (recesses) is formed. It can also be used as a conductive layer.

[0299] For exposure during resist mask formation in the third photolithography step, ultraviolet light or KrF A laser beam or ArF laser beam can be used. On the oxide semiconductor layer 399, adjacent numbers The gap between the lower end of electrode 1 395a and the lower end of electrode 2 395b is used to determine the later formation The channel length L of the transistor is determined. Note that channel length L = less than 25 nm When performing exposure, use ultra-ultraviolet light with extremely short wavelengths of a few nanometers to several tens of nanometers. Resist mask in the third photolithography step using Ultraviolet Exposure is performed during the formation process. Exposure with ultra-ultraviolet light provides high resolution and a large depth of field. Therefore The channel length L of the transistor formed later will be set to be between 10 nm and 1000 nm. This is also possible, allowing for faster circuit operation, and furthermore, the off-current value is extremely small, This allows for lower power consumption of transistors.

[0300] Furthermore, in order to reduce the number of photomasks and processes used in the photolithography process, A resist formed by a multi-gradation mask, which is an exposure mask where the light that passes through it has multiple intensities. The etching process may be performed using a mask. A resist formed using a multi-gradation mask. The mask has a shape with multiple film thicknesses, and its shape can be further deformed by etching. Because it can do this, it can be used in multiple etching processes to process different patterns. Therefore, a single multi-tone mask can be used to create at least two different patterns. A corresponding resist mask can be formed. Therefore, the number of exposure masks can be reduced. Furthermore, the corresponding photolithography process can also be reduced, thus simplifying the overall process.

[0301] Furthermore, the exposed material is removed by plasma treatment using gases such as N2O, N2, or Ar. Adsorbed water and other substances adhering to the surface of the oxide semiconductor layer 399 may be removed. Also, oxygen and Plasma treatment may be performed using a mixed gas of argon. In this embodiment, any of the above The plasma treatment is performed.

[0302] Next, the exposed oxide semiconductor, after plasma treatment, is not exposed to the atmosphere. A protective insulating film 396 is formed in contact with layer 399, the first electrode 395a, and the second electrode 395b. This is achieved (see Figure 15(D)). At this time, the oxide semiconductor layer 399 and the protective insulating layer 396 To ensure that hydrogen, hydroxyl groups, or moisture are not present, residual moisture in the processing chamber is removed. It is preferable to form a protective insulating layer 396. In order to remove residual moisture in the processing chamber It is preferable to use an adsorption-type vacuum pump. For example, a cryopump or an ion pump. It is preferable to use a titanium sublimation pump. Also, as an exhaust means, A cryopump may be used to add a cold trap to the pump. The treated chamber exhausts, for example, hydrogen atoms and compounds containing hydrogen atoms, such as water (H2O). Therefore, the concentration of impurities in the protective insulating layer 396 formed in the processing chamber can be reduced. ru.

[0303] In this embodiment, an oxide insulating layer is formed as the protective insulating layer 396. As a method for forming 6, an island-shaped oxide semiconductor layer 399, a first electrode 395a, and a second electrode The substrate 394 on which the electrode 395b is formed is heated at room temperature or to a temperature below 100°C. Then, a sputtering gas containing high-purity oxygen from which hydrogen and water have been removed is introduced, and silicon semiconductor A silicon oxide layer is formed using the target. Note that the oxide insulating layer is silicon oxide. Instead of the silicon oxide layer, a silicon oxide nitride layer, an aluminum oxide layer, or an aluminum oxide nitride layer can be used. It is also possible to use layers such as um.

[0304] For example, a silicon target with a purity of 6N and doped with boron (resistance value 0.0 Using a 1Ωcm resistor, the distance between the substrate and the target (TS distance) was 89mm, and the pressure was 0.4 Pa, DC power supply 6kW, pulsed DC under an oxygen (oxygen flow rate ratio 100%) atmosphere. A silicon oxide layer is formed by the puttering method. The thickness of the silicon oxide layer is 300 nm. This is the case. Furthermore, quartz (preferably synthetic quartz) may be used instead of a silicon target. Yes, it is possible. For the sputtering gas, oxygen or a mixture of oxygen and argon can be used.

[0305] Furthermore, with the protective insulating layer 396 and the oxide semiconductor layer 399 in contact, the temperature is 100°C to 40°C. It is preferable to perform the heat treatment at 0°C. This heat treatment allows the oxide semiconductor layer 399 to... Impurities such as hydrogen, water, hydroxyl groups, or hydrides are diffused into the protective insulating layer 396. This makes it possible to further reduce the impurities contained in the oxide semiconductor layer 399.

[0306] Through the above process, oxide semiconductors with reduced concentrations of hydrogen, water, hydroxyl groups, or hydrides are obtained. A transistor 390 having a body layer 392 can be formed (see Figure 15(E)). As described in this embodiment, when forming an oxide semiconductor layer, residuals in the reaction atmosphere By removing the water-retaining deposits, the concentrations of hydrogen and hydrides in the oxide semiconductor layer are reduced. This can be done. As a result, an intrinsic or substantially intrinsic semiconductor can be obtained.

[0307] Furthermore, an insulating layer may be provided on the protective insulating layer 396. In this embodiment, protective insulating An insulating layer 398 is formed on the edge layer 396. The insulating layer 398 is a silicon nitride film, nitride You can use silicon oxide film, aluminum nitride film, or aluminum nitride oxide film. stomach.

[0308] As a method for forming the insulating layer 398, the substrate 394 on which the protective insulating layer 396 has been formed is 10 Sputtered gas containing high-purity nitrogen, which has been heated to temperatures of 0°C to 400°C to remove hydrogen and moisture. A silicon nitride film is deposited using a silicon semiconductor target. In the same manner as the protective insulating layer 396, the insulating layer 398 is also treated while removing residual moisture in the processing chamber. It is preferable to form a film. When forming the insulating layer 398, the substrate 394 is heated to 100°C to 400°C. By heating, hydrogen or moisture contained in the oxide semiconductor layer 399 is removed from the insulating layer 398. It can be diffused. In this case, the heat treatment is not performed immediately after the formation of the protective insulating layer 396. It's fine.

[0309] Furthermore, a silicon oxide layer is formed as the protective insulating layer 396, and a silicon nitride layer is formed as the insulating layer 398. When forming the silicon oxide layer and silicon nitride layer in the same processing chamber, A silicon target can be used to deposit the film. First, an etching gas containing oxygen is introduced. Entering the chamber, a silicon oxide layer is formed using a silicon target installed inside the processing chamber, and then Then, the etching gas is switched to an etching gas containing nitrogen and the same silicon target is used. Then a silicon nitride layer is formed. The silicon oxide layer and the silicon nitride layer are not exposed to the atmosphere. Because it can be formed continuously, impurities such as hydrogen and moisture are absorbed onto the surface of the silicon oxide layer. This prevents adhesion. Furthermore, a silicon oxide layer is formed as the protective insulating layer 396, providing insulation. After laminating a silicon nitride layer as layer 398, hydrogen contained in the oxide semiconductor layer or A heat treatment (temperature between 100°C and 400°C) is performed to diffuse moisture into the oxide insulating layer. And is even more preferable.

[0310] After the formation of the protective insulating layer 396, it is further exposed to air at a temperature between 100°C and 200°C for at least 1 hour. Heat treatment may be performed for less than 0 hours. This heat treatment involves maintaining a constant heating temperature. Alternatively, you may raise the temperature from room temperature to a heating temperature of 100°C to 200°C, and then... The cooling process to room temperature may be repeated multiple times. Alternatively, this heat treatment can be performed in an oxide-free environment. The process may be carried out under reduced pressure before the formation of the margin layer. Heating under reduced pressure shortens the heating time. It is possible.

[0311] The above process is carried out at temperatures below 400°C, so the thickness is 1 mm or less and the length is 1 m on each side. It can also be applied to manufacturing processes using glass substrates exceeding 400°C. Since all processes can be carried out at the processing temperature, the energy required to manufacture the display panel is reduced. Consumption can be reduced.

[0312] The transistor having the oxide semiconductor layer described in this embodiment constitutes the display unit of the display device. By using it in the pixels that make up the structure, the off-current can be reduced. Therefore, the retaining capacitance This allows for a longer period during which the voltage can be maintained, thereby reducing power consumption when displaying still images, etc. This is possible. Furthermore, by stopping the control signal when displaying still images, low power consumption is achieved. It can be optimized. Furthermore, it can switch between still images and moving images without malfunction. .

[0313] (Embodiment 5) In this embodiment, an example of the structure of the first transistor 6401 described in Embodiment 1 is shown. An example of its manufacturing method will be described. That is, using a high-purity oxide semiconductor... An example of a transistor structure and an example of its fabrication method will be explained using Figure 16. .

[0314] Figures 16(A) to (D) show examples of the cross-sectional structure of a transistor. Transistor 360 shown in () is called a channel-protected type (also called a channel-stopped type). It is one of the bottom gate structures and is also called an inverse staggered transistor. Transistor 360 can be used as the first transistor 6401 described in Embodiment 1. Yes. Note that transistor 360 refers to a single-gate transistor, The present invention is not limited to this configuration, and may have multiple gate electrodes and a channel forming region It may also be a transistor with a multi-gate structure having multiple such elements.

[0315] The transistor 360 is fabricated on the substrate 320 using Figures 16(A) to (D) below. I will explain the method.

[0316] First, a conductive film is formed on the substrate 320, and then a first photolithography process is performed. A electrode 361 is formed. The material of the substrate 320 is the same as the substrate 3 described in Embodiment 4. Similar to 94 can be used. Also, the material and film deposition method of the gate electrode 361, etc. The gate electrode 391 described in Embodiment 4 can be the same as the one used in Embodiment 4.

[0317] Next, a gate insulating layer 322 is formed on the gate electrode 361. Regarding the material, the same material as that used for the gate insulating layer 397 described in Embodiment 4 should be adopted. This can be done. In this embodiment, the gate insulating layer 322 is made thick by plasma CVD. A silicon oxide nitride layer with a wavelength of 00 nm or less is formed.

[0318] Next, an oxide semiconductor layer with a thickness of 2 nm to 200 nm is formed on the gate insulating layer 322. The material is then processed into island-shaped oxide semiconductor layers using a second photolithography process. The materials, film formation method, and processing method for the oxide semiconductor layer are the same as those described in Embodiment 4 for the island-shaped oxide semiconductor layer. The same material as the conductive layer 399 can be used. In this embodiment, the oxide semiconductor layer For this purpose, a film is deposited by sputtering using an In-Ga-Zn-O based oxide semiconductor target. do.

[0319] Next, the oxide semiconductor layer is dehydrated or dehydrogenated. The temperature of the heat treatment in step 1 is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The value is set to less than 1. Here, a substrate is introduced into an electric furnace, which is one of the heat treatment devices, and an oxide semiconductor The body layer was subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. By preventing this, the re-importation of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 332 is obtained. (See Figure 16(A).)

[0320] Next, plasma treatment is performed using a gas such as N2O, N2, or Ar. The process removes adsorbed water and other substances adhering to the surface of the exposed oxide semiconductor layer. Alternatively, plasma treatment may be performed using a mixed gas of oxygen and argon.

[0321] Next, an oxide insulating layer was formed on the gate insulating layer 322 and the oxide semiconductor layer 332. Next, a resist mask is formed by a third photolithography process, followed by selective etching. After performing the procedure to form the oxide insulating layer 366, the resist mask is removed.

[0322] In this embodiment, a silicon oxide film with a thickness of 200 nm is sputtered as the oxide insulating layer 366. The film is deposited using the following method. The substrate temperature during film deposition should be between room temperature and 300°C. In this form, the temperature is set to 100°C. For silicon oxide film deposition by sputtering, a rare gas (typically...) is used. Under an argon atmosphere, under an oxygen atmosphere, or under a noble gas (typically argon) and oxygen atmosphere It can be carried out under gas. Also, silicon oxide target or silicon A target can be used. For example, a silicon target can be used in an oxygen and nitrogen atmosphere. A silicon oxide film can be formed by sputtering under gas pressure. The oxide insulating layer 366 that forms it contains moisture, hydrogen ions, and OH - It does not contain impurities such as An inorganic insulating film is used to block the intrusion of these from the outside, typically silicon oxide. Using films, silicon oxide nitride films, aluminum oxide films, or aluminum oxide nitride films, etc. It is possible to be there.

[0323] At this time, hydrogen, hydroxyl groups, or water are present in the oxide semiconductor layer 332 and the oxide insulating layer 366. To prevent contamination, the oxide insulating layer 366 is formed while removing residual moisture in the processing chamber. It is preferable to do so. Regarding the method for removing residual moisture in the processing chamber, see other embodiments. You can use the method described above.

[0324] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. It is preferable to perform the procedure at a temperature between 00°C and 400°C, for example, between 250°C and 350°C. For example, a second heat treatment is performed at 250°C for 1 hour under a nitrogen atmosphere. Then, when a portion of the oxide semiconductor layer (channel formation region) is in contact with the oxide insulating layer 366, To be heated.

[0325] In this embodiment, the oxide semiconductor layer in the region not covered by the oxide insulating layer 366 332 is heat-treated under nitrogen, an inert gas atmosphere, or under reduced pressure. Oxide insulating layer 3 The oxide semiconductor layer 332 in the region not covered by 66 is under a nitrogen, inert gas atmosphere. Alternatively, if heat treatment is performed under reduced pressure, dehydrogenation occurs simultaneously with oxygen deficiency, resulting in low resistance. It can be transformed. For example, a heat treatment at 250°C for 1 hour under a nitrogen atmosphere is recommended. .

[0326] Heat treatment of an oxide semiconductor layer 332 provided with an oxide insulating layer 366 under a nitrogen atmosphere As a result, the exposed region of the oxide semiconductor layer 332 has low resistance, while regions with different resistances (Figure 16) (B) is an oxide semiconductor layer 362 having the shaded region and the white region.

[0327] Next, on the gate insulating layer 322, the oxide semiconductor layer 362, and the oxide insulating layer 366, After forming the film, a resist mask is formed by a fourth photolithography step, and then selected After etching is performed to form the first electrode 365a and the second electrode 365b, then the resin Remove the tomask (see Figure 16(C)).

[0328] The materials for the first electrode 365a and the second electrode 365b are Al, Cr, Cu, Ta, An element selected from Ti, Mo, and W, or an alloy containing the above elements, or as described above. Examples include alloy films combining various elements. Furthermore, the metal conductive film may have a single-layer structure. It may also be a laminated structure of two or more layers.

[0329] Through the above process, the oxide semiconductor layer after film formation undergoes dehydration or dehydrogenation. After heat treatment to reduce resistance, a portion of the oxide semiconductor layer is selectively subjected to oxygen excess treatment. This state is assumed. As a result, the channel formation region 363 that overlaps with the gate electrode 361 is type I and As a result, a low-resistance source region 364a overlaps with the first electrode 365a, and the second electrode 365b... The overlapping low-resistance drain region 364b is formed in a self-aligned manner. Through the above process, A lunger 360 is formed.

[0330] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat it while maintaining the heating temperature, or you may heat it from room temperature to a heating temperature of 100°C to 200°C. The process of raising the temperature to a certain degree and then lowering it from the heating temperature back to room temperature may be repeated multiple times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. Doing so can shorten the heating time.

[0331] Furthermore, in the oxide semiconductor layer superimposed on the second electrode 365b (and the first electrode 365a) This forms a low-resistance drain region 364b (or low-resistance source region 364a). This can further improve the reliability of transistors. Specifically, the low-resistance drain region By forming region 364b, the drain electrode is separated from the low-resistance drain region 364b and the channel In the formation region 363, a structure can be created that allows for a stepwise change in conductivity. Therefore, it is operated by connecting it to the wiring that supplies a high power potential VDD to the second electrode 365b. In this case, even if a high electric field is applied between the gate electrode 361 and the second electrode 365b, the resistance remains low. The rain region acts as a buffer, preventing the application of a localized high electric field and improving the transistor's breakdown voltage. It can be configured in this way.

[0332] Next, a protective insulating layer is placed on the first electrode 365a, the second electrode 365b, and the oxide insulating layer 366. Form 323. In this embodiment, the protective insulating layer 323 is formed using a silicon nitride film. (See Figure 16(D).)

[0333] The transistor having the oxide semiconductor layer described in this embodiment constitutes the display unit of the display device. By using it in the pixels that make up the structure, the off-current can be reduced. Therefore, the retaining capacitance This allows for a longer period during which the voltage can be maintained, thereby reducing power consumption when displaying still images, etc. This is possible. Furthermore, power consumption is reduced by stopping the control signal when displaying still images. It can be made more efficient. Furthermore, it can switch between still images and moving images without malfunction. ru.

[0334] (Embodiment 6) This embodiment illustrates another example of a transistor applicable to the display device disclosed herein. The transistor 350 shown in this embodiment is used in each pixel of the pixel section of Embodiment 1. It can be used in transistors such as the 6401.

[0335] The transistor 350 shown in Figure 17(D) represents a single-gate transistor. However, the present invention is not limited to this configuration, and may have multiple gate electrodes and a channel It may also be a transistor with a multi-gate structure having multiple formation regions.

[0336] The transistor 350 is fabricated on the substrate 340 using Figures 17(A) to (D) below. Let me explain the process.

[0337] First, a conductive film is formed on the substrate 340, and then a first photolithography process is performed. A gate electrode 351 is formed. In this embodiment, the gate electrode 351 has a film thickness of 150 nm. The tungsten film is formed using the sputtering method.

[0338] Next, a gate insulating layer 342 is formed on the gate electrode 351. In this embodiment, A silicon oxide nitride film with a thickness of 100 nm or less is formed as the insulating layer 342 by plasma CVD. To accomplish.

[0339] Next, a conductive film is formed on the gate insulating layer 342, and then a conductive film is formed by a second photolithography process. A resist mask is formed on the film, and selective etching is performed on the source electrode 355a, After forming the rain electrode 355b, the resist mask is removed (see Figure 17(A)).

[0340] Next, an oxide semiconductor layer 345 is formed (see Figure 17(B)). In this embodiment, acid As the semiconductor layer 345, an In-Ga-Zn-O based metal oxide target is used in spa The film is formed by the tat method. Subsequently, the oxide semiconductor layer 345 is subjected to a third photolithography process. This process is used to create island-shaped oxide semiconductor layers.

[0341] In the process of forming the oxide semiconductor layer 345, residual moisture in the processing chamber is removed while acid is used. By forming the oxide semiconductor layer 345, hydrogen, hydroxyl groups or It is preferable to ensure that no moisture is present. Regarding the method for removing residual moisture in the processing chamber, Alternatively, the methods described in other embodiments can be used.

[0342] Next, a first heat treatment is performed to dehydrate or dehydrogenate the oxide semiconductor layer. The temperature of the first heat treatment is 400°C to 750°C, preferably 400°C or higher, to reduce substrate strain. The temperature should be below the 0.0 point. Here, the substrate is introduced into an electric furnace, which is one of the heat treatment devices, and the oxide semiconductor... The conductive layer was subjected to a heat treatment at 450°C for 1 hour under a nitrogen atmosphere, and then exposed to air. By preventing this, the re-importation of water and hydrogen into the oxide semiconductor layer is prevented, and the oxide semiconductor layer 346 Obtain (see Figure 17(C)).

[0343] Furthermore, as a first heat treatment, the base is placed in an inert gas heated to a high temperature of 650°C to 700°C. The board is moved and placed inside, heated for several minutes, then the substrate is moved and placed in a hot inert gas chamber. You may perform a GRTA (Great Value Analysis) from this source.

[0344] Next, an oxide insulating layer 356 is formed in contact with the oxide semiconductor layer 346. 56 has a film thickness of at least 1 nm, and impurities such as water and hydrogen are contained in the oxide insulating layer 356. It can be formed using appropriate methods that do not introduce contamination (e.g., sputtering). If hydrogen is present in the marginal layer 356, the hydrogen may penetrate into the oxide semiconductor layer, or the hydrogen may... Oxygen is extracted from the oxide semiconductor layer, resulting in lower resistance in the back channels of the oxide semiconductor layer. This can lead to (N-type conversion) and the formation of parasitic channels. Therefore, oxide insulation It is important to use a film deposition method that results in a film that contains as little hydrogen as possible for layer 356. .

[0345] Regarding the material and film formation method of the oxide insulating layer 356, please refer to the protection in Embodiment 4. A material similar to that used for insulating layer 396 can be employed.

[0346] Next, a second heat treatment (preferably 2) is performed under an inert gas atmosphere or an oxygen gas atmosphere. Perform the procedure at temperatures between 0°C and 400°C (for example, between 250°C and 350°C). For example, under a nitrogen atmosphere. A second heat treatment is performed at 250°C for 1 hour under gas pressure. After the second heat treatment, the oxide semiconductor The body layer is heated while in contact with the oxide insulating layer 356.

[0347] Through the above process, the oxide semiconductor layer after film formation undergoes dehydration or dehydrogenation. After reducing resistance through heat treatment for chemical conversion, the oxide semiconductor layer is subjected to an oxygen-rich state. As a result, a type I oxide semiconductor layer 352 is formed. Through the above process, a transistor is formed. 350 is formed.

[0348] Furthermore, a heat treatment is performed in air at a temperature between 100°C and 200°C for between 1 hour and 30 hours. This may be done. In this embodiment, the heat treatment is performed at 150°C for 10 hours. This heat treatment is constant You may heat it while maintaining the heating temperature, or you may heat it from room temperature to a heating temperature of 100°C to 200°C. The process of raising the temperature to a certain degree and then lowering it from the heating temperature back to room temperature may be repeated multiple times. This heat treatment may be performed under reduced pressure before the formation of the oxide insulating film. This process shortens the heating time. This heat treatment removes the oxide semiconductor layer By incorporating hydrogen into the oxide insulating layer, it is possible to obtain a transistor that is normally off. This allows for improved reliability of the display device.

[0349] Furthermore, an insulating layer may be provided on the oxide insulating layer 356. In this embodiment, An insulating layer 343 is formed on the material insulating layer 356 (see Figure 17(D)). The materials and film formation method are the same as those used for the protective insulating layer 398 in Embodiment 4. It is possible.

[0350] Furthermore, a planarizing insulating layer may be provided for the purpose of planarizing the surface on the insulating layer 343.

[0351] The transistor having the oxide semiconductor layer described in this embodiment constitutes the display unit of the display device. By using it in the pixels that make up the structure, the off-current can be reduced. Therefore, the retaining capacitance This allows for a longer period during which the voltage can be maintained, thereby reducing power consumption when displaying still images, etc. This is possible. Furthermore, power consumption is reduced by stopping the control signal when displaying still images. It can be made more efficient. Furthermore, it can switch between still images and moving images without malfunction. ru.

[0352] (Embodiment 7) This embodiment describes one type of display device in which a phosphorescent layer is provided in the pixel portion.

[0353] Figure 18 is a cross-sectional view of the pixel portion of the bottom-face injection structure, and the transistors (drivers) provided in the pixels are shown. A transistor 7211 (for use with transistor 7211) and a light-emitting element 7 electrically connected to the transistor 7211. This is a cross-sectional view of the cross-section including 212.

[0354] The transistor 7211 has an insulating layer, an oxide semiconductor layer, a source electrode layer and a drain on the substrate. It has an in electrode layer, a gate insulating layer, and a gate electrode layer, and the source electrode layer and drain electrode layer Each wiring layer is electrically connected and installed.

[0355] Furthermore, an insulating layer 7231 is formed covering the transistor 7211, and on the insulating layer 7231 A phosphorescent layer 7233 having an opening is provided. Also, a layer is formed covering the phosphorescent layer 7233. A transparent conductive film 7217 is applied to the overcoat layer 7234 and insulating layer 7235. A conductive film 721 is formed on the drain electrode 7230 of transistor 7211. 7 consists of a phosphorescent layer 7233, an overcoat layer 7234, an insulating layer 7235, and an insulating layer 723 It is electrically connected through the opening formed in 1. Also, a light-emitting element is on the conductive film 7217. The first electrode 7213 of the sub 7212 is provided in contact with it. The light-emitting element 7212 is The structure has an EL layer 7214 sandwiched between the first electrode 7213 and the second electrode 7215, A shielding film 7216 is provided on electrode 2 7015.

[0356] The transistor 7211 and the light-emitting element 7212 will be described in Embodiments 3 to 6. Since it can be manufactured using the same method, a detailed explanation will be omitted here.

[0357] The phosphorescent layer 7233 contains a phosphorescent material and stores light emitted by adjacent light-emitting elements. Even after the light-emitting element stops emitting light, the phosphorescent material contained in the phosphorescent layer 7233 continues to emit light. In this embodiment, copper-plated activated zinc sulfide (ZnS:Cu) is used as the phosphorescent material. Phosphors are created by adding activators to sulfides such as trontium (SrS) as a base, or by adding rare earth elements. Activated alkaline earth aluminates can also be used. Alkali with activated rare earth elements. Specific examples of earth metal aluminates include CaAl2O4:Eu, CaAl2O4:Nd, and S r4Al 14 O 25 :Eu,Sr4Al 14 O 25 :Dy, SrAl2O4:Eu, and SrAl2O4:Dy is one example. Furthermore, when using inorganic particles as phosphorescent materials, the particle size... If the particle size is less than 1 nm, the phosphorescence may be lost. Also, if the particle size is 10 μm or larger... In this case, the flatness of the phosphorescent layer may be impaired, making it difficult to manufacture the light-emitting element. Therefore, it is preferable that the particle size be between 1 nm and 10 μm.

[0358] The duration for which the phosphorescent layer 7233 continues to emit light can be varied depending on the type of phosphorescent material used. In other words, the duration of luminescence, or afterglow time, differs depending on the type of phosphorescent material. You should select the material according to the application. For example, if the display content does not need to be rewritten frequently... Electronic devices equipped with display devices used in the process (for example, electronic paper) have a long afterglow time. It is preferable to select and use phosphorescent materials. Also, it is not necessary to rewrite the display relatively frequently. An electronic device equipped with a display device for a certain purpose (for example, a television receiver) has a afterglow time. It is preferable to select and use short pieces of phosphorescent material.

[0359] Furthermore, the phosphorescent layer 7233 may also contain a binder polymer. In this case, the phosphorescent material Inkjet and other droplet ejection methods, printing methods, and spin coating methods using dispersed dispersions. The etching method using photolithography technology can be appropriately selected to form the object. ru.

[0360] Furthermore, in order to flatten the unevenness on the surface of the phosphorescent layer 7233, the surface of the phosphorescent layer 7233 is overlaid. - It is preferable to cover it with a coat layer 7234. Also, the overcoat layer 7234 is covered with an insulating layer 7 It is preferable to cover with 235. Note that in Figure 18, the overcoat layer 7234 and A contact hole formed in the protective insulating layer 7235 and reaching the drain electrode 7230. It is positioned in a location that overlaps with bulkhead 7219.

[0361] Furthermore, the position where the phosphorescent layer 7233 is provided is limited to the space between the user of the display device and the light-emitting element. No. For example, a light-emitting element with a double-sided injection structure in which an EL layer is sandwiched between a pair of translucent electrodes is It is translucent. When the light-emitting element is translucent in this way, the phosphorescent layer 7233 is used for display. It can be placed on the back side of the light-emitting layer from the user's perspective. In other words, the phosphorescent layer can be placed on the back side of the light-emitting layer. It is also possible to place a light-emitting element between the device and the user. When placed between the user and the phosphorescent layer, the phosphorescent layer does not necessarily need to be light-transmitting, therefore This broadens the range of material choices. Specifically, it allows for phosphorescent materials with a particle size of 100 μm or less. It will become available.

[0362] As described above, the display device described in this embodiment has a high-purity oxide semiconductor layer In addition to the transistors, the pixel portion includes a phosphorescent layer. Such a display device has an off-current In addition to having transistors with reduced emission in the pixels, the pixels also have a phosphorescent layer, thus reducing the emission element It has the characteristic that even if the interval between flashes is long, the flicker is not noticeable. In this embodiment, the display device suppresses power consumption and also displays still images. It can be made to be of superior quality.

[0363] (Embodiment 8) In this embodiment, the electronic device is equipped with the display device described in the above embodiment. Examples will be explained. However, the electronic devices to which the present invention can be applied are not limited to the specific examples shown below. It is not something that can be determined.

[0364] The electronic device shown in Figure 19(A) is a portable gaming machine, comprising a casing 9630, a display unit 9631, Speaker 9633, operation keys 9635, connection terminal 9636, recording medium reading unit 9672, etc. It possesses. Furthermore, portable gaming machines can read programs or data recorded on a recording medium. Functions to display information on the display unit, and functions to share information via wireless communication with other portable gaming machines. They may also have the following. However, the functions of a portable gaming machine are not limited to these, and various other functions may be included. It can have the ability.

[0365] The electronic device shown in Figure 19(B) is a digital camera, consisting of a housing 9630 and a display unit 9631. Speaker 9633, Operation key 9635, Connection terminal 9636, Shutter button 9676 It has an image receiving unit 9677, etc. Digital cameras have functions for taking still images and shooting videos. Functions include: correcting captured images automatically or manually, and storing captured image information in a memory element. It has functions such as saving, displaying captured image information on the display unit, and receiving television signals. It is also acceptable. Furthermore, the functions of a digital camera are not limited to these, and it may have a variety of other functions. It is possible.

[0366] The electronic device shown in Figure 19(C) is a television receiver, comprising a housing 9630, a display unit 9631, It has a speaker 9633, operation keys 9635, connection terminals 9636, etc. The television receiver is A function that processes television signals and converts them into image signals, and processes image signals to create signals suitable for display. It may also have functions for converting to, or functions for converting the frame frequency of an image signal. However, the functions of a television receiver are not limited to these, and it can have a variety of functions.

[0367] The electronic device shown in Figure 20(A) is a computer, comprising a housing 9630, a display unit 9631, Speaker 9633, operation key 9635, connection terminal 9636, pointing device 96 It has external connection ports such as 81 and 9680. The computer can handle various types of information (still images, videos). Functions to display text, images, etc. on the display unit, and various software (programs) This includes functions to control processing, communication functions such as wireless or wired communication, and various functions using communication functions. Functions to connect to computer networks, and to transmit various data using communication functions or It may also have functions for receiving data. However, the functions of a computer are not limited to this. It can have various functions.

[0368] The electronic device shown in Figure 20(B) is a mobile phone, and consists of a housing 9630, a display unit 9631, and It has a speaker 9633, operation keys 9635, a microphone 9638, etc. The mobile phone is Features that display various information (still images, videos, text images, etc.), calendar, date or This includes functions for displaying the time and other information on the display unit, functions for manipulating or editing the information displayed on the display unit, and It may have functions to control processing by various software (programs). However, the functions that a mobile phone can have are not limited to these; it can have a variety of functions.

[0369] The electronic device shown in Figure 20(C) is an electronic paper, and consists of a housing 9630, a display unit 9631, It has operation keys 9635, etc. Electronic paper displays various information (still images, videos, text images). Functions to display images, etc., a calendar, date or time, etc. on the display unit, display Functions to manipulate or edit information displayed in the section, through various software (programs) It may also have functions to control processing, etc. However, the functions of electronic paper are not limited to these. It is not fixed and can have various functions. Also, specific examples of applications using electronic paper. Examples include ebooks (also called electronic books or e-books), posters, and train advertisements. Examples include in-vehicle advertisements for goods.

[0370] The electronic device shown in Figure 20(D) is a digital photo frame, and the housing 9701 has a display unit The 9703 is incorporated. The display unit 9703 is capable of displaying various images. For example, by displaying image data taken with a digital camera, it can be used in a regular photo frame. It can be made to function similarly.

[0371] The digital photo frame includes an operating unit and external connection terminals (USB terminal, USB cable, etc.). It has terminals that can be connected to various types of cables, a recording medium insertion section, etc. These configurations While it may be integrated on the same surface as the display unit, placing it on the side or back improves the design. This is preferable. For example, a digital camera is inserted into the recording medium insertion section of a digital photo frame. Insert the memory containing the image data captured by the camera and import the image data. Image data can be displayed on the display unit 9703.

[0372] Furthermore, digital photo frames may also have the ability to send and receive information wirelessly. i. In this case, the desired image data is wirelessly captured and displayed on the digital photo frame. It can be made to do so. Furthermore, the functions of a digital photo frame are not limited to these. It can have various functions.

[0373] By applying a display device according to one aspect of the present invention to these electronic devices, still images and the like can be displayed. This allows for lower power consumption during display. Therefore, displaying still images is preferable to displaying videos. This product is for electronic devices such as digital cameras, e-paper displays, and digital photo frames, which are frequently used. When a display device, which is one aspect of the invention, is applied, the effect of reducing power consumption becomes remarkably apparent, Particularly preferable. [Explanation of Symbols]

[0374] 1000 display devices 1001 Display Panel 1002 Signal generation circuit 1003 Memory circuit 1004 Comparison circuit 1005 Selection Circuit 1006 Display control circuit 1007 Drive circuit section 1008 pixel section 1009A Gate wire drive circuit 1009B Signal Line Drive Circuit 1010 frame memory

Claims

1. A display device having a function to change the frequency of writing image signals to the pixel section, The display device comprises the pixel section, a gate line driving circuit, and a conductive film. The pixel section includes a first transistor, a second transistor, a light-emitting element, a signal line, and a power line. Each of the first transistor and the second transistor has an oxide semiconductor in the channel formation region. The source electrode or drain electrode of the first transistor is always in electrical contact with the signal line. The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the second transistor is always in electrical contact with the pixel electrode of the light-emitting element. The gate line driving circuit has a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film, At least one of the source or drain electrodes of one of the plurality of third transistors is always in electrical contact with the gate of the first transistor via the scan line. The conductive film is given a power supply potential. Display device.

2. A display device having a function to change the frequency of writing image signals to the pixel section, The display device comprises the pixel section, a gate line driving circuit, and a conductive film. The pixel section includes a first transistor, a second transistor, a light-emitting element, a signal line, and a power line. Each of the first transistor and the second transistor has an oxide semiconductor in the channel formation region. The source electrode or drain electrode of the first transistor is always in electrical contact with the signal line. The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the second transistor is always in electrical contact with the pixel electrode of the light-emitting element. The gate line driving circuit has a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film, At least one of the source or drain electrodes of one of the plurality of third transistors is always in electrical contact with the gate of the first transistor via the scan line. The conductive film is given a power supply potential. The conductive film has an overlap with the region between the pixel portion and the gate line driving circuit. Display device.

3. A display device having a function to change the frequency of writing image signals to the pixel section, The display device comprises the pixel section, a gate line driving circuit, and a conductive film. The pixel section includes a first transistor, a second transistor, a light-emitting element, a signal line, and a power line. Each of the first transistor and the second transistor has an oxide semiconductor in the channel formation region. The source electrode or drain electrode of the first transistor is always in electrical contact with the signal line. The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the second transistor is always in electrical contact with the pixel electrode of the light-emitting element. The gate line driving circuit has a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film, At least one of the source or drain electrodes of one of the plurality of third transistors is always in electrical contact with the gate of the first transistor via the scan line. The conductive film is given a power supply potential. Display device.

4. A display device having a function to change the frequency of writing image signals to the pixel section, The display device comprises the pixel section, a gate line driving circuit, and a conductive film. The pixel section includes a first transistor, a second transistor, a light-emitting element, a signal line, and a power line. Each of the first transistor and the second transistor has an oxide semiconductor in the channel formation region. The source electrode or drain electrode of the first transistor is always in electrical contact with the signal line. The source electrode or drain electrode of the first transistor is always in electrical contact with the gate electrode of the second transistor. The source electrode or drain electrode of the second transistor is always in electrical contact with the power line. The source electrode or drain electrode of the second transistor is always in electrical contact with the pixel electrode of the light-emitting element. The gate line driving circuit has a plurality of third transistors arranged below the conductive film so as to overlap with the conductive film, At least one of the source or drain electrodes of one of the plurality of third transistors is always in electrical contact with the gate of the first transistor via the scan line. The conductive film is given a power supply potential. The power supply potential is applied to the common electrode of the light-emitting element. The conductive film has an overlap with the region between the pixel portion and the gate line driving circuit. Display device.

5. In any one of claims 1 to 4, The pixel portion has a capacitive element, One electrode of the capacitive element is always in electrical contact with the pixel electrode of the light-emitting element. The other electrode of the capacitive element is always in electrical contact with the gate electrode of the second transistor. Display device.

6. In any one of claims 1 to 4, The oxide semiconductor is an In-Ga-Zn-O system, In-Sn-Zn-O system, Sn-Ga-Zn-O system, Al-Ga-Zn-O system, Sn-Al-Zn-O system, In-Zn-O system, In-Sn-O system, Sn-Zn-O system, Al-Zn-O system, In-O system, Sn-O system, Zn-O system, or In-Al-Zn-O system oxide semiconductor. Display device.

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