Indication device

Abstract

Embodiments of the present invention disclose a display device that prevents disconnection of the semiconductor layer due to a lower step by having a conductive layer located below the semiconductor layer of a drive transistor correspond to at least the channel region of the semiconductor layer, and secures a large capacitance by forming a capacitor with a plurality of conductive layers located below and above the semiconductor layer superimposed on the channel region of the semiconductor layer. A display device according to one embodiment includes a first conductive wire, a first electrode located on and superimposed on the first conductive wire, a semiconductor layer located on and superimposed on the first electrode, a second electrode located on the semiconductor layer and superimposed on the first electrode, and a third electrode located on and superimposed on the second electrode, electrically connected to the semiconductor layer and the first electrode, characterized in that the region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

Description

Technical Field

[0001] The present invention relates to pixels and display devices including the same.

Background Art

[0002] In recent years, the applications of display devices have been diversified. Further, the display devices tend to have a reduced thickness, a reduced weight, and a wider range of use.

[0003] As display devices are utilized in various ways, there can be various methods for designing the form of display devices, and the functions applicable or coordinated with display devices are increasing.

Summary of the Invention

Problems to be Solved by the Invention

[0004] Embodiments of the present invention can provide a display device with improved display quality. However, such problems are exemplary and do not limit the scope of the present invention.

Means for Solving the Problems

[0005] A display device according to an embodiment of the present invention includes: a first conductive line; a first electrode disposed on the first conductive line and overlapping the first conductive line; a semiconductor layer disposed on the first electrode and overlapping the first electrode; a second electrode disposed on the semiconductor layer and overlapping the first electrode; a third electrode disposed on the second electrode and overlapping the second electrode, and electrically connected to the semiconductor layer and the first electrode; wherein a region of the semiconductor layer overlapping the second electrode overlaps the first conductive line.

[0006] In one embodiment, the display device further includes: a fourth electrode disposed in the same layer as the third electrode and electrically connected to the second electrode; a fifth electrode disposed on the fourth electrode and overlapping the fourth electrode, and electrically connected to the third electrode.

[0007] In one embodiment, the display device further includes a sixth electrode arranged on the same layer as the first conductive wire, wherein the first electrode, the second electrode and the third electrode are superimposed on the sixth electrode, and the second electrode may be electrically connected to the sixth electrode.

[0008] In one embodiment, the display device has an opening defined in the first electrode that overlaps the sixth electrode, and the second electrode may be electrically connected to the sixth electrode through the opening.

[0009] In one embodiment, the display device further includes a seventh electrode arranged on the same layer as the third electrode and electrically connected to the second electrode; and an eighth electrode arranged on the seventh electrode, superimposed on the seventh electrode, and electrically connected to the third electrode.

[0010] In one embodiment, the display device further includes a second conductive wire spaced apart from the first conductive wire, wherein the voltage applied to the second conductive wire is different from the voltage applied to the first conductive wire.

[0011] In one embodiment, the first electrode is superimposed on the second conductive wire.

[0012] A display device according to one embodiment of the present invention includes: a first circuit region where a pixel circuit for a first pixel is arranged; a second circuit region where a pixel circuit for a second pixel is arranged; a first conductive wire arranged in the first circuit region and the second circuit region; a first electrode arranged in the first circuit region and the second circuit region respectively, which is placed on the first conductive wire and superimposed on the first conductive wire; a semiconductor layer placed on the first electrode and superimposed on the first electrode; a second electrode placed on the semiconductor layer and superimposed on the first electrode; and a third electrode placed on the second electrode, superimposed on the second electrode, and electrically connected to the semiconductor layer and the first electrode; wherein the region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

[0013] In one embodiment, the display device further includes: a fourth electrode arranged on the same layer as the third electrode and electrically connected to the second electrode, respectively, in the first and second circuit regions; and a fifth electrode arranged on the fourth electrode, superimposed on the fourth electrode, and electrically connected to the third electrode.

[0014] In one embodiment, the display device further includes a sixth electrode arranged on the same layer as the first conductive wire in the first circuit region, wherein the first electrode, the second electrode and the third electrode are superimposed on the sixth electrode, and the second electrode is electrically connected to the sixth electrode.

[0015] In one embodiment, in the first circuit region, an opening is defined on the first electrode that overlaps the sixth electrode, and the second electrode is electrically connected to the sixth electrode through the opening.

[0016] In one embodiment, the display device further includes: a seventh electrode arranged on the same layer as the third electrode and electrically connected to the second electrode, respectively, in the first and second circuit regions; and an eighth electrode arranged on the seventh electrode, superimposed on the seventh electrode, and electrically connected to the third electrode.

[0017] A display device according to one embodiment of the present invention includes: a first circuit region where a pixel circuit for a first pixel is arranged; a second circuit region where a pixel circuit for a second pixel is arranged; a first conductive wire arranged in the first and second circuit regions; a second conductive wire spaced apart in the same layer as the first conductive wire in the first and second circuit regions; a first electrode arranged in the first and second circuit regions, respectively, on the first conductive wire and superimposed on the first conductive wire; a semiconductor layer arranged on the first electrode and superimposed on the first electrode; a second electrode arranged on the semiconductor layer and superimposed on the first electrode; and a third electrode arranged on the second electrode, superimposed on the second electrode, and electrically connected to the semiconductor layer and the first electrode; wherein the region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

[0018] In one embodiment, the display device further includes: a fourth electrode arranged on the same layer as the third electrode and electrically connected to the second electrode, respectively, in the first and second circuit regions; and a fifth electrode arranged on the fourth electrode, superimposed on the fourth electrode, and electrically connected to the third electrode.

[0019] In one embodiment, the display device further includes a sixth electrode arranged on the same layer as the first conductive wire in the first circuit region, wherein the first electrode, the second electrode and the third electrode are superimposed on the sixth electrode, and the second electrode is electrically connected to the sixth electrode.

[0020] In one embodiment, in the first circuit region, an opening is defined on the first electrode that overlaps the sixth electrode, and the second electrode is electrically connected to the sixth electrode through the opening.

[0021] In one embodiment, the display device further includes: a seventh electrode arranged on the same layer as the third electrode and electrically connected to the second electrode, respectively, in the first and second circuit regions; and an eighth electrode arranged on the seventh electrode, superimposed on the seventh electrode, and electrically connected to the third electrode.

[0022] In one embodiment, the third circuit region further includes a third circuit region in which the pixel circuit of the third pixel is arranged, the first conductive wire and the second conductive wire extend into the third circuit region, the first conductive wire includes a plurality of spaced subconducting wires, and the region superimposed on the second electrode of the semiconductor layer arranged in the third circuit region is located between the subconducting wires.

[0023] In one embodiment, the first electrode is superimposed on the second conductive wire.

[0024] In one embodiment, the area over which the first electrode arranged in the first circuit region overlaps the second conductive wire is different from the area over which the first electrode arranged in the second circuit region overlaps the second conductive wire. [Effects of the Invention]

[0025] According to an embodiment of the present invention, a display device with improved display quality can be provided. Needless to say, the scope of the present invention is not limited by such an effect.

Brief Description of the Drawings

[0026] [Figure 1A] It is a diagram schematically showing a display device according to an embodiment. [Figure 1B] It is a diagram schematically showing a display device according to an embodiment. [Figure 2] It is a diagram schematically showing a display device according to an embodiment. [Figure 3] It is a diagram schematically showing the arrangement of light-emitting regions of a plurality of pixels according to an embodiment. [Figure 4] It is a schematic diagram of an equivalent circuit of a pixel according to an embodiment. [Figure 5] It is an arrangement diagram schematically showing the positions of a transistor and a capacitor of a pixel according to an embodiment. [Figure 6] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 7] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 8] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 9] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 10] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 11A] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 11B] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 12] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 13] It is an arrangement diagram schematically showing the components of a pixel by layer. [Figure 14]This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 15] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 16] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 17] These are schematic cross-sectional views taken along lines Ia-Ia' and IIa-IIa' in Figures 5 and 16. [Figure 18] These are schematic cross-sectional views taken along lines Ia-Ia' and IIa-IIa' in Figures 5 and 16. [Figure 19] These are schematic cross-sectional views taken along Ic-Ic' and IIc-IIc' in Figures 5 and 16. [Figure 20] This is a schematic diagram showing the arrangement relationship between the conductive layer and the semiconductor layer in a comparative example. [Figure 21] This is a schematic diagram showing the arrangement relationship between the conductive layer and the semiconductor layer in a comparative example. [Figure 22] This is a schematic diagram of an equivalent pixel circuit according to one embodiment. [Figure 23] This is a schematic arrangement diagram showing the positions of transistors and capacitors in a pixel according to one embodiment. [Figure 24] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 25] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 26] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 27] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 28] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 29A] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 29B] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 29C] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 30]This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 31] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 32] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 33] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 34] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 35] These are schematic cross-sectional views taken along IVa-IVa' and Va-Va' in Figures 23 and 34. [Figure 36] These are schematic cross-sectional views taken along IVb-IVb' and Vb-Vb' in Figures 23 and 34. [Figure 37] These are schematic cross-sectional views taken along IVc-IVc' and Vc-Vc' in Figures 23 and 34. [Figure 38] This is a schematic diagram of an equivalent pixel circuit according to one embodiment. [Figure 39] This is a schematic arrangement diagram showing the positions of transistors and capacitors in a pixel according to one embodiment. [Figure 40] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 41] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 42] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 43] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 44] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 45A] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 45B] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 46] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 47] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 48] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 49] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 50] This is a schematic diagram showing the constituent elements of a pixel layer by layer. [Figure 51] These are schematic cross-sectional views taken along lines VI-VI' and VII-VII' in Figures 39 and 50. [Figure 52A] This is a schematic cross-sectional view showing the structure of a display element according to one embodiment. [Figure 52B] This is a schematic cross-sectional view showing the structure of a display element according to one embodiment. [Figure 52C] This is a schematic cross-sectional view showing the structure of a display element according to one embodiment. [Figure 52D] This is a schematic cross-sectional view showing the structure of a display element according to one embodiment. [Figure 53A] This is a schematic cross-sectional view showing the structure of a display element according to one embodiment. [Figure 53B] This is a schematic cross-sectional view showing the structure of a display element according to one embodiment. [Figure 54] This is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment. [Modes for carrying out the invention]

[0027] A display device according to one embodiment of the present invention includes: a first conductive wire; a first electrode disposed on the first conductive wire and superimposed on the first conductive wire; a semiconductor layer disposed on the first electrode and superimposed on the first electrode; a second electrode disposed on the semiconductor layer and superimposed on the first electrode; and a third electrode disposed on the second electrode and superimposed on the second electrode, electrically connected to the semiconductor layer and the first electrode; wherein the region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

[0028] The embodiments will be described in detail below with reference to the following. These examples are illustrated in the accompanying drawings, and similar reference numerals throughout indicate similar elements. In this regard, the embodiments are not limited to those described herein and may be embodied in other forms. Therefore, the embodiments will be described below with reference to the drawings only in order to illustrate the points of this description.

[0029] The term "and / or" includes all possible combinations of one or more configurations that the relevant configurations may define. For example, "A and / or B" is understood to mean "A, B, or A and B." For the purposes of this invention, the phrase "at least one of A and B" may be interpreted as A alone, B alone, or any combination of A and B. Similarly, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as X alone, Y alone, Z alone, or any combination of two or more of X, Y, and Z.

[0030] The present invention can be subjected to various transformations and has a variety of embodiments. Specific embodiments are illustrated in the drawings and described in detail in the detailed description. The effects and features of the present invention, and how they are achieved, will become clear with reference to the embodiments described in detail below, along with the drawings. However, the present invention is not limited to the embodiments disclosed below and can be embodied in a variety of forms.

[0031] In the following embodiments, terms such as "first," "second," etc., are not limited in meaning but are used to distinguish one component from other components.

[0032] In the following embodiments, a singular expression includes multiple expressions unless they imply a clearly different meaning in context.

[0033] In the following embodiments, terms such as “includes” or “has” mean that the features or components described in the specification are present, and do not preclude the possibility that one or more other features or components may be added.

[0034] In the following embodiments, when a part such as a membrane, region, or component is located above or above another part, this includes not only cases where it is directly above the other part, but also cases where another membrane, region, component, etc. is interposed between them.

[0035] In the following embodiments, when X and Y are said to be connected, this can include cases where X and Y are electrically connected, functionally connected, or physically connected. When X and Y are said to be connected to each other, this means cases where X and Y are directly connected to each other or indirectly connected to each other. Here, X and Y may be objects (e.g., devices, elements, circuits, wiring, electrodes, terminals, conductive films, layers, etc.). Therefore, the connections are not limited to predetermined connections, such as those shown in the drawings or detailed description, but may also include connections other than those shown in the drawings or detailed description.

[0036] When X and Y are electrically connected, this can include, for example, cases where X and Y are directly electrically connected to each other, and cases where one or more elements (e.g., switches, transistors, capacitive elements, inductors, resistive elements, diodes, etc.) that enable the electrical connection between X and Y are connected between X and Y.

[0037] In the following embodiments, "ON" as used in relation to the state of an element refers to an activated state, and "OFF" refers to an inactivated state. "ON" as used in relation to signals received by an element may refer to a signal that activates the element, and "OFF" may refer to a signal that deactivates the element. An element can be activated by a high-level or low-level voltage. For example, a P-channel transistor (P-type transistor) is activated by a low-level voltage, and an N-channel transistor (N-type transistor) is activated by a high-level voltage. Therefore, it must be understood that the "ON" voltages for P-type and N-type transistors are at opposite (low / high) voltage levels.

[0038] In the following embodiments, the x, y, and z directions are not limited to directions along the three axes on a Cartesian coordinate system, but can be interpreted in a broader sense that includes these directions. For example, the x, y, and z directions may be orthogonal to each other, but they may also refer to different directions that are not orthogonal to each other.

[0039] Unless otherwise defined or suggested herein, all terms used herein (including technical and scientific terms) have the same meaning as generally understood by those skilled in the art. Terms defined in general dictionaries should also be interpreted in accordance with their meaning in the context of the relevant technology and the content of this disclosure, and should not be interpreted in an ideal or overly formal sense unless specifically defined. A display device according to an embodiment of the present invention is a device for displaying moving images or still images and can be used as a display screen for various products, including not only portable electronic devices such as mobile phones, smartphones, tablet personal computers, mobile communication terminals, electronic organizers, e-books, portable multimedia players (PMPs), navigation systems, and Ultra Mobile PCs (UMPCs), but also televisions, laptops, monitors, billboards, and the Internet of Things (IoT). Furthermore, a display device 1 according to one embodiment can be used in wearable devices such as smartwatches, watch phones, eyeglass displays, and head-mounted displays (HMDs). Furthermore, a display device according to one embodiment can be used as an instrument panel in an automobile, a Center Information Display (CID) located in the center fascia or dashboard of an automobile, a rearview mirror display replacing a side mirror in an automobile, or a display located on the back of the front seat as entertainment for the rear seats of an automobile. The display device may also be a flexible device.

[0040] Figures 1A and 1B schematically show a display device according to one embodiment. Figure 2 schematically shows a display panel 10 according to one embodiment.

[0041] Referring to Figures 1A and 1B, the display device includes a display area DA for displaying an image and a peripheral area PA outside the display area DA. The display area DA may be entirely surrounded by the peripheral area PA.

[0042] When viewed in planar terms, the display area DA is rectangular. In other embodiments, the display area DA may be a polygon such as a triangle, pentagon, or hexagon, a circle, an ellipse, or an irregular shape. The display area DA may have rounded corners at its edges. In one embodiment, the display device may have a display area DA with a shape in which the length in the x-direction is longer than the length in the y-direction, as shown in Figure 1A. In another embodiment, the display device may have a display area DA with a shape in which the length in the y-direction is longer than the length in the x-direction, as shown in Figure 1B.

[0043] The display device includes a display panel 10, and a cover window (not shown) is positioned above the display panel 10 to protect it.

[0044] Various components constituting the display panel 10 may be arranged on the substrate 100. The substrate 100 and / or the display panel 10 include a display area DA and a peripheral area PA surrounding the display area DA.

[0045] The substrate 100 may contain at least one diverse material, such as glass, ceramic, metal, or a material having flexible or bendable properties. The substrate 100 has a single-layer structure of organic layers or a multilayer structure of organic and inorganic layers. For example, the substrate 100 has a laminated structure of a first base layer / barrier layer / second base layer. The first base layer and the second base layer may each be organic layers containing a polymer resin. The first base layer and the second base layer contain a transparent polymer resin. The barrier layer is a barrier layer that prevents the penetration of external foreign matter and may be a single layer or multilayer containing an inorganic material such as silicon nitride (SiNx) or silicon oxide (SiOx).

[0046] Pixels PX may be arranged in the display area DA. The display area DA may contain gate lines GL, data lines DL, and pixels PX connected to them. Pixels PX can be arranged in various configurations, such as stripe, pentile, diamond, and mosaic arrangements, to display an image. Each pixel PX includes an organic light-emitting diode (OLED) as a display element (light-emitting element), and the OLED may be connected to the pixel circuit. The pixel circuit may include multiple transistors and at least one capacitor. Pixels PX emit, for example, red, green, blue, or white light through the OLED. Each pixel PX may be connected to a corresponding gate line among the gate lines GL and a corresponding data line among the data lines DL.

[0047] Each gate line GL can extend in the x-direction (row direction) and be connected to a pixel PX located in the same row. Each gate line GL transmits a gate signal to each pixel PX in the same row. Each data line DL can extend in the y-direction (cross direction) and be connected to a pixel PX located in the same column. Each data line DL transmits a data signal to each pixel PX in the same column, synchronized with the gate signal. Each pixel PX can be connected to a drive voltage line PL to be supplied with a drive voltage ELVDD. Each drive voltage line PL can extend in the y-direction (cross direction) and be connected to a pixel PX located in the same column.

[0048] Figure 2 shows an example where a pixel PX is connected to a single gate line GL, but the embodiments of the present invention are not limited to this. A pixel PX can be connected to one or more gate lines GL.

[0049] Each pixel circuit that drives a pixel PX may be electrically connected to an outer circuit located in the peripheral region PA. In one embodiment, the peripheral region PA may include a first gate drive circuit GDRV1, a second gate drive circuit GDRV2, a terminal section PAD, a drive voltage supply line 11, and a common voltage supply line 13.

[0050] In one embodiment, the peripheral region PA may be a non-display area where no pixels PX are located. In another embodiment, pixels PX may be arranged superimposed on the outer circuit at at least one corner of the peripheral region PA. This reduces the dead area and expands the display area DA.

[0051] The first gate drive circuit GDRV1 is connected to the gate line GL and can apply a gate signal to each pixel circuit that drives the pixel PX via the gate line GL. The second gate drive circuit GDRV2 is located on the opposite side of the first gate drive circuit GDRV1 with respect to the display area DA and is substantially parallel to the first gate drive circuit GDRV1. In one embodiment, the pixel circuits of the pixels PX in the display area DA may be electrically connected to the first gate drive circuit GDRV1 and the second gate drive circuit GDRV2. In another embodiment, some of the pixel circuits of the pixels PX in the display area DA may be electrically connected to the first gate drive circuit GDRV1, and the remainder may be electrically connected to the second gate drive circuit GDRV2. The second gate drive circuit GDRV2 may be omitted.

[0052] The terminal pad is located on one side of the circuit board 100. The terminal pad is exposed and not covered by an insulating layer, and can be connected to the display circuit board 30. The display drive unit 32 is located on the display circuit board 30.

[0053] The display drive unit 32 includes a data drive circuit, which is connected to a data line DL and generates a data signal. The generated data signal can be transmitted to the pixel circuit of the pixel PX via a fan-out line FW and a data line DL connected to the fan-out line FW.

[0054] The display drive unit 32 includes a power supply circuit, which supplies a drive voltage ELVDD to a drive voltage supply line 11 and a common voltage ELVSS to a common voltage supply line 13. The drive voltage ELVDD is applied to the pixel circuit of the pixel PX via the drive voltage line PL of the display area DA, which is connected to the drive voltage supply line 11, and the common voltage ELVSS may be applied to the counter electrode of the display element via the common voltage supply line 13. In one embodiment, the common voltage supply line 13 and / or the counter electrode are connected to the common voltage line EL of the display area DA (see Figure 22), and the common voltage ELVSS may be applied to the common voltage line (EL).

[0055] The display drive unit 32 includes a controller, which generates control signals to be transmitted to the first gate drive circuit GDRV1, the second gate drive circuit GDRV2, the data drive circuit, and / or the power supply circuit.

[0056] The drive voltage supply line 11 is connected to the terminal section PAD and may extend in the x-direction below the display area DA. The common voltage supply line 13 is connected to the terminal section PAD and has a shape with one side of the roof open, and may partially surround the display area DA.

[0057] Parts or all of the first gate drive circuit GDRV1 and the second gate drive circuit GDRV2 may be formed directly in the peripheral area PA of the substrate 100 during the process of configuring the pixel circuit in the display area DA of the substrate 100. The display drive unit 32 may be formed in the form of an integrated circuit chip and placed on a display circuit board 30 which is electrically connected to a terminal PAD located on one side of the substrate 100. The display circuit board 30 may be an FPCB (flexible printed circuit board). In other embodiments, the display drive unit 32 may be placed directly on the substrate using a COG (Chip-On-Glass) or COP (Chip-On-Plastic) method.

[0058] In one embodiment, the transistors included in the pixel circuit of the display area DA and the transistors included in the outer circuit of the peripheral area PA, for example, the first gate drive circuit GDRV1 and the second gate drive circuit GDRV2, are N-type oxide thin-film transistors. The transistors included in the outer circuit of the peripheral area PA can be formed simultaneously and in the same process as the formation of the transistors included in the pixel circuit of the display area DA. In another embodiment, the transistors included in the pixel circuit of the display area DA are N-type oxide thin-film transistors, and the transistors included in the outer circuit of the peripheral area PA are P-type silicon thin-film transistors.

[0059] Oxide thin-film transistors have a semiconductor layer that contains an oxide. Oxide semiconductors are Zn oxide-based materials, including Zn oxide, In-Zn oxide, and Ga-In-Zn oxide. In some embodiments, the oxide semiconductor may be an IGZO (In-Ga-Zn-O) semiconductor containing metals such as indium (In) and gallium (Ga) in ZnO. In some embodiments, the oxide semiconductor may be an ITGZO (In-Sn-Ga-Zn-O) semiconductor. In one embodiment, the oxide thin-film transistor may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor. Silicon thin-film transistors are low-temperature poly-silicon (LTPS) thin-film transistors, in which the semiconductor layer contains amorphous silicon, polysilicon, etc.

[0060] Figure 3 is a schematic diagram showing the arrangement of light-emitting regions of multiple pixels according to one embodiment.

[0061] Referring to Figure 3, the pixels PX arranged in the display area DA may include a first pixel PX1 that emits light in a first color, a second pixel PX2 that emits light in a second color, and a third pixel PX3 that emits light in a third color. For example, the first pixel PX1 is a red pixel, the second pixel PX2 is a green pixel, and the third pixel PX3 is a blue pixel. The first pixels PX1, the second pixels PX2, and the third pixels PX3 may be repeatedly arranged in a predetermined pattern in the x and y directions. Each of the first pixels PX1, the second pixels PX2, and the third pixels PX3 includes a pixel circuit and an organic light-emitting diode (OLED) as a display element electrically connected to the pixel circuit.

[0062] The display area DA defined on the substrate 100 includes a plurality of circuit areas, which include pixel rows and pixel columns that intersect (or intersect) each other. In each pixel area, one pixel row and one pixel column intersect each other, and a pixel circuit may be arranged. In one embodiment, a unit circuit area can be defined which includes two or more adjacent circuit areas in the x direction. For example, the unit circuit area PCAu includes three adjacent first circuit areas PCA1, second circuit area PCA2, and third circuit area PCA3 in the x direction. The first circuit area PCA1 may be the area where the pixel circuit of the first pixel PX1 is arranged. The second circuit area PCA2 may be the area where the pixel circuit of the second pixel PX2 is arranged. The third circuit area PCA3 may be the area where the pixel circuit of the third pixel PX3 is arranged.

[0063] Pixel circuits PC, located in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3, can each be electrically connected to display elements that emit light of different colors. The pixel circuits located in the first circuit region PCA1, the second circuit region PCA2, and the third circuit region PCA3 each drive the display elements to which they are electrically connected. For example, a display element electrically connected to a pixel circuit located in the first circuit region PCA1 emits red light. A display element electrically connected to a pixel circuit located in the second circuit region PCA2 emits green light. A display element electrically connected to a pixel circuit located in the third circuit region PCA3 emits blue light.

[0064] Figure 3 shows the pixel electrodes PE and light-emitting regions EA of the first pixel PX1, second pixel PX2, and third pixel PX3, respectively. The light-emitting region EA is the region where the light-emitting layer EL of the organic light-emitting diode (OLED) is located. The light-emitting region EA can be defined by the aperture of the pixel definition layer. Since the light-emitting layer EL is located on the pixel electrode PE, the arrangement of light-emitting regions shown in Figure 3 can be understood as an arrangement of pixel electrodes or an arrangement of pixels.

[0065] The luminescent region EA can have shapes such as rectangles, octagons, and other polygons, as well as circles and ellipses, and polygons also include shapes with rounded corners (vertices).

[0066] The light-emitting regions EA of the first pixel PX1 and the second pixel PX2 are arranged adjacent to each other in the y-direction, and the light-emitting region EA of the third pixel PX3 may be arranged adjacent to the light-emitting regions EA of the first pixel PX1 and the second pixel PX2 in the x-direction. As a result, the light-emitting regions EA of the first pixel PX1 and the second pixel PX2 are arranged alternately in the y-direction along a virtual straight line ISL1, and the light-emitting region EA of the third pixel PX3 may be repeatedly arranged in the y-direction along a virtual straight line ISL2.

[0067] The x-direction length and y-direction length of the light-emitting region EA of the first pixel PX1, the second pixel PX2, and the third pixel PX3 are the same or different. For example, the light-emitting region EA of the first pixel PX1 is square-shaped, while the light-emitting region EAs of the second pixel PX2 and the third pixel PX3 are rectangular with their longer sides in the y-direction. The y-direction length of the light-emitting region EA of the third pixel PX3 may be the same as, or greater than, the sum of the y-direction lengths of the light-emitting region EA of the first pixel PX1 and the second pixel PX2.

[0068] The first light-emitting region EA of the first pixel PX1, the second light-emitting region EA of the second pixel PX2, and the third light-emitting region EA of the third pixel PX3 have different areas (sizes). In one embodiment, the light-emitting region EA of the third pixel PX3 has a larger area than the light-emitting region EA of the first pixel PX1. The light-emitting region EA of the third pixel PX3 has a larger area than the light-emitting region EA of the second pixel PX2. The light-emitting region EA of the second pixel PX2 has a larger area than the light-emitting region EA of the first pixel PX1.

[0069] Auxiliary electrodes AE may be further positioned between the light-emitting regions EA. The auxiliary electrodes AE are positioned between the light-emitting regions EA of the third pixel PX3. The auxiliary electrodes AE can contact the opposing electrodes and / or common voltage lines in the display region DA.

[0070] Figure 4 is a schematic diagram of the equivalent circuit of a pixel according to one embodiment.

[0071] Referring to Figure 4, a pixel PXa may include a pixel circuit PCa and an organic light-emitting diode (OLED) as a display element connected to the pixel circuit PCa.

[0072] Pixel PXa is connected to the first gate line GWL which transmits the first gate signal GW, the second gate line GIL which transmits the second gate signal GI, the third gate line GRL which transmits the third gate signal GR, the fourth gate line EML which transmits the fourth gate signal EM, the fifth gate line EMBL which transmits the fifth gate signal EMB, and the data line DL which transmits the data signal. Since the illumination of pixel PX is controlled by the fourth gate signal EM and the fifth gate signal EMB, the fourth gate signal EM and the fifth gate signal EMB may also be called illumination control signals, and the fourth gate line EML and the fifth gate line EMBL may also be called illumination control lines. Pixel PX is connected to the drive voltage line PL which transmits the drive voltage ELVDD, the reference voltage line VRL which transmits the reference voltage Vref, and the initialization voltage line VL which transmits the initialization voltage Vint.

[0073] In one embodiment, the transistor included in the pixel circuit PCa may be an N-type oxide thin-film transistor. The oxide thin-film transistor is a low-temperature polycrystalline oxide (LTPO) thin-film transistor in which the semiconductor layer contains an oxide. However, this is illustrative and not limited to N-type transistors. For example, the semiconductor layer included in an N-type transistor may include an inorganic semiconductor (e.g., amorphous silicon, polysilicon) or an organic semiconductor.

[0074] The pixel circuit PCa includes first to sixth transistors T1 to T6 and first and second capacitors C1 and C2. The first transistor T1 is a drive transistor that outputs a drive current corresponding to the data signal DATA, and the second to sixth transistors T2 to T6 are switching transistors that transmit signals. The first terminal (first electrode) and second terminal (second electrode) of each of the first to sixth transistors T1 to T6 can be a source (or source electrode) or a drain (or drain electrode) depending on the voltage between the first and second terminals. For example, depending on the voltage between the first and second terminals, the first terminal may be the drain and the second terminal may be the source, or the first terminal may be the source and the second terminal may be the drain. Hereinafter, the node connected to the first gate of the first transistor T1 is defined as the first node N1, and the node connected to the second terminal of the first transistor T1 is defined as the second node N2.

[0075] The first transistor T1 is connected to the drive voltage line PL and the organic light-emitting diode OLED. The first transistor T1 is connected between the fifth transistor T5 and the sixth transistor T6. The first transistor T1 includes a gate, a first terminal, and a second terminal connected to the second node N2. The first transistor T1 includes a first gate connected to the first node N1. The first transistor T1 may further include a second gate connected to its own second terminal. The first and second gates may be located opposite each other in different layers. For example, the first and second gates of the first transistor T1 are located opposite each other with a narrow semiconductor layer. Hereinafter, the gate (or gate electrode) of the first transistor T1 means the first gate involved in the turn-on and turn-off of the first transistor T1.

[0076] The first gate of the first transistor T1 is connected to the second terminal of the second transistor T2, the first terminal of the third transistor T3, and the first capacitor C1. The second gate of the first transistor T1 is connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first terminal of the first transistor T1 is connected to the drive voltage line PL via the fifth transistor T5, and the second terminal is connected to the pixel electrode of the organic light-emitting diode (OLED) via the sixth transistor T6. The first terminal of the first transistor T1 is connected to the second terminal of the fifth transistor T5. The second terminal of the first transistor T1 is connected to the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The first transistor T1 receives a data signal DATA through the switching operation of the second transistor T2, and can control the amount of drive current flowing to the organic light-emitting diode (OLED).

[0077] The second transistor T2 (writing transistor) is connected to the data line DL and the first gate of the first transistor T1. The second transistor T2 includes a gate connected to the first gate line GWL, a first terminal connected to the data line DL, and a second terminal connected to the first node N1. The second terminal of the second transistor T2 is connected to the first gate of the first transistor T1, the first terminal of the third transistor T3, and the first capacitor C1. The second transistor T2 is turned on by the first gate signal GW transmitted to the first gate line GWL, electrically connecting the data line DL and the first node N1, and can transmit the data signal DATA transmitted to the data line DL to the first node N1.

[0078] The third transistor T3 (first initialization transistor) is connected to the first gate of the first transistor T1 and to the reference voltage line VRL. The third transistor T3 includes a gate connected to the third gate line GRL, a first terminal connected to the first node N1, and a second terminal connected to the reference voltage line VRL. The first terminal of the third transistor T3 is connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first capacitor C1. The third transistor T3 is turned on by the third gate signal GR transmitted to the third gate line GRL, and can transmit the reference voltage Vref transmitted to the reference voltage line VRL to the first node N1.

[0079] The fourth transistor T4 (second initialization transistor) is connected to the sixth transistor T6 and the initialization voltage line VL. The fourth transistor T4 may be connected between the organic light-emitting diode OLED and the initialization voltage line VL. The fourth transistor T4 includes a gate connected to the second gate line GIL, a first terminal connected to the third node N3, and a second terminal connected to the initialization voltage line VL. The first terminal of the fourth transistor T4 is connected to the second terminal of the sixth transistor T6 and the pixel electrode of the organic light-emitting diode OLED. The fourth transistor T4 can be turned on by the second gate signal GI transmitted to the second gate line GIL and transmit the initialization voltage Vint transmitted to the initialization voltage line VL to the third node N3.

[0080] The fifth transistor T5 (first light-emitting control transistor) is connected to the drive voltage line PL and the first transistor T1. The fifth transistor T5 includes a gate connected to the fourth gate line EML, a first terminal connected to the drive voltage line PL, and a second terminal connected to the first terminal of the first transistor T1. The fifth transistor T5 can be turned on or turned off by the fourth gate signal EM transmitted to the fourth gate line EML.

[0081] The sixth transistor T6 (second light-emitting control transistor) is connected to the first transistor T1 and the organic light-emitting diode OLED. The sixth transistor T6 may be connected between the second node N2 and the third node N3. The sixth transistor T6 includes a gate connected to the fifth gate line EMBL, a first terminal connected to the second node N2, and a second terminal connected to the third node N3. The first terminal of the sixth transistor T6 is connected to the second terminal of the first transistor T1, the first capacitor C1, and the second capacitor C2. The second terminal of the sixth transistor T6 is connected to the first terminal of the fourth transistor T4 and the pixel electrode of the organic light-emitting diode OLED. The sixth transistor T6 may be turned on or turned off by the fifth gate signal EMB transmitted to the fifth gate line EMBL.

[0082] The first capacitor C1 is connected between the first gate and the second terminal of the first transistor T1. The first electrode of the first capacitor C1 is connected to the first node N1, and the second electrode is connected to the second node N2. The first electrode of the first capacitor C1 may be connected to the first gate of the first transistor T1, the second terminal of the second transistor T2, and the first terminal of the third transistor T3. The second electrode of the first capacitor C1 may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the second capacitor C2, and the first terminal of the sixth transistor T6. The first capacitor C1 is a storage capacitor and stores the threshold voltage and the voltage corresponding to the data signal DATA of the first transistor T1.

[0083] If both the third transistor T3 and the fifth transistor T5 are turned on, the first transistor T1 may be turned on. If the voltage at the second terminal of the first transistor T1 drops by the difference between the reference voltage Vref and the threshold voltage Vth of the first transistor T1 (Vref-Vth), the first transistor T1 is turned off, and the first capacitor C1 stores a voltage corresponding to the threshold voltage Vth of the first transistor T1, thereby compensating for the threshold voltage Vth of the first transistor T1.

[0084] The second capacitor C2 is connected between the drive voltage line PL and the second node N2. The first electrode of the second capacitor C2 may be connected to the drive voltage line PL. The second electrode of the second capacitor C2 may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, and the first terminal of the sixth transistor T6.

[0085] The capacitances of the first capacitor C1 and the second capacitor C2 may vary depending on the color of the light emitted by the pixel PX.

[0086] The organic light-emitting diode (OLED) may be connected to the first transistor T1 via a sixth transistor T6. The OLED includes a pixel electrode (anode) connected to a third node N3 and a counter electrode (cathode) facing the pixel electrode, the counter electrode being supplied with a common voltage ELVSS. The counter electrode may be a common electrode common to pixels PX. The drive current output by the first transistor T1 flows through the OLED via the turned-on fifth transistor T5 and the turned-on sixth transistor T6, causing the OLED to emit light with a brightness corresponding to the size of the drive current.

[0087] Figure 5 is a schematic arrangement diagram showing the positions of transistors and capacitors in a pixel according to one embodiment. Figures 6 to 16 are schematic arrangement diagrams showing the pixel components layer by layer. Figure 15 is a schematic diagram showing the arrangement of vertical conductive wires according to one embodiment. Figure 17 is a schematic cross-sectional view taken along Ia-Ia' and IIa-IIa' in Figures 5 and 16. Figure 18 is a schematic cross-sectional view taken along Ib-Ib' and IIb-IIb' in Figures 5 and 16. Figure 19 is a schematic cross-sectional view taken along Ic-Ic' and IIc-IIc' in Figures 5 and 16.

[0088] In Figure 5, the pixel circuits located in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a correspond to the pixel circuits PCa of the pixels shown in Figure 4, respectively.

[0089] In one embodiment, different initialization voltages Vint are supplied to the first pixel PX1, the second pixel PX2, and the third pixel PX3, taking into consideration the light emission characteristics of the first pixel PX1, the second pixel PX2, and the third pixel PX3. For example, the pixel circuit PCa of the first pixel PX1 is connected to the 1-1 initialization voltage line VL11, and the pixel circuits PCa of the second pixel PX2 and the third pixel PX3 are connected to the 1-2 initialization voltage line VL12. The initialization voltage supplied to the 1-1 initialization voltage line VL11 and the initialization voltage supplied to the 1-2 initialization voltage line VL12 may be different.

[0090] The same elements may be arranged in each layer of the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a. For the convenience of illustration and explanation, the elements of the pixel circuit PCa arranged in the first circuit region PCA1a will be assigned identification numbers, and the explanation will focus on the first circuit region PCA1a. Explanations regarding the same components can be similarly applied to the components of the second circuit region PCA2a and the third circuit region PCA3a. The explanation below will be given with reference to Figures 6 to 19. Hereinafter, a connecting electrode is an electrode that transmits a signal by electrically connecting a conductive wire and an electrode (conductive pattern) arranged in different layers.

[0091] A first conductive layer is placed on the substrate 100. As shown in Figure 6, the first conductive layer includes a conductive wire 200, a first electrode 210, and a repair wire RL. In one embodiment, a barrier layer may be further placed between the substrate 100 and the first conductive layer.

[0092] The first electrode 210 is provided as an island type. The first electrode 210 is positioned adjacent to the conductive wire 200 in the first circuit region PCA1a and the second circuit region PCA2a, but may not be positioned in the third circuit region PCA3a. In one embodiment, the area of ​​the first electrode 210 in the first circuit region PCA1a is larger than the area of ​​the first electrode 210 in the second circuit region PCA2a.

[0093] The conductive wire 200 extends in the x-direction and may be arranged across the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a. The conductive wire 200 is a drive voltage line PL to which the drive voltage ELVDD is applied. Hereinafter, the conductive wire 200 and the drive voltage line PL may be used interchangeably. The conductive wire 200 includes a main line 200m extending in the x-direction in each circuit region and a projection 200p1 projecting from the main line 200m in the -y direction. The conductive wire 200 may further include projections 200p2 and 200p3 projecting in the +y direction in the first circuit region PCA1a and the second circuit region PCA2a.

[0094] The area of ​​the conductive wire 200 differs for each circuit region. The area of ​​the conductive wire 200 can be adjusted by the width of the main wire 200m in the y-direction, the width (length) of the protruding portion in the x-direction and y-direction, etc. In one embodiment, the area of ​​the conductive wire 200 in the third circuit region PCA3a is larger than the area of ​​the conductive wire 200 in the first circuit region PCA1a and the second circuit region PCA2a. The area of ​​the conductive wire 200 in the second circuit region PCA2a is larger than the area of ​​the conductive wire 200 in the first circuit region PCA1a. The width w13 in the y-direction of the main wire 200m in the third circuit region PCA3a is larger than the width w12 in the y-direction of the main wire 200m in the second circuit region PCA2a, and the width w12 in the y-direction of the main wire 200m in the second circuit region PCA2a is larger than the width w11 in the y-direction of the main wire 200m in the first circuit region PCA1a. The width w13 in the y-direction of the main line 200m in the third circuit region PCA3a can be at least equal to or greater than the length in the y-direction of the channel region of the first transistor T1.

[0095] In the first circuit region PCA1a and the second circuit region PCA2a, the protrusion 200p2 is superimposed on the data line DL. In the first circuit region PCA1a and the second circuit region PCA2a, the protrusion 200p3 is superimposed on the channel region of the first transistor T1. The width w14 in the y direction between the main line 200m and the protrusion 200p3 in the first circuit region PCA1a and the width w15 in the y direction between the main line 200m and the protrusion 200p3 in the second circuit region PCA2a are the same and can be at least equal to or greater than the length in the y direction of the channel region of the first transistor T1.

[0096] The repair line RL extends in the x-direction and may be positioned across the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a.

[0097] A first insulating layer 111 is disposed on the substrate 100, covering or superimposing the first conductive layer, and a second conductive layer may be disposed on the first insulating layer 111. As shown in Figure 7, the second conductive layer includes a second electrode 220, a lower first gate line GWLb, a reference voltage line VRL, and first-to-second initialization voltage lines VL12.

[0098] The second electrode 220 is provided as an island type. The second electrode 220 is superimposed on the first electrode 210 and the conductive wire 200. The second electrode 220 is the second gate electrode G12 and source electrode of the first transistor T1. In the first circuit region PCA1a and the second circuit region PCA2a, an aperture SOP superimposed on the first electrode 210 may be defined for the second electrode 220. The area of ​​the second electrode 220 differs for each circuit region. For example, the area of ​​the second electrode 220 in the second circuit region PCA2a and the third circuit region PCA3a is larger than the area of ​​the second electrode 220 in the first circuit region PCA1a. In the second circuit region PCA2a, the area of ​​the second electrode 220 superimposed on the conductive wire 200 is larger than the area of ​​the second electrode 220 superimposed on the conductive wire 200 in the first circuit region PCA1a. In the third circuit region PCA3a, the area over which the second electrode 220 overlaps the conductive wire 200 is larger than the area over which the second electrode 220 overlaps the conductive wire 200 in the first circuit region PCA1a and the second circuit region PCA2a.

[0099] The lower first gate line GWLb, reference voltage line VRL, and first-to-second initialization voltage line VL12 extend in the x direction and may be positioned across the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a.

[0100] A second insulating layer 112 is arranged on top of a first insulating layer 111, covering a second conductive layer. On top of the second insulating layer 112, a semiconductor layer ACT containing an oxide semiconductor is arranged, as shown in Figure 8. The semiconductor layer ACT includes a first semiconductor layer ACT1, a second semiconductor layer ACT2, and a third semiconductor layer ACT3. The semiconductor layer ACT includes the source region, drain region, and channel region between the source region and drain region of the first to sixth transistors T1 to T6, respectively. Depending on the embodiment, the source region and drain region may also be interpreted as the source electrode and drain electrode of the transistor.

[0101] Figure 10 shows the transistors in the first circuit region PCA1a. Referring to Figure 10, the first semiconductor layer ACT1 includes the source region S1 and drain region D1 of the first transistor T1, and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 includes the source region S2 and drain region D2 of the second transistor T2, and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 includes the source region S4 and drain region D4 of the fourth transistor T4, and the source region S6 and drain region D6 of the sixth transistor T6.

[0102] A third insulating layer 113 may be placed on the second insulating layer 112, covering a semiconductor layer ACT, and a third conductive layer may be placed on the third insulating layer 113. As shown in Figure 9, the third conductive layer includes a third electrode 230, a fourth electrode 240, a connecting electrode 250, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and / or a first-first initialization voltage line VL11.

[0103] The third electrode 230, the fourth electrode 240, and the connecting electrode 250 are provided as island-type electrodes. The third electrode 230, the fourth electrode 240, and the connecting electrode 250 can be arranged in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a, respectively.

[0104] The area of ​​the third electrode 230 differs for each circuit region. For example, the area of ​​the third electrode 230 in the second circuit region PCA2a and the third circuit region PCA3a is larger than the area of ​​the third electrode 230 in the first circuit region PCA1a. The area in which the third electrode 230 overlaps the second electrode 220 in the second circuit region PCA2a and the third circuit region PCA3a is larger than the area in which the third electrode 230 overlaps the second electrode 220 in the first circuit region PCA1a.

[0105] In the first circuit region PCA1a and the second circuit region PCA2a, the third electrode 230 can be electrically connected to the first electrode 210 via a contact hole 31a that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The contact hole 31a is insulated from the opening SOP of the second electrode 220 and is located within the opening SOP.

[0106] In the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a, the connecting electrode 250 can be electrically connected to the protruding portion 200p1 of the conductive wire 200 via a contact hole 33a that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0107] The upper first gate line GWLt, second gate line GIL, third gate line GRL, fourth gate line EML, fifth gate line EMBL, and 1-1 initialization voltage line VL11 extend in the x direction and may be arranged across the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a.

[0108] The upper first gate wire GWLt is superimposed on the lower first gate wire GWLtb and can be electrically connected to the lower first gate wire GWLtb via contact holes 32a that penetrate the second insulating layer 112 and the third insulating layer 113.

[0109] As shown in Figure 10, the third conductive layer includes gate electrodes G1 to G6 of the first to sixth transistors T1 to T6. Gate electrodes G1 to G6 are superimposed on the channel region of the semiconductor layer ACT.

[0110] Referring to Figure 10, the third electrode 230 includes the first gate electrode G11 of the first transistor T1. The first gate electrode G11 is superimposed on the first semiconductor layer ACT1. The fourth electrode 240 is the gate electrode G2 of the second transistor T2. The fourth electrode 240 is superimposed on the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 is the portion of the third gate line GRL that is superimposed on the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 is the portion of the second gate line GIL that is superimposed on the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 is the portion of the fourth gate line EML that is superimposed on the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 is the portion of the fifth gate line EMBL that is superimposed on the third semiconductor layer ACT3.

[0111] A fourth insulating layer 114 is placed on the third insulating layer 113, covering the third conductive layer, and a fourth conductive layer is placed on the fourth insulating layer 114. As shown in Figure 11A, the fourth conductive layer includes data lines DL and connecting electrodes 270, 271, 272, 273, 274, 275, 276, and 277.

[0112] The data lines DL are arranged extending in the y-direction for each circuit region. The data lines DL are electrically connected to the drain region D2 of the second transistor T2 via contact holes 43a that penetrate the third insulating layer 113 and the fourth insulating layer 114.

[0113] The connecting electrode 270 includes a first region 270a superimposed on the first electrode 210, the second electrode 220, and the third electrode 230, and a second region 270b protruding from the first region 270a in the -y direction. The connecting electrode 270 electrically connects the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the sixth transistor T6.

[0114] The first region 270a of the connecting electrode 270 can be electrically connected to the source region S1 of the first transistor T1 via a contact hole 42a that penetrates the third insulating layer 113 and the fourth insulating layer 114. The first region 270a of the connecting electrode 270 can be electrically connected to the second electrode 220 via a contact hole 41a that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. Thus, the connecting electrode 270 can be a source electrode electrically connected to the source region S1 of the first transistor T1. The second electrode 220 corresponds to the second gate electrode G12 of the first transistor T1, and the second gate electrode G12 of the first transistor T1 faces the first gate electrode G11 of the first transistor T1 and superimposes on the channel region of the first transistor T1. By connecting the connecting electrode 270 to the second electrode 220, the second gate electrode G12 of the first transistor T1 can be electrically connected to the source region S1 of the first transistor T1.

[0115] The second region 270b of the connecting electrode 270 can be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 50a that penetrates the third insulating layer 113 and the fourth insulating layer 114.

[0116] The connecting electrode 271 can be electrically connected to the gate electrode G2 of the second transistor T2 via a contact hole 45a that penetrates the fourth insulating layer 114. The connecting electrode 271 can also be electrically connected to the upper first gate wire GWLt via a contact hole 44a that penetrates the fourth insulating layer 114.

[0117] The connecting electrode 272 is electrically connected to the source region S3 of the third transistor T3 via a contact hole 46a that penetrates the third insulating layer 113 and the fourth insulating layer 114, and can be electrically connected to the reference voltage line VRL via a contact hole 47a that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0118] The connecting electrode 273 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 48a that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 273 can be electrically connected to the third electrode 230 via a contact hole 49a that penetrates the fourth insulating layer 114, and thereby electrically connected to the first gate electrode G11 of the first transistor T1. The connecting electrode 273 is a node electrode corresponding to the first node N1 in Figure 4. The connecting electrode 273 is a bridge electrode that electrically connects at least two transistors. For example, the connecting electrode 273 is a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0119] The connecting electrode 274 can be electrically connected to the protruding portion 200p1 of the conductive wire 200 via a contact hole 51a that penetrates the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connecting electrode 274 can also be electrically connected to the drain region D5 of the fifth transistor T5 via a contact hole 52a that penetrates the third insulating layer 113 and the fourth insulating layer 114. This allows the drain region D5 of the fifth transistor T5 to be electrically connected to the conductive wire 200.

[0120] The connecting electrode 275 can be electrically connected to the source region S6 of the sixth transistor T6 and the drain region D4 of the fourth transistor T4 via a contact hole 53a that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 275 superimposes a portion of the repair line RL. The connecting electrode 275 is insulated from the repair line RL and can be electrically connected to the repair line RL if a defect occurs in a pixel circuit located in the circuit region later.

[0121] In the first circuit region PCA1a, the connecting electrode 276 can be electrically connected to the source region S4 of the fourth transistor T4 via a contact hole 54a that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 276 can also be connected to the first-1 initialization voltage line VL11 via a contact hole 55a that penetrates the fourth insulating layer 114.

[0122] In the second circuit region PCA2a and the third circuit region PCA3a, the connecting electrode 276 can be electrically connected to the source region S4 of the fourth transistor T4 via a contact hole 54a that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 276 can also be electrically connected to the first-to-second initialization voltage line VL12 via a contact hole 56a that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0123] In a portion of the first circuit region PCA1a, the connecting electrode 276 may further have a protrusion 276p, as shown in Figure 11B. For example, the protrusion 276p of the connecting electrode 276 is formed only in the first circuit region PCA1a where the first vertical initialization voltage line VLl1v (see Figure 12), which will be described later, is located.

[0124] In the first circuit region PCA1a, the connecting electrode 277 can be electrically connected to the first-to-second initialization voltage line VL12 via a contact hole 31a that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connecting electrode 277 can be placed only in a part of the first circuit region PCA1a. For example, the connecting electrode 277 can be placed only in the first circuit region PCA1a where the second vertical initialization voltage line VL12v (see Figure 13), one of the vertical conductive lines described later, is located.

[0125] A fifth insulating layer 115 is positioned on top of the fourth insulating layer 114, covering or superimposing the fourth conductive layer, and a fifth conductive layer is positioned on top of the fifth insulating layer 115. As shown in Figures 12 to 15, the fifth conductive layer includes vertical conductive wires VCL and connecting electrodes 281 and 283. For ease of illustration and explanation, only a portion of the lower conductive layers connected to the fifth conductive layer is shown in Figures 12 to 14.

[0126] The connecting electrode 281 can be electrically connected to the connecting electrode 275 via a contact hole 61a that penetrates the fifth insulating layer 115, and thereby electrically connected to the source region S6 of the sixth transistor T6.

[0127] The connecting electrode 283 can be electrically connected to the connecting electrode 270 via a contact hole 62a that penetrates the fifth insulating layer 115. The connecting electrode 283 can cover the connecting electrode 273, which is the node electrode, and be positioned superimposed on the connecting electrode 273. The second electrode 220 is positioned below the connecting electrode 273, and the connecting electrode 283 is positioned above the connecting electrode 273. The connecting electrode 283 covers the connecting electrode 273 substantially, and the second electrode 220 covers the connecting electrode 273 substantially. The connecting electrode 283 functions as an upper shielding layer for the connecting electrode 273, and the second electrode 220 functions as a lower shielding layer for the connecting electrode 273.

[0128] The vertical conductive lines VCL include the vertical drive voltage line PLv, the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the vertical common voltage line ELv, and / or the vertical reference voltage line VRLv. Each vertical conductive line VCL extends in the y direction and may be arranged in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a, spaced apart from each other in the x direction.

[0129] Four vertical conductive lines may be arranged spaced apart in the x-direction within the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a. For example, four vertical conductive lines VCL from among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv may be arranged spaced apart in the x-direction. The vertical conductive lines VCL may be electrically connected to horizontal conductive lines extending in the x-direction. The horizontal conductive line VCL includes conductive line 200 which is the drive voltage line PL, the first-first initialization voltage line VL11, the first-second initialization voltage line VL12, and the reference voltage line VRL.

[0130] Figure 12 shows an example in which the first vertical initialization voltage line VL11v, a pair of vertical drive voltage lines PLv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a.

[0131] Figure 13 shows an example in which the second vertical initialization voltage line VLl2v, a pair of vertical drive voltage lines PLv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a.

[0132] Figure 14 shows an example in which the second vertical initialization voltage line VLl2v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a.

[0133] A pair of adjacent vertical drive voltage lines PLv may be connected by a coupling section BR. A pair of vertical drive voltage lines PLv may be formed integrally. In one embodiment, the coupling section BR is located every two rows. For example, a pair of vertical drive voltage lines PLv may be connected by a coupling section BR in odd-numbered or even-numbered rows, as shown in Figure 13, and separated from each other without a coupling section BR in even-numbered or odd-numbered rows.

[0134] In one embodiment, as shown in Figure 15, the first vertical conduction line VCL of the unit circuit region PCAu is the first vertical initialization voltage line VL11v or the second vertical initialization voltage line VL12v. The fourth vertical conduction line VCL of the unit circuit region PCAu is the vertical reference voltage line VRLv. The second and third vertical conduction lines VCL of the unit circuit region PCAu are a pair of vertical drive voltage lines PLv or a pair of vertical drive voltage lines PLv and a vertical common voltage line ELv.

[0135] As shown in Figure 12, the first vertical initialization voltage line VL11v can be electrically connected to a connecting electrode 276 located in the first circuit region PCA1a via a contact hole 63a that penetrates the fifth insulating layer 115. The connecting electrode 276 is electrically connected to the first-first initialization voltage line VL11, which has a mesh structure in the display region DA.

[0136] As shown in Figure 13, the second vertical initialization voltage line VL12v can be electrically connected to a connecting electrode 277 located in the first circuit region PCA1a via a contact hole 66a that penetrates the fifth insulating layer 115. The connecting electrode 277 is electrically connected to the first-to-second initialization voltage line VL12, which has a mesh structure in the display region DA.

[0137] As shown in Figures 12 to 14, the vertical drive voltage line PLv can be electrically connected to a connecting electrode 274 located in the second circuit region PCA2a via a contact hole 64a that penetrates the fifth insulating layer 115. The connecting electrode 274 is electrically connected to the conductive wire 200, and the drive voltage line PL has a mesh structure in the display region DA.

[0138] As shown in Figure 14, the vertical common voltage line ELv can be electrically connected to the common voltage supply line 13 (Figure 2) located in the surrounding region PA.

[0139] As shown in Figures 12 to 14, the vertical reference voltage line VRLv can be electrically connected to a connecting electrode 272 located in the third circuit region PCA3a via a contact hole 64a that penetrates the fifth insulating layer 115. The connecting electrode 272 is electrically connected to the reference voltage line VRL, which has a mesh structure in the display region DA.

[0140] Although not shown in the diagram, the peripheral region PA may also contain additional voltage supply lines electrically connected to the horizontal and / or vertical conductive lines. The voltage supply lines may be located on at least one of the following sides of the peripheral region PA: above, below, left, and right.

[0141] The corresponding connecting electrodes with the same function in the first circuit region PCA1a, the second circuit region PCA2a, and the third circuit region PCA3a may differ in shape and position depending on the position of the wiring placed in the circuit region.

[0142] A sixth insulating layer 116 is placed on top of the fifth insulating layer 115, covering the fifth conductive layer, and an organic light-emitting diode (OLED) is placed on top of the sixth insulating layer 116 as a display element. The organic light-emitting diode (OLED) includes a pixel electrode 511, a counter electrode 515, and an intermediate layer (or intervening layer) between the pixel electrode 511 and the counter electrode 515.

[0143] The pixel electrode 511 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 281, which is a lower conductive pattern, via the contact hole 71a of the sixth insulating layer 116. As shown in Figure 16, the pixel electrode 511 connected to the pixel circuit of the first pixel PX1 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 281 located in the first circuit region PCA1a. The pixel electrode 511 connected to the pixel circuit of the second pixel PX2 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 281 located in the second circuit region PCA2a. The pixel electrode 511 connected to the pixel circuit of the third pixel PX3 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 281 located in the third circuit region PCA3.

[0144] As shown in Figure 3, an auxiliary electrode AE ​​may be further arranged on the same layer as the pixel electrode 511. The auxiliary electrode AE ​​is positioned between the pixel electrodes 511 of the third pixel PX3. The auxiliary electrode AE ​​makes contact with the opposing electrode 515 in the display area DA. In one embodiment, the auxiliary electrode AE ​​is electrically connected to the vertical common voltage line ELv in the display area DA.

[0145] As shown in Figures 17 to 19, a seventh insulating layer 117, which is a pixel-defining layer covering the edges of the pixel electrode 511, may be placed on top of the pixel electrode 511. The seventh insulating layer 117 may have an aperture 117OP that exposes a portion of the pixel electrode 511 and defines a light-emitting region. The seventh insulating layer 117 is a single-layer or multi-layer organic insulating layer and / or inorganic insulating layer.

[0146] The intermediate layer includes an emissive layer 513 and a first functional layer below the emissive layer 513 and / or a second functional layer above the emissive layer 513. The first functional layer is a hole transport layer (HTL). As another example, the first functional layer includes a hole injection layer (HIL) and a hole transport layer (HTL). The second functional layer includes an electron transport layer (ETL) and / or an electron injection layer (EIL). The first and second functional layers may be formed integrally to correspond to an organic light-emitting diode (OLED) contained in a display area DA. The first or second functional layer may be omitted. Figure 16 shows the light-emitting layer 513a of the organic light-emitting diode OLED1, which is electrically connected to the pixel circuit located in the first circuit region PCA1a; the light-emitting layer 513b of the organic light-emitting diode OLED2, which is electrically connected to the pixel circuit located in the second circuit region PCA2a; and the light-emitting layer 513c of the organic light-emitting diode OLED3, which is electrically connected to the pixel circuit located in the third circuit region PCA3a.

[0147] The counter electrode 515 can be integrally formed to correspond to the organic light-emitting diode OLED located in the display area DA.

[0148] Referring to Figures 17 to 19, the conductive wire 200 corresponds to the entire channel region CH1 of the first transistor T1 in each circuit region, and the entire channel region CH1 of the first transistor T1 is superimposed on the conductive wire 200.

[0149] Figures 20 and 21 are schematic diagrams showing the arrangement relationship between the conductive layer and the semiconductor layer in a comparative example. In the comparative example shown in Figures 20 and 21, the conductive wire 200' corresponds to a part of the channel region CH1 of the first transistor T1, and a part of the channel region CH1 of the first transistor T1 superimposes on the conductive wire 200'. Due to the step formed between the region where the conductive wire 200' is placed and the region where the conductive wire 200' is not placed, the channel region CH1 of the first transistor T1, which is contained in the first semiconductor layer ACT1, may be completely or partially disconnected in region X. Since the output current amount of the first transistor T1 changes depending on the degree of disconnection of the channel region CH1 of the first transistor T1, deterioration of short-range uniformity (SRU) occurs, and sand-grain-like spots or dark spots may appear.

[0150] In an embodiment of the present invention, by arranging the conductive wire 200 to correspond at least to the channel region CH1 of the first transistor T1, the disconnection of the channel region CH1 of the first transistor T1 can be minimized (prevented).

[0151] Embodiments of the present invention allow for the optimization of the ratio of the first capacitor C1 to the second capacitor C2 for each pixel by adjusting the degree of overlap between the conductive wire 200 and the second electrode 220, the isolation distance between the conductive wire 200 and the first electrode 210, and the size and / or width in the y-direction of the conductive wire 200 and / or the first electrode 210.

[0152] Referring again to Figures 17 and 18, the first capacitor C1 of the first pixel PX1 and the second pixel PX2 includes a first electrode C11 and a second electrode C12. The first electrode C11 includes a lower first electrode C11b formed by a first electrode 210, an intermediate first electrode (or intervening first electrode) C11m formed by a third electrode 230, and an upper first electrode C11t formed by a connecting electrode 273. The lower first electrode C11b and the intermediate first electrode C11m are electrically connected via a contact hole 31a, and the intermediate first electrode C11m and the upper first electrode C11t are electrically connected via a contact hole 49a. The second electrode C12 includes a lower second electrode C12b formed by a second electrode 220, an intermediate second electrode (or intervening second electrode) C12m formed by a connecting electrode 270, and an upper second electrode C12t formed by a connecting electrode 283. The lower second electrode C12b and the intermediate second electrode C12m are electrically connected via a contact hole 41a, and the intermediate second electrode C12m and the upper second electrode C12t are electrically connected via a contact hole 62a.

[0153] The capacitance of the first capacitor C1 is the sum of the capacitance formed by the lower first electrode C11b and the lower second electrode C12b, the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 has a parallel connection structure of subcapacitors formed by conductive wires superimposed in the z direction, thereby allowing the capacitance to be increased (secured) in the x and y directions without increasing the area.

[0154] The width wc1 in the y-direction of the lower first electrode C11b of the first capacitor C1 of the first pixel PX1 is greater than the width wc1 in the y-direction of the lower first electrode C11b of the first capacitor C1 of the second pixel PX2. The area where the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the second pixel PX2 overlap is greater than the area where the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the first pixel PX1 overlap. The sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the second pixel PX2 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap, is greater than the sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the first pixel PX1 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap.

[0155] The second capacitor C2 of the first pixel PX1 and the second pixel PX2 includes a first electrode C21 formed by the conductive wire 200 and a second electrode C22 formed by the second electrode 220. In the second circuit region PCA2a, the area over which the second electrode 220 overlaps the conductive wire 200 is greater than the area over which the second electrode 220 overlaps the conductive wire 200 in the first circuit region PCA1a. Therefore, the capacitance of the second capacitor C2 of the second pixel PX2 is greater than the capacitance of the second capacitor C2 of the first pixel PX1.

[0156] Referring to Figure 19, the first capacitor C1 of the third pixel PX3 may be formed between the third electrode 230 and the connecting electrode 270, between the second electrode 220 and the third electrode 230, and between the connecting electrode 273 and the connecting electrode 283. The first capacitor C1 of the first pixel PX1 includes a first electrode C11 and a second electrode C12. The first electrode C11 includes an intermediate first electrode C11m formed by the third electrode 230 and an upper first electrode C11t formed by the connecting electrode 273. The intermediate first electrode C11m and the upper first electrode C11t may be electrically connected via a contact hole 49a. The second electrode C12 includes a lower second electrode C12b formed by the second electrode 220, an intermediate second electrode C12m formed by the connecting electrode 270, and an upper second electrode C12t formed by the connecting electrode 283. The lower second electrode C12b and the intermediate second electrode C12m are electrically connected via a contact hole 41a, and the intermediate second electrode C12m and the upper second electrode C12t are electrically connected via a contact hole 62a.

[0157] The capacitance of the first capacitor C1 is the sum of the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 has a parallel connection structure of subcapacitors formed by conductive wires superimposed in the z direction, thereby allowing the capacitance to be increased (secured) in the x and y directions without increasing the area.

[0158] The second capacitor C2 of the third pixel PX3 includes a first electrode C21 formed by the conductive wire 200 and a second electrode C22 formed by the second electrode 220. In the third circuit region PCA3a, the area over which the second electrode 220 overlaps the conductive wire 200 is larger than the area over which the second electrode 220 overlaps the conductive wire 200 in the first circuit region PCA1a and the second circuit region PCA2a. Therefore, the capacitance of the second capacitor C2 of the third pixel PX3 is greater than the capacitance of the second capacitor C2 of the first pixel PX1 and the second pixel PX2.

[0159] Figure 22 is a schematic diagram of an equivalent pixel circuit according to one embodiment.

[0160] Referring to Figure 22, the pixel circuit PCb of pixel PXb may further include a third capacitor C3 in addition to the pixel circuit PCa of pixel PXa shown in Figure 4. The other configuration and operation are substantially the same as that of pixel PXa shown in Figure 4.

[0161] The third capacitor C3 may be connected between the second node N2 and the common voltage line EL, which is supplied with the common voltage ELVSS. The first electrode of the third capacitor C3 may be connected to the common voltage line EL. The second electrode of the third capacitor C3 may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the second capacitor C2, the second electrode of the second capacitor C2, the first terminal of the fourth transistor T4, and the first terminal of the sixth transistor T6.

[0162] The capacitances of the first capacitor C1, the second capacitor C2, and the third capacitor C3 may differ depending on the color of the light emitted by the pixel PX.

[0163] Figure 23 is a schematic arrangement diagram showing the positions of transistors and capacitors in a pixel according to one embodiment. Figures 24 to 34 are schematic arrangement diagrams showing the pixel components layer by layer. Figure 33 is a schematic diagram showing the arrangement of vertical conductive wires according to one embodiment. Figure 35 is a schematic cross-sectional view taken along IVa-IVa' and Va-Va' in Figures 23 and 34. Figure 36 is a schematic cross-sectional view taken along IVb-IVb' and Vb-Vb' in Figures 23 and 34. Figure 37 is a schematic cross-sectional view taken along IVc-IVc' and Vc-Vc' in Figures 23 and 34.

[0164] In Figure 23, the pixel circuits located in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b correspond to the pixel circuits PCb of the pixels shown in Figure 22, respectively.

[0165] In one embodiment, the pixel circuit PCb of the first pixel PX1 is connected to the 1-1 initialization voltage line VL11, and the pixel circuit PCb of the second pixel PX2 and the pixel circuit PCb of the third pixel PX3 are connected to the 1-2 initialization voltage line VL12. The initialization voltage supplied to the 1-1 initialization voltage line VL11 and the initialization voltage supplied to the 1-2 initialization voltage line VL12 may be different.

[0166] For the sake of illustration and explanation, identification numbers will be assigned to the elements of the pixel circuit PCb located in the first circuit region PCA1b, and the explanation will focus on the first circuit region PCA1b. The explanation regarding the same components can be similarly applied to the components of the second circuit region PCA2b and the third circuit region PCA3b. The explanation below will be given with reference to Figures 24 to 37.

[0167] A first conductive layer is placed on the substrate 100. As shown in Figure 24, the first conductive layer includes a first conductive wire 300a, a second conductive wire 300b, a first electrode 310, and a repair wire RL. In one embodiment, a barrier layer may be further placed between the substrate 100 and the first conductive layer.

[0168] The first electrode 310 is provided as an island type. The first electrode 310 is positioned on a plane between the first conductive wire 300a and the second conductive wire 300b in the first circuit region PCA1b and the second circuit region PCA2b, and may not be positioned in the third circuit region PCA3b. The area of ​​the first electrode 310 in the second circuit region PCA2b is different from the area of ​​the first electrode 310 in the first circuit region PCA1b. In one embodiment, the area of ​​the first electrode 310 in the second circuit region PCA2b is larger than the area of ​​the first electrode 310 in the first circuit region PCA1b.

[0169] The first conductive wire 300a extends in the x-direction and may be arranged across the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. The first conductive wire 300a is a drive voltage wire PL to which a drive voltage ELVDD is applied. The first conductive wire 300a includes sub-wires 300as that are disconnected and separated at predetermined intervals. The sub-wires 300as are arranged spaced apart in the x-direction. In one embodiment, the sub-wires 300as narrow the first semiconductor layer ACT1 (Figure 26) on a plane in the first circuit region PCA1b and are spaced apart by a predetermined interval SL. As a result, the sub-wires 300as do not overlap the first semiconductor layer ACT1 in the first circuit region PCA1b.

[0170] Each sub-line 300as includes a main line 300am extending in the x direction and a projection 300ap1 projecting from the main line 300am in the -y direction. The projection 300ap1 superimposes on the data line DL in each circuit region. In the second circuit region PCA2b and the third circuit region PCA3b, the sub-line 300as may further include a projection 300ap2 projecting in the +y direction. In the second circuit region PCA2b and the third circuit region PCA3b, the main line 300am and the projection 300ap2 superimpose on the first semiconductor layer ACT1. In the second circuit region PCA2b and the third circuit region PCA3b, the main line 300am and the projection 300ap2 superimpose on at least the channel region of the first transistor T1. In one embodiment, the width w25 in the x-direction of the protrusion 300ap2 in the third circuit region PCA3b is greater than the width w24 in the x-direction of the protrusion 300ap2 in the second circuit region PCA2b.

[0171] The area of ​​the first conductive wire 300a differs for each circuit region. For example, the area of ​​the first conductive wire 300a in the third circuit region PCA3b is larger than the area of ​​the first conductive wire 300a in the first circuit region PCA1b and the second circuit region PCA2b. The area of ​​the first conductive wire 300a in the second circuit region PCA2b is larger than the area of ​​the first conductive wire 300a in the first circuit region PCA1b. In one embodiment, the width w23 in the y direction of the main wire 300am in the third circuit region PCA3b is larger than the width w22 in the y direction of the main wire 300am in the second circuit region PCA2b and the width w21 in the y direction of the main wire 300am in the first circuit region PCA1b, and the width w21 in the y direction of the main wire 300am in the first circuit region PCA1b is larger than the width w22 in the y direction of the main wire 300am in the second circuit region PCA2b.

[0172] The second conductive wire 300b extends in the x-direction and may be positioned across the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. The second conductive wire 300b is a common voltage line EL to which a common voltage ELVSS is applied. Hereafter, the second conductive wire 300b and the common voltage line EL may be used interchangeably. The second conductive wire 300b may be positioned alongside the first conductive wire 300a. The second conductive wire 300b includes a main line 300m extending in the x-direction in each circuit region and a projection 300bp1 projecting from the main line 300m in the -y direction. The main line 300bm extends in the x-direction with a bend. The projection 300bp1 superimposes on the data line DL in each circuit region. The second conductive wire 300b may further include a projection 300bp2 projecting in the -y direction in the third circuit region PCA3b. In the third circuit region PCA3b, the protrusion 300bp2 is positioned on a plane, narrowing the protrusion 300ap2 of the first conductive wire 300a and moving away from the protrusion 300bp1.

[0173] The repair line RL extends in the x-direction and may be positioned across the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0174] A first conductive layer is placed on the substrate 100, with a first insulating layer 111 covering it, and a second conductive layer may be placed on the first insulating layer 111. As shown in Figure 25, the second conductive layer includes a second electrode 320, a lower first gate line GWLb, a reference voltage line VRL, and / or first-to-second initialization voltage lines VL12.

[0175] The second electrode 320 is provided as an island type. The second electrode 320 is superimposed on a portion of the first conductive wire 300a and the second conductive wire 300b. In the first circuit region PCA1b and the second circuit region PCA2b, the second electrode 320 is superimposed on the first electrode 310. In the third circuit region PCA3b, the second electrode 320 is superimposed on the protrusion 300bp2 of the second conductive wire 300b. The second electrode 320 is the second gate electrode G12 and source electrode of the first transistor T1. In the first circuit region PCA1b and the second circuit region PCA2b, an aperture SOP may be defined for the second electrode 320 superimposed on the first electrode 310. The area of ​​the second electrode 320 differs for each circuit region. In one embodiment, the area of ​​the second electrode 320 in the third circuit region PCA3b is larger than the area of ​​the second electrode 320 in the first circuit region PCA1b, and the area of ​​the second electrode 320 in the first circuit region PCA1b is larger than the area of ​​the second electrode 320 in the second circuit region PCA2b. The area in which the second electrode 320 overlaps the first electrode 310 in the second circuit region PCA2b is larger than the area in which the second electrode 320 overlaps the first electrode 310 in the first circuit region PCA1b.

[0176] The lower first gate line GWLb, reference voltage line VRL, and first-to-second initialization voltage line VL12 extend in the x direction and may be positioned across the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0177] A second insulating layer 112 is disposed on the first insulating layer 111, covering or superimposing the second conductive layer, and a semiconductor layer ACT containing an oxide semiconductor is disposed on the second insulating layer 112, as shown in Figure 26. The semiconductor layer ACT includes a first semiconductor layer ACT1, a second semiconductor layer ACT2, and / or a third semiconductor layer ACT3. The semiconductor layer ACT includes the source region, drain region, and channel region between the source region and drain region of the first to sixth transistors T1 to T6, respectively. Depending on the embodiment, the source region and drain region may also be interpreted as the source electrode and drain electrode of the transistor.

[0178] Figure 28 shows the transistors in the first circuit region PCA1b. Referring to Figure 28, the first semiconductor layer ACT1 includes the source region S1 and drain region D1 of the first transistor T1, and the source region S5 and drain region D5 of the fifth transistor T5. The second semiconductor layer ACT2 includes the source region S2 and drain region D2 of the second transistor T2, and the source region S3 and drain region D3 of the third transistor T3. The third semiconductor layer ACT3 includes the source region S4 and drain region D4 of the fourth transistor T4, and the source region S6 and drain region D6 of the sixth transistor T6.

[0179] A third insulating layer 113 may be disposed on the second insulating layer 112, covering or superimposing a semiconductor layer ACT, and a third conductive layer may be disposed on the third insulating layer 113. As shown in Figure 27, the third conductive layer includes a third electrode 330, a fourth electrode 340, connecting electrodes 350 and 360, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, and / or a first-first initialization voltage line VL11.

[0180] The third electrode 330, the fourth electrode 340, and the connecting electrodes 350 and 360 are provided as island-type electrodes. The third electrode 330, the fourth electrode 340, and the connecting electrode 350 may be arranged in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b, respectively. The connecting electrode 360 ​​may be arranged in part of the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. For example, as shown in Figure 27, the connecting electrode 360 ​​is arranged between the second circuit region PCA2b and the third circuit region PCA3b. Part of the connecting electrode 360 ​​is superimposed on the data line DL. Part of the connecting electrode 360 ​​is superimposed on the first conductive line 300a.

[0181] The area of ​​the third electrode 330 in the first circuit region PCA1b and the third circuit region PCA3b is greater than the area of ​​the third electrode 330 in the second circuit region PCA2b. The area in which the third electrode 330 overlaps the second electrode 320 in the first circuit region PCA1b and the third circuit region PCA3b is greater than the area in which the third electrode 330 overlaps the second electrode 320 in the second circuit region PCA2b.

[0182] In the first circuit region PCA1b and the second circuit region PCA2b, the third electrode 330 can be electrically connected to the first electrode 310 via a contact hole 31b that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113. The contact hole 31b is insulated from the opening SOP of the second electrode 320 and is located within the opening SOP.

[0183] In the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b, the connecting electrode 350 can be electrically connected to the protruding portion 300ap1 of the first conductive wire 300a via a contact hole 33b that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0184] Between the second circuit region PCA2b and the third circuit region PCA3b, the connecting electrode 360 ​​can be electrically connected to the protruding portion 300bp1 of the second conductive wire 300b via a contact hole 34b that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0185] The upper first gate line GWLt, second gate line GIL, third gate line GRL, fourth gate line EML, fifth gate line EMBL, and 1-1 initialization voltage line VL11 extend in the x direction and may be arranged across the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0186] The upper first gate wire GWLt is superimposed on the lower first gate wire GWLtb and can be electrically connected to the lower first gate wire GWLtb via contact holes 32b that penetrate the second insulating layer 112 and the third insulating layer 113.

[0187] As shown in Figure 28, the third conductive layer includes the gate electrodes G1 to G6 of the first to sixth transistors T1 to T6. The gate electrodes G1 to G6 are superimposed on the channel region of the semiconductor layer ACT.

[0188] Referring to Figure 28, the third electrode 330 includes the first gate electrode G11 of the first transistor T1. The first gate electrode G11 is superimposed on the first semiconductor layer ACT1. The fourth electrode 340 is the gate electrode G2 of the second transistor T2. The fourth electrode 340 is superimposed on the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 is the portion of the third gate line GRL that is superimposed on the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 is the portion of the second gate line GIL that is superimposed on the third semiconductor layer ACT3. The gate electrode G5 of the fifth transistor T5 is the portion of the fourth gate line EML that is superimposed on the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 is the portion of the fifth gate line EMBL that is superimposed on the third semiconductor layer ACT3.

[0189] A fourth insulating layer 114 is placed on top of the third insulating layer 113, covering the third conductive layer, and a fourth conductive layer is placed on top of the fourth insulating layer 114. As shown in Figure 29A, the fourth conductive layer includes data lines DL and connecting electrodes 370, 371, 372, 373, 374, 375, 376, 377, and 378.

[0190] The data lines DL are arranged extending in the y-direction for each circuit region. The data lines DL are electrically connected to the drain region D2 of the second transistor T2 via contact holes 43b that penetrate the third insulating layer 113 and the fourth insulating layer 114.

[0191] The connecting electrode 370 includes a first region 370a superimposed on the first electrode 310, the second electrode 320, and the third electrode 330, and a second region 370b protruding from the first region 370a in the -y direction. The connecting electrode 370 electrically connects the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the sixth transistor T6.

[0192] The first region 370a of the connecting electrode 370 can be electrically connected to the source region S1 of the first transistor T1 via a contact hole 42b that penetrates the third insulating layer 113 and the fourth insulating layer 114. The first region 370a of the connecting electrode 370 can be electrically connected to the second electrode 320 via a contact hole 41b that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. Thus, the connecting electrode 370 can be a source electrode electrically connected to the source region S1 of the first transistor T1. The second electrode 320 corresponds to the second gate electrode G12 of the first transistor T1, which faces the first gate electrode G11 of the first transistor T1 and superimposes on the channel region of the first transistor T1. By connecting the connecting electrode 370 to the second electrode 320, the second gate electrode G12 of the first transistor T1 can be electrically connected to the source region S1 of the first transistor T1.

[0193] The second region 370b of the connecting electrode 370 can be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 50b that penetrates the third insulating layer 113 and the fourth insulating layer 114.

[0194] The connecting electrode 371 can be electrically connected to the gate electrode G2 of the second transistor T2 via a contact hole 45b that penetrates the fourth insulating layer 114. The connecting electrode 371 can also be electrically connected to the upper first gate wire GWLt via a contact hole 44b that penetrates the fourth insulating layer 114.

[0195] The connecting electrode 372 is electrically connected to the source region S3 of the third transistor T3 via a contact hole 46b that penetrates the third insulating layer 113 and the fourth insulating layer 114, and can be electrically connected to the reference voltage line VRL via a contact hole 47b that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0196] The connecting electrode 373 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 48b that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 373 can be electrically connected to the third electrode 330 via a contact hole 49b that penetrates the fourth insulating layer 114, and thereby electrically connected to the first gate electrode G11 of the first transistor T1. The connecting electrode 373 is a node electrode corresponding to the first node N1 in Figure 22. The connecting electrode 373 is a bridge electrode that electrically connects at least two transistors. For example, the connecting electrode 373 is a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0197] The connecting electrode 374 can be electrically connected to the protruding portion 300p1 of the first conductive wire 200 via a contact hole 51b that penetrates the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connecting electrode 374 can also be electrically connected to the drain region D5 of the fifth transistor T5 via a contact hole 52b that penetrates the third insulating layer 113 and the fourth insulating layer 114. This allows the drain region D5 of the fifth transistor T5 to be electrically connected to the first conductive wire 300a.

[0198] In a portion of the first circuit region PCA1b, the connecting electrode 374 may further have a protruding portion 374p, as shown in Figure 29B. For example, the protruding portion 374p of the connecting electrode 374 is formed only in the first circuit region PCA1b where the vertical drive voltage line PLv (see Figure 30), which will be described later, is located.

[0199] The connecting electrode 375 can be electrically connected to the source region S6 of the sixth transistor T6 and the drain region D4 of the fourth transistor T4 via a contact hole 53b that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 375 superimposes a portion of the repair line RL. The connecting electrode 375 is insulated from the repair line RL and can be electrically connected to the repair line RL if a defect occurs in a pixel circuit located in the circuit region later.

[0200] In the first circuit region PCA1b, the connecting electrode 376 can be electrically connected to the source region S4 of the fourth transistor T4 via a contact hole 54b that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 376 can also be connected to the first-1 initialization voltage line VL11 via a contact hole 55b that penetrates the fourth insulating layer 114.

[0201] In the second circuit region PCA2b and the third circuit region PCA3b, the connecting electrode 376 can be electrically connected to the source region S4 of the fourth transistor T4 via a contact hole 54b that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 376 can also be electrically connected to the first-to-second initialization voltage line VL12 via a contact hole 56b that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0202] In a portion of the first circuit region PCA1b, the connecting electrode 376 may further have a protrusion 376p, as shown in Figure 29C. For example, the protrusion 376p of the connecting electrode 376 is formed only in the first circuit region PCA1b where the first vertical initialization voltage line VLl1v (see Figure 31), which will be described later, is located.

[0203] In the first circuit region PCA1b, the connecting electrode 377 can be electrically connected to the first-to-second initialization voltage line VL12 via a contact hole 57b that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connecting electrode 377 can be placed only in a portion of the first circuit region PCA1b. For example, the connecting electrode 377 can be placed only in the first circuit region PCA1b where the second vertical initialization voltage line VL12v (see Figure 32), one of the vertical conductive lines described later, is located.

[0204] In the second circuit region PCA2b, the connecting electrode 378 can be electrically connected to the connecting electrode 360 ​​via a contact hole 57b that penetrates the fourth insulating layer 114.

[0205] A fifth insulating layer 115 is positioned on top of the fourth insulating layer 114, covering or superimposing the fourth conductive layer, and a fifth conductive layer is positioned on top of the fifth insulating layer 115. As shown in Figures 30 to 33, the fifth conductive layer includes a vertical conductive wire VCL and connecting electrodes 381 and 383. For ease of illustration and explanation, only a portion of the lower conductive layer connected to the fifth conductive layer is shown in Figures 30 to 32.

[0206] The connecting electrode 381 can be electrically connected to the connecting electrode 375 via a contact hole 61b that penetrates the fifth insulating layer 115, and thereby electrically connected to the source region S6 of the sixth transistor T6.

[0207] The connecting electrode 383 may be electrically connected to the connecting electrode 370 via a contact hole 62b that penetrates the fifth insulating layer 115. The connecting electrode 383 may cover the node electrode, the connecting electrode 373, and be positioned superimposed on the connecting electrode 373. The second electrode 320 may be positioned below the connecting electrode 373, and the connecting electrode 383 may be positioned above the connecting electrode 373. The connecting electrode 383 covers the connecting electrode 373 substantially, and the second electrode 320 covers the connecting electrode 373 substantially. The connecting electrode 383 functions as an upper shielding layer for the connecting electrode 373, and the second electrode 320 functions as a lower shielding layer for the connecting electrode 373.

[0208] The vertical conductive lines VCL include the vertical drive voltage line PLv, the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the vertical common voltage line ELv, and the vertical reference voltage line VRLv. Each vertical conductive line VCL extends in the y direction and may be arranged in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b, spaced apart from each other in the x direction.

[0209] Four vertical conductive lines VCL may be arranged spaced apart in the x-direction in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b. For example, four vertical conductive lines VCL from among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv may be arranged spaced apart in the x-direction. The vertical conductive lines VCL may be electrically connected to horizontal conductive lines extending in the x-direction. The horizontal conductive lines include the first conductive line 300a, which is the drive voltage line PL; the second conductive line 300b, which is the common voltage line EL; the first-1 initialization voltage line VL11; the first-2 initialization voltage line VL12; and the reference voltage line VRL.

[0210] Figure 30 shows an example in which a vertical drive voltage line PLv, a pair of vertical common voltage lines ELv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0211] Figure 31 shows an example in which the first vertical initialization voltage line VL11v, a pair of vertical drive voltage lines PLv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0212] Figure 32 shows an example in which the second vertical initialization voltage line VLl2v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b.

[0213] A pair of adjacent vertical drive voltage lines PLv may be connected by a coupling section BR. A pair of vertical drive voltage lines PLv may be formed integrally. In one embodiment, the coupling section BR is located every two rows. For example, a pair of vertical drive voltage lines PLv may be connected by a coupling section BR in odd-numbered or even-numbered rows, as shown in Figure 31, and separated from each other without coupling sections BR in even-numbered or odd-numbered rows.

[0214] In one embodiment, as shown in Figure 33, the first vertical conduction line VCL of the unit circuit region PCAu is the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, or the vertical drive voltage line PLv. The fourth vertical conduction line VCL of the unit circuit region PCAu is the vertical reference voltage line VRLv. The second and third vertical conduction lines VCL of the unit circuit region PCAu are a pair of vertical drive voltage lines PLv, a pair of vertical common voltage lines ELv, or a pair of vertical drive voltage lines PLv and a vertical common voltage line ELv.

[0215] As shown in Figure 30, the vertical drive voltage line PLv can be electrically connected to a connecting electrode 374 located in the first circuit region PCA1b via a contact hole 67b that penetrates the fifth insulating layer 115. As shown in Figure 31, the vertical drive voltage line PLv can be electrically connected to a connecting electrode 374 located in the second circuit region PCA2b via a contact hole 64b that penetrates the fifth insulating layer 115. The connecting electrode 374 is electrically connected to the first conductive wire 300a, and the drive voltage line PL has a mesh structure in the display region DA.

[0216] As shown in Figure 31, the first vertical initialization voltage line VL11v can be electrically connected to a connecting electrode 376 located in the first circuit region PCA1b via a contact hole 63b that penetrates the fifth insulating layer 115. The connecting electrode 376 is electrically connected to the first-first initialization voltage line VL11, which has a mesh structure in the display region DA.

[0217] As shown in Figure 32, the second vertical initialization voltage line VL12v can be electrically connected to a connecting electrode 377 located in the first circuit region PCA1b via a contact hole 66b that penetrates the fifth insulating layer 115. The connecting electrode 377 is electrically connected to the first-to-second initialization voltage line VL12, which has a mesh structure in the display region DA.

[0218] As shown in Figures 30 and 32, the vertical common voltage line ELv can be electrically connected to a connecting electrode 378 located in the second circuit region PCA2b via a contact hole 66b that penetrates the fifth insulating layer 115. The connecting electrode 378 is electrically connected to the second conductive wire 300b, which is the common voltage line EL, and the common voltage line EL has a mesh structure in the display region DA. In one embodiment, the vertical common voltage line ELv can be electrically connected to a common voltage supply line 13 (Figure 2) located in the peripheral region PA.

[0219] As shown in Figures 30 to 32, the vertical reference voltage line VRLv can be electrically connected to a connecting electrode 372 located in the third circuit region PCA3b via a contact hole 65b that penetrates the fifth insulating layer 115. The connecting electrode 372 is electrically connected to the reference voltage line VRL, which has a mesh structure in the display region DA.

[0220] Although not shown in the diagram, the peripheral region PA may also contain additional voltage supply lines electrically connected to the horizontal and / or vertical conductive lines. The voltage supply lines may be located on at least one of the following sides of the peripheral region PA: above, below, left, and right.

[0221] The corresponding connecting electrodes in the first circuit region PCA1b, the second circuit region PCA2b, and the third circuit region PCA3b, which have the same actual function, may differ in shape and position depending on the position of the wiring placed in the circuit region.

[0222] The pixel electrode 511 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 581, which is a lower conductive pattern, via the contact hole 71b of the sixth insulating layer 116. As shown in Figure 34, the pixel electrode 511 connected to the pixel circuit of the first pixel PX1 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 381 located in the first circuit region PCA1b. The pixel electrode 511 connected to the pixel circuit of the second pixel PX2 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 381 located in the second circuit region PCA2b. The pixel electrode 511 connected to the pixel circuit of the third pixel PX3 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 381 located in the third circuit region PCA3b.

[0223] As shown in Figure 3, auxiliary electrodes AE may also be placed on the same layer as the pixel electrodes 511.

[0224] As shown in Figures 35 to 37, a seventh insulating layer 117, which is a pixel-defining layer covering the edges of the pixel electrode 511, may be placed on top of the pixel electrode 511. The seventh insulating layer 117 may have an aperture 117OP that exposes a portion of the pixel electrode 511 and defines a light-emitting region. The seventh insulating layer 117 is a single-layer or multi-layer organic insulating layer and / or inorganic insulating layer. The intermediate layer includes a light-emitting layer 513 and a first functional layer below the light-emitting layer 513 and / or a second functional layer above the light-emitting layer 513. The counter electrode 515 may be integrally formed to correspond to an organic light-emitting diode OLED placed in the display region DA.

[0225] Referring to Figures 35 to 37, in embodiments of the present invention, the first conductive wire 300a can be arranged to correspond to or not to the channel region CH1 of the first transistor T1, thereby minimizing (preventing) disconnection of the channel region CH1 of the first transistor T1.

[0226] Embodiments of the present invention allow for the optimization of the ratio of the first capacitor C1, the second capacitor C2, and the third capacitor C3 for each pixel by adjusting the degree of overlap between the first conductive wire 300a and the second electrode 320, the degree of overlap between the second conductive wire 300b and the second electrode 320, the isolation distance between the first conductive wire 300a and the first electrode 310, and / or the size and / or width in the y direction of the first conductive wire 300a and / or the first electrode 310.

[0227] Referring to Figures 35 and 36, the first capacitor C1 of the first pixel PX1 and the second pixel PX2 includes a first electrode C11 and a second electrode C12. The first electrode C11 includes a lower first electrode C11b formed by a first electrode 310, an intermediate first electrode C11m formed by a third electrode 330, and an upper first electrode C11t formed by a connecting electrode 373. The lower first electrode C11b and the intermediate first electrode C11m are electrically connected via a contact hole 31b, and the intermediate first electrode C11m and the upper first electrode C11t are electrically connected via a contact hole 49b. The second electrode C12 includes a lower second electrode C12b formed by a second electrode 320, an intermediate second electrode C12m formed by a connecting electrode 370, and an upper second electrode C12t formed by a connecting electrode 383. The lower second electrode C12b and the intermediate second electrode C12m are electrically connected via a contact hole 41b, and the intermediate second electrode C12m and the upper second electrode C12t are electrically connected via a contact hole 62b.

[0228] The capacitance of the first capacitor C1 is the sum of the capacitance formed by the lower first electrode C11b and the lower second electrode C12b, the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 has a parallel connection structure of subcapacitors formed by conductive wires superimposed in the z direction, thereby allowing the capacitance to be increased (or secured) in the x and y directions without increasing the area.

[0229] The width wc2 in the y-direction of the lower first electrode C11b of the first capacitor C1 of the second pixel PX2 is greater than the width wc2 in the y-direction of the lower first electrode C11b of the first capacitor C1 of the first pixel PX1. The area where the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the second pixel PX2 overlap is greater than the area where the lower first electrode C11b and the lower second electrode C12b of the first capacitor C1 of the first pixel PX1 overlap. The sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the first pixel PX1 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap, is greater than the sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the second pixel PX2 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap.

[0230] The second capacitor C2 of the first pixel PX1 and the second pixel PX2 includes a first electrode C21 formed by a conductive wire 200 and a second electrode C22 formed by a second electrode 320. The area over which the second electrode C22 of the second pixel PX2 overlaps the first electrode C21 is the same as or different from the area over which the second electrode C22 of the first pixel PX1 overlaps the first electrode C21.

[0231] The third capacitor C3 of the first pixel PX1 and the second pixel PX2 includes a first electrode C31 formed by a second conductive wire 300b and a second electrode C32 formed by a portion of the second electrode 320.

[0232] Referring to Figure 37, the first capacitor C1 of the third pixel PX3 includes a first electrode C11 and a second electrode C12. The first electrode C11 includes an intermediate first electrode C11m formed by the third electrode 330 and an upper first electrode C11t formed by the connecting electrode 373. The second electrode C12 includes a lower second electrode C12b formed by the second electrode 320, an intermediate second electrode C12m formed by the connecting electrode 370, and an upper second electrode C12t formed by the connecting electrode 383. The capacitance of the first capacitor C1 is the sum of the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 has a parallel connection structure of subcapacitors formed by conductive wires superimposed in the z direction, thereby allowing the capacitance to be increased (secured) in the x and y directions without increasing the area.

[0233] The sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the third pixel PX3 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap, is greater than the sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the first pixel PX1 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap, and is greater than the sum of the area where the lower second electrode C12b and the intermediate first electrode C11m of the first capacitor C1 of the second pixel PX2 overlap, and the area where the intermediate first electrode C11m and the intermediate second electrode C12m overlap.

[0234] The second capacitor C2 of the third pixel PX3 includes a first electrode C21 formed by the first conductive wire 300a and a second electrode C22 formed by a portion of the second electrode 320. The area over which the second electrode C22 of the third pixel PX3 overlaps the first electrode C21 is larger than the area over which the second electrodes C22 of the first pixel PX1 and the second pixel PX2 overlap the first electrode C21.

[0235] The third capacitor C3 of the third pixel PX3 includes a first electrode C31 formed by the second conductive wire 300b and a second electrode C32 formed by a portion of the second electrode 320.

[0236] Figure 38 is a schematic diagram of the equivalent circuit of a pixel according to one embodiment.

[0237] The pixel circuit PCc of pixel PXc shown in Figure 38 may further include a seventh transistor T7 in addition to the pixel circuit PCa of pixel PXa shown in Figure 4.

[0238] Referring to Figure 38, the seventh transistor T7 is connected between the first transistor T1 and the second initialization voltage line VL2. The seventh transistor T7 includes a gate connected to the second gate line GIL, a first terminal connected to the second node N2, and a second terminal connected to the second initialization voltage line VL2. The first terminal of the seventh transistor T7 is connected to the second terminal of the first transistor T1, the first terminal of the sixth transistor T6, the first capacitor C1, and the second capacitor C2. The seventh transistor T7 is turned on by the second gate signal GI transmitted to the second gate line GIL, and can transmit the second initialization voltage Vint2 transmitted to the second initialization voltage line VL2 to the second node N2. The voltage level of the second initialization voltage Vint2 is lower than the voltage level of the initialization voltage Vint.

[0239] The fourth transistor T4 of the pixel circuit PCc shown in Figure 38 differs from the fourth transistor T4 of the pixel circuit PCa shown in Figure 4 in that its gate is connected to the sixth gate line GBL and supplied with the sixth gate signal GB. The gate of the fourth transistor T4 is connected to the sixth gate line GBL, and the fourth transistor T4 is turned on by the sixth gate signal GB transmitted to the sixth gate line GBL, and can transmit the initialization voltage Vint transmitted to the initialization voltage line VL to the third node N3.

[0240] The second capacitor C2 of the pixel circuit PCc shown in Figure 38 differs from the second capacitor C2 of the pixel circuit PCa shown in Figure 4 in that it is connected at least between the reference voltage line VRL and the second node N2. The first electrode of the second capacitor C2 may be connected to the reference voltage line VRL. The second electrode of the second capacitor C2 may be connected to the second terminal and second gate of the first transistor T1, the second electrode of the first capacitor C1, the first terminal of the seventh transistor T7, and the first terminal of the sixth transistor T6. The capacitances of the first capacitor C1 and the second capacitor C2 may vary depending on the color of the light emitted by the pixel PXc.

[0241] The other configurations of the pixel circuit PCc shown in Figure 38 are identical to those of the pixel circuit PCa shown in Figure 4.

[0242] Figure 39 is a schematic arrangement diagram showing the positions of transistors and capacitors in a pixel according to one embodiment. Figures 40 to 50 are schematic arrangement diagrams showing the pixel components layer by layer. Figure 49 is a schematic diagram showing the arrangement of vertical conductive wires according to one embodiment. Figure 51 is a schematic cross-sectional view taken along lines VI-VI' and VII-VII' in Figures 39 and 50.

[0243] In Figure 39, the pixel circuits located in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c correspond to the pixel circuits PCc of the pixels shown in Figure 38, respectively.

[0244] In one embodiment, the pixel circuit PCc of the first pixel PX1 is connected to the 1-1 initialization voltage line VL11, and the pixel circuits PCc of the second pixel PX2 and the third pixel PX3 are connected to the 1-2 initialization voltage line VL12. The initialization voltage supplied to the 1-1 initialization voltage line VL11 and the initialization voltage supplied to the 1-2 initialization voltage line VL12 may be different.

[0245] For the sake of illustration and explanation, identification numbers will be assigned to the elements of the pixel circuit PCc located in the first circuit region PCA1c, and the explanation will focus on the first circuit region PCA1c. The explanation regarding the same components can be similarly applied to the components of the second circuit region PCA2c and the third circuit region PCA3c. The explanation below will be given with reference to Figures 39 to 51.

[0246] A first conductive layer is placed on the substrate 100. As shown in Figure 40, the first conductive layer includes a first conductive wire 400a, a second conductive wire 400b, a reference voltage wire VRL, and / or a repair wire RL. In one embodiment, a barrier layer may be further placed between the substrate 100 and the first conductive layer.

[0247] The first conductive wire 400a extends in the x-direction and may be positioned across the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c. The first conductive wire 400a is a drive voltage line PL to which the drive voltage ELVDD is applied. The first conductive wire 400a includes a main line 400m extending in the x-direction and a projection 400ap projecting from the main line 400m in the -y direction. The projection 400ap superimposes on the data line DL in each circuit region.

[0248] The second conductive wire 400b extends in the x-direction and may be positioned across the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0249] The second conductive wire 400b is a drive voltage line PL to which the drive voltage ELVDD is applied. The second conductive wire 400b includes a main wire 400m extending in the x direction and a projection 400bp projecting from the main wire 400m in the -y direction. The projection 400bp is superimposed on the first semiconductor layer ACT1 in each circuit region. The projection 400bp is superimposed on the entire channel region of the first transistor T1. The second conductive wire 400b functions as the first electrode C21 of the second capacitor C2. For example, the first electrode C21 of the second capacitor C2 in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c are connected to each other.

[0250] The reference voltage line VRL is arranged in parallel with the second conductive line 400b, extends in the x direction, and can be arranged across the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c. The reference voltage line VRL is connected to the second conductive line 400b via the connection part CP. Therefore, the second conductive line 400b can be understood as a part of the reference voltage line VRL. In one embodiment, the reference voltage line VRL, the second conductive line 400b, and the connection part CP are integrally formed with each other and provided in the same layer. The connection part CP overlaps the data line DL.

[0251] The repair line RL extends in the x direction and can be arranged across the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0252] The first insulating layer 111 is arranged to cover the first conductive layer on the substrate 100, and the second conductive layer can be arranged on the first insulating layer 111. As shown in FIG. 41, the second conductive layer includes the first electrode 420, the lower first gate line GWLb, the second initialization voltage line VL2, and / or the first - 2 initialization voltage line VL12.

[0253] The first electrode 420 is provided as an island type. The first electrode 420 overlaps the second conductive line 400b and the protrusion 400bp. The first electrode 420 is the second gate electrode G12 and the source electrode of the first transistor T1.

[0254] The lower first gate line GWLb, the second initialization voltage line VL2, and the first - 2 initialization voltage line VL12 extend in the x direction and can be arranged across the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0255] A second insulating layer 112 is disposed to cover a second conductive layer on a first insulating layer 111, and a semiconductor layer ACT including an oxide semiconductor is disposed on the second insulating layer 112 as shown in FIG. 42. The semiconductor layer ACT includes a first semiconductor layer ACT1, a second semiconductor layer ACT2, a third semiconductor layer ACT3, a fourth semiconductor layer ACT4, and a fifth semiconductor layer ACT5. The semiconductor layer ACT includes source regions, drain regions, and channel regions between the source regions and the drain regions of the first to seventh transistors T1 to T7, respectively. The source regions and drain regions may be interpreted as source electrodes and drain electrodes of the transistors in some cases.

[0256] FIG. 44 is a diagram schematically showing the transistors in the first circuit region PCA1c. Referring to FIG. 44, the first semiconductor layer ACT1 includes source regions S1 and drain regions D1 of the first transistor T1, and source regions S5 and drain regions D5 of the fifth transistor T5. The second semiconductor layer ACT2 includes source regions S2 and drain regions D2 of the second transistor T2, and source regions S3 and drain regions D3 of the third transistor T3. The third semiconductor layer ACT3 includes source regions S6 and drain regions D6 of the sixth transistor T6. The fourth semiconductor layer ACT4 includes source regions S4 and drain regions D4 of the fourth transistor T4. The fifth semiconductor layer ACT5 includes source regions S7 and drain regions D7 of the seventh transistor T7.

[0257] A third insulating layer 113 is disposed to cover the semiconductor layer ACT on the second insulating layer 112, and a third conductive layer may be disposed on the third insulating layer 113. As shown in FIG. 43, the third conductive layer includes a second electrode 430, a third electrode 440, connecting electrodes 450 and 460, an upper first gate line GWLt, a second gate line GIL, a third gate line GRL, a fourth gate line EML, a fifth gate line EMBL, a sixth gate line GBL, and / or a first-1 initialization voltage line VL11.

[0258] The second electrode 430, the third electrode 440, and the connecting electrodes 450 and 460 are provided as island-type electrodes. The second electrode 430, the third electrode 440, and the connecting electrodes 450 and 460 can be arranged in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c, respectively.

[0259] The connecting electrode 450 can be electrically connected to the protruding portion 400ap of the first conductive wire 400a via a contact hole 51a that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0260] The connecting electrode 460 can be electrically connected to the reference voltage line VRL via a contact hole 35c that penetrates the first insulating layer 111, the second insulating layer 112, and the third insulating layer 113.

[0261] The upper first gate line GWLt, second gate line GIL, third gate line GRL, fourth gate line EML, fifth gate line EMBL, sixth gate line GBL, and 1-1 initialization voltage line VL11 extend in the x direction and may be arranged across the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0262] The upper first gate wire GWLt is superimposed on the lower first gate wire GWLtb and can be electrically connected to the lower first gate wire GWLtb via contact holes 32c that penetrate the second insulating layer 112 and the third insulating layer 113. The first gate wire GWL has a two-layer structure, including the lower first gate wire GWLb and the upper first gate wire GWLt, which are arranged in different layers.

[0263] As shown in Figure 44, the third conductive layer includes the gate electrodes G1 to G7 of the first to seventh transistors T1 to T7. The gate electrodes G1 to G7 are superimposed on the channel region of the semiconductor layer ACT.

[0264] Referring to Figure 44, the second electrode 430 includes the first gate electrode G11 of the first transistor T1. The first gate electrode G11 is superimposed on the first semiconductor layer ACT1. The third electrode 440 is the gate electrode G2 of the second transistor T2. The third electrode 440 is superimposed on the second semiconductor layer ACT2. The gate electrode G3 of the third transistor T3 is the portion of the third gate line GRL that is superimposed on the second semiconductor layer ACT2. The gate electrode G4 of the fourth transistor T4 is the portion of the sixth gate line GBL that is superimposed on the fourth semiconductor layer ACT4. The gate electrode G5 of the fifth transistor T5 is the portion of the fourth gate line EML that is superimposed on the first semiconductor layer ACT1. The gate electrode G6 of the sixth transistor T6 is the portion of the fifth gate line EMBL that is superimposed on the third semiconductor layer ACT3. The gate electrode G7 of the seventh transistor T7 is the portion of the second gate line GIL that is superimposed on the fifth semiconductor layer ACT5.

[0265] A fourth insulating layer 114 is placed on the third insulating layer 113, covering the third conductive layer, and a fourth conductive layer is placed on the fourth insulating layer 114. As shown in Figure 45A, the fourth conductive layer includes data lines DL and connecting electrodes 470, 471, 472, 473, 474, 475, 476, 477, 478, and 479.

[0266] The data lines DL are arranged extending in the y-direction for each circuit region. The data lines DL are electrically connected to the drain region D2 of the second transistor T2 via contact holes 43c that penetrate the third insulating layer 113 and the fourth insulating layer 114.

[0267] The connecting electrode 470 includes a first region 470a superimposed on the second conductive wire 400b, the first electrode 420, and the second electrode 430, and a second region 470b protruding from the first region 470a in the -y direction. The connecting electrode 470 electrically connects the source region S1 of the first transistor T1 to the second gate electrode G12 of the first transistor T1 and the sixth transistor T6.

[0268] The first region 470a of the connecting electrode 470 can be electrically connected to the source region S1 of the first transistor T1 via a contact hole 42c that penetrates the third insulating layer 113 and the fourth insulating layer 114. The first region 470a of the connecting electrode 470 can be electrically connected to the first electrode 420 via a contact hole 41c that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. Thus, the connecting electrode 470 can be a source electrode electrically connected to the source region S1 of the first transistor T1. The first electrode 420 corresponds to the second gate electrode G12 of the first transistor T1, and the second gate electrode G12 faces the first gate electrode G11 of the first transistor T1 and superimposes on the channel region of the first transistor T1. By connecting the connecting electrode 470 to the first electrode 420, the second gate electrode G12 of the first transistor T1 can be electrically connected to the source region S1 of the first transistor T1.

[0269] The second region 470b of the connecting electrode 470 can be electrically connected to the drain region D6 of the sixth transistor T6 via a contact hole 50c that penetrates the third insulating layer 113 and the fourth insulating layer 114. The second region 470b of the connecting electrode 470 can be electrically connected to the drain region D7 of the seventh transistor T7 via a contact hole 58c that penetrates the third insulating layer 113 and the fourth insulating layer 114.

[0270] The connecting electrode 471 can be electrically connected to the gate electrode G2 of the second transistor T2 via a contact hole 45c that penetrates the fourth insulating layer 114. The connecting electrode 471 can also be electrically connected to the upper first gate wire GWLt via a contact hole 44c that penetrates the fourth insulating layer 114.

[0271] The connecting electrode 472 is electrically connected to the source region S3 of the third transistor T3 via a contact hole 46c that penetrates the third insulating layer 113 and the fourth insulating layer 114, and can be electrically connected to the reference voltage line VRL via a contact hole 47c that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0272] The connecting electrode 473 can be electrically connected to the source region S2 of the second transistor T2 and the drain region D3 of the third transistor T3 via a contact hole 48c that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 473 can be electrically connected to the second electrode 430 via a contact hole 49c that penetrates the fourth insulating layer 114, and thereby electrically connected to the first gate electrode G11 of the first transistor T1. The connecting electrode 473 is a node electrode corresponding to the first node N1 in Figure 38. The connecting electrode 473 is a bridge electrode that electrically connects at least two transistors. For example, the connecting electrode 473 is a bridge electrode that connects the first gate electrode G11 of the first transistor T1, the source region S2 of the second transistor T2, and the drain region D3 of the third transistor T3.

[0273] The connecting electrode 474 can be electrically connected to the protruding portion 400ap of the first conductive wire 400a via a contact hole 51c that penetrates the first insulating layer 111, the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connecting electrode 474 can also be electrically connected to the drain region D5 of the fifth transistor T5 via a contact hole 52c that penetrates the third insulating layer 113 and the fourth insulating layer 114. This allows the drain region D5 of the fifth transistor T5 to be electrically connected to the first conductive wire 400a.

[0274] The connecting electrode 475 can be electrically connected to the source region S6 of the sixth transistor T6 via a contact hole 53c that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 475 can be electrically connected to the drain region D4 of the fourth transistor T4 via a contact hole 59c that penetrates the third insulating layer 113 and the fourth insulating layer 114. The connecting electrode 475 superimposes on a portion of the repair line RL. The connecting electrode 475 is insulated from the repair line RL and can be electrically connected to the repair line RL if a defect occurs in a pixel circuit located in the circuit region later.

[0275] In the first circuit region PCA1c, the connection electrode 476 can be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole 54c penetrating through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 476 can be connected to the first-1 initialization voltage line VL11 through a contact hole 55c penetrating through the fourth insulating layer 114.

[0276] In the second circuit region PCA2c and the third circuit region PCA3c, the connection electrode 476 can be electrically connected to the source region S4 of the fourth transistor T4 through a contact hole 54c penetrating through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 476 can be electrically connected to the first-2 initialization voltage line VL12 through a contact hole 56c penetrating through the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0277] In a part of the first circuit region PCA1c, as shown in FIG. 45B, the connection electrode 476 may further have a protruding portion 476p. For example, the protruding portion 476p of the connection electrode 476 is formed only in the first circuit region PCA1c where the first vertical initialization voltage line VLl1v (see FIG. 46) among the vertical conductive lines described later is arranged.

[0278] In the first circuit region PCA1c, the connection electrode 477 can be electrically connected to the first-2 initialization voltage line VL12 through a contact hole 57c penetrating through the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connection electrode 477 can be arranged only in a part of the first circuit region PCA1c. For example, the connection electrode 477 is arranged only in the first circuit region PCA1c where the second vertical initialization voltage line VLl2v (see FIG. 47) among the vertical conductive lines described later is arranged.

[0279] The connection electrode 478 can be electrically connected to the source region S7 of the seventh transistor T7 through a contact hole 60c penetrating through the third insulating layer 113 and the fourth insulating layer 114. The connection electrode 478 can be electrically connected to the second initialization voltage line VL2 through a contact hole 68c penetrating through the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114.

[0280] In the second circuit region PCA2c, the connecting electrode 479 can be electrically connected to the second initialization voltage line VL2 via a contact hole 69c that penetrates the second insulating layer 112, the third insulating layer 113, and the fourth insulating layer 114. The connecting electrode 479 can be placed only in a portion of the second circuit region PCA2c. For example, the connecting electrode 479 can be placed only in the second circuit region PCA2c where the third vertical initialization voltage line VL2v (see Figure 47), one of the vertical conductive lines described later, is located.

[0281] A fifth insulating layer 115 is positioned on top of the fourth insulating layer 114, covering or superimposing the fourth conductive layer, and a fifth conductive layer is positioned on top of the fifth insulating layer 115. As shown in Figures 46 to 49, the fifth conductive layer includes vertical conductive wires VCL and connecting electrodes 481 and 483. For ease of illustration and explanation, only a portion of the lower conductive layers connected to the fifth conductive layer is shown in Figures 46 to 48.

[0282] The connecting electrode 481 can be electrically connected to the connecting electrode 475 via a contact hole 61c that penetrates the fifth insulating layer 115, and thereby electrically connected to the source region S6 of the sixth transistor T6.

[0283] The connecting electrode 483 may be electrically connected to the connecting electrode 470 via a contact hole 62c that penetrates the fifth insulating layer 115. The connecting electrode 483 may cover the connecting electrode 473, which is the node electrode, and may be positioned superimposed on the connecting electrode 473. The first electrode 420 is positioned below the connecting electrode 473, and the connecting electrode 483 is positioned above the connecting electrode 473. The connecting electrode 483 covers the connecting electrode 473 substantially, and the first electrode 420 covers or superimposes the connecting electrode 473 substantially. The connecting electrode 483 functions as an upper shielding layer for the connecting electrode 473, and the first electrode 420 functions as a lower shielding layer for the connecting electrode 473.

[0284] The vertical conductive lines VCL include the vertical drive voltage line PLv, the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL2v, the vertical common voltage line ELv, and / or the vertical reference voltage line VRLv. Each vertical conductive line VCL extends in the y direction and may be arranged in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c, spaced apart from each other in the x direction.

[0285] Four vertical conductive lines may be arranged spaced apart in the x-direction within the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c. For example, four vertical conductive lines from among the first vertical initialization voltage line VL11v, the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL2v, the vertical drive voltage line PLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv may be arranged spaced apart in the x-direction. The vertical conductive lines may be electrically connected to horizontal conductive lines extending in the x-direction. The horizontal conductive lines include conductive line 400 which is the drive voltage line PL, the first-first initialization voltage line VL11, the first-second initialization voltage line VL12, the second initialization voltage line VL2, and the reference voltage line VRL.

[0286] Figure 46 shows an example in which the first vertical initialization voltage line VL11v, a pair of vertical drive voltage lines PLv, and a vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0287] Figure 47 shows an example in which the second vertical initialization voltage line VL12v, the third vertical initialization voltage line VL2v, and a pair of vertical reference voltage lines VRLv are arranged sequentially in the x-direction in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0288] Figure 48 shows an example in which the second vertical initialization voltage line VL12v, the vertical reference voltage line VRLv, the vertical common voltage line ELv, and the vertical reference voltage line VRLv are arranged sequentially in the x-direction in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c.

[0289] A pair of adjacent vertical conductive wires VCL may be connected by a connector. A pair of vertical conductive wires VCL may be formed integrally. For example, as shown in Figure 46, a pair of adjacent vertical drive voltage lines PLv may be connected by a connector BR1. A pair of vertical drive voltage lines PLv may be formed integrally. As shown in Figure 47, a pair of adjacent vertical reference voltage lines VRLv may be connected by a connector BR2. A pair of vertical reference voltage lines VRLv may be formed integrally. In one embodiment, connectors BR1 and BR2 are located every two rows. For example, a pair of vertical drive voltage lines PLv may be connected by a connector BR1 in odd-numbered or even-numbered rows, as shown in Figure 46, and separated from each other without a connector BR1 in even-numbered or odd-numbered rows.

[0290] In one embodiment, as shown in Figure 49, the first vertical conduction line VCL of the unit circuit region PCAu is either the first vertical initialization voltage line VL11v or the second vertical initialization voltage line VL12v. The fourth vertical conduction line VCL of the unit circuit region PCAu is the vertical reference voltage line VRLv. The second and third vertical conduction lines VCL of the unit circuit region PCAu are either a pair of vertical drive voltage lines PLv, or a pair of vertical drive voltage lines PLv and a vertical reference voltage line VRLv, or a pair of vertical reference voltage lines VRLv and a vertical common voltage line ELv.

[0291] As shown in Figure 46, the vertical drive voltage line PLv can be electrically connected to a connecting electrode 474 located in the second circuit region PCA2c via a contact hole 64c that penetrates the fifth insulating layer 115. The connecting electrode 474 is electrically connected to the first conductive wire 400a, which is the drive voltage line PL, and the drive voltage line PL has a mesh structure in the display region DA.

[0292] As shown in Figure 46, the first vertical initialization voltage line VL11v can be electrically connected to a connecting electrode 476 located in the first circuit region PCA1c via a contact hole 63c that penetrates the fifth insulating layer 115. The connecting electrode 476 is electrically connected to the first-first initialization voltage line VL11, which has a mesh structure in the display region DA.

[0293] As shown in Figure 47, the second vertical initialization voltage line VL12v can be electrically connected to a connecting electrode 477 located in the first circuit region PCA1c via a contact hole 66c that penetrates the fifth insulating layer 115. The connecting electrode 477 is electrically connected to the first-to-second initialization voltage line VL12, which has a mesh structure in the display region DA.

[0294] As shown in Figure 47, the third vertical initialization voltage line VL2v can be electrically connected to a connecting electrode 479 located in the second circuit region PCA2c via a contact hole 67c that penetrates the fifth insulating layer 115. The connecting electrode 479 is electrically connected to the second initialization voltage line VL2, which has a mesh structure in the display region DA.

[0295] As shown in Figures 46 to 48, the vertical reference voltage line VRLv can be electrically connected to a connecting electrode 472 located in the second circuit region PCA2c and / or the third circuit region PCA3c via a contact hole 65c that penetrates the fifth insulating layer 115. The connecting electrode 472 is electrically connected to the reference voltage line VRL, which has a mesh structure in the display region DA.

[0296] The vertical common voltage line ELv can be electrically connected to a common voltage supply line 13 (Figure 2) located in the surrounding region PA.

[0297] Although not shown in the diagram, the peripheral region PA may also contain additional voltage supply lines electrically connected to the horizontal and / or vertical conductive lines. The voltage supply lines may be located on at least one of the following sides of the peripheral region PA: above, below, left, and right.

[0298] The corresponding connecting electrodes with the same function in the first circuit region PCA1c, the second circuit region PCA2c, and the third circuit region PCA3c may differ in shape and position depending on the position of the wiring placed in the circuit region.

[0299] A sixth insulating layer 116 is arranged on top of the fifth insulating layer 115, covering or superimposing the fifth conductive layer, and an organic light-emitting diode (OLED) is arranged on top of the sixth insulating layer 116 as a display element. The organic light-emitting diode (OLED) includes a pixel electrode 511, a counter electrode 515, and an intermediate layer between the pixel electrode 511 and the counter electrode 515.

[0300] The pixel electrode 511 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 481, which is a lower conductive pattern, via the contact hole 71c of the sixth insulating layer 116. As shown in Figure 50, the pixel electrode 511 connected to the pixel circuit of the first pixel PX1 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 481 located in the first circuit region PCA1c. The pixel electrode 511 connected to the pixel circuit of the second pixel PX2 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 481 located in the second circuit region PCA2c. The pixel electrode 511 connected to the pixel circuit of the third pixel PX3 can be electrically connected to the first transistor T1 by being electrically connected to the connecting electrode 481 located in the third circuit region PCA3.

[0301] As shown in Figure 3, auxiliary electrodes AE may also be placed on the same layer as the pixel electrodes 511.

[0302] As shown in Figure 51, a seventh insulating layer 117, which is a pixel-defining layer covering the edges of the pixel electrode 511, may be positioned above the pixel electrode 511. The seventh insulating layer 117 may have an aperture 117OP that exposes a portion of the pixel electrode 511 and defines a light-emitting region. The seventh insulating layer 117 is a single-layer or multi-layer organic insulating layer and / or inorganic insulating layer. The intermediate layer includes a light-emitting layer 513 and a first functional layer below the light-emitting layer 513 and / or a second functional layer above the light-emitting layer 513. The counter electrode 515 may be integrally formed to correspond to an organic light-emitting diode OLED positioned in the display region DA.

[0303] Referring to Figure 51, the protrusion 400bp of the second conductive wire 400b corresponds to the entire channel region CH1 of the first transistor T1 in each circuit region. In the embodiment of the present invention, by positioning the protrusion 400bp of the second conductive wire 400b to correspond to at least the channel region CH1 of the first transistor T1, it is possible to minimize (prevent) disconnection of the channel region CH1 of the first transistor T1 due to steps.

[0304] The first capacitor C1 of the first pixel PX1, the second pixel PX2, and the third pixel PX3 includes a first electrode C11 and a second electrode C12. The first electrode C11 includes an intermediate first electrode C11m formed by a second electrode 430 and an upper first electrode C11t formed by a connecting electrode 473. The intermediate first electrode C11m and the upper first electrode C11t may be electrically connected via a contact hole 49c. The second electrode C12 includes a lower second electrode C12b formed by a first electrode 420, an intermediate second electrode C12m formed by a connecting electrode 470, and / or an upper second electrode C12t formed by a connecting electrode 483. The lower second electrode C12b and the intermediate second electrode C12m are electrically connected via a contact hole 41c, and the intermediate second electrode C12m and the upper second electrode C12t are electrically connected via a contact hole 62c.

[0305] The capacitance of the first capacitor C1 is the sum of the capacitance formed by the lower second electrode C12b and the intermediate first electrode C11m, the capacitance formed by the intermediate first electrode C11m and the intermediate second electrode C12m, and the capacitance formed by the upper first electrode C11t and the upper second electrode C12t. The first capacitor C1 has a parallel connection structure of subcapacitors formed by conductive wires superimposed in the z direction, thereby allowing the capacitance to be increased (secured) in the x and y directions without increasing the area.

[0306] The second capacitor C2 includes a first electrode C21 formed by a second conductive wire 400b connected to the reference voltage line VRL, and a second electrode C22 formed by the first electrode 420. The capacitance of the second capacitor C2 can be adjusted for each pixel depending on the width in the y direction of the second conductive wire 400b including the first electrode C21 and the area over which the second electrode C22 overlaps the first electrode C21.

[0307] In the display device according to an embodiment of the present invention, at least one conductive layer located below the semiconductor layer of the drive transistor corresponds to at least the channel region of the semiconductor layer of the drive transistor, thereby preventing disconnection of the semiconductor layer due to a step at the bottom.

[0308] Figures 52A to 53B are schematic cross-sectional views showing the structure of a display element according to one embodiment.

[0309] As a display element according to one embodiment, the organic light-emitting diode (OLED) includes a pixel electrode 511, a counter electrode 515, and an intermediate layer 513m between the pixel electrode 511 (first electrode, anode) and the counter electrode 515 (second electrode, cathode).

[0310] The pixel electrode 511 contains a translucent conductive oxide such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In2O3), indium gallium oxide (IGO), or aluminum zinc oxide (AZO). The pixel electrode 511 may also contain a reflective film containing silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), or compounds thereof. For example, the pixel electrode 511 has a three-layer structure of ITO / Ag / ITO.

[0311] The counter electrode 515 is placed on the intermediate layer 513m. The counter electrode 515 includes metals, alloys, conductive compounds, or any combination thereof with a low work function. For example, the counter electrode 515 includes lithium (Li), silver (Ag), magnesium (Mg), aluminum (Al), aluminum-lithium (Al-Li), calcium (Ca), magnesium-indium (Mg-In), magnesium-silver (Mg-Ag), ytterbium (Yb), silver-ytterbium (Ag-Yb), ITO, IZO, or any combination thereof. The counter electrode 515 is a transmissive electrode, a semi-transmissive electrode, or a reflective electrode.

[0312] The intermediate layer 513m contains polymer or low molecular weight organic material that emits light of a predetermined color. In addition to various organic materials, the intermediate layer 513m may further contain metal-containing compounds such as organometallic compounds, inorganic materials such as quantum dots, etc.

[0313] In one embodiment, the intermediate layer 513m includes one light-emitting layer and a first functional layer and a second functional layer below and above the light-emitting layer, respectively. The first functional layer includes, for example, a hole transport layer (HTL) or a hole transport layer and a hole injection layer (HIL). The second functional layer includes an electron transport layer (ETL) and / or an electron injection layer (EIL). The first or second functional layer may be omitted. The first and second functional layers may be formed integrally to correspond to an organic light-emitting diode (OLED) contained in the display area DA.

[0314] In one embodiment, the intermediate layer 513m includes two or more emitting units sequentially stacked between the pixel electrode 511 and the counter electrode 515, and a charge generation layer (CGL) disposed between the two emitting units. When the intermediate layer 513m includes emitting units and a charge generation layer, the organic light-emitting diode (OLED) can be a tandem light-emitting element. The organic light-emitting diode (OLED) can improve color purity and luminous efficiency by having a stacked structure of emitting units.

[0315] A single light-emitting unit includes a light-emitting layer and a first functional layer and a second functional layer below and above the light-emitting layer, respectively. The charge generation layer CGL includes a negative charge generation layer and a positive charge generation layer. The negative charge generation layer and the positive charge generation layer can further increase the luminous efficiency of an organic light-emitting diode (OLED), which is a tandem light-emitting element equipped with a light-emitting layer.

[0316] The negative charge generation layer is an n-type charge generation layer. The negative charge generation layer supplies electrons. The negative charge generation layer contains a host and a dopant. The host contains organic material. The dopant contains metallic material. The positive charge generation layer is a p-type charge generation layer. The positive charge generation layer supplies holes. The positive charge generation layer contains a host and a dopant. The host contains organic material. The dopant contains metallic material.

[0317] In one embodiment, as shown in Figure 52A, the organic light-emitting diode (OLED) includes a first light-emitting unit EU1, which includes a first light-emitting layer EML1, and a second light-emitting unit EU2, which includes a second light-emitting layer EML2, stacked in order. A charge generation layer CGL may be provided between the first light-emitting unit EU1 and the second light-emitting unit EU2. For example, the organic light-emitting diode (OLED) includes a pixel electrode 211, a first light-emitting layer EML1, a charge generation layer CGL, a second light-emitting layer EML2, and a counter electrode 515, stacked in order. A first functional layer and a second functional layer may be included below and above the first light-emitting layer EML1, respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer EML2, respectively. The first light-emitting layer EML1 may be a blue light-emitting layer, and the second light-emitting layer EML2 may be a yellow light-emitting layer.

[0318] In some embodiments, as shown in Figure 52B, the organic light-emitting diode (OLED) includes a first light-emitting unit EU1 and a third light-emitting unit EU3, each containing a first light-emitting layer EML1, and a second light-emitting unit EU2, each containing a second light-emitting layer EML2. A first charge generation layer CGL1 may be provided between the first light-emitting unit EU1 and the second light-emitting unit EU2, and a second charge generation layer CGL2 may be provided between the second light-emitting unit EU2 and the third light-emitting unit EU3. For example, the organic light-emitting diode (OLED) includes, in order, a stacked pixel electrode 511, a first light-emitting layer EML1, a first charge generation layer CGL1, a second light-emitting layer EML2, a second charge generation layer CGL2, a first light-emitting layer EML1, and a counter electrode 515. A first functional layer and a second functional layer may be included below and above the first light-emitting layer EML1, respectively. A first functional layer and a second functional layer may be included below and above the second light-emitting layer EML2, respectively. The first light-emitting layer EML1 may be a blue light-emitting layer, and the second light-emitting layer EML2 may be a yellow light-emitting layer.

[0319] In one embodiment, the organic light-emitting diode (OLED) further includes a third light-emitting layer EML3 and / or a fourth light-emitting layer EML4 in direct contact below and / or above the second light-emitting layer EML2, in addition to the second light-emitting unit EU2. Here, direct contact means that no other layers are disposed between the second light-emitting layer EML2 and the third light-emitting layer EML3 and / or between the second light-emitting layer EML2 and the fourth light-emitting layer EML4. The third light-emitting layer EML3 may be a red light-emitting layer, and the fourth light-emitting layer EML4 may be a green light-emitting layer.

[0320] For example, as shown in Figure 52C, an organic light-emitting diode (OLED) includes, in order, a stacked pixel electrode 511, a first light-emitting layer EML1, a first charge generation layer CGL1, a third light-emitting layer EML3, a second light-emitting layer EML2, a second charge generation layer CGL2, a first light-emitting layer EML1, and a counter electrode 515. As another example, as shown in Figure 52D, an organic light-emitting diode (OLED) includes, in order, a stacked pixel electrode 511, a first light-emitting layer EML1, a first charge generation layer CGL1, a third light-emitting layer EML3, a second light-emitting layer EML2, a fourth light-emitting layer EML4, a second charge generation layer CGL2, a first light-emitting layer EML1, and a counter electrode 515.

[0321] Figure 53A is a schematic cross-sectional view illustrating an example of the organic light-emitting diode shown in Figure 52C, and Figure 53B is a schematic cross-sectional view illustrating an example of the organic light-emitting diode shown in Figure 52D.

[0322] Referring to Figure 53A, the organic light-emitting diode (OLED) includes a first light-emitting unit EU1, a second light-emitting unit EU2, and a third light-emitting unit EU3 stacked in order. A first charge generation layer CGL1 may be provided between the first light-emitting unit EU1 and the second light-emitting unit EU2, and a second charge generation layer CGL2 may be provided between the second light-emitting unit EU2 and the third light-emitting unit EU3. The first charge generation layer CGL1 and the second charge generation layer CGL2 each include a negative charge generation layer nCGL and a positive charge generation layer pCGL, respectively.

[0323] The first light-emitting unit EU1 includes a blue light-emitting layer BEML. The first light-emitting unit EU1 may further include a hole injection layer HIL and a hole transport layer HTL between the pixel electrode 211 and the blue light-emitting layer BEML. In one embodiment, a p-doped layer may further be included between the hole injection layer HIL and the hole transport layer HTL. The p-doped layer can be formed by doping the hole injection layer (HIL) with a p-type dopant. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer BEML and the hole transport layer HTL. The blue light auxiliary layer can increase the light-emitting efficiency of the blue light-emitting layer BEML. The blue light auxiliary layer can increase the light-emitting efficiency of the blue light-emitting layer BEML by adjusting the hole charge balance. The electron blocking layer can prevent electron injection into the hole transport layer HTL. The buffer layer can compensate for the resonance distance corresponding to the wavelength of light emitted from the light-emitting layer.

[0324] The second light-emitting unit EU2 includes a yellow light-emitting layer YEML and a red light-emitting layer REML that is in direct contact with the yellow light-emitting layer YEML. The second light-emitting unit EU2 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the first charge generation layer CGL1 and the red light-emitting layer REML, and may further include an electron transport layer ETL between the yellow light-emitting layer YEML and the negative charge generation layer nCGL of the second charge generation layer CGL2.

[0325] The third light-emitting unit EU3 includes a blue light-emitting layer BEML. The third light-emitting unit EU3 may further include a hole transport layer HTL between the positive charge generation layer pCGL of the second charge generation layer CGL2 and the blue light-emitting layer BEML. The third light-emitting unit EU3 may further include an electron transport layer ETL and an electron injection layer EIL between the blue light-emitting layer BEML and the counter electrode 515. The electron transport layer ETL is monolayer or multilayer. In one embodiment, at least one of a blue light auxiliary layer, an electron blocking layer, and a buffer layer may further be included between the blue light-emitting layer BEML and the hole transport layer HTL. At least one of a hole blocking layer and a buffer layer may further be included between the blue light-emitting layer BEML and the electron transport layer ETL. The hole blocking layer prevents hole injection into the electron transport layer ETL.

[0326] The organic light-emitting diode (OLED) shown in Figure 53B differs from the OLED shown in Figure 53A in the stacked structure of the second light-emitting unit (EU2), but the rest of the configuration is the same. Referring to Figure 53B, the second light-emitting unit (EU2) includes a yellow light-emitting layer (YEML), a red light-emitting layer (REML) directly in contact with the yellow light-emitting layer (YEML) below the yellow light-emitting layer (YEML), and a green light-emitting layer (GEML) directly in contact with the yellow light-emitting layer (YEML) on top of the yellow light-emitting layer (YEML). The second light-emitting unit (EU2) may further include a hole transport layer (HTL) between the positive charge generation layer (pCGL) of the first charge generation layer (CGL1) and the red light-emitting layer (REML), and an electron transport layer (ETL) between the green light-emitting layer (GEML) and the negative charge generation layer (nCGL) of the second charge generation layer (CGL2).

[0327] Figure 54 is a schematic cross-sectional view showing the pixel structure of a display device according to one embodiment.

[0328] Referring to Figure 54, the display device includes pixels. The pixels include a first pixel PX1, a second pixel PX2, and a third pixel PX3. The first pixel PX1, the second pixel PX2, and the third pixel PX3 each include a pixel electrode 511, a counter electrode 515, and an intermediate layer 513m. In one embodiment, the first pixel PX1 may be a red pixel, the second pixel PX2 may be a green pixel, and the third pixel PX3 may be a blue pixel. Here, the pixels include an organic light-emitting diode (OLED) as a display element, and the OLED of each pixel may be electrically connected to the pixel circuit.

[0329] The pixel electrode 511 may be provided independently for each of the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0330] The intermediate layer 513m of each of the organic light-emitting diodes (OLEDs) of the first pixel PX1, second pixel PX2, and third pixel PX3 includes a first light-emitting unit EU1 and a second light-emitting unit EU2 stacked in order, and a charge generation layer CGL between the first light-emitting unit EU1 and the second light-emitting unit EU2. The charge generation layer CGL includes a negative charge generation layer nCGL and a positive charge generation layer pCGL. The charge generation layer CGL is a common layer formed continuously across the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0331] The first light-emitting unit EU1 of the first pixel PX1 includes a hole injection layer HIL, a hole transport layer HTL, a red light-emitting layer REML, and an electron transport layer ETL, which are sequentially stacked on the pixel electrode 5111. The first light-emitting unit EU1 of the second pixel PX2 includes a hole injection layer HIL, a hole transport layer HTL, a green light-emitting layer GEML, and an electron transport layer ETL, which are sequentially stacked on the pixel electrode 511. The first light-emitting unit EU1 of the third pixel PX3 includes a hole injection layer HIL, a hole transport layer HTL, a blue light-emitting layer BEML, and an electron transport layer ETL, which are sequentially stacked on the pixel electrode 511. The hole injection layer HIL, the hole transport layer HTL, and the electron transport layer ETL of the first light-emitting unit EU1 can each be a common layer formed continuously in the first pixel PX1, the second pixel PX2, and the third pixel PX3.

[0332] The second light-emitting unit EU2 of the first pixel PX1 includes a hole transport layer HTL, an auxiliary layer AXL, a red light-emitting layer REML, and an electron transport layer ETL, which are sequentially stacked on the charge generation layer CGL. The second light-emitting unit EU2 of the second pixel PX2 includes a hole transport layer HTL, a green light-emitting layer GEML, and an electron transport layer ETL, which are sequentially stacked on the charge generation layer CGL. The second light-emitting unit EU2 of the third pixel PX3 includes a hole transport layer HTL, a blue light-emitting layer BEML, and an electron transport layer ETL, which are sequentially stacked on the charge generation layer CGL. The hole transport layer HTL and the electron transport layer ETL of the second light-emitting unit EU2 may be common layers formed continuously in the first pixel PX1, the second pixel PX2, and the third pixel PX3. In one embodiment, in the second light-emitting unit EU2 of the first pixel PX1, the second pixel PX2, and the third pixel PX3, at least one of a hole blocking layer and a buffer layer may be further included between the light-emitting layer and the electron transport layer ETL.

[0333] The thicknesses H1 of the red light-emitting layer (REML), H2 of the green light-emitting layer (GEML), and H3 of the blue light-emitting layer (BEML) are determined by the resonance distance. The auxiliary layer AXL is a layer added to match the resonance distance and may contain resonance-enhancing material. For example, the auxiliary layer AXL contains the same material as the hole transport layer (HTL).

[0334] In Figure 54, the auxiliary layer AXL is provided only on the first pixel PX1, but the embodiments of the present invention are not limited to this. For example, the auxiliary layer AXL may be provided on at least one of the first pixel PX1, the second pixel PX2, and the third pixel PX3 in order to match the resonance distances of the first pixel PX1, the second pixel PX2, and the third pixel PX3, respectively.

[0335] The display device may further include a capping layer 517 positioned outside the counter electrode 515. The capping layer 517 plays a role in increasing the luminous efficiency through the principle of reinforced interference. This can improve the light extraction efficiency of the organic light-emitting diode (OLED), thereby improving the luminous efficiency of the OLED.

[0336] Thus, the present invention has been described by reference to the embodiments illustrated in the drawings, but these are merely illustrative, and those skilled in the art will understand that a wide variety of modifications and variations of embodiments are possible. Therefore, the true scope of technical protection of the present invention must be determined by the technical idea of ​​the attached claims.

Claims

1. First conductive wire and A first electrode is arranged on the first conductive wire and superimposed on the first conductive wire, A semiconductor layer disposed on the first electrode and superimposed on the first electrode, A second electrode is disposed on the semiconductor layer and superimposed on the first electrode, The third electrode is disposed on the second electrode, superimposed on the second electrode, and electrically connected to the semiconductor layer and the first electrode, A display device in which a region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

2. A fourth electrode is arranged on the same layer as the third electrode and is electrically connected to the second electrode, The display device according to claim 1, further comprising: a fifth electrode disposed on the fourth electrode, superimposed on the fourth electrode, and electrically connected to the third electrode.

3. The system further includes a sixth electrode arranged on the same layer as the first conductive wire, The first electrode, the second electrode, and the third electrode are superimposed on the sixth electrode. The display device according to claim 1, wherein the second electrode is electrically connected to the sixth electrode.

4. An opening is defined in the first electrode that overlaps with the sixth electrode. The display device according to claim 3, wherein the second electrode is electrically connected to the sixth electrode via the opening.

5. A seventh electrode is arranged on the same layer as the third electrode and is electrically connected to the second electrode, The display device according to claim 3, further comprising: an eighth electrode disposed on the seventh electrode, superimposed on the seventh electrode, and electrically connected to the third electrode.

6. The material further includes a second conductive wire spaced apart from the first conductive wire, The display device according to claim 1, wherein the voltage applied to the second conductive wire is different from the voltage applied to the first conductive wire.

7. The display device according to claim 6, wherein the first electrode is superimposed on the second conductive wire.

8. A first circuit region where the pixel circuit of the first pixel is located, and a second circuit region where the pixel circuit of the second pixel is located, A first conductive wire arranged in the first circuit region and the second circuit region, Arranged in the first circuit region and the second circuit region, A first electrode is arranged on the first conductive wire and superimposed on the first conductive wire, A semiconductor layer disposed on the first electrode and superimposed on the first electrode, A second electrode is disposed on the semiconductor layer and superimposed on the first electrode, The third electrode is disposed on the second electrode, superimposed on the second electrode, and electrically connected to the semiconductor layer and the first electrode, A display device in which a region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

9. Arranged in the first circuit region and the second circuit region, A fourth electrode is arranged on the same layer as the third electrode and is electrically connected to the second electrode, The display device according to claim 8, further comprising a fifth electrode disposed on the fourth electrode, superimposed on the fourth electrode, and electrically connected to the third electrode.

10. In the first circuit region, The system further includes a sixth electrode arranged on the same layer as the first conductive wire, The first electrode, the second electrode, and the third electrode are superimposed on the sixth electrode. The display device according to claim 8, wherein the second electrode is electrically connected to the sixth electrode.

11. In the first circuit region, An opening is defined in the first electrode that overlaps with the sixth electrode. The display device according to claim 10, wherein the second electrode is electrically connected to the sixth electrode through the opening.

12. Arranged in the first circuit region and the second circuit region, A seventh electrode is arranged on the same layer as the third electrode and is electrically connected to the second electrode, The display device according to claim 10, further comprising: an eighth electrode disposed on the seventh electrode, superimposed on the seventh electrode, and electrically connected to the third electrode.

13. A first circuit region where the pixel circuit of the first pixel is located, and a second circuit region where the pixel circuit of the second pixel is located, A first conductive wire arranged in the first circuit region and the second circuit region, The first circuit region and the second circuit region are provided with a second conductive wire, which is spaced apart from the first conductive wire and is on the same layer as the first conductive wire. Arranged in the first circuit region and the second circuit region, A first electrode is arranged on the first conductive wire and superimposed on the first conductive wire, A semiconductor layer disposed on the first electrode and superimposed on the first electrode, A second electrode is disposed on the semiconductor layer and superimposed on the first electrode, The third electrode is disposed on the second electrode, superimposed on the second electrode, and electrically connected to the semiconductor layer and the first electrode, A display device in which a region of the semiconductor layer superimposed on the second electrode superimposed on the first conductive wire.

14. Arranged in the first circuit region and the second circuit region, A fourth electrode is arranged on the same layer as the third electrode and is electrically connected to the second electrode, The display device according to claim 13, further comprising a fifth electrode disposed on the fourth electrode, superimposed on the fourth electrode, and electrically connected to the third electrode.

15. In the first circuit region, The system further includes a sixth electrode arranged on the same layer as the first conductive wire, The first electrode, the second electrode, and the third electrode are superimposed on the sixth electrode. The display device according to claim 13, wherein the second electrode is electrically connected to the sixth electrode.

16. In the first circuit region, An opening is defined in the first electrode that overlaps with the sixth electrode. The display device according to claim 15, wherein the second electrode is electrically connected to the sixth electrode through the opening.

17. Arranged in the first circuit region and the second circuit region, A seventh electrode is arranged on the same layer as the third electrode and is electrically connected to the second electrode, The display device according to claim 15, further comprising: an eighth electrode disposed on the seventh electrode, superimposed on the seventh electrode, and electrically connected to the third electrode.

18. It further includes a third circuit region in which the pixel circuit of the third pixel is arranged, The first conductive wire and the second conductive wire extend into the third circuit region, The first conductive wire includes a plurality of sub-conductive wires arranged at intervals from each other, The display device according to claim 17, wherein the region superimposed on the second electrode of the semiconductor layer arranged in the third circuit region is located between the subconducting wires.

19. The display device according to claim 13, wherein the first electrode is superimposed on the second conductive wire.

20. The display device according to claim 19, wherein the area over which the first electrode arranged in the first circuit region overlaps the second conductive wire and the area over which the first electrode arranged in the second circuit region overlaps the second conductive wire are different.

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