Display panels and display devices

Abstract

A display panel is provided. The display panel includes a display area, which includes a central area and two edge areas. The display panel includes a base substrate and a drive circuit layer. The drive circuit layer includes a plurality of pixel circuit units, a plurality of data write signal lines, a plurality of data lead lines, and a shield layer. The plurality of data write signal lines are located in the display area and include a first lead line section and a second lead line section, one end of the first lead line section being electrically connected to a data write signal line located in an edge area, and the other end of the first lead line section being electrically connected to one end of the second lead line section. The second lead line section is located in the central area. The orthographic projection of the second lead line section on the base substrate at least partially overlaps with the orthographic projection of the first pole of at least one drive transistor on the base substrate. The shield layer is configured to have a constant voltage signal. The shield layer includes at least one first shield pattern, the first shield pattern being located between the first pole of the drive transistor and the second lead line section.

Description

Technical Field

[0001] (Cross - reference to related applications) This application claims priority based on a Chinese patent application with application number 202310627900.8 filed on May 30, 2023 as the basic application, and all of its disclosure content is incorporated herein by reference.

[0002] This disclosure relates to the field of display technology, and particularly to display panels and display devices.

Background Art

[0003] OLED (Organic Light Emitting Diode) display devices have a series of advantages such as self - emission, fast response speed, high brightness, full viewing angle, and flexible display, so they have become one of the display devices with competitiveness and development prospects at present.

Summary of the Invention

Means for Solving the Problems

[0004] In one embodiment, a display panel is provided. The display panel includes a display area, the display area includes a central area and two edge areas, the central area being located between the two edge areas along a first direction. The display panel includes a base substrate and a drive circuit layer located on one side of the base substrate. The drive circuit layer includes a plurality of pixel circuit units, a plurality of data write signal lines, a plurality of data lead lines and a shield layer. The plurality of pixel circuit units are arranged in a plurality of rows and a plurality of columns within the display area. One pixel circuit unit includes at least one sub-pixel drive circuit, the sub-pixel drive circuit includes a drive transistor. The plurality of data write signal lines are located in the display area and are arranged along a first direction and extend along a second direction, the second direction intersecting the first direction, and one data write signal line is connected to a row of sub-pixel drive circuits. The data lead wire includes a first lead wire portion and a second lead wire portion, one end of the first lead wire portion is electrically connected to a data write signal line located in the edge region, and the other end of the first lead wire portion is electrically connected to one end of the second lead wire portion. The first lead wire portion extends along a first direction, the second lead wire portion extends along a second direction, and the second lead wire portion is located in the central region. The orthographic projection of the second lead wire portion on the base substrate at least partially overlaps with the orthographic projection of the first pole of at least one of the drive transistors on the base substrate. The shield layer is configured to have a constant voltage signal. The shield layer includes at least one first shield pattern, the first shield pattern is located between the first pole of the drive transistor and the second lead wire portion, and the orthographic projection of the first shield pattern on the base substrate, the orthographic projection of the first pole of the drive transistor on the base substrate, and the orthographic projection of the second lead wire portion on the base substrate overlap.

[0005] In some embodiments, the orthographic projection of the first shield pattern on the base substrate covers the orthographic projection of the first pole of the drive transistor on the base substrate.

[0006] In some embodiments, along the first direction, the second lead wire portion and the first shield pattern are located on the same side of the gate of the drive transistor.

[0007] In some embodiments, the sub-pixel driving circuit further includes a data writing transistor and a first reset transistor. The first pole of the data writing transistor is electrically connected to one of the data writing signal lines, and the second pole of the data writing transistor is electrically connected to the first pole of the driving transistor. The first pole of the first reset transistor is electrically connected to the gate of the driving transistor. Along the second direction, the first reset transistor in one of the sub-pixel driving circuits in one of the pixel circuit units is located on the side of the data writing transistor away from the driving transistor, and at least a portion of the first lead wire passing through the same pixel circuit unit is located on the side of the first reset transistor away from the data writing transistor.

[0008] In some embodiments, along the first direction, the first lead portion includes a body portion and a relief portion, the relief portion protruding from the body portion toward the side away from the drive transistor. Here, the relief portion is located on the side of the first reset transistor toward the side away from the data write transistor.

[0009] In some embodiments, the pixel circuit unit includes two sub-pixel drive circuits arranged along the first direction, the two sub-pixel drive circuits being a first sub-pixel drive circuit and a second sub-pixel drive circuit, respectively. The second lead portion corresponding to the first sub-pixel drive circuit and the second lead portion corresponding to the second sub-pixel drive circuit are adjacent, and the first shield pattern in the first sub-pixel drive circuit is provided adjacent to the first shield pattern in the second sub-pixel drive circuit.

[0010] In some embodiments, the first shield pattern in the first sub-pixel driving circuit is electrically connected to the first shield pattern in the second sub-pixel driving circuit, and the first shield pattern in the first sub-pixel driving circuit and the first shield pattern in the second sub-pixel driving circuit are provided on the same layer.

[0011] In some embodiments, the first sub-pixel driving circuit and the second sub-pixel driving circuit are symmetrical with respect to the first direction.

[0012] In some embodiments, the orthographic projection of the first lead wire portion on the base substrate partially overlaps with the orthographic projection of the data writing signal line on the base substrate. The shielding layer further includes at least one second shielding pattern, the second shielding pattern located between the first lead wire portion and the data writing signal line, and the orthographic projection of the second shielding pattern on the base substrate, the orthographic projection of the first lead wire portion on the base substrate, and the orthographic projection of the data writing signal line on the base substrate all overlap.

[0013] In some embodiments, the drive circuit layer further includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first wiring metal layer, and a second wiring metal layer laminated on the base substrate. The first pole of the drive transistor is located in the first semiconductor layer, the first lead wire portion is located in the first wiring metal layer, and the second lead wire portion is located in the second wiring metal layer. The first shield pattern is located in the second gate metal layer and / or the first wiring metal layer.

[0014] In some embodiments, the drive circuit layer further includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first wiring metal layer, a second wiring metal layer, and a third wiring metal layer laminated on the base substrate. The first pole of the drive transistor is located in the first semiconductor layer, the first lead wire portion is located in the first wiring metal layer, and the second lead wire portion is located in the third wiring metal layer. The first shield pattern is located in at least one of the second gate metal layer, the first wiring metal layer, and the second wiring metal layer.

[0015] In some embodiments, the drive circuit layer further includes a third gate metal layer, the third gate metal layer located between the second gate metal layer and the first wiring metal layer. At least a portion of the first shield pattern is located on the third gate metal layer.

[0016] In some embodiments, the pixel circuit unit further includes a first power signal line located in the second wiring metal layer, the first power signal line being configured to supply a constant voltage power signal to the pixel drive circuit, wherein the first power signal line is electrically connected to the shield layer.

[0017] In some embodiments, the sub-pixel driving circuit further includes a storage capacitor, the first electrode plate of the storage capacitor being electrically connected to the gate of the driving transistor, and the second electrode plate of the storage capacitor being electrically connected to a first power signal line. The first electrode plate of the storage capacitor is located in the first gate metal layer, and the first electrode plate of the storage capacitor further functions as the gate of the driving transistor, and the second electrode plate of the storage capacitor is located in the second gate metal layer.

[0018] In some embodiments, the second electrode plate of the storage capacitance includes a first sub-part, the first sub-part, the first pole of the drive transistor and the second lead wire portion overlap along a direction perpendicular to the base substrate, and the first sub-part further functions as the first shield pattern.

[0019] In some embodiments, the first wiring metal layer further includes a first connection portion used to electrically connect the second pole of the storage capacitance to the first power signal line, and the first connection portion further functions as the first shield pattern.

[0020] In some embodiments, the one subpixel driving circuit further includes a first light-emitting control transistor, the first pole of the first light-emitting control transistor being electrically connected to the first pole of the driving transistor, and the second pole of the first light-emitting control transistor being electrically connected to a first power signal line. The first wiring metal layer further includes a first splice, the first splice being used to electrically connect the second pole of the first light-emitting control transistor to the first power signal line, and the first splice further functions as the first shield pattern.

[0021] In some embodiments, the display panel further includes a bonding area, the bonding area is located on one side of the display area, the bonding area includes a connecting lead wire, and the other end of the data lead wire is electrically connected to the connecting lead wire.

[0022] In another embodiment, a display device is provided. The display device includes a display panel as described in any of the embodiments described above. [Brief explanation of the drawing]

[0023] To provide a clearer explanation of the technical solutions presented in this disclosure, the following is a brief introduction to the drawings used in some embodiments of this disclosure. Clearly, the drawings in the following description represent only a few embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these. Furthermore, the drawings in the following description can be considered schematic diagrams and do not limit the actual dimensions of the products, the actual processes of the methods, the actual timing of the signals, etc., relating to the embodiments of this disclosure. [Figure 1] This is a structural diagram of a display panel according to several embodiments. [Figure 2]It is a structural diagram of a display panel according to some embodiments. [Figure 3] It is a cross-sectional view of a display panel according to some embodiments. [Figure 4] It is a structural diagram of a display panel according to some other embodiments. [Figure 5] It is a membrane layer structural diagram of a pixel driving unit according to some embodiments. [Figure 6] It is a circuit diagram of a sub-pixel driving circuit according to some embodiments. [Figure 7] It is a circuit diagram of a sub-pixel driving circuit according to some other embodiments. [Figure 8] It is a timing chart of a sub-pixel driving circuit according to some embodiments. [Figure 9] It is a membrane layer diagram of the first semiconductor layer in FIG. 5. [Figure 10] It is a membrane layer diagram of the first gate metal layer in FIG. 5. [Figure 11] It is a membrane layer diagram of the first semiconductor layer and the first gate metal layer in FIG. 5. [Figure 12] It is a membrane layer diagram of the first wiring metal layer in FIG. 5. [Figure 13] It is a membrane layer diagram of the second wiring metal layer in FIG. 5. [Figure 14] It is a membrane layer diagram of the first semiconductor layer, the first gate metal layer, the first wiring metal layer and the second wiring metal layer in FIG. 5. [Figure 15] It is a membrane layer structural diagram of a pixel driving unit according to some other embodiments. [Figure 16] It is a membrane layer structural diagram of a pixel driving unit according to some further other embodiments. [Figure 17] It is a membrane layer diagram of the first semiconductor layer in FIG. 15. [Figure 18] It is a membrane layer diagram of the first gate metal layer in FIG. 15. [Figure 19] It is a membrane layer diagram of the first semiconductor layer and the first gate metal layer in FIG. 15. [Figure 20] It is a membrane layer diagram of the second gate metal layer in FIG. 15. [Figure 21] Figure 15 shows the film layer diagram of the first wiring metal layer. [Figure 22] Figure 15 shows the film layer diagram of the second wiring metal layer. [Figure 23] This is a film layer diagram of the second gate metal layer in a sub-pixel driving circuit according to several embodiments. [Figure 24] This is a film layer diagram of the second gate metal layer in a sub-pixel driving circuit according to several other embodiments. [Figure 25] Furthermore, here are diagrams illustrating the film layer structure of a pixel drive unit according to several other embodiments. [Figure 26] This is a film layer diagram of the second semiconductor layer in Figure 15. [Figure 27] Figure 15 shows the film layer diagram of the third gate metal layer. [Figure 28] Figure 15 shows the film layers of the second gate metal layer, the second semiconductor layer, and the third gate metal layer. [Modes for carrying out the invention]

[0024] Hereinafter, several embodiments of this disclosure will be clearly and completely described with reference to the drawings. Of course, the embodiments described herein are only a selection of, and not all, embodiments of this disclosure. All other embodiments that a person skilled in the art could conceive of based on the embodiments of this disclosure are included within the scope of this disclosure.

[0025] Unless otherwise indicated in the context, the term “comprise” and other forms, such as the third-person singular “comprises” and the present participle “comprising,” should be interpreted in an open, comprehensive sense, i.e., “including, but not limited to.” In the description of the specification, terms such as “one embodiment,” “some embodiments,” “exemplary embodiments,” “example,” “specific example,” or “some examples” are intended to indicate that certain features, structures, materials, or properties related to this embodiment or such example are included in at least one embodiment or example of the present disclosure. The general expressions of the above terms do not necessarily refer to the same embodiment or example. Furthermore, any specific features, structures, materials, or properties described may be included in any one or more embodiments or examples in any suitable manner.

[0026] In the following, the terms “first” and “second” are merely for illustrative purposes and should not be understood as indicating or implying relative importance or the quantity of the indicated technical feature. Accordingly, the features defined as “first” and “second” may explicitly or implicitly include one or more such features. As used herein and in the appended claims, the singular forms “one” and “the said” also include multiple items unless otherwise specified herein. In the description of the embodiments of this disclosure, “multiple” means two or more unless otherwise specified.

[0027] In describing some embodiments, the terms “coupling,” “connection,” and related expressions may be used. The term “connection” should be interpreted broadly; for example, “connection” may be a fixed connection, a detachable connection, a jointly formed connection, a direct connection, or an indirect connection via an intermediate medium. The term “coupling” indicates, for example, that two or more parts have direct physical or electrical contact. The term “coupling” or “communicatively coupled” may also refer to cases where two or more parts do not have direct contact with each other but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to those described herein.

[0028] "At least one of A, B, and C" is synonymous with "at least one of A, B, or C," and both include the following combinations of A, B, and C: A only, B only, C only, a combination of A and B, a combination of A and C, a combination of B and C, and a combination of A, B, and C.

[0029] "A and / or B" includes three combinations: A only, B only, and a combination of A and B.

[0030] Where used herein, the term "if" may be interpreted, depending on the context, as "when," "on the occasion of," "in response to having determined that," or "in response to having detected." Similarly, wherever the context, the phrase "if it is determined that" or "if [the described condition or event] is detected" may be interpreted, depending on the context, as "when it is determined that," "in response to having determined that," "when [the described condition or event] is detected," or "in response to having detected [the described condition or event]."

[0031] In this specification, the use of “to apply to…” or “to be arranged to…” means open and inclusive language and does not exclude devices to be applied to or arranged to perform additional tasks or steps.

[0032] Furthermore, the use of "based on" has an open and inclusive meaning, because in practice, a process, step, calculation, or other action performed "based on" one or more of the aforementioned conditions or values ​​may also be based on additional conditions other than the aforementioned conditions, or on values ​​exceeding the aforementioned values.

[0033] As used herein, “about,” “approximately,” or “approximately” includes the stated value and the mean value within an acceptable range of deviation of a particular value, where the acceptable range of deviation is determined taking into account the errors associated with the measurement and the measurement of a particular quantity (i.e., limitations of the measurement system) as considered by those skilled in the art.

[0034] As used herein, “parallel,” “perpendicular,” and “equal” include the conditions described and conditions that approximate them, the range of these similar conditions being within an acceptable range of deviation, the acceptable range of deviation being determined in consideration of the errors (i.e., limitations of the measuring system) associated with the measurement and the measurement of a particular quantity as considered by a person skilled in the art. For example, “parallel” includes true parallel and approximate parallel, where the acceptable range of deviation for approximate parallel is, for example, a deviation of 5° or less; and “perpendicular” includes true perpendicular and approximate perpendicular, where the acceptable range of deviation for approximate perpendicular may be, for example, a deviation of 5° or less. “Equal” includes absolutely equal and approximately equal, where within the acceptable range of deviation for approximately equal, for example, the difference between the two equals is 5% or less of either.

[0035] When a layer or element is mentioned as being on another layer or substrate, it is understood that the layer or element may be directly located on the other layer or substrate, or there may be an intermediate layer between the layer or element and the other layer or substrate.

[0036] This specification describes exemplary embodiments with reference to cross-sectional and / or plan views, which are idealized, illustrative drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape from the drawings may be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, exemplary embodiments should not be interpreted as being limited to the shapes of the regions illustrated herein, and may include deviations in shape due to manufacturing, etc. For example, an etching region shown as a rectangle typically has curved characteristics. Therefore, the regions shown in the drawings are essentially illustrative, and their shapes are not intended to represent the actual shapes of the regions in the apparatus, nor are they intended to limit the scope of the exemplary embodiments.

[0037] In the circuit structures provided by the embodiments of this disclosure, the first pole of each transistor employed is either the source or the drain, and the second pole of each transistor is the other of the source or the drain. Since the source and drain of a transistor can be structurally symmetrical, there may be no structural distinction between the source and the drain. In other words, the first and second poles of a transistor in the embodiments of this disclosure may be structurally indistinguishable.

[0038] For example, if the transistor is a P-type transistor, the first pole of the transistor is the source pole, and the second pole is the drain pole.

[0039] For example, if the transistor is an N-type transistor, the first pole of the transistor is the drain pole, and the second pole is the source pole.

[0040] In the circuit structures provided by the embodiments of this disclosure, the nodes such as the first node, second node, etc., do not represent actual existing components, but rather represent the junction points of the relevant connections in the circuit diagram. In other words, these nodes are nodes obtained by equating the junction points of the relevant connections in the circuit diagram.

[0041] Figure 1 is a structural diagram of a display device according to several embodiments. Referring to Figure 1, several embodiments of the present disclosure provide a display device 200, which includes a display panel 100.

[0042] Exemplary, the display device 200 further includes a frame and other electronic components, etc.

[0043] For example, the display device 200 may be an electroluminescent display device or a photoexcited light-emitting display device. If the display device is an electroluminescent display device, the electroluminescent display device may be an organic light-emitting diode (OLED) or a quantum dot light-emitting diode (QLED). If the display device is a photoexcited light-emitting display device, the photoexcited light-emitting display device may be a quantum dot photoexcited light-emitting display device.

[0044] Exemplary, the display device 200 described above may display moving images (e.g., video) or still images (e.g., still images), may display text or graphics, and may be any device. More specifically, it is expected that the described embodiments may be implemented in or associated with various electronic devices. The various electronic devices mentioned above include, but are not limited to, mobile phones, wireless devices, personal digital assistants (PDAs), handheld or portable computers, GPS receivers / navigation devices, cameras, MP4 video players, video cameras, game consoles, watches, clocks, calculators, television monitors, flat panel displays, computer monitors, automobile displays (e.g., odometer displays), navigators, cockpit controllers and / or displays, camera view displays (e.g., displays for rear-view cameras in vehicles), electrophotography, electronic signs or indicators, projectors, architectural structures, and packaging and aesthetic structures (e.g., displays for displaying images of jewelry).

[0045] Figure 2 is a structural diagram of a display panel according to several embodiments, and Figure 3 is a cross-sectional view of a display panel according to several embodiments.

[0046] Referring together to Figures 2 and 3, some embodiments of the present disclosure provide a display panel 100, which includes a display area (also known as the Active Area, AA area, or effective display area) AA. The display area AA includes a central area AA1 and two edge areas AA2, with the central area AA1 located between the two edge areas AA2 along a first direction X.

[0047] In some examples, along the first direction X, the widths of the two edge regions AA2 of the display region AA are the same or approximately the same.

[0048] The display panel 100 includes a base substrate 10 and a drive circuit layer 20 located on one side of the base substrate 10.

[0049] In some examples, the base substrate 10 may be a flexible base. For example, the material of the base substrate 10 may be an organic material. For instance, the material of the base substrate 10 may be polyimide (PI), polycarbonate (PC), or polyvinyl chloride (PVC).

[0050] In some other examples, the base substrate 10 may be a rigid base. For example, the rigid substrate may be glass-based or PMMA (Polymethyl methacrylate)-based, etc.

[0051] The drive circuit layer 20 includes multiple pixel circuit units P, multiple data writing signal lines 21, and multiple data lead lines 22.

[0052] Here, multiple pixel circuit units P are arranged in multiple rows and multiple columns within the display area AA. Each pixel circuit unit P includes at least one sub-pixel driving circuit Q.

[0053] In some examples, one pixel circuit unit P may contain one sub-pixel driver circuit Q. In some other examples, it is understood that one pixel circuit unit P may contain multiple sub-pixel driver circuits Q. For example, one pixel circuit unit P may contain two sub-pixel driver circuits Q. Here, Figure 2 schematically shows an example in which one pixel circuit unit P contains one sub-pixel driver circuit Q.

[0054] For the sake of explanation, in this disclosure, we will describe an example in which the above-mentioned plurality of pixel circuit units P are arranged in a matrix format. In this case, since each pixel circuit unit P includes at least one sub-pixel driving circuit Q, we will also describe an example in which the plurality of sub-pixel driving circuits Q in the display panel 100 are arranged in a matrix format.

[0055] In this case, a sub-pixel driving circuit P arranged in a row along the first direction X is referred to as a sub-pixel driving circuit row, and a sub-pixel driving circuit P arranged in a row along the second direction Y is referred to as a sub-pixel driving circuit column.

[0056] In some embodiments, referring again to Figure 3, the display panel 100 may further include a plurality of light-emitting units O located on the side of the drive circuit layer 20 away from the base substrate 10, and a plurality of sub-pixel drive circuits Q are electrically connected to the plurality of light-emitting units O.

[0057] In some examples, the multiple sub-pixel driving circuits Q and multiple light-emitting units O described above can be electrically connected in a one-to-one correspondence. In some other examples, one sub-pixel driving circuit Q can be coupled with multiple light-emitting units O, or multiple sub-pixel driving circuits Q can be coupled with one light-emitting unit O.

[0058] Hereinafter, this disclosure schematically describes the structure of the display panel 100, using an example in which one sub-pixel driving circuit Q is coupled with one light-emitting unit O.

[0059] In the display panel 100, the sub-pixel driving circuit Q can generate a driving signal by being adjusted based on multiple different types of signal lines. Each light-emitting unit O can emit light through the driving action of the driving signal generated by the corresponding sub-pixel driving circuit Q, and the light emitted by multiple light-emitting units O cooperates with each other to realize the display function of the display panel 100.

[0060] In some examples, the light-emitting unit O includes an anode layer, a light-emitting layer, and a cathode layer, which are stacked in order. In some examples, an electron transport layer may be further placed between the cathode layer and the light-emitting layer, and a hole transport layer may be further placed between the anode layer and the light-emitting layer. Exemplarily, the light-emitting unit O described above may be, but is not limited to, an OLED light-emitting unit. Embodiments of this disclosure do not limit the type of light-emitting unit; that is, the light-emitting unit O may be any other light-emitting unit (e.g., a light-emitting unit that emits light by discharge), as long as they emit light and can display a screen on the display panel 100.

[0061] In some examples, the display area AA includes multiple subpixel areas, each subpixel area containing a subpixel driving circuit Q and a light-emitting unit O electrically connected to the subpixel driving circuit Q. Based on this, the display panel 100 can display a predetermined image in the display area AA using the light emitted by the light-emitting units O within the multiple subpixel areas. Specifically, the multiple subpixel areas may include multiple subpixel areas with different emission colors.

[0062] Exemplary, the multiple subpixel regions include a first subpixel region, a second subpixel region, and a third subpixel region. Each of the first, second, and third subpixel regions emits primary color light; for example, the first subpixel region may emit red light, the second subpixel region may emit green light, and the third subpixel region may emit blue light.

[0063] Here, among the multiple different types of signal lines, there is a data write signal line 21, which is configured to provide a data write signal to the sub-pixel drive circuit Q. Here, the data write signal may be a type of pulse signal; that is, the data write signal is a non-constant signal that is constantly changing.

[0064] Multiple data write signal lines 21 are located within the drive circuit layer 20, arranged along a first direction X and extending along a second direction Y. Multiple data write signal lines 21 are located in the display area AA, and one data write signal line 21 is connected to a row of sub-pixel drive circuits Q. Here, the first direction X and the second direction Y intersect.

[0065] In some cases, the first direction X and the second direction Y may be perpendicular. In some other cases, it is understood that the first direction X and the second direction Y intersect to form a first included angle, which may be acute or obtuse.

[0066] Here, some of the multiple data write signal lines 21 are located within one edge region AA2, some of the other data write signal lines 21 are located within another edge region AA2, and some of the other data write signal lines 21 are located within the central region AA1.

[0067] In some examples, the number of data write signal lines 21 in the two edge regions AA2 may be the same. In some other examples, the number of data write signal lines 21 in the two edge regions AA2 may be different.

[0068] In some examples, the number of data write signal lines 21 in one edge region AA2 may be the same as the number of data write signal lines 21 in the central region AA1. In some other examples, the number of data write signal lines 21 in one edge region AA2 may be different from the number of data write signal lines 21 in the central region AA1.

[0069] The display panel 100 employs FIAA (Fanout In AA) technology, and by arranging the data lead lines 22 within the display area AA, it is advantageous for achieving a narrow bezel for the display panel 100.

[0070] The data lead line 22 includes a first lead line section 221 and a second lead line section 222. The second lead line section 222 extends along the second direction Y and is located in the central region AA1. The first lead line section 221 extends along the first direction X, with one end of the first lead line section 221 located in the edge region AA2 and the other end of the first lead line section 221 located in the central region AA1.

[0071] Based on this, one end of the first lead wire section 221 may be electrically connected to a data writing signal line 21 located in the edge region AA2, and the other end of the first lead wire section 221 may be electrically connected to one end of the second lead wire section 222 located in the central region AA1. This enables switching the data writing signal line 21 in the edge region AA2 to the central region AA1, which is advantageous for narrowing the bezel of the display panel 100.

[0072] Figure 4 shows the structure of a display panel according to several other embodiments.

[0073] In some embodiments, referring to Figure 4, the display panel 100 may further include a bonding area BB. The bonding area BB is located on one side of the display area AA and includes a connecting lead wire 40, the other end of the data lead wire 22 is electrically connected to the connecting lead wire 40.

[0074] In some cases, the bonding region BB may include a drive chip (integrated circuit, abbreviated as IC).

[0075] One end of the connection lead wire 40 within the bonding region BB is electrically connected to the drive chip IC, the other end of the connection lead wire 40 is electrically connected to the other end of the data lead wire 22, and one end of the data lead wire 22 is electrically connected to the data write signal line 21. Based on this, the data write signal provided by the drive chip IC is input to the data write signal line 21 via the connection lead wire 40 and the data lead wire 22 in that order, and the data write signal line 21 can transmit the data write signal to the sub-pixel drive circuit Q.

[0076] In some examples, the data write signal line 21 located within the central region AA1 may be electrically connected to the connection lead line 40 of the bonding region BB via the data lead line 22. In some other embodiments, it is understood that the data write signal line 21 located within the central region AA1 may be directly electrically connected to the connection lead line 40 of the bonding region BB. Here, Figure 4 schematically shows an example in which the data write signal line 21 located within the central region AA1 can be directly electrically connected to the connection lead line 40 of the bonding region BB.

[0077] Based on this, the signal lines that need to be electrically connected to the bonding area BB (data lead lines 22 electrically connected to the data writing signal line 21 in the edge area AA2, and data writing signal line 21 in the central area AA1) can all be concentrated within the display area AA at the location corresponding to the drive chip IC, which is advantageous for narrowing the bezel.

[0078] However, through their investigation, the inventors of this disclosure, referring back to Figure 2 or Figure 5, discovered that by laying out the data lead lines 22 within the display area AA, the orthographic projection of the data lead lines 22 on the base substrate 10 and the orthographic projection of the sub-pixel driving circuit Q on the base substrate 10 overlap.

[0079] Based on this, parasitic capacitance occurs between the data lead line 22 and the sub-pixel drive circuit Q. Due to capacitive coupling, when the data lead line 22 transmits a data write signal to the data write signal line 21, and a jump occurs in the data write signal, it affects the potential of the sub-pixel drive circuit Q. As a result, the drive signal output by the sub-pixel drive circuit Q to the light-emitting unit O is affected, which in turn affects the brightness of the light-emitting unit O, and the brightness uniformity of the display panel 100 decreases.

[0080] Figure 5 is a film layer structure diagram of a pixel driving unit according to several embodiments. Here, Figure 5 schematically shows an example in which one pixel driving unit P includes one sub-pixel driving circuit Q. In other words, Figure 5 can also be understood as a film layer structure diagram of one sub-pixel driving circuit according to several embodiments.

[0081] With respect to the display panel 100 provided by some embodiments of the present disclosure, and continuing to refer to Figure 5, the drive circuit layer 20 in the display panel 100 further includes a shield layer 30, the shield layer 30 configured to have a constant voltage signal. The shield layer 30 includes at least one first shield pattern 31. The sub-pixel drive circuit Q also includes a drive transistor T1.

[0082] If the orthographic projection of the second lead wire portion 222 on the base substrate 10 and the orthographic projection of the first pole a1 of at least one drive transistor T1 on the base substrate 10 overlap at least partially, the first shield pattern 31 is placed between the first pole a1 of the drive transistor T1 and the second lead wire portion 222, and the first shield pattern 31 is configured to have a constant voltage signal.

[0083] Specifically, the first shield pattern 31 is provided in the film layer between the film layer where the second lead wire portion 222 is located and the film layer where the first pole a1 of the drive transistor T1 is located, and is arranged so that the orthographic projection of the first shield pattern 31 on the base substrate 10, the orthographic projection of the second lead wire portion 222 on the base substrate 10, and the orthographic projection of at least one first pole a1 of the drive transistor T1 on the base substrate 10 overlap.

[0084] Based on this, the first shield pattern 31 can be used to separate the second lead wire section 222 from the first pole a1 of the drive transistor T1. Furthermore, since the first shield pattern 31 is configured to have a constant voltage signal, when a jump occurs in the data writing signal transmitted by the second lead wire section 222, the first shield pattern 31 can improve the effect on the potential of the first pole a1 of the drive transistor T1. As a result, the stability of the drive transistor T1 in the sub-pixel drive circuit Q is improved, which is advantageous in improving the brightness uniformity of the display panel 100.

[0085] Note that Figure 5 above shows an example where the first pole a1 of the drive transistor T1 is located on the right side of the drive transistor T1. It is understood that in some other examples, the first pole a1 of the drive transistor T1 can be located on the left side of the drive transistor T1.

[0086] In summary, the display panel 100 provided by some embodiments of this disclosure can easily achieve a narrow bezel by employing FIAA technology to lay out the data lead lines 22 within the display area AA of the display panel 100. Furthermore, the drive circuit layer 20 within the display panel 100 further includes a shield layer 30, the first shield pattern 31 is configured to have a constant voltage signal, and the first shield pattern 31 is positioned between the first pole a1 of the drive transistor T1 and the second lead line portion 222. By utilizing the first shield pattern 31 in the shield layer 30 to separate the first pole a1 of the drive transistor T1 and the second lead line portion 222 of the data lead line 22, the influence on the potential of the first pole a1 of the drive transistor T1 when a jump occurs in the data writing signal transmitted by the second lead line portion 222 to the data writing signal line 21 can be improved by the first shield pattern 31. As a result, the stability of the drive transistor T1 in the sub-pixel drive circuit Q is improved, and the brightness uniformity of the display panel 100 is improved. In other words, the display panel 100 provided by some embodiments of this disclosure can achieve a narrow bezel for the display panel 100 while simultaneously ensuring uniform brightness of the display panel 100.

[0087] Here, the first pole a1 of the drive transistor T1 can be the source pole of the drive transistor T1. Alternatively, the first pole a1 of the drive transistor T1 can be the drain pole of the drive transistor T1. Below, we will explain using an example where the first pole a1 of the drive transistor T1 is the source pole of the drive transistor T1.

[0088] In some embodiments, referring again to Figure 5, the first shield pattern 31 is positioned between the second lead portion 222 of the data lead wire 22 and the first pole a1 of the drive transistor T1, that is, positioned so that the orthographic projection of the first shield pattern 31 on the base substrate 10 and the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10 overlap at least partially.

[0089] Based on this, parasitic capacitance is generated between the first shield pattern 31 and the first pole a1 of the drive transistor T1. However, due to capacitive coupling, the first shield pattern 31, which has a constant voltage signal, is advantageous in stabilizing the potential of the first pole a1 of the drive transistor T1. As a result, the stability of the drive transistor T1 in the sub-pixel drive circuit Q is improved, and the brightness uniformity of the display panel 100 is improved.

[0090] In some examples, referring again to Figure 5, the orthographic projection of the first shield pattern 31 on the base substrate 10 and the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10 may be arranged to partially overlap. Exemplarily, the orthographic projection of the first shield pattern 31 on the base substrate 10 and the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10 within the overlapping region may be arranged to partially overlap. Here, the overlapping region is the region where the orthographic projection of the second lead wire portion 222 on the base substrate 10 and the orthographic projection of at least one first pole a1 of the drive transistor T1 on the base substrate 10 overlap.

[0091] Based on this, the display panel 100 can separate the first pole a1 of the drive transistor T1 from the second lead portion 222 of the data lead line 22 by utilizing the first shielding pattern 31 in the shielding layer 30. The first shielding pattern 31 can improve the influence on the potential of the first pole a1 of the drive transistor T1 when a jump occurs in the data writing signal transmitted by the second lead portion 222 to the data writing signal line 21. As a result, the stability of the drive transistor T1 in the sub-pixel drive circuit Q is improved, and the brightness uniformity of the display panel 100 is improved.

[0092] In some other examples, continuing to refer to Figure 5, assuming that the first shield pattern 31 is placed between the second lead portion 222 of the data lead wire 22 and the first pole a1 of the drive transistor T1, the orthographic projection of the first shield pattern 31 on the base substrate 10 may be further positioned to cover the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10.

[0093] Here, the statement that the orthographic projection of the first shield pattern 31 on the base substrate 10 covers the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10 includes the following two cases:

[0094] Case 1: The orthographic projection of the first shield pattern 31 on the base substrate 10 overlaps with the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10. That is, the size of the first shield pattern 31 and the size of the first pole a1 of the drive transistor T1 are approximately the same, so that the first shield pattern 31 can effectively shield the first pole a1 of the drive transistor T1, and prevent any influence on the potential of the first pole a1 of the drive transistor T1 when a jump occurs in the data writing signal transmitted by the second lead wire portion 222 to the data writing signal line 21. As a result, the stability of the drive transistor T1 in the sub-pixel drive circuit Q is improved, and the brightness uniformity of the display panel 100 is improved.

[0095] In the second case, the outer edge of the orthographic projection of the first shield pattern 31 on the base substrate 10 surrounds the outer edge of the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10. That is, the size of the first shield pattern 31 is larger than the size of the first pole a1 of the drive transistor T1, so that the first shield pattern 31 can shield the first pole a1 of the drive transistor T1 over a wider area, and when a jump occurs in the data writing signal transmitted by the second lead wire portion 222 to the data writing signal line 21, it is possible to prevent the effect on the potential of the first pole a1 of the drive transistor T1. As a result, the stability of the drive transistor T1 in the sub-pixel drive circuit Q is improved and the brightness uniformity of the display panel 100 is improved. However, the embodiments of this disclosure are not limited thereto.

[0096] Figure 6 is a circuit diagram of a sub-pixel driving circuit according to several embodiments.

[0097] In some embodiments, with reference to Figures 5 and 6, the drive circuit layer 20 in the display panel 100 includes multiple metal layers. Within the multiple metal layers are a sub-pixel drive circuit Q and multiple different types of signal lines. Here, the multiple different types of signal lines may include, in addition to the data write signal line 21 and data lead line 22, a first power signal line VDD, a first scan signal line G1, a second scan signal line G2, a first reset signal line R1, a second reset signal line R2, a first initialization signal line V1, a second initialization signal line V2, and an enable signal line E1, etc. The above-mentioned multiple signal lines are electrically connected to the sub-pixel drive circuit Q, thereby providing the necessary signals to the sub-pixel drive circuit Q.

[0098] The multiple metal layers include a first semiconductor layer POLY1, a first gate metal layer Gate1, a first wiring metal layer SD1, and a second wiring metal layer SD2, which are stacked on the base substrate 10. Each of the multiple signal lines is located within the multiple metal layers, and the specific arrangement method will be described in detail below.

[0099] Here, there are several types of sub-pixel driver circuit Q structures, which can be selected and configured based on actual needs. For example, sub-pixel driver circuit structures may include "2T1C", "6T1C", "7T1C", "6T2C", "7T2C", or "8T1C", etc. Here, "T" represents a thin-film transistor, the number before "T" indicates the number of thin-film transistors, "C" represents a storage capacitor C, and the number before "C" indicates the number of storage capacitors C.

[0100] In other words, the sub-pixel driving circuit Q may include multiple transistors, but in the above embodiment, only the case in which the sub-pixel driving circuit Q includes a driving transistor T1 was described.

[0101] The gate c1 of the drive transistor T1 is electrically connected to the first node N1, the first pole a1 of the drive transistor T1 is electrically connected to the second node N2, and the second pole b1 of the drive transistor T1 is electrically connected to the third node N3.

[0102] The drive transistor T1 is configured to transmit the voltage from the second node N2 to the third node N3 under the control of the voltage at the first node N1.

[0103] Furthermore, the sub-pixel driving circuit Q may include other transistors, and the sub-pixel driving circuit of "7T1C" will be used as an example in the following explanation.

[0104] The sub-pixel driving circuit Q further includes a writing sub-circuit 101, a compensation sub-circuit 102, a first reset sub-circuit 103, a light emission control sub-circuit 104, and a second reset sub-circuit 105.

[0105] The writing subcircuit 101 is coupled to the first scan signal line G1, the data writing signal line 21, and the second node N2. During the writing phase, the writing subcircuit 101 is configured to transmit the data signal received on the data writing signal line 21 to the second node under the control of the first scan signal received from the first scan signal line G1.

[0106] In some examples, the writing subcircuit 101 includes a data writing transistor T2. The gate c2 of the data writing transistor T2 is electrically connected to the first scan signal line G1, the first pole a2 of the data writing transistor T2 is electrically connected to the data writing signal line 21, and the second pole b2 of the data writing transistor T2 is electrically connected to the second node N2.

[0107] The compensation subcircuit 102 is coupled to the second scan signal line G2, the third node N3, and the first node N1. During the writing phase, the compensation subcircuit 102 is configured to transmit the voltage of the third node N3 to the first node N1 under the control of the second scan signal received from the second scan signal line G2.

[0108] In some examples, the compensation subcircuit 102 includes a compensation transistor T3. The gate c3 of the compensation transistor T3 is electrically connected to the second scan signal line G2, the first pole a3 of the compensation transistor T3 is electrically connected to the third node N3, and the second pole b3 of the compensation transistor T3 is electrically connected to the first node N1.

[0109] The first reset subcircuit 103 is configured to, during the initialization phase, transmit the first initialization signal received on the first initialization signal line V1 to the first node N1 under the control of the first reset signal received from the first reset signal line R1, thereby resetting the first node N1. This is advantageous for ensuring voltage stability at the first node N1.

[0110] In some examples, the first reset subcircuit 103 includes a first reset transistor T4. The gate c4 of the first reset transistor T4 is electrically connected to the first reset signal line R1, the first pole a4 of the first reset transistor T4 is electrically connected to the first node N1, and the second pole b4 of the first reset transistor T4 is electrically connected to the first initialization signal line V1.

[0111] The light emission control subcircuit 104 is coupled to the enable signal line E1, the first power supply signal line VDD, the second node N2, and the fourth node N4. The light emission control subcircuit 104 is configured to transmit a drive signal to the fourth node N4 in cooperation with the drive transistor T1, under the control of the enable signal from the enable signal line E1. Here, the fourth node N4 is electrically connected to the light emission unit O. That is, the light emission control subcircuit 104 is configured to transmit a drive signal to the light emission unit O in cooperation with the drive transistor T1, under the control of the enable signal from the enable signal line E1.

[0112] In some examples, the light emission control subcircuit 104 includes a first light emission control transistor T5 and a second light emission control transistor T6. The gate c5 of the first light emission control transistor T5 is electrically connected to the enable signal line E1, the first pole a5 of the first light emission control transistor T5 is electrically connected to the second node N2, and the second pole b5 of the first light emission control transistor T5 is electrically connected to the first power supply signal line VDD. The gate c6 of the second light emission control transistor T6 is electrically connected to the enable signal line E1, the first pole a6 of the second light emission control transistor T6 is electrically connected to the third node N3, and the second pole b6 of the second light emission control transistor T6 is electrically connected to the fourth node N4.

[0113] The second reset subcircuit 105 is electrically connected to the second reset signal line R2, the second initialization signal line V2, and the fourth node N4. During the initialization phase, the second reset subcircuit 105 is configured to transmit the second initialization signal received from the second initialization signal line V2 to the fourth node N4 under the control of the second reset signal received from the second reset signal line R2, thereby resetting the fourth node N4.

[0114] Here, since the fourth node N4 is electrically connected to the light-emitting unit O, resetting the fourth node N4 is equivalent to using the signal to reset the anode of the light-emitting unit O, thereby improving the stability of the light-emitting unit O.

[0115] In some examples, the second reset subcircuit 105 includes a second reset transistor T7. The gate c7 of the second reset transistor T7 is electrically connected to the second reset signal line R2, the first pole a7 of the second reset transistor T7 is electrically connected to the second initialization signal line V2, and the second pole b7 of the second reset transistor T7 is electrically connected to the fourth node N4.

[0116] In some embodiments, with further reference to Figures 5 and 6, the compensation transistor T3 and the first reset transistor T4 may be oxide thin-film transistors. Exemplarily, the compensation transistor T3 and the first reset transistor T4 may be indium gallium zinc oxide (IGZO) thin-film transistors.

[0117] This configuration is advantageous in reducing the leakage current risk of the compensation transistor T3 and the first reset transistor T4, and further advantageous in ensuring the voltage stability of the first node N1. In other words, it is advantageous in ensuring the stability of the gate c1 of the drive transistor T1.

[0118] In some examples, the compensation transistor T3 and the first reset transistor T4 may be N-type transistors.

[0119] In some embodiments, with further reference to Figures 5 and 6, the drive transistor T1, data writing transistor T2, first light emission control transistor T5, second light emission control transistor T6, and second reset transistor T7 may be low-temperature polycrystalline oxide (LTPO) thin-film transistors.

[0120] In some examples, the drive transistor T1, data writing transistor T2, first light emission control transistor T5, second light emission control transistor T6, and second reset transistor T7 may be P-type transistors.

[0121] Furthermore, the sub-pixel driving circuit Q further includes a storage capacitor Cst, the first electrode plate S1 of the storage capacitor Cst is electrically connected to the first node N1, and the second electrode plate S2 of the storage capacitor Cst is electrically connected to the first power signal line VDD.

[0122] An N-type transistor turns on when it receives a high-voltage signal at its gate, while a P-type transistor turns on when it receives a low-voltage signal at its gate. The terms "high-voltage signal" and "low-voltage signal" are general terms. Typically, the on-condition for an N-type transistor is that the gate-source voltage difference is greater than its threshold voltage; that is, the gate voltage of the N-type transistor is greater than the sum of its source voltage and its threshold voltage, and the threshold voltage of the N-type transistor is positive. In this case, the gate voltage signal that turns on the N-type transistor is called a high-voltage signal. The on-condition for a P-type transistor is that the absolute value of the gate-source voltage difference is greater than its threshold voltage, and the threshold voltage of the P-type transistor is negative; that is, the gate voltage of the P-type transistor is less than the sum of its source voltage and its threshold voltage. In this case, the gate voltage signal that turns on the P-type transistor is called a low-voltage signal. Here, the voltage of the "high-voltage signal" is greater than the voltage of the "low-voltage signal".

[0123] Furthermore, each sub-pixel driving circuit Q in the display panel 100 includes multiple thin-film transistors (TFTs), and by employing TFT driving technology, display speed, contrast, and brightness can be improved, and resolution can be increased. However, TFTs are subject to a hysteresis effect. The hysteresis effect of a TFT is the uncertainty shown in the electrical characteristics of the TFT under a constant bias voltage; that is, the current flowing through the TFT is related not only to the current bias voltage but also to the state of the TFT at the previous time. The hysteresis effect of the TFT is related to the gate dielectric of the TFT, the semiconductor material, and the interface state trap between the two. During the light emission stage, the hysteresis effect of the TFT tends to cause the current to decrease within one frame period, which is perceived by the human eye as a flickering phenomenon, thus affecting the display quality of the display panel 100.

[0124] Figure 7 is a circuit diagram of a sub-pixel driving circuit according to several other embodiments.

[0125] Furthermore, in some embodiments, with reference to Figure 7, the sub-pixel driving circuit provided by this embodiment will be explained using the "8T1C" sub-pixel driving circuit as an example, and the differences from the sub-pixel driving circuit Q shown in Figure 6 are as follows.

[0126] The sub-pixel driving circuit Q further includes a third reset sub-circuit 106. The third reset sub-circuit 106 is coupled to a third reset signal line R3, a third initialization signal line V3, and a second node. The third reset sub-circuit is configured to transmit the third initialization signal on the third initialization signal line V3 to the second node N2 under the control of the third reset signal from the third reset signal line R3, thereby initializing the second node N2. This is advantageous for fixing the initial state of the driving transistor TD before the write stage and stabilizing the driving transistor T1 during the write stage, and significantly improves the hysteresis effect of the driving transistor T1.

[0127] The third reset subcircuit 106 further includes a third reset transistor T8. The gate c8 of the third reset transistor T8 is electrically connected to the third reset signal line R3, the first pole a8 of the third reset transistor T8 is electrically connected to the third initialization signal line V3, and the second pole b8 of the third reset transistor T8 is electrically connected to the second node N2.

[0128] In some cases, the third reset transistor T8 may be a low-temperature polycrystalline oxide (LTPO) thin-film transistor.

[0129] In some examples, the third reset transistor T8 may be a p-type transistor.

[0130] In some embodiments, the third reset signal line R3 and the second reset signal line R2 can respond to the same signal line. Alternatively, the second reset signal line R2 can be understood as functioning as the third reset signal line R3. The following describes an example in which the second reset signal line R2 functions as the third reset signal line R3.

[0131] In some embodiments, the third initialization signal transmitted by the third initialization signal line V3 may be a high-voltage signal. Furthermore, the second node N2 can be reset using this high-voltage signal, which is equivalent to resetting the first pole a1 of the drive transistor T1. This is advantageous for fixing the initial state of the drive transistor T1 before the data writing stage t2, stabilizing the drive transistor T1 during the data writing stage t2, and significantly improving the hysteresis effect of the drive transistor T1.

[0132] In some examples, the first power supply signal line VDD can further function as a third initialization signal line V3, thereby simplifying the layout of each transistor in the sub-pixel driver circuit Q and the signal lines electrically connected to them. However, the disclosure is not limited thereto.

[0133] Figure 8 shows timing charts for sub-pixel driving circuits according to several embodiments.

[0134] In some embodiments, referring together to Figures 7 and 8, the driving process of the sub-pixel driving circuit Q of "8T1C" shown in Figure 7 is such that one frame period includes an initialization stage t1, a data writing stage t2, an adjustment stage t3, and an illumination stage t4.

[0135] Initialization stage t1: The enable signal transmitted by the enable signal line E1 is a high-voltage signal, and at this time, both the first light emission control transistor T5 and the second light emission control transistor T6 are in the off state. The first scan signal transmitted by the first scan signal line G1 is a high-voltage signal, and at this time, the data writing transistor T2 is in the off state.

[0136] The first reset signal transmitted by the first reset signal line R1 includes a high-voltage signal. At this time, the first reset transistor T4 turns on, and transmits the first initialization signal transmitted by the first initialization signal line V1 to the first node N1, resetting the first node N1. This is advantageous for improving the stability of the drive transistor T1 included in the sub-pixel drive circuit Q.

[0137] The second scan signal transmitted by the second scan signal line G2 includes a high-voltage signal, which turns on the compensation transistor T3. The first initialization signal transmitted by the first initialization signal line V1 is then transmitted to the third node N3 via the compensation transistor T3, which resets the third node N3. This is advantageous for improving the stability of the drive transistor T1 included in the sub-pixel drive circuit Q.

[0138] The second reset signal transmitted by the second reset signal line R2 includes a low-voltage signal, which turns on the third reset transistor T8 and transmits the third initialization signal transmitted by the third initialization signal line V3 to the second node N2. This is equivalent to resetting the first pole a1 of the drive transistor T1, which is advantageous for fixing the initial state of the drive transistor T1 before the data writing stage t2 and stabilizing the drive transistor T1 during the data writing stage t2, thereby significantly improving the hysteresis effect of the drive transistor T1.

[0139] Furthermore, the second reset signal transmitted by the second reset signal line R2 is a low-voltage signal. At this time, the second reset transistor T7 turns on and transmits the second initialization signal transmitted by the second initialization signal line V2 to the fourth node N4. This is equivalent to resetting the anode of the light-emitting unit O, thereby improving the stability of the light-emitting unit O.

[0140] Data writing stage t2: The enable signal transmitted by the enable signal line E1 is a high-voltage signal, and at this time, both the first light emission control transistor T5 and the second light emission control transistor T6 are in the off state. The first reset signal transmitted by the first reset signal line R1 is a low-voltage signal, and at this time, the first reset transistor T4 is in the off state. The second reset signal transmitted by the second reset signal line R2 is a high-voltage signal, and at this time, both the second reset transistor T7 and the third reset transistor T8 are in the off state.

[0141] The second scan signal transmitted by the second scan signal line G2 contains a high-voltage signal, which turns on the compensation transistor T3. The first scan signal transmitted by the first scan signal line G1 is a low-voltage signal, which turns on the data writing transistor T2. The data writing signal transmitted by the data writing signal line 21 is then transmitted to the first node N1 via the data writing transistor T2, the drive transistor T1, and the compensation transistor T3 in sequence, compensating the first node N1. The potential of the first node N1 gradually rises to Vdata + Vth. Here, Vdata is the voltage value of the data writing signal provided by the data writing signal line 21, and Vth is the threshold voltage of the drive transistor T1 in the sub-pixel drive circuit Q. When the potential of the first node N1 reaches Vdata + Vth, the charging process is completed. Subsequently, the discharge of the storage capacitor Cst is used to maintain the conduction state of the drive transistor T1 included in the sub-pixel drive circuit Q, ensuring the emission of light from the light-emitting unit O.

[0142] Adjustment stage t3: The enable signal transmitted by the enable signal line E1 is a high-voltage signal, and at this time, both the first light emission control transistor T5 and the second light emission control transistor T6 are in the off state. The first scan signal transmitted by the first scan signal line G1 is a high-voltage signal, and at this time, the data writing transistor T2 is in the off state. The second scan signal provided by the second scan signal line G2 is a low-voltage signal, and at this time, the compensation transistor T3 is in the off state. The first reset signal transmitted by the first reset signal line R1 is a low-voltage signal, and at this time, the first reset transistor T4 is in the off state.

[0143] The second reset signal transmitted by the second reset signal line R2 includes a low-voltage signal, which turns on the third reset transistor T8 and transmits the third initialization signal transmitted by the third initialization signal line V3 to the second node N2. This is equivalent to resetting the first pole a1 of the drive transistor T1, which is advantageous for fixing the initial state of the drive transistor T1 before the data writing stage t2 and stabilizing the drive transistor T1 during the data writing stage t2, thereby significantly improving the hysteresis effect of the drive transistor T1.

[0144] Furthermore, the second reset signal transmitted by the second reset signal line R2 is a low-voltage signal. At this time, the second reset transistor T7 turns on and transmits the second initialization signal transmitted by the second initialization signal line V2 to the fourth node N4. This is equivalent to resetting the anode of the light-emitting unit O, thereby improving the stability of the light-emitting unit O.

[0145] Light emission stage t4: The second scan signal provided by the second scan signal line G2 is a low-voltage signal, and at this time, the compensation transistor T3 is in the off state. The first reset signal transmitted by the first reset signal line R1 is a low-voltage signal, and at this time, the first reset transistor T4 is in the off state. The first scan signal transmitted by the first scan signal line G1 is a high-voltage signal, and at this time, the data writing transistor T2 is in the off state. The second reset signal transmitted by the second reset signal line R2 is a high-voltage signal, and at this time, both the second reset transistor T7 and the third reset transistor T8 are in the off state.

[0146] Furthermore, the enable signal transmitted by the enable signal line E1 is a low-voltage signal, and at this time, both the first light emission control transistor T5 and the second light emission control transistor T6 are turned on. At this time, the discharge of the storage capacitor Cst can be used to maintain the conduction state of the drive transistor T1 included in the sub-pixel drive circuit Q. Based on this, the constant-voltage power supply signal provided by the first power supply signal line VDD can flow to the anode of the light emission unit O via the first light emission control transistor T5, the drive transistor T1, and the second light emission control transistor T6 in sequence, and the cathode of the light emission unit O may be electrically connected to the second power supply signal line VSS. This allows the light emission unit O to be driven and made to emit light. Here, the first power supply signal line VDD may be a high-power supply signal line, and the second power supply signal line VSS may be a low-power supply signal line.

[0147] Figure 9 is a film layer diagram of the first semiconductor layer in Figure 5, Figure 10 is a film layer diagram of the first gate metal layer in Figure 5, Figure 11 is a film layer diagram of the first semiconductor layer and the first gate metal layer in Figure 5, Figure 12 is a film layer diagram of the first wiring metal layer in Figure 5, Figure 13 is a film layer diagram of the second wiring metal layer in Figure 5, and Figure 14 is a film layer diagram of the first semiconductor layer, the first gate metal layer, the first wiring metal layer and the second wiring metal layer in Figure 5.

[0148] In some embodiments, referring together to Figures 5, 9 to 14, if the orthographic projection of the second lead wire portion 222 on the base substrate 10, the orthographic projection of the first shield pattern 31 on the base substrate 10, and the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10 overlap, the second lead wire portion 222 and the first shield pattern 31 may be arranged on the same side along the first direction X of the gate c1 of the same drive transistor T1.

[0149] That is, in the first direction X, the second lead wire portion 222 and the first shield pattern 31 are concentrated on one side of the gate c1 of the drive transistor T1. This is equivalent to concentrating the second lead wire portion 222 and the first shield pattern 31 at a position corresponding to the edge region of the sub-pixel drive circuit Q.

[0150] Furthermore, the second lead wire portion 222 and the first shield pattern 31 can better avoid other transistors in the sub-pixel driving circuit Q, and can better avoid the gate c1 and second pole b1 of the driving transistor T1, forming a region that overlaps only with the first pole a1 of the driving transistor T1.

[0151] Based on this, it is advantageous to increase the distance between the second lead wire portion 222 and the gate c1 and second pole b1 of the drive transistor T1, thereby reducing the parasitic capacitance formed between the second lead wire portion 222 and the gate c1 of the drive transistor T1, and also reducing the parasitic capacitance formed between the second lead wire portion 222 and the second pole b1 of the drive transistor T1. As a result, when a jump occurs in the data writing signal transmitted by the second lead wire portion 222 to the data writing signal line 21, it is possible to prevent the effect on the voltage at the gate c1 and second pole b1 of the drive transistor T1, and as a result, it is advantageous to improve the stability of the drive transistor T1 in the sub-pixel driving circuit Q. On the one hand, it is advantageous for planning the layout of the first shield pattern 31, as the first shield pattern 31 can shield a wider area of ​​the first pole a1 of the drive transistor T1, and when a jump occurs in the data writing signal transmitted by the second lead wire portion 222 to the data writing signal line 21, it is possible to prevent the effect on the potential of the first pole a1 of the drive transistor T1, and as a result it is advantageous for improving the stability of the drive transistor T1 in the sub-pixel drive circuit Q.

[0152] As described above, by setting the relative positions of the second lead portion 222 of the data lead 22, the drive transistor T1 (the first pole a1 of the drive transistor T1, the second pole b1 of the drive transistor T1, and the gate c1 of the drive transistor T1) and the first shield pattern 31 in this manner, it is advantageous to reduce the parasitic capacitance formed between the second lead portion 222 of the data lead 22 and the drive transistor T1, and further advantageous to prevent the potential jump problem of the drive transistor T1 caused by the second lead portion 222 of the data lead 22. This improves the stability of the drive transistor T1 and improves the brightness uniformity of the display panel 100.

[0153] In some examples, the capacitance value of the parasitic capacitance formed between the second lead portion 222 of the data lead 22 and the drive transistor T1 (the first pole a1 of the drive transistor T1, the second pole b1 of the drive transistor T1, and the gate c1 of the drive transistor T1) is 0.01 fF or less.

[0154] For example, the capacitance value of the parasitic capacitance formed between the second lead portion 222 of the data lead wire 22 and the first pole a1 of the drive transistor T1 is 0.01 fF or less.

[0155] For example, the capacitance value of the parasitic capacitance formed between the second lead portion 222 of the data lead wire 22 and the second pole b1 of the drive transistor T1 is 0.01 fF or less.

[0156] For example, the capacitance value of the parasitic capacitance formed between the second lead portion 222 of the data lead wire 22 and the gate c1 of the drive transistor T1 is 0.01 fF or less.

[0157] By setting it in this way, the capacitance value of the parasitic capacitance formed between the second lead portion 222 of the data lead 22 and the drive transistor T1 can be reduced. As a result, it is advantageous to prevent the potential jump problem of the drive transistor T1 caused by the second lead portion 222 of the data lead 22, improve the stability of the drive transistor T1, and improve the brightness uniformity of the display panel 100.

[0158] The above explanation, accompanied by diagrams, described the overlapping relationship between the second lead wire section 222, the first shield pattern 31, and the drive transistor T1. Based on this foundation, the following section will specifically explain the positional relationship between the first shield pattern 31 and the multiple transistors in the sub-pixel drive circuit Q, accompanied by related diagrams.

[0159] In some embodiments, with reference to Figures 5, 7 to 14, the sub-pixel driving circuit Q further includes a write sub-circuit 101. The write sub-circuit 101 is coupled to a first scan signal line G1, a data write signal line 21, and a second node N2. During the writing phase, the write sub-circuit 101 is configured to transmit the data signal received on the data write signal line 21 to the second node under the control of the first scan signal received from the first scan signal line G1.

[0160] In some examples, the writing subcircuit 101 includes a data writing transistor T2. The gate c2 of the data writing transistor T2 is electrically connected to the first scan signal line G1, the first pole a2 of the data writing transistor T2 is electrically connected to the data writing signal line 21, and the second pole b2 of the data writing transistor T2 is electrically connected to the second node N2.

[0161] The first pole a1 of the drive transistor T1 is electrically connected to the second node N2, and the second pole b2 of the data writing transistor T2 is electrically connected to the second node N2. That is, the second pole b2 of the data writing transistor T2 is electrically connected to the first pole a1 of the drive transistor T1.

[0162] Based on the connection relationship between the drive transistor T1 and the data writing transistor T2 in the sub-pixel drive circuit Q described above, the data writing transistor T2 may be positioned on one side of the drive transistor T1 along the second direction Y. Furthermore, at least a portion of the first shield pattern 31 is located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2.

[0163] Furthermore, when we say that the data writing transistor T2 is located on one side of the drive transistor T1 along the second direction Y, it can mean that the data writing transistor T2 is located at any position in the region on both sides of the drive transistor T1 along the second direction Y. That is, the data writing transistor T2 can be located directly above, diagonally above, directly below, or diagonally below the drive transistor T1 along the second direction Y. Here, Figure 5 shows an example where the data writing transistor T2 is located diagonally above the drive transistor T1.

[0164] Since the first pole a1 of the drive transistor T1 is located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2, by placing the first shield pattern 31 between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2, the first shield pattern 31 can shield the first pole a1 of the drive transistor T1 more effectively. In other words, the first shield pattern 31 can better separate the first pole a1 of the drive transistor T1 from the second lead portion 222 of the data lead wire 22, which is advantageous in preventing potential jump problems of the first pole a1 of the drive transistor T1 caused by the second lead portion 222 of the data lead wire 22, improving the stability of the drive transistor T1 and improving the brightness uniformity of the display panel 100.

[0165] In some examples, referring to Figures 5, 7 to 14, the second pole b2 of the data writing transistor T2 is electrically connected to the first pole a1 of the drive transistor T1, and the data writing transistor T2 and the drive transistor T1 are laid out along the second direction Y, that is, the data writing transistor T2 and the drive transistor T1 are laid out along the extending direction of the second lead wire portion 222. Also, the second pole b2 of the data writing transistor T2 is located on the side of the gate c2 of the data writing transistor T2 that is closer to the drive transistor T1. Based on this, there may be an overlapping region between the orthographic projection of the second lead wire portion 222 on the base substrate 10 and the orthographic projection of the second pole b2 of the data writing transistor T2 on the base substrate 10.

[0166] In the above configuration, by placing at least a portion of the first shield pattern 31 between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2, the orthographic projection of the first shield pattern 31 located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2 on the base substrate 10 can be superimposed on the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10. Furthermore, the orthographic projection of the first shield pattern 31 located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2 on the base substrate 10 can also be superimposed on the orthographic projection of the second pole b2 of the data writing transistor T2 on the base substrate 10.

[0167] As a result, the first shield pattern 31 separates the first pole a1 of the drive transistor T1 from the second lead portion 222 of the data lead wire 22, and at the same time separates the second pole b2 of the data writing transistor T2 from the second lead portion 222 of the data lead wire 22. This prevents the potential jump problem of the first pole a1 of the drive transistor T1 caused by the potential jump problem of the second pole b2 of the data writing transistor T2 caused by the second lead portion 222 of the data lead wire 22, thereby improving the stability of the drive transistor T1 and is advantageous for improving the brightness uniformity of the display panel 100.

[0168] Here, "at least a portion of the first shield pattern 31 is located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2" includes the following two cases:

[0169] Case 1: A portion of the first shield pattern 31 is located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2. That is, the first shield pattern 31 can be extended based on the spatial position of each film layer of the sub-pixel drive circuit Q, and a portion of the first shield pattern 31 can be placed at other positions as well. Figure 5 shows the first case as an example.

[0170] Second case: The entirety of the first shield pattern 31 is located between the gate c1 of the drive transistor T1 and the gate c2 of the data writing transistor T2.

[0171] In some embodiments, with reference to Figures 5, 7 to 14, the sub-pixel driving circuit Q further includes a light emission control sub-circuit 104. The light emission control sub-circuit 104 is coupled to an enable signal line E1, a first power supply signal line VDD, a second node N2, and a fourth node N4. The light emission control sub-circuit 104 is configured to transmit a drive signal to the fourth node N4 in cooperation with a drive transistor T1, under the control of an enable signal from the enable signal line E1. Here, the fourth node N4 is electrically connected to the light emission unit O. That is, the light emission control sub-circuit 104 is configured to transmit a drive signal to the light emission unit O in cooperation with a drive transistor T1, under the control of an enable signal from the enable signal line E1.

[0172] In some examples, the light emission control subcircuit 104 includes a first light emission control transistor T5 and a second light emission control transistor T6. The gate c5 of the first light emission control transistor T5 is electrically connected to the enable signal line E1, the first pole a5 of the first light emission control transistor T5 is electrically connected to the second node N2, and the second pole b5 of the first light emission control transistor T5 is electrically connected to the first power supply signal line VDD. The gate c6 of the second light emission control transistor T6 is electrically connected to the enable signal line E1, the first pole a6 of the second light emission control transistor T6 is electrically connected to the third node N3, and the second pole b6 of the second light emission control transistor T6 is electrically connected to the fourth node N4.

[0173] The first pole a1 of the drive transistor T1 is electrically connected to the second node N2, the second pole b2 of the data writing transistor T2 is electrically connected to the second node N2, and the first pole a5 of the first light emission control transistor T5 is electrically connected to the second node N2. In other words, the first pole a1 of the drive transistor T1, the second pole b2 of the data writing transistor T2, and the first pole a5 of the first light emission control transistor T5 are all electrically connected to the same second node N2.

[0174] Based on the connection relationship between the data writing transistor T2, the first light emission control transistor T5, and the driving transistor T1 in the sub-pixel driving circuit Q described above, the first light emission control transistor T5 may be positioned along the second direction Y on the side of the driving transistor T1 that is away from the data writing transistor T2. Furthermore, at least a portion of the first shield pattern 31 is located between the gate c1 of the driving transistor T1, the gate c2 of the data writing transistor T2, and the gate c5 of the first light emission control transistor T5.

[0175] Furthermore, when we say that the first light-emitting control transistor T5 is located on the side of the drive transistor T1 away from the data writing transistor T2 along the second direction Y, it may mean that the first light-emitting control transistor T5 is located at any position within the region of the drive transistor T1 away from the data writing transistor T2. That is, if the data writing transistor T2 is located diagonally above the drive transistor T1, the first light-emitting control transistor T5 may be located either directly below or diagonally below the drive transistor T1 along the second direction Y. Here, Figure 5 shows an example where the first light-emitting control transistor T5 is located diagonally above the drive transistor T1.

[0176] Furthermore, since the first pole a1 of the drive transistor T1, the second pole b2 of the data writing transistor T2, and the first pole a5 of the first light emission control transistor T5 are all electrically connected to the same second node N2, by arranging the three components so that they are electrically connected to the same second node N2, and placing them within the region enclosed by the gate c2 of the data writing transistor T2, the gate c5 of the first light emission control transistor T5, and the gate c1 of the drive transistor T1, a configuration in which the first pole a1 of the drive transistor T1, the second pole b2 of the data writing transistor T2, and the first pole a5 of the first light emission control transistor T5 are electrically connected to each other can be easily realized.

[0177] Based on the relative positional relationship of the data writing transistor T2, the first light emission control transistor T5, and the drive transistor T1 described above, the first shield pattern 31 may be placed within the region enclosed by the gate c2 of the data writing transistor T2, the gate c5 of the first light emission control transistor T5, and the gate c1 of the drive transistor T1. As a result, the orthographic projection of the first shield pattern 31 on the base substrate 10 can be superimposed on the orthographic projection of the first pole a1 of the drive transistor T1 on the base substrate 10, and the first shield pattern 31 can better separate the first pole a1 of the drive transistor T1 from the second lead portion 222 of the data lead 22. This is advantageous in preventing the potential jump problem of the first pole a1 of the drive transistor T1 caused by the second lead portion 222 of the data lead 22, improving the stability of the drive transistor T1 and enhancing the brightness uniformity of the display panel 100.

[0178] In some examples, the first pole a1 of the drive transistor T1, the second pole b2 of the data writing transistor T2, and the first pole a5 of the first light emission control transistor T5 are electrically connected to the same second node N2, and the data writing transistor T2, the drive transistor T1, and the first light emission control transistor T5 are laid out in this order along the second direction Y, that is, the data writing transistor T2, the drive transistor T1, and the first light emission control transistor T5 are laid out along the extending direction of the second lead wire portion 222.

[0179] Based on this, there is a possibility that an overlapping region exists between the orthographic projection of the second lead wire portion 222 on the base substrate 10 and the orthographic projection of the second pole b2 of the data writing transistor T2 on the base substrate 10. Furthermore, there is a possibility that an overlapping region exists between the orthographic projection of the second lead wire portion 222 on the base substrate 10 and the orthographic projection of the first pole a5 of the first light emission control transistor T5 on the base substrate 10.

[0180] For example, the second pole b2 of the data writing transistor T2 is located on the side of the gate c2 of the data writing transistor T2 that is closer to the driving transistor T1. Also, the first pole a5 of the first light emission control transistor T5 is located on the side of the gate c5 of the first light emission control transistor T5 that is closer to the driving transistor T1.

[0181] Based on this, if at least a portion of the first shield pattern 31 is positioned between the gate c1 of the drive transistor T1, the gate c2 of the data writing transistor T2, and the gate c5 of the first light-emitting control transistor T5, then the orthographic projection of the first shield pattern 31 on the base substrate 10 can be superimposed not only on the orthographic projection of the first pole a1 of the drive transistor T1, but also on the orthographic projection of the first shield pattern 31 on the base substrate 10, as well as on the orthographic projection of the second pole b2 of the data writing transistor T2, and also on the orthographic projection of the first shield pattern 31 on the base substrate 10, as well as on the orthographic projection of the first pole a5 of the first light-emitting control transistor T5.

[0182] Furthermore, when the first shield pattern 31 separates the first pole a1 of the drive transistor T1 from the second lead portion 222 of the data lead wire 22, the second pole b2 of the data writing transistor T2 from the second lead portion 222 of the data lead wire 22, and the first pole a5 of the first light-emitting control transistor T5 from the second lead portion 222 of the data lead wire 22 can be separated. This prevents a potential jump problem in the first pole a1 of the drive transistor T1 caused by a potential jump problem in the second pole b2 of the data writing transistor T2 caused by the second lead portion 222 of the data lead wire 22, and also prevents a potential jump problem in the first pole a1 of the drive transistor T1 caused by a potential jump problem in the first pole a5 of the first light-emitting control transistor T5 caused by the second lead portion 222 of the data lead wire 22. This is advantageous for improving the stability of the drive transistor T1 and enhancing the brightness uniformity of the display panel 100.

[0183] Here, "at least a portion of the first shield pattern 31 is located between the gate c1 of the drive transistor T1, the gate c2 of the data writing transistor T2, and the gate c5 of the first light emission control transistor T5" includes the following two cases:

[0184] Case 1: A portion of the first shield pattern 31 is located between the gate c1 of the drive transistor T1, the gate c2 of the data writing transistor T2, and the gate c5 of the first light emission control transistor T5. That is, the first shield pattern 31 may be extended based on the spatial position of each film layer of the sub-pixel drive circuit Q, and a portion of the first shield pattern 31 may be placed at other positions as well. Figure 5 shows the first case as an example.

[0185] Second case: The entirety of the first shield pattern 31 is located between the gate c1 of the drive transistor T1, the gate c2 of the data writing transistor T2, and the gate c5 of the first light emission control transistor T5.

[0186] The above section, along with related diagrams, specifically explained the positional relationship between the first shield pattern 31 and the multiple transistors in the sub-pixel driving circuit Q. Below, along with related diagrams, the positional relationship between the first lead portion 221 of the data lead line 22 and the sub-pixel driving circuit Q will be explained.

[0187] In some embodiments, with reference to Figures 5, 7 to 14, the sub-pixel driving circuit Q further includes a first reset sub-circuit 103 with a first reset signal line R1, a first initialization signal line V1, and a first node N1. The first reset sub-circuit 103 is configured to, during the initialization phase, transmit the first initialization signal received on the first initialization signal line V1 to the first node N1 under the control of the first reset signal received from the first reset signal line R1, thereby resetting the first node N1. This is advantageous for ensuring voltage stability at the first node N1.

[0188] In some examples, the first reset subcircuit 103 includes a first reset transistor T4. The gate c4 of the first reset transistor T4 is electrically connected to the first reset signal line R1, the first pole a4 of the first reset transistor T4 is electrically connected to the first node N1, and the second pole b4 of the first reset transistor T4 is electrically connected to the first initialization signal line V1.

[0189] The first pole a4 of the first reset transistor T4 is electrically connected to the first node N1, and the gate c1 of the drive transistor T1 is electrically connected to the first node N1. That is, the first pole a4 of the first reset transistor T4 is electrically connected to the gate c1 of the drive transistor T1.

[0190] Based on the connection relationships of each transistor in the sub-pixel driving circuit Q described above, the first reset transistor T4 in one sub-pixel driving circuit Q within one pixel circuit unit P may be positioned along the second direction Y such that it is located on the side of the data writing transistor T2 that is away from the driving transistor T1. Furthermore, at least a portion of the first lead wire portion 221 passing through the same pixel circuit unit P is located on the side of the first reset transistor T4 that is away from the data writing transistor T2.

[0191] As shown in Figure 5, positioning at least a portion of the first lead portion 221 of the data lead 22 on the side of the first reset transistor T4 away from the data writing transistor T2 is equivalent to laying out the first lead portion 221 of the data lead 22 in the uppermost or lowermost edge region of the sub-pixel driving circuit Q. This allows the first lead portion 221 of the data lead 22 to better avoid the driving transistor T1 and other transistors in the sub-pixel driving circuit Q. Figure 5 shows an example in which the first lead portion 221 of the data lead 22 is laid out at the top of the sub-pixel driving circuit Q.

[0192] This configuration is advantageous for increasing the distance between the first lead wire portion 221 and the drive transistor T1 in the sub-pixel drive circuit Q, and simultaneously for increasing the distance between the first lead wire portion 221 and other transistors in the sub-pixel drive circuit Q. This reduces the parasitic capacitance formed between the first lead wire portion 221 and the drive transistor T1 in the sub-pixel drive circuit Q, and between the first lead wire portion 221 and other transistors in the sub-pixel drive circuit Q. As a result, the effect on the potential of the drive transistor T1 in the sub-pixel drive circuit Q when a jump occurs in the data writing signal transmitted by the first lead wire portion 221 of the data lead wire 22 is improved. This is advantageous for improving the stability of the drive transistor T1 in the sub-pixel drive circuit Q. At the same time, the potential jump problem of other transistors in the sub-pixel drive circuit Q caused by the first lead wire portion 221 is also reduced, which is advantageous for improving the brightness uniformity of the display panel 100.

[0193] In some examples, the capacitance value of the parasitic capacitance formed between the first lead portion 221 of the data lead wire 22 and the drive transistor T1 (the first pole a1 of the drive transistor T1, the second pole b1 of the drive transistor T1, and the gate c1 of the drive transistor T1) is 0.01 fF or less.

[0194] By setting it in this way, the capacitance value of the parasitic capacitance formed between the first lead portion 221 of the data lead 22 and the drive transistor T1 can be reduced. As a result, it is advantageous to prevent the potential jump problem of the drive transistor T1 caused by the first lead portion 221 of the data lead 22, improve the stability of the drive transistor T1, and enhance the brightness uniformity of the display panel 100.

[0195] Furthermore, "passing through" means that the orthographic projection of the first lead wire section 221 on the base substrate 10 and the orthographic projection of the pixel circuit unit P on the base substrate 10 overlap.

[0196] In some embodiments, referring together to Figures 5, 7 to 14, at least a portion of the first lead portion 221 of the data lead 22 may be positioned on the side of the first reset transistor T4 away from the data writing transistor T2, that is, assuming that the first lead portion 221 of the data lead 22 is laid out at the top or bottom of the sub-pixel driving circuit Q, the first lead portion 221 may be configured to include a main portion 221A and a relief portion 221B along the first direction X. The relief portion 221B protrudes from the main portion 221A away from the driving transistor T1, and the relief portion 221B is positioned on the side of the first reset transistor away from the data writing transistor T2.

[0197] To make it easier to understand, when the first lead wire portion 221 is laid out in the uppermost or lowermost edge region of the sub-pixel driving circuit Q, it is also necessary to position the first lead wire portion 221 as close to the inside of the sub-pixel driving circuit Q as possible. This allows the first lead wire portion 221 and the sub-pixel driving circuit Q to be placed in a concentrated area, which is advantageous for the layout of other adjacent sub-pixel driving circuits Q. However, since the first reset transistor T4 is also located in this edge region, there is a possibility that the orthographic projection of the first lead wire portion 221 on the base substrate 10 and the orthographic projection of the first reset transistor T4 on the base substrate 10 may overlap.

[0198] Based on this, the first lead wire portion 221 is configured to include the main body portion 221A and the relief portion 221B, and the relief portion 221B is made to protrude away from the drive transistor T1 relative to the main body portion 221A, thereby allowing the relief portion 221B to avoid the first reset transistor T4. This increases the distance between the first lead wire portion 221 and the first reset transistor T4, which is equivalent to increasing the distance between the first lead wire portion 221 and the drive transistor T1. As a result, it is advantageous to prevent potential jump problems in the drive transistor T1 and the first reset transistor T4 caused by the first lead wire portion 221 of the data lead wire 22, and is advantageous to improve the brightness uniformity of the display panel 100.

[0199] The above explanation, accompanied by related diagrams, mainly described an example in which one pixel driving unit P includes one sub-pixel driving circuit Q. Below, accompanied by related diagrams, an explanation will be given in an example in which one pixel driving unit P includes two sub-pixel driving circuits Q.

[0200] Figure 15 is a film layer structure diagram of a pixel drive unit according to several other embodiments. Here, Figure 15 shows an example in which one pixel drive unit P includes two sub-pixel drive circuits Q.

[0201] In some embodiments, with reference to Figure 15, a pixel circuit unit P includes two sub-pixel drive circuits Q arranged along a first direction X, where these two sub-pixel drive circuits Q are referred to as the first sub-pixel drive circuit Q1 and the second sub-pixel drive circuit Q2, respectively. The second lead wire portion 222 corresponding to the first sub-pixel drive circuit Q1 and the second lead wire portion 222 corresponding to the second sub-pixel drive circuit Q2 are arranged adjacent to each other.

[0202] Specifically, the second lead wire portion 222 corresponding to the first sub-pixel driving circuit Q1 is laid out in the edge region of the first sub-pixel driving circuit Q1 that is close to the second sub-pixel driving circuit Q2. At the same time, the second lead wire portion 222 corresponding to the second sub-pixel driving circuit Q2 is laid out in the edge region of the second sub-pixel driving circuit Q2 that is close to the first sub-pixel driving circuit Q1.

[0203] By configuring it in this way, the second lead wire portion 222 can more easily avoid the gap between the drive transistors T1 in the sub-pixel drive circuit Q, that is, it becomes easier to increase the gap between the second lead wire portion 222 and the corresponding drive transistor T1 in the sub-pixel drive circuit Q. As a result, it is possible to prevent the formation of parasitic capacitance between the second lead wire portion 222 and the corresponding drive transistor T1 in the sub-pixel drive circuit Q, which is advantageous in preventing the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222 of the data lead wire 22. This is advantageous in improving the stability of the drive transistor T1 and enhancing the brightness uniformity of the display panel 100.

[0204] To make it easier to understand, in some other embodiments, the second lead wire portion 222 corresponding to the first sub-pixel driving circuit Q1 may be laid out in the edge region of the first sub-pixel driving circuit Q1 furthest from the second sub-pixel driving circuit Q2, and the second lead wire portion 222 corresponding to the second sub-pixel driving circuit Q2 may be laid out in the edge region of the second sub-pixel driving circuit Q2 furthest from the first sub-pixel driving circuit Q1.

[0205] Even with this configuration, the second lead wire portion 222 can more easily avoid the gap between the drive transistors T1 in the sub-pixel drive circuit Q, that is, it becomes easier to increase the gap between the second lead wire portion 222 and the corresponding drive transistor T1 in the sub-pixel drive circuit Q. As a result, it is possible to prevent the formation of parasitic capacitance between the second lead wire portion 222 and the corresponding drive transistor T1 in the sub-pixel drive circuit Q, which is advantageous in preventing the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222 of the data lead wire 22. This is advantageous in improving the stability of the drive transistor T1 and enhancing the brightness uniformity of the display panel 100.

[0206] The second lead wire portion 222 corresponding to the first sub-pixel driving circuit Q1 may refer to the second lead wire portion 222 that overlaps with the first sub-pixel driving circuit Q1 in a direction perpendicular to the base substrate 10. Similarly, the second lead wire portion 222 corresponding to the second sub-pixel driving circuit Q2 may refer to the second lead wire portion 222 that overlaps with the second sub-pixel driving circuit Q2 in a direction perpendicular to the base substrate 10.

[0207] In some embodiments, with reference to Figure 15, when the second lead wire portion 222 corresponding to the first sub-pixel driving circuit Q1 and the second lead wire portion 222 corresponding to the second sub-pixel driving circuit Q2 are adjacent to each other, the first shield pattern 31 of the first sub-pixel driving circuit Q1 and the first shield pattern 31 of the second sub-pixel driving circuit Q2 may be arranged adjacent to each other within the same pixel circuit unit P.

[0208] By configuring it in this way, not only can the potential jump problem of the drive transistor T caused by the second lead wire section 222 be improved by using the first shield pattern 31, but the first shield pattern 31 itself can also be laid out in the edge region of the sub-pixel drive circuit Q. This makes it possible to avoid each transistor in the sub-pixel drive circuit Q and expand the layout space of the first shield pattern 31.

[0209] In some embodiments, with reference to Figure 15, when the first shield pattern 31 of the first sub-pixel driving circuit Q1 and the first shield pattern 31 of the second sub-pixel driving circuit Q2 are adjacent within the same pixel circuit unit P, the first shield pattern 31 of the first sub-pixel driving circuit Q1 and the first shield pattern 31 of the second sub-pixel driving circuit Q2 are electrically connected, and the first shield pattern 31 of the first sub-pixel driving circuit Q1 and the first shield pattern 31 of the second sub-pixel driving circuit Q2 may be arranged on the same layer.

[0210] In other words, the first shield pattern 31 of the first sub-pixel driving circuit Q1 and the first shield pattern 31 of the second sub-pixel driving circuit Q2 can be formed by the same patterning process. This simplifies the manufacturing process of the display panel 100.

[0211] Furthermore, since the first shield pattern 31 needs to be configured to have a constant voltage signal, after electrically connecting the first shield pattern 31 of the first sub-pixel driving circuit Q1 and the first shield pattern 31 of the second sub-pixel driving circuit Q2, simply transmitting a constant voltage signal to the first shield pattern 31 of one of the sub-pixel driving circuits Q1 and Q2 will cause the first shield pattern 31 of the other sub-pixel driving circuit Q to also have a constant voltage signal. This is advantageous for signal transmission.

[0212] In some embodiments, as shown in Figure 15, the first sub-pixel drive circuit Q1 and the second sub-pixel drive circuit Q2 are symmetrical along the first direction X within the same pixel drive unit P. This configuration is advantageous for improving the orderliness of the display panel 100 and for reducing the difficulty of manufacturing the display panel 100.

[0213] In some cases, the first sub-pixel drive circuit Q1 and the second sub-pixel drive circuit Q2 within the same pixel drive unit P can be arranged symmetrically along the first direction X. This is advantageous for improving the orderliness of the display panel 100 and simultaneously for reducing the difficulty of manufacturing the display panel 100.

[0214] Furthermore, if the first sub-pixel driving circuit Q1 and the second sub-pixel driving circuit Q2 are symmetrical, each structure arranged symmetrically and adjacently within the first sub-pixel driving circuit Q1 and the second sub-pixel driving circuit Q2 can be formed using the same drafting process. This simplifies the manufacturing process of the display panel 100. For example, the electrode plate that needs to be electrically connected to the first voltage terminal VDD in the storage capacitor Cst (see Figure 7) can be formed using the same drafting process, which is advantageous in reducing the difficulty of manufacturing the display panel 100.

[0215] Figure 16 shows the film layer structure diagram of a pixel driving unit according to several other embodiments.

[0216] In some embodiments, as shown in Figure 16, the first lead wire portion 221 extends along a first direction X, and the data writing signal line 21 extends along a second direction, so the orthographic projection of the first lead wire portion 221 on the base substrate 10 and the orthographic projection of the data writing signal line 21 on the base substrate 10 may partially overlap. Since the first lead wire portion 221 is not part of the data lead line 22 which is electrically connected to the data writing signal line 21, the data writing signal transmitted by the first lead wire portion 221 may be different from the data writing signal transmitted by the data writing signal line 21. As a result, parasitic capacitance formed between the first lead wire portion 221 and the data writing signal line 21 may affect the data writing signal transmitted by the first lead wire portion 221 and the data writing signal transmitted by the data writing signal line 21, and consequently, the brightness uniformity of the display panel 100 may be affected.

[0217] Based on this, the shield layer 30 of the display panel 100 may further include at least one second shield pattern 32, the second shield pattern 32 configured to have a constant voltage signal. The second shield pattern 32 is positioned between the first lead wire portion 221 and the data writing signal line 21, and the orthographic projection of the second shield pattern 32 on the base substrate 10, the orthographic projection of the first lead wire portion 221 on the base substrate 10, and the orthographic projection of the data writing signal line 21 on the base substrate 10 overlap each other.

[0218] With the above configuration, the second shield pattern 32 can separate the first lead wire section 221 from the data writing signal line 21, thereby reducing mutual influence between the first lead wire section 221 and the data writing signal line 21. This is advantageous for improving the brightness uniformity of the display panel 100.

[0219] In this case, the data writing signal line 21 may be placed on the third metal wiring layer, and the second shield pattern 32 may be placed on the second metal wiring layer. This allows the second shield pattern 32 to be positioned between the first lead wire portion 221 and the data writing signal line 21, but the embodiments of this disclosure are not limited thereto.

[0220] Figure 17 is a film layer diagram of the first semiconductor layer in Figure 15, Figure 18 is a film layer diagram of the first gate metal layer in Figure 15, Figure 19 is a film layer diagram of the first semiconductor layer and the first gate metal layer in Figure 15, Figure 20 is a film layer diagram of the second gate metal layer in Figure 15, Figure 21 is a film layer diagram of the first wiring metal layer in Figure 15, and Figure 22 is a film layer diagram of the second wiring metal layer in Figure 15.

[0221] In some embodiments, the drive circuit layer 20 of the display panel 100 includes multiple metal layers, with reference to Figures 7, 15, and 17-22. Sub-pixel drive circuits Q and multiple signal lines are arranged within the multiple metal layers. The structure of the sub-pixel drive circuit Q can be seen in Figure 7. Here, the multiple metal layers include a first semiconductor layer POLY1, a first gate metal layer Gate1, a second gate metal layer Gate2, a first wiring metal layer SD1, and a second wiring metal layer SD2, which are stacked on the base substrate 10.

[0222] The first semiconductor layer POLY1 is located on the base substrate 10 and includes the first electrode a1 and the second electrode b1 of the drive transistor T1.

[0223] In some examples, the material of the first semiconductor layer POLY1 may include semiconductor materials such as amorphous silicon, single-crystal silicon, or polycrystalline silicon.

[0224] The first gate metal layer Gate1 is located on the side of the first semiconductor layer POLY1 that is away from the base substrate 10. The first gate metal layer Gate1 includes the gate c1 of the drive transistor T1.

[0225] Exemplary, the material of the first gate metal layer Gate 1 includes a conductive metal. This conductive metal may include, but is not limited to, at least one of aluminum (Al), copper (Cu), and molybdenum (Mo).

[0226] For example, a first gate insulating layer is provided between the first semiconductor layer POLY1 and the first gate metal layer Gate1, and the first gate insulating layer electrically insulates the first semiconductor layer POLY1 and the first gate metal layer Gate1.

[0227] For example, the material of the first gate insulating layer includes one of the inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the first gate insulating layer may also include silicon dioxide, but this disclosure is not limited thereto.

[0228] The above example illustrates the formation of the drive transistor T1 of the sub-pixel drive circuit Q using the first semiconductor layer POLY1 and the first gate metal layer Gate1. However, the first semiconductor layer POLY1 and the first gate metal layer Gate1 are also used to form some of the transistors in the sub-pixel drive circuit Q. These some transistors may include the data writing transistor T2, the first light emission control transistor T5, the second light emission control transistor T6, and the second reset transistor T7. In the case of the "8T1C" sub-pixel drive circuit Q, these some transistors further include a third reset transistor T8.

[0229] Furthermore, the first semiconductor layer POLY1 and the first gate metal layer Gate1 are also used to form some signal lines. These signal lines include the first initialization signal line V1, the enable signal line E1, the first scan signal line G1, and the second reset signal line R2.

[0230] In some examples, a first scan signal line G1 located on a first gate metal layer Gate1 includes a first portion, which can further function as the gate c2 of a data writing transistor T2.

[0231] In some examples, a second reset signal line R2 located on the first gate metal layer Gate1 includes a first portion, the first portion of which can further function as the gate c7 of the second reset transistor T7.

[0232] In some examples, the enable signal line E1 located on the first gate metal layer Gate1 includes a first part and a second part. Here, the first part of the enable signal line E1 can further function as the gate of a first light emission control transistor T5, and the second part of the enable signal line E1 can further function as the gate of a second light emission control transistor T6.

[0233] Furthermore, there is an overlap between the orthographic projection of the first semiconductor layer POLY1 on the base substrate 10 and the orthographic projection of the first gate metal layer Gate1 on the base substrate 10. Here, the portion of the first semiconductor layer POLY1 covered by the first gate metal layer Gate1 constitutes the channel portion of each transistor, and the portion of the first semiconductor layer POLY1 not covered by the first gate metal layer Gate1 is a conductive portion and constitutes a part of the first or second pole of each transistor.

[0234] The second gate metal layer Gate2 is located on the side of the first gate metal layer Gate1 that is away from the first semiconductor layer POLY1.

[0235] For example, the material of the second gate metal layer Gate2 may be the same as the material of the first gate metal layer Gate1. In some other examples, it will be understood that the material of the second gate metal layer Gate2 may be different from the material of the first gate metal layer Gate1. The embodiments of this disclosure are not limited thereto.

[0236] For example, a second gate insulating layer is provided between the second gate metal layer Gate2 and the first gate metal layer Gate1. This second gate insulating layer electrically insulates the second gate metal layer Gate2 and the first gate metal layer Gate1.

[0237] For example, the material of the second gate insulating layer includes one of the inorganic insulating materials such as silicon nitride, silicon oxynitride, and silicon oxide. The material of the second gate insulating layer may also include silicon dioxide, but this disclosure is not limited thereto.

[0238] In some embodiments, the sub-pixel driving circuit Q further includes a storage capacitor Cst. The first electrode plate S1 of the storage capacitor Cst is electrically connected to the gate c1 of the driving transistor T1, and the second electrode plate S2 of the storage capacitor Cst is electrically connected to the first power supply signal line VDD.

[0239] The first electrode plate S1 of the storage capacitor Cst is located in the first gate metal layer Gate1, and the second electrode plate S2 of the storage capacitor Cst is located in the second gate metal layer Gate2. The orthographic projection of the first electrode plate S1 of the storage capacitor Cst on the base substrate 10 and the orthographic projection of the second electrode plate S2 of the storage capacitor Cst on the base substrate 10 overlap at least partially, thereby forming the storage capacitor Cst.

[0240] Here, the first electrode plate S1 of the storage capacitor Cst located on the first gate metal layer Gate1 can further function as the gate c1 of the drive transistor T1. Based on this, there is no need to separately provide the gate c1 of the drive transistor T1, which is advantageous in simplifying the manufacturing process of the sub-pixel drive circuit Q. Furthermore, by sharing the first electrode plate S1 of the storage capacitor Cst as the gate c1 of the drive transistor T1, the first electrode plate S1 of the storage capacitor Cst and the gate c1 of the drive transistor T1 can be directly electrically connected, eliminating the need to separately provide a connection part, which is also advantageous for the layout of the sub-pixel drive circuit Q.

[0241] Furthermore, the second gate metal layer Gate2 is used to form some signal lines. These signal lines include the first reset signal line R1 and the second scan signal line G2.

[0242] In some examples, the first reset signal line R1 located in the second gate metal layer Gate2 may include a first portion, which may further function as the gate c4 of the first reset transistor T4.

[0243] In some examples, the second scan signal line G2 located in the second gate metal layer Gate2 may include a first portion, which may further function as the gate c3 of the compensating transistor T3.

[0244] The first wiring metal layer SD1 is located on the side of the second gate metal layer Gate2 that is away from the first gate metal layer Gate1.

[0245] For example, the material of the first wiring metal layer SD1 may be a multilayer composite material of titanium (Ti)-aluminum (Al)-titanium (Ti). Based on this, the sheet resistance of the first wiring metal layer SD1 is approximately 0.05 mΩ / □.

[0246] For example, a first planarization layer (PLN) is provided between the first wiring metal layer SD1 and the second gate metal layer Gate2. This first planarization layer electrically insulates the first wiring metal layer SD1 and the second gate metal layer Gate2.

[0247] Exemplary, the material of the first planarization layer is generally an organic material. For example, the material of the first planarization layer may include at least one of polyimide (PI), acrylic polymer, or silicon polymer.

[0248] Furthermore, the first wiring metal layer SD1 is used to form a portion of the signal line. This portion of the signal line includes the second initialization signal line V2.

[0249] The second wiring metal layer SD2 is located on the side of the first wiring metal layer SD1 that is away from the first gate metal layer Gate1.

[0250] In some examples, the material of the second wiring metal layer SD2 may be the same as the material of the first wiring metal layer SD1. It is understood that the material of the second wiring metal layer SD2 may be different from the material of the first wiring metal layer SD1. The embodiments of this disclosure are not limited thereto.

[0251] For example, a second planarization layer is provided between the second wiring metal layer SD2 and the first wiring metal layer SD1. This second planarization layer electrically insulates the second wiring metal layer SD2 and the first wiring metal layer SD1.

[0252] Exemplary, the material of the second planarization layer is generally an organic material. For example, the material of the second planarization layer may include at least one of polyimide (PI), acrylic polymer, or silicon polymer.

[0253] As is evident from the structure of the drive circuit layer 20 in the display panel 100 described above, the drive transistor T1 is mainly formed in the first semiconductor layer POLY1 and the first gate metal layer Gate1. Furthermore, the spacing between the first wiring metal layer SD1 and the second wiring metal layer SD2 and the drive transistor T1 is greater than the spacing between the second gate metal layer Gate2 and the drive transistor T1. As a result, by placing the data lead wires 22 in the first wiring metal layer SD1 and the second wiring metal layer SD2, the spacing between the data lead wires 22 and the drive transistor T1 can be increased, which is advantageous in reducing the parasitic capacitance formed between the data lead wires 22 and the drive transistor T1. This reduces the potential jump problem of the drive transistor T1 caused by the data lead wires 22, improves the stability of the drive transistor T1 in the sub-pixel drive circuit Q, and is advantageous in improving the brightness uniformity of the display panel 100.

[0254] Exemplary, the first wiring metal layer SD1 may include a first lead wire portion 221 extending along a first direction X of the data lead wire 22. The second wiring metal layer SD2 may include a second lead wire portion 222 extending along a second direction Y of the data lead wire 22.

[0255] Here, when the second lead wire portion 222 is placed on the second wiring metal layer SD2, the distance between the second lead wire portion 222 and the drive transistor T1 can be increased compared to when it is placed on the first wiring metal layer SD1. That is, the distance between the second lead wire portion 222 and the first pole a1 of the drive transistor T1 can be increased, and the influence on the potential of the first pole a1 of the drive transistor T1 when a jump occurs in the data writing signal transmitted by the second lead wire portion 222 to the data writing signal line 21 can be reduced. This improves the stability of the drive transistor T1 in the sub-pixel driving circuit Q and is advantageous in improving the brightness uniformity of the display panel 100.

[0256] For example, by setting it as described above, the minimum distance between the second lead wire portion 222 and the gate c1 of the drive transistor T1 can be set to 6 μm or more, and the minimum distance between the second lead wire portion 222 and the first pole a1 of the drive transistor T1 can be set to 18 μm or more.

[0257] When the minimum distance between the second lead wire portion 222 and the gate c1 of the drive transistor T1 is equal to or close to 6 μm, and the minimum distance between the second lead wire portion 222 and the first pole a1 of the drive transistor T1 is equal to or close to 18 μm, the distance between the second lead wire portion 222 and the gate c1 of the drive transistor T1 can be made sufficiently large, and the distance between the second lead wire portion 222 and the first pole a1 of the drive transistor T1 can also be made sufficiently large. As a result, the distance between the second lead wire portion 222 and the first pole a1 of the drive transistor T1 can be increased, and the influence on the potential of the first pole a1 of the drive transistor T1 when a jump occurs in the data writing signal transmitted by the second lead wire portion 222 to the data writing signal line 21 can be reduced. This is advantageous in improving the stability of the drive transistor T1 in the sub-pixel driving circuit Q and improving the brightness uniformity of the display panel 100.

[0258] Here, a larger gap between the second lead wire portion 222 and the drive transistor T1 is preferable. However, due to space constraints such as the need to make the display panel 100 thinner and lighter, it is necessary to adjust the gap between the second lead wire portion 222 and the drive transistor T1 to be as large as possible within an appropriate range. This further reduces the influence of the second lead wire portion 222 on the drive transistor T1, improving the stability of the drive transistor T1 in the sub-pixel drive circuit Q and is advantageous in enhancing the brightness uniformity of the display panel 100.

[0259] Furthermore, due to the difference in materials between the first wiring metal layer SD1 and the second wiring metal layer SD2 and the second gate metal layer Gate2, the sheet resistance of the first wiring metal layer SD1 and the second wiring metal layer SD2 can be made less than or equal to the sheet resistance of the second gate metal layer Gate2. As a result, by placing the data lead wires 22 in the first wiring metal layer SD1 and the second wiring metal layer SD2, which have low sheet resistance, the RC impedance of the data lead wires 22 can be reduced, and the voltage transmission loss of the data writing signal in the data lead wires 22 can be reduced. This prevents a drop in the voltage of the data writing signal received by the data writing signal line 21 when the data writing signal is transmitted to the data writing signal line 21 by the data lead wires 22. Consequently, this is advantageous for making the data writing signals received by each sub-pixel driving circuit Q from the data writing signal line 21 approximately equal, and is advantageous for improving the brightness uniformity of the display panel 100.

[0260] In the above explanation, an example was given in which the data lead lines 22 are arranged on the first wiring metal layer SD1 and the second wiring metal layer SD2. However, the first wiring metal layer SD1 and the second wiring metal layer SD2 are also used to form some other signal lines. These other signal lines include the first power signal line VDD, the data write signal line 21, and so on.

[0261] Exemplary, the pixel circuit unit P further includes a first power signal line VDD. The first power signal line VDD is located in the second wiring metal layer SD2 and is configured to supply a constant voltage power signal to the pixel drive circuit Q.

[0262] As is clear from the structure of the drive circuit layer 20 in the display panel 100 described above, the drive transistor T1 is mainly formed in the first semiconductor layer POLY1 and the first gate metal layer Gate1, and the second lead portion 222 of the data lead wire 22 is formed in the second wiring metal layer SD2. Thus, it can be seen that at least the second gate metal layer Gate2 and the first wiring metal layer SD1 are interposed between the second lead portion 222 and the drive transistor T1.

[0263] Furthermore, the first shield pattern 31 may be placed on the second gate metal layer Gate2 and / or the first wiring metal layer SD1. Here, the film layer position of the first shield pattern 31 includes several cases as follows:

[0264] Case 1: The first shield pattern 31 is placed on the second gate metal layer Gate2.

[0265] Second case: The first shield pattern 31 is placed on the first wiring metal layer SD1.

[0266] Third case: The first shield pattern 31 is placed on both the second gate metal layer Gate2 and the first wiring metal layer SD1. That is, a portion of the first shield pattern 31 is placed on the second gate metal layer Gate2, and the other portion of the first shield pattern 31 is placed on the first wiring metal layer SD1. In this case, it is necessary to electrically connect the first shield pattern 31 located on the second gate metal layer Gate2 and the first shield pattern 31 located on the first wiring metal layer SD1.

[0267] Based on this, the first shield pattern 31 may be placed within the metal layer (second gate metal layer Gate2 and first wiring metal layer SD1) interposed between the second lead wire portion 222 and the drive transistor T1, depending on the layout space of the metal layer. This allows the second lead wire portion 222 and the drive transistor T1 to be separated using the first shield pattern 31, improving the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222 and increasing the brightness uniformity of the display panel 100. Furthermore, the space of the metal layer interposed between the second lead wire portion 222 and the drive transistor T1 can be effectively utilized, eliminating the need to separately provide a metal film layer for forming the first shield pattern 31, which is advantageous for making the display panel 100 thinner.

[0268] In some embodiments, the shield layer 30 can be electrically connected to the first power signal line VDD, and the shield layer 30 can be configured to have a constant voltage signal. Based on this, since the shield layer 30 has a constant voltage signal, there is no need to provide a separate constant voltage signal line, which is advantageous for simplifying the internal structure of the display panel 100.

[0269] Figure 23 is a film layer diagram of the second gate metal layer in a sub-pixel driving circuit according to several embodiments.

[0270] In some embodiments, with reference to Figures 15, 17-19, and 21-23, the second electrode plate S2 of the storage capacitor Cst includes a first sub-part F1. Along the direction perpendicular to the base substrate 10, the first sub-part F1, the first pole a1 of the drive transistor T1, and the second lead wire portion 222 overlap, and the first sub-part F1 further functions as a first shield pattern 31.

[0271] The second electrode plate S2 of the storage capacitor Cst is located in the second gate metal layer Gate2, and the second gate metal layer Gate2 is located between the first gate metal layer Gate1 and the second wiring metal layer SD2. Therefore, when forming the second gate metal layer Gate2, the first shield pattern 31 can be formed simultaneously.

[0272] Based on this, when forming the second electrode plate S2 of the storage capacitor Cst on the second gate metal layer Gate2, the second electrode plate S2 can be extended to form the first sub-part F1 of the second electrode plate S2 of the storage capacitor Cst. Here, the second electrode plate S2 of the storage capacitor Cst is extended along a direction perpendicular to the base substrate 10 so that the first sub-part F1, the first pole a1 of the drive transistor T1, and the second lead wire portion 222 overlap, that is, the second electrode plate S2 of the storage capacitor Cst is extended to the space between the first pole a1 of the drive transistor T1 and the second lead wire portion 222.

[0273] Furthermore, by utilizing the first sub-part F1 of the second electrode plate S2 of the storage capacitor Cst, the first pole a1 of the drive transistor T1 and the second lead wire portion 222 can be separated, thereby improving the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222. This is advantageous in improving the stability of the drive transistor T1 and enhancing the uniformity of the display panel 100.

[0274] Furthermore, since the second electrode plate S2 of the storage capacitor Cst needs to be electrically connected to the first power signal line VDD, there is no need to separately provide a configuration for electrically connecting the first shield pattern (the first sub-part F1 of the second electrode plate S2 of the storage capacitor Cst) to the first power signal line VDD, which is advantageous for simplifying the layout.

[0275] In some embodiments, referring together to Figures 15, 17 to 22, when one pixel drive unit P includes two sub-pixel drive circuits Q, the second electrode plates S2 of the storage capacitors Cst in both sub-pixel drive circuits Q must be electrically connected to the first power supply signal line VDD. That is, the signals acquired by the second electrode plates S2 of the storage capacitors Cst in the two sub-pixel drive circuits Q are identical.

[0276] Based on this, the second electrode plates S2 of the storage capacitors Cst in the two sub-pixel driving circuits Q may be electrically connected, that is, the first sub-parts F1 of the second electrode plates S2 of the storage capacitors Cst in the two sub-pixel driving circuits Q may also be electrically connected.

[0277] In this case, it is advantageous to increase the size of the first sub-part F1, that is, it is advantageous to increase the size of the first shield pattern 31. Thereby, the first shield pattern 31 can further preferably separate the first pole a1 of the driving transistor T1 and the second lead wire part 222, which is advantageous for improving the stability of the driving transistor T1.

[0278] In addition, in some other embodiments, as shown in FIG. 24, FIG. 24 is a film layer diagram of a second gate metal layer in a sub-pixel driving circuit according to some other embodiments, and referring to FIGS. 15, 17-19, 21 and 22 together, a first shield pattern 31 independent of the storage capacitor Cst may be arranged on the second gate metal layer Gate2. The first shield pattern 31 is located on the side of the second electrode plate S2 of the storage capacitor Cst close to the first pole a1 of the driving transistor T1. Thereby, the orthographic projection of the first shield pattern 31 on the base substrate 10 overlaps with the orthographic projection of the first pole a1 of the driving transistor T1 on the base substrate 10.

[0279] Based on this, the space on the second gate metal layer Gate2 can be effectively utilized, and the first shield pattern 31 can be arranged at a position corresponding to the first pole a1 of the driving transistor T1. Thereby, the first shield pattern 31 is used to separate the first pole a1 of the driving transistor T1 and the second lead wire part 222, and the potential jump problem of the driving transistor T1 caused by the second lead wire part 222 can be improved. This is advantageous for enhancing the luminance uniformity of the display panel 100.

[0280] Furthermore, the first shield pattern 31 located in the second gate metal layer Gate2 can be given a constant voltage potential by connecting it to the first power signal line VDD located on the second wiring metal layer SD2 using a conductive block located in the first wiring metal layer SD1.

[0281] The first shield pattern 31 located in the second gate metal layer Gate2 can also be connected to the first power signal line VDD on the second wiring metal layer SD2 using via holes directly, so that the first shield pattern 31 has a constant voltage potential. Embodiments of this disclosure are not limited thereto.

[0282] In some embodiments, referring together to Figures 15, 17 to 22, the second electrode plate S2 of the storage capacitor Cst located in the second gate metal layer Gate2 needs to be electrically connected to the first power signal line VDD located in the second wiring metal layer SD2.

[0283] Between the second gate metal layer Gate2 and the first power signal line VDD, at least the second gate insulating layer, the first wiring metal layer SD1, and the first planarization layer are interposed. Because there are many film layers interposed between the second gate metal layer Gate2 and the first power signal line VDD, if the film layers between the second gate metal layer Gate2 and the first power signal line VDD are directly etched to form a communication hole and electrically connect the second electrode plate S2 of the storage capacitor Cst to the first power signal line VDD, the depth of the communication hole becomes excessive, making the manufacturing process difficult and increasing the likelihood of blind holes occurring.

[0284] Based on this, a first connection part PAD1 may be formed on the first wiring metal layer SD1 located between the second gate metal layer Gate2 and the first power signal line VDD. The orthographic projection of the first connection part PAD1 on the base substrate 10 overlaps with the orthographic projection of the second electrode plate S2 of the storage capacitor Cst on the base substrate 10, and the orthographic projection of the first connection part PAD1 on the base substrate 10 also overlaps with the orthographic projection of the first power signal line VDD on the base substrate 10.

[0285] Furthermore, via holes may be formed in the second gate insulating layer and the first planarization layer, respectively, using a segmented punching process. This allows one end of the first connection part PAD1 to be electrically connected to the second electrode plate S2 of the storage capacitor Cst via a via hole on the second gate insulating layer, and the other end of the first connection part PAD1 to be electrically connected to the first power signal line VDD via a via hole on the first planarization layer. This realizes an electrical connection between the second electrode plate S2 of the storage capacitor Cst and the first power signal line VDD. By using a segmented punching process, the depth of the via holes can be reduced, which is advantageous in lowering the difficulty of the punching process and is advantageous in improving the yield rate of the display panel 100.

[0286] Furthermore, since the first connection part PAD1 is electrically connected to the first power signal line VDD, the first connection part PAD1 can be configured to have a constant voltage signal.

[0287] Based on this, the first connection part PAD1 may be laid out between the second lead wire portion 222 and the drive transistor T1, and the first connection part PAD1 may further function as the first shield pattern 31. Furthermore, the first connection part PAD1 can be used to separate the first pole a1 of the drive transistor T1 from the second lead wire portion 222, thereby improving the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222. This is advantageous in improving the stability of the drive transistor T1 and increasing the uniformity of the display panel 100.

[0288] Furthermore, since the first connection part PAD1 can also function directly as the first shield pattern 31, there is no need to separately manufacture the first shield pattern 31 within the display panel 100, which is advantageous in simplifying the manufacturing process of the display panel 100.

[0289] In some embodiments, referring together to Figures 15, 17 to 22, when the second electrode plate S2 of the storage capacitor Cst on the second gate metal layer Gate2 includes a first sub-part F1 and a first connection part PAD1 is provided on the first wiring metal layer SD1, the first connection part PAD1 may be used to electrically connect the first sub-part F1 of the second electrode plate S2 of the storage capacitor Cst. As a result, the second electrode plate S2 of the storage capacitor Cst can receive a constant voltage power supply signal from the first power supply signal line VDD via the first connection part PAD1.

[0290] In this case, the first sub-part F1 and the first connection part PAD1 of the second electrode plate S2 of the storage capacitor Cst also function as a first shield pattern 31. By utilizing the first sub-part F1 and the first connection part PAD1 of the second electrode plate S2 of the storage capacitor Cst to separate the first pole a1 and the second lead wire portion 222 of the drive transistor T1, the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222 can be improved. This is advantageous for improving the stability of the drive transistor T1 and increasing the uniformity of the display panel 100.

[0291] In some embodiments, referring together to Figures 15, 17 to 22, one sub-pixel driving circuit Q further includes a first light emission control transistor T5, the second pole b5 of the first light emission control transistor T5 being electrically connected to a first power supply signal line VDD.

[0292] The second pole b5 of the first light-emitting control transistor T5 is located in the first semiconductor layer POLY1, and the first power signal line VDD is located in the second wiring metal layer SD2. Therefore, a number of film layers are interposed between the second pole b5 of the first light-emitting control transistor T5 and the first power signal line VDD. If the film layer between the first semiconductor layer POLY1 and the second wiring metal layer SD2 is directly etched to form a communication hole, and the second pole b5 of the first light-emitting control transistor T5 and the first power signal line VDD are electrically connected, the depth of the communication hole becomes excessive, making the manufacturing process difficult and increasing the likelihood of blind holes occurring.

[0293] Based on this, a first joint PAD2 may be formed on the first wiring metal layer SD1, which is located between the first semiconductor layer POLY1 and the second wiring metal layer SD2. By employing a segmented punching process, the first joint PAD2 can be electrically connected to the second pole b5 of the first light-emitting control transistor T5 and the first power signal line VDD. By utilizing a segmented punching process, the depth of the via holes can be reduced, which is advantageous in lowering the difficulty of the punching process and improving the yield rate of the display panel 100.

[0294] Furthermore, since the first joint PAD2 is electrically connected to the first power signal line VDD, the first joint PAD2 can be configured to have a constant voltage signal.

[0295] Based on this, the first joint PAD2 may be laid out between the second lead wire portion 222 and the drive transistor T1, and the first joint PAD2 can further function as the first shield pattern 31. Furthermore, by using the first joint PAD2 to separate the first pole a1 of the drive transistor T1 from the second lead wire portion 222, the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222 can be improved. This is advantageous for improving the stability of the drive transistor T1 and increasing the uniformity of the display panel 100.

[0296] In some embodiments, the first joint PAD2 and the first connection PAD1 of the first wiring metal layer SD1 may be electrically connected to form the first shield pattern 31. Furthermore, the first joint PAD2 and the first connection PAD1 may be formed using the same drafting process, which is advantageous for simplifying the manufacturing process of the display panel 100.

[0297] In addition, by forming the first joint portion PAD2 and the first connection portion PAD1 to form the first shield pattern 31, it is advantageous to increase the size of the first shield pattern 31, and the first shield pattern 31 can more favorably separate the driving transistor T1 and the second lead wire portion 222, which is advantageous for improving the stability of the driving transistor T1.

[0298] FIG. 25 is a diagram of a film layer structure of a pixel driving unit according to some other embodiments.

[0299] In some embodiments, referring to FIG. 25, in addition to the first semiconductor layer POLY1, the first gate metal layer Gate1, the second gate metal layer Gate2, the first wiring metal layer SD1, and the second wiring metal layer SD2 laminated on the base substrate 10, the driving circuit layer 20 may further include a third wiring metal layer SD3. The third wiring metal layer SD3 is located on the side of the second wiring metal layer SD2 away from the first wiring metal layer SD1.

[0300] Exemplarily, the material of the third wiring metal layer SD3 can be a multilayer laminated composite material of titanium (Ti)-aluminum (Al)-titanium (Ti). Based on this, the sheet resistance of the third wiring metal layer SD3 is about 0.05 mΩ / □.

[0301] Exemplarily, a third planarization layer is included between the third wiring metal layer SD3 and the second wiring metal layer SD2. The third planarization layer is used to electrically insulate the third wiring metal layer SD3 and the second wiring metal layer SD2.

[0302] Exemplarily, the material of the third planarization layer is generally an organic material. For example, the material of the third planarization layer may include at least one of polyimide (full English name: Polyimide, English abbreviation: PI), acrylic polymer, or silicon-based polymer.

[0303] If the drive circuit layer 20 of the display panel 100 includes a third wiring metal layer SD3, the second lead portion 222 of the data lead line 22 may be placed on the third wiring metal layer SD3. Placing the second lead portion 222 of the data lead line 22 on the third wiring metal layer SD3 is advantageous for increasing the distance between the second lead portion 222 and the first pole a1 of the drive transistor T1 compared to placing the second lead portion 222 on the second wiring metal layer SD2. This reduces the influence on the potential of the first pole a1 of the drive transistor T1 when a jump occurs in the data writing signal transmitted by the second lead portion 222 to the data writing signal line 21, improving the stability of the drive transistor T1 in the sub-pixel drive circuit Q and improving the brightness uniformity of the display panel 100.

[0304] As is clear from the structure of the drive circuit layer 20 in the display panel 100 described above, the drive transistor T1 is mainly formed in the first semiconductor layer POLY1 and the first gate metal layer Gate1, and the second lead portion 222 of the data lead wire 22 is formed in the third wiring metal layer SD3. As can be seen from this, at least the second gate metal layer Gate2, the first wiring metal layer SD1 and the second wiring metal layer SD2 are interposed between the second lead portion 222 and the drive transistor T1.

[0305] Furthermore, the first shield pattern 31 may be placed on at least one of the second gate metal layer Gate2, the first wiring metal layer SD1, and the second wiring metal layer SD2. Here, the film layer position of the first shield pattern 31 includes several cases as follows.

[0306] Case 1: The first shield pattern 31 is placed on the second gate metal layer Gate2.

[0307] Second case: The first shield pattern 31 is placed on the first wiring metal layer SD1.

[0308] Third case: The first shield pattern 31 is placed on the second wiring metal layer SD2.

[0309] Case 4: The first shield pattern 31 is placed on the second gate metal layer Gate2 and the first wiring metal layer SD1.

[0310] Case 5: The first shield pattern 31 is placed on the second gate metal layer Gate2 and the second wiring metal layer SD2.

[0311] Case 6: The first shield pattern 31 is placed on the first wiring metal layer SD1 and the second wiring metal layer SD2.

[0312] Case 7: The first shield pattern 31 is placed on the second gate metal layer Gate2, the first wiring metal layer SD1, and the second wiring metal layer SD2.

[0313] In this case, if the first shielding pattern 31 is distributed across two or three layers, the first shielding patterns 31 on different film layers can be electrically connected to each other.

[0314] Based on this, the first shield pattern 31 can be placed within the metal layer (second gate metal layer Gate2, first wiring metal layer SD1, and second wiring metal layer SD2) interposed between the second lead wire portion 222 and the drive transistor T1, depending on the layout space of the metal layer. This allows the second lead wire portion 222 and the drive transistor T1 to be separated using the first shield pattern 31, improving the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222 and enhancing the brightness uniformity of the display panel 100. Furthermore, the space of the metal layer interposed between the second lead wire portion 222 and the drive transistor T1 can be effectively utilized, eliminating the need to separately provide a metal film layer for forming the first shield pattern 31, which is advantageous for making the display panel 100 thinner.

[0315] Furthermore, the method described in the above embodiment, which allows components on different film layers to function as the first shield pattern 31, is also applicable to this embodiment, so a detailed explanation is omitted here.

[0316] Note that the film layer structure diagrams in Figure 25, excluding the second wiring metal layer SD2, are identical to the exploded view of the sub-pixel driving circuit Q shown in Figure 15. The only difference regarding the second wiring metal layer SD2 is that the second lead wire portion 222 in the second wiring metal layer SD2 shown in Figure 15 has moved to the third wiring metal layer SD3.

[0317] Figure 26 is a film layer diagram of the second semiconductor layer in Figure 15, Figure 27 is a film layer diagram of the third gate metal layer in Figure 15, and Figure 28 is a film layer diagram of the second gate metal layer, the second semiconductor layer, and the third gate metal layer in Figure 15.

[0318] In some embodiments, with reference to Figures 15, 17-22, and 26-28, the drive circuit layer 20 may further include a second semiconductor layer IGZO and a third gate metal layer Gate 3. The compensation transistor T3 and the first reset transistor T4 in the sub-pixel drive circuit Q may be oxide thin-film transistors. The gate c3 of the compensation transistor T3 includes the top gate c31 and the bottom gate c32 of the compensation transistor T3, and the gate c4 of the first reset transistor T4 includes the top gate c41 and the bottom gate c42 of the first reset transistor T4.

[0319] Here, the bottom gate c32 of the compensation transistor T3 and the bottom gate c42 of the first reset transistor T4 are located in the second gate metal layer Gate2.

[0320] The second semiconductor layer IGZO is located on the side of the second gate metal layer Gate2 that is away from the first gate metal layer Gate1. The second semiconductor layer IGZO includes the first electrode a3 of the compensation transistor T3, the second electrode b3 of the compensation transistor T3, the first electrode a4 of the first reset transistor T4, and the second electrode b4 of the first reset transistor T4.

[0321] The third gate metal layer Gate3 is located on the side of the second semiconductor layer IGZO that is away from the second gate metal layer Gate2. The second gate metal layer Gate2 includes the first reset transistor T4 and the top gate c41 of the first reset transistor T4.

[0322] Whether the second lead wire portion 222 is located in the second wiring metal layer SD2 or in the third wiring metal layer SD3, the third gate metal layer Gate3 is located between the film layer where the second lead wire portion 222 is located and the first semiconductor layer POLY1. Furthermore, a first shield pattern 31 may be formed on the third gate metal layer Gate3, and the second lead wire portion 222 and the drive transistor T1 can be separated by utilizing the first shield pattern 31 formed on the third gate metal layer Gate3. This improves the potential jump problem of the drive transistor T1 caused by the second lead wire portion 222, which is advantageous for improving the brightness uniformity of the display panel 100. In addition, the space of the metal layer interposed between the second lead wire portion 222 and the drive transistor T1 can be effectively utilized, eliminating the need to separately provide a metal film layer for forming the first shield pattern 31, which is advantageous for making the display panel 100 thinner.

[0323] Furthermore, other portions of the first shield pattern 31 may be formed on other film layers interposed between the second lead wire portion 222 and the drive transistor T1, but the disclosure is not limited thereto.

[0324] In some embodiments, referring together to Figures 15, 21, and 27, the first subpixel region, the second subpixel region, and the third subpixel region each emit primary color light, which can lead to different luminescence efficiencies in the light-emitting units O (returning to Figure 7) within subpixel regions of different colors, resulting in a tendency for the color display of the display panel 100 to be non-uniform.

[0325] Based on this, two second initialization signal lines V2 may be arranged in correspondence to one sub-pixel driving circuit Q, and these two second initialization signal lines V2 are the first second initialization signal line V2 and the second second initialization signal line V2, respectively. Here, the second initialization signal provided by the first second initialization signal line V2 is different from the second initialization signal provided by the second second initialization signal line V2.

[0326] This allows for the selection of different second initialization signal lines V2 to be electrically connected depending on the luminous efficiency of the light-emitting units O in subpixel regions of different colors. That is, light-emitting units O that are electrically connected to subpixel driving circuits Q in subpixel regions of different colors may be electrically connected to different second initialization signal lines V2. This allows the light-emitting units O to be reset using different second initialization signals, making the brightness of the light emitted by subpixel regions of different colors approximately the same, and enhancing the display effect of the display panel 100.

[0327] In some examples, of the two second initialization signal lines V2, the first second initialization signal line V2 may be formed on the first wiring metal layer SD1, and of the two second initialization signal lines V2, the second second initialization signal line V2 may be formed on the third gate metal layer Gate3. However, embodiments of the present disclosure are not limited thereto, and the second second initialization signal line V2 may also be formed on other configurable film layers.

[0328] In the above embodiment, a schematic explanation was given using an example in which the light-emitting unit O is electrically connected to the first second initialization signal line V2 located in the first wiring metal layer SD1.

[0329] In some of the above embodiments, the film layer structure of the pixel driving circuit of "8T1C" was described, and a configuration in which the shield layer 30 mainly shields the first pole of the driving transistor T1 was introduced. In some other embodiments, it is understood that if the orthographic projection of the second lead wire portion 222 on the base substrate 10 and the orthographic projection of the second pole of the driving transistor T1 on the base substrate 10 overlap, the shield layer 30 can be moved correspondingly between the second pole of the driving transistor T1 and the second lead wire portion 222.

[0330] Furthermore, if the distance between the second lead wire portion 222 and the gate of the drive transistor T1 is short, the shield layer 30 can be placed on the side of the gate of the drive transistor T1 that is closer to the second lead wire portion 222. The disclosure is not limited thereto.

[0331] The foregoing describes only specific embodiments of the Disclosure, but the scope of protection of the Disclosure is not limited thereto. Any modification or substitution that a person skilled in the art could conceive within the technical scope of the Disclosure is included within the scope of protection of the Disclosure. Therefore, the scope of protection of the Disclosure should be determined by the scope of protection of the claims.

Claims

1. The display panel includes a display area, the display area includes a central area and two edge areas, and along a first direction, the central area is located between the two edge areas. The display panel includes a base substrate and a drive circuit layer located on one side of the base substrate. The aforementioned drive circuit layer is A plurality of pixel circuit units arranged in multiple rows and columns within the display area, wherein one pixel circuit unit includes at least one sub-pixel driving circuit, and the sub-pixel driving circuit includes a plurality of pixel circuit units including a driving transistor, A plurality of data writing signal lines located in the display area, arranged along a first direction, and extending along a second direction, wherein the second direction intersects with the first direction, and one data writing signal line is connected to a plurality of data writing signal lines connected to a row of sub-pixel driving circuits. A plurality of data leads, each data lead including a first lead portion and a second lead portion, one end of the first lead portion being electrically connected to a data write signal line located in the edge region, the other end of the first lead portion being electrically connected to one end of the second lead portion, the first lead portion extending along a first direction, the second lead portion extending along a second direction, the second lead portion located in the central region, and the orthographic projection of the second lead portion on the base substrate of the plurality of data leads at least partially overlapping with the orthographic projection of the first pole of at least one of the drive transistors on the base substrate. A shielding layer configured to have a constant voltage signal, comprising at least one first shielding pattern, wherein the first shielding pattern is located between the first pole of the drive transistor and the second lead wire portion, and the orthographic projection of the first shielding pattern on the base substrate, the orthographic projection of the first pole of the drive transistor on the base substrate, and the orthographic projection of the second lead wire portion on the base substrate overlap the shielding layer, Display panel.

2. The orthographic projection of the first shield pattern on the base substrate covers the orthographic projection of the first pole of the drive transistor on the base substrate. The display panel according to claim 1.

3. Along the first direction, the second lead wire portion and the first shield pattern are located on the same side of the gate of the drive transistor. The display panel according to claim 1 or 2.

4. The sub-pixel driving circuit further includes a data writing transistor and a first reset transistor, The first pole of the data writing transistor is electrically connected to one of the data writing signal lines, the second pole of the data writing transistor is electrically connected to the first pole of the drive transistor, and the first pole of the first reset transistor is electrically connected to the gate of the drive transistor. Along the second direction, the first reset transistor in one of the sub-pixel driving circuits in one of the pixel circuit units is located on the side of the data writing transistor away from the driving transistor, and at least a portion of the first lead wire passing through the same pixel circuit unit is located on the side of the first reset transistor away from the data writing transistor. A display panel according to any one of claims 1 to 3.

5. Along the first direction, the first lead wire portion includes a main body portion and a relief portion, the relief portion protrudes from the main body portion toward the side away from the drive transistor, and the relief portion is located toward the side of the first reset transistor toward the data writing transistor. The display panel according to claim 4.

6. The pixel circuit unit includes two sub-pixel driving circuits arranged along the first direction, the two sub-pixel driving circuits being a first sub-pixel driving circuit and a second sub-pixel driving circuit, respectively. The second lead wire portion corresponding to the first sub-pixel driving circuit and the second lead wire portion corresponding to the second sub-pixel driving circuit are adjacent to each other. Furthermore, the first shield pattern in the first sub-pixel driving circuit is provided adjacent to the first shield pattern in the second sub-pixel driving circuit. A display panel according to any one of claims 1 to 5.

7. The first shield pattern in the first sub-pixel driving circuit is electrically connected to the first shield pattern in the second sub-pixel driving circuit, and the first shield pattern in the first sub-pixel driving circuit and the first shield pattern in the second sub-pixel driving circuit are provided on the same layer. The display panel according to claim 6.

8. Along the first direction, the first sub-pixel driving circuit and the second sub-pixel driving circuit are symmetrical. The display panel according to claim 6 or 7.

9. The orthographic projection of the first lead wire portion on the base substrate partially overlaps with the orthographic projection of the data writing signal line on the base substrate. The shield layer further includes at least one second shield pattern, the second shield pattern being located between the first lead wire portion and the data writing signal line, and the orthographic projection of the second shield pattern on the base substrate, the orthographic projection of the first lead wire portion on the base substrate, and the orthographic projection of the data writing signal line on the base substrate overlap. A display panel according to any one of claims 1 to 8.

10. The drive circuit layer further includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first wiring metal layer, and a second wiring metal layer laminated on the base substrate. The first pole of the drive transistor is located in the first semiconductor layer, the first lead wire portion is located in the first wiring metal layer, and the second lead wire portion is located in the second wiring metal layer. The first shield pattern is located in the second gate metal layer and / or the first wiring metal layer. A display panel according to any one of claims 1 to 9.

11. The drive circuit layer further includes a first semiconductor layer, a first gate metal layer, a second gate metal layer, a first wiring metal layer, a second wiring metal layer, and a third wiring metal layer, which are laminated on the base substrate. The first pole of the drive transistor is located in the first semiconductor layer, the first lead wire portion is located in the first wiring metal layer, and the second lead wire portion is located in the third wiring metal layer. The first shield pattern is located in at least one of the second gate metal layer, the first wiring metal layer, and the second wiring metal layer. A display panel according to any one of claims 1 to 9.

12. The drive circuit layer further includes a third gate metal layer, the third gate metal layer being located between the second gate metal layer and the first wiring metal layer. At least a portion of the first shield pattern is located in the third gate metal layer, The display panel according to claim 10 or 11.

13. The pixel circuit unit further includes a first power signal line located in the second wiring metal layer, the first power signal line being configured to supply a constant voltage power signal to the pixel drive circuit, and the first power signal line being electrically connected to the shield layer. A display panel according to any one of claims 10 to 12.

14. The sub-pixel driving circuit further includes a storage capacitor, the first electrode plate of the storage capacitor being electrically connected to the gate of the driving transistor, and the second electrode plate of the storage capacitor being electrically connected to the first power signal line. The first electrode plate of the storage capacitor is located in the first gate metal layer, and the first electrode plate of the storage capacitor further functions as the gate of the drive transistor, and the second electrode plate of the storage capacitor is located in the second gate metal layer. The display panel according to claim 12.

15. The second electrode plate of the storage capacitance includes a first sub-part, and the first sub-part, the first pole of the drive transistor, and the second lead wire overlap in a direction perpendicular to the base substrate, and the first sub-part further functions as the first shield pattern. The display panel according to claim 14.

16. The first wiring metal layer further includes a first connection portion, which is used to electrically connect the second pole of the storage capacitance to the first power signal line, and the first connection portion further functions as the first shield pattern. The display panel according to claim 14 or 15.

17. The aforementioned sub-pixel driving circuit further includes a first light-emitting control transistor, the first pole of the first light-emitting control transistor being electrically connected to the first pole of the driving transistor, and the second pole of the first light-emitting control transistor being electrically connected to a first power signal line. The first wiring metal layer further includes a first joint, which is used to electrically connect the second pole of the first light-emitting control transistor to the first power signal line, and the first joint further functions as the first shield pattern. A display panel according to any one of claims 14 to 16.

18. The display panel further includes a bonding area, the bonding area is located on one side of the display area, the bonding area includes a connecting lead wire, and the other end of the data lead wire is electrically connected to the connecting lead wire. A display panel according to any one of claims 1 to 17.

19. Includes a display panel according to any one of claims 1 to 18, Display device.

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