Hybrid Digital Linear Switched Capacitor Voltage Regulator

JP7652757B2Active Publication Date: 2025-03-27INTEL CORP
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Patent Information

Application Number
JP2022506349
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Priority Date
2019-09-06
Filing Date
2020-08-06
Publication Date
2025-03-27
Estimated Expiration
2040-08-06
Patent Text Reader

Abstract

An on-die voltage regulator is provided that can provide much higher conversion efficiency than traditional solutions (e.g., FIVR, LDO) during standby mode of a system-on-chip (SOC), significantly reducing power consumption during connected standby mode. The VR operates as a switched-capacitor VR under low load current conditions typical during SOC standby mode, while automatically switching to digital linear VR operation to handle sudden high load current conditions upon exiting standby. Using a digital proportional-integral-derivative (PID) controller or a digital proportional-derivative-average (PDA) controller, very low-power operation is achieved, along with stability and robustness. Therefore, the hybrid VR achieves much higher conversion efficiency than a linear voltage regulator (LVR) for low load current conditions (e.g., less than 500 mA).
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