Semiconductor Device

By adopting a three-layer structure semiconductor device and connecting technology through silicon cores, the problem of excessive electrical connection in stacked semiconductor devices is solved, and more efficient signal transmission and equipment performance is achieved.

JP7657747B2Active Publication Date: 2025-04-07NIKON CORP
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Patent Information

Application Number
JP2022014950
Authority / Receiving Office
JP · JP
Patent Type
Patents
Current Assignee / Owner
Filing Date
2022-02-02
Publication Date
2025-04-07
Estimated Expiration
2035-12-11

AI Technical Summary

Technical Problem

In a stacked semiconductor device, the electrical connection between the two semiconductor substrates becomes too long, affecting the performance and efficiency of the device.

Method used

The semiconductor device adopting a three-layer structure realizes electrical connection between the three-layer semiconductor substrates through a silicon core (TSV). The specific steps include: first combining the first and second semiconductor substrates together by bonding or other methods, and thinning the second semiconductor substrate; then combining the third semiconductor substrate with the second semiconductor substrate, and thinning the third semiconductor substrate; finally forming an electrical signal through the silicon core through the silicon core and connecting the three-layer semiconductor substrate through a photolithography and plasma etching technology.

Benefits of technology

Through the three-layer structure and the design through the silicon core, the length of electrical connections in semiconductor devices is significantly shortened, and the efficiency of signal transmission and the overall performance of the device are improved.

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Abstract

The electrical connection between the circuits on the two stacked semiconductor substrates is shortened. [Solution] The semiconductor device includes a first semiconductor substrate on which pixels having photoelectric conversion units that convert light into electric charges and first wiring are provided, a second semiconductor substrate stacked on the first semiconductor substrate and on which memory, second wiring, and third wiring are provided, a third semiconductor substrate stacked on the second semiconductor substrate and on which a signal processing circuit, fourth wiring, and fifth wiring are provided, a first connection portion that penetrates the second wiring and fourth wiring and connects the first wiring, the second wiring, and the fourth wiring, a second connection portion that penetrates the fifth wiring and connects the third wiring and the fifth wiring, and an electrode that is provided on the first semiconductor substrate and connected to wiring that is provided on the third semiconductor substrate.
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