Gaming Machines

Abstract

To provide a game machine in which a performance control operation is further improved.SOLUTION: A game machine has a drawing circuit which generates image data on the basis of a display list DL, and a data transfer circuit which transfers the display list DL to the drawing circuit. An audio performance which outputs an audio signal corresponding to a speech notice is executed behind an issue of a display list identifying a speech. A predetermined NOP command is added to this display list DL, as required, whereby its total bit length is adjusted to an integral multiplication of a transfer bit unit of the data transfer circuit.SELECTED DRAWING: Figure 21

Description

[Technical field]

[0001] The present invention relates to a gaming machine that performs a lottery process based on gaming actions and executes image effects corresponding to the lottery results, and more particularly to a gaming machine that can stably execute powerful image effects. [Background technology]

[0002] A pinball game machine such as a pachinko machine is configured with a pattern start opening on the game board, a pattern display section that displays a series of pattern change patterns based on multiple displayed patterns, and a large prize opening with an opening / closing plate that opens and closes. When a detection switch provided in the pattern start opening detects the passage of a game ball, the machine enters a winning state, and after the game ball is paid out as a prize ball, the displayed pattern in the pattern display section changes for a predetermined period of time. After that, when the pattern stops in a predetermined manner such as 7·7·7, the machine enters a large win state, and the large prize opening is repeatedly opened, creating a game state that is advantageous to the player.

[0003] Whether or not such a game state occurs is determined by a jackpot lottery that is executed on the condition that a game ball enters the symbol start hole, and the above-mentioned symbol change operation is based on the result of this lottery. For example, if the lottery result is a winning state, a presentation operation called a reach action is executed for about 20 seconds, and then the special symbols are aligned. On the other hand, even if the winning state is not won, a similar reach action may be executed, and in this case, the player will pay close attention to the progress of the presentation operation while strongly hoping for a jackpot state. Then, if the predetermined symbols are aligned on the stop line at the end of the symbol change operation, the player is guaranteed a jackpot state.

[0004] Such a pattern changing operation is usually performed on a liquid crystal display. A liquid crystal display is generally composed of pixels of H dots horizontally and V dots vertically, and each pixel of the H x V dots is composed of a basic pixel of the three colors of RGB.

[0005] The driving of each pixel in a liquid crystal display is executed in synchronization with the device's operating clock CK (=dot clock DCK), and pixel driving of H dots corresponding to one horizontal line is repeated in synchronization with a horizontal synchronization signal HS, and when driving of V lines is completed, it is configured to return to pixel driving of the first line in synchronization with a vertical synchronization signal VS (see Figure 40). Therefore, it is necessary for an external device to supply to the liquid crystal display an image signal corresponding to a resolution of H x V dots, together with a horizontal synchronization signal HS, a vertical synchronization signal VS, and a dot clock DCK.

[0006] Here, in order to smoothly perform the display update operation (frame update) of the liquid crystal display, certain conditions are required for the pulse width of each synchronization signal HS, Vs and the timing between each synchronization signal HS, Vs and the transmission timing of the image signal. For example, Figure 40(g) shows an example of the drive timing conditions required for a 640 x 408 dot VGA (Video Graphics Array).

[0007] In the driving conditions shown in the figure, first, the pulse width PWh of the horizontal synchronization signal HS is 96 clocks of the operating clock CK, and the front porch FPh and back porch BPh required before and after the horizontal synchronization signal PWh are specified as 16 and 48 clocks of the operating clock CK, respectively.

[0008] On the other hand, the pulse width PWv of the vertical synchronization signal VS is two lines, and the front porch FPv and back porch BPv required before and after the vertical synchronization signal VS are specified as 19 lines and 33 lines, respectively.

[0009] Therefore, in this LCD display, the operating period of the drive operation for one line, counted by the operating clock CK, is 16+96+48+640 (=800) cycles, and by repeating this vertically for 10+2+33+480 lines (=525), the display for one frame of the display screen is updated.

[0010] The above operation cycle is 800 x 525 counted by the operation clock CK. For example, when the frequency of the operation clock is 25 MHz, the time required to update one frame is 800 x 525 / (25 x 10 6 ) = 16.8mS, which is an operating cycle of about 1 / 60 seconds.

[0011] Then, the external control device that controls the LCD display will repeatedly supply to the LCD display a horizontal synchronizing signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and a horizontal synchronizing signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh), as well as an image signal that corresponds to the number of pixels of the display screen. [Prior art documents] [Patent documents]

[0012] [Patent Document 1] JP 2017-093633 A [Patent Document 2] JP 2017-093632 A [Patent Document 3] JP 2016-159030 A [Patent Document 4] JP 2016-159029 A Summary of the Invention [Problem to be solved by the invention]

[0013] However, in this type of gaming machine, it is desirable to make the various effects more complex and abundant, and there is a particularly high demand for image effects using liquid crystal displays. Therefore, the applicant has made various proposals (Patent Documents 1 to 4), but further sophistication of image effects and further improvements in various effect control operations, centered on image effect control, are desired.

[0014] The present invention has been made in consideration of the above problems, and aims to provide a gaming machine in which various presentation control operations, mainly image presentation control, are further improved. [Means for solving the problem]

[0015] In order to achieve the above object, the present invention provides The present invention provides a CPU circuit having a CPU for executing program processing, a DMAC (Direct Memory Access Controller) circuit divided into a plurality of channel circuits capable of operating in parallel and capable of defining priority, and an operation control register in which a setting value for defining the operation of the DMAC circuit is set, and a VDP (Video Display Processor) ) and a CPU that issues a display list to the VDP functions to execute various performance operations including image performance, the memory space accessible by the CPU includes a plurality of external address spaces that are located outside a CPU circuit including the CPU and each of which can specify a data bus width, while the memory space accessible by the VDP includes a CG memory that stores CG compressed data and a video RAM used to generate image data for image performance, and among the plurality of external address spaces, a predetermined ROM space stores first address information belonging to the external address space and second address information that does not belong to any of the external address spaces in a non-volatile manner, and after resetting the CPU, the second address information is set in a stack pointer of the CPU and the first address information is set in a program counter of the CPU, thereby starting execution of a predetermined initial program, and thereafter, the DMAC circuit functions to enable DMA transfer of data required for the performance operation, and the video RAM is configured to secure a plurality of memory areas based on a base address where all lower bits below a predetermined bit position are 0, and the destination of the expansion of the CG compressed data in the predetermined memory area is specified by the VDP. . Effect of the Invention

[0016] According to the present invention described above, Various production control operations centered on image production control but Furthermore It will be improved. [Brief description of the drawings]

[0017] [Figure 1] 1 is a perspective view showing a pachinko machine according to an embodiment of the present invention. [Diagram 2] 2 is a front view showing a gaming area of ​​the gaming machine of FIG. 1. [Diagram 3] 2 is a block diagram showing the overall circuit configuration of the gaming machine of FIG. 1. [Figure 4] 1 is a diagram illustrating the specifications of a display device. [Diagram 5] FIG. 2 is a block diagram illustrating an internal configuration of the display device. [Figure 6] 2 is a block diagram showing in some detail the circuit configuration of a performance control unit for the gaming machine of FIG. 1. [Figure 7] 1 is a diagram for explaining a composite chip that constitutes a performance control unit. [Figure 8] 5 is a block diagram showing an internal configuration of the CPU circuit shown in FIG. 4. [Figure 9] This illustrates the memory map of the built-in CPU (performance control CPU) of the CPU circuit. [Figure 10] 1 is a diagram for explaining various transfer operation modes (a)-(b) and transfer operation procedures (c)-(e) of a DMAC. [Figure 11] 1 is a diagram for explaining an index space, an index table, a virtual drawing space, and a drawing area. [Figure 12] 1 is a block diagram illustrating an internal configuration of a data transfer circuit together with related circuit configurations. [Figure 13]2 is a block diagram showing the internal configuration of a display circuit together with related circuit configurations. FIG. [Figure 14] 1 is a diagram illustrating a data valid signal ENAB output from a VDP circuit. [Figure 15] 11 is a flowchart illustrating a power reset operation after a CPU reset. [Figure 16] 16 is a flowchart illustrating a memory section initialization process which is a part of FIG. 15. [Figure 17] 16 is a flowchart illustrating a main control process and an interrupt process which are part of FIG. 15. [Figure 18] 11 is a flowchart illustrating a CGROM initialization process which is a part of the main control process. [Figure 19] 13 is a flowchart for explaining a part of the processing contents regarding another interrupt processing. [Figure 20] 13 is a flowchart illustrating the control operation of the performance control CPU 63 when a preloader is not used. [Figure 21] 1 is a diagram for explaining the configuration of a display list. [Figure 22] 13 is a flowchart showing a DL issuing process for issuing a display list DL. [Diagram 23] 23 is a flowchart for explaining the operation of FIG. 22 when a DMAC is involved. [Figure 24] 24 is a flowchart illustrating an operation subsequent to the processing of FIG. 23. [Diagram 25] 13 is a flowchart illustrating the control operation of the performance control CPU 63 when a preloader is used. [Figure 26] 26 is a flowchart illustrating a part of FIG. 25. [Figure 27] 26 is a flowchart illustrating another part of FIG. 25. [Figure 28] 11 is a time chart showing the operation of each part of the VDP in an embodiment in which a preloader is not used. [Figure 29]11 is a time chart showing the operation of each part of the VDP in an embodiment using a preloader. [Diagram 30] FIG. 11 is a block diagram showing an overall circuit configuration according to another embodiment. [Diagram 31] FIG. 31 is a block diagram showing a portion of FIG. 30 in some detail. [Diagram 32] 13 is a flowchart illustrating the operation of another embodiment. [Diagram 33] 11 is a diagram illustrating yet another embodiment. [Diagram 34] 11 is a diagram for explaining an embodiment in which a set value is repeatedly set; [Diagram 35] 1 is a diagram illustrating a circuit configuration of an embodiment using a built-in audio circuit. [Diagram 36] 4 is a flowchart illustrating an initial setting operation of the audio circuit. [Figure 37] 11 is a diagram for explaining another embodiment of a power reset operation after a CPU reset. [Figure 38] 4 is a time chart showing an example of a memory READ operation and a memory WRITE operation. [Figure 39] 11 is a diagram illustrating another embodiment. [Diagram 40] 1 is a diagram illustrating a method of driving a general display device. [Diagram 41] 1 is a diagram illustrating a display list. [Diagram 42] 13 is a diagram explaining a zoom preview. [Diagram 43] 13 is a diagram illustrating a CPU process for realizing a rotation operation. [Diagram 44] 1 is a diagram showing the basis of a calculation formula. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0018] The present invention will be described in detail below based on the embodiments. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM is composed of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached to be able to open and close via a hinge 2 fixed to the outer frame 1. A game board 5 is detachably attached to this inner frame 3 from the front side, not from the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so that they can be opened and closed. In this specification, the glass door 6 and the front panel 7 are collectively referred to as a front door member. The inner frame 3 to which the front door member (glass door 6 and front panel 7) is pivotally attached may be referred to as a game frame.

[0019] Illuminated lamps such as LED lamps are arranged in an approximate C-shape around the periphery of the glass door 6. Meanwhile, a total of three speakers are arranged on the upper left and right positions and on the lower side of the glass door 6. The two speakers arranged on the upper side are configured to output the sounds of the left and right channels R and L, respectively, and the speaker on the lower side is configured to output low-pitched sounds.

[0020] An upper tray 8 for storing game balls to be launched is attached to the front panel 7, and a lower tray 9 for storing game balls that have spilled over or been removed from the upper tray 8, and a launch handle 10 are provided at the bottom of the inner frame 3. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0021] A chance button 11 is provided on the outer periphery of the upper tray 8. This chance button 11 is provided in a position where it can be operated by the player's left hand, and the player can operate the chance button 11 without taking his / her right hand off the launch handle 10. This chance button 11 is not normally functional, but when the game state becomes a button chance state, a built-in lamp is lit and the button becomes operable. The button chance state is a game state that is provided as necessary.

[0022] In addition, a rotary switch type volume switch VLSW is located below the chance button 11, and the player can adjust the speaker volume in eight steps from silent level (=0) to the maximum level (=7) by operating the volume switch VLSW. The speaker volume is initially set by a setting switch (not shown) that can be operated only by the attendant, and the initially set volume is maintained unless the player operates the volume switch VLSW. In addition, the abnormality notification sound that notifies the occurrence of an abnormal situation is emitted at the maximum volume regardless of the initially set volume by the attendant or the volume set by the player.

[0023] An operation panel 12 for operating the ball lending machine is provided on the right side of the upper tray 8, and includes a degree display section that displays the remaining balance on the card in three digits, a ball lending switch that commands the lending of a specified amount of game balls, and a return switch that commands the return of the card when the game ends.

[0024] As shown in Fig. 2, a guide rail 13 consisting of an outer rail and an inner rail made of metal is provided in a ring shape on the surface of the game board 5, and a central opening HO is provided in the approximate center of the guide rail 13. A movable performance body (not shown) is stored in a concealed state below the central opening HO, and during a movable advance notice performance, the movable performance body rises and becomes exposed, thereby realizing an advance notice performance with a predetermined reliability. Here, the advance notice performance is a performance that uncertainly notifies the player that a favorable jackpot state will occur, and the reliability of the advance notice performance means the probability that the jackpot state will occur.

[0025] A main display device DS1 consisting of a large (e.g., 1280 pixels wide x 1024 pixels high) liquid crystal color display (LCD) is disposed in the central opening HO, and a movable sub-display device DS2 consisting of a small (e.g., 480 pixels wide x 800 pixels high) liquid crystal color display is disposed on the right side of the main display device DS1. The main display device DS1 is a device that variably displays specific symbols related to the jackpot state, and also displays background images and various characters in an animated manner. This display device DS1 has special symbol display sections Da-Dc in the center and a normal symbol display section 19 in the upper right. The special symbol display sections Da-Dc may execute reach effects that anticipate the arrival of a jackpot state, and appropriate advance notice effects are executed in and around the special symbol display sections Da-Dc.

[0026] The sub-display device DS2 normally displays image information in a stationary state with its display screen tilted at an angle that is easy for the player to see. However, during a specified preview performance, the display screen changes its tilt angle to an angle that is easy for the player to see, moves to the left in the figure, and displays a specified preview image.

[0027] That is, the sub-display device DS2 of the embodiment is not just a display device, but also functions as a movable performance body that executes the preview performance. Here, the preview performance by the sub-display device DS2 is set to have a high reliability, so that the player pays attention to the movement of the sub-display device DS2 with great expectation.

[0028] In the game area where the game balls fall, there are arranged a first symbol start hole 15a, a second symbol start hole 15b, a first big prize hole 16a, a second big prize hole 16b, a normal prize hole 17, and a gate 18. Each of these prize holes 15 to 18 has a detection switch inside so that it can detect the passage of the game ball.

[0029] Above the first symbol start opening 15a, there is disposed a performance stage 14 configured so that the game ball that enters from the introduction opening IN can enter the first symbol start opening 15 after moving in a seesaw or roulette shape. When the game ball enters the first symbol start opening 15, the special symbol display sections Da to Dc are configured to start varying.

[0030] The second pattern starting opening 15b is configured to be opened and closed by an electric tulip equipped with a pair of opening and closing claws on the left and right, and when the stopped pattern after the normal pattern display section 19 changes displays a winning pattern, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0031] The normal symbol display unit 19 displays normal symbols. When a gaming ball passing through the gate 18 is detected, the normal symbols change for a predetermined period of time and then stop displaying a stopping symbol determined by a random number value for lottery extracted at the time the gaming ball passes through the gate 18.

[0032] The first large prize opening 16a is configured with a slide plate that moves back and forth, and the second large prize opening 16b is configured with an opening and closing plate whose lower end is supported by a shaft and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a is configured to correspond to the first symbol starting opening 15a, and the second large prize opening 16b is configured to correspond to the first symbol starting opening 15b.

[0033] In other words, when a game ball enters the first pattern start opening 15a, the special pattern display sections Da to Dc begin to change in size, and then, when a predetermined jackpot pattern is aligned in the special pattern display sections Da to Dc, a special game representing the first jackpot begins, and the sliding plate of the first large prize opening 16a opens forward, facilitating the entry of the game ball.

[0034] On the other hand, as a result of the change action started by the entry of the game ball into the second symbol start hole 15b, when a predetermined jackpot symbol is aligned in the special symbol display section Da-Dc, a special game as a second jackpot is started, and the opening and closing plate of the second big prize entry hole 16b is opened to facilitate the entry of the game ball. The game value of the special game (jackpot state) varies depending on the aligned jackpot symbols, but which game value is awarded is determined in advance based on the result of a lottery according to the timing of the entry of the game ball.

[0035] In a typical jackpot state, after the opening and closing plate of the big prize opening 16 is opened, the opening and closing plate closes after a predetermined time has elapsed or when a predetermined number of game balls (for example, 10 balls) have entered the prize. This operation continues for a maximum of, for example, 15 times, and is controlled to be in a state advantageous to the player. If the stopped pattern after the change of the special pattern display sections Da to Dc is a specific pattern among the special patterns, a special privilege is given in which the game after the end of the special game will be in a high probability state (probability state).

[0036] Fig. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes the above-mentioned operations. Fig. 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNI arranged on the payout control board 25, and Fig. 3(c) is a diagram explaining the specifications of the main display device DS1 used in this embodiment.

[0037] First, the specifications of the main display device DS1 used in the embodiment will be described with reference to Fig. 3(c). As described above, the display device DS1 is a liquid crystal color display with 1280 horizontal x 1024 vertical pixels, and is configured so that odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the left-right direction are received by the receiver RV (RVa+RVb) through separate LVDS (Low Voltage Differential Signaling) transmission paths. Therefore, in this embodiment, in response to this specification, the ODD signal is transmitted via the first transmission path LVDS1, and the EVEN signal is transmitted via the second transmission path LVDS2 (lower right of Fig. 3(a)).

[0038] In addition, in this display device DS1, the operating clock CK (see FIG. 7) that defines the internal operation of the display device DS1 is specified to have a frequency in the range of 40 MHz to 70 MHz (typical value = 54 MHz). This operating clock CK corresponds to the LVDS clock CLK described later, but for convenience of explanation, the frequency of the operating clock CK is assumed to be a typical value of 54 MHz below. Also, a configuration will be described in which the update time FR (Frame Rate) required to update an image for one frame is made to coincide with approximately 1 / 60 seconds for the 54 MHz operating clock CK.

[0039] The display device DS1 is configured to simultaneously process two adjacent pixels in the left and right direction of the display screen with one operation clock CK based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. As a result, the pixel data of 1280 pixels in one horizontal line is updated with an operation time of 640 / 54MHz=11.85μS, and this operation is repeated for 1024 lines to update the image display of 1280×1024 pixels for one frame. The image is updated line by line in a non-interlaced manner, such as the first line → the second line... → the 1024th line.

[0040] However, as shown in Fig. 3(c), the specifications of the display device DS1 stipulate that a waiting time (blank period) of 204 clocks is provided as a typical value in the horizontal direction, and a waiting time (blank period) of 42 rows is provided as a typical value in the vertical direction. Therefore, the actual screen update period FR taking these blank periods into consideration is calculated based on the above typical value as (204 + 640) × (42 + 1024) / 54 MHz ≒ 16.66 mS, so the frame rate FR is about 1 / 60 Hz.

[0041] For the horizontal waiting time WTh and the vertical waiting time WTv, a tolerance range for the typical value is specified, and in reality, a value different from the typical value described above can be selected. However, to set the frame rate FR=1 / 60 sec, it is necessary to accurately set the horizontal / vertical waiting times WTh / WTv so that (WTh+640)×(WTv+1024) / 54MHz=1 / 60 sec.

[0042] On the other hand, this display device DS1 does not particularly need to receive the horizontal sync signal HS and the vertical sync signal VS, but requires the transmission of an H-level data valid signal ENAB when transmitting the ODD and EVEN signals. In other words, when a significant signal (ODD / EVEN signal) is being transmitted to the transmission paths LVDS1 and LVDS2, the data valid signal ENAB needs to be at an active level (H).

[0043] Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the performance control board 23 and the main display device DS1 are LVDS-connected with a dual link transmission path of an LVDS clock CLK with a frequency of 54 MHz (= 1 / 2 the dot clock DCK) (FIGS. 5 and 13(a)). Also, in the VDP circuit 52 of this embodiment, a horizontal blank period WTh and a vertical blank period WTv that satisfy the specifications of the main display device DS1 are provided, and when image data (ODD / EVEN signals) are output, the data valid signal ENAB is set to an active level (H level).

[0044] That is, as shown in Fig. 4(b), the data valid signal ENAB is configured to be H level only during the horizontal display period THd in the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always L level except for the vertical display period TVd in the vertical synchronization period TV. Note that the horizontal blank period WTh and the vertical blank period WTv adopt values ​​different from their respective typical values ​​(WTh=204 / WTv=42), but the specific design values ​​will be described later with reference to Fig. 14.

[0045] In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operation cycle of the LVDS clock CLK via the differential signal lines RA2 / RB2. The data valid signal ENAB shown in Fig. 4(b) and Fig. 4(c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous discrete DE signal on the time axis. In addition, the vertical synchronizing signal VS and the horizontal synchronizing signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB) on the differential signal lines RA2 / RB, but the main display device DS1 used in the embodiment does not utilize these synchronizing signals VS and HS.

[0046] However, the display device DS1 does not prohibit the transmission of the horizontal sync signal HS or the vertical sync signal VS. However, the internal operations regulated by these sync signals are not executed. In other words, the horizontal line feed timing of the display line is regulated to an optimal timing for the internal circuit of the display device DS1 based on the falling timing of the data valid signal ENAB and the number of operation clocks CK (corresponding to the LVDS clock CLK) after the rising timing of the data valid signal ENAB (640 = 1280 / 2 in the embodiment), regardless of the received horizontal sync signal HS (downward arrow in FIG. 4(b)).

[0047] The same is true for the vertical line feed timing after one frame of image display, which is determined to be optimal for the internal circuitry of the display device DS1 based on the number of consecutive data valid signals ENAB of a predetermined pulse width (1024 in this embodiment) and is not affected by the received vertical synchronizing signal VS (downward arrow in FIG. 4(c)). As such, in this embodiment, since there is no need to transmit the horizontal synchronizing signal HS or the vertical synchronizing signal VS to the display device DS1, there is no need to optimally set the pulse widths PWh / PWv of the synchronizing signals HS and VS, the front ports FPh / FPv, and the back ports BPh / BPv, and the control burden on the performance control unit 23 and the VDP circuit 52 is greatly reduced.

[0048] In addition, the internal operation of the display device DS1 is also such that horizontal and vertical line feed operations are performed at optimal timing based on its own internal configuration, eliminating the risk of unnatural display operation. Incidentally, in the case of a display device that operates based on a horizontal synchronous signal HS or a vertical synchronous signal VS received from the outside, if the pulse width of the synchronous signals HS and VS or the front porch period and back porch period before and after the synchronous signals HS and VS are inappropriate, normal display operation may be impaired.

[0049] 4(a), the first differential signal LVDS1 using the differential signal lines RA0-RA3 and RACLK transmits odd-numbered pixels (ODD signal on side A), and the second differential signal LVDS2 using the differential signal lines RB0-RB3 and RBCLK transmits even-numbered pixels (EVEN signal on side B). In this way, in this embodiment, by transmitting two types of ODD signals and EVEN signals over a dual link transmission path, the frequency of the dot clock DCK can be reduced to 1 / 2, which improves noise resistance and also increases the transmission distance.

[0050] On the other hand, the main display device DS1 has a built-in conversion receiver RV for the ODD and EVEN signals transmitted over the dual link transmission line, and restores the RGB signal from the two LVDS signals (ODD and EVEN signals) to display one frame (1280 x 1024 dots) of image. As explained above, since the RGB signal is composed of 8 bits each, the main display device DS1 can display a gradation of 2 8 ×2 8 ×2 8 A full color image is displayed.

[0051] 5 is a block diagram illustrating the internal configuration of the display device DS1 together with the relevant parts of the VDP circuit 52. As illustrated, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS-parallel conversion unit RVb via the second LVDS line (B side). Of the 8-bit RGB data transmitted over the differential lines SA0 / SB0, image data R0-R5 and G0 are extracted, and image data G1-G5 and B0-B1 are extracted from the differential lines SA1 / SB1.

[0052] Also, image data B2-B5, DE signal, VS signal, and HS signal are output from the differential line SA2 / SB2, and image data G6-G7, R6-R7, and B6-B7 are output from the differential line SA3 / SB3. Here, the DE signal is nothing but the data valid signal ENAB. Also, as mentioned above, the output VS signal and HS signal are not used.

[0053] Next, the LVDS clock CLK of the differential line RACLK / RBCLK is supplied to a PLL circuit to generate an operation clock CK with the same frequency of 54 MHz as the LVDS clock CLK. This operation clock CK regulates the internal operation of the liquid crystal controller LCD_CTL, which processes image data corresponding to two RGB pixels (8 bits x 3 x 2) adjacent to each other in the left and right direction of the liquid crystal panel LCD collectively in synchronization with one operation clock CK.

[0054] Therefore, a pixel with 1280 (=640 x 2) dots in the horizontal direction will be processed in 11.85 μS (=640 / 54 MHz), which is the processing time for 640 operation clocks CK. Note that one pixel is composed of three basic pixels of RGB colors, and the image data of the basic pixels of RGB colors is one byte long each, and has a gradation of 2. 8 ×2 8 ×2 8 Therefore, the image data for all pixels (1280 dots) on one line is 3×1280 bytes long overall.

[0055] As shown in Figure 5, the LCD controller LCD_CNT divides 1280 source signal lines into 2 8 It appropriately controls the source driver SDV, which is driven by a drive signal with (=256) gradations, and the gate driver GDV, which controls the ON / OFF of 1024 gate signal lines. Specifically, the liquid crystal controller LCD_CNT realizes image update operation at a frame rate FR=1 / 60 Hz by appropriately operating each part based on the DE signal extracted from the LVDS transmission line and the operating clock CK. As confirmed earlier, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

[0056] In this embodiment, the source driver SDV is configured by arranging 10 driver elements each having 384 output terminals. As described above, all pixels (1280 dots) on one line of the liquid crystal panel LCD are composed of 3 x 1280 basic pixels of three colors, RGB, so 10 driver elements are required to drive them. Image data DAT is supplied in order from the liquid crystal controller LCD_CNT to these 10 driver elements, which are transferred appropriately based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, the analog-converted drive signal is supplied to 3840 source signal lines. As described above, it takes 11.85 μS (= 640 / 54 MHz) to update all pixels (1280 dots) on one line of the liquid crystal panel LCD.

[0057] On the other hand, the liquid crystal controller LCD_CNT updates the gate signal lines to be driven by supplying a gate start signal GS and a gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured by arranging four driver elements, each with 256 output terminals.

[0058] The update timing of the gate signal line is determined based on the falling edge timing of the DE signal and the operating clock CK, and the horizontal line feed period of the gate signal line is counted by the operating clock CK and is calculated to be 640+204 clocks in typical value calculation (see FIG. 3(c)). Based on the number of DE signals (1024), the gate signal line to be driven is reset to the initial state, and the gate start signal GS is output at the optimal timing, and the output of the gate clock signal GCLK is resumed. The vertical line feed period of the gate signal line is counted by the operating clock CK and is calculated to be 42+1024 clocks in typical value calculation (see FIG. 3(c)). However, as described above, in this embodiment, the display device DS1 is operated with a design different from the typical value (see FIG. 14).

[0059] The main display device DS1 has been described in detail above, but the sub-display device DS2 operates in a similar manner to that shown in Fig. 40, based on the horizontal sync signal HS and vertical sync signal VS received from the VDP circuit 52. However, it is also preferable to adopt a configuration in which the sub-control device DS2 operates based on a data valid signal ENAB, not based on the horizontal sync signal HS or vertical sync signal VS. The data valid signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, not in the form of a discrete DE signal (see the lower right part of Fig. 13(a)).

[0060] Next, returning to Fig. 3(a), the overall circuit configuration of the pachinko machine GM will be described. As shown in Fig. 3(a), this pachinko machine GM is mainly composed of a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) together with AC24V, a main control board 21 that centrally and comprehensively handles game control operations, a performance interface board 22 equipped with circuit elements SND for sound performance, a performance control board 23 that executes lamp performance, sound performance, and image performance in a unified manner based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the performance control board 23 and the display devices DS1 and DS2, a payout control board 25 that controls the payout motor M based on control commands CMD' received from the main control board 21 to pay out game balls, and a launch control board 26 that launches game balls in response to the player's operation.

[0061] The performance interface board 22, performance control board 23, and liquid crystal interface board 24 are directly connected to male and female connectors without using wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made complex and advanced, the storage space of the entire board can be minimized, and noise resistance can be improved by shortening the connection lines.

[0062] As shown in the figure, the control command CMD' output by the main control board 21 is transmitted to the dispensing control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, the control commands CMD and CMD' are both 16 bits long, but are sent in parallel in two batches of 8 bits each.

[0063] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcomputer. The performance control board 23 is equipped with a composite chip 50 with built-in computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51. These control boards 21, 25, 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are sometimes referred to functionally as the main control unit 21, the performance control unit 23, and the payout control unit 25 in this specification. Note that the performance control unit 23 and the payout control unit 25 are sub-control units relative to the main control unit 21.

[0064] This pachinko machine GM is broadly divided into a frame side member GM1 surrounded by a dashed line in Fig. 3(a) and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and an outer wooden frame 1 on the outside of that, and is fixedly installed in the game hall for a long period of time regardless of changes in the model. On the other hand, the board side member GM2 is replaced in response to a change in the model, and a new board side member GM2 is attached to the frame side member GM1 in place of the original board side member. All except the frame side member 1 is the board side member GM2.

[0065] As shown in the dashed frame in Fig. 3(a), the frame side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are fixed to appropriate positions in the inner frame 3. Meanwhile, the main control board 21 and the performance control board 23 are fixed to the back of the game board 5 together with the display devices DS1, DS2 and other circuit boards. The frame side member GM1 and the board side member GM2 are electrically connected by centralized connectors C1 to C3 arranged in one place.

[0066] The power supply board 20 generates three types of DC voltages (35V, 12V, 5V) based on the AC voltage AC24V distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the centralized connection connector C2. The three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. The DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are then distributed to the main control board 21 together with the backup power supply BAK via the centralized connection connector C1.

[0067] The DC 35V is used as a driving power source for the ball feed solenoid and launch solenoid in relation to the launching operation of the game ball, and as a driving power source for the electromagnetic solenoid that opens and closes the electric tulip (variable winning device) and the large winning port 16. The DC 12V is used as a driving power source for the LED lamps and motors controlled by each control board, and as a power source voltage for the digital amplifier, while the DC 5V is used as a power source voltage for the one-chip microcomputer of the payout control board 25 and the main control board 21, and as a power source voltage for the logic elements mounted on each control board. The DC 5V is also stepped down in level by the DC / DC converter of the performance interface board 22, and the stepped down voltages of various levels are used as power source voltages for various computer circuits (such as the composite chip 50 and the voice processor 27).

[0068] The backup power supply BAK is a DC 5V power supply for holding data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after the power is cut off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage of 5V received from the payout control board 25 during game operation.

[0069] On the other hand, after the power is cut off, the backup power supply BAK holds the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the gaming operation before the power is cut off after the power is turned on. Note that the backup power supply board 33 is equipped with an electric double layer capacitor that can hold the memory contents of the built-in RAM of each one-chip microcomputer for at least several days.

[0070] By the way, in this embodiment, unlike the conventional equipment configuration, the power supply abnormality signal ABN indicating an abnormal drop in the AC voltage AC24V is generated not by the power supply board 20 but by the power supply monitor unit MNT of the dispensing control board 25. As shown in FIG. 3(b), the power supply monitor unit MNT is configured to have a full-wave rectifier circuit that rectifies AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits electricity, a phototransistor TR that uses a DC voltage of 5V received from the power supply board 20 as a power source and operates ON based on the emission of the photodiode D, and an output unit that outputs a detection signal ABN (power supply abnormality signal) of H level based on the ON operation of the phototransistor TR. The photodiode D and the phototransistor TR constitute a photocoupler PH.

[0071] In the above configuration, after power is turned on, the photocoupler PH quickly turns ON, causing the power supply abnormality signal ABN to go to a normal level (H). However, if the AC power supply drops abnormally for some reason (normally due to a power cut), the photocoupler PH turns OFF, causing the power supply abnormality signal ABN to go to an abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer of the payout control board 25, and is also transmitted to the one-chip microcomputer of the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the power supply abnormality signal ABN of an abnormal level executes a backup process to store necessary information in its own built-in RAM. As explained above, the information in the built-in RAM is maintained by the backup power supply BAK, so that the game operation before the power cut can be resumed after the power is turned on.

[0072] 3(a), the performance interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as a VDP circuit 52 and an embedded CPU circuit 51. Hereinafter, the embedded CPU circuit may be abbreviated to the CPU circuit.

[0073] The performance interface board 22 is equipped with reset circuits RST3 and RST4 that detect a rise in the power supply voltage when the power is turned on and generate various reset signals RT3 and RT4. First, the reset circuit RST3 generates the reset signal RT3 based on the DC voltages of 12V and 5V distributed from the power supply board 20. The reset signal RT3 then resets the power supply of only the audio memory 28 and is transmitted directly to the performance control board 23.

[0074] As shown in Figure 6(a), the reset signal RT3 transmitted to the performance control board 23 is ANDed with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1, and is output as a system reset signal SYS, which resets the power supply to the CPU circuit 51 and VDP circuit 52 (see Figures 6(a) and 6(d)).

[0075] The reset signal RT3 generated by the reset circuit RST3 maintains the L level as a power reset signal for a predetermined time after power is turned on, and then rises to the H level. However, if either the DC voltage of 12V or the DC voltage of 5V drops thereafter (usually when the power is cut off), the system reset signal SYS also drops to the L level in response to the drop in the level of the reset signal RT3, and the CPU circuit 51 and the VDP circuit 52 of the performance control board 23 are put into a stopped state.

[0076] This system reset signal SYS also changes based on the output of the WDT circuit 58 (normally at H level). Therefore, when the reset signal RT3 is in the H state and the output of the WDT circuit 58 drops to L level due to a program runaway or the like, the system reset signal SYS also changes to L level, abnormally resetting the CPU circuit 51 and VDP circuit 52 (see Figure 6(d)).

[0077] On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3 V generated by dropping the 5 V distributed from the power supply board 20. This reset signal RT4 resets the power supply of the audio processor 27 as a power supply reset signal when the power is turned on.

[0078] As shown in the figure, the reset circuit RST4 is also supplied with a system reset signal SYS returned from the performance control board 23, so when the CPU circuit 51 or VDP circuit 52 is abnormally reset, the audio processor 27 is also abnormally reset in synchronization with the abnormal reset of these circuits. As a result, the audio performance returns to the initial state together with the image and lamp performances, and there is no risk of unnatural audio performance continuing.

[0079] Next, the payout control board 25, which is the frame side member GM1, and the main control unit 21, which is the board side member GM2, are each equipped with reset circuits RST1 and RST2, and are configured so that when the power is turned on, a power reset signal is generated and each computer circuit is power reset.

[0080] In this embodiment, the reset circuits RST1 to RST4 are arranged in the main control unit 21, the payout control unit 25, and the performance interface board 22, respectively, and the system reset signal SYS is not transmitted between the circuit boards. In other words, since there is no wiring cable for transmitting the system reset signal SYS, the risk of the computer circuit being abnormally reset by noise superimposed on the wiring cable is eliminated.

[0081] However, the reset circuits RST1, RST2 provided in the main control unit 21 and the dispensing control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21, 25, each CPU is forcibly reset.

[0082] Furthermore, main control unit 21 is provided with an initialization switch SW that can be operated by an attendant, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW has been turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcomputers of main control unit 21 and dispensing control unit 25, and determines whether or not the entire area of ​​the built-in RAM of the one-chip microcomputer of each control unit 21, 25 should be initialized.

[0083] As explained earlier, the one-chip microcomputers of the main control unit 21 and the dispensing control unit 25 are configured to receive a power supply abnormality signal ABN from the power supply monitor MNT located in the dispensing control unit 25 and initiate the necessary shutdown processing prior to a power outage or closure of business.

[0084] As shown in Fig. 3(a), the main control unit 21 receives a prize ball count signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN from the payout control unit 25. The status signal CON includes, for example, a supply out signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after the power is turned on.

[0085] The main control unit 21 also receives switch signals from detection switches built into each winning hole 16-18 on the game board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate on the power supply voltage VB (12V) distributed from the main control unit 21. Each switch signal indicating the winning status of the symbol start hole 15 is converted to a TTL level or CMOS level switch signal by an interface IC that operates on the power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0086] As explained above, the performance interface board 22 receives various levels of DC voltage (5V, 12V, 35V) from the power supply board 20 via the centralized connection connector C2 (see Figs. 3(a) and 6(a)). The 12V DC voltage is the power supply voltage for the digital amplifier 29 and is also used as the drive voltage for LED lamps and the like. The 35V DC voltage is distributed to appropriate locations in the play frame and is used as the drive voltage for solenoids that reciprocate movable objects.

[0087] Meanwhile, the DC voltage of 5V is supplied as a power supply voltage for the circuit elements in various parts of the performance interface board 22, and is also supplied to two DC / DC converters DC1 and DC2 to generate 3.3V and 1.0V (see FIG. 6(a)). The generated DC voltages of 3.3V and 1.0V are supplied to the audio processor 27 as power supply voltages for I / O (input / output) and the chip core, respectively. The DC voltage of 3.3V also becomes the base voltage for the power supply reset signal RT4 generated by the reset circuit RST4.

[0088] The DC voltage 5V distributed to the performance interface board 22 is distributed to the performance control board 23 together with the 3.3V generated by the DC / DC converter DC1. The DC voltage 3.3V distributed to the performance control board 23 is supplied to the composite chip 50, PROM 53, and CGROM 55 as a power supply voltage.

[0089] As shown in Fig. 6(a), two DC / DC converters DC3 and DC4 are arranged on the performance control board 23, and generate 1.5V and 1.05V based on the DC voltage of 5V supplied to each of them. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as the power supply voltage.

[0090] As shown in Fig. 3(a), the performance interface board 22 receives a control command CMD and a strobe signal STB from the main control unit 21 and transfers them to the performance control board 23. More specifically, as shown in Fig. 6(a), the control command CMD and strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the performance control board 23 via an input buffer 40. Here, the strobe signal STB is a received interrupt signal IRQ_CMD, and the performance control CPU 63 obtains the control command CMD based on an interrupt processing program (interrupt handler) that is started in response to the received interrupt signal IRQ_CMD.

[0091] 6(a), the input buffer 44 of the performance interface board 22 receives switch signals of the chance button 11 and the volume switch VLSW from the frame relay boards 35, 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits to the CPU circuit 51 a 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW, and a 1-bit length indicating the ON / OFF state of the chance button 11.

[0092] The performance interface board 22 is also connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. For convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43 in FIG. 6(a). The input buffer 43a receives the outputs SN0 to SNn of the origin sensor that grasps the current position of the role object, which is the movable performance body (the rotational position of the performance motors M1 to Mn), and transmits them to the CPU circuit 51 of the performance control board 23.

[0093] The lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 transfers the serial signal received from the performance control board 23 to each driver IC. The serial signal is specifically a lamp (motor) drive signal SDATA and a clock signal CK, and the drive signal SDATA is transmitted to each driver IC in a clock synchronization system, and lamp performances using a large number of LED lamps and electric lamps, and role-play performances using performance motors M1 to Mn are executed.

[0094] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2, and the lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 in synchronization with the clock signal CK0 via the frame relay boards 35 and 36. The series of lamp drive signals SDATA0 transmitted as serial signals are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, thereby updating the lighting state of all the lamps at once.

[0095] The above points also apply to the lamp driving board 30, where the driver IC of the lamp driving board 30 receives the lamp driving signal SDATA1 for the lamp group CH1 in synchronization with the clock signal CK1, and simultaneously updates the lighting state of the lamp group CH1 when the operation control signal ENABLE1 changes to the active level.

[0096] Meanwhile, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 by receiving a lamp drive signal transmitted in clock synchronous mode, and drives the performance motor group M1 to Mn, which is composed of a plurality of stepping motors, by receiving a motor drive signal transmitted in clock synchronous mode. The lamp drive signal and the motor drive signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1, and the driver IC that receives them updates the drive state of the lamp group CH2 and the motor group M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0097] Next, the audio circuit SND will be described. As shown in Fig. 6(a), the performance interface board 22 is equipped with an audio processor (audio synthesis circuit) 27 that reproduces an audio signal based on an instruction received from the CPU circuit 51 (performance control CPU 63) of the performance control board 23, an audio memory 28 that stores compressed audio data, which is the original data of the reproduced audio signal, and a digital amplifier 29 that receives the audio signal output from the audio processor 27.

[0098] The sound processor 27 is configured with a built-in WDT circuit that automatically resets the internal circuit settings to default values ​​(initial values) when the internal circuit operates abnormally, and a sound control register SRG. The sound processor 27 accesses the sound memory 28 based on the operating parameters (setting values ​​by sound commands) received by the sound control register SRG from the performance control CPU 63, and reproduces and outputs the required sound signals.

[0099] As shown in FIG. 6(a), the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. 26 ×16) of data can be stored.

[0100] The sound control register SRG is divided into register banks 1 to 6, each of which is identified by a register number from 00H to FFH. Therefore, a predetermined setting operation is realized by the performance control CPU 63 specifying the register bank and then writing a 1-byte operation parameter to the sound control register SRG of a predetermined register number (1 byte long).

[0101] In this embodiment, the register number (00H to FFH) of the sound control register SRG corresponds to the address space CS3 of the performance control CPU 63. For example, when setting an operating parameter YYH in the sound control register SRG with register number XXH, the performance control CPU 63 writes XXH to address zero of the address space CS3, and then writes YYH to address 1. In other words, the performance control CPU 63 writes XXH and YYH in that order to the data bus. In this specification, the subscript H and the prefix 0X / 0x indicate that the numerical value is expressed in hexadecimal.

[0102] In this specification, the address space CS0 to CS7 refers to an external memory (excluding built-in memory) for the CPU circuit 51, which can specify the memory type including the presence or absence of volatility and the data bus width (8 / 16 / 32 bits). The address space CS0 to CS7 is selected by different chip select signals CS0 to CS7, and is configured to be configurable so that the READ / WRITE control signal that functions during READ / WRITE access can be optimized according to the memory type. This setting operation is executed for the bus state controller 66.

[0103] FIG. 6(e) illustrates the setting operation of the audio register SRG by the effect control CPU 63, showing the contents of the 2-bit address bus A1 - A0 and the 1-byte data bus D7 - D0. In this embodiment, the chip select signal CS3 is set at power-on so as to be automatically activated when accessing the address space CS3. This will be described later with reference to FIGS. 8 and 15.

[0104] Anyway, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by the 13-bit phrase number NUM (000H to 1FFFH). A piece of a series of background music (BGM) or a set of effect sounds (preview sounds), etc., up to 8192 types (= 2 13 ) are stored corresponding to the phrase number NUM respectively. And this phrase number NUM is specified by the set value (operation parameter) of the audio command transmitted from the effect control CPU 63 to the audio control register SRG of the audio processor 27.

[0105] As described above, the audio memory 28 having the above configuration is power reset by the reset signal RT3, and the audio processor 27 is power reset by the reset signal RT4. As shown in FIG. 6(c), the reset signal RT4 rises to the H level after a predetermined assert period ASRT (L-level section) after power-on. In this embodiment, thereafter, the internal circuit of the audio processor 27 automatically functions and is configured to execute an initialization sequence process. Note that this initialization sequence process is an internal operation executed in a predetermined procedure, and during the operation of the initialization sequence process, the effect control CPU 63 cannot access the audio register SRG.

[0106] Then, when the internal operation of the initialization sequence process is completed, the interrupt signal IRQ_SND for the CPU circuit 51 changes to L level, and the CPU circuit 51 (performance control CPU 63) executes an interrupt processing program based on the interrupt signal IRQ_SND. Then, the interrupt signal IRQ_SND is returned to H level based on a predetermined command, the details of which will be described further below with reference to FIG. 17(c).

[0107] 6(a), the data bus and address bus of the CPU circuit 51 of the performance control unit 23 extend to the clock circuit (real time clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and is configured so that when the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 can arbitrarily access the internal register (having a 4-bit long address value).

[0108] Moreover, the performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory), which is connected to 16 bits of the address bus and the lower 16 bits of the data bus of the CPU circuit 51, and when the chip is selected by the chip select signal CS4, the game performance information and other information stored in the SRAM (performance data memory) 39 are appropriately read / write accessible by the CPU circuit 51. In the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are assigned to the clock circuit 38, and therefore are not used by the SRAM 39.

[0109] The clock circuit 38 and the performance data memory 39 are driven by a secondary battery (not shown), which is charged appropriately by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is cut off, the clock circuit 38 continues to measure time, and the game performance information stored in the performance data memory 39 is permanently stored (non-volatile). The clock circuit (RTC) 38 is configured to be able to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the date, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed, and in this embodiment, an alarm interrupt that updates the daily game performance information at the end of business each day is used.

[0110] As shown on the right side of Figure 6(a), the performance control board 23 is equipped with a composite chip 50 incorporating a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 that stores the control program for the CPU circuit 51, a DRAM (Dynamic Random Access Memory) 54 that can access large amounts of data at high speed, and a CGROM 55 that stores large amounts of CG data required for performance control.

[0111] 9, in this embodiment, the control memory (PROM) 53 is located in an address space CS0 selected by a chip select signal CS0, and the DRAM (Dynamic Random Access Memory) 54, which is configured as a double-data-rate 3 (DDR), is located in an address space CS5 selected by a chip select signal CS5.

[0112] 7(a) is a circuit block diagram illustrating the composite chip 50 constituting the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL at predetermined time intervals, and a VDP circuit 52 that generates image data based on the issued display list DL to drive the display devices DS1 and DS2. The CPU circuit 51 and the VDP circuit 52 are connected via a CPUIF circuit 56 that relays the data transmitted and received by each other.

[0113] Incidentally, the VDP circuit 52 has a built-in audio circuit SND that performs the same function as the audio processor 27, but in the first embodiment described below, the audio circuit SND is not used. However, if the audio circuit SND built into the VDP circuit 52 is used as in the last embodiment described below, the arrangement of the audio memory 28 and audio processor 27 becomes unnecessary.

[0114] First, the CPU circuit 51 receives the oscillation output (for example, 100 / 3 MHz) of the oscillator OSC1 at the HCLKI terminal and multiplies the frequency (for example, by 8) to generate a CPU operating clock of about 266.7 MHz (see FIG. 13(b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby achieving EMI (Electromagnetic Interference) measures to prevent radio interference / electromagnetic jamming.

[0115] Incidentally, in the case of this embodiment, it is possible to generate the CPU operation clock based on the output of oscillator OSC2 (described later) instead of oscillator OSC1, making oscillator OSC1 unnecessary. However, in a configuration in which a single oscillator is used, the frequency multiplication ratio of the PLL circuit is a fixed value (e.g., 5) the same as that of the system clock described below, so the frequency of the CPU operation clock is 200 MHz (=40 MHz x 5), the same as that of the system clock of the VDP circuit 52.

[0116] While adopting such a configuration has the advantage of sharing the operating cycles of the built-in CPU circuit 51 and the VDP circuit 52, it runs counter to the demand for making the CPU operate as fast as possible. In other words, since the VDP operation cannot be made faster than a certain level, it is not possible to reliably meet the demand for faster CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the operating cycles of the VDP circuit 52 and the CPU circuit 51. Also, by providing a separate oscillator OSC1, the above-mentioned EMI countermeasures can be improved.

[0117] Considering the above, the VDP circuit 52 will be explained. The VDP circuit 52 receives the oscillation output (40 MHz) of an oscillator OSC2, which is separate from the oscillator OSC1, at its PLLREF terminal, and multiplies the frequency in a PLL (Phase Locked Loop) circuit to use it as the system clock for the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly defined by the setting value of a predetermined setting terminal, and in this embodiment, since the setting value of the setting terminal (3-bit PLLMD terminal) is a fixed value of 5, the system clock of the VDP circuit 52 is 200 MHz (=40 MHz x 5) (see FIG. 13(b)).

[0118] In this embodiment, a dot clock DCK that regulates the operation of the display circuits 74A to 74C A ~DCK C The DDR clock of the external DRAM 54 is also generated based on the oscillation output (40 MHz) of the oscillator OSC2. That is, the output (40 MHz) of the oscillator OSC2 functions as a reference clock for the entire VDP circuit 52.

[0119] As will be described later with reference to FIG. 13 and FIG. 14, the display circuits 74A to 74C usually drive display devices with different specifications, so a dot clock DCK that defines the operation of each of the display circuits 74A to 74C is used. A ~DCK CIt is necessary to make the display device to be driven compatible with the specifications. Based on this requirement, in this embodiment, the display circuits 74A to 74C receive one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC, and convert it into the dot clock DCK A ~DCK C It is also possible to configure it as follows.

[0120] When this configuration is used, it is not necessary to design the multiplication ratio and division ratio, which will be described later, or to set the VDP register RGij. A ~DCK C That is, the dot clock frequency F of the main display device DS1 can be easily optimized. DOT1 The oscillation frequency F DOT1 A dedicated oscillator circuit DCLKA is provided, and the dot clock frequency F of the sub-display device DS2 is DOT2 The oscillation frequency F DOT2 It is also possible to provide a dedicated oscillator circuit DCLKB.

[0121] However, when such a configuration is adopted, a dedicated oscillator circuit is required corresponding to the number of display devices, and the device configuration becomes complicated. Therefore, in this embodiment, in order to simplify the device configuration, the dot clock DCK of the display circuits 74A / 74B is generated based on the oscillation output (40 MHz) of the oscillator OSC2. A / DCK B Specifically, as shown in FIG. 13B, for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is multiplied (×108) and divided (1 / 40) to generate a dot clock DCK with a frequency of 108 MHz. A is generated.

[0122] Similarly, for the display circuit 74B that drives the sub-display device DS2, the oscillation output (40 MHz) of the oscillator OSC2 is multiplied (×108) and divided (1 / 160) to obtain a frequency F dot =27MHz dot clock DCK BDesigning these multiplication and division ratios is quite complicated, and it would be easier to provide a dedicated oscillator circuit, but in this embodiment, since emphasis is placed on simplifying the device configuration, a dedicated oscillator circuit is not provided.

[0123] In any case, the dot clock DCK A ~DCK C is set individually for each of the display circuits 74A to 74C, but these dot clocks DCK A ~DCK C In the present specification, the dot clock DCK may be collectively referred to as the "display clock DCK." A or DCK B For convenience, this is sometimes abbreviated as "dot clock DCK."

[0124] In this embodiment, since the configuration of low-speed LVDS output is not adopted, the LVDS clock CLK of the LVDS signal output via the display circuit 74A is also the dot clock DCK A The frequency of the LVDS clock CLK is 108 MHz through the same generation process as in Example 1. However, since a dual link transmission line is used in this embodiment, the actual frequency of the LVDS clock CLK is 54 MHz as explained in relation to Figure 4. If a single link transmission line is used, the frequency of the LVDS clock CLK is 108 MHz.

[0125] As described above, in this embodiment, the oscillation output (40 MHz) of the oscillator OSC2 is utilized as the reference clock for the system clock, the dot clock DCK, and the DDR clock. In consideration of this importance, the oscillator OSC2 is configured to operate at the same power supply voltage of 3.3 V as the VDP circuit 52, and to oscillate and output the reference clock on the condition that the output enable terminal OE is at H level (=3.3 V). In the unlikely event that the power supply voltage of 3.3 V drops below a predetermined level, normal performance operation cannot be expected, so a non-maskable interrupt (NMI) is generated.

[0126] The composite chip 50 is also provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, it is determined whether the boot program (initial setting program) executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL = H) or in some other memory (HBTSL = L). As shown in the figure, in this embodiment, HBTSL is set to the L level, and address zero of the address space CS0 of the performance control CPU 63 is assigned to a place other than CGROM, and specifically, the address space CS0 is assigned to the control memory 53.

[0127] On the other hand, when the HBTSL terminal is set to the H level (see the dashed line), address zero of the address space CS0 of the performance control CPU 63 is assigned to the CGROM 55. In this case, the memory type and bus width (64 / 32 / 16 bits) of the CGROM 55 are specified based on the input values ​​to the 2-bit HBTBWD terminal and the 4-bit HBTRMSL terminal, respectively. These points will be described further below with reference to FIG. 37.

[0128] Next, the CPUIF circuit 56 that relays data transmitted and received between the CPU circuit 51 and the VDP circuit 52 will be described. As shown in Fig. 7(a), a control memory (PROM) 53 that stores control programs and necessary control data in a non-volatile manner, and a work memory (RAM) 57 having a storage capacity of about 2 MB are connected to the CPUIF circuit 56, and each is configured to be accessible from the CPU circuit 51. As described above, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is located in the address space CS6 selected by the chip select signal CS6.

[0129] In this working memory (RAM) 57, a DL buffer BUF is secured to primarily store a display list DL in which a series of instruction commands for specifying each frame of the display devices DS1 and DS2 is described. In the case of this embodiment, the series of instruction commands includes texture load commands such as a TXLOAD command for reading out and decoding (expanding) a pixel material (texture) from the CGROM 55, texture setting commands such as a SETINDEX command having functions such as preliminarily specifying a VRAM area (index space) as a decoding (expansion) destination, primitive drawing commands such as a SPRITE command for arranging the decoded (expanded) pixel material at a predetermined position in the virtual drawing space, environment setting commands such as a SETDAVR command and a SETDAVF command for specifying a drawing area to be actually drawn on the display devices among the images drawn in the virtual drawing space by the drawing commands, and index table control commands (WRIDXTBL) related to an index table IDXTBL for managing the index space.

[0130] Note that FIG. 11(c) illustrates the relationship between a virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), a drawing area that can be arbitrarily set within the virtual drawing space, and an actual drawing area in frame buffers FBa and FBb that primarily store image data output to the display devices DS1 and DS2.

[0131] Next, the CPU circuit 51 is a circuit having the same performance as a general-purpose one-chip microcomputer, and is configured with a performance control CPU 63 that controls image performance in an integrated manner based on the control program in the control memory 53, a watchdog timer (WDT) that forcibly resets the CPU when the program goes out of control, an internal RAM 59 that has a storage capacity of about 16k bytes and is used as a work area for the CPU, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without passing through the CPU 63, a serial input / output port (SIO) 61 having a plurality of input ports Si and an output port So, a parallel input / output port (PIO) 62 having a plurality of input ports Pi and an output port Po, and an operation control register REG in which a set value is set to control the operation of each of the above-mentioned parts. However, in this embodiment in which an external WDT circuit 58 is provided, the watchdog timer (WDT) built into the CPU circuit 51 is not utilized.

[0132] In this specification, for convenience, the term "input / output port" is used, but the input / output port includes an input port and an output port that operate independently in the performance control unit 23. This also applies to the input / output circuit 64p and the input / output circuit 64s described below.

[0133] The parallel input / output port 62 is connected to an external device (performance interface board 22) through an input / output circuit 64p, and the performance control CPU 63 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB through the input circuit 64p. The 3-bit encoder output and 1-bit switch signal are supplied to the parallel input / output port (PIO) 62 through the input / output circuit 64p.

[0134] Similarly, the received control command CMD is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. The strobe signal STB is also supplied to the interrupt terminal of the performance control CPU 63 via the input / output circuit 64p, thereby starting the reception interrupt process. Therefore, the performance control CPU 63, which has grasped the control command CMD based on the reception interrupt process, will perform a performance lottery and the like to uniformly control the sound performance, lamp performance, motor performance, and image performance corresponding to this control command CMD.

[0135] Although not particularly limited, in this embodiment, an SMC (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp and motor performance. The SMC 78 is a composite controller incorporating an LED controller and a Motor controller, and is configured to be able to output a serial signal in a clock synchronous manner. The Motor controller is configured to be able to output a latch pulse at any timing based on a set value in a predetermined control register 70, and is also configured to be able to input a serial signal in a clock synchronous manner.

[0136] Therefore, in this embodiment, the motor drive signal and the LED drive signal are output from the SMC unit 78 in synchronization with the clock signal, while the latch pulse is output as the operation control signal ENABLE at an appropriate timing. Also, the origin sensor signals SN0 to SNn from the performance motor groups M1 to Mn are configured to be input serially in a clock synchronization method.

[0137] 6(a), the clock signals CK0-CK2, the drive signals SDATA0-SDATA2, and the operation control signals ENABLE0-ENABLE2 are transmitted to the predetermined drive boards 30, 31, and 37 via the output buffers 41-43. In addition, the origin sensor signals SN0-SNn are serially input from the motor lamp drive board 31 to the SMC unit 78 via the input / output buffer 43.

[0138] However, in this embodiment, it is not essential to use the SMC unit 78. That is, since the CPU circuit 51 has a general-purpose serial input / output port SIO61 built in, it is also possible to use these to execute lamp effects and motor effects.

[0139] 7(a), the configuration shown by the dashed lines outputs clock signals CK0-CK2 and drive signals SDATA0-SDATA2 via an input / output circuit 64s internally connected to a serial input / output port SIO61, and outputs operation control signals ENABLE0-ENABLE2 via an input / output circuit 64p. Note that, for convenience, these are referred to as input / output ports and input / output circuits, but it is the output ports and output circuits that actually function.

[0140] Here, the serial output port SO is configured to incorporate a 16-stage FIFO register. The DMAC circuit 60 is configured to start upon receiving an operation start instruction (see ST18 in FIG. 20(b)) from the performance control CPU 63, read out the necessary drive data in order from the lamp / motor drive table (see FIG. 20(b)), and DMA transfer it to the FIFO register of the serial output port SO. The drive data stored in the FIFO register is serially output from the serial output port SO in a clock synchronous manner. Note that the DMAC circuit has multiple DMA channels (e.g., seven), and is configured to DMA transfer lamp drive data using the third DMA channel, which has a lower priority, and DMA transfer motor drive data using the first DMA channel, which has the highest priority.

[0141] The operation control register REG built into the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit register with a register number (address value) starting from 0xFF400000, and is configured to be appropriately WRITE / READ accessible from the performance control CPU 63 (see FIG. 9). Therefore, due to the influence of noise, etc., there is a possibility that an irrational value is set in the operation control register REG.

[0142] However, for example, the composite chip 50 can be reset as an abnormality by intentionally executing an infinite loop process to start up the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij in the VDP circuit 52 is also returned to the default value (initial value), thereby eliminating the abnormal state.

[0143] FIG. 6(b) is a diagram illustrating the circuit configuration related to this reset operation, and is a diagram explaining the reset mechanism characteristic of this embodiment. In this specification, the VDP register indicated as RGij does not mean the operation control register REG built into the CPU circuit 51, but any one of the control register group 70 (see FIG. 9) that controls the internal operation of the VDP circuit 52. Also, the system control circuit 520 shown in FIG. 6(b) means the internal control circuit of the VDP circuit 52 that functions based on the set value in the VDP register RGij (any one of the control register group 70 in FIG. 9) (see FIG. 6(a)). In addition, the VDP register RGij is positioned in the address space CS7 selected by the chip select signal CS7 in the address map of the performance control CPU 63.

[0144] 6(b), the composite chip 50 is configured so that the internal circuit can be reset via three OR gates G2 to G4 that receive the logically inverted system reset signal SYS bar. However, in this embodiment, as shown by the dashed line, the built-in WDT is not enabled, so the input terminal and output terminal of the OR gate G2 are directly connected.

[0145] In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is configured to output a reset signal RST on condition that a predetermined keyword sequence (encryption sequence for reset) is received from a parallel input / output port (PIO) 62.

[0146] The internal circuitry of the composite chip 50 is divided into three parts: (1) a CPU circuit 51, (2) a display circuit 74 of the VDP circuit 52, and (3) non-display circuits in the VDP circuit 52, and each part is configured to receive reset signals from the first reset path to the third reset path from OR gates G2 to G4.

[0147] First, the OR gate G2, whose input and output terminals are directly connected, is associated with the first reset path, and is configured to perform a system reset of the entire CPU circuit 51 based on the system reset signal SYS bar. The OR gate G3 is associated with the second reset path, and is configured to receive the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK, and to be able to reset the entire VDP circuit 52 based on OR logic.

[0148] This second reset path is used not only for the power reset operation when the power is turned on, but also when the performance control CPU 63 detects a certain abnormality and abnormally resets the entire VDP circuit 52 to return it to its initial state. Specifically, when it is determined that a serious abnormality has occurred based on a certain status register RGij indicating the internal operation of the VDP circuit 52, the pattern check circuit CHK generates a reset signal RST to abnormally reset the entire VDP circuit 52. The display circuit 74 is abnormally reset via the second reset path → third reset path via the OR gate G4.

[0149] Meanwhile, the internal circuits built into the VDP circuit 52 are configured so that they can be individually reset when necessary via a fourth reset path. The internal circuits that can be individually reset include the index table IDXTBL, data transfer circuit 72, preloader 73, display circuit 74, drawing circuit 76, SMC circuit 78, and audio circuit SND shown in Fig. 7(a), and the ICM circuit shown in Fig. 12.

[0150] The method for realizing an individual reset operation is as described at the bottom of FIG. 6(b). For example, the display circuit 74 is reset via the fourth reset path 4A → the third reset path by writing a first reset value to a predetermined VDP register RGij (system command register).

[0151] Furthermore, each internal circuit (72, 73, 74, 76, SND, ...) of the VDP circuit 52 is individually reset by (1) writing a setting value that identifies the target circuit to the first VDP register RGij (reset RQ register), and then (2) writing a second reset value to a specific VDP register RGij (system command register) (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can be reset not only by the fourth reset path 4B, but also by writing a reset value to a specific VDP register (circuit setting command register) (fourth reset path 4C).

[0152] Since this embodiment has the above configuration, not only does the entire VDP circuit 52 automatically return to the initial state when the power is turned on or the program runs out of control, but also each part can be returned to the initial state as necessary to recover from an abnormal situation. For example, when the drawing circuit 76 freezes because there is no READ / WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is initialized individually via the fourth reset path 4B (see ST16a in FIG. 20(d)). The same is true for the preloader 73 and the data transfer circuit 72, and when a certain abnormality occurs, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in FIG. 27), and the data transfer circuit 72 is initialized via the fourth reset path 4B (see ST27 in FIG. 22 and FIG. 27).

[0153] In addition, when an underrun abnormality continues in which the generation of display data does not keep up with the display timing every 1 / 60 seconds, the display circuit 74 is individually initialized via the fourth reset path 4A or the fourth reset path 4B (see ST10c in FIG. 20). These individual reset operations will be described in more detail later in relation to the program processing described in FIG. 20 and subsequent figures.

[0154] The above describes the reset mechanism characteristic of this embodiment. When any of the reset paths 1 to 4 functions and the internal circuit of the composite chip 50 is reset, the setting value of the VDP register RGij corresponding to that internal circuit returns to the same default value as after power is turned on.

[0155] Next, returning to the internal configuration of the CPU circuit 51, the description of the characteristic circuit configuration will be continued. Fig. 8 is a block diagram showing the internal configuration of the CPU circuit 51 in some detail. The CPU circuit 51 is configured to include many characteristic circuits in addition to the internal RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

[0156] First, the CPU circuit 51 has a separate CPU fetch bus for instructions and a CPU memory access bus for data, realizing a Harvard architecture. Therefore, the fetch operation by which the CPU core (performance control CPU) 63 reads instructions from memory does not conflict with the memory access operation, realizing high-speed processing by making the fetch operation continuous.

[0157] The CPU core 63 is also configured to have a plurality of (e.g., 15) register banks RB0 to RB14, and is configured to be able to select whether or not to use them. In an operating state in which the use of the register bank RBi is permitted, at the start of an interrupt process, the register values ​​(each 32-bit long) of the CPU's built-in registers (e.g., 19 registers) are automatically saved to the free register bank RBi.

[0158] In addition, when a specific restore command is executed at the end of an interrupt process, for example, 19 pieces of saved data are automatically restored to the corresponding built-in registers. This eliminates the need to execute the PUSH command 19 times at the start of an interrupt process and the POP command 19 times at the end of the interrupt process, as in the normal configuration, and achieves high-speed processing.

[0159] Furthermore, the CPU circuit 51 of the embodiment is provided with an instruction cache memory 67, an operand cache memory 89, and a cache controller 69 to realize Harvard cache operation, and when the same address is accessed, cached data is utilized to further speed up program processing. The internal bus is appropriately connected to the peripheral bus (1), the peripheral bus (2), and the peripheral bus (3) by providing a bus bridge 65, a controller for the peripheral bus (1), a controller for the peripheral bus (2), and a controller for the peripheral bus (3).

[0160] Next, in the circuit configuration of Fig. 8, the bus state controller 66 is a part that operates based on appropriate set values ​​in the operation control register REG to optimize memory READ operations and memory WRITE operations with various memory devices connected to the CPU circuit 51. The memory READ operations and memory WRITE operations are executed, for example, at the operation timing exemplified in Fig. 38, but the operation timing of the address data output from the address bus (28 bits), the READ data read out to the READ data bus (32 bits), the WRITE data written out to the WRITE data bus (32 bits), and control signals such as the chip select signals CS0 to CS7 are appropriately specified in accordance with the characteristics of each memory device based on the set values ​​in the operation control register REG.

[0161] The separate READ data bus and WRITE data bus realize the high speed operation by the Harvard architecture mentioned above. In this specification, the address bus (28 bits), READ data bus (32 bits), and WRITE data bus (32 bits) are sometimes collectively called external buses to distinguish them from the internal buses and peripheral buses (1) to (3) shown in Figure 8.

[0162] 9 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and illustrates an address map for the performance control CPU 63 accessed via the bus state controller 66. First, each of the address spaces CS0 to CS7 is specified to a maximum of 64 MB (=0x4000000H=67108864).

[0163] As explained above, the address spaces CS0 to CS7 refer to external memories for the CPU circuit 51, which can specify the memory type including the presence or absence of volatility and the data bus width (8 / 16 / 32 bits). In this embodiment, as shown in Fig. 8(b) and Fig. 9, the control memory (PROM) 53 is located in the address space CS0, the audio control register SRG of the audio processor 27 is located in the address space CS3, the internal register of the clock circuit 38 and the SRAM 39 are located in the address space CS4, the external DRAM (DDR) 54 is located in the address space CS5, the work memory 57 is located in the address space CS6, and the VDP register RGij is located in the address space CS7. The address spaces CS1 and CS2 will not be explained.

[0164] 9, the address space CS0-CS7 is reserved not only for address values ​​0x00000000-0x1FFFFFFF (cache-enabled space) but also for address values ​​0x20000000-0x3FFFFFFF (cache-disabled space). This allows the cache function to be used at will by disabling the cache based on the internal operation of the CPU circuit 51 when the address bit A29=1, and enabling the cache when the address bit A29=0.

[0165] Therefore, in this embodiment, out of the total 32-bit address information (bits A31 to A0), even if the value of bit A29 is either 1 or 0, if the values ​​of the remaining 31 bits (bits A31 to A30 and bits A28 to A0) are the same, the same address in the same memory is specified. For example, whether address 0x18000000 is accessed for READ or address 0x38000000 is accessed for READ, the same data is read from address zero of the work memory 57. Note that when address 0x18000000 is accessed for READ, the read data is stored in the cache, and FIG. 8(b) illustrates the access operation with the cache enabled / disabled.

[0166] Of course, it is also possible to disable the cache operation for the instruction cache and / or the operand cache based on the setting value of a predetermined operation control register REG. However, in this embodiment, after power is turned on, the cache operation for the instruction cache and the operand cache is enabled, and then the cache operation is disabled as necessary by accessing the cache disabled space.

[0167] 9, the address range from 0x40000000 onwards is an internal memory space where the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are assigned to the address array space of the cache. Addresses 0xFF400000 to 0xFFF7FFFF and addresses 0xFFFC0000 to 0xFFFFFFFF are assigned to built-in peripheral modules, specifically, to the operation control register REG of the CPU circuit. The address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

[0168] Continuing the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multifunction timer unit MTU are circuits that count an external signal supplied to the CPU circuit 51 or count a counting clock obtained by multiplying or dividing the internal clock, and generate an interrupt signal or the like when the count result reaches a predetermined value. Although not particularly limited, in this embodiment, the multifunction timer unit MTU is utilized to generate a 1 ms interrupt signal and a 20 μS interrupt signal.

[0169] Next, the interrupt controller INTC is a circuit that receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multifunction timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, IRQ_RCT, etc., and starts interrupt processing (interrupt handler) based on a predefined priority order. Here, IRQ_CMD is a command reception interrupt signal that should receive a control command CMD, IRQ_SND is an end interrupt signal that indicates that the audio processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

[0170] In this embodiment, the command reception interrupt IRQ_CMD has the highest interrupt priority, followed by 20μS interrupt → 1mS interrupt → interrupts from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → IRQ_RCT (see Figure 17(d)). Note that all of these are maskable interrupts, and the non-maskable interrupt NMI is output to the performance control CPU 63 when the reference clock is not being output from the oscillator OSC2, as explained above.

[0171] In any interrupt processing, the register values ​​(each 32-bit long) of the multiple built-in registers of the CPU are automatically saved to any of the free register banks RBi. Then, when a predetermined restore command is executed at the end of the interrupt processing, the saved data is automatically restored to the corresponding built-in register.

[0172] Next, the DMAC circuit 60 will be described. The DMAC circuit 60 of the embodiment is a circuit that repeats data transfer from a transfer source (Source) to a transfer destination (Destination) for each specified data transfer unit a specified number of times in a specified DMA transfer mode based on the set value in a specified operation control register REG. Note that multiple channels DMAC0 to DMACn having the same internal configuration are prepared and can operate in parallel. However, the priority is determined (channel 0>...>channel n), and during parallel operation in the channel arbitration operation mode, the operation of the DMACi with the higher priority is prioritized by channel arbitration at a specified timing.

[0173] As an example of the use of the DMAC circuit 60, in an embodiment in which the serial output port SO functions (see the dashed line in FIG. 9(a)), the operation control register REG of the CPU circuit 51 is specified with the top address of the lamp / motor drive table (top value of the source address), the address of the input register of the serial output port SO (fixed value of the destination address), the data transfer unit (8 bits), and the number of transfers. Then, upon receiving an operation start instruction from a specific operation control register REG, the DMAC circuit 60 DMA transfers the drive data to the specific destination address while updating the source address. Then, when all DMA transfers are completed, a DMAC interrupt (operation end interrupt) is generated.

[0174] This is almost the same in the embodiment (FIG. 23, FIG. 27(c)) in which the DMAC circuit 60 issues the display list DL. That is, the performance control CPU 63 sets the start address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, the number of transfers, and other conditions in a predetermined operation control register REG of the CPU circuit 51. These points will be described further below with reference to FIG. 23.

[0175] Generally, DMA transfer modes include a cycle steal transfer mode in which the DMA operation does not occupy the memory bus, such as by releasing bus control rights in the middle of a unit operation (R operation / W operation) of a DMA transfer, a burst transfer (pipeline transfer) mode in which the bus control rights are not released until a specified number of transfers are completed, such as by consecutively performing multiple R operations or W operations, and a demand transfer mode in which the DMA operation continues while a DMA transfer request (demand) received from another device is active. However, the DMAC circuit 60 of this embodiment functions in a cycle steal transfer mode that provides at least one cycle of memory release period between the read access start (R operation) and the write access start (W operation) during DMA transfer, thereby preventing any disruption to the operation of the performance control CPU 63.

[0176] Fig. 10 is a diagram explaining cycle steal transfer operation (a1) and pipeline transfer (a2). As shown in Fig. 10(a1), the DMAC circuit 60 functioning in cycle steal transfer mode operates with at least one cycle between the read access start (R) and write access start (W) of one data transfer, and in this empty cycle, the performance control CPU 63 can use the bus. As is clear from the comparison between Fig. 10(a1) and Fig. 10(a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in cycle steal transfer mode, the bus is released to the CPU for each read access, so the operation of the CPU is not significantly delayed.

[0177] For example, in an embodiment in which the DMAC circuit 60 is used when issuing a display list DL to the VDP circuit 52, the data transfer unit (one operand) for one cycle is set to 32×2 bits, and the source address of the internal RAM 59 in which the display list DL is stored is appropriately increased (+8 for each operand transfer), while a DMA transfer operation is performed for the transfer port register TR_PORT (see FIG. 12) of the data transfer circuit 72 specified by a fixed address.

[0178] As will be described later, in this embodiment, the total data size is adjusted to a fixed value (for example, 4 x 64 = 256 bytes, or an integer multiple thereof) by adding a required number of NOP (no operation) commands to the display list DL, and the issuance of the display list DL is completed by repeating one operand transfer of 32 bits x 2 times 32 times (or an integer multiple thereof). Note that even if the drawing circuit 76 executes a NOP command, it is in a no operation state, and in effect, no change occurs.

[0179] Furthermore, when classifying the operating modes with respect to the DMA transfer conditions, generally, there are single operand transfer (see FIG. 10(b1)), consecutive operand transfer (see FIG. 10(b2)), and non-stop transfer (see FIG. 10(b3)).

[0180] Here, single operand transfer means an operation mode in which, as shown in Fig. 10(b1), the transfer of one operand is repeated each time a DMA transfer request is issued, and a DMA interrupt request occurs when the byte count, which counts the number of transferred bytes, reaches zero. Next, consecutive operand transfer means an operation mode in which, as shown in Fig. 10(b2), DMA transfer is repeated with one DMA request until the byte count reaches zero.

[0181] In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed each time one operand transfer is completed, and the current channel transfer continues on the condition that there is no DMA request for a channel with a higher priority (channel arbitration operation mode). Therefore, in this embodiment, the single operand transfer method is adopted for issuing the display list DL to the VDP circuit and for DMA transfer of lamp drive data and motor drive data. During parallel operation, the DMACi of the optimal channel is used so that channel arbitration is performed with the priority of motor data>display list DL>lamp data, for example.

[0182] On the other hand, non-stop transfer is an operation mode in which channel arbitration is not performed, and as shown in Fig. 10(b3), DMA transfer is continuously repeated in response to one DMA request until the byte count reaches zero. In this embodiment, in the memory section initialization process at power-on (SP8 in Fig. 15), programs and data are DMA transferred in non-stop transfer.

[0183] Having explained the CPU circuit 51 above, we will now explain the VDP circuit 52. The VDP circuit 52 is connected to a CGROM 55 that stores compressed data that is a component of still images and moving images that make up the image presentation, an external DRAM (Dynamic Random Access Memory) 54 with a storage capacity of about 4 Gbit, a main display device DS1, and a sub-display device DS2. The DRAM 54 is preferably configured with DDR3 (Double-Data-Rate3 SDRAM).

[0184] Although not particularly limited, in this embodiment, the CGROM 55 is configured as a flash SSD (solid state drive) composed of a NAND type flash memory with a storage capacity of about 62 Gbit, and is configured to obtain the necessary compressed data by serial transmission. Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is eliminated, and extremely high-speed transmission operation is possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by an HSS (High Speed ​​Serial) method conforming to Serial ATA.

[0185] Regardless of whether or not the HSS method conforming to SerialATA is adopted, NAND type flash memory is more mechanically stable than a hard disk and allows high-speed access, but since it is a sequential access memory, it has problems with random access compared to DRAM and SRAM (Static Random Access Memory). Therefore, in this embodiment, a preload operation is performed in which a group of compressed data (CG data) is read into the DRAM 54 prior to the drawing operation, thereby realizing smooth random access of the CG data during the drawing operation. Incidentally, the access speed is slower in the following order: built-in VRAM > external DRAM > CGROM.

[0186] In detail, the VDP circuit 52 comprises a control register group 70 in which various operating parameters that define the operation of the VDP (Video Display Processor) can be set by the performance control CPU 63; an internal VRAM (video RAM) 71 of about 48 MB that is used when generating image data to be displayed on the display devices DS1 and DS2; a data transfer circuit 72 that executes data transmission and reception between each part inside the chip and data transmission and reception with the outside of the chip; an index table IDXTBL that can specify address information of the source and destination for the internal VRAM 71; a preloader 73 that can execute a preload operation to read and access the CGROM 55 prior to a drawing operation; a graphics decoder (GDEC) 75 that decodes (decodes and expands / expands) compressed data read from the CGROM 55; a drawing circuit 76 that generates image data for one frame of each of the display devices DS1 and DS2 by appropriately combining still image data and video data after decoding (expanding); The display circuit 74A-74C has three systems (A / B / C) capable of executing appropriate image processing in parallel, an output selection section 79 that appropriately selects and outputs the output of the display circuit 74 of the three systems (A / B / C), an LVDS section 80 that converts the image data output by the output selection section 79 into an LVDS signal, an SMC section 78 that can transmit and receive serial data, a CPUIF section 81 that relays data transmission and reception with the CPUIF circuit 56, a CG bus IF section 82 that relays data reception from the CGROM 55, a DRAMIF section 83 that relays data transmission and reception with the external DRAM 54, and a VRAMIF section 84 that relays data transmission and reception with the built-in VRAM 71 (see FIG. 7(a)). An audio circuit SND is also built in.

[0187] 7(b) shows the relationship between the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, and the VRAMIF unit 84 and the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. As shown in the figure, the CG data acquired from the CGROM 55 is transferred, for example, as preload data, to the preload area of ​​the external DRAM 54 via the data transfer circuit 72 and the DRAMIF unit 83.

[0188] However, the above-mentioned preload operation is not an essential operation, and the data transfer destination is not limited to the external DRAM 54, and may be the built-in VRAM 71. Therefore, for example, in an embodiment in which the preload operation is not executed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAMIF unit 84 (FIG. 7(b)).

[0189] In this embodiment, the built-in VRAM 71 requires a decompression area for compressed data read from the CGROM 55, a frame buffer area for storing image data specifying each ARGB information (32 bit = 8 × 4) of W × H display pixels of the display device, and a Z buffer area for storing depth information of each display pixel. In the ARGB information, A means 8-bit alpha plane data, and RGB means 8-bit data of the three primary colors.

[0190] Here, each of the above-mentioned areas of the built-in VRAM 71 is indirectly accessed based on the various instruction commands (such as the textures and sprites mentioned above) written in the display list DL by the performance control CPU 63, but it would be cumbersome to specify the destination address and source address of the built-in VRAM 71 each time for that READ / WRITE access. Therefore, in this embodiment, in the initial processing after the CPU is reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as index space) required for drawing operations is secured, and an index number is assigned to each index space, making it possible to access based on the index number.

[0191] Specifically, after the CPU is reset, the internal VRAM 71 is roughly divided into three types of memory areas, and the required number of index spaces are secured in each memory area. Then, an index table IDXTBL (see FIG. 11(a)) that associates and stores the index spaces with index numbers is constructed, thereby realizing subsequent operations based on the index numbers.

[0192] This index space needs to be added after (1) initial processing, or conversely, to be released (2). Therefore, a flag area FG is provided in the index table IDXTBL, which can determine whether the timing for adding / release processing is possible or not, and whether the processing such as adding / release has actually been completed or not, during the operation of the performance control CPU 63 for adding / release. The built-in VRAM 71 is roughly divided into three types of memory areas, namely, two AAC areas (a1, a2), a page area (b), and an arbitrary area (c), which will be described below, and the index table IDXTBL is divided into three areas corresponding to the three types of memory areas (a1, a2), (b), and (c) (FIG. 11(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a), but this is not particularly limited, and only one of them may be used. In the following description, the first and second AAC areas (a1, a2) may be collectively referred to as AAC area (a).

[0193] In this embodiment, the built-in VRAM 71 is configured to be divisible into (a) an AAC area in which an index space and its index number are automatically assigned by internal processing and which has a memory cache function, (b) a page area in which an index space can be secured within an integer multiple of a two-dimensional space of, for example, 4096 bits x 128 lines, and (c) an arbitrary area in which a start address (space start address) STx and a horizontal size Hx can be set arbitrarily (see FIG. 11(b)). However, in order to facilitate the internal operation of the VDP circuit 52, the space start address STx of the index space arbitrarily set in the arbitrary area (c) must have the lowest 11 bits 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

[0194] After the CPU is reset, the maximum address space required for each area and the area start address (lower 11 bits = 0) are specified, and the AAC area (a1), the second AAC area (a2), and the page area (b) are secured, and the remaining memory area becomes the arbitrary area (c). In order to facilitate the internal operation of the VDP circuit 52, the maximum address space of the AAC area is specified in units of 2048 bits, and the maximum address space of the page area is an integer multiple of the unit space of 4096 bits x 128 lines described above.

[0195] Next, the necessary number of index spaces are set in each of the areas (a1, a2), (b), and (c) thus secured. When the arbitrary area (c) is used, in order to facilitate the internal operation of the VDP circuit 52, the horizontal size Hx of the index space that handles two-dimensional data can be arbitrarily set as a multiple of 256 bits, while its vertical size is a fixed value (for example, 2048 lines).

[0196] In any case, the first and second AAC areas (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 52, so if the decoding destination is specified as the AAC area (a) by the SETINDEX command, which is a texture setting command, then it is sufficient to specify the source address of the CGROM 55 and the horizontal and vertical size after expansion (decoding) in the TXLOAD (texture load) command that reads CG data from the CGROM 55. Therefore, in this embodiment, the decoding destination is set to the AAC area (a) for still images (textures) such as characters that appear temporarily during preview performances, and I-stream moving images.

[0197] Since both of these AAC areas (a) are provided with a memory cache function, for example, when the same texture of CGROM55 is read into AAC area (a) multiple times, the decoded data cached in AAC area (a) can be used from the second time onwards, and unnecessary READ access and decode processing can be suppressed. However, when AAC area (a) is used up, old data is automatically destroyed, so in this embodiment, when AAC area (a) is used, the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are acquired in the second AAC area (a2).

[0198] Examples of textures that are used repeatedly include characters that appear repeatedly during a specific preview performance, background images when constructing a background screen with still images, etc. In such cases, the SETINDEX command, which is a texture setting command, sets the decoding destination to the second AAC area (a2), and after the TXLOAD command decodes the textures such as the characters and background images into the second AAC area (a2), the second AAC area (a2) is not used to protect the decoded results.

[0199] Then, when the same TXLOAD command is executed to reacquire the acquired texture after specifying the second AAC area (a2) as the decoding destination by the SETINDEX command, the acquired texture will hit the cache, so that it is possible to eliminate the READ access to the CGROM 55 and the time required for the decoding process. As will be described later, such a cache hit function is also exhibited by the preload data pre-read into the preload area, but the significance is that the preload data that hits the cache in the preload area is compressed data before decoding, whereas the cache hit in the AAC area is expanded data after decoding.

[0200] Incidentally, texture is generally a concept that refers to the feel and texture of an object's surface, but in this specification, it is used to include not only sprite image data that makes up a still image, image data that makes up one frame of a video, and image data that is pasted onto drawing primitives such as triangles and rectangles, but also image data after decoding. When copying image data within the built-in VRAM 71 (hereinafter, for convenience, referred to as moving), the source image data is set as a texture by the SETINDEX command, which is a texture setting command, and then the SPRITE command is executed.

[0201] Note that when a SPRITE command is executed, the source Source image data is technically rendered in the virtual rendering space shown in Figure 11(c); however, if the correspondence between the rendering area in the virtual rendering space that is actually rendered on the display device, and the index space that serves as the frame buffer has been set beforehand using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then, for example, when drawing into the virtual rendering space with the SPRITE command, the source Source image data will be rendered in a specified index space (frame buffer) (see Figure 11(c)).

[0202] In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be secured for each area, and each index space is specified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte long, and the performance control CPU 63 can freely assign index numbers within the range of 0 to 255 to the page area (b) and arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuit).

[0203] Therefore, in this embodiment, as shown in Fig. 11(a), a pair of frame buffers FBa is reserved in the arbitrary area (c) for the display device DS1, and index numbers 255 and 254 are assigned to both of the double buffer structure. That is, index space 255 and index space 254 are reserved as frame buffer FBa for the main display device DS1, which are switched in a toggle manner. Although not particularly limited, these index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the display device DS1. Note that each pixel is specified by 32 bits of ARGB information, so the horizontal size 1280 means 32 x 1280 = 40960 bits (a multiple of 256 bits).

[0204] Also, for the display device DS2, another pair of frame buffers FBb are secured in the arbitrary area (c), and index numbers 252, 251 are assigned to both sides of the double buffer structure. That is, index space 252 and index space 251 are secured as frame buffer FBb for the sub display device DS2. These index spaces 252, 251 have a horizontal size of 480, corresponding to the number of horizontal pixels of the display device DS2. In this case as well, each pixel is specified by 32-bit ARGB information, so the horizontal size of 480 means 32×480=15360 bits (a multiple of 256 bits).

[0205] The frame buffers FBa and FBb are reserved in the arbitrary area (c) because the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (=256 bits=8 pixels), and as described above, if it is set to match the number of horizontal pixels of the display devices DS1 and DS2, no waste will occur in the reserved area. On the other hand, the page area (b) can only be set to horizontal / vertical sizes that are integer multiples of the unit space of 128 pixels x 128 lines.

[0206] However, the vertical size of the two-dimensional index space secured in the arbitrary area (c) is a fixed value (for example, 2048 lines). Therefore, in the frame buffer FBa, only an area of ​​horizontal size 1280 × vertical size 1024 becomes the valid data area for the main display device DS1. The same is true for the sub-display device DS2, and in the frame buffer FBb, only an area of ​​horizontal size 480 × vertical size 800 becomes the valid data area for the sub-display device DS2 (see Fig. 11(c) and Fig. 20(e)).

[0207] Although the above points will be described further below, in any case, the frame buffers FBa, FBb are alternately used as the drawing area for the drawing circuit 76 with each double buffer (255 / 254, 252 / 251), and are alternately used as the display area for the display circuits 74A, 74B with each double buffer (255 / 254, 252 / 251). Note that in this embodiment, a missing number (253) occurs because a Z buffer that stores depth information of display pixels is not used, but if a Z buffer is used, the index spaces 253, 250 of index numbers 253, 250 in the arbitrary area (c) become the Z buffers for the display devices DS1 and DS2.

[0208] Furthermore, in this embodiment, when an additional index space (memory area) is reserved in the arbitrary area (c) where the frame buffers FBa and FBb are reserved, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, an index space (0) is reserved in the arbitrary area (c) as a working area for preview performance in which performance images made up of characters and other still images are made to appear in a part of the display screen in an appropriate rotational position as necessary.

[0209] However, the use of a work area is not essential, and index space may be reserved as a work area in the page area (b) instead of the arbitrary area (c). If the page area (b) is used, an index space with dimensions that are multiples of a square unit space of horizontal size 128 (=4096 bits) x vertical size 128 can be reserved, making it suitable for handling small-sized performance images.

[0210] In this embodiment, the background image is also composed of moving images, and the image presentation is realized almost entirely by moving images. In particular, during a variation presentation, a large number of moving images (usually 10 or more) are simultaneously drawn. All of these moving images are stored in the CGROM 55 in a compressed state as a series of moving image frames, and are classified into I-stream moving images composed of I-frames only, and IP-stream moving images composed of I-frames and P-frames. Here, an I-frame (Intra coded frame) means a frame in which an input image is compressed as is, independent of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame in which forward predictive coding is performed, and an I-frame or P-frame located in the past in time is required.

[0211] Therefore, in this embodiment, IP stream video is expanded in the page area (b) rather than the AAC area (a) where there is a concern that old data may be destroyed. In other words, a large number of index spaces (IDXs) are allocated in the page area (b) where an index space of a multiple of 128 horizontal size x 128 vertical size can be secured. 0 ~IDX N) is secured so that a series of video frames are always decoded using the same index space IDXi corresponding to each video MVi. That is, video MV1 is expanded into index space IDX1, video MV2 is expanded into index space IDX2, and so on, video MVi is expanded into index space IDXi.

[0212] To explain the moving image MVi more specifically, the SETINDEX command specifies in advance that the decoding destination of the IP stream moving image MVi is the index space (i) of index number i in the page area (b), and then the TXLOAD command is executed to obtain one frame of the IP stream moving image MVi.

[0213] Then, one frame of video (any of a series of video frames) on CGROM 55 specified by the TXLOAD command is first retrieved into the AAC area (a), and then the retrieved one frame of video is decoded and expanded into the index space (i) of the page area (b) by the GDEC (graphics decoder) 75, which starts automatically.

[0214] On the other hand, in this embodiment, the I stream video is treated the same as a still image, and the SETINDEX command is used to specify that the I stream video MVj is decoded to the first AAC area (a1), and the TXLOAD command is executed. As a result, the video frame is acquired in the first AAC area (a1), and then the GDEC75, which starts automatically, expands the decoded data in the first ACC area (a1). As described above, the index space of the AAC area (a) is automatically generated, so there is no need to specify an index number. The expansion volume required for the index space, that is, the horizontal and vertical sizes of the decoded texture (video frame), are specified by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b).

[0215] Incidentally, the IP stream video MVi and the I stream video MVj are generally composed of N video frames (I frames and P frames). Therefore, the TXLOAD command specifies, for example, the source address of the CGROM 55 in which the kth (1≦k≦N) video frame is stored, and the horizontal and vertical sizes after expansion. Although not limited in any way, in an embodiment in which still images are hardly used, most of the 48 MB address space of the built-in VRAM 71 (about 30 MB) is assigned to the page area (b). In an embodiment in which still images are hardly used, only the first AAC area (a1) is reserved as the AAC area, and the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

[0216] It is also possible to provide a dedicated GDEC (graphics decoder) circuit to speed up the decoding process of the compressed video data. If a dedicated GDEC circuit is built into the VDP circuit 52, it will be sufficient to specify the start address of the compressed video data to the GDEC circuit in the decoding process of the compressed video data consisting of N compressed video frames, and it will not be necessary to specify the start address for each of the N compressed video frames.

[0217] However, if multiple dedicated GDEC circuits like this are built in for each compression algorithm, the internal configuration of the VDP circuit 52 becomes even more complicated. Therefore, in this embodiment, a software GDEC is used, and decoding processing is realized by software processing corresponding to each compression algorithm for data such as IP stream video, I stream video, still images, and other α values. The difference in processing time between hardware processing and software processing is not much of a problem, and it is mainly the access (READ) time from CGROM 55 that is an issue in processing time.

[0218] Returning to Fig. 7(a), the data transfer circuit 72 is a circuit that executes data transfer operations between a resource (storage medium) inside the VDP circuit and an external storage medium as a transfer source port and a transfer destination port in a DMA (Direct Memory Access) manner. Fig. 12 is a block diagram showing the internal configuration of the data transfer circuit 72 together with the related circuit configurations.

[0219] 12, the data transfer circuit 72 is configured to transmit and receive data to and from the CGROM 55, the DRAM 54, and the built-in VRAM 71 via an integrated connection bus ICM having a router function. The CGROM 55 and the DRAM 54 are accessed via a CG bus IF unit 82 and a DMA MIF unit 83.

[0220] On the other hand, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and the preloader 73 via a transfer port register TR_PORT built in the data transfer circuit 72. The CPU circuit 51 and the data transfer circuit 72 are connected bidirectionally, and when issuing a display list DL, the transfer port register TR_PORT functions as a data write port that accepts one unit of data that constitutes the display list DL. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control unit 72d.

[0221] As shown in the figure, the performance control CPU 63 can access the transfer port register TR_PORT for WRITE via the CPUIF unit 81, but when the DMAC circuit 60 is used, the DMAC circuit 60 directly accesses the transfer port register TR_PORT for WRITE. The series of instruction commands written to the transfer port register TR_PORT (that is, the sequence of instruction commands that make up the display list DL) are automatically stored in 32-bit units in the CPU bus control unit 72d that has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

[0222] Also, this data transfer circuit 72 executes data transmission and reception operations through transmission paths of three channels ChA to ChC, and includes a ChA control circuit 72a (N = 130 stages) having a FIFO buffer with a FIFO structure (64 bits × N stages), a ChB control circuit 72b (N = 1026 stages), and a ChC control circuit 72c (N = 130 stages).

[0223] Then, the instruction command sequence (display list DL) stored in the CPU bus control unit 72d is transferred to the drawing circuit 76 or the preloader 73 based on the setting value to the data transfer register RGij (a type of various control registers 70) by the rendering control CPU 63. As shown by the arrow, the display list DL is configured to be transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b and to the preloader 73 via the FIFO buffer of the ChC control circuit 72c.

[0224] In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is transferred to the display list analyzer of the drawing circuit 76 or the preloader 73 as a part of the display list DL via the FIFO buffers of the ChB control circuit 72b and the ChC control circuit 72c, respectively.

[0225] Then, the drawing circuit 76 starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 executes a necessary preloading operation based on the transferred display list DL. By the preloading operation, the CG data in the CGROM 55 is pre-read into the preloaded area secured in the DRAM 54, and a display list DL (hereinafter referred to as a rewritten list DL') in which the source address of the texture is changed for a TXLOAD command or the like is stored in the DL buffer area BUF' secured in the DRAM 54.

[0226] On the other hand, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function for data transfer between storage media such as the CGROM 55, the DRAM 54, and the built-in VRAM 71. Also, the IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71, which requires address information of the index table IDXTBL. Specifically, the ChA control circuit 72a functions, for example, when (a) compressed data of the CGROM 55 is transferred to the built-in VRAM 71, (b) compressed data of the CGROM 55 is preloaded (read ahead) and transferred to the external DRAM 54, or (c) read-ahead data of the preload area is transferred to the built-in VRAM 71.

[0227] Here, the ChA control circuit 72a is configured to be able to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the above-mentioned operations (a) to (c) can be executed in parallel with the issuing operation of the display list DL (ST8 in FIG. 20, PT11 in FIG. 25) and the transfer operation of the rewrite list DL' (PT10 in FIG. 25). The ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously, and for example, the process of step PT10 in FIG. 25 in which the ChB control circuit 72b functions and the process of step PT11 in which the ChC control circuit 72c functions can be executed in parallel. However, since there is only one transfer port register TR_PORT, when one of them (72b / 72c) is using the transfer port register TR_PORT, the other (72c / 72b) cannot access the transfer port register TR_PORT.

[0228] During operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates data transmission with each storage element (CGROM 55, DRAM 54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the embodiment in which the preloader 73 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b (see FIG. 26(b)).

[0229] As described above, the data transfer circuit 72 of this embodiment realizes high-speed data transfer between a data transfer source arbitrarily selected from various storage resources and a data transfer destination arbitrarily selected from various storage resources. As can be seen from Fig. 12, the storage resources in which the data transfer circuit 72 functions include not only the built-in VRAM 71 but also external devices via the CPUIF unit 56, the CG bus IF unit 82, and the DRAMIF unit 83.

[0230] Furthermore, the amount of data transferred between the external device in which the ChA control circuit 72a functions, such as the amount of data to be obtained at one time from the CGROM 55 (memory sequential READ), is enormous compared to the display list DL in which the ChB control circuit 72b or the ChC control circuit 72c functions, and the amounts of data transferred differ greatly between the two.

[0231] Here, it is conceivable to configure these various data transfers so that the unit data amount and the total data transfer amount can be set in detail, but this would complicate the control operation inside the VDP and hinder smooth transfer operations. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total data transfer amount is limited to an integer multiple of the minimum data amount DTmin, thereby realizing high-speed and smooth data transfer operations. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total data transfer amount is limited to an integer multiple of this amount.

[0232] Therefore, the display list DL instruction command sequence stored in the FIFO buffer of the CPU bus control unit 72d for each 32 bits is transferred to the ChB control circuit 72b and the ChC control circuit 72b when the total amount reaches the minimum data amount Dmin, and is stored in each FIFO buffer.

[0233] The display list DL is composed of a series of instruction commands, but in this embodiment, the display list DL is composed of only instruction commands whose command length is an integer N times 32 bits (N>0) corresponding to the write unit (32 bits) of the transfer port register TR_PORT. Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction commands of the display list DL via the data transfer circuit 72 can quickly and smoothly start the command analysis process (DL analyze). Note that the command length of an integer N times 32 bits does not necessarily mean that all bits are significant bits, but also includes don't care bits, meaning an integer N times 32 bits.

[0234] Next, the preloader 73 will be described. As briefly described above, the preloader 73 is a circuit that interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b) and transfers the CG data on the CGROM 55 referenced by the TXLOAD command to the preload area of ​​the DRAM 54 in advance. The preloader 73 also stores a rewrite list DL' in which the reference destination of the CG data is rewritten to the address after transfer for this TXLOAD command in the DL buffer BUF' of the DRAM 54. The DL buffer BUF' and the preload area are secured in advance during the initial processing after the CPU is reset (ST3 in FIG. 20).

[0235] The rewrite list DL' is then transferred to a display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b of the data transfer circuit 72 when the drawing operation of the drawing circuit 76 starts. The drawing circuit 76 then executes drawing operations based on the rewrite list DL'. Therefore, based on a TXLOAD command or the like, CG data that should originally be obtained from the CGROM 55 is obtained from the preload area of ​​the DRAM 54 as preload data pre-read into the preload area. In this case, the preload data can be used repeatedly unless it is overwritten and erased, and preload data that has hit the cache in the preload area is repeatedly reused.

[0236] In this embodiment, the preload area is set in the external DRAM 54, which has a sufficient storage capacity, so the above-mentioned cache hit function works effectively. Also, since the storage capacity of the external DRAM 54 is large, multiple preloading, for example, in which multiple frames of CG data are preloaded at once, is also possible. That is, multiple preloading is realized by appropriately setting the operation period of the preloader 73, which is a series of preload operations including the CG data read-ahead operation, within the range of an integer multiple of the operation cycle δ of the VDP circuit 52 during intermittent operation.

[0237] However, in the following description, for the sake of convenience, an embodiment without multiple preloading will be described, and therefore the preloader 73 of the embodiment will complete the preloading operation for one frame during one operation period (δ). As will be described later with reference to Fig. 20, in this embodiment, the operation period δ during intermittent operation of the VDP circuit 52 is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS1.

[0238] Next, the drawing circuit 76 is a circuit that sequentially analyzes the instruction command sequences of the display list DL and the rewrite list DL' transferred via the data transfer circuit 72, and works together with the graphics decoder 75, the geometry engine 77, etc. to draw one frame's worth of images for each of the display devices DS1, DS2 in a frame buffer formed in the VRAM 71.

[0239] As described above, in the embodiment in which the preloader 73 is operated, the CG data in the rewrite list DL' is referenced not to the CGROM 55 but to the preload area set in the DRAM 54. Therefore, sequential access to the CG data generated during the execution of drawing by the drawing circuit 76 can be quickly executed, and high-resolution moving images with fast movement can be drawn without any problems. In other words, according to this embodiment, it is possible to execute complex and highly advanced image presentation while utilizing an inexpensive SATA module as the CGROM 55.

[0240] Incidentally, regardless of whether the preloader 73 is enabled or disabled, even if data corruption occurs during transfer of the display list DL or the rewrite list DL', the drawing circuit 76 cannot detect this. In addition, the drawing circuit 76 may freeze due to the influence of noise or the like, causing an abnormal stop in READ / WRITE access to the built-in VRAM 71. Therefore, in this embodiment, when the drawing circuit 76 detects an irrational instruction command (a bit sequence that cannot be analyzed) or when there is no READ / WRITE access to the built-in VRAM 71 for a certain period of time, a drawing abnormality interrupt is generated (drawing abnormality interrupt is permitted). This point will be described later with reference to FIG. 20(d).

[0241] Next, as described with reference to FIG. 11, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a read area, and the two areas are used by switching between different applications. In this embodiment, since two display devices DS1 and DS2 are connected, two frame buffers FBa / FBb are secured as shown in FIG. 11. Therefore, the drawing circuit 76 draws one frame of image data in the drawing area (write area) of the frame buffer FBa for the display device DS1, and also draws one frame of image data in the drawing area (write area) of the frame buffer FBa for the display device DS2. When image data is written in the drawing area, the display circuit 74 reads out image data from the other read area (display area) and outputs it to each display device DS1 and DS2.

[0242] The display circuit 74 is a circuit that reads image data from the frame buffers FBa and FBb, performs final image processing, and outputs the result (see FIG. 13(a)). The final image processing includes, for example, a scaling process using a scaler that enlarges or reduces the image, subtle color correction processing, and dithering processing that minimizes quantization errors in the entire image. The digital RGB signal (total of 24 bits) that has undergone these image processes is then normally output together with a horizontal synchronization signal HS, a vertical synchronization signal VS, etc.

[0243] As shown in Fig. 13(a), in this embodiment, three display circuits A / B / C are provided that execute the above operations in parallel, and each display circuit 74A-74C reads image data from the corresponding frame buffer FBa / FBb / FBc and executes the above final image processing. However, in this embodiment, since there are two display devices, the frame buffer FBc is not reserved and the display circuit 74C does not function.

[0244] Here, when checking the specifications of the main display device DS1, the main display device DS1 needs to receive odd pixels (ODD) and even pixels (EVEN) adjacent to the left and right direction at the receiver RV (RVa+RVb) through separate LVDS (Low Voltage Differential Signaling) transmission paths. In addition, the frequency of the operating clock CK of the main display device DS1 needs to be about 40 to 70 MHz (typical value 54 MHz), and the horizontal / vertical waiting time WTh / WTv needs to be set so that (WTh+640)×(WTv+1024) / 54 MHz≒1 / 60 seconds. Furthermore, at the timing when image data (ODD / EVEN signal) is output to the main display device DS1, an active level data valid signal ENAB needs to be output.

[0245] Therefore, the display circuit 74A needs to output a signal that satisfies all of the above specifications. Figures 14(a) to 14(e) show various signals output from the display circuit 74A. First, the frequency of the dot clock (LVDS clock) DCK needs to be determined. In this embodiment, the main display device DS1 is operated by an operating clock CK with a typical value of 54 MHz, so that the designed dot clock DCK (in the VDP circuit 52) ​​is set to 108 MHz (=54×2).

[0246] This is because in a display panel LCD (1280 dots horizontally and 1024 lines vertically) (see FIG. 14(f)), two adjacent pixels on the left and right are processed at once in synchronization with a 54 MHz operating clock CK, which is essentially equivalent to operating with a 108 MHz dot clock DCK.

[0247] And various operation parameters that define the operation of the display circuit 74A are defined based on the dot clock DCK with a frequency of 108 MHz. First, it is necessary to set the horizontal / vertical standby times WTh / WTv so that (WTh + 640) × (WTv + 1024) / 54 MHz ≒ 1 / 60 second. However, for the operation parameters WTh and WTv of the display circuit 74A, it is necessary to satisfy (WTh + 1280) × (WTv + 1024) / 108 MHz ≒ 1 / 60 second.

[0248] Also, regarding the horizontal / vertical standby times WTh / WTv, it is necessary to consider the allowable range in the specifications of the display device DS1. Therefore, in this embodiment, the horizontal standby time WTh is counted with the dot clock DCK of 108 MHz and set to 382 clocks, and the vertical standby time WTv is set to 59 lines. Therefore, the time required for updating an image for one frame is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) is 1 / 60 second.

[0249] This relationship defines the update period FR [seconds] of the display device DS1. Using the frequency F of the dot clock DCK, the number of cycles THc of the horizontal synchronization, and the number of lines TVl of the vertical synchronization described later, FR = THc × TVl / F dot and it becomes. Here, if the update period FR is too long, there is a possibility that abnormalities such as flicker may occur. On the other hand, if the update period FR is too short, the display device cannot execute normal update processing. Therefore, it should be defined in the range of 0.95 / 60 < FR [seconds] < 1.05 / 60. dot

[0250] ​Corresponding to this setting, the data valid signal ENAB is at L level during the waiting time WTh (=382 / 108MHz) corresponding to 382 clocks during the image update operation of each line, and then becomes active level (H) during the active section (=1280 / 108MHz) corresponding to 1280 clocks (Fig. 14(c)). As shown in Fig. 14(d) and Fig. 14(e), during the active section of the data valid signal ENAB, image data is output so that the image update operation for one line of 1280 dots of pixels is completed within a predetermined time (11.85μS=1280 / 108MHz). In other words, 1280 pixel data (Pixel Data) are output in synchronization with 1280 dot clocks DCK. The display device DS1 has a gradation of 2 8 ×2 8 ×2 8 Since a full-color image is displayed, the pixel data for one pixel is 3×8 bits long.

[0251] In this embodiment, the main display device DS1 outputs a vertical sync signal VS and a horizontal sync signal HS, although they are not required. The vertical sync signal VS is output within a vertical wait time WTv, and the horizontal sync signal HS is output within a horizontal wait time WTh. For ease of understanding, each operation period is shown in FIG. 14(a) and FIG. 14(b). Also, in FIG. 14(f), a circle is shown at the top left and bottom right vertices of a rectangular frame specified by TH×TV (=1083×1662 clocks), and "start of display operation" and "end of display operation" are written, but this circle signifies "start of V blank" which specifies the operation period of the display circuit 74A which starts every 1 / 60 seconds. Since the 1083×1662 clocks which specify the display operation coincide with 1 / 60 seconds, the elapsed time from "start of display operation" to "end of display operation" (operation period of the display circuit 74A) is 1 / 60 seconds. The "V blank start" will be described later with reference to FIG.

[0252] Returning to Fig. 13, the output selection unit 79 of the embodiment divides the output signal of the display circuit 74A into dual links by dividing the 108MHz dot clock DCK by two, and transmits them to the LVDS unit 80a and the LVDS unit 80b, respectively (see Fig. 13(a) and Fig. 5). Each of the LVDS units 80a and 80b converts image data (a total of 24-bit digital RGB signal) into a first and a second LVDS signal, adds a pair that transmits a clock signal (54MHz = 108 / 2), and outputs a total of five pairs of differential signals LVDS1 and LVDS2 to the main display device DS1 via two routes (see Fig. 13(a) and Fig. 4).

[0253] As explained earlier, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for an adjacent pixel are processed at the same timing, so that the actual frequency of the operating clock CK matches the 108 MHz dot clock DCK output by the display circuit 74A.

[0254] The above has been explained regarding the display circuit 74A which generates an image to be transmitted to the main display device DS1, but the display circuit 74B generates image data to be transmitted to the sub-display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB section 80c via the output selection section 79, and is transmitted to the sub-display device DS2 together with the vertical synchronizing signal VS and the horizontal synchronizing signal HS.

[0255] Incidentally, together with the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB section 80c. However, it goes without saying that each of these signals is transmitted as a continuous signal, not as discrete values ​​as in the case of an LVDS transmission line (see FIG. 13(a)).

[0256] In this embodiment, the display circuits 74A to 74B are provided with underrun counters URCNTa to URCNTc that count underrun abnormalities that occur when display data is not generated in time with respect to the display timing (see FIG. 14). The counter values ​​of the underrun counters URCNTa to URCNTc are automatically incremented for each VBLANK when an underrun abnormality occurs.

[0257] Next, the SMC unit 78 (Serial Management Controller) is a composite controller with a built-in LED controller and a motor controller. It outputs LED drive signals and motor drive signals in synchronization with a clock signal to an LED / Motor driver (a driver IC with a built-in shift register) mounted on an external board, while being capable of outputting latch pulses at appropriate timing.

[0258] Regarding the internal circuitry and its operation of the VDP circuit 52 described above, the operation content to be executed by the internal circuitry is specified by the operation parameters (setting values) set in the control register group 70 by the performance control CPU 63, and the execution state of the VDP circuit 52 can be specified by reading the operation status values ​​of the control register group 70. The control register group 70 refers to a large number of VDP registers RGij mapped in an address space (0 to FFFFFH) of about 1 MB on the memory map of the performance control CPU 63, and the performance control CPU 63 executes the WRITE (setting) operation of the operation parameters and the READ operation of the operation status values ​​via the CPUIF unit 81 (see FIG. 7(b)).

[0259] The control register group 70 (VDP register RGij) includes a "system control register" in which initial setting values ​​related to system operations such as interrupt operations are written, an "index table register" which determines the AAC area (a) and page area (b) in the built-in VRAM and is used for constructing or changing the index table IDXTBL, a "data transfer register" in which setting values ​​related to data transfer processing by the data transfer circuit 72 between the performance control CPU 63 and the internal circuitry of the VDP circuit 52 are written, a "GDEC register" which specifies the execution status of the graphics decoder 75, a "drawing register" in which instruction commands and setting values ​​related to the drawing circuit 76 are written, a "preloader register" in which setting values ​​related to the operation of the preloader 73 are written, a "display register" in which setting values ​​related to the operation of the display circuit 74 are written, an "LED control register" in which setting values ​​related to the LED controller (SMC unit 78) are written, a "motor control register" in which setting values ​​related to the Motor controller (SMC unit 78) are written, and an "audio control register SRG" in which setting values ​​related to the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not used.

[0260] In any case, in the following description, one or more registers RGij included in the control register group 70 may be referred to by the individual names described above, or may be referred to collectively as VDP registers RGij. In any case, the performance control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate set values ​​to the specified VDP registers RGij. Specifically, the performance control CPU 63 realizes a predetermined image performance based on the display list DL, which is updated at appropriate time intervals, and the set values ​​to the specified VDP registers RGij. In this embodiment, the performance control CPU 63 is in charge of lamp performances and motor performances, so the VDP registers RGij also include LED control registers and motor control registers.

[0261] Next, the unified control operation of the image performance, the sound performance, the motor performance, and the lamp performance, which is realized by the composite chip 50 incorporating the above-mentioned CPU circuit 51 and VDP circuit 52, will be described.

[0262] In this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see FIG. 15(a)) due to power-on or abnormal reset, and is configured to transition to main control processing (SP10) by the performance control program Main and the interrupt processing program (vector handler) Vopt after passing through initial setting processing (SP1-SP9) by the initial setting program (boot program) Pinit. The processing contents of the introductory part of the main control processing are shown in FIG. 17(a), and the processing contents of the main body part are shown in FIG. 20(a). The processing of step SP27 in FIG. 17 includes the processing of steps ST1-ST3 in FIG. 20(a).

[0263] Based on the above, the power-on reset operation will be described with reference to FIG. 15(a). When the system reset signal SYS maintains the L level for a predetermined period (assertion period), such as when the power is turned on, all operation control registers REG and all VDP registers RGij are automatically set to a predetermined default value. Then, when the system reset signal SYS subsequently changes to the H level (negate level), in this embodiment, first, 32-bit data from the top address of the address space CS0 is set in the program counter PC of the performance control CPU 63, and the following 32-bit data is set in the stack pointer SP. In addition, in FIG. 9 and FIG. 16(c), the top area of ​​the memory that stores the initial values ​​of the program counter PC and stack pointer SP is called the vector table VECT.

[0264] As shown in Fig. 15(b), in this vector table VECT, vector numbers that specify priority and interrupt factors, etc., and address information are stored in correspondence with each other. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and the address information stored is the start address of an interrupt processing program executed at the time of an NMI interrupt. Vector number 64 is an internal interrupt (VDP_IRQ0) from the VDP, and the address information stored is the start address of an interrupt processing program executed at the time of a VDP_IRQ0 interrupt.

[0265] 17(d), the start addresses of the interrupt processing programs for the control command receive interrupt IRQ_CMD, the 20μS timer interrupt, and the 1mS timer interrupt are stored in the vector number column smaller than vector number 64. On the other hand, the start addresses of the interrupt processing programs (IRQ_SND, IRQ_RTC, etc.) with a lower priority than VDP_IRQ 1 are stored in the vector number column larger than vector number 64.

[0266] In addition, in the vector table VECT, the vector number 0 and the vector number 1 are regulated as set values ​​to be automatically set in the program counter and stack pointer of the CPU at the time of power-on reset. As shown in FIG. 15(b), in this embodiment, as an internal operation at the time of power-on reset (reset assertion period), 4-byte data "****" is set in the program counter PC, and 4-byte data "++++" is set in the stack pointer SP. Note that "****" is the top address value of the initial setting program Pinit (SP1 to SP9 in FIG. 15) stored in a non-volatile manner in the address space CS0, and "++++" is the address value of the beginning or end of the stack area secured in the internal RAM 59 and functioning in a LIFO (Last-In First-Out) manner.

[0267] In this embodiment, since the register bank RBi is effectively used, the stack area is not consumed during interrupt processing, and so a large memory capacity is not required. In other words, in this embodiment, the stack area is used exclusively for function processing and subroutine processing.

[0268] As a result of the above operations, the performance control CPU 63 will then execute the initial setting program Pinit written after the address value "****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG that specifies the operation of the bus state controller 66 (Fig. 8). The initial value of this operation control register REG is a value that is automatically set during the reset assertion period (the period shown in Fig. 6(d) during which the system reset signal SYS maintains the L level), and is set to the slowest READ access operation (default access operation) so that no matter what memory device the address space CS0 is configured with, READ access can be performed without any problems.

[0269] Therefore, in order to change this default access operation to an optimal access operation, first, an optimal value is set in a predetermined operation control register REG that specifies the operation of the bus state controller 66 (FIG. 8) for the address space CS0 (SP1). That is, in order to optimize the memory READ operation when accessing the PROM 53 that stores the initial setting program Pinit (SP1-SP9), the performance control program MainB (SP10), constant data, etc., according to the memory device, the bus width and the presence or absence of page access are set, and the operation timing of the chip select signal CS0, the READ control signal, the WRITE control signal, and other signals are optimally set (see FIG. 38).

[0270] As a result of the above settings, the processing from step SP2 onwards will be executed by optimally reading the program stored in the address space CS0 from memory. Next, in order to optimise the READ / WRITE access operation when the performance control CPU 63 accesses the VDP register RGij, an optimal value is set in a predetermined operation control register REG that specifies the operation of the bus state controller 66 (Fig. 8) for the VDP register RGij (SP2).

[0271] As explained earlier, in this embodiment, the VDP register RGij is positioned in the address space CS7 of the performance control CPU 63, so a predetermined value is written to a predetermined operation control register REG in order to optimally set the operation timing of the chip select signal CS7 and other control signals.

[0272] Next, the register value of a specific VDP register RGij is read out, and it is determined whether or not the value is a predetermined value (device code) (SP3). This is a confirmation and determination as to whether the system clock of the VDP circuit 52 has stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, and this is a determination as to whether or not the VDP circuit 52 can normally accept commands from the CPU circuit 51 (i.e., settings to the VDP register RGij, etc.).

[0273] Then, if it is confirmed by the device code read process (SP3) that the system clock has stabilized, then normal operation of the VDP circuit 52 can be expected, and setting processes for the predetermined VDP register RGij are executed (SP4 to SP6). Specifically, first, the endian setting (big / little) and the data bus width when the performance control CPU 63 accesses the VDP register RGij are set (SP4).

[0274] In this embodiment, the most significant bit of the setting value is set to big endian and stored in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits, but if these setting values ​​are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

[0275] Next, the interrupt significance level (H / L) is set for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit, and a setting is made to operate the DDR (DRAM 54) based on the clock signal (reference clock) to the PLLREF terminal (see FIG. 7(a)) (SP4). Note that the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal, as explained with reference to FIG. 7(a).

[0276] Next, address spaces CS1 to CS6 are defined (SP5) to realize the memory map shown in Fig. 9. As described above, address space CS3 is assigned to the internal register of the audio processor 27, address space CS4 is assigned to the internal register of the RTC 38 and the address space of the SRAM 39, address space CS5 is assigned to the external DRAM (DDR) 54, and address space CS6 is assigned to the work memory 57 of the built-in CPU.

[0277] Since it is fixedly specified that the VDP register RGij is assigned to the address space CS7, there is no need to define the address space CS7. Also, it is fixedly specified in advance that the address space CS0 is after address 0x000000000 in the memory map of the CPU circuit 51. Based on this specification, whether the address space CS0 is secured in the CGROM 55 or assigned to another memory device is specified by the H / L level of the HBTSL terminal.

[0278] As explained above, in this embodiment, the HBTSL terminal is set to L, which indicates that the address space CS0 is defined in addition to the CGROM 55. And, since the specific bus width and optimal access operation of the control memory 53 other than the CGROM 55 have already been set in step SP1, the process of step SP5 is not required for the address space CS0 either.

[0279] Next, for the address spaces CS1 to CS6 defined in the process of step SP5, a predetermined value is written to a predetermined operation control register REG regarding the bus width and the presence or absence of page access when accessing each address space CSi (SP6). Also, in order to optimally set the chip select signal CSi and others, a predetermined value is written to a predetermined operation control register REG (SP6). These processes are the same as those of steps SP1 and SP2, and the chip select signal CSi, READ control signal, WRITE control signal, and other operation timings are optimally set by the write process to the operation control registers that define the operation of the bus state controller 66 (FIG. 8).

[0280] Next, a clear signal is output to the WDT circuit 58 to avoid an abnormal reset (SP7). This is because the WDT circuit 58 automatically starts operating after power is turned on, and similar processing is executed repeatedly thereafter. The processing of step SP9 is stored in the control memory 53 as a subroutine SP7, but until the end of step SP9, the subroutine SP7 in the control memory 53 is called, and after the end of step SP9, another subroutine SP7' transferred to the external DRAM 54 is called and executed.

[0281] Next, among the programs and data stored in address space CS0, the vector handler Vopt (interrupt processing program), error recovery processing program Piram, performance control program MainB, variables with initial values ​​D, and constant data C shown in Fig. 15(b) and Fig. 16(c) are transferred to external DRAM 54 or internal RAM 59 (SP8). Note that variables with initial values ​​D refer to initial value data stored in a specified variable area. This memory section initialization process (SP8) is a process for transferring programs and data in order to speed up performance control processing, and is a process for avoiding access to ROM, which has a slower access speed.

[0282] Next, a setting is made to use the register bank RBi (SP9). Therefore, thereafter, the register banks RB0 to RB14 function during interrupt processing, speeding up the interrupt processing and reducing the consumption of the stack area.

[0283] The above processing is realized by executing the "initial setting program Pinit" stored in the control memory 53, which is the address space CS0 (see FIG. 16(c)). Then, once execution of this initial setting program Pinit is completed, the main control processing is executed by the performance control program Main (SP10). Here, execution of the main control processing means execution of the "performance control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer processing of step SP8 (see FIG. 15(b)).

[0284] The specific contents of the main control process (performance control program Main) will be explained based on Fig. 17(a) and Fig. 20(a), but before that, the memory section initialization process (SP8) will be explained. As shown in Fig. 16(a), in the memory section initialization process (SP8), first, the DMACs of multiple channels are initialized to a stopped state. Note that this process is merely a formality just to be sure.

[0285] When the above processing is completed, the DMACi of the specified channel is started, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is DMA transferred by the non-stop transfer method (see FIG. 10(b3)) to the internal RAM 59. In this embodiment, since the interrupt processing program Vopt is transferred to the internal RAM 59, appropriate abnormality response processing is possible even when an abnormality occurs in the external DRAM 54.

[0286] The subsequent processing is the same, and is executed in a non-stop transfer mode using the DMACi of a specified channel, and the error recovery processing program Piram is DMA-transferred to the internal RAM 59 (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the internal RAM 59, the peripheral circuits can be reliably reset during the error recovery processing. For example, if the error recovery processing program Piram is transferred to an external DRAM 54, for example, other than the internal RAM 59, the external DRAM 54 cannot be reset during the error recovery processing.

[0287] Next, the performance control program Main is DMA transferred to the external DRAM 54 (SP63), and the constant data C is DMA transferred to the external DRAM 54 (SP64). The constant data includes lottery data used in the performance lottery, and lamp drive data and motor drive data in the various drive data tables shown in Fig. 20(b). In addition, a variable D with an initial value is DMA transferred to the external DRAM 54 (SP65), and all of these are executed by a non-stop transfer method using the DMACi of a specified channel.

[0288] Finally, clear data is written to the beginning of variable area B in the external DRAM (SP66). If this beginning address is assumed to be ADb, then in the subsequent DMA transfer process, the source address is initially set to ADb and the destination address is initially set to ADb+1, and then the clear data is diffused while the address values ​​ADb and ADb+1 are incremented, thereby executing the clear process of variable area B (SP67).

[0289] The above-described steps SP61 to SP66 and step SP67 are all similar operations, as shown in Fig. 16(b). That is, first, for the DMACi of a predetermined channel, the following DMA transfer conditions are set (SP68): (1) cycle steal transfer mode, (2) non-stop transfer method, and (3) source and destination address values ​​are incremented.

[0290] Next, the initial values ​​of the source address and destination address are set (SP69), the transfer size is set, and interrupts are disabled (SP70), and then the DMA transfer operation is started (SP71). Note that the settings in steps SP68 to SP71 are all realized by setting a predetermined operation control register REG.

[0291] In the initialization process for this memory section, an interrupt upon completion of DMA transfer is prohibited (SP70), so after starting the DMA transfer operation, the status flag of a specified operation control register REG is repeatedly read and accessed to wait for the completion of the DMA transfer (SP72). However, taking into consideration the processing time until the operation ends, a clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, when the DMA transfer ends, the DMACi is stopped based on the setting operation to the specified operation control register REG.

[0292] Next, the operation contents of the main control process will be described with reference to Figures 17 to 20. As described above, the process contents of the introductory part (SP20 to SP27) of the main control process are shown in Figure 17(a), and the process contents of the main part (ST4 to ST14) are shown in Figure 20(a). Note that the process of step SP27 in Figure 17 includes the processes of steps ST1 to ST3 in Figure 20(a).

[0293] As shown in Fig. 17(a), in the main control process (introduction), first, the bus width and the type of ROM device of the CGROM 55 are specified (SP20). Specifically, as shown in Fig. 18(a), a predetermined VDP register RGij (e.g., a CG bus status register) that specifies the operating state of the CG bus that controls the interface with the CGROM 55 is accessed for READ (SP80), and it is determined whether the operation of the CG bus can be set (SP81).

[0294] If the value of the CG bus Status register is 1, it means that the internal circuit of the CG bus is undergoing a reset operation, and the set value for the VDP register RGij cannot be accepted. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), the CPU sets operational parameters such as (1) enable / disable of each device section SPAi, (2) ROM device type, and (3) data bus width in the specified VDP register RGij for each device section (SPA0-SPAn) that can be defined corresponding to the memory devices that make up the CGROM (SP82).

[0295] 17(a), in this embodiment, the CGROM 55 can be divided into a plurality of areas (device sections), and for example, the memory device and data bus width can be selected for each device section (SPA0 to SPAn). The memory devices are roughly classified into, for example, (1) the SATA module (AHSI / F) used in this embodiment, (2) memory elements using a parallel I / F (Interface) format, and (3) memory elements using a sequential I / F format, and for each roughly classified memory device, the memory device can be specifically selected, and the data bus width, etc. can be arbitrarily specified.

[0296] Next, in order to optimize the memory READ operation with the memory device selected for each device section (SPA0 to SPAn), a predetermined operation parameter is set in a predetermined VDP register RGij (SP83). The operation parameter includes a set value that specifies the operation timing of the chip select signal and other control signals (such as the READ control signal). In addition, when a memory element that adopts a sequential I / F format is selected, the output timing of the address latch and the number of read clocks are also specified to realize the operation shown in FIG. 18(b).

[0297] Therefore, it is possible to combine different types of memory devices to configure the CGROM 55. However, in this embodiment, the CGROM 55 is configured using only SATA modules, only the device section (SPA0) is enabled, and the other device sections (SPA1 to SPAn) are disabled.

[0298] In any case, when the setting process of steps SP82 to SP83 is completed, a predetermined value is written to a predetermined VDP register RGij in order to execute the setting process (SP84). This is because it takes a certain amount of time for the internal circuitry of the CG bus to be able to operate in response to the setting process of steps SP82 to SP83, and while the internal circuitry is operating, the value of the CG bus Status register (see SP80) is 0.

[0299] Therefore, thereafter, the CG bus Status register is repeatedly accessed for reading (SP85), and processing ends after confirming that the value of the Status register has returned from 1 to 0 (SP86). Note that regardless of the predetermined number of judgments, if the value of the Status register has not returned from 1 to 0, processing of step SP66 may end. In that case, however, the game processing will start in a state in which the CGROM cannot be accessed normally, and the WDT circuit 58 will then start up at some point and the composite chip 50 will enter an abnormal reset state. In this case, the power-on reset operation will be executed again.

[0300] On the other hand, after the processing of step SP20 in FIG. 17 is executed normally, the internal circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing (SP21).

[0301] Next, for the multifunction timer unit MTU, a predetermined timer measurement operation is started (SP22), and then a permission setting value is written to a predetermined operation control register REG for internal interrupts and internal interrupts to set the interrupt permission state (SP23).

[0302] As a result, various interrupts shown in Fig. 17(d) may occur after that. Normally, at this timing, the sound processor 27 has finished its initialization sequence, so the end interrupt signal IRQ_SND should have dropped to L level as shown in Fig. 6(c). Therefore, the interrupt process shown in Fig. 17(c) is started, and the performance control CPU 63 initializes the error flag ERR to 1, and performs READ access to the address space CS3 (SP30), obtains the value of a predetermined sound register SRG of the sound processor 27, and determines whether the initialization sequence has been completed normally (SP31).

[0303] Then, in the unlikely event that the initialization sequence has not ended normally, the performance control CPU 63 writes a reset command to a predetermined sound register SRG of the sound processor 27 (SP32), and sets the error flag ERR, which is initially set to 1, to 2 (SP33). This error flag ERR specifies whether or not to execute the sound processor initialization process (SP26), and the error flag ERR=1 is the execution condition for step SP26.

[0304] On the other hand, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the end interrupt signal IRQ_SND at H level, and when the initialization sequence ends, drops the end interrupt signal IRQ_SND to L level, resulting in the process of FIG. 17(c) being executed again.

[0305] The above describes the exceptional case where the initialization sequence does not end normally, but normally, following step SP31, the processing of step SP32 is executed, and the performance control CPU 63 writes a predetermined value to a predetermined sound register SRG, thereby returning the termination interrupt signal IRQ_SND from L level to H level (SP34).

[0306] Finally, a predetermined value is written to a predetermined voice register SRG, thereby permitting READ / WRITE access to all voice registers SRG (SP35). As a result of this process, the necessary setting process can be executed in the subsequent voice processor initialization process (SP26).

[0307] An example of a maskable interrupt corresponding to the interrupt permission setting in step SP23 has been described above, but a non-maskable interrupt based on the oscillation stop of oscillator OSC2 can be activated at any timing. As explained above, the operating clock (CPU system clock) of the circuits other than the built-in CPU (performance control CPU 63) is generated by multiplying the frequency of the output clock of oscillator OSC2 by a PLL (Phase Locked Loop), and if the oscillation of oscillator OSC2 is stopped, normal operation of the VDP circuit 52 thereafter is impossible.

[0308] On the other hand, the operating clock of the performance control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by a PLL, so that program processing can continue. Moreover, the interrupt processing program is stored in the built-in RAM 59. Therefore, the performance control CPU 63 notifies the occurrence of an abnormality by sound or lamp (SP28), and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality notification is, for example, a sound notification saying "An abnormality has occurred. Please contact a staff member immediately." The reason for continuing to output the clear signal to the WDT circuit 58 is to avoid an abnormal reset operation. In other words, in the event of a serious abnormality in which the oscillator OSC1 stops operating, it is considered that the device cannot be expected to return to normal even if the abnormal reset process is repeated.

[0309] 17(b) and 17(c) have been explained above, so let's go back to Fig. 17(a) and continue the explanation. In step SP24, in order to protect the program area of ​​the external DRAM, the necessary areas are set to be write-protected. Next, for the clock circuit 38 that is battery-powered when the power is cut off, normal operation at the time of power cut is confirmed, and the alarm interrupt is reset just to be sure (SP25).

[0310] Then, on condition that the error flag ERR=1, the necessary setting values ​​are written to the built-in register (voice register SRG) of the voice processor 27 to execute initialization processing (SP26). Note that if the error flag ERR=0, a predetermined time is waited until the error flag ERR=1, but if the limit time is exceeded, an infinite loop process is started to start the WDT circuit 58.

[0311] Next, necessary setting values ​​are written to the VDP register RGij to execute initialization processing of the VDP circuit 52 (SP27). Note that the processing of step SP27 includes the processing of ST1 to ST3 in FIG.

[0312] Although an embodiment in which the end interrupt signal IRQ_SND is received from the audio processor has been described above, it is also preferable to omit the interrupt process in Fig. 17(c). Fig. 19 shows a modified embodiment in which a 1 ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the end interrupt signal IRQ_SND.

[0313] 19 shows a part of the 1 ms timer interrupt process, which realizes four stages of operation based on the value (0 / 1 / 2 / 3) of the operation management flag FLG, whose initial state is 0. Note that the IRQ_SND output terminal of the sound processor 27 is open, and the IRQ_SND input terminal of the CPU circuit 51 is fixed to the H level.

[0314] In the 1 ms timer interrupt process, first, if it is determined in the process of step SP42 that the operation management flag FLG = 0, it is confirmed that the initialization sequence of the sound processor 27 has ended normally (SP43). If it has ended normally, a predetermined value is written to a predetermined sound register SRG to clear the interrupt signal (IRQ_SND) (SP46), and the operation management flag FLG is set to 1 (SP47). The processes of steps SP43 and SP46 are the same as the processes of steps SP31 and SP34 in Fig. 17(c).

[0315] On the other hand, if the initialization sequence has not ended normally, a reset command is written to a predetermined voice register SRG to cause the voice processor 27 to start the initialization sequence (SP44), and the operation management flag FLG is reset to zero (SP45). The process of step SP44 corresponds to the process of step SP32 in FIG. 17(c).

[0316] Normally, the operation management flag FLG becomes 1 after the processing of step SP47, so that at the next 1 ms timer interrupt, a predetermined value is written to a predetermined voice register to permit access to all voice registers (SP48), and the operation management flag FLG is set to 2 (SP49). The processing of step SP48 corresponds to the processing of step SP35 in FIG. 17(c).

[0317] Next, in the 1 ms timer interrupt with operation management flag FLG=2, as in step SP26 of Figure 17(a), the necessary setting values ​​are written to the built-in register (voice register SRG) of the voice processor 27, initialization processing is performed (SP50), and the operation management flag FLG=3 is set.

[0318] The operation management flag FLG=3 means a normal voice control state, and voice control is advanced by setting necessary operation parameters in necessary voice registers SRG (SP52).

[0319] The above describes a method for checking whether the initialization sequence of the audio processor 27 has ended normally by using an interrupt process caused by an interrupt signal (IRQ_SND) (SP31 in FIG. 17(c)) and a method for checking by using a 1 ms timer interrupt process (SP43 in FIG. 19), but the present invention is not limited to these methods. For example, it is also preferable to determine whether the initialization sequence of the audio processor 27 has ended normally as part of the process of step SP26 in FIG. 17.

[0320] The introductory part of the main control process (SP20 to SP27 in FIG. 17) has been explained above, so below, the operation of the main part of the main control process will be explained based on FIG. 20. As shown in FIG. 20, the operation of the performance control CPU 63 is composed of a main control process (a), a timer interrupt process (b) that starts every 1 ms, a reception interrupt process (not shown) that starts upon receiving a control command CMD, a VBLANK interrupt process (c) that starts upon receiving a VBLANK signal that occurs at the start timing of the V blank (vertical blanking period) of the display device DS1, and a drawing abnormality interrupt process (d) that occurs when the operation freezes or an irrational instruction command is detected. Note that an explanation of the 20 μS interrupt process will be omitted.

[0321] In the reception interrupt process, the control command CMD received from the main control unit 21 is stored in a predetermined reception buffer so that it can be referenced in the main control process (ST13), and the process ends. Also, in the VBLANK interrupt process (FIG. 20(b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start timing of the main control process, the interrupt counter VCNT is cleared to zero after grasping the operation start timing of 1 / 30 seconds based on the value of the interrupt counter VCNT (ST4).

[0322] On the other hand, the timer interrupt process includes, as shown in Fig. 20(b), a lamp performance or motor performance progress process (ST18), and a sensor signal acquisition process (ST19) for acquiring origin sensor signals SN0 to SNn, chance button signals, etc. The lamp performance or motor performance is controlled based on a performance scenario that centrally manages all performance operations, and when the performance start time managed by the performance counter EN is reached, the motor drive table or lamp drive table is specified in the performance scenario update process (ST11).

[0323] Then, the motor performance proceeds based on the specified motor drive table, and the lamp performance proceeds based on the specified motor drive table. As described above, there is also an embodiment in which the DMAC circuit (first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor performance proceeds every 1 mS, but the lamp performance proceeds at appropriate timing longer than 1 mS.

[0324] On the other hand, as shown in Fig. 20(d), in the drawing abnormality interrupt process, the status register RGij indicating the operation state of the drawing circuit 76 is accessed for READ to identify the cause of the interrupt. Specifically, it is identified (ST16a) whether the drawing abnormality interrupt is due to (1) detection of an abnormal instruction command (bit garbling) or (2) operation abnormality (freezing) of the drawing circuit 76. Then, if the drawing abnormality interrupt is due to detection of an abnormal instruction command, a predetermined value is written to a predetermined system control register RGij to initialize the drawing circuit 76 (ST16b). This operation is nothing but an individual reset operation of the reset path 4B shown in Fig. 6(b).

[0325] Next, after confirming the normal end of the individual reset operation with a predetermined status register RGij, a group of operation parameters that define the operation of the drawing circuit 76 are reset in the predetermined drawing register RGij, and the process is terminated (ST16c). Then, after adjusting the stack area that stores the return address (release process that erases the return address after the interrupt process), the process proceeds to step ST13 (ST16c).

[0326] On the other hand, in the case of a drawing abnormality interrupt based on an operational abnormality of the drawing circuit 76, the process transitions to an infinite loop process (ST16d), starting the WDT circuit 58 and resetting the entire combined chip 50. If it is not desired to reset the CPU circuit 51, a predetermined keyword string may be output to the pattern check circuit CHK and only the VDP circuit 52 may be reset by the reset signal RST (see FIG. 6(b)). In this case, after confirming that the reset operation of the VDP circuit 52 has been completed normally, the process transitions to steps ST4 and ST13. In order to avoid overlooking the control command CMD as much as possible, it is better to transition to step ST13 from step ST4, including other cases.

[0327] When the entire composite chip 50 is reset, the previous effects disappear and the effect control returns to the initial state (power-on state), but when only the VDP circuit 52 is reset, a series of effect control can be continued, although there is a predetermined waiting time until the reset operation of the VDP circuit 52 is completed. Note that the effect control CPU 63 controls the image effect, lamp effect, and sound effect in a unified manner, so there is no unnatural gap between the effects.

[0328] Next, the main control process (a) will be described for an embodiment in which the preloader does not function. As shown in Fig. 20(a), the main control process is divided into an introductory initial process (ST1 to ST3) that is executed after a CPU reset, and a regular process (ST4 to ST14) that is repeatedly executed every 1 / 30 seconds thereafter. Note that the initial process (ST1 to ST3) is a part of the introductory part of the main control process, and the regular process means the main part of the main control process.

[0329] And, steady-state processing is started when interrupt counter VCNT becomes VCNT≧2 (ST4), so the operation period δ of steady-state processing is 1 / 30 seconds. This operation period δ is none other than the substantial operation period δ of VDP circuit 52, which operates intermittently under the control of performance control CPU 63. Note that the reason for setting the judgment condition as VCNT≧2 is to take into consideration the possibility that steady-state processing (ST4 to ST14) may be abnormally prolonged and the timing of VCNT=2 may be missed, but it is designed to prevent a situation where VCNT=3 occurs.

[0330] Continuing with the explanation of the main control process (FIG. 20(a)) based on the above, in this embodiment, in the initial process, the built-in VRAM 71 with a storage capacity of 48 MB is appropriately divided into an ACC area (a) having an appropriate storage capacity, a page area (b), and an arbitrary area (c) (ST1). Specifically, for the ACC area (a1, a2) and the page area (b), the start addresses of each area and the total required data size are set in a predetermined index table register RGij (ST1). Then, the secured ACC area (a1, a2) and the remaining area not included in the page area (b) become the arbitrary area (c).

[0331] Here, the lowest 11 bits of the area start addresses of the first and second ACC areas (a1, a2) and the page area (b) must each be 0, but they can be selected arbitrarily in units of 2048 bits (1 address = 1 byte, and selection can be made in increments of 256 addresses). The total data size can also be selected arbitrarily within the range of an integer multiple of the unit size. Although not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbits.

[0332] In this embodiment, certain conditions are set for the area settings of the ACC area (a1, a2) and the page area (b), in order to eliminate as much wasted area as possible from the built-in VRAM 71, which has a limited memory capacity, while facilitating the internal operation of the VDP circuit 52. In other words, if the memory capacity of the built-in VRAM 71 is increased without reason, there is a concern that the manufacturing cost will rise and the chip area will become larger, while if free area settings that completely eliminate the wasted area are allowed, the internal processing will become complicated and the processing time for VRAM access cannot be shortened. The same reason is also why certain restrictions are set for the reservation of the index space, which will be explained below.

[0333] Continuing the explanation based on the above, following the processing of step ST1, the necessary index space IDXi is secured for the page area (b) and the arbitrary area (c) (ST2). Specifically, the index space IDXi for each area (b) and (c) is secured by setting necessary information in a predetermined index table register RGij.

[0334] For example, when an index space IDXi is provided in the page area (b), multiple information (horizontal and vertical multiple information for the unit space) of an arbitrary horizontal size Hx and an arbitrary vertical size Wx corresponding to an arbitrary index number i is set in a predetermined index table register RGij (ST2).

[0335] As explained above, the index space IDXi of the page area (b) has a unit space of 128 lines in horizontal size x 128 lines in vertical size, and one pixel is specified by 32 bits of information, so an index space IDXi with a data size (bit length) = 32 x 128 x Hx x 128 x Wx is secured based on the horizontal size Hx and vertical size Wx. The top address (space top address) of the index space IDXi of the page area (b) is automatically assigned internally.

[0336] Moreover, when an index space IDXi is provided in the arbitrary area (c), an arbitrary start address (space start address) STx and multiple information of an arbitrary horizontal size Hx are set in a predetermined index table register RGij corresponding to an arbitrary index number i (ST2). Here, "arbitrary" means that a predetermined condition is assumed, and the horizontal size Hx is arbitrarily determined in units of 256 bits, and the lower 11 bits of the start address STx are 0, and the horizontal size Hx is arbitrarily determined in units of 2048 bits. As explained above, the vertical size of the arbitrary area is fixed to 2048 lines, so that an index space of data size (bit length) = 2048 x Hx is secured after the start address STx based on the setting of the horizontal size Hx.

[0337] Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces with a horizontal size of 1280 x vertical lines of 2048 are set in one or more predetermined index table registers RGij with a specified index number for each, and as the frame buffer FBb of the sub display device DS2, a pair of index spaces with a horizontal size of 480 x vertical lines of 2048 are set in one or more predetermined index table registers RGij with a specified index number for each. If the number of horizontal pixels of the display device does not match an integer multiple of 256 bits / 32 bits, the horizontal size of each index space is set to a value that is larger than the number of horizontal pixels of the display device and is an integer multiple of 256 / 32=8, thereby minimizing the generation of wasted memory area.

[0338] As described above, the required size information and address information for the page area (b) and the arbitrary area (c) are set in the predetermined index table register RGij, respectively, to generate the required number of index spaces IDXi (ST2). Then, in response to this setting process (ST2), an index table IDXTBL that specifies the address information and size information of each index space IDXi is automatically constructed. As shown in FIG. 11(a), the index table IDXTBL stores the top address of each index space IDXi together with other necessary information, and is referred to when transferring data within the VDP circuit 52 or when acquiring data from an external storage resource (resource) (see FIG. 12). Note that the index space IDXi of the AAC area (a) is automatically generated and automatically deleted when necessary, so the setting process of step ST2 is not required.

[0339] As shown in Figures 11(a) and 11(b), a pair of frame buffers FBa and FBb are secured in the arbitrary area (c), and each is assigned an index number. In an embodiment that does not use a Z-buffer, a pair of index spaces 255 and 254 assigned with index numbers 255 and 254 are secured as the frame buffer FBa. Also, a pair of index spaces 252 and 251 assigned with index numbers 252 and 251 are secured as the frame buffer FBb. In this embodiment, a work area (index space 0) with index number 0 is also secured in the arbitrary area (c).

[0340] In this embodiment, the page area (a) is allocated with a necessary number of index spaces IDXi to be used as the decode area for the IP stream video, and the index number i is assigned to each of the index spaces. However, initially, the index space IDXi for the background video (IP stream video) is 0 Then, depending on the necessity of the image presentation (variable presentation or preview presentation), the index space IDXj of the page area (a) is increased based on the setting process to the index table register RGij and the instruction command of the display list DL, and then, when it becomes unnecessary, the index space IDXj is released. That is, FIG. 11(a) shows the index table IDXTBL during normal operation.

[0341] The index space of the ACC area (a) is automatically generated when necessary based on the instruction command written in the display list DL, and the top address of the automatically generated index space IDXj and other necessary information are automatically set in the index table IDXTBL. In this embodiment, this AAC area (a) is used as a decoding area for still images and other textures.

[0342] The above operation of reserving index space is realized mainly by a setting operation to the index table register RGij included in the control register group 70, but following the processing of steps ST1 to ST2, the necessary setting operation (ST3) is executed to other VDP registers RGij, enabling steady operation (intermittent operation) of the VDP circuit 52 shown in Figures 28 to 29.

[0343] In this embodiment, the necessary setting process (ST3) includes at least the processes (SS30 to SS43) shown in Table 1. Note that the order of steps SS30 to SS43 is not limited, and they can be executed in any order regardless of the order described below. [Table 1]

[0344] In this embodiment, first, a predetermined system control register RGij is set to construct a dual link transmission path for the main display device DS1 (SS30). As a result of this setting, the output of the display circuit 74A is supplied to the LVDS section 80a and the LVDS section 80b in a state in which the dot clock DCK is divided into an ODD signal and an EVEN signal, which are obtained by dividing the dot clock DCK by two.

[0345] Next, for the display circuit 74A and the display circuit 74B, the dot clock DCK is generated based on the 40 MHz reference clock (the output of the oscillator OSC2). A or DCK B The multiplication ratio and division ratio for this reference clock are appropriately specified for each display circuit (SS32).

[0346] The dot clock DCK is set separately for the display circuit 74A and the display circuit 74B, and the dot clock DCK for the main display device DS1 applied to the display circuit 74A AAs explained above, the frequency of the dot clock DCK for the sub-display device DS2 applied to the display circuit 74B is set to 108 MHz. B The frequency is set to 27 MHz, corresponding to 480 pixels wide by 800 pixels high.

[0347] Also, a predetermined system control register RGij is set so that the start of operation of the display circuit 74B is synchronized with the start of operation of the display circuit 74A (SS33).

[0348] Next, predetermined operating parameters (number of lines and number of pixels) are written to a predetermined display register RGij that specifies the operation of the display circuit 74, thereby setting the number of display lines and the number of horizontal pixels for each display device DS1, SD2 (SS34). In this embodiment, the number of horizontal pixels of the main display device DS1 is 1280 dots, and the number of display lines is 1024 rows. The number of horizontal pixels of the sub display device DS2 is 480 dots, and the number of display lines is 80 rows. As a result of the setting process of step SS34, the vertical and horizontal dimensions of the effective data area (broken line area in FIG. 20(e)) to be accessed for READ by the display circuits 74A, 74B are specified in each frame buffer FBa, FBb.

[0349] Next, the number of cycles THc of the horizontal period TH and the horizontal waiting time WTh are set for each display device DS1, SD2 (SS35) by writing predetermined operating parameters (THc, WTh) to a predetermined display register RGij that specifies the operation of the display circuit 74. Also, the number of lines TVl of the vertical period TV and the vertical waiting time WTv are set for each display device DS1, SD2 by writing predetermined operating parameters (TVl, WTv) to a predetermined display register RGij (SS36).

[0350] As explained with reference to Fig. 14, for the main display device DS1, the number of cycles of the horizontal period TH is set to THc = 1662, and the number of lines of the vertical period TV is set to TVl = 1083. In addition, the horizontal waiting time WTh is set to 382, ​​and the vertical waiting time WTv is set to 59 lines. On the other hand, for the sub display device DS2, for example, the number of cycles of the horizontal period TH is set to THc = 519, the number of lines of the vertical period TV is set to TVl = 867, the horizontal waiting time WTh is set to 39, and the vertical waiting time WTv is set to 67 lines. Note that THc - WTh = 519 - 39 = 480, and TVl - WTv = 867 - 67 = 800, which matches the number of pixels (480 horizontal x 800 vertical) of the sub display device.

[0351] In any case, the frequency F of the dot clock DCK is set by the process of step SS32. dot (=108 MHz) is determined, and the number of cycles THc (=1662) of the horizontal period TH and the number of lines TVl (=1083) of the vertical period TV are determined for the main display device DS1 by the processing in steps SS35 and SS36. As a result, the display period of one frame is determined as follows: THc×TVl / F dot Specifically, the display period of one frame is determined to be 1083×1662 / 108MHz=16.667mS, and the frame rate FR is determined to be 1 / 60 seconds.

[0352] For the sub-display device DS2, for example, the frequency F of the dot clock DCK is dot = 27 MHz, the number of cycles in the horizontal period THc = 519, and the number of lines in the vertical period TVl = 867, it is determined that 519 x 867 / 27 MHz = 16.66 mS.

[0353] In this embodiment, in response to the above-mentioned determination process, the display circuit 74 enters a V blank start state every 1 / 60 seconds, and the display operation shown in Fig. 14 is repeated. Note that in Fig. 14, the start timing of the display operation and the end timing of the display operation indicated by circles indicate the V blank start timing.

[0354] Based on this V blank start timing, a horizontal reference point TH0 (= horizontal reference time) and a vertical reference point (= vertical reference time) TV0 in the operation of the display circuit 74 are defined, and the display circuit 74 waits without outputting image data corresponding to each pixel of the display device until the horizontal waiting time WTh has elapsed from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait without outputting image data corresponding to each pixel of the display device until the vertical waiting time WTv has elapsed from the vertical reference point TV0.

[0355] In addition, since the display circuit 74B operates in synchronization with the display device 74A (SS33), the start and end timings of the display operation for the sub-display device DS2 are also the same as those of the main display device DS1. Therefore, by setting the frame period (519×867 / 27) for the sub-display device DS2 shorter than the frame period (1083×1662 / 108) for the sub-display device DS2, the update process for the sub-display device DS2 is set to be completed at the start of the V blank.

[0356] Next, in this embodiment, for the sub-display device DS2, the pulse width of the horizontal periodic signal HS and the number of cycles from the V blank start timing of the pulse rising edge are set in a predetermined display register RGij (SS37). Also, for the sub-display device DS2, the pulse width of the vertical periodic signal VS and the number of cycles from the V blank start timing of the pulse rising edge are set (SS38).

[0357] As explained above, the main display device DS1 does not require the horizontal sync signal HS or the vertical sync signal VS, and therefore the above processing (SS37 to SS38) for the main display device DS1 is not required. However, if the setting processing of steps SS37 to SS38 is omitted, the default values ​​set at the time of power reset function, so that the display device 74A actually outputs the horizontal sync signal HS and the vertical sync signal VS.

[0358] According to the default values, for example, a horizontal synchronization signal HS with a pulse width of 40 clocks that becomes active 16 clocks after the V blank start timing is output, and a vertical synchronization signal VS with a pulse width of 3 lines that becomes active in synchronization with the V blank start timing is output.

[0359] This operation means that a horizontal sync signal HS with a horizontal front porch HPv=16, pulse width PWh=40, and horizontal back porch BPv=326 is output to the main display device DS1 during the horizontal wait time WTh=382 clocks, and a vertical sync signal VS with a vertical front porch HPv=0, pulse width PWv=3, and vertical back porch BPv=56 is output during the vertical wait time WTv=59 lines. However, as described above, these sync signals are ignored in the main display device.

[0360] In order to prevent the synchronization signals HS and VS based on the default value from being output, a configuration may be adopted in which a predetermined system control register RGij is set so as not to output the horizontal synchronization signal HS or the vertical synchronization signal VS. When such a mask setting is provided, the output terminal of the horizontal synchronization signal HS and the output terminal of the vertical synchronization signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

[0361] Next, a predetermined system control register RGij is set to permit V blank interrupts (SS39). As a result, in this embodiment, a VBLANK start interrupt occurs in response to the V blank start timing that occurs every 16.667 mS = 1 / 60 seconds, as shown in Fig. 20 (c). This V blank interrupt timing specifies the start timing of the regular processing (ST5 to ST14) of the performance control CPU 63, and also indicates the start timing of the display period for the display circuits 74A and 74B (the end timing of the previous display period).

[0362] Next, a predetermined operation parameter (address value) is written to a predetermined display register RGij to specify the vertical display start position and the horizontal display start position for each frame buffer FBa, FBb (SS40). As a result, the effective data area whose vertical and horizontal dimensions are specified in the processing of step SS34 is determined on the frame buffers FBa, FBb. Here, the vertical display start position and the horizontal display start position are relative address values ​​in each index space, and in the embodiment shown in Figure 20(e), the display start position is (0,0).

[0363] Here, the "display area" refers to the index space (frame buffers FBa and FBb) from which the display circuits 74A and 74B should read image data to drive the display devices DS1 and DS2, and refers to either one of the double buffers in the frame buffers FBa and FBb, which have a double buffer structure. However, the display circuits 74A and 74B actually read image data only from the "valid data area" in the display area (0) or display area (1) specified in steps SS34 and SS40.

[0364] Next, the display areas are defined by setting "display area (0)" and "display area (1)" in the display register RGij(DSPAINDEX) for the display circuit 74A that drives the main display device DS1 and the display register RGij(DSPBINDEX) for the display circuit 74B that drives the sub-display device DS2 (SS41).

[0365] Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 of index number 254 in the VRAM arbitrary area (c) is defined as the "display area (0)," and the index space 255 of index number 255 in the VRAM arbitrary area (c) is defined as the "display area (1)" (SS41).

[0366] Also, for frame buffer FBb, index space 251 of index number 251 in VRAM arbitrary area (c) is set as "display area (0)," and index space 252 of index number 252 in VRAM arbitrary area (c) is set as "display area (1)" (SS41). Note that there is no particular limitation to defining the "display area" in the initialization process (ST3), and the index space (display area) to which display circuit 74 should access image data for READ may be toggled for each operation cycle δ.

[0367] In this embodiment, once the initial setting including the above processes (SS30 to SS41) is completed, a predetermined prohibition value is set in the first type prohibition setting register RGij so that the setting value in the predetermined system control register RGij is not subsequently changed due to the influence of noise or the like (first prohibition setting SS42).

[0368] Here, the setting values ​​that are prohibited from being written in the future include (1) setting values ​​related to the display clock DCK of the display devices DS1 and DS2, (2) setting values ​​related to the sampling clock of the LVDS, (3) setting values ​​related to the selection operation of the output selection circuit 79, and (4) the synchronous relationship of the multiple display devices DS1 and DS2 (the display circuit 74B is subordinate to the operation cycle of the display circuit 74A). Although there is software processing for canceling the first prohibition setting, it is not used in this embodiment. However, it is preferable to use it as necessary.

[0369] Next, a predetermined inhibit value is set in the second type inhibit setting register RGij, thereby inhibiting writing to the VDP register RGij of the initial setting system (second inhibit setting SS43). Here, the registers to be inhibited include the VDP register RGij related to steps SS30 to SS42.

[0370] On the other hand, by setting a predetermined prohibition value in the third type prohibition setting register RGij, it is also possible to set prohibition on a large number of VDP registers, including the VDP registers related to the setting process of steps ST1 to ST3 (third prohibition setting). However, this is not used in principle in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be released at will by writing a release value in a predetermined release register RGij, and it is also possible to change the set value during normal operation.

[0371] The initial setting process of steps ST1 to ST3 described above is executed based on an initial value setting table SETTABLE (see FIG. 34) that associates the register address value of the VDP register RGij with the setting value for that register RGij. As the initial setting process has been described above, before describing the steady-state process (ST4 to ST14), the steady-state operation (intermittent operation) of the VDP circuit 52 controlled by the performance control CPU 63 will be roughly described based on FIG. 28(a) and FIG. 29(b).

[0372] The intermittent operation of the VDP circuit 52 is as shown in Figures 28 and 29, and in an embodiment that does not use the preloader 73, as shown in Figure 28(a), the display list DLi completed by the performance control CPU 63 is issued to the drawing circuit 76 in its operation cycle (T1), and the drawing circuit 76 completes image data in the frame buffers FBa, FBb by drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa, FBb is output by the display circuit 74 to the display devices DS1, DS2 in the next operation cycle T1+δ, and the display screen sensed by the player is generated based on the drawing operation of the display devices DS1, DS2 thereafter.

[0373] 29(a), the display list DLi completed by the performance control CPU 63 is issued to the preloader 73 in its operation cycle (T1), and the preloader 73 interprets the display list DLi and executes the necessary pre-reading operation, while rewriting a part of the display list DLi to complete the rewrite list DL'. The pre-read CG data and the rewrite list DL' are stored in the appropriate places in the DRAM 54.

[0374] Next, in the next operation cycle (T1+δ), the drawing circuit 76 obtains the rewrite list DL' from the DRAM 54 and completes the image data in the frame buffers FBa, FBb by performing drawing operations based on the rewrite list DL'. Then, in the next operation cycle (T1+2δ), the display circuit 74 outputs the completed image data in the frame buffers FBa, FBb to the display devices DS1, DS2, and the display screen sensed by the player is generated based on the subsequent drawing operations of the display devices DS1, DS2.

[0375] The above is a brief overview of the intermittent operation of the VDP circuit 52. In order to realize the operation of Figures 28 to 29 described above, after initial processing (ST1 to ST3), the performance control CPU 63 repeatedly refers to the value of the interrupt counter VCNT and waits for the operation start timing to be reached, and when the operation start timing (the start timing of every other V blank) is reached, it clears the interrupt counter VCNT to zero (ST4).

[0376] Thereafter, steady operation is started. In this embodiment, first, it is determined whether or not an operation start condition for starting steady operation is satisfied (ST5). Note that this determination timing is the timings T1, T1+δ, T1+2δ, . . . shown in Figs. 28 and 29, that is, the start timing of the vertical blanking period (VBLANK) of the display device DS1. Note that the display timing of the display device DS2 is set at the initial setting (ST3) so as to be subordinate to the display timing of the display device DS1.

[0377] The operation start condition determined at the start timing of the vertical blanking period (VBLANK) differs depending on whether the preloader 73 is used or not, so first, an embodiment (FIG. 20) in which the preloader 73 is not used will be described. In this case, the circuit configuration and the program are designed so that the internal operation of the VDP proceeds as shown in the time chart of FIG. 28(a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should finish the drawing operation during that operation cycle (T1 to T1+δ). However, for example, as in the case of the display list DL3 completed in the operation cycle (T1+2δ) of FIG. 28(a), it cannot be said that there is no possibility that the drawing operation will not be completed during that operation cycle (T1+2δ to T1+3δ). Also, there is a possibility that an underrun abnormality occurs in the display circuit 74, in which the generation of display data is not in time with the display timing.

[0378] The judgment process of step ST5 takes such a situation into consideration, and the performance control CPU 63 accesses the status register RGij (a type of the control register group 70) indicating the operating state of the drawing circuit 76, and judges at the timing of step ST5 whether the drawing circuit 76 has completed the necessary operation and whether there is an underrun abnormality. The presence or absence of an underrun abnormality is judged based on the underrun counters URCNTa to URCNTc. Also, in an embodiment that does not utilize the preloader 73, for example, at timing T1+δ in FIG. 28(a), the status information of the drawing register related to the drawing circuit 76 is read and accessed to confirm that the drawing operation based on the display list DL1 has ended.

[0379] If the operation start conditions are not met (abnormal / non-conformity), the abnormality flag ER, which counts the number of abnormalities, is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER is determined in steps ST9 and ST10 together with other serious abnormality flags ABN, and assuming that the serious abnormality flag ABN is in the reset state, if the number of consecutive abnormalities is not high (ER≦2), the performance command analysis process is executed in the same way as in normal times (ST13).

[0380] Similarly, in the case of an underrun abnormality, steps ST6 to ST8 are skipped. Then, a predetermined clear value is written to a predetermined system control register RGij to initialize the display clock DCK (frequency) and the display circuit 74 (ST10c). After confirming that this initialization process has ended normally, the frequency of the display clock DCK and the values ​​of a group of system control registers RGij that define the operation of the display circuit 74 are reset to predetermined values ​​(ST10c), and then the performance command analysis process is executed (ST13).

[0381] In the performance command analysis process (ST13), it is determined whether or not a control command CMD has been received from the main control board 21, and if a control command CMD has been received, the control command CMD is analyzed and necessary processing is executed (ST13). Here, the necessary processing includes a start preparation process for a new variable performance based on the control command CMD that instructs the start of a variable performance, and a start process for an error notification based on the control command CMD that indicates the occurrence of an error. Next, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

[0382] The above describes the case where there is a minor underrun abnormality or the operation start conditions are not met and the abnormality flag ER is ER≦2. In such cases, in that operation cycle, the process (ST6) of toggling the display area read by the display circuit 74 and the process (ST7) of creating a display list are skipped, and the performance scenario does not proceed (see ST8 to ST12). This is to prevent the image data of the frame buffers FBa and FBb in an incomplete state from being output. Therefore, for example, in the operation cycle (T1+3δ) in FIG. 28(a), the image performance does not proceed, and a frame drop occurs in which the original screen (screen based on DL2) is redisplayed.

[0383] Here, in order to avoid dropping frames, it is also possible to have a configuration in which the system waits until the operation start condition is satisfied. However, since there are many control processes (ST6 to ST12) that the performance control CPU 63 must execute, and each process needs to have its own processing time, in this embodiment, frame dropping occurs when the operation start condition is not satisfied.

[0384] However, even if a frame drop occurs, the image performance is delayed by only about 1 / 30 to 2 / 30 seconds compared to the lamp performance and motor performance that proceed by interrupt processing (Fig. 20(b)), and the player will not notice this. Moreover, when a frame is dropped, the performance scenario processing (ST11) including the update processing of the performance counter EN and the sound progression processing (ST12) are also skipped, so there is no risk of the start timing of the image performance, sound performance, lamp performance, and motor performance being shifted in the reach performance, notice performance, and gimmick performance that are started afterwards.

[0385] That is, in the performance scenario, the start timing of the image performance, the sound performance, the lamp performance, and the motor performance, and the performance contents to be executed thereafter are managed in a unified manner, and the start timing is controlled by the performance counter EN, which is updated only in normal times, so that the synchronization of various performances is not lost. For example, if there is a performance action that combines the sound of an explosion, an explosion image, the movement of a role object, and a lamp flash action, each of the above performance actions will start correctly in synchronization even after a frame drop occurs.

[0386] Although the above describes relatively minor abnormalities, if the serious abnormality flag ABN is set, if the number of consecutive abnormalities is large (ER>2), or if the Underrun abnormality occurs repeatedly, an infinite loop state is entered after the judgment in step ST10 (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, and the composite chip 50 including the performance control CPU 63 is reset due to an abnormality, and then the initial processing (ST1 to ST3) is re-executed, which is expected to eliminate the root cause of the abnormality.

[0387] This reset operation is performed by activating the WDT circuit 58, so the entire composite chip 50, including the CPU circuit 51, is reset (FIG. 6(b)). Therefore, in order to avoid resetting the CPU circuit 51, it is also preferable for the performance control CPU 63 to output a predetermined keyword string (e.g., three pieces of 1-byte data) to the pattern check circuit CHK and output a reset signal RST to the VDP circuit 52 (see ST100 in FIG. 34). In this case, too, after confirming that the reset operation of the VDP circuit 52 has ended normally (ST101), the process will move on to steps ST4 and ST13.

[0388] In any case, in the event of this abnormality, the sound circuit SND is also reset, so the image presentation, sound presentation, lamp presentation, and motor presentation are all returned to their initial states. However, these reset operations have no effect on the main control unit 21 or the payout control unit 25, so there is no risk of the big win state disappearing or the prize balls disappearing.

[0389] Although the above has been described regarding abnormal situations, in reality, the above-mentioned abnormalities rarely occur, even if they are minor, and after the processing of step ST5, the "display area" of the frame buffers FBa, FBb that store the image data to be read by the display circuits 74A and 74B is toggled (ST6) based on the setting of a predetermined display register RGij (DSPACTL / DSPBCTL). As explained above, since the "display area (0)" and the "display area (1)" are defined in advance in the initial processing (ST3), in the processing of step ST6, it is specified whether the "display area" at this time is the display area (0) or the display area (1) for the frame buffers FBa, FBb.

[0390] By executing this step ST6, the display circuit 74A alternately reads out image data from the index space 254 (display area (0)) and the index space 255 (display area (1)) for each operation cycle δ to drive the display device DS1. Similarly, the display circuit 74B alternately reads out image data from the index space 251 (display area (0)) and the index space 252 (display area (1)) for each operation cycle δ to drive the sub-display device DS2. As explained above, the actual READ access by the display circuit 74 is limited to the valid data area in the display area (0) / display area (1).

[0391] In any case, in this embodiment, the "display area" switches for each operation cycle, so that the display circuits 74A, 74B start output processing to the display devices DS1, DS2 for the image data that the drawing circuit 76 completed in the immediately preceding operation cycle. However, since the processing of step ST5 starts at the start of the vertical blanking period (V blank) of the main display device DS1, the output processing of the image data actually starts after the vertical blanking period is completed. In FIG. 28(a), the arrows shown in the display circuit column indicate the operation cycle of this output processing.

[0392] When the processing of step ST6 having the above significance is completed, the performance control CPU 63 then completes a display list DL that specifies image data to be output to the display device by the display circuit 74 in the next operating cycle (ST7). Although not limited to this, in this embodiment, a list buffer area (DL buffer BUF) of the RAM 59 is secured, and the display list DL is completed therein (see FIG. 12).

[0393] The display list DL is configured by listing a series of instruction commands in an appropriate order and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to realize smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all instruction commands including the EODL command are limited to only instruction commands whose command length is an integer multiple of 32 bits (N>0). As explained above, instruction commands consisting of an integer multiple of 32 bits may also include a don't care bit.

[0394] In this way, since the display list DL of the embodiment is composed only of instruction commands whose command length is an integer N times (N>0) 32 bits, the data volume value (total amount of data) of the entire display list DL is always an integer multiple of the minimum unit of the command length (32 bits=4 bytes). Furthermore, in this embodiment, taking into consideration the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is adjusted to be an integer multiple (1 or more) of the minimum data amount Dmin and an integer multiple of the minimum unit of the instruction command (4 bytes). For example, if Dmin=256 bytes, the data volume value of the display list DL is adjusted to be either 256 bytes, 512 bytes, or the like.

[0395] Here, it would be preferable to adjust it to 256 bytes or 512 bytes as appropriate depending on the complexity of the presentation content, but in this embodiment, taking into consideration that there are two display devices and the sub-display device DS2 does not execute very complex image presentations, the data volume value of the display list DL is always adjusted to 256 bytes.

[0396] However, this method is not limited in any way, and in the case of a gaming machine with three or more display devices or a gaming machine that executes complex image effects including the sub-display device DS2, the data volume value is adjusted to 512 bytes or 768 bytes. Also, during normal effects, it is preferable to adjust the data volume value of the display list DL to 256 bytes, and only when a special effect is executed, to adjust the data volume value of the display list DL to 512 bytes or 768 bytes.

[0397] However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. The adjustment method may be a simple method (A) in which a 32-bit EODL command is followed by a 32-bit NOP (No Operation) command to fill in the missing area, or a standard method (B) in which the missing area is filled with a 32-bit NOP command and then a 32-bit EODL command is written at the end. In addition, a non-adjustment method (C) may be considered in which the data volume value (total amount of data) of the display list DL is terminated with an EODL command without any adjustment, and dummy data is additionally transferred during the operation of the data transfer circuit 72 to ensure a transfer amount that is an integer multiple of the minimum data amount Dmin.

[0398] Here, when the standard method (B) is adopted, the command counter CNT is initially set to a specified value (64-1 corresponding to 256 bytes), and the command counter CNT is appropriately decremented each time a significant instruction command is written in the DL buffer area BUF, and when the writing of a series of significant instruction commands is completed, NOP commands are written until the command counter CNT reaches zero, and finally an EODL command is written. In the case of this embodiment, the instruction commands are limited to those whose command length is an integer multiple of 32 bits (N>0), so the above process is easy, and the decrement process of the command counter CNT corresponds to the integer N.

[0399] On the other hand, when the simplified method (A) is adopted, it is sufficient to fill the entire list buffer area (DL buffer BUF) with NOP commands at the beginning when creating the display list DL, and therefore at first glance it appears to be superior to the standard method (B). Also, from the viewpoint of simplicity, the non-adjustment method (C) also appears to be superior. However, this embodiment basically adopts the standard method (B), and adjusts so that the actual amount of data from the beginning of the display list DL to the EODL command, that is, the amount of data up to the EODL command, is always an integer multiple of the minimum data amount Dmin of the data transfer circuit 72.

[0400] This is because, if the simple method (A) or the adjustment-free method (C) is adopted, the actual data amount of the display list DL up to the EODL command becomes a random value, causing a problem when the rewrite list DL' rewritten by the preloader 73 is transferred to the DRAM 54 and when the rewrite list DL' is transferred from the DRAM 54 to the drawing circuit 76. Note that, when the rewrite list DL' is transferred to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when the rewrite list DL' is transferred to the drawing circuit 76, the ChB control circuit 72b functions (see FIG. 26). In either case, however, only the rewrite list DL' up to the EODL command is transferred.

[0401] The above describes the advantages of the standard method (B) of adjusting the data volume value of the display list DL. However, in an embodiment that does not use the preloader 73, the issued display list DL is simply processed by the drawing circuit 76, so there is no prohibition on using the simple method (A) or the adjustment-free method (C).

[0402] However, in the following description, the display list DL will be described in detail with reference to FIG. 21 on the assumption that the standard method (B) is adopted in principle, regardless of whether the preloader 73 is used or not.

[0403] Although not particularly limited, in this embodiment, the instruction command sequence (L11 to L16) for the main display device DS1 is written in the display list DL first, and then the instruction command sequence (L17 to L20) for the sub display device DS2 is written. Also, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 21 also shows the procedure by which the performance control CPU 63 writes instruction commands in the list buffer area of ​​the RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

[0404] As shown in Fig. 21, at the beginning of the display list DL, an environment setting command (SETDAVR) is written to specify the upper left base address (X, Y) in the index space IDX for the frame buffer FBa of the display device DS1 (L11). As explained with reference to Fig. 11(a), in this embodiment, a pair of frame buffers FBa is reserved in the arbitrary area (c) for the display device DS1. Usually, the base address (X, Y) = (0, 0) is set to correspond to the valid data area for the display circuit 74, and the frame buffer FBa is used by the drawing circuit 76 from its beginning.

[0405] In Figure 11(c), the actual drawing area on the lower left side is labeled L11, which means that the instruction command L11 has specified that the actual drawing area on the frame buffer FBa begins at the base address (0,0) of the frame buffer FBa. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically specifies this actual drawing area have not yet been determined, and will be determined by the instruction command (SETINDEX) L13, which will be described later. Note that the instruction command L11 also specifies whether or not to use the Z buffer.

[0406] Next, the environment setting command (SETDAVF) is used to set the upper left base point coordinates (Xs,Ys) and the lower right diagonal point coordinates (Xe,Ye) in the virtual drawing space, defining a drawing area with dimensions W x H (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn on using drawing command commands (such as the SPRITE command) (see Figure 11(c)).

[0407] This instruction command L12 (SETDAVF) divides the virtual drawing space into a drawing area where the drawing contents are actually reflected on the display device DS1, and the other non-drawing area. Also, the instruction command L12 (SETDAVF) associates the actual drawing area, whose start position (base address) is specified by the instruction command L11, with the drawing area in the virtual drawing space.

[0408] In other words, the instruction command L12 defines an actual drawing area of ​​W x H starting from the base address, which corresponds to the drawing area in the virtual drawing space, in the frame buffer FBa (with the index space undefined). Therefore, the drawing area specified by the instruction command L12 must be equal to or smaller than the horizontal size of the frame buffer FBa. Usually, the drawing area or actual drawing area is defined to have the same dimensions as the effective data area (Figure 20(e)) for the display circuit 74.

[0409] After the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing contents drawn in the virtual drawing space that are included in the drawing area are reflected in the actual drawing area of ​​the frame buffer FBa. Therefore, the drawing contents that extend beyond the drawing area or the drawing contents in the area indicated as the working area in Fig. 11(c) are not reflected in the frame buffer as is. Note that when a working area is allocated in the virtual drawing space, the non-drawing area of ​​the virtual drawing space is used.

[0410] Next, in the current operation cycle, the drawing circuit 76 specifies where to draw the drawing contents based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the display device DS1 with a double buffer configuration, the index space IDX that will be the "write area" of the drawing contents based on the current display list DL is specified (L13). Specifically, the SETINDEX command, which is a texture setting command, specifies (1) that the frame buffer FBa is secured in an arbitrary area, and (2) that the index space IDX that will be the "write area" is specified. N An index number N on an arbitrary region of is identified.

[0411] For example, when N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined in the virtual drawing space is, specifically, the index space IDX in the frame buffer FBa having a double buffer structure. 255 It has been defined as:

[0412] In this embodiment, the index number of the frame buffer FBa is 255 or 254 (FIG. 11(a)), and either one is designated by toggling (L13). Note that this index number is not the index number of the display area (0) / (1) designated in step ST6 of the main control process. For example, in the process of step ST6, if display area (0) is designated for the display circuit 74, display area (1) becomes the "write area" for the drawing circuit 76.

[0413] As described above, the correspondence between the actual drawing area (logical space of W×H) and the drawing area (virtual space of W×H) is generally defined by instruction command L11 and instruction command L12, and then the W×H virtual space is associated with the W×H logical space in a specific index space IDX by instruction command L13 (SETINDEX), which specifically specifies the index space IDX.

[0414] In other words, from now on, the content that is virtually drawn in the W x H virtual space based on a series of instruction commands will become image data in the built-in VRAM 71 (frame buffer) based on a conversion table inside the VDP that specifies the correspondence between the virtual space and the real addresses of the built-in VRAM 71.

[0415] Next, an instruction command is written to execute a frame buffer clear process that fills the specified index space IDX as the "write area" with, for example, black (L14, L15). This is nothing but a process to erase the image data that was written to the frame buffer FBa two operation periods ago.

[0416] Specifically, for example, black is selected by the SETFCOLOR command, which is a type of environment setting command, and a rectangular area is specified to be filled by the RECTANGLE command, which is a primitive drawing command. Note that the RECTANGLE command specifies the XY coordinates of the upper left corner and the lower right corner of the drawing area (virtual space corresponding to the frame buffer FBa) set in the virtual drawing space (see Figure 11(c)).

[0417] With the above processing, the rendering preparation processing is completed, and next, instruction commands are listed for rendering an appropriate texture, such as a still image or one frame of a video, in the virtual rendering space. Typically, the index space IDX into which the texture is to be deployed is specified with a texture setting command, and then a texture load command, a TXLOAD command, is written to write in the display list DL a specific texture to be read from CGROM 55 and deployed in the specific index space IDX.

[0418] As explained above, in this embodiment, the background video is composed of IP stream video. Therefore, for example, the index space IDX in which the background video should be expanded is set to the index space IDX of the page area (b) by the SETINDEX command of the texture setting system. 0After specifying the above, write the TXLOAD command for loading textures. Note that the TXLOAD command needs to specify the start address of CGROM55 (texture source address) and the data size after expansion (horizontal x vertical) for the video frame to be loaded this time.

[0419] When the VDP circuit 52 executes the TXLOAD command, one video frame (texture) of the background video is first acquired in the AAC area (a), and then the GDEC 75, which starts automatically, loads it into the index space IDX in the page area (b). 0 Next, this one video frame is drawn in the virtual drawing space. In this case, the SETINDEX command (texture setting system) is used to set the index space IDX of the page area (b). 0 is the texture to be processed thereafter." However, if processing is to be performed immediately after the TXLOAD command, the SETINDEX command can be omitted.

[0420] In any case, "Index space IDX of page area (b) 0 is the texture to be processed thereafter," then an appropriate inter-drawing calculation command is entered, such as setting parameters for alpha blending. Alpha blending is a process for making the image already written in the drawing area (frame buffer FBa) transparent / semi-transparent with the image to be overwritten. Therefore, for the first drawing operation, such as a video frame of a background video, there is no need to use an inter-drawing calculation command.

[0421] Next, the index space IDX of the page area (b) is set by the SPRITE command, which is a command for drawing primitives. 0Write a SPRITE command to draw the "texture (one video frame of the background video)" in the appropriate location (rectangular destination area) in the virtual drawing space. Note that the SPRITE command requires that the upper left and lower right corners of the destination area in the virtual drawing space be specified.

[0422] This destination area is the entire drawing area (virtual space defined on the virtual drawing space) that has been associated with the actual drawing area (FBa) in advance by the instruction commands L11 and L12, or a part of it. However, since the background video is usually drawn on the entire display screen, the destination area in such a case is the entire drawing area or larger. Note that a destination area larger than the entire drawing area is, for example, when the background video is zoomed in.

[0423] With the above processing, drawing of the video frames of the background video is completed, and next, instruction commands such as texture load, texture setting, inter-drawing calculation, and primitive drawing commands are listed in an appropriate order, and a display list DL is constructed to draw various textures by overlaying them on the background video. As explained above, a large number of videos are required during variable performance, and in that case, an index table control instruction command (NEWPIX) is written to increase the index space IDX for the page area (b) of the built-in VRAM 71.

[0424] For example, for the second IP stream video, the NEWPIX command creates an additional index space IDX in page area (b). 1 After allocating this index space IDX 1 (SETINDEX), instructs the rendering of one frame of the second video (TXLOAD), and places the rendered texture in the appropriate location in the drawing area (SPRITE). Normally, the destination area in this case is part of the drawing area.

[0425] The same process is repeated below. The NEWPIX command is used to create the index space IDX. k After securing the required space, multiple IP streams are drawn in the drawing area while performing appropriate alpha blending, and the contents drawn in the drawing area are sequentially stored as image data in the frame buffer FBa, which is the actual drawing area. When multiple N IP stream videos are drawn, multiple N index spaces are functioning in the page area (b).

[0426] And when the series of variable performances is completed, the numerous index spaces IDX reserved in the page area (b) 1 ~IDX k In order to free up any index space IDX that is deemed unnecessary, the unnecessary index space IDX can be deleted using the DELPIX command.

[0427] When drawing still images or I-stream videos, use the SETINDEX command to specify that the decoding destination for these textures is the AAC area (a), then execute the TXLOAD command. The texture acquired in the AAC area (a) will then be expanded in the ACC area (a) by GDEC75, which starts automatically. The expanded texture can then be drawn in the appropriate location in the drawing area using the SPRITE command. Depending on whether or not the cache hit function is used, either the first AAC area (a1) or the second AAC area (a2) will be used.

[0428] In the explanation so far, each texture is drawn directly in the drawing area of ​​the main display device DS1, but the operation is not necessarily limited to this. For example, if an appropriate drawing area is provided (FIG. 11(c)) without overlapping with the drawing area already reserved for the display device DS1, and this drawing area is associated with the working area of ​​the built-in VRAM 71, an intermediate drawing area can be constructed and an appropriate performance image can be completed. Here, the reason for not overlapping with the drawing area for the display device DS1 is that the later association setting takes precedence for the overlapping area, and the drawing contents in that area are not reflected in the frame buffer FBa.

[0429] As shown in FIG. 11(c), the working area in this embodiment is the index space IDX in the arbitrary area (c). 0 Then, at the timing of the performance using this work area, the drawing area for the performance image (see FIG. 11(c)) is first created in advance as the work area (index space IDX 0 11C, the drawing area for the performance image is secured in an area not included in the drawing area for the main display device DS1.

[0430] Then, the same instruction commands as the instruction command sequence L16 for the frame buffer FBa are listed to create the index space IDX 0 In this embodiment, since the performance image is composed of a still image, a command (SETINDEX) is written to instruct the decoded data to be expanded in the first AAC area (a1), and then the index space IDX 0 A primitive rendering instruction command (SPRITE) is used, with the appropriate location in the rendering area of ​​the object as the Destination. Note that this type of operation is repeated once or multiple times depending on the content of the presentation.

[0431] And the index space IDX that completes the performance image 0After positioning the texture (SETINDEX), the index space IDX is set to the appropriate position in the drawing area of ​​the main display device DS1 by the SPRITE command. 0 In this case, the index space IDX 0 It is conceivable that the performance image of the above is decomposed into triangular drawing primitives, rotated at an appropriate angle, and then drawn in the drawing area. Note that the rotation angle of the texture is associated with, for example, the reliability of the preview performance.

[0432] The instruction command sequence (L11 to L16) for completing one frame of the main display device DS1 has been described above, but the instruction command sequence (L17 to L12) for completing one frame of the sub-display device DS2 is similar. That is, the starting XY coordinates of the frame buffer FBb are specified (L17) and defined (usually X=0, Y=0), and a drawing area for the sub-display device DS2 is defined (L18) in the virtual drawing space shown in Fig. 11(c).

[0433] Incidentally, in this embodiment, after completing the generation of image data for the main display device DS1, the process moves to the generation process for the sub display device DS2, so there is no problem even if the drawing area for the sub display device DS2 overlaps with the drawing area for the main display device DS1, and the drawing area can be set freely. Therefore, when developing a generation program for a display list DL, for example, in the case of pasting an appropriate texture into a newly set drawing area with a SPRITE command, the settings of the operation parameters (Destination area) of the SPRITE command and others can be standardized to a certain extent.

[0434] Once the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the display device DS2 with a double buffer configuration, the index space IDX that will be the "write area" of the drawing contents based on the current display list DL is specified (L19). The index number of this index space IDX is the index number of the frame buffer FBb that does not correspond to the display area (0) / (1) specified in step ST6 of the main control process.

[0435] Then, the instruction command sequence L20 to L22 for the sub-display device DS2 is listed in the same manner as the instruction command sequence L14 to L16 for the main display device DS1. 0 You can also use the completed performance image.

[0436] As described above, in this embodiment, the command lengths of all of the instruction commands L11 to L22 that make up the display list DL are limited to integer multiples of 32 bits. As explained above, the data volume value (total amount of data) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and a necessary number of NOP commands (L23) are added as dummy commands, and the display list DL is terminated with an EODL command (L24). That is, the embodiment in FIG. 21 employs the standard method (B) described above.

[0437] However, even when the standard method (B) is adopted, it is not necessarily required to fix the total data amount of the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total data amount of the display list DL excluding NOP commands exceeds 256 bytes (for example, during a special performance period), the total data amount of the display list DL is adjusted to 512 bytes or more, that is, N×256 bytes, by adding NOP commands. Note that, as explained above, when the standard method (B) is adopted, the end of the N×256 bytes is terminated with an EODL command.

[0438] The configuration of the display list DL has been explained in detail above, and the performance control CPU 63 issues the completed display list DL of fixed byte length to the VDP circuit (ST7 to ST8). Fig. 22 is a flowchart explaining the DL issuing process (ST8 in Fig. 20) in which the performance control CPU 63 directly WRITE accesses the transfer port register TR_PORT of the transfer circuit 72 and issues a display list DL to the drawing circuit 76. The transfer port register TR_PORT is a type of data transfer register RGij that specifies the operation content of the data transfer circuit 72.

[0439] To realize DL issuing processing, first, it is necessary to set necessary setting values ​​in a plurality of data transfer registers RGij that define the operation contents of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are specified in a predetermined data transfer register RGij. The setting contents are not particularly limited, but here, it is set that the data is transferred from the CPUIF unit 56 via the ChB control circuit 72b, and that the CPU bus control unit 72d executes the data transfer operation while checking the remaining capacity of the FIFO buffer (ST20). In the following description, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

[0440] Next, the total transfer size is set in a predetermined data transfer register RGij. As explained above, in this embodiment, the total data amount of the display list DL is adjusted to an integer multiple of 256 bytes, so that value is set. Note that the total data amount=256×N is also an integer multiple N of the minimum data amount Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following explanation, N=1 will be used.

[0441] Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit register, the performance control CPU 63 executes a register WRITE operation for the transfer port TR_PORT for every 32 bits. Therefore, the value of the management counter CN, which manages the number of register WRITEs, is initialized to 64 (ST21). Note that, if the non-adjustment method (C) is adopted, at this timing, the data transfer amount that is an integer multiple of the minimum data amount Dmin is determined and the management counter CN is set.

[0442] The above process completes the initial settings, and next, data transfer operation via the transfer circuit ChB is set to a start state (ST22), and drawing operation is started based on the set value of a predetermined drawing register RGij that specifies the operation of the drawing circuit 76 (ST23). As a result, a prompt and smooth analysis process is ensured by the drawing circuit 76 (display list analyzer) for the instruction command sequence that the performance control CPU 63 subsequently writes to the transfer port TR_PORT.

[0443] Furthermore, the fact that the instruction commands listed in the display list DL are limited to those whose command length is an integer multiple of 32 bits also contributes effectively to a fast and smooth analysis process. Timings t1, t2, t3, and t4 in Fig. 28(a) indicate the operation timing of step ST23. Note that since the display list DL issuance process (ST8) is completed quickly, the time required for the issuance process is not shown in Figs. 28 and 29.

[0444] Next, it is confirmed whether the setting in step ST22 has worked (ST24). This is because the initial settings of each part of the data transfer circuit 72 take more processing time than the register WRITE operation (setting operation) by the performance control CPU 63, so no further instructions are given to the data transfer circuit 72 in an incomplete state. Then, in the unlikely event that the circuit does not enter an operation start state even after waiting for a predetermined time, the serious abnormality flag ABN is set and the DL issuance process is terminated (ST25). As a result, the WDT circuit 58 then works, and the composite chip 50 is reset as an abnormality (ST10).

[0445] As mentioned above, in order to avoid resetting the CPU circuit 51, the performance control CPU 63 may output a predetermined keyword sequence to the pattern check circuit CHK and abnormally reset only the VDP circuit 52 based on the reset signal RST.

[0446] However, since the setting of step ST22 is usually completed quickly, next, after confirming that the FIFO buffer (32 bits x 130 stages) of the CPU bus control unit 72d is not full (ST26), an instruction command is written to the transfer port TR_PORT for each line, starting from the first line constituting the display list DL (ST28).

[0447] Then, while decrementing the management counter CN (ST29), the processing of steps ST26 to ST29 is repeated until the management counter CN becomes zero (ST30). In this embodiment, since a minimum data amount Dmin is specified for the data transfer circuit 72, a data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer, resulting in an intermittent transfer operation.

[0448] In any case, in this embodiment, the DL issuance process (ST28) is completed quickly, but in the unlikely event that the settings in the VDP register RGij become inconsistent due to the effects of noise or the like, the FIFO buffer full state may not be resolved even after waiting for a predetermined time in the judgment of step ST26. In such a case, initialization data is set in a predetermined VDP register RGij, the drawing circuit 76 and the data transfer circuit 72 are initialized, and the serious abnormality flag ABN is set to end the DL issuance process (ST27).

[0449] By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and have completed a certain amount of processing, so the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area, while maintaining the contents of the drawing register RGij. Similarly, the initialization process of the data transfer circuit 72 includes initialization of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

[0450] In the initialization process of step ST27 described above, the contents of the drawing register RGij are maintained, but the contents of certain drawing registers may be initialized. The certain drawing registers that are cleared to their initial values ​​include (a) an execution control register (see ST23 in FIG. 22) that sets the start of drawing execution, (b) a status register that indicates the execution status of the drawing circuit 76, and (c) a status register that specifies the position of the display list currently being processed.

[0451] In any case, as a result of setting the serious abnormality flag ABN, the WDT circuit 58 and the performance control CPU 63 then function to perform an abnormal reset of either the composite chip 50 or the VDP circuit 52 (ST10a), so it is not necessarily required to initialize the drawing circuit 76 and the data transfer circuit 72. On the other hand, when the drawing circuit 76 and the data transfer circuit 72 are initialized, it is possible to expect a recovery from the abnormality as a result, so it is also preferable to return to the processing of step ST20 and re-execute the DL issuance processing without setting the serious abnormality flag ABN.

[0452] This also applies to the processing of step ST25, and it is preferable to return to the processing of step ST20 without setting the serious abnormality flag ABN after initializing the data transfer circuit 72 and the drawing circuit 76. In such a case, however, the number of times the DL issuance processing is retried is counted, and if the number of times exceeds a limit value, the serious abnormality flag ABN is set and the DL issuance processing is terminated.

[0453] 22(b) is a diagram for confirmation of a normal operating state. As shown in the diagram, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and operations based on each instruction command are executed. This operation is executed in parallel with the issuing process of the display list DL and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

[0454] For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from the CGROM 55 and acquired in the AAC area (a), after which the GDEC 75 is automatically started to execute the decoding operation, and the decoded data is expanded in a predetermined index space. Depending on the instruction command, the geometry engine 77 and others function, but in any case, the image data corresponding to the display list DL is completed in the frame buffers FBa and FBb by the cooperation of each part of the drawing circuit 76.

[0455] Next, a case where a display list DL is issued via the DMAC circuit 60 will be described with reference to Fig. 23. Although not limited thereto, it is assumed that the third DMA channel is used among the first to fourth DMA channels built into the DMAC circuit 60.

[0456] In the embodiment of Fig. 23, first, a clear value is set in a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively, to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is the same as the error process in step ST27 of Fig. 22, and the internal circuitry of the data transfer circuit 72 including the FIFO buffer is initialized, the status bit of the data transfer register indicating the progress of the data transfer is set to an initial value, and the bit indicating that the entire data transfer is being initialized is set to a predetermined value.

[0457] The same is true for the drawing circuit 76, and includes the above-mentioned (1) setting the internal parameters to initial values, (2) setting the internal control circuit to an initial state, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area. Also, in the initialization process of the drawing circuit (ST20 in FIG. 23), the above-mentioned predetermined drawing register RGij may be initialized. Incidentally, in the process of FIG. 22, such initialization process may be executed first.

[0458] 23, next, a predetermined status register RGij that specifies the operating states of the data transfer circuit 72 and the drawing circuit 76 is read to confirm that the initialization process has been completed normally (ST21). If the initialization cannot be completed, a serious abnormality flag ABN is set and the process ends (ST22). However, this situation almost never actually occurs.

[0459] Next, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are set in a predetermined data transfer register RGij. The setting contents are not particularly limited, but here, it is set that the data is transferred from the CPUIF unit 56 via the ChB control circuit 72b, and that the transfer protocol to the CPU bus control unit 72d follows the setting in the DMAC circuit 60 (ST23).

[0460] Next, the total transfer size is set in a predetermined data transfer register RGij. As in the case of FIG. 22, the total data amount=256. If the non-adjustment method (C) is adopted, the total transfer size is determined and set at this timing as an integer multiple of the minimum data amount Dmin. Next, the drawing operation of the drawing circuit 76 is started based on the set value in the predetermined drawing register RGij (ST25). The timings t1, t2, t3, and t4 in FIG. 28(a) are also the operation timings of step ST25. Next, the operation of the DMAC circuit 60 is started (ST26), and then the data transfer operation of the data transfer circuit 72 is started (ST27).

[0461] The process of starting the operation of the DMAC circuit 60 is as shown in Fig. 23(b), and first, with DMAC transfer inhibited, the process waits for the transfer of one cycle of data transfer unit (one operand) to be completed (ST40). The detailed operation is the same as the process shown in Fig. 24, and is divided into a process of inhibiting DMAC transfer (ST53) and a subsequent waiting process (ST54).

[0462] The reason for providing such processing is that (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main control processing or timer interrupt processing (FIG. 20), and (2) in other embodiments that do not provide the processing of step ST5 in FIG. 20, the DMAC circuit 60 that has started issuing a display list DL may not be able to complete the DL issuing operation within its operating period (δ).

[0463] In the above-mentioned exceptional situation, if new setting values ​​(such as contradictory setting values) are additionally set to the operating DMAC circuit 60, normal DMA operation is not guaranteed at all, and serious trouble is a concern, but by providing the processing of step ST40, normal operation based on the subsequent setting values ​​is guaranteed. That is, even in the modified embodiment in which this embodiment is partially modified, normal DMA operation can be realized thereafter regardless of the preceding trouble.

[0464] After the processing of step ST40 having the above significance is executed, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in Fig. 8, the cycle steal transfer mode is selected, and one operand transfer is set to 32-bit transfer x 2 times. Also, it is specified that the source address is an address of the list buffer area (DL buffer BUF) of RAM 59 and should be recognized as sequentially increasing, while the destination address is the transfer port TR_PORT and should be a fixed value.

[0465] Next, the start address of the DL buffer BUF in the RAM 59 is set in a predetermined operation control register REG that specifies the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). In addition, the total transfer size, that is, the total amount of data in the display list DL, is set to 256 bytes (ST44), and the DMA operation of the DMAC circuit 60 is started (ST45).

[0466] Incidentally, the explanation so far has been based on the premise that the effective bit length of the instruction command is an integer multiple of 32 bits. However, the configuration of the display list DL and the instruction command is not necessarily limited, so the following explanation will be given of such a case.

[0467] For example, including the case where the above-mentioned non-adjustment method (C) is adopted, when the total data amount X of the display list DL is an arbitrary value X that is not an integer multiple of 32 bits, in the process of step ST44, this arbitrary value X is adjusted to an appropriate transfer amount MOD, and then the process of setting the total transfer size is executed. Here, the appropriate transfer amount MOD is specified based on the setting contents for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

[0468] Specifically, if one operand transfer setting is N bytes × M times, the transfer amount MOD is adjusted to a value that is an integer multiple of N × M (bytes) and an integer multiple of Dmin (bytes). For example, if N × M = 8 × 4 and Dmin = 256, the arbitrary value X (= 300) bytes is adjusted to the transfer amount MOD (= 512) bytes.

[0469] As explained above, including the general theory, the DMA operation of the DMAC circuit 60 starts a cycle steal transfer operation as shown in Fig. 8, and the display list DL is transferred to the transfer port TR_PORT in units of 32 bits in this embodiment, without interfering with the operation of the CPU. The transferred data is then transferred to the drawing circuit 76 via the transfer circuit ChB.

[0470] To achieve such an operation, in this embodiment, following the processing of step ST45, the data transfer circuit 72 starts the transfer operation and ends the processing (ST27). Thereafter, the data transfer circuit 72 receives a series of instruction commands of the display list DL from the DMAC circuit 60, with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. The drawing circuit 76 then executes the drawing operation based on the instruction commands of the display list DL. Therefore, after the processing of step ST27, the performance control CPU 63 can start the processing of step ST11 in FIG. 20, and can control the sound performance, lamp performance, and motor performance in parallel with the drawing operation by the VDP circuit 52 (DL issuing processing by the DMAC circuit 60).

[0471] This operation is illustrated in Fig. 23(c). Prior to the DMA transfer, the drawing circuit starts operating (ST25), the display list analyzer of the drawing circuit 76 executes the analysis process quickly and smoothly, and based on the operations of the GDEC 75, the geometry engine 77, etc., one frame's worth of image data is generated in the frame buffers FBa, FBb for each of the display devices DS1, DS2.

[0472] However, the configuration of Fig. 23 in which the DL issuing process ends with the process of step ST27 is not necessarily limited. For example, as in Figs. 30 to 31, when the sound effect, the lamp effect, and the motor effect are controlled by another CPU, it is preferable to check the normal operation of the DMAC circuit 60 and the data transfer circuit 72 after the process of step ST27. Fig. 24 is a flow chart explaining the process of checking the normal operation, which is the operation following step ST27 in Fig. 23.

[0473] First, a predetermined status register is referenced to confirm that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). Also, it is confirmed that the data transfer circuit 72 has completed the transfer operation (ST51). Usually, the DL issue process in FIG. 23 is completed through this route.

[0474] On the other hand, if the operation of the .DMAC circuit 60 is not completed even after waiting for a predetermined time, or if the data transfer circuit 72 has not completed its transfer operation, a clear value is set in a predetermined VDP register RGij for the drawing circuit 76 and the data transfer circuit 72 to initialize the DL issuance process (ST52). This is an operation based on the fact that the display list DL issuance process has not ended normally, and specifically, it is the same as the error process in step ST27 in Fig. 22 and the initial process in step ST20 in Fig. 23.

[0475] That is, in this case too, the drawing circuit 76 has already started operating and completed a certain amount of processing, so the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area.

[0476] Next, after prohibiting new DMA transfer operations (ST53), the process waits for the transfer operation of one operand being executed to finish (ST54). As explained above, in this embodiment, one operand is transferred by 32 bits x 2 times, and this is to avoid abruptly initializing the DMAC circuit 60 that is in operation.

[0477] Once this preparation work is complete, a clear value is set in a predetermined operation control register REG that defines the operation of the DMAC circuit 60, and the DMAC circuit 60 is initialized (ST52). Then, the serious abnormality flag ABN is set and the DL issuance process is terminated. In this case, since the abnormality can be expected to be recovered from by the processing of steps ST52 and ST55, it is also preferable to return to step ST20 in Fig. 23 and re-execute the DL issuance process without setting the serious abnormality flag ABN. However, it is necessary to count the number of re-executions of the DL issuance process (ST23 to ST27), and if the number of re-executions exceeds a limit value, to set the serious abnormality flag ABN and terminate the DL issuance process.

[0478] Next, the main control process when the preloader 73 is used will be described with reference to Fig. 25. The process in Fig. 25 is similar to the process in Fig. 20, but first the contents of the start condition determination (ST5') are different. That is, in the embodiment using the preloader, at the start of each operation cycle, a READ access is made to the status information of the drawing circuit 76 and the preloader 73 to confirm that the drawing operation based on the display list DL1 has ended, and that the preload operation based on the display list DL2 has ended (ST5').

[0479] 29(a), the preloader 76 should have completed a look-ahead operation (preload operation) during an operation cycle (T1 to T1+δ) based on the display list DL1 issued during that operation cycle (T1). Also, the drawing circuit 76 should have completed a drawing operation based on the display list DL1 during that operation cycle (T1+δ to T1+2δ) based on an operation start command issued during that operation cycle (T1+δ).

[0480] Therefore, in (ST5'), the status information of the VDP register RGij related to the drawing circuit 76 and the preloader 73 is read and accessed to confirm the above-mentioned normal operation. Fig. 29(a) shows a state in which normal operation is confirmed at the judgment timings of the operation cycles T1, T1+δ, T1+2δ, and T1+4δ, but the preload operation has not ended at the judgment timing of the operation cycle T1+3δ.

[0481] In the event of such an abnormality, the abnormality flag ER is incremented (ER=ER+1) and the process proceeds to step ST9. Therefore, as in the embodiment of FIG. 20, a frame is dropped. That is, the display area switching process (ST6) is skipped, and the same screen is redisplayed. The operating period (T1+3δ to T1+4δ) shown in FIG. 28(a) shows this operating state.

[0482] Furthermore, if the start condition is not satisfied in the determination of step ST5', a start instruction (PT10) for a drawing operation based on the rewrite list DL' is not executed to the drawing circuit 76, so the drawing circuit 76 is in a non-operating state, and a new display list is not generated. Note that in Fig. 29(a), timings t0, t2, and t4 indicate the operation timing of the start instruction (PT10) for a drawing operation, more precisely, the timing of step ST26 in Fig. 26.

[0483] The above describes the case where the judgment in step ST5' is non-compliant, but in the normal case, after toggling the display areas of the frame buffers FBa and FBb (ST6), the drawing circuit 76 is made to start drawing operations based on the rewrite list DL' (PT10). The specific contents are as shown in Fig. 26, and the drawing circuit 76, under the control of the performance control CPU 63, acquires the rewrite list DL' from the DL buffer BUF' of the external DRAM 54 via the data transfer circuit 72 (transfer circuit ChB) and executes the drawing operations.

[0484] 26 which realizes this operation, the operation of the preloader 73 will be examined; the preloader 73 has already completed the look-ahead operation (preload) of the CGROM 55 based on the display list DL acquired one operation cycle ago, and the look-ahead data has already been stored in a preload area secured in the external DRAM 54. Also, for texture load commands (TXLOAD) written in the display list DL, their source addresses have been rewritten to addresses in the preload area, and these have been stored in the DL buffer BUF' of the external DRAM 54 as a rewrite list DL'.

[0485] In this rewrite process, the total amount of data in the display list DL does not change, and the total amount of data in the rewrite list DL' is the same as that in the display list DL. The display list DL is created by the standard method (B), and the end of the rewrite list DL' is an EODL command, just like the display list DL.

[0486] Considering the above, referring to Fig. 26, the performance control CPU 63 first sets a clear value to a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively, to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is the same as the process of ST20 in Fig. 23. Next, it is confirmed that this initialization process has ended normally (ST21), and in the unlikely event that the initialization is not completed even after a predetermined time has passed, the major abnormality flag ABN is set and the process is terminated (ST22).

[0487] Usually, the initialization of the data transfer circuit 72 and the drawing circuit 76 ends normally, so the transmission route within the data transfer circuit 72 is set to a predetermined data transfer register RGij (ST23). Specifically, it is set to transfer data from the external DRAM 54 to the drawing circuit 76 via the ChB control circuit 72b (ST23). Next, for the DL buffer BUF' of the external DRAM 54 in which the rewrite list DL' is stored, its top address is set to a predetermined data transfer register RGij (ST24).

[0488] Also, for this rewrite list DL', the total transfer size is set in a predetermined data transfer register RGij (ST25). As described above, the total amount of data in the rewrite list DL' is the same as the total amount of data in the display list DL, and specifically, for example, is 256 bytes.

[0489] Next, the drawing operation of the drawing circuit 76 is started based on the set value of the predetermined drawing register RGij (ST26). Timings t1, t2, t3, and t4 in FIG. 28(a) are also the operation timings of step ST26. Next, the operation of the data transfer circuit 60 is started based on the set value of the predetermined data transfer register RGij, and the process ends (ST27). Thereafter, the performance control CPU 63 is not particularly involved in the operation of the data transfer circuit 72 or the drawing circuit, and proceeds to the generation process (ST7) of a display list to be executed in the next operating cycle.

[0490] On the other hand, the drawing circuit 76, which starts operating at the timing of step ST26, executes drawing operations based on the rewrite list DL', and generates image data based on the rewrite list DL' in the frame buffers FBa and FBb. Note that in this operation, the drawing circuit 76 does not perform READ access to the CGROM 55, but only performs READ access to the preload area, so that a series of drawing operations can be completed quickly.

[0491] Having explained the process contents of step PT10 above, returning to Fig. 25 to continue the explanation, after the process of step PT11, in an embodiment utilizing the preloader 73, a display list DL to be executed in the next cycle is created based on the standard method (B) (ST7). For example, in the operation cycle (T1) shown in Fig. 29(a), a display list DL to be referenced by the drawing circuit 76 is created in the operation cycle (T1+δ), which is the next cycle.

[0492] Next, the performance control CPU 63 issues the created display list DL to the preloader 73, not to the drawing circuit 76 (PT11). The specific operation is as shown in Fig. 27. Previously, in relation to the embodiment (Fig. 20) in which the preloader 73 is not used, the performance control CPU 63 has shown a case in which the display list DL is issued directly to the drawing circuit 76 (Fig. 22) and a case in which the display list is issued via the DMAC circuit 60 (Fig. 23). In Fig. 27, almost the same operation is shown in Figs. 27(b) and 27(c), except that the issuing destination is the preloader 73.

[0493] Fig. 27(a) is a flow chart for explaining the operation of Fig. 27(b), and is almost the same as the flow chart of Fig. 22. However, it is set that the data is transferred from the CPUIF unit 56 via the ChC control circuit 72c, and that the data is transferred to the CPU bus control unit 72d while checking the remaining capacity of the FIFO buffer (ST20). In the following description, the ChC control circuit 72c may be abbreviated as "transfer circuit ChC" for convenience.

[0494] Next, the total transfer size (for example, 256 bytes adjusted by the standard method (B)) is set in a predetermined data transfer register RGij, and the management counter CN is initialized to 64 (ST21). Next, the data transfer operation via the transfer circuit ChC is set to a start state (ST22), and the preload operation is started based on the set value in the preload register RGij that specifies the operation of the preloader 73 (ST23).

[0495] As a result, thereafter, the preloader 73 executes the necessary analysis (Analyze) processing for each instruction command that the performance control CPU 63 writes to the transfer port TR_PORT, and when it detects an instruction command (TXLOAD) to access CGROM 55 for READ, it preloads the texture and stores it in the preload area of ​​DRAM 54. It also stores the rewrite list DL' in which the source address of the texture has been changed in the DL buffer area BUF' of DRAM 54.

[0496] Timings t1, t3, and t5 in Fig. 29(a) practically indicate the operation timing of step ST23 in Fig. 27. However, also in this embodiment, if any abnormality occurs during the process of issuing the display list DL, the processes of steps ST25 and ST27 are executed. Specifically, the operations of the data transfer circuit 72 and the preloader 73 are initialized, and the process of issuing the display list DL (ST20 to ST30) is executed again to the extent possible. The initialization process of the preloader 73 includes erasing the incomplete rewrite list DL' and clearing the preload area in which new preload data has been stored.

[0497] Although the above has described in detail the cases where the preloader 73 is used and where it is not used, the specific operation contents are not particularly limited. Fig. 28(b) shows an embodiment in which the display list generated by the performance control CPU 63 is issued to the drawing circuit 76 with a delay of one operation cycle δ, rather than the operation cycle in which it was generated. In such an embodiment, the drawing circuit 76 can use almost the entire time of one operation cycle (δ), thereby reducing the possibility of frame dropping.

[0498] 29(b) shows an embodiment in which the display list generated by the performance control CPU 63 is issued to the preloader 73 one operation cycle later than the operation cycle in which the display list was generated. In this case, the preloader 73 can execute the preloading operation using almost the entire time of one operation cycle (δ), so that the possibility of frame dropping is also reduced in this case.

[0499] In the above explanation, the composite chip 50 is used, but it is not necessary to integrate the performance control CPU 63 and the VDP circuit 52 into a single element. Furthermore, in the above embodiment, the entire performance control is controlled by a single CPU (performance control CPU 63), but the upstream CPU and the downstream performance control CPU 63 may cooperate with each other to execute the performance control operation.

[0500] 30 and 31 are block diagrams showing such an embodiment. As shown in the figures, in this embodiment, the upstream performance control CPU controls the audio performance, the lamp performance, and the motor performance. Meanwhile, the downstream CPU circuit 51 controls only the image performance based on the control command CMD' received from the performance control CPU.

[0501] When such a configuration is adopted, the CPU circuit 51 does not need to execute the process of step ST12 in Fig. 20(a) and the process of Fig. 20(b), and can take a sufficient amount of time to generate a complex display list DL, thereby enabling more complex and advanced image presentation such as 3D (Dimension) to be realized. In such a case, the display list becomes large, but in that case, the total data amount of the display list DL is adjusted to 512 bytes or more, that is, N x 256 bytes, by adding a dummy command.

[0502] In addition, since the operation of the downstream CPU circuit 51 is specialized for image presentation control, it is also possible to check whether the drawing operation is completed after the display list DL is issued. The lower part of Fig. 22 shows an example of operation control in this case, and if the drawing operation is not completed even after the limit time has elapsed, the serious abnormality flag ABN is set and processing ends (ST32). Note that since the processing of the downstream CPU circuit 51 is limited to image presentation control, it is also possible to simply wait for the drawing operation to be completed in an infinite loop.

[0503] When such a configuration is adopted, the start condition determination (ST5) in Fig. 20(a) can be repeated for a predetermined time. Even with such a configuration, if the delay in the completion of the drawing operation is not too long, the only problem that occurs is a delay in switching between display area (0) and display area (1). That is, as in the operation period T1+3δ shown in Fig. 32(a), in one operation period in which the display operation is repeated twice, a frame drop state occurs only in the first half, and normal frames are displayed in the second half.

[0504] This is also the case when a preloader is used, and the start condition determination (ST5') in FIG. 25(a) can be repeated for a predetermined time. If there is a slight delay, then, as in the operation cycle T1+3δ shown in FIG. 32(b), only the first half will experience frame dropping, and normal frames will be displayed in the second half. However, if the completion of the drawing operation is significantly delayed, then complete frame dropping will occur, as in the operation cycle T1+3δ in FIG. 28(a), and if this situation continues, the WDT circuit 58 will be activated. This is also the case when a preloader is not used.

[0505] Furthermore, in an embodiment in which the control operation of the CPU circuit 51 is specialized for image rendering control, as shown in the lower part of Fig. 24, the completion of the drawing operation of the drawing circuit 76, the completion of the operation of the data transfer circuit 72, and the completion of the operation of the DMAC circuit 60 are determined (ST50' to ST52'). If any of the operations does not end normally, the operations of the data transfer circuit 72 and the drawing circuit 76 are initialized, and the same processing as the processing of steps ST53 to ST55 (ST55' to ST57') is executed. In this case, it is also preferable to re-execute the DL issuance process a predetermined number of times.

[0506] The above describes an embodiment in which an index space with a horizontal size that completely matches the number of horizontal pixels of each display device is constructed as the frame buffers FBa and FBb of the main display device DS1 and the sub display device DS2. Figure 33(a) clearly illustrates this relationship, showing a case in which the drawing area (W×H) in the virtual drawing space and the effective data area (actual drawing area W×H) in the index space both match the number of horizontal / vertical pixels of the display devices.

[0507] In such a correspondence relationship, the drawing operation into the virtual drawing space by the display list DL is not necessarily limited to the drawing area (W×H). For example, as shown by the left sloping line at the top of Figure 33(a), by moving the drawing position in time for a drawing image (W'×H') that exceeds the drawing area (W×H), it is possible to appropriately move the drawing content into the actual drawing area W×H shown by the right sloping line at the bottom of Figure 33(a) vertically / horizontally / diagonally.

[0508] To achieve this effect, an index space with a horizontal size W larger than the number of horizontal pixels of the display device may be provided, as shown in Fig. 33(b), for example. In this case, the drawing area W×H in the virtual drawing space defined by the instruction command L12 (SETDAVF) in the display list DL is set to be larger than the actual drawing area w×h corresponding to the number of horizontal / vertical pixels of the display device. Note that the actual drawing area w×h is indicated by a right-sloping line at the bottom of Fig. 33(b).

[0509] The vertical and horizontal dimensions of the actual drawing area w×h are then identified as the number of display lines and the number of horizontal pixels of the display device in step SS30 of FIG. 20, and the upper left corner point of the actual drawing area w×h is set in a specified display register as the vertical / horizontal display start position in step SS31 of FIG. 20.

[0510] On the other hand, the base address (X, Y) in the index space is set in a predetermined drawing register by the display list instruction command L11. As explained above, specifically, the upper left base address on the index space IDX is specified as (0, 0), for example, by the environment setting instruction command L11 (SETDAVR). If the upper left end point of the actual drawing area w×h is moved appropriately in the normal processing, the drawing contents of the actual drawing area W×H shown by the right slanting line at the bottom of Figure 33(b) will move vertically / horizontally / diagonally as appropriate.

[0511] As explained with respect to Figure 20, the VDP registers RGij relating to steps SS30 to SS32 are write-prohibited after initial setting (second prohibition setting SS34), but at the timing of executing the above-mentioned performance, this prohibition is released by writing a release value to a specific VDP register RGij.

[0512] In the above embodiment, the first and second type inhibition setting registers are utilized to uniformly set the predetermined system control register RGij and the predetermined VDP register RGij of the initial setting system to a write inhibit state (see SS33 and SS34 in FIG. 20 and FIG. 25), so that the set values ​​of these registers are not changed thereafter due to the influence of noise, etc. However, it is also preferable to repeat the setting process for the set values ​​of important system control registers RGij at predetermined time intervals without setting them to such a write inhibit state.

[0513] Fig. 34 is a diagram for explaining the processing in such a case, and the setting values ​​to be set in the initial setting processing (ST3) are collected in a setting value table SETTABLE stored in the control memory 53 (PROGMROM). Note that, although explanation is omitted for step ST3 in Fig. 20, (a) the initial setting processing is executed based on the initial value setting table SETTABLE, and (b) the contents of the initial value setting table SETTABLE are substantially the same as those explained below in the embodiment of Fig. 20.

[0514] In any embodiment, the setting value table SETTABLE is composed of multiple sets (N sets) of the register address value of the VDP register RGij and the setting value for that register RGij. Although not particularly limited, the register address value is fixed to a length of 16 bits, and the setting value is fixed to a length of 32 bits, and since each is a fixed length, the data capacity of the initial value setting table SETTABLE is 6×N bytes (=48t×N bits) long, and there are N VDP registers RGij.

[0515] However, in the embodiment of FIG. 20, the initial value setting table SETTABLE is accessed for READ only once and all N VDP registers RGij are initialized only once, whereas in the embodiment of FIG. 34, all N VDP registers RGij are divided into N1 VDP registers RGij that are initialized only once and N2 VDP registers RGij that are repeatedly initialized every 1 / 30 seconds after the first initialization.

[0516] In the embodiment of FIG. 34, the setting values ​​that are repeatedly initialized include (1) setting values ​​for DMA transfer operations, (2) setting values ​​for VRAM, (3) setting values ​​for interrupts, (4) setting values ​​for the display circuit 74, and (5) setting values ​​for the drawing circuit 76.

[0517] (1) The setting values ​​related to the DMA transfer operation are, for example, setting values ​​that are prerequisites for the operating conditions specified in step ST41, and are basic setting values ​​that are fixedly applied regardless of the differences in the operating conditions in Fig. 23(c) and Fig. 27(c). Specifically, the setting values ​​include (a) a threshold value (e.g., 1 / 2 of the entire stage) for how much of the FIFO buffer (N stages) built into the DMA circuit 60 needs to be released before a transfer request is made to the transfer source, and (b) whether or not to perform a handshake operation with the transfer destination and transfer source (e.g., No).

[0518] Also, (2) the VRAM setting value includes the refresh cycle of the refresh operation. The built-in VRAM 71 operates at this refresh cycle to prevent natural discharge of stored data. Next, (3) the interrupt setting value is a value that specifies the type of error that will cause an interrupt request and the output terminal of the interrupt signal (internal terminal of the built-in CPU), and includes, for example, setting values ​​such as (a) that if the drawing circuit 76 freezes, a drawing abnormality interrupt is generated for the CPU circuit 51 (interrupt enabled state, see FIG. 20(d)), and (b) that when VBLANK of the display device DS1 starts, a VBLANK start interrupt is generated for the CPU circuit 51 (see FIG. 20(c)).

[0519] In this embodiment, a composite chip 50 is used in which the CPU circuit 51 and the VDP circuit 52 are integrated, but if they are separate chips, the output terminal from which the VDP circuit 52 outputs an interrupt signal is connected to the external interrupt input terminal of the CPU circuit 51.

[0520] In addition, (4) the setting values ​​related to the display circuit include (a) the horizontal / vertical starting position of each frame buffer (see SS31), (b) the setting value related to the horizontal synchronization signal of each display device, (c) the setting value related to the vertical synchronization signal of each display device, (d) the setting value related to the scaler, and (e) the setting values ​​of the number of horizontal pixels and the number of display lines of each display device (SS30).

[0521] (5) The setting values ​​related to the drawing circuit 76 include a setting value of the freeze time until a drawing abnormal interrupt occurs. This setting value is set, for example, as an integer multiple of the period of the vertical synchronization signal. As explained in FIG. 20(d), if the drawing circuit 76 does not access the VRAM during the freeze period specified here, the drawing circuit 76 is individually reset (ST16b), and the operating parameters for the drawing circuit 76 are re-set (ST16c).

[0522] As described above, in this embodiment, important set values ​​are repeatedly reset at predetermined time intervals, so that even if the set value is corrupted due to the influence of noise, etc., the abnormality is immediately restored. Also, in this embodiment, unlike the embodiment of Fig. 20, the first and second type inhibition setting registers RGij are not inhibited from being write-inhibited, so that rewriting can be freely performed without going through a somewhat complicated inhibition release process.

[0523] In the above embodiments, a configuration has been described in which a drawing abnormality interrupt is generated from the drawing circuit 76 of the VDP circuit 52 to the CPU circuit 51 when (1a) the drawing circuit 76 enters an operation freeze state after a predetermined freeze time has elapsed, or (1b) the drawing circuit 76 detects an irrational instruction command in the display list DL (see FIG. 20(d)). When a drawing abnormality interrupt occurs, the cause of the interrupt is determined (ST16a in FIG. 20(d)), and processing is executed according to the determination result (ST16c to ST16d).

[0524] However, according to the inventor's experiments, even under harsh operating conditions with a lot of noise, drawing abnormality interrupts rarely occur. Therefore, in order to reduce the control burden, it is preferable to either uniformly shift to an infinite loop process (see FIG. 25(b)) without providing the interrupt cause determination process (ST16a), or to operate the pattern check circuit CHK (see FIG. 6(b)) (see ST17a in FIG. 25(c)).

[0525] In this case, the WDT circuit 58 will then be started after a prescribed time and the entire combined chip 50 will be reset, or alternatively, just the VDP circuit 52 will be immediately reset thereafter (see FIG. 6(b)).When the VDP circuit 52 is reset based on the reset keyword output process (ST17a), the normal completion of the reset operation will be confirmed and the stack area for storing the return address will be sorted (ST17b), after which the process will proceed to, for example, step ST4 or ST13.

[0526] In this embodiment, since the abnormality determination process (ST5 in FIG. 20 or FIG. 25) is provided to determine the completion of the operation of the drawing circuit 76 every 1 / 30 seconds, a drawing abnormality interrupt process (FIG. 25(d)) that does not actually execute anything may be provided to further reduce the control load. As shown in FIG. 25(d), in this configuration, when a drawing abnormality interrupt occurs, an IRET (Interrupt Return) command is immediately executed to return to the main control process, so the frozen state of the drawing circuit 76 continues as is. However, in this embodiment, the number of frame drops is counted by the abnormality flag ER in the process of step ST5 in FIG. 20 or FIG. 25, and the WDT circuit 58 or the pattern check circuit CHK will be started soon, so the configuration of FIG. 25(d) is substantially the same as the configuration of FIG. 25(b) or FIG. 25(c).

[0527] In order to further reduce the control load, it is also preferable to set the VDP circuit 52 to a drawing abnormality interrupt disabled state during initialization (see step ST3 in FIG. 20 and FIG. 25). If the configuration is such that the drawing abnormality interrupt disabled state is the default state when the power is turned on, then (a) a specific system control register RGij, in which an enable / disable value that specifies whether an abnormality interrupt is enabled or disabled, should be set, is set to a write-disabled state, or (b) a disable value is repeatedly written to the system control register RGij at specific time intervals.

[0528] At first glance, this configuration seems superior to the configuration of Fig. 25(b) or Fig. 25(b). However, from the viewpoint of versatility of the control program, it is better to (a) uniformly set the drawing abnormal interrupt to a prohibited state for all types of gaming machines of this type, and then select for each type whether to adopt the configuration of Fig. 20(d) or one of Figs. 25(b) to (d), after uniformly setting the drawing abnormal interrupt to a permitted state. Note that the former configuration (a) requires (complexity) changing the initial setting routine (see step ST3 in Fig. 20 or Fig. 25) for each type.

[0529] As a further modified embodiment, it is also preferable to utilize the audio circuit SND built into the composite chip 50. Fig. 35 is a block diagram showing such an embodiment. As is clear from comparing Fig. 35 with Fig. 6, in this embodiment, the audio processor 27 and audio memory 28 are not required, and external wiring to the audio circuit is not required for the data bus (8 bits) and address bus (2 bits) of the CPU circuit 51. In addition, since there is no transmission line for the underflow signal UF, the risk of the composite chip being erroneously reset due to noise superimposed on this UF transmission line is also avoided.

[0530] In this embodiment, in order to eliminate the voice memory 28, the voice data to be stored in the voice memory 28 is stored in the CGROM 53. Fig. 36(d) illustrates the storage contents of the CGROM 53, which permanently stores sound ROM header information, phrase header information HD, a large number of phrase data PH compressed from a group of voice data, and a large number of sound commands SCMD which specify the operation of the voice circuit SND.

[0531] As shown in the figure, sound ROM header information is stored from the start address SNDst, followed by phrase header information HD of data size HDvl stored from the start address HDst, phrase data PH of data size PHvl stored from the start address PHst, and sound command SCMD of data size SCMDvl stored from the start address SCMDst.

[0532] Here, the sound ROM header information specifically means the head address HDst of the phrase header HD area, the data size HDvl of the phrase header HD area, the head address PHst of the phrase data area PH, the data size PHvl of the phrase data area PH, the head address SCMDst of the sound command area SCM, and the data size SCMDvl of the sound command area SCMD. These pieces of information are acquired by the internal circuit of the sound circuit SND when the power is turned on (see step SD4).

[0533] Moreover, the phrase header information HD and phrase data PH are transferred to the external DRAM 54 when the power is turned on, thereby speeding up subsequent READ access (step SD6). Thus, in this embodiment, the voice processor 27 and voice memory 28 are eliminated, thereby achieving miniaturization and reduced manufacturing costs, and overcoming the weakness of the CGROM 53, which is low-cost and easy to increase in capacity, but has a slow access speed.

[0534] Based on the above, the initial setting process at the time of power-on will be described with reference to Fig. 36(a). Note that this process is executed as part of the process of step ST3 in Fig. 20 or Fig. 25.

[0535] As explained with reference to Fig. 6(b), when the power is turned on or when an abnormal reset occurs in which the WDT 58 is activated, the audio circuit SND is hardware reset via the reset path 2 (step SD1). Also, if the performance control CPU 63 detects an abnormality in the audio circuit SND, the audio circuit SND is hardware reset via the reset path 4B or 4C (step SD1). Note that the performance control CPU 63 may activate the pattern check circuit CHK, causing the audio circuit SND to be hardware reset together with the other circuits (72, 73, 74, etc.) (step SD1).

[0536] In either case, the performance control CPU 63 then confirms that the reset operation has been completed normally (step SD2), and first sets the top address SNDst of the sound data area to the system control register RGij of the sound circuit SND (step SD3). Next, a predetermined value is set in a predetermined system control register, causing the sound ROM header information HD to be stored in the internal circuit. The sound ROM header information HD is the six elements (HDst, HDvl, PHst, PHvl, SCMDst, SCMDvl) mentioned above, as shown in FIG. 36(c).

[0537] Then, it is confirmed that the processing up to this point has been normal, and if it should not end normally, the audio circuits are individually reset via the reset path 4B or 4C. However, since normal end can usually be confirmed, the phrase header information HD and phrase data PH are then transferred to the external DRAM 54 using the data transfer circuit 72 (step SD6). Note that the destination start address BGN, the source start address HDst, the total amount of data to be transferred HDvl+FDvl, etc. are appropriately specified in the data transfer circuit 72.

[0538] Next, a predetermined system control register RGij is set to indicate that the phrase header information HD and phrase data PH are stored in the external DRAM 54, not in the CGROM 55 (step SD7), and the start address BGN (sound RAM start address) of the grou...

Claims

[Claim 1] A CPU circuit is provided having a CPU for executing program processing, a DMAC (Direct Memory Access Controller) circuit which is divided into a plurality of channel circuits capable of operating in parallel and for which priority can be specified, and an operation control register in which a setting value for specifying the operation of the DMAC circuit is set, A gaming machine in which a VDP (Video Display Processor) and a CPU that issues a display list to the VDP function to execute various performance operations including image performance, The memory space accessible by the CPU includes a plurality of external address spaces that are located outside a CPU circuit including the CPU and each of which can define a data bus width, The memory space accessible by the VDP includes a CG memory for storing CG compressed data and a video RAM used for generating image data for image presentation. Among the plurality of external address spaces, a predetermined ROM space stores in a non-volatile manner first address information belonging to the external address space and second address information not belonging to any of the external address spaces; After the CPU is reset, the second address information is set in a stack pointer of the CPU, and the first address information is set in a program counter of the CPU, thereby starting execution of a predetermined initial program, and then the DMAC circuit functions to enable DMA transfer of data necessary for the performance operation; In the video RAM, a plurality of memory areas are allocated based on a base address in which all lower bits below a predetermined bit position are 0, A gaming machine configured such that the destination of the CG compressed data in a specified memory area is determined by the VDP.

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