Gaming machine

Abstract

To provide a game machine capable of suitably performing management of a game machine.SOLUTION: A main-side RAM 344 includes a total game number counter 344a and an advantageous game number counter 344b. The total game number counter 344a measures a total of games consumed without any regardless of a game state, and the advantageous game number counter 344b measures a total number of games consumed in an ART state as the number of advantageous games. A ratio of the number of advantageous games to the total number of games is reported by notification display devices 346 to 348. The notification display devices 346 to 348 are provided on a main control device 341, and the main control device 341 is illuminated with lighting devices 349a, 349b when a front door is opened. When a ratio of the number of advantageous games to the total number of games reaches at least a predetermined ratio, a shift to the ART state is restricted.SELECTED DRAWING: Figure 86

Description

[Technical field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to a player, and the game balls stored in the tray storage section are guided to a game ball launching device and launched toward a game area in response to a launching operation by the player. Then, for example, when a game ball enters a ball entry section provided in the game area, the game ball is paid out from a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko machines, and in this case, the game balls stored in the upper tray storage section are guided to the game ball launching device, and the game balls that are surplus in the upper tray storage section are discharged to the lower tray storage section (see, for example, Patent Document 1).

[0003] In addition, in a slot machine, when a start lever is operated to start a new game while medals have been bet, a lottery process is executed by the control means. When the lottery process is executed, the control means executes a rotation start control to start the rotation of the reels, and when a stop button is operated during the rotation of the reels, the control means executes a rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2009-261415 A Summary of the Invention [Problem to be solved by the invention]

[0005] Here, in the gaming machines such as those exemplified above, The gaming machines need to be properly managed, There is still room for improvement in this regard.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, It is possible to optimally manage gaming machines. The object of the present invention is to provide a gaming machine that is [Means for solving the problem]

[0007] In order to solve the above problem, the invention described in claim 1 is as follows: a predetermined storage execution means for causing a predetermined event to occur as a result of a game to be stored in a predetermined storage means, whereby the predetermined information is stored in the predetermined storage means; an information calculation means for calculating behavior information corresponding to a game result during a predetermined period of time using the predetermined information each time a predetermined calculation trigger occurs; a result storage and execution means for sequentially storing the aspect information obtained by the calculation by the information calculation means in a calculation result storage means; Equipped with the result storage execution means includes means for causing the behavior information to be stored among the behavior information obtained by the calculation by the information calculation means to be stored in the calculation result storage means; The aspect information obtained by the calculation by the information calculation means, which is not a storage target, is not stored in the calculation result storage means, This gaming machine is A means for generating a specific advantageous period when a specific opportunity occurs; a notification means capable of notifying the user of the content corresponding to the aspect information stored in the calculation result storage means; Equipped with The information calculation means calculates the status information using the predetermined information during the specific advantageous period as the status information corresponding to the game result during the predetermined period. It is characterized by: Effect of the Invention

[0008] According to the present invention, Manage gaming machines appropriately It becomes possible. [Brief description of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a pachinko machine according to a first embodiment. [Diagram 2] 1 is an exploded perspective view showing the main components of a pachinko machine. [Diagram 3] FIG. 2 is a front view showing the configuration of the game board. [Figure 4] An explanatory diagram to explain the configuration regarding the discharge of game balls that have flowed down the game area. [Diagram 5] FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. [Figure 6] FIG. 13 is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. [Figure 7] 4 is a flowchart showing a main process executed by a main CPU. [Figure 8] 13 is a flowchart showing a timer interrupt process executed by a main CPU. [Figure 9] This is an explanatory diagram to explain the configuration in which the detection results of the ball entry detection sensor are input to the main CPU. [Figure 10] This is a flowchart showing the ball entry detection processing executed by the main CPU. [Figure 11] A block diagram to explain the electrical configuration of a dispensing control device and various devices that communicate with the dispensing control device. [Figure 12] 13 is a flowchart showing the timer interrupt processing executed by the dispensing CPU. [Figure 13] FIG. 2 is a block diagram for explaining an electrical configuration of a management IC. [Figure 14] FIG. 2 is an explanatory diagram for explaining the configuration of an input port of a management side I / F; [Figure 15] FIG. 2 is an explanatory diagram for explaining a configuration of a correspondence relationship memory; [Figure 16] FIG. 2 is an explanatory diagram for explaining a configuration of a history memory; [Figure 17] 13 is a flowchart showing a recognition process executed by a main CPU. [Figure 18] 13 is a flowchart showing a management process executed by a management CPU. [Figure 19] 13(a) to 13(d) are time charts showing how information on the correspondence between the first to fifteenth buffers and the types of signals is stored in a correspondence memory. [Figure 20] 13 is a flowchart showing a management output process executed by a main CPU. [Figure 21] 13 is a flowchart showing a history setting process executed by a management CPU. [Figure 22] 13(a) to 13(e) are time charts showing how history information is stored in a history memory. [Diagram 23] 13 is a flowchart showing a data output process executed by a main CPU. [Figure 24] 13 is a flowchart showing an external output process executed by a management CPU. [Diagram 25] FIG. 11 is an explanatory diagram for explaining a configuration of an input port of a management side I / F in the second embodiment. [Figure 26] 13 is a flowchart showing a recognition process executed by a main CPU. [Figure 27] 13 is a flowchart showing a management process executed by a management CPU. [Figure 28] 13(a) to 13(h) are time charts showing how information on the correspondence between the first to twelfth buffers and the types of signals is stored in a correspondence memory. [Figure 29] FIG. 13 is a block diagram for explaining the electrical configuration of a management IC according to a third embodiment. [Diagram 30] FIG. 2 is an explanatory diagram for explaining the configuration of an input port of a management side I / F; [Diagram 31] 13 is a flowchart showing a power outage information storage process executed by a main CPU. [Diagram 32] 13 is a flowchart showing a power failure response process executed by a management CPU. [Diagram 33] 13 is a flowchart showing an external output process executed by a management CPU. [Diagram 34] 13 is a flowchart showing a power failure response process executed by a control CPU in the fourth embodiment. [Diagram 35] 13A is a flowchart showing a trigger identification process executed by a main CPU in the fifth embodiment, and FIG. 13B is a flowchart showing a calculation process executed by a management CPU. [Diagram 36] 23 is a flowchart showing a trigger identification process executed by a main CPU in the sixth embodiment. [Figure 37] 23 is a flowchart showing a calculation process executed by a control-side CPU in the seventh embodiment. [Figure 38] 23 is a flowchart showing a history setting process executed by a management CPU in the eighth embodiment. [Figure 39] FIG. 23 is an explanatory diagram for explaining the configuration of a history memory in the ninth embodiment. [Diagram 40] 13 is a flowchart showing a history setting process executed by a management CPU. [Diagram 41] FIG. 23 is a block diagram for explaining the electrical configuration of an MPU of a main control device in a tenth embodiment. [Diagram 42] This is a flowchart showing the ball entry detection processing executed by the main CPU. [Diagram 43] FIG. 23 is a block diagram for explaining the electrical configuration of a main control device in the eleventh embodiment. [Diagram 44] FIG. 2 is an explanatory diagram for explaining the configuration of an input port of a management side I / F; [Diagram 45] FIG. 2 is an explanatory diagram for explaining a configuration of a history memory; [Diagram 46] 13 is a flowchart showing a history setting process executed by a management CPU. [Figure 47] 13 is a flowchart showing an external output process executed by a management CPU. [Figure 48] 13 is a flowchart showing a parameter management process executed by a main CPU. [Figure 49] A block diagram to explain the configuration of the signal path that transmits the detection results of each ball entry detection sensor to the main CPU and management IC in the 12th embodiment. [Figure 50] A block diagram for explaining the electrical configuration of the main control device and the audio and light emission control device in the thirteenth embodiment. [Figure 51] 13 is a flowchart showing a timer interrupt process executed by a main CPU. [Figure 52]13 is a flowchart showing the special chart special power control processing executed by the main CPU. [Diagram 53] 13 is a flowchart showing the performance control process executed by the sound / light side CPU. [Figure 54] This is a flowchart showing the special chart change start processing executed by the main CPU. [Figure 55] 13 is a flowchart showing the special call start processing executed by the main CPU. [Figure 56] 1 is an explanatory diagram for explaining a normal counter area, an opening / closing execution mode counter area, and a high frequency support mode counter area provided in a main RAM. FIG. [Figure 57] This is a flowchart showing the ball entry detection processing executed by the main CPU. [Figure 58] This is a flowchart showing the normal ball scoring detection processing executed by the main CPU. [Figure 59] 13 is a flowchart showing a check process executed by a main CPU. [Figure 60] (a) is a front view of the special map display section, (A) is an explanatory diagram for explaining the display contents of the special map display section, (b) is a front view of the general map display section, and (B) is an explanatory diagram for explaining the display contents of the general map display section. [Figure 61] 13 is a flowchart showing a check waiting process executed by a main CPU. [Figure 62] 13 is a flowchart showing a process during display of a check result executed by a main CPU. [Figure 63] 13(a) to 13(g) are time charts showing the progress of a check waiting period and a check result display period. [Figure 64] 4 is a flowchart showing a main process executed by a main CPU. [Figure 65] 1(a) to (j) are diagrams showing individual patterns that are variably displayed on a pattern display device. [Figure 66] 1A and 1B are diagrams showing the display surface of a pattern display device. [Figure 67]13A and 13B are explanatory diagrams for explaining the display contents of the pattern display device during the check waiting period or the check result display period. [Figure 68] 23 is a flowchart showing a check process executed by a main CPU in the fourteenth embodiment. [Figure 69] 13 is a flowchart showing a process during display of a check result executed by a main CPU. [Figure 70] 13(a) to 13(g) are time charts showing the progress of a check waiting period and a check result display period. [Figure 71] 23 is an explanatory diagram for explaining the configuration of an input port provided in an MPU of an audio and light emission control device in the fifteenth embodiment. FIG. [Figure 72] 11 is an explanatory diagram for explaining the configuration of a correspondence area provided in the audio / optical side ROM; FIG. [Figure 73] 13 is a flowchart showing a management output process executed by a main CPU. [Figure 74] 13 is a flowchart showing the performance control process executed by the sound / light side CPU. [Figure 75] 10 is an explanatory diagram for explaining a normal counter area, an opening / closing execution mode counter area, and a high frequency support mode counter area provided in the sound / light side RAM. FIG. [Figure 76] 13 is a flowchart showing a history setting process executed by a CPU on the sound and light side. [Figure 77] 13 is a flowchart showing a check process executed by a CPU on the sound and light side. [Figure 78] A front view of the main control device in the 16th embodiment. [Figure 79] 79 is a cross-sectional view taken along line AA in FIG. 78. [Figure 80] FIG. 23 is a front view of the slot machine according to the seventeenth embodiment. [Figure 81] 1 is an oblique view of the slot machine with the front door open. [Figure 82] FIG. [Figure 83] 1 is an explanatory diagram for explaining the arrangement of symbols on each reel. FIG. [Figure 84] FIG. [Figure 85] FIG. 13 is an explanatory diagram for explaining the correspondence between winning symbol combinations and the benefits that are awarded when a winning combination is achieved. [Figure 86] FIG. 2 is a block diagram showing the electrical configuration of the slot machine. [Figure 87] 4 is a flowchart showing main processing executed by a main MPU. [Figure 88] 11 is a flowchart showing a timer interrupt process executed by a main MPU. [Figure 89] 11 is a flowchart showing normal processing executed by a main MPU. [Figure 90] 13 is a flowchart showing a lottery process executed by the master MPU. [Figure 91] FIG. 13 is a diagram showing an example of a lottery table for a normal mode. [Figure 92] 13 is an explanatory diagram for explaining the relationship between the stopping order of the reels and the winning patterns that are achieved when the lottery table for the normal mode is selected. FIG. [Figure 93] FIG. 13 is a diagram showing an example of a lottery table for a first RT mode. [Figure 94] FIG. 13 is an explanatory diagram for explaining the relationship between the stopping order of the reels and the winning patterns that are achieved when the lottery table for the first RT mode is selected. [Figure 95] FIG. 13 is a diagram showing an example of a lottery table for the second RT mode. [Figure 96] FIG. 13 is an explanatory diagram for explaining the relationship between the stopping order of the reels and the winning modes that are achieved when the lottery table for the second RT mode is selected. [Figure 97] 13 is a flowchart showing the response process executed by the main MPU when a game ends. [Figure 98] 13 is a flowchart showing a transition chance management process executed by a main MPU. [Figure 99]13 is a flowchart showing the ART state processing executed by the main MPU. [Figure 100] 13 is a flowchart showing a game management process executed by a master MPU. [Figure 101] 1A and 1B are explanatory diagrams for explaining the display contents of an image display device. [Figure 102] 13 is a flowchart showing a management process executed by a main MPU. [Figure 103] 11 is a flowchart showing a lighting process executed by a main MPU. [Figure 104] 6A and 6B are time charts showing the relationship between the opening angle of the front door and the control state of the lighting device. [Figure 105] FIG. 1A is an explanatory diagram for explaining the state of the lighting device when the front door is open and the opening angle is equal to or less than a predetermined opening angle, and FIG. 1B is an explanatory diagram for explaining the state of the lighting device when the opening angle of the front door is at the maximum opening angle. [Fig. 106] (a) An explanatory diagram for explaining the contents of various areas provided in the main RAM in the 18th embodiment; (b) An explanatory diagram for explaining the contents of various counters provided in the total accumulation buffer; (c) An explanatory diagram for explaining the contents of various counters provided in the first accumulation buffer; and (d) An explanatory diagram for explaining the contents of various counters provided in the second accumulation buffer. [Figure 107] 13(a) to (h) are time charts showing how game history is managed. [Figure 108] 13 is a flowchart showing a game management process executed by a master MPU. [Fig. 109] 13 is a flowchart showing a target switching process executed by a main MPU. [Figure 110] 13 is a flowchart showing a management process executed by a main MPU. [Figure 111] FIG. 23 is a block diagram for explaining the electrical configuration of a management IC according to the nineteenth embodiment. [Figure 112]FIG. 2 is an explanatory diagram for explaining the configuration of a first history memory and a second history memory. [Figure 113] 13 is a flowchart showing a history setting process executed by a management CPU. [Fig. 114] 13 is a flowchart showing a target switching process executed by a management CPU. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <First embodiment> A first embodiment of a pachinko gaming machine (hereinafter referred to as a "pachinko machine"), which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a perspective view of a pachinko machine 10, and Fig. 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded form. For convenience, Fig. 2 omits the components within the play area PA of the pachinko machine 10.

[0011] As shown in Fig. 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so as to be rotatable forward. The outer frame 11 is made of wooden boards connected at all four sides, forming a rectangular frame. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to an island facility. Note that the outer frame 11 is not a required component of the pachinko machine 10, and the outer frame 11 may be installed in the island facility of the amusement hall.

[0012] 2, the gaming machine body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 is rotatable forward with the left side as the base end and the right side as the tip end when viewed from the front.

[0013] A front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side as the base end and the right side as the tip end when viewed from the front. A back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated backward with the left side as the base end and the right side as the tip end when viewed from the front.

[0014] The gaming machine body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states is released by performing an unlocking operation using an unlocking key on a cylinder lock 17 that is exposed on the front of the pachinko machine 10.

[0015] Next, the configuration of the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 having an outer shape substantially identical to that of the outer frame 11. A substantially elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front side of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

[0017] Here, the configuration of the game board 24 will be described with reference to Fig. 3. Fig. 3 is a front view of the game board 24.

[0018] An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and the inner rail section 25 and the outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0019] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeder 27b that supplies game balls stored in the upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c that is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by rotating a launching operation device (or an operation handle) 28 provided on the front door frame 14. The game balls are launched.

[0020] A number of large and small openings are formed in the game board 24, penetrating in the front-rear direction. Each opening is provided with a general winning port 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special chart unit 37, and a general chart unit 38. There are a total of four general winning ports 31, and one of each of the others.

[0021] Even if a ball enters the through gate 35, the payout of game balls is not executed. On the other hand, when balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls are paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball is paid out, when one game ball enters the general winning opening 31, ten prize balls are paid out, and when one game ball enters the special electric winning device 32, fifteen prize balls are paid out.

[0022] The number of prize balls is arbitrary, and for example, the second actuating port 34 may be configured to have a smaller number of prize balls than the first actuating port 33, or the second actuating port 34 may be configured to have a larger number of prize balls than the first actuating port 33.

[0023] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes are discharged from the game area PA through the outlet 24a. In addition, the game board 24 is provided with a large number of nails 24b for appropriately dispersing and adjusting the falling direction of the game balls, and various components such as windmills are also provided.

[0024] Here, the term "entering the ball" means that the game ball passes through a specified opening, and includes not only the state in which the game ball passes through the opening and is discharged from the game area PA, but also the state in which the game ball continues to flow down the game area PA without being discharged from the game area PA after passing through the opening. However, in the following explanation, in order to clearly distinguish from the game ball entering the outlet 24a, the game ball entering the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 will also be expressed as winning.

[0025] The first actuation port 33 and the second actuation port 34 are unitized as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 are open upward. In addition, both actuation ports 33, 34 are aligned vertically with the first actuation port 33 facing upward. The second actuation port 34 is provided with a normal power device 34a as a guide piece consisting of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

[0026] A through gate 35 is provided upstream of the second operating port 34 in the flow direction of the game ball. The through gate 35 has a through hole (not shown) that penetrates vertically, and the game ball that enters the through gate 35 flows down the game area PA after entering. This makes it possible for the game ball that enters the through gate 35 to enter the second operating port 34.

[0027] Based on winning the through gate 35, the normal power role 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the winning of the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38 provided in the lower right corner of the play area PA, which is an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role opening and the stop result corresponding to the result is displayed and the variable display of the normal map display section 38a is terminated, the state transitions to the normal power opening state. In the normal power opening state, the normal power role 34a is opened in a predetermined manner.

[0028] The map display unit 38a is composed of a segment display in which a plurality of segment light-emitting parts are arranged in a predetermined manner, but is not limited thereto, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. As for the pattern displayed variably on the map display unit 38a, a configuration in which a plurality of characters are displayed variably, a configuration in which a plurality of symbols are displayed variably, a configuration in which a plurality of characters are displayed variably, or a configuration in which a plurality of colors are displayed in a switched manner may be considered.

[0029] In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. The number of game balls that enter the through gate 35 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

[0030] A winning lottery is held by triggering a winning entry into the first operating port 33 or the second operating port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Regarding the special chart unit 37 in detail, the special chart unit 37 is provided with a special chart display section 37a. The display area of ​​the special chart display section 37a is narrower than the display surface 41a of the pattern display device 41. In the special chart display section 37a, a winning lottery is held by triggering the winning of the first operating port 33 or the winning of the second operating port 34, and a variable display or a predetermined display of the pattern is performed. Then, a result corresponding to the lottery result is displayed. The special chart display section 37a is composed of a segment display device in which a plurality of segment light-emitting sections are arranged in a predetermined manner, but is not limited to this, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. In addition, as the pattern displayed on the special chart display section 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed may be considered.

[0032] In the special chart unit 37, a special chart reserve display section 37b is provided at a position adjacent to the special chart display section 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special chart reserve display section 37b.

[0033] In detail, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display contents are controlled by a display control device described later. The pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

[0034] In the pattern display device 41, when the special pattern display unit 37a displays a variable or predetermined pattern based on the winning of the first operation port 33 or the winning of the second operation port 34, the pattern display device 41 displays a variable or predetermined pattern accordingly. For example, the display surface 41a of the pattern display device 41 has three pattern rows, an upper row, a middle row, and a lower row, set as a plurality of display areas, and the main patterns numbered "1" to "9" are scrolled in ascending or descending order in each pattern row. In this scroll display, the scroll display of all pattern rows is started first, and the scroll display is switched to standby display in the order of the upper pattern row → the lower pattern row → the middle pattern row, and finally the scroll display is ended in a state where a predetermined pattern is statically displayed in each pattern row. Then, for example, in a game round in which the game result is a jackpot result, a predetermined combination of patterns is stopped and displayed on a valid line set in advance on the display surface 41a of the pattern display device 41.

[0035] In addition, the pattern display device 41 performs not only a display performance triggered by winning the first operation port 33 or the second operation port 34, but also a display performance during the opening and closing execution mode to which the mode is shifted after a winning is obtained. In addition, based on the winning of either operation port 33, 34, the display is started on the special pattern display unit 37a and the pattern display device 41, and one game round is performed until a predetermined result is displayed and the game ends. In addition, the manner of the variable display of the pattern in the pattern display device 41 is not limited to the above and is arbitrary, and the number of pattern rows, the direction of the variable display of the pattern in the pattern row, the number of patterns in each pattern row, etc. can be changed as appropriate. In addition, the pattern displayed by the pattern display device 41 is not limited to the above patterns, and for example, a configuration in which only numbers are displayed as patterns may be configured to be displayed.

[0036] When a big win is won in a lottery based on winning the first operation port 33 or the second operation port 34, the mode shifts to an open / close execution mode in which winning is possible in the special electric winning device 32. The special electric winning device 32 is provided with a large winning port (not shown) that leads to the back side of the game board 24, and is provided with an open / close door 32a that opens and closes the large winning port. The open / close door 32a is arranged in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which the game ball cannot win, and is switched to an open state in which the game ball can win when the internal lottery is selected to switch to the open / close execution mode. Incidentally, the open / close execution mode is a mode to which the mode shifts when a winning result is obtained. It should be noted that the closed state does not mean that winning is impossible, but it may be configured to be in a state in which winning is more difficult than in the open state.

[0037] FIG. 4 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

[0038] As already explained, a game ball that enters any of the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the game area PA. In other words, a game ball that is launched from the game ball launching mechanism 27 and flows into the game area PA is discharged from the game area PA by entering any of the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A game ball that enters any of the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the game board 24.

[0039] On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning port 31, the special winning device 32, the first operating port 33, the second operating port 34, and the outlet 24a, respectively. The game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, and are guided to the lower end of the game board 24 on the back side of the game board 24, and are collected in a discharge ball collection section (not shown). The game balls collected in the discharge ball collection section are then discharged to a ball circulation device of an island facility where a pachinko machine 10 is installed in a game hall.

[0040] Each of the discharge passages 42-48 is provided with various detection sensors 42a-48a for detecting game balls. The discharge passages 42-48 and the detection sensors 42a-48a will be described below. As already described, four general winning openings 31 are provided, and therefore, the discharge passages 42-44 exist corresponding to each of the four general winning openings 31. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage 42 corresponding to the leftmost general winning opening 31 and the second discharge passage 43 corresponding to the general winning opening 31 adjacent thereto to the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located in the middle of the first discharge passage 42, and the second winning opening detection sensor 43a is provided so that its detection range is located in the middle of the second discharge passage 43. A game ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage section 42, and a game ball that enters the general winning opening 31 adjacent to the left is detected by the second winning opening detection sensor 43a while passing through the second discharge passage section 43. A third discharge passage section 44 is provided for the two general winning openings 31 on the right side, which are formed so as to merge at an intermediate position. The third discharge passage section 44 has an entrance side area corresponding to each of the two general winning openings 31, and the entrance side areas merge at an intermediate position to form one exit side area. A third winning opening detection sensor 44a is provided so that a detection range exists at an intermediate position of the exit side area in the third discharge passage section 44. A game ball that enters one of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage section 44.

[0041] A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists in the middle of the fourth discharge passage section 45, and the game ball that entered the special electric winning device 32 is detected by the special electric detection sensor 45a in the middle of passing through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists in the middle of the fifth discharge passage section 46, and the game ball that entered the first operating port 33 is detected by the first operating port detection sensor 46a in the middle of passing through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second actuation port detection sensor 47a is provided so that a detection range exists in a midway position of the sixth discharge passage section 47, and a game ball that enters the second actuation port 34 is detected by the second actuation port detection sensor 47a in the middle of passing through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that a detection range exists in a midway position of the seventh discharge passage section 48, and a game ball that enters the outlet 24a is detected by the outlet detection sensor 48a in the middle of passing through the seventh discharge passage section 48.

[0042] In addition, a gaming ball that is detected by any one of the various detection sensors 42a to 48a is not detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on the way down the game area PA is detected by the gate detection sensor 49a.

[0043] Although electromagnetic induction type proximity sensors are used as the various detection sensors 42a-49a, any sensor can be used as long as it can detect the game balls individually. The various detection sensors 42a-49a are electrically connected to a main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a game ball, and output a HI level signal when they are detecting a game ball. However, this is not limited to this, and the relationship between HI and LOW may be reversed.

[0044] As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the game board 24 of the above configuration to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of ​​the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into the window portion 51. The window panel 52 is formed of glass so as to be colorless and transparent, but is not limited thereto and may be formed of synthetic resin so as to be colorless and transparent, or may be formed of colored transparency as long as the game area PA can be viewed through the window panel 52 from the front of the pachinko machine 10.

[0045] Above the window 51, a display light-emitting unit 53 is provided. A pair of left and right speaker units 54 are provided to output sound effects according to the game state. Below the window 51, an upper bulge 55 and a lower bulge 56 are arranged vertically side by side, bulging toward the front. An upper tray 55a opening upward is provided inside the upper bulge 55, and a lower tray 56a opening upward is provided inside the lower bulge 56. The upper tray 55a has a function of temporarily storing game balls dispensed from a dispensing device described later, and guiding the game balls to the game ball launching mechanism 27 while aligning them in a row. The lower tray 56a has a function of storing game balls that are surplus in the upper tray 55a.

[0046] Next, the configuration of the rear side of the gaming machine main body 12 will be described.

[0047] As shown in FIG. 2, the main control device 60 that mainly controls the game is mounted on the back of the inner frame 13 (specifically, the game board 24). The main control device 60 is configured by housing a main control board 61 in a board box 60a. The board box 60a may be provided with a trace means for leaving a trace of its opening or a trace structure for leaving a trace of its opening. As the trace means, a structure of a joint part that inseparably joins the multiple case bodies constituting the board box 60a and requires destruction of a predetermined part when separating them, or a structure of attaching a seal that leaves a trace of its removal by leaving an adhesive layer on the object to be attached when peeled off, so as to straddle the boundaries between the multiple case bodies. As the trace structure, a structure of applying an adhesive to the boundaries between the multiple case bodies constituting the board box 60a may be considered.

[0048] The back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 has a back pack 72 formed from a transparent synthetic resin, to which a dispensing mechanism section 73 and a control device assembly unit 74 are attached.

[0049] The payout mechanism 73 includes a tank 75 to which game balls are successively replenished from the island equipment of the gaming hall, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power supply on and off.

[0050] The control device assembly unit 74 includes a payout control device 77 having a function of controlling the payout device 76, and a power supply / launch control device 78 which generates and outputs a predetermined amount of power required by various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply / launch control device 78 are stacked in front of and behind each other, with the payout control device 77 at the rear of the pachinko machine 10.

[0051] <Electrical configuration of the pachinko machine 10> FIG. 5 is a block diagram showing the electrical configuration of the pachinko machine 10. As shown in FIG.

[0052] The main control device 60 comprises a main control board 61 which is responsible for the main control of the game, and a power failure monitoring board 67 which monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 has a main CPU 63, which is a processing device including a control unit and a calculation unit, as well as a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also has an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as random number generators, and the like built in.

[0053] The main ROM 64 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0054] The main RAM 65 is a memory (i.e., a volatile storage means) that requires an external power supply to retain memory such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 is randomly accessible, and when compared with the main ROM 64 for the same data capacity, it takes less time to read data. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0055] The management IC 66 is a management device that manages the ball entry patterns of game balls in the game area PA based on information supplied from the main CPU 63. Although details will be described later, the management IC 66 grasps the ball entry history of game balls into the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, and grasps the ball entry frequency into the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 according to the grasped ball entry history.

[0056] The MPU 62 is provided with an input port and an output port. The input side of the MPU 62 is connected to a power failure monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power failure monitoring board 67 is connected to a power supply / launch control device 78 having a function of supplying operating power, and the MPU 62 is supplied with operating power via the power failure monitoring board 67.

[0057] Various sensors such as the ball entry detection sensors 42a-49a are connected to the input side of the MPU 62. As already explained, the ball entry detection sensors 42a-49a are the first winning hole detection sensor 42a, the second winning hole detection sensor 43a, the third winning hole detection sensor 44a, the special electric detection sensor 45a, the first operation hole detection sensor 46a, the second operation hole detection sensor 47a, the out hole detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a-49a, the main CPU 63 judges whether a ball has entered each entry section. In addition, the main CPU 63 executes various lotteries based on the winning of the first operation hole 33, and executes various lotteries based on the winning of the second operation hole 34.

[0058] The output side of the MPU 62 is connected to the power failure monitoring board 67, the payout control device 77, and the sound and light emission control device 81. For example, a prize ball command is output to the payout control device 77 based on the fact that a game ball has entered a prize ball entry section among the above-mentioned ball entry sections, in which the occurrence of the ball entry corresponds to the payout of the game ball. Various commands such as a variation command, a type command, and an opening command are output to the sound and light emission control device 81.

[0059] The output side of the MPU 62 is connected to the special power drive unit 32b that opens and closes the opening and closing door 32a of the special power winning device 32, the normal power drive unit 34b that opens and closes the normal power role 34a of the second operating port 34, the special chart unit 37, and the normal chart unit 38. Incidentally, the special chart unit 37 is provided with a special chart display unit 37a and a special chart reserved display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal chart unit 38 is provided with a normal chart display unit 38a and a normal chart reserved display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 executes drive control of various drive units and various display units through the driver circuits.

[0060] That is, in the open / close execution mode, the main CPU 63 executes drive control of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the normal power role 34a is won, the main CPU 63 executes drive control of the normal power drive unit 34b so that the normal power role 34a is opened and closed. Also, during each game, the main CPU 63 executes display control of the special chart display unit 37a. Also, when the lottery result of whether or not the normal power role 34a is opened is to be clearly indicated, the main CPU 63 executes display control of the normal chart display unit 38a. In addition, when a winning entry occurs at the first operating port 33 or the second operating port 34, or when a changing display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart pending display unit 37b, and when a winning entry occurs at the through gate 35, or when a changing display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart pending display unit 38b.

[0061] The power failure monitoring board 67 relays between the main control board 61 and the power supply / launch control device 78, and monitors the voltage of 24 V DC stable, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0062] The power supply / launch control device 78 is connected to a commercial power supply (external power supply) in, for example, a game hall. Based on the external power supplied from the commercial power supply, the power supply / launch control device 78 generates the operating power required for each of the main control board 61, the payout control device 77, etc., and supplies the generated operating power. Incidentally, the power supply / launch control device 78 is provided with a power supply unit for use during power interruption, such as a backup capacitor, and even when the power supply of the pachinko machine 10 is in an OFF state, power for memory retention is supplied from the power supply unit for use during power interruption to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply / launch control device 78 is also responsible for controlling the launch of the game ball launching mechanism 27, and the game ball launching mechanism 27 is driven when a predetermined launch condition is met.

[0063] The audio and light-emitting control device 81 drives and controls the display light-emitting unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 executes display control of the pattern display device 41 based on commands received from the audio and light-emitting control device 81.

[0064] <Electrical configuration for performing various lotteries in the main CPU 63> Next, the electrical configuration for performing various lotteries in the main CPU 63 will be described with reference to FIG.

[0065] The master CPU 63 uses various counter information during play to perform a lottery for a big win, setting the display of the special symbol display section 37a, setting the symbol display of the symbol display device 41, setting the display of the normal symbol display section 38a, and the like. Specifically, as shown in FIG. 6, the master CPU 63 uses a winning random number counter C1 used for a lottery for a winning occurrence, a big win type counter C2 used for determining a big win type, a reach random number counter C3 used for a reach occurrence lottery when the symbol display device 41 misses and varies, a random number initial value counter CINI used for setting the initial value of the winning random number counter C1, and a variation type counter CS for determining the display duration time in the special symbol display section 37a and the symbol display device 41. Furthermore, the master CPU 63 uses a normal power role release counter C4 used for a lottery for whether or not the normal power role 34a of the second operating port 34 is in a normal power open state. The above counters C1 to C3, CINI, CS, and C4 are provided in the various counter areas 65b of the master RAM 65.

[0066] Each counter C1-C3, CINI, CS, C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching the maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

[0067] The reserved storage area 65a includes a reserved area RE and an execution area AE. The reserved area RE includes a first reserved area RE1, a second reserved area RE2, a third reserved area RE3, and a fourth reserved area RE4, and a combination of numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored as reserved information in one of the reserved areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

[0068] In this case, when winning occurs multiple times consecutively in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first hold area RE1 to the fourth hold area RE4 in the order of the first hold area RE1 → the second hold area RE2 → the third hold area RE3 → the fourth hold area RE4 in chronological order. By providing the four hold areas RE1 to RE4 in this way, up to four winning histories of game balls in the first actuation port 33 or the second actuation port 34 can be reserved and stored.

[0069] In addition, the number of items that can be stored on hold is not limited to four and is arbitrary, and may be other multiples such as two, three, or five or more, or may be singular.

[0070] The execution area AE is an area for moving each piece of numerical information stored in the first holding area RE1 of the holding area RE when the changing display of the special chart display section 37a begins, and when one game round begins, a win / loss determination, etc. is made based on the various numerical information stored in the execution area AE.

[0071] Each of the above counters will now be described in detail.

[0072] First, the normal power accessory opening counter C4 will be described. The normal power accessory opening counter C4 is configured to be incremented by 1 in the range of 0 to 250, for example, and to return to "0" after reaching the maximum value. The normal power accessory opening counter C4 is periodically updated and stored in the normal power reserve area 65c of the main RAM 65 at the timing when the game ball enters the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether or not to control the normal power accessory 34a to an open state based on the value of the stored normal power accessory opening counter C4.

[0073] In the present pachinko machine 10, a plurality of types of support modes are set so that the manner of support by the normal power accessory 34a is different from each other. In detail, the support modes are set to a high frequency support mode and a low frequency support mode so that the frequency with which the normal power accessory 34a of the second operating port 34 is in an open state per unit time is relatively high and low when compared with a situation in which the launch of game balls continues in the same manner in the game area PA.

[0074] In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power role opening counter C4 is the same (for example, both are 4 / 5), but in the high-frequency support mode, the number of times that the normal power role 34a is in the open state when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for one time is set to be longer. In this case, when the normal power opening state is won in the high-frequency support mode and the open state of the normal power role 34a occurs multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for one time. Furthermore, in the high-frequency support mode, the minimum time to be secured between one normal power opening lottery and the next normal power opening lottery (i.e., the display duration of one time in the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0075] As described above, in the high frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, the probability of a winning entry into the first actuation port 33 is higher than in the second actuation port 34, but in the high frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the first actuation port 33. When a winning entry into the second actuation port 34 occurs, a predetermined number of game balls are paid out, so that in the high frequency support mode, the player can play without losing too many balls.

[0076] The configuration for increasing the frequency of the high-frequency support mode becoming in the normal power release state per unit time compared to the low-frequency support mode is not limited to the above, and may be, for example, a configuration for increasing the probability of winning the normal power release state in the normal power release lottery. In addition, in a configuration in which a plurality of types of secured time (for example, the time of variable display executed in the normal power display unit 38a based on winning the through gate 35) are provided for securing from one normal power release lottery to the next normal power release lottery, the high-frequency support mode may be set so that a shorter secured time is more likely to be selected or the average secured time is shorter than in the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of conditions from increasing the number of openings, lengthening the opening time, shortening the secured time secured from one normal power release lottery to the next normal power release lottery, shortening the average secured time, and increasing the winning probability.

[0077] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by one within the range of, for example, 0 to 599, and to return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 goes around once, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically, and is stored in the reserved storage area 65a of the main RAM 65 at the timing when the game ball enters the first actuation port 33 or the second actuation port 34.

[0078] The random number value that will result in a jackpot win is stored as a win / lose table in the main ROM 64. As the win / lose table, a win / lose table for a low probability mode and a win / lose table for a high probability mode are set. In other words, in this pachinko machine 10, a low probability mode and a high probability mode are set as the lottery modes in the win / lose lottery means.

[0079] In a game state where the winning / losing table for the low probability mode is referenced in the above lottery, the number of random numbers that will result in a jackpot winning is 2. On the other hand, in a game state where the winning / losing table for the high probability mode is referenced in the above lottery, the number of random numbers that will result in a jackpot winning is 20. Note that the number of random numbers that will result in a winning is arbitrary as long as the winning probability is higher in the high probability mode than in the low probability mode.

[0080] The big win type counter C2 is configured to be incremented by one within the range of 0 to 29, and to return to "0" after reaching the maximum value. The big win type counter C2 is periodically updated, and is stored in the reserved storage area 65a when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0081] A plurality of jackpot results are set in this pachinko machine 10. These plurality of jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special electric prize winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning / losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the regular electric role 34a of the second operating port 34 after the opening and closing execution mode ends.

[0082] As the manner of opening and closing control of the special line winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special line winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds are played up to the upper limit.

[0083] Here, the round game is a game that continues until one of the following conditions is met: the predetermined upper limit duration time has elapsed, or the predetermined upper limit number of game balls have entered the special electric winning device 32. In addition, the number of round games in the open / close execution mode triggered by a jackpot result is the same as the fixed number of rounds, regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the jackpot result, the upper limit number of round games is set to 15 rounds.

[0084] In addition, in the present pachinko machine 10, a plurality of types are set for the opening mode of the special electric prize winning device 32, with different opening durations from when the special electric prize winning device 32 is opened to when it is closed. In detail, a long-time mode in which the opening duration is set to a long time of 29 seconds and a short-time mode in which the opening duration is set to a short time of 0.06 seconds, which is shorter than the long-time mode, are set.

[0085] In this pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area PA every 0.6 seconds. In addition, the upper limit number of balls for the end condition of the round game is set to nine. Then, in the long-time mode among the above-mentioned opening modes, the opening duration is set to a time longer than the product of the game ball launch cycle and one round game. On the other hand, in the short-time mode, the opening duration is set to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when one opening is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of balls in one round game, and when one opening is performed in the short-time mode, it is expected that no winning will occur in the special electric winning device 32, or that even if a winning occurs, it will be about one ball.

[0086] In the high frequency winning mode, the special electric winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special electric winning device 32 is opened once in each round of play in a short time mode.

[0087] In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of times in one round of play in the high-frequency winning mode and low-frequency winning mode are arbitrary and are not limited to the above values, so long as the frequency of winning in the special electric winning device 32 between the start and end of the opening and closing execution mode is higher in the high-frequency winning mode than in the low-frequency winning mode.

[0088] The allocation destination of the game result for the jackpot type counter C2 is stored as an allocation table in the main ROM 64. And, as such allocation destination, a low probability jackpot result, a low prize high probability jackpot result, and a most advantageous jackpot result are set.

[0089] The low probability jackpot result is a jackpot result in which the open / close execution mode becomes the high frequency winning mode, and after the open / close execution mode ends, the winning / losing lottery mode becomes the low probability mode, and the support mode becomes the high frequency support mode. However, this high frequency support mode will transition to the low frequency support mode if the number of games played after the transition reaches the end reference number (specifically, 100 times).

[0090] The low-prize high-probability jackpot result is a jackpot result in which the open / close execution mode becomes the low-frequency prize mode, and after the open / close execution mode ends, the win / lose lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery becomes a jackpot state win and transitions to the jackpot state.

[0091] The most favorable jackpot result is a jackpot result in which the open / close execution mode becomes a high-frequency winning mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high probability mode and the support mode becomes a high-frequency support mode. These high probability mode and high frequency support mode continue until the lottery result in the win / lose lottery becomes a jackpot state win and transitions to the jackpot state.

[0092] In relation to the above game states, the normal game state refers to a state where the winning / losing lottery mode is not the open / close execution mode, and the win / loose lottery mode is the low probability mode, and the support mode is the low frequency support mode. Also, a configuration may be made in which a low winning high probability jackpot result is not set as a game result. Also, in the open / close execution mode in a low winning high probability jackpot result, the number of rounds of play may be less than the number of rounds of play in the case of a low probability jackpot result and the most favorable jackpot result.

[0093] In the distribution table, of the values ​​of the jackpot type counter C2, which are "0 to 29," "0 to 9" correspond to a low probability jackpot result, "10 to 14" correspond to a low probability jackpot result with a high probability of winning, and "15 to 29" correspond to the most favorable jackpot result.

[0094] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by one within the range of, for example, 0 to 238, and to return to "0" after reaching the maximum value. Here, in this pachinko machine 10, an expectation effect is set as a type of display effect in the pattern display device 41. The expectation effect refers to a display state for making a player think that the variable display state is likely to result in the award corresponding result at the stage before the stop result is derived and displayed after the variable display of the patterns in the pattern display device 41 is started in a gaming machine that is equipped with a pattern display device 41 capable of performing a variable display of patterns and in which the final stop result is a grant corresponding result in a game round that results in a predetermined jackpot result. In addition, specifically, the award corresponding result is displayed by stopping a combination of patterns with the same number on any of the pay lines.

[0095] There are two types of expectation effects: a reach display and a notice display that creates anticipation for the occurrence of a reach display or a corresponding result before the reach display occurs.

[0096] The reach display includes a display state in which a combination of reach symbols is displayed by stopping and displaying symbols for some of the multiple symbol rows displayed on the display surface 41a of the symbol display device 41, and in that state, the remaining symbol rows are displayed with varying symbols. Also, in the state in which the reach symbol combination is displayed as described above, the remaining symbol rows are displayed with varying symbols, and a reach performance is performed by displaying a predetermined character or the like as a moving image on the background screen, and a reach performance is performed by displaying a reduced or non-displayed combination of reach symbols and then displaying a predetermined character or the like as a moving image on almost the entire display surface 41a.

[0097] The advance notice display includes a mode in which characters are displayed separately from the symbols on the symbol rows in a situation in which symbols are displayed in a variable manner in all symbol rows after the display surface 41a of the symbol display device 41 starts displaying the variable manner of symbols, or in a situation in which symbols are displayed in a variable manner in some symbol rows. It also includes a mode in which the background screen is displayed in a predetermined manner different from the previous manner, and a mode in which the symbols on the symbol rows are displayed in a predetermined manner different from the previous manner. Such advance notice display can occur in both a game in which a reach display is performed and a game in which a reach display is not performed, but is set to occur with a higher probability when a reach display is performed than when a reach display is not performed.

[0098] The reach display is executed regardless of the value of the reach random number counter C3 in a game round in which the same symbol combination is finally stopped and displayed. Also, in a game round corresponding to a big win result in which the same symbol combination is not stopped and displayed, it is not executed regardless of the value of the reach random number counter C3. Also, in a game round corresponding to a miss result, it is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0099] On the other hand, the decision as to whether or not to display a notice is not made by the main control device 60 but by the audio and light emitting control device 81. In this case, the audio and light emitting control device 81 executes a lottery process for the notice display so that a game round corresponding to any jackpot result satisfies at least one of the conditions that a notice display is more likely to occur and that a notice display with a low occurrence rate is more likely to occur in a game round corresponding to a miss result. Incidentally, this lottery result is reflected when the performance for the game round is executed by the symbol display device 41.

[0100] Next, the variation type counter CS will be described. The variation type counter CS is configured to be incremented by 1 in the range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variation type counter CS is used in determining the display duration in the special chart display unit 37a and the display duration of the pattern in the pattern display device 41 in the main CPU 63. The variation type counter CS is updated once each time the normal processing described below is executed once, and is repeatedly updated within the remaining time in the normal processing. Then, the buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special chart display unit 37a and at the start of the variation of the pattern by the pattern display device 41.

[0101] <Processing configuration of the main CPU 63> Next, we will explain each process executed to progress the game by the master CPU 63. The processes of the master CPU 63 are roughly divided into main processes that are started when the power is turned on, and timer interrupt processes that are started periodically (in this embodiment, at 4 msec intervals).

[0102] <Main processing> First, the main processing will be described with reference to the flowchart of FIG.

[0103] First, the power-on wait process is executed (step S101). In the power-on wait process, for example, the main process is started and a predetermined wait time (specifically, 1 sec) elapses before proceeding to the next process. During the execution period of the power-on wait process, the operation start and initial setting of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102), and the internal function register of the main CPU 63 is set (step S103).

[0104] Then, it is determined whether or not the RAM erase switch provided on the power supply / launch control device 78 has been manually operated (step S104), and further whether or not the power failure flag of the main RAM 65 has been set to "1" (step S105). Also, a checksum calculation process is executed to calculate a checksum (step S106), and it is determined whether or not the checksum matches the checksum saved when the power was cut off, that is, the validity of the stored data is determined (step S107).

[0105] In this pachinko machine 10, when the RAM data is initialized when the power is turned on, for example, when the game hall opens for business, the power is turned on while pressing the RAM clear switch. Therefore, if the RAM clear switch is pressed, the process proceeds to step S108. Similarly, if the power cutoff occurrence information is not set, or if an abnormality is found in the stored data by the checksum, the process proceeds to step S108. In step S108, the main RAM 65 is cleared. Then, the process proceeds to step S109.

[0106] On the other hand, if the RAM erase switch is not pressed, the process proceeds to step S109 without executing the process of step S108, provided that the power failure flag is set to "1" and the checksum is normal. In step S109, a power-on setting process is executed. In the power-on setting process, a predetermined area of ​​the main RAM 65, such as the initialization of the power failure flag, is set to an initial value, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After the process of step S109 is executed, a recognition process (step S110) is executed to make the management IC 66 recognize various information, and a data output process is executed to output various data to a reading device connected to the MPU 62 (step S111). Details of the recognition process and the data output process will be described later.

[0107] The main CPU 63 is configured to periodically execute timer interrupt processing, but when the main processing is started, the occurrence of timer interrupt processing is prohibited. This state in which the occurrence of timer interrupt processing is prohibited is released at a timing when the processing of step S111 is completed and before the processing of step S112 is executed, and the execution of timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 is started, the data output processing of step S111 is completed, and the timer interrupt processing is not executed until the stage before the processing of step S112 is started. Therefore, the processing for progressing the game in the main CPU 63 is not started until the situation is reached.

[0108] Thereafter, the process proceeds to the remaining process of steps S112 to S115. That is, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is utilized to repeatedly execute the remaining process of steps S112 to S115. In this respect, the remaining process of steps S112 to S115 can be said to be non-periodic processing that is executed non-periodically.

[0109] In the remaining process, first, in step S112, interrupt inhibition is set to inhibit occurrence of timer interrupt processing. In the following step S113, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S114, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, the current numerical value information is read from the corresponding counter in the main RAM 65, and the read numerical value information is added by 1, and then the counter from which it was read is overwritten. In this case, when the counter value reaches the maximum value, each is cleared to "0". After that, in step S115, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is inhibited to a state in which it is permitted. After executing the processing of step S115, the process returns to step S112, and the processing of steps S112 to S115 is repeated.

[0110] <Timer interrupt processing> Next, the timer interrupt process will be described with reference to the flowchart of Fig. 8. The timer interrupt process is executed periodically (for example, every 4 msec).

[0111] First, the power failure information storage process is executed (step S201). In the power failure information storage process, it is monitored whether a power failure signal corresponding to the occurrence of a power cut is received from the power failure monitoring board 67, and if the occurrence of a power failure is identified, the power failure process is executed and then an infinite loop is entered. In the power failure process, the power failure flag in the main RAM 65 is set to "1", and the checksum is calculated and the calculated checksum is saved.

[0112] After that, a lottery random number update process is executed (step S202). In the lottery random number update process, the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power role release counter C4 are updated. Specifically, the current numerical information is read out sequentially from the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power role release counter C4, and after executing a process of adding 1 to each of the read numerical information, a process of overwriting the counter from which it was read out is executed. In this case, when the counter value reaches the maximum value, each is cleared to "0". After that, in step S203, a random number initial value update process is executed as in step S113, and in step S204, a variable counter update process is executed as in step S114.

[0113] Thereafter, a fraud detection process is executed to monitor whether or not a predetermined event set as a monitoring target for fraud has occurred (step S205). In the fraud detection process, the occurrence of a plurality of types of events is monitored, and when a predetermined event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S206, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S206, the process from step S207 onwards is executed.

[0114] In step S207, a port output process is executed. In the port output process, when output information has been set in the previous timer interrupt process, a process is executed to output corresponding to the output information to the various drive units 32b, 34b. For example, when information is set to switch the special power winning device 32 to an open state, the output of a drive signal to the drive unit 32b for special power is started, and when information is set to switch to a closed state, the output of the drive signal is stopped. Also, when information is set to switch the normal power role 34a of the second operating port 34 to an open state, the output of a drive signal to the drive unit 34b for normal power is started, and when information is set to switch to a closed state, the output of the drive signal is stopped.

[0115] Then, a read process is executed (step S208). In the read process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in the subsequent processes.

[0116] After that, a ball entry detection process is executed (step S209). In the ball entry detection process, signals received from the ball entry detection sensors 42a to 49a are read, and based on the read results, the presence or absence of balls entering the out gate 24a, the general winning gate 31, the special electric winning device 32, the first operating gate 33, the second operating gate 34, and the through gate 35 is identified. Details of the ball entry detection process will be described later.

[0117] Thereafter, a timer update process is executed to collectively update the numerical information of multiple types of timer counters provided in the main RAM 65 (step S210). In this case, the timer counters in which the stored numerical information is updated by subtraction are handled collectively, but it is also possible to collectively update both the subtractive timer counters and the additive timer counters.

[0118] Then, a launch control process is executed to control the launch of the game balls (step S211). In a state where the launch operation to the launch operation device 28 is continued, one game ball is launched at a predetermined launch cycle of 0.6 seconds. In the following step S212, as an input state monitoring process, based on the information read in the reading process of step S208, a disconnection check is performed for each ball entry detection sensor 42a to 49a, and an opening check is performed for the game machine main body 12 and the front door frame 14.

[0119] Thereafter, a special chart special electric control process is executed to control the execution of a game round and the opening / closing execution mode (step S213). In the special chart special electric control process, when a winning occurs in the first operation port 33 or the second operation port 34 in a situation where the number of reserved information stored in the reserved storage area 65a is less than the upper limit number, the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 at that time is stored as reserved information in the reserved storage area 65a in chronological order. In addition, in the special chart special electric control process, under the condition that the game round and the opening / closing execution mode are not in progress and reserved information is stored, a win / loss determination process is executed to determine whether the reserved information corresponds to a big win or not, and if it corresponds to a big win, an allocation determination process is executed to determine which big win result the reserved information corresponds to. In addition, in the special chart special power control process, not only the hit / miss judgment process and the allocation judgment process, but also, when the reserved information does not correspond to a big win, a reach judgment process is executed to judge whether the reserved information corresponds to a reach occurrence or not, and a process to select the duration of the game round using the numerical information of the variation type counter CS at that time is executed. Then, a variation command including information on the duration according to the results of each process and a type command including information on the game result are transmitted to the voice light emission control device 81, and the variation display of the pattern on the special chart display unit 37a is started. By receiving the variation command and the type command, the voice light emission control device 81 starts the performance for the game round corresponding to the contents of these commands on the display light emission unit 53 and the speaker unit 54. In addition, the voice light emission control device 81 transmits a variation pattern command corresponding to the contents of the variation command and the type command to the display control device 82. By receiving the variation pattern command, the display control device 82 starts the variation display of the pattern corresponding to the contents of the variation pattern command on the pattern display device 41. This results in a state in which one game round has started.

[0120] In the special symbol special electricity control process, during the execution of one game round, by determining whether the duration of the game round determined at the start of the game round has elapsed, it is determined whether it is time to end the game round. If it is time to end the game round, a process is executed to end the game round with a display corresponding to the game result. In this case, if the current game round corresponds to the occurrence of any jackpot result, a picture corresponding to the type of the jackpot result is stopped and displayed on the special symbol display unit 37a, and if the current game round corresponds to a loss result, a picture corresponding to the loss result is stopped and displayed on the special symbol display unit 37a. In addition, a final stop command indicating that the game round should be ended is transmitted to the sound and light emission control device 81. By receiving the final stop command, the sound and light emission control device 81 ends the performance for the current game round in the display light emission unit 53 and the speaker unit 54. In addition, the sound and light emission control device 81 transmits the final stop command to the display control device 82. By receiving the final stop command, the display control device 82 ends the performance for the current game round in the pattern display device 41.

[0121] In the special chart special electric control process, if the result of the game round corresponds to the transition to the open / close execution mode, a process for starting the open / close execution mode is executed. At the start, an opening command indicating that the open / close execution mode is to be started is sent to the sound light emission control device 81. In addition, in the special chart special electric control process, a process for starting each round game and a process for ending each round game are executed. When a round game is started, the special electric winning device 32 is in an open state, and when a round game is ended, the special electric winning device 32 is in a closed state. In each of these processes, an opening command indicating that a round game is to be started is sent to the sound light emission control device 81, and a closing command indicating that the round game is to be ended is sent to the sound light emission control device 81. In addition, in the special chart special electric control process, when the open / close execution mode is to be ended, an ending command indicating that is to be ended is sent to the sound light emission control device 81. The sound light emission control device 81 executes the performance for the open / close execution mode in the display light emission unit 53 and the speaker unit 54 in a manner corresponding to various commands received during the open / close execution mode. Also, the sound and light emission control device 81 transmits a command corresponding to the command received during the opening and closing execution mode to the display control device 82. The display control device 82 causes the pattern display device 41 to execute the performance for the opening and closing execution mode in a manner corresponding to the various commands received during the opening and closing execution mode. Also, in the special pattern special electricity control process, when the opening and closing execution mode is to be ended, a process is executed so that the winning / losing lottery mode and the support mode after the end of the opening and closing execution mode become modes corresponding to the type of the big win result that triggered the execution of the opening and closing execution mode.

[0122] After executing the special power control process of step S213 in the timer interrupt process, execute the normal power control process (step S214). In the normal power control process, if a winning entry to the through gate 35 occurs, execute a process to acquire the reserved information of the normal side, and if the reserved information of the normal side is stored, execute an opening judgment for the reserved information, and execute a process to perform a performance for the normal side using the opening judgment as a trigger. Also, execute a process to open and close the normal power role 34a of the second operating port 34 based on the result of the opening judgment. In this case, if the support mode is the low frequency support mode, execute a corresponding process, and if the support mode is the high frequency support mode, execute a corresponding process. Also, if the opening and closing execution mode is selected, the support mode will be the low frequency support mode even if the support mode immediately before is the high frequency support mode.

[0123] In the next step S215, based on the processing results of the previous steps S213 and S214, output information is set to reflect the increase / decrease in the reserved information related to the special drawing display unit 37a in the special drawing reserved display unit 37b, and output information is set to reflect the increase / decrease in the reserved information related to the ordinary drawing display unit 38a in the ordinary drawing reserved display unit 38b. Also, in step S215, based on the processing results of the previous steps S213 and S214, output information is set to update the display contents of the special drawing display unit 37a, and output information is set to update the display contents of the ordinary drawing display unit 38a.

[0124] Then, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation result (step S216). Also, a payout output process is executed to set the prize ball command as an output target (step S217). Also, an external information setting process is executed to control the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process (step S218). Then, a management output process is executed to output information corresponding to the ball entry result in the game area PA to the management IC 66 (step S219). The details of the management output process will be described later.

[0125] Next, a configuration will be described for the main CPU 63 to determine whether or not game balls have entered the out hole 24a, the general winning hole 31, the special winning device 32, the first operating hole 33, the second operating hole 34, and the through gate 35 based on the detection results of the ball entry detection sensors 42a to 49a. Fig. 9 is an explanatory diagram for explaining a configuration for inputting the detection results of the ball entry detection sensors 42a to 49a to the main CPU 63.

[0126] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so as to be able to handle eight types of signals simultaneously. An area in which information "0" or "1" is stored according to the voltage of each signal is provided in one-to-one correspondence with each terminal. That is, the area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals are input to the input port 63a, in order to limit the number of signals that are input simultaneously to eight types, the group of signals to be input to the input port 63a is switched through switching control by a driver IC.

[0127] In the ball entry detection process (step S209) of the timer interrupt process (FIG. 8), the signal group to be input to the input port 63a is set to the signal group from each ball entry detection sensor 42a-49a. In a situation where such a setting is made, the 0th bit D0 stores information corresponding to the detection signal from the first winning opening detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the second winning opening detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the third winning opening detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special electric detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the first operation opening detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the second operation opening detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the out opening detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0128] When the ball entrance detection sensors 42a to 49a do not detect the passage of a game ball, they output a LOW level signal indicating that the ball is not being detected as a detection signal, and when the ball entrance detection sensors 42a to 49a detect the passage of a game ball, they output a HI level signal indicating that the ball is being detected as a detection signal. When the ball entrance detection sensors 42a to 49a receive a LOW level signal, they store "0" information in the corresponding bit, and when the ball entrance detection sensors 42a to 49a receive a HI level signal, they store "1" information in the corresponding bit. In other words, when the ball entrance detection sensors 42a to 49a do not detect the passage of a game ball, they store "0" information in the corresponding bit, which corresponds to the information indicating that the ball is not being detected, and when the ball entrance detection sensors 42a to 49a detect the passage of a game ball, they store "1" information in the corresponding bit, which corresponds to the information indicating that the ball is being detected.

[0129] FIG. 10 is a flowchart showing the ball scoring detection process executed in step S209 of the timer interrupt process (FIG. 8).

[0130] When it is confirmed that the 0th bit D0 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first winning hole detection sensor 42a (step S301: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S302), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S303). The first output flag is a flag for the main CPU 63 to specify that information output indicating that one game ball has been detected by the first winning hole detection sensor 42a should be executed to the management IC 66. The 10-ball counter is a counter for the main CPU 63 to specify the number of times that the 10 game balls should be paid out. If the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (FIG. 8), and the value of the 10 prize ball counter is decremented by 1 when the 10 prize ball command is output once. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0131] When it is confirmed that the first bit D1 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second winning hole detection sensor 43a (step S304: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S305), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S306). The second output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the second winning hole detection sensor 43a should be executed to the management IC 66.

[0132] When it is confirmed that the second bit D2 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the third winning hole detection sensor 44a (step S307: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S308), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S309). The third output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the third winning hole detection sensor 44a should be executed to the management IC 66.

[0133] When it is confirmed that the third bit D3 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the special electric detection sensor 45a (step S310: YES). In this case, the special electric winning flag provided in the main RAM 65 is set to "1" (step S311), the fourth output flag provided in the main RAM 65 is set to "1" (step S312), and the value of the 15-ball counter provided in the main RAM 65 is incremented by 1 (step S313). The special electric winning flag is a flag for the main CPU 63 to specify that one game ball has entered the special electric winning device 32 in a round game in the open / close execution mode. In the special chart special electric control process (step S213) of the timer interrupt process (FIG. 8), by confirming that the special electric winning flag is set to "1", it is determined that one game ball has entered the special electric winning device 32, and the number of remaining balls that can enter the special electric winning device 32 in a round game is reduced by one. When the process of reducing the number of balls that can enter by one is executed, the special electric winning flag is cleared to "0". The fourth output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the special electric detection sensor 45a should be executed to the management IC 66. The 15-ball counter is a counter for specifying in the main CPU 63 the number of times that 15 game balls should be paid out. If the value of the 15 prize ball counter is 1 or more, a 15 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (FIG. 8), and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0134] When it is confirmed that the fourth bit D4 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first actuation port detection sensor 46a (step S314: YES). In this case, the first actuation winning flag provided in the main RAM 65 is set to "1" (step S315), the fifth output flag provided in the main RAM 65 is set to "1" (step S316), and the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S317). The first actuation winning flag is a flag for the main CPU 63 to specify that one game ball has entered the first actuation port 33. In the special chart special power control process (step S213) of the timer interrupt process (FIG. 8), by confirming that the first operation winning flag is set to "1", a process for newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit number of 4. In the special power special power control process (step S213), it is confirmed that the first operation winning flag is set to "1", and when the process corresponding to the confirmation is executed, the first operation winning flag is cleared to "0". The fifth output flag is a flag for specifying in the main CPU 63 that the information output indicating that one game ball has been detected by the first operation port detection sensor 46a should be executed to the management IC 66. The one-ball counter is a counter for specifying in the main CPU 63 the number of times that one game ball should be paid out. When the value of the 1 prize ball counter is 1 or more, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S217 in the timer interrupt process (FIG. 8), and when the 1 prize ball command is output once, the value of the 1 prize ball counter is decremented by 1. When the payout control device 77 receives the 1 prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0135] When it is confirmed that the fifth bit D5 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second actuation port detection sensor 47a (step S318: YES). In this case, the second actuation winning flag provided in the main RAM 65 is set to "1" (step S319), the sixth output flag provided in the main RAM 65 is set to "1" (step S320), and the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S321). The second actuation winning flag is a flag for the main CPU 63 to specify that one game ball has entered the second actuation port 34. In the special chart special electric control process (step S213) of the timer interrupt process (FIG. 8), by confirming that the second operation winning flag is set to "1", a process for newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit number of 4. In the special electric special electric control process (step S213), it is confirmed that the second operation winning flag is set to "1", and when the process corresponding to the confirmation is executed, the second operation winning flag is cleared to "0". The sixth output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the second operation port detection sensor 47a should be executed to the management IC 66.

[0136] When it is confirmed that the sixth bit D6 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the outlet detection sensor 48a (step S322: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S323). The seventh output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the outlet detection sensor 48a should be executed to the management IC 66.

[0137] When it is confirmed that the seventh bit D7 has switched from a state in which "0" information is stored to a state in which "1" information is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S324: YES). In this case, the gate winning flag provided in the main RAM 65 is set to "1" (step S325). The gate winning flag is a flag for the main CPU 63 to specify that one game ball has entered the through gate 35. In the normal map normal power control process (step S214) of the timer interrupt process (FIG. 8), by confirming that the gate winning flag is set to "1", the process is executed to store the current numerical information of the normal power role release counter C4 as the normal map side reserved information in the normal power reserve area 65c, provided that the number of reserved information on the normal map side stored in the normal power reserve area 65c is less than the upper limit number of four. In the normal map normal power control process (step S214), it is confirmed that the gate winning flag is set to "1", and when the process corresponding to that confirmation is executed, the gate winning flag is cleared to "0".

[0138] As already explained, the timer interrupt process (FIG. 8) is started at a 4 msec cycle, so when one ball entry sensor 42a-49a starts detecting one game ball, the main CPU 63 specifies that one game ball has been detected by the ball entry sensor 42a-49a while the ball entry sensor 42a-49a continues to detect the one game ball. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0139] Next, a description will be given of the processing contents executed by the dispensing control device 77. First, the electrical configuration of the dispensing control device 77 and various devices that communicate with the dispensing control device 77 will be described with reference to the block diagram of FIG.

[0140] The dispensing control device 77 is equipped with an MPU 91. In addition to a dispensing side CPU 92, which is a processing device including a control unit and a calculation unit, the MPU 91 also includes a dispensing side ROM 93, a dispensing side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, and the like.

[0141] The dispensing ROM 93 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory such as a NOR type flash memory or a NAND type flash memory, and is used for read-only purposes. The dispensing ROM 93 stores various control programs and fixed value data executed by the dispensing CPU 92.

[0142] The dispensing side RAM 94 is a memory (i.e., a volatile memory means) that requires an external power supply to retain memory such as SRAM and DRAM, and is used for both reading and writing. The dispensing side RAM 94 is randomly accessible, and when compared with the dispensing side ROM 93 for the same data capacity, it takes less time to read data. The dispensing side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing side ROM 93.

[0143] The payout side CPU 92 is capable of two-way communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout side CPU 92 drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. In addition, the payout side CPU 92 monitors whether or not the game balls can be paid out normally, and when it is determined that the game balls cannot be paid out normally, it stops the payout device 76 even if the payout side RAM 94 stores information on the number of prize balls that have not been paid out. In addition, the payout side CPU 92 transmits a payout limit command to the main CPU 63 indicating that the game balls cannot be paid out normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the sound and light emission control device 81 so that a notification indicating that the game balls cannot be paid out normally is executed by the pattern display device 41, the display light emission unit 53, and the speaker unit 54. States in which it is not possible to normally dispense game balls include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been replenished with game balls, an abnormal dispense state in which the dispensing device 76 is not operating normally, a main body open state in which the gaming machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

[0144] A full tank detection sensor (not shown) is provided in the middle of the game ball passage leading from the payout device 76 to the lower tray 56a, and the detection result of the full tank detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

[0145] A no-ball detection sensor (not shown) is provided at a midpoint of the game ball passage leading from tank 75 to payout device 76, and the detection result of the no-ball detection sensor is input to payout side CPU 92. Payout side CPU 92 determines that a no-ball state exists when the no-ball detection sensor continues to not detect a game ball, and determines that the no-ball state has been released when the state in which the no-ball detection sensor continues to not detect a game ball is released.

[0146] The payout device 76 is provided with a payout detection sensor (not shown) for detecting game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout side CPU 92. When a game ball is detected by the payout detection sensor, the payout side CPU 92 determines that one game ball has been paid out from the payout device 76. Furthermore, the payout side CPU 92 determines that an abnormal payout state exists when a game ball is continuously not detected by the payout detection sensor despite the payout device 76 being driven and controlled so that a game ball is paid out, and determines that the abnormal payout state has been released when the state in which a game ball is continuously not detected by the payout detection sensor is released.

[0147] A front door open sensor 95 is provided on the front part of the inner frame 13 (see FIG. 2), and the detection result of the front door open sensor 95 is input to the dispensing side CPU 92. In this case, when the front door frame 14 is in a closed state relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing side CPU 92, and when the front door frame 14 is in an open state relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing side CPU 92. When the dispensing side CPU 92 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is in a closed state, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is in an open state. In addition, the dispensing side CPU 92 transmits a front door open command to the main side CPU 63 at the timing when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main side CPU 63 at the timing when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when a front door open command is received, and determines that the front door frame 14 is in a closed state when a front door close command is received.

[0148] A main body open sensor 96 is provided on the front part of the back pack unit 15 (see FIG. 2), and the detection result of the main body open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the payout side CPU 92. When the payout side CPU 92 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when the payout side CPU 92 receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state. In addition, the payout side CPU 92 transmits a main body open command to the main side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body close command to the main side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from an open state to a closed state. The main CPU 63 determines that the gaming machine main body 12 is in the open state when it receives a main body open command, and determines that the gaming machine main body 12 is in the closed state when it receives a main body close command.

[0149] The timer interrupt process executed by the dispensing CPU 92 will be described with reference to the time chart of Fig. 12. The timer interrupt process is repeatedly started at a predetermined cycle (for example, 2 msec).

[0150] First, the full tank process is executed (step S401). In the full tank process, as already explained, it is determined whether the tank is full based on the detection result of the full tank detection sensor, and if the tank is full, it executes a process to stop the payout of game balls and transmits a command indicating the full tank state to the main CPU 63. Also, if the full tank state is released, it executes a process to enable the payout of game balls and transmits a command indicating that the full tank state has been released to the main CPU 63.

[0151] Thereafter, the no-ball process is executed (step S402). In the no-ball process, as already explained, it is determined whether or not the state is a no-ball state based on the detection result of the no-ball detection sensor, and if the state is a no-ball state, it executes a process to stop the payout of game balls and transmits a command indicating the no-ball state to the main CPU 63. In addition, if the no-ball state is released, it executes a process to enable the payout of game balls and transmits a command indicating that the no-ball state has been released to the main CPU 63.

[0152] Thereafter, a payout abnormality monitoring process is executed (step S403). In the payout abnormality monitoring process, as already described, it is determined whether or not a payout abnormality state exists based on the detection result of the payout detection sensor, and if a payout abnormality state exists, a process for stopping the payout of game balls is executed and a command indicating that a payout abnormality state exists is sent to the main CPU 63. In addition, if the payout abnormality state is released, a process for enabling the payout of game balls is executed and a command indicating that the payout abnormality state has been released is sent to the main CPU 63.

[0153] Thereafter, a front door open monitoring process is executed (step S404). In the front door open monitoring process, as already described, it is determined whether the front door frame 14 is open or not based on the detection result of the front door open sensor 95, and if the front door frame 14 is open, a process for stopping the payout of game balls is executed and a front door open command is sent to the main CPU 63. In addition, if the front door frame 14 is closed, a process for enabling the payout of game balls is executed and a front door close command is sent to the main CPU 63.

[0154] Thereafter, a main body open monitoring process is executed (step S405). In the main body open monitoring process, as already described, it is determined whether the gaming machine main body 12 is in an open state based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is in an open state, a process for stopping the payout of game balls is executed and a main body open command is sent to the main CPU 63. In addition, if the gaming machine main body 12 is closed, a process for enabling the payout of game balls is executed and a main body close command is sent to the main CPU 63.

[0155] Then, a command read process is executed (step S406). In the command read process, a process of reading the prize ball command transmitted by the main CPU 63 is executed. Then, the prize ball command is stored in the payout side RAM 94. Then, after executing a prize ball setting process for adding the number corresponding to the received prize ball command to the unpaid prize ball number information in the payout side RAM 94 (step S407), a payout control process for controlling the execution of the payout of game balls by the payout device 76 is executed (step S408). In the payout control process, when the unpaid prize ball number information stored in the payout side RAM 94 is a value of 1 or more, the payout device 76 is driven and controlled, and when the payout detection sensor detects one game ball, the value of the prize ball number information is subtracted by 1. Then, when the value of the prize ball number information becomes "0", the drive control of the payout device 76 is stopped. Thereafter, an external information setting process is executed to control the start and end of output of an external signal according to the results of various processes executed in the current timer interrupt process (step S409).

[0156] Next, a configuration for externally outputting information from the pachinko machine 10 to a hall computer HC installed in the gaming hall will be described.

[0157] As shown in Fig. 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with a large number of external terminals, some of which, i.e., a plurality of external terminals, are electrically connected to the main CPU 63, and some of which, i.e., a plurality of external terminals, are electrically connected to the dispensing CPU 92. In this manner, each of the main CPU 63 and the dispensing CPU 92 is electrically connected to the external terminal board 97, so that the main CPU 63 and the dispensing CPU 92 can externally output information to the hall computer HC, as shown in Fig. 11.

[0158] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and one external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. In detail, a signal relay board 98 is provided at a midpoint of the signal path from the front door open sensor 95 to the dispensing side CPU 92. The signal relay board 98 is provided with a branch path SL2 that branches from the signal path SL1 from the front door open sensor 95 to the dispensing side CPU 92. The branch path SL2 is connected to an external terminal for opening the front door on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the front door open sensor 95 is not only input to the dispensing side CPU 92, but also input to the external terminal for opening the front door on the external terminal board 97. This makes it possible to externally output a signal indicating whether the front door frame 14 is in an open state to the hall computer HC without being controlled by the dispensing side CPU 92.

[0159] Regarding the main body open sensor 96 in detail, a branch path SL4 is provided on the signal relay board 98, which branches off from a signal path SL3 extending from the main body open sensor 96 toward the payout side CPU 92. The branch path SL4 is connected to an external terminal for main body opening on the external terminal board 97. Therefore, an electric signal corresponding to the detection result of the main body open sensor 96 is not only input to the payout side CPU 92, but also input to the external terminal for main body opening on the external terminal board 97. This makes it possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through the control of the payout side CPU 92.

[0160] Next, a description will be given of the contents of information externally output from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, a description will be given of the contents of information externally output from the main CPU 63 to the hall computer HC.

[0161] In the external information setting process (step S218) in the timer interrupt process (FIG. 8), the main CPU 63 performs information output settings to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the opening / closing execution mode is in progress, information indicating that the support mode is in the high frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (e.g., 100 balls) of game balls have been discharged from the game area PA through any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, information indicating that a game ball has entered the first operating port 33, and information indicating that a game ball has entered the second operating port 34.

[0162] In the external information setting process (step S409) in the timer interrupt process (FIG. 12), the payout side CPU 92 performs setting for outputting information to each external terminal assigned to the payout side CPU 92 in the external terminal board 97. The information output from the payout side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0163] The hall computer HC can grasp the manner in which the game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, The payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10 - Ball payout rate in normal game mode other than the open / close execution mode and the high frequency support mode (hereinafter, this ball payout rate will be referred to as "B") -Ball payout rate in open / close execution mode - Payout rate in high frequency support mode The number of times a game is played until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S") BS x "number of winning balls for winning into the first actuation port 33 and the second actuation port 34" The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S1") The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S2") B-(S1 x "number of winning balls for winning into the first operating port 33" + S2 x "number of winning balls for winning into the second operating port 34") The hall computer HC is thereby able to manage the manner in which game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are paid out when one game ball enters the corresponding ball entry section.

[0164] <Configuration for managing winning status of gaming balls> Next, a description will be given of a configuration for managing winning states of game balls using the management IC 66. First, the electrical configuration of the management IC 66 will be described with reference to the block diagram of FIG.

[0165] As already explained, the MPU 62 of the main control device 60 includes the main CPU 63, the main ROM 64, the main RAM 65, and the management IC 66. The MPU 62 also includes an I / F 101 and a read terminal 102 in addition to these.

[0166] The I / F 101 is an interface for transmitting and receiving signals between the MPU 62 and external devices. The I / F 101 is electrically connected to the main CPU 63 via the internal bus 103. Through the input port of the I / F 101, the detection results from the sensors such as the ball entry detection sensors 42a-49a and the commands from the payout side CPU 92 are input to the MPU 62, and various processes are executed by the main CPU 63 as described above based on the input detection results and the contents of the commands. In addition, when a signal is output to a device such as the special power drive unit 32b as a result of the execution of various processes by the main CPU 63, the signal output is performed through the output port of the I / F 101, and when a command is output to the payout side CPU 92 and the sound and light emission control device 81 as a result of the execution of various processes by the main CPU 63, the command output is performed through the output port of the I / F 101.

[0167] The reading terminal 102 is a terminal for electrically connecting the MPU 62 to a reading device, which is an external device of the pachinko machine 10, and is provided on the surface of the MPU 62 so that the terminal portion for connection is exposed. However, as already described, the main control board 61 on which the MPU 62 is mounted is housed in the board box 60a, and the reading terminal 102 faces the wall of the board box 60a so as not to be exposed to the outside of the main control device 60. Therefore, in order to electrically connect the reading device to the reading terminal 102, it is necessary to open the board box 60a to expose the MPU 62. This makes it possible to prevent the reading device from being electrically connected to the reading terminal 102 in an unauthorized manner. Note that this is not limited to this, and a configuration may be adopted in which an opening is formed in the board box 60a to expose the reading terminal 102 to the outside of the main control device 60, and the reading device can be electrically connected to the reading terminal 102 without the need to destroy the board box 60a.

[0168] The management IC 66 includes a management I / F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, and a history memory 117. These devices are connected to each other via an internal bus 66a provided in the management IC 66 so as to be capable of two-way communication.

[0169] The management side I / F 111 is an interface for receiving various signals from the main CPU 63 via a group of signal paths 118 for one-way communication built in the MPU 62, and for transmitting various signals to the reading terminal 102 via a group of signal paths 119 for one-way communication built in the MPU 62. Various signals from the main CPU 63 are input to an input port of the management side I / F 111, and various signals to the reading terminal 102 are output from an output port of the management side I / F 111. The main CPU 63 is electrically connected to the reading terminal 102 via a group of signal paths 120 for two-way communication built in the MPU 62.

[0170] The management CPU 112 is an arithmetic processing device including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain memory such as a NOR flash memory and a NAND flash memory, and is used for reading only. The management ROM 113 stores various control programs and fixed value data executed by the management CPU 112. The management RAM 114 is a memory (i.e., a volatile storage means) that requires an external power supply to retain memory such as an SRAM and a DRAM, and is used for both reading and writing. The management RAM 114 is randomly accessible, and when compared with the same data capacity, the time required for reading is faster than that of the management ROM 113. The management RAM 114 temporarily stores various data and the like for the execution of the control programs stored in the management ROM 113.

[0171] The RTC 115 is a real-time clock that constantly measures date and time information and is configured to be able to output the measured date and time information in response to an instruction from the management CPU 112. The RTC 115 is provided with a backup power supply, so that it is possible to measure date and time information even when the power to the pachinko machine 10 is cut off.

[0172] The correspondence memory 116 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as SRAM and DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a-122p provided in the input port 121 of the management side I / F 111 and the types of signals input to those buffers 122a-122p. Details of the contents of the correspondence memory 116 will be described later.

[0173] The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information regarding balls entering the game machine, which is received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be described later.

[0174] Next, a description will be given of the configuration of the input port 121 provided in the management side I / F 111. Fig. 14 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111.

[0175] The input port 121 is provided with a plurality of buffers 122a-122p. Specifically, first to sixteenth buffers 122a-122p are provided. One type of signal can be input to each of the first to sixteenth buffers 122a-122p via signal paths 118a-118p, and each of the first to sixteenth buffers 122a-122p stores information of "0" as the first data when the input signal is at a LOW level, and stores information of "1" as the second data when the input signal is at a HI level. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0176] A first signal corresponding to the detection result of the first winning hole detection sensor 42a is input to the first buffer 122a. In this case, the master CPU 63 outputs a first signal of LOW level when the first winning hole detection sensor 42a does not detect a new game ball, and outputs a first signal of HI level for a specific period when the first winning hole detection sensor 42a detects one game ball. This specific period is a period sufficient for the management CPU 112 to identify that a first signal of HI level has been input to the first buffer 122a.

[0177] The second buffer 122b receives a second signal corresponding to the detection result of the second winning hole detection sensor 43a. In this case, the master CPU 63 outputs a LOW level second signal when the second winning hole detection sensor 43a detects no new game ball, and outputs a HI level second signal for a specific period when the second winning hole detection sensor 43a detects one game ball. This specific period is sufficient for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

[0178] The third buffer 122c receives a third signal corresponding to the detection result of the third winning hole detection sensor 44a. In this case, the main CPU 63 outputs a LOW level third signal when the third winning hole detection sensor 44a detects no new game ball, and outputs a HI level third signal for a specific period when the third winning hole detection sensor 44a detects one game ball. This specific period is sufficient for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

[0179] A fourth signal corresponding to the detection result of the special electric detection sensor 45a is input to the fourth buffer 122d. In this case, the master CPU 63 outputs a LOW level fourth signal when the special electric detection sensor 45a does not detect a new game ball, and outputs a HI level fourth signal for a specific period when the special electric detection sensor 45a detects one game ball. This specific period is sufficient for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

[0180] A fifth signal corresponding to the detection result of the first actuation port detection sensor 46a is input to the fifth buffer 122e. In this case, the master CPU 63 outputs a LOW level fifth signal when the first actuation port detection sensor 46a does not detect a new game ball, and outputs a HI level fifth signal for a specific period when the first actuation port detection sensor 46a detects one game ball. This specific period is a period sufficient for the management CPU 112 to identify that a HI level fifth signal has been input to the fifth buffer 122e.

[0181] A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the master CPU 63 outputs a sixth signal of LOW level when the second actuation port detection sensor 47a does not detect a new game ball, and outputs a sixth signal of HI level for a specific period when the second actuation port detection sensor 47a detects one game ball. This specific period is a period sufficient for the management CPU 112 to determine that a sixth signal of HI level has been input to the sixth buffer 122f.

[0182] A seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g. In this case, the master CPU 63 outputs a LOW level seventh signal when the outlet detection sensor 48a does not detect a new game ball, and outputs a HI level seventh signal for a specific period when the outlet detection sensor 48a detects one game ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0183] The eighth buffer 122h receives an eighth signal corresponding to whether or not the open / close execution mode is in progress. In this case, the main CPU 63 continuously outputs the eighth signal at a LOW level when the open / close execution mode is not in progress, and continuously outputs the eighth signal at a HI level when the open / close execution mode is in progress.

[0184] A ninth signal corresponding to whether or not the high-frequency support mode is in effect is input to the ninth buffer 122i. In this case, the main CPU 63 continuously outputs a LOW-level ninth signal when the high-frequency support mode is not in effect, and continuously outputs a HI-level ninth signal when the high-frequency support mode is in effect.

[0185] A tenth signal corresponding to whether or not the front door frame 14 is open is input to the tenth buffer 122j. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

[0186] An output instruction signal is input to the 16th buffer 122p to cause the management CPU 112 to recognize the opportunity to output history information stored in the history memory 117 to the reading terminal 102. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output history information, and outputs a HI level output instruction signal for a specific period of time when there is a need to output history information. This specific period is a period of time sufficient for the management CPU 112 to identify that a HI level output instruction signal has been input to the 16th buffer 122p.

[0187] Although the eleventh buffer 122k, the twelfth buffer 122l, the thirteenth buffer 122m, the fourteenth buffer 122n, and the fifteenth buffer 122o can receive signals from the main CPU 63, they are blank in this pachinko machine 10 and do not receive normal signals. In this way, the number of buffers 122a-122p provided as the input port 121 of the management I / F 111 is greater than the number of types of signals output from the main CPU 63 to the management IC 66 in this pachinko machine 10, so that the management IC 66 can be used in models other than this pachinko machine 10. This makes it possible to increase the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and the first to sixteenth buffers 122a to 122p, respectively, so as to correspond one-to-one to the first to sixteenth buffers 122a to 122p, but this is not limited to this, and the signal paths 118k to 118o may not be formed between the main CPU 63 and the buffers 122k to 122o to be blanked.

[0188] It is determined in the design stage of the management IC 66 that an output instruction signal is input to the 16th buffer 122p in the input port 121 of the management I / F 111, and the management CPU 112 can specify that an output instruction signal is input to the 16th buffer 122p without receiving an instruction from the main CPU 63. On the other hand, it is not determined in the design stage of the management IC 66 what kind of signals are input to the first to fifteenth buffers 122a to 122o, and the types of these signals are specified by the management CPU 112 upon receiving an instruction from the main CPU 63. The type of these signals is specified by the management CPU 112 when a type identification command is sent from the main CPU 63 to the management CPU 112 when control is started in the main CPU 63 and the management CPU 112 in response to the supply of operating power to the MPU 62, as will be described in detail later. In this case, information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of various signals when operating power is being supplied, the information stored in the correspondence memory 116 is referenced.

[0189] 15 is an explanatory diagram for explaining the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to fifteenth correspondence areas 123a to 123o in one-to-one correspondence with the first to fifteenth buffers 122a to 122o provided in the input port 121 of the management side I / F 111.

[0190] The first correspondence area 123a stores information indicating that the general winning opening 31 is the information for the management CPU 112 to specify the type of signal input to the first buffer 122a. The first correspondence area 123a also stores information indicating that the general winning opening 31 is the information indicating the number of game balls paid out when one game ball enters the general winning opening 31 (10 balls). The second correspondence area 123b stores information indicating that the general winning opening 31 is the information for the management CPU 112 to specify the type of signal input to the second buffer 122b. The second correspondence area 123b also stores information indicating that the general winning opening 31 is the information indicating the number of game balls paid out when one game ball enters the general winning opening 31 (10 balls). The third correspondence area 123c stores information indicating that the general winning opening 31 is the information for specifying the type of signal input to the third buffer 122c by the management CPU 112. In addition, the third correspondence area 123c stores information indicating that the general winning opening 31 is the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31, in addition to the information indicating that the general winning opening 31 is the information.

[0191] The fourth correspondence area 123d stores information indicating that the device is the special electric winning device 32 as information for the management side CPU 112 to specify the type of signal input to the fourth buffer 122d. The fourth correspondence area 123d also stores information indicating that the device is the special electric winning device 32, as well as information on the number of game balls (15) that will be paid out when one game ball enters the special electric winning device 32. The fifth correspondence area 123e stores information indicating that the device is the first operating port 33 as information for the management side CPU 112 to specify the type of signal input to the fifth buffer 122e. The fifth correspondence area 123e also stores information indicating that the device is the first operating port 33, as well as information on the number of game balls (1) that will be paid out when one game ball enters the first operating port 33. The sixth correspondence area 123f stores information indicating that the signal is the second actuation port 34, as information for the management CPU 112 to identify the type of signal input to the sixth buffer 122f. The sixth correspondence area 123f also stores information indicating that the signal is the second actuation port 34, as well as information on the number of game balls (one) that will be paid out when one game ball enters the second actuation port 34. The seventh correspondence area 123g stores information indicating that the signal is the outlet 24a, as information for the management CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0192] The eighth correspondence area 123h stores information indicating the open / close execution mode as information for the management CPU 112 to identify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating the high frequency support mode as information for the management CPU 112 to identify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating the front door frame 14 as information for the management CPU 112 to identify the type of signal input to the tenth buffer 122j.

[0193] The eleventh correspondence area 123k stores information indicating that the area is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the eleventh buffer 122k. The twelfth correspondence area 123l stores information indicating that the area is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the twelfth buffer 122l. The thirteenth correspondence area 123m stores information indicating that the area is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the thirteenth buffer 122m. The fourteenth correspondence area 123n stores information indicating that the area is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the fourteenth buffer 122n. The fifteenth correspondence area 123o stores information indicating that the area is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the fifteenth buffer 122o.

[0194] As described above, by configuring the management CPU 112 to specify what types of signals are input to the first to fifteenth buffers 122a to 122o by receiving instructions from the main CPU 63, it becomes possible to use the management IC 66 for models other than the present pachinko machine 10. This makes it possible to increase the versatility of the management IC 66.

[0195] Moreover, instead of outputting information for recognizing the type of signal every time a signal corresponding to storage of history information is output to the first to fifteenth buffers 122a to 122o, information for recognizing the type of signal is output in advance, and information for specifying the type of signal input to the first to fifteenth buffers 122a to 122o by the management CPU 112 based on the output information is stored in the correspondence memory 116. This makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration in which information for recognizing the type of signal is output every time a signal corresponding to storage of history information is output to the first to fifteenth buffers 122a to 122o.

[0196] Moreover, the information for the management CPU 112 to specify the types of signals input to the first to fifteenth buffers 122a to 122o is output when the supply of operating power starts. This allows the management CPU 112 to specify the types of signals input to the first to fifteenth buffers 122a to 122o when a game is started in the pachinko machine 10.

[0197] In addition, the information setting that the output instruction signal is input to the 16th buffer 122p is performed at the design stage of the management IC 66. This makes it possible to omit the process for identifying the type of signal input to the 16th buffer 122p for the output instruction signal that is used reliably not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load of the process for identifying the type of such signal.

[0198] Next, a description will be given of the history memory 117 of the management IC 66. FIG.

[0199] The history memory 117 is provided with a history area 124 for sequentially storing the history information. In the history area 124, a plurality of pointer information are set with consecutive numbers, and a history information storage area 125 is set in one-to-one correspondence with each pointer information. The history information storage area 125 can store a combination of RTC information and correspondence information. In this case, each history information storage area 125 has a data capacity of 2 bytes, and a data capacity of 1 byte is assigned as an area for storing RTC information, and a data capacity of 1 byte is assigned as an area for storing correspondence information. When it becomes necessary to store correspondence information according to the signal input to the first to fifteenth buffers 122a to 122o (actually, the first to tenth buffers 122a to 122j in this pachinko machine 10), first, the date information and time information measured by the current RTC 115 are stored in the area for storing RTC information in the history information storage area 125 corresponding to the pointer information currently being written. Thereafter, the correspondence information corresponding to the buffers 122a-122o that triggered the current information storage is read from the correspondence areas 123a-123o corresponding to the buffers 122a-122o in the correspondence memory 116, and the read correspondence information is stored in an area for storing correspondence information in the history information storage area 125 that corresponds to the pointer information currently being written.

[0200] Specifically, regarding the correspondence information stored in the history information storage area 125, since the first to seventh buffers 122a to 122g receive signals corresponding to the detection results of the ball entry detection sensors 42a to 48a as already explained, the first to seventh correspondence areas 123a to 123g in the correspondence memory 116 store information corresponding to the types of the ball entry detection sensors 42a to 48a. More specifically, information corresponding to the types of ball entry sections corresponding to the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. In this pachinko machine 10, since the first to third winning hole detection sensors 42a to 44a all detect game balls that have entered the general winning hole 31 as already explained, the first to third correspondence areas 123a to 123c corresponding to these first to third winning hole detection sensors 42a to 44a all store information indicating that they are the general winning hole 31. Also, the fourth correspondence area 123d stores information indicating that it is the special electric winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the outlet 24a. If the buffer 122a-122o that triggered the current information storage is any of the first to seventh buffers 122a-122g, information on the type of ball entry part corresponding to that buffer 122a-122g is read from any of the first to seventh correspondence areas 123a-123g, and the read information on the type of ball entry part is stored as is in the area for storing the correspondence information in the history information storage area 125.

[0201] On the other hand, the eighth buffer 122h receives a signal indicating whether or not it is in the opening / closing execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in the high frequency support mode, and the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open. Therefore, the eighth correspondence area 123h stores information indicating the opening / closing execution mode, the ninth correspondence area 123i stores information indicating the high frequency support mode, and the tenth correspondence area 123j stores information indicating the front door frame 14.

[0202] As already explained, the main CPU 63 continuously outputs the 8th signal at a LOW level when the open / close execution mode is not in effect, and continuously outputs the 8th signal at a HI level when the open / close execution mode is in effect, so that the control CPU 112 can determine that the open / close execution mode has started when the 8th signal changes from a LOW level to a HI level, and can determine that the open / close execution mode has ended when the 8th signal changes from a HI level to a LOW level. In addition, in both cases where the 8th signal changes from a LOW level to a HI level and where the HI level changes from a LOW level to a LOW level, the control CPU 112 determines that a trigger for storing the correspondence information in the history information storage area 125 has occurred. In other words, when the 8th signal changes from a LOW level to a HI level, not only the information indicating the open / close execution mode read from the 8th correspondence area 123h but also the start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the eighth signal changes from HI level to LOW level, not only the information indicating the opening / closing execution mode read from the eighth correspondence area 123h but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

[0203] As already explained, the main CPU 63 continuously outputs the ninth signal at a LOW level when the high-frequency support mode is not in effect, and continuously outputs the ninth signal at a HI level when the high-frequency support mode is in effect, so that the control CPU 112 can determine that the high-frequency support mode has started when the ninth signal changes from a LOW level to a HI level, and can determine that the high-frequency support mode has ended when the ninth signal changes from a HI level to a LOW level. In addition, in both cases where the ninth signal changes from a LOW level to a HI level and where the HI level changes from a LOW level to a LOW level, the control CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from a LOW level to a HI level, not only the information indicating the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the 9th signal changes from HI level to LOW level, not only the information indicating that it is the high-frequency support mode read from the 9th correspondence area 123i but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

[0204] As already explained, the main CPU 63 continuously outputs the tenth signal at a LOW level when the front door frame 14 is in a closed state, and continuously outputs the tenth signal at a HI level when the front door frame 14 is in an open state, so that the management CPU 112 can determine that the front door frame 14 is opened when the tenth signal changes from a LOW level to a HI level, and can determine that the front door frame 14 is closed when the tenth signal changes from a HI level to a LOW level. In addition, in both cases where the tenth signal changes from a LOW level to a HI level and where the HI level changes from a LOW level to a LOW level, the management CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the tenth signal changes from a LOW level to a HI level, not only the information indicating that it is the front door frame 14 read from the tenth correspondence area 123j but also the opening start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening completion information are stored in an area for storing correspondence information in the history information storage area 125.

[0205] The history information storage area 125 is provided for a number of times that allows all the history information generated during the ten consecutive business days during which the shooting of game balls continues in the pachinko machine 10 from opening to closing to be stored. For example, if history information is generated 60,000 times a day, more than 600,000 history information storage areas 125 are provided. This makes it possible to store and hold all the history information in the history memory 117 for at least ten days.

[0206] The history memory 117 is provided with a pointer area 126 in addition to the history area 124. The pointer area 126 stores information for the management CPU 112 to specify the pointer information currently being written in the history memory 117. Specifically, at the time of shipping the pachinko machine 10, information is set in the pointer area 126 specifying the pointer information of "0" as the writing target. Then, every time one piece of history information is newly stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information becomes the writing target and history information is stored in the history information storage area 125 corresponding to the last pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the writing target. As a result, when a storage trigger for history information occurs in which the number of pieces of history information that can be stored is exceeded, the history information storage area 125 in which the oldest history information is stored is overwritten with the new history information in order.

[0207] Furthermore, when the reading of history information from the history memory 117 occurs by a reading device, the history information storage area 125 is cleared to all "0"s, and the information in the pointer area 126 is updated so that pointer information of "0" becomes the write target. This makes it possible to prevent history information that has once been read from becoming the read target again.

[0208] Next, a specific processing configuration for managing the winning status of the game balls using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence between the first to fifteenth buffers 122a to 122o provided in the input port 121 of the management side I / F 111 and the signal types in the correspondence memory 116 will be described. Fig. 17 is a flowchart showing the recognition processing executed by the main side CPU 63. The recognition processing is executed in step S110 in the main processing (Fig. 7).

[0209] First, "15" is set to a recognition output counter provided in the main RAM 65 (step S501). The recognition output counter is a counter for the main CPU 63 to identify the remaining number of times information output is required to make the management CPU 112 recognize which type of signal each of the buffers 122a-122p of the input port 121 in the management I / F 111 corresponds to. As already explained, the 15 buffers 122a-122o are targets for signal type recognition, so the recognition output counter is set to "15".

[0210] Thereafter, output processing of the identification start command is executed (step S502). The main CPU 63 outputs various commands to the management CPU 112 to make the management CPU 112 recognize which types of signals the first to fifteenth buffers 122a to 122o correspond to. When outputting these commands, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 to store the history information are used to output a command to make the management CPU 112 recognize which types of signals the first to fifteenth buffers 122a to 122o correspond to. This makes it possible to reduce the number of signal paths and simplify the configuration, compared to a configuration in which the signal paths for outputting the commands are provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In the output process of the identification start command, the output state of the ninth signal is switched to HI level at the timing of starting the output of the identification start command in order to make the management CPU 112 recognize that a new command has been transmitted. The output period of the identification start command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 specifies that a process should be started for storing information on the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals in the correspondence memory 116.

[0211] Thereafter, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S503). In this case, the first buffer 122a is the first to be set as a signal type, and thereafter, the signal type recognition setting corresponding to the first to fifteenth buffers 122a to 122o is performed such that the signal type is set to the nth buffer and then the (n+1)th buffer. Therefore, if the recognition output counter is "15" to "13", a type identification command indicating that it is the general winning port 31 and the number of prize balls is read out; if the recognition output counter is "12", a type identification command indicating that it is the special winning device 32 and the number of prize balls is read out; if the recognition output counter is "11", a type identification command indicating that it is the first operating port 33 and the number of prize balls is read out; if the recognition output counter is "10", a type identification command indicating that it is the second operating port 34 and the number of prize balls is read out; if the recognition output counter is "9", a type identification command indicating that it is the outlet 24a is read out; if the recognition output counter is "8", a type identification command indicating that it is in the opening / closing execution mode is read out; if the recognition output counter is "7", a type identification command indicating that it is in the high frequency support mode is read out; if the recognition output counter is "6", a type identification command indicating that it is the front door frame 14 is read out; and if the recognition output counter is "5" to "1", a type identification command indicating that it is blank is read out.

[0212] Then, the output process of the read type identification command is executed (step S504). The type identification command has a data capacity of 8 bits like the identification start command, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In the output process of the identified type command, the output state of the ninth signal is switched to HI level at the timing of starting output of the identified type command to make the management CPU 112 recognize that a new command has been transmitted. The output period of the identified type command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identified type command and the output state of the ninth signal. By receiving the identified type command, the management CPU 112 stores information corresponding to the identified type command in the correspondence areas 123a to 123o corresponding to the buffer that is the current setting target among the first to fifteenth buffers 122a to 122o.

[0213] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S505), and it is determined whether the value of the recognition output counter after decrement is "0" (step S506). If the value of the recognition output counter is 1 or more (step S506: NO), a process is executed to output a type identification command corresponding to the value of the recognition output counter after decrement (steps S503 and S504).

[0214] On the other hand, if the value of the recognition output counter is "0" (step S506: YES), output processing of the recognition end command is executed (step S507). The recognition end command has a data capacity of 8 bits, and the data of each bit is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the recognition end command output processing, the output state of the ninth signal is switched to HI level at the timing of starting output of the recognition end command in order to make the management side CPU 112 recognize that a new command has been transmitted. In addition, the output period of the recognition end command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management side CPU 112 to recognize the recognition end command and the output state of the ninth signal. By receiving the recognition end command, the management side CPU 112 determines that the process for storing information on the correspondence relationship between the first to fifteenth buffers 122a to 122o and the signal types in the correspondence relationship memory 116 has been completed.

[0215] Next, the management process executed by the management CPU 112 will be described with reference to the flowchart of Fig. 18. The management process is started when the supply of operating power to the management CPU 112 is started. The processing speed of the management CPU 112 is faster than the processing speed of the main CPU 63, and the combination of processes from step S606 onwards in the management process is executed 16 or more times from the start of one timer interrupt process (Fig. 8) in the main CPU 63 until the start of the next timer interrupt process (Fig. 8).

[0216] When an identification start command is received from the main CPU 63 (step S601: YES), the value of a setting target counter provided in the management RAM 114 is cleared to "0" (step S602). The setting target counter is a counter for the management CPU 112 to specify the type of buffers 122a-122o for which a signal type is to be set. The first buffer 122a is the first to be set as a signal type, and thereafter the nth buffer and then the (n+1)th buffer are set as a signal type setting target.

[0217] Thereafter, on condition that a type identification command has been received from the main CPU 63 (step S603: YES), a correspondence setting process is executed (step S604). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter of the control RAM 114, among the first to fifteenth correspondence areas 123a to 123o of the correspondence memory 116. Thereafter, the value of the setting target counter of the control RAM 114 is incremented by 1 (step S605).

[0218] If a negative determination is made in step S603, or if the process of step S605 is executed, it is determined whether or not an identification end command has been received from the main CPU 63 (step S606). If an identification end command has not been received (step S606: NO), the process returns to step S603, and the processes of steps S604 and S605 are executed again on the condition that a new type identification command is received from the main CPU 63 (step S603: YES).

[0219] If an identification end command has been received from the main CPU 63 (step S606: YES), the processes of steps S607 and S608 are repeatedly executed. In step S607, details of which will be described later, a history setting process is executed for storing history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S608, details of which will be described later, an external output process is executed for outputting the history information stored in the history memory 117 to the reading terminal 102.

[0220] Fig. 19 is a time chart showing how information on the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o is stored in the correspondence memory 116. Fig. 19(a) shows a period during which a command is output from the main CPU 63 to the control CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Fig. 19(b) shows a period during which the output state of the ninth signal is at HI level, Fig. 19(c) shows an execution period of an identification state during which a process for identifying the correspondence between the first to fifteenth buffers 122a to 122o and the types of signals input to these buffers 122a to 122o is executed, and Fig. 19(d) shows the timing at which the correspondence setting process (step S604) is executed by the control CPU 112.

[0221] As the supply of operating power to the main CPU 63 and the control CPU 112 is started, output of the identification start command using the first to eighth signals is started at the timing of t1 as shown in FIG. 19(a). Also, at the timing of t1, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 19(b). Thereafter, at the timing of t2 in which the output of the identification start command is continued, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 19(b). The control CPU 112 identifies that a command has been sent from the main CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the identification start command has been received, the control CPU 112 makes an affirmative decision in step S601 of the management process (FIG. 18) to enter the identification state. Thereafter, output of the identification start command is stopped at the timing of t3 as shown in FIG. 19(a).

[0222] After that, at the timing of t4, the output of the first type identification command using the first to eighth signals is started as shown in FIG. 19(a). Also, at the timing of t4, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 19(b). After that, at the timing of t5, in which the output of the type identification command is continued, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 19(b). The management side CPU 112 identifies that a command has been sent from the main side CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main side CPU 63 by confirming the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command has been received, the management side CPU 112 executes the correspondence setting process as shown in FIG. 19(d) at the timing of t5. In the correspondence setting process, the information indicating that it is the general winning port 31 and the information on the number of winning balls are stored in the first correspondence area 123a of the correspondence memory 116. After that, at timing t6, the output of the type identification command is stopped as shown in FIG. 19(a).

[0223] Thereafter, from time t7 to time t9, from time t10 to time t12, from time t13 to time t15, and from time t16 to time t18, similar to the time t4 to time t6, the correspondence setting process corresponding to the type identification command output from the master CPU 63 is executed by the management CPU 112. In this case, the correspondence setting process corresponding to the 15th type identification command is completed from time t16 to time t18.

[0224] After that, at the timing of t19, the output of the identification end command using the first to eighth signals is started as shown in FIG. 19(a). Also, at the timing of t19, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 19(b). After that, at the timing of t20, in which the output of the identification end command is continued, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 19(b). The control side CPU 112 identifies that a command has been sent from the main side CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main side CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the identification end command has been received, the identification state of the control side CPU 112 is ended at the timing of t20 as shown in FIG. 19(c). After that, the output of the identification end command is stopped at the timing of t21 as shown in FIG. 19(a).

[0225] As described above, the configuration allows the management CPU 112 to recognize whether or not a command is being output using the 9th signal, so that the management CPU 112 can clearly recognize that a command is being output even in a configuration in which the command is output using the 1st to 8th signals (i.e., the 1st to 8th signal paths) used to instruct the management CPU 112 to store history information.

[0226] Next, a description will be given of a process configuration for storing history information in the history memory 117. Fig. 20 is a flowchart showing the output process for management executed by the main CPU 63. The output process for management is executed in step S219 in the timer interrupt process (Fig. 8).

[0227] First, the managed object counter provided in the main RAM 65 is set to "10" (step S701). The managed object counter is a counter for the main CPU 63 to determine whether there is a managed object that has not been specified as whether the signal output state to the management CPU 112 should be changed in the current management output process, and for which managed object the signal output state to the management CPU 112 should be changed. In one management output process, the managed objects for which the main CPU 63 specifies whether the signal output state to the management CPU 112 should be changed are the seven ball entry detection sensors 42a-48a, whether the opening and closing execution mode is being executed, whether the high frequency support mode is being executed, and whether the front door frame 14 is being opened or closed, a total of 10 objects. Therefore, the managed object counter is initially set to "10".

[0228] Then, it is determined whether the output state of the signal to the management side CPU 112 for the managed object corresponding to the current value of the managed counter is at HI level (step S702). If it is not at HI level (step S702: NO), it is determined whether the value of the managed counter is 4 or more, thereby identifying which of the seven ball entry detection sensors 42a to 48a is the managed object corresponding to the value of the managed counter (step S703).

[0229] If the answer is "yes" in step S703, it is determined whether the output flag of the main RAM 65 corresponding to the value of the managed counter is set to "1" (step S704). Specifically, if the value of the managed counter is "10" and corresponds to the first winning hole detection sensor 42a, it is determined whether the first output flag is set to "1", if the value of the managed counter is "9" and corresponds to the second winning hole detection sensor 43a, it is determined whether the second output flag is set to "1", if the value of the managed counter is "8" and corresponds to the third winning hole detection sensor 44a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "7" and corresponds to the special power detection sensor 45a, it is determined whether the third ... special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "7" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "7" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to " If the value of the managed counter is "6" and corresponds to the first actuation port detection sensor 46a, the process determines whether the fourth output flag is set to "1" or not; if the value of the managed counter is "5" and corresponds to the second actuation port detection sensor 47a, the process determines whether the sixth output flag is set to "1" or not; if the value of the managed counter is "4" and corresponds to the out port 24a, the process determines whether the seventh output flag is set to "1" or not. As already explained, the first to seventh output flags are set to "1" in the ball entry detection process (FIG. 10).

[0230] If the output flag corresponding to the value of the managed counter is set to "1" (step S704: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HI level (step S705). After that, the output flag corresponding to the value of the managed counter is cleared to "0" (step S706).

[0231] If a negative determination is made in step S703, it is determined whether or not a trigger has occurred to switch the output state of the signal corresponding to the value of the managed counter to HI level (step S707). Specifically, if the value of the managed counter is "3", it is determined whether or not a transition to the open / close execution mode has occurred, if the value of the managed counter is "2", it is determined whether or not a transition to the high frequency support mode has occurred, and if the value of the managed counter is "1", it is determined whether or not the front door frame 14 has entered the open state. If a positive determination is made in step S707, the output state of the signal corresponding to the value of the managed counter is set to HI level (step S708).

[0232] If the answer is YES in step S702, it is determined whether or not a trigger has occurred to switch the output state of the signal corresponding to the value of the managed counter to a LOW level (step S709). Specifically, if the value of the managed counter is 4 or more and the currently managed object is any of the ball entry detection sensors 42a-48a, it is determined whether or not a HI output duration (specifically, 10 msec) has elapsed since the output state of the signal corresponding to the value of the managed counter among the first to seventh signals was switched from a LOW level to a HI level. This HI output duration is set in the management CPU 112 to a period longer than the longest processing interval of the history setting process (step S607) of the management process (FIG. 18), and is a period that allows the management CPU 112 to reliably identify the output state of the signal that has switched from a LOW level to a HI level. Also, if the value of the managed counter is "3" and the current managed object is in the open / close execution mode, it is determined whether the open / close execution mode has ended, if the value of the managed counter is "2" and the current managed object is in the high-frequency support mode, it is determined whether the high-frequency support mode has ended, and if the value of the managed counter is "1" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. If an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed counter to a LOW level (step S709: YES), the output state of the signal corresponding to the value of the managed counter is set to a LOW level (step S710).

[0233] If a negative determination is made in step S704, if the process of step S706 is executed, if a negative determination is made in step S707, if the process of step S708 is executed, if a negative determination is made in step S709, or if the process of step S710 is executed, the value of the managed object counter in the main RAM 65 is decremented by 1 (step S711). Then, it is determined whether the value of the managed object counter after the decrement is "0" (step S712). If the value of the managed object counter is 1 or more (step S712: NO), the process of step S702 and subsequent steps is executed for the managed object corresponding to the new managed object counter value.

[0234] Next, the history setting process executed by the management side CPU 112 will be described with reference to the flowchart of Fig. 21. The history setting process is executed in step S607 of the management process (Fig. 18).

[0235] First, the number of buffers to be checked by the management CPU 112 among the first to fifteenth buffers 122a to 122o is set in a check target counter provided in the management RAM 114 (step S801). Specifically, the number of correspondence areas in which information other than information indicating that they are blank is stored among the first to fifteenth correspondence areas 123a to 123o in the correspondence memory 116 is identified, and the information of the identified number is set in the check target counter. As already explained, in this pachinko machine 10, information other than information indicating that they are blank is stored in the first to tenth correspondence areas 123a to 123j, so in step S801, the check target counter is set to "10".

[0236] Thereafter, by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fifteenth buffers 122a to 122o has changed from "0" to "1", it is determined whether the output state of the input signal from the main CPU 63 to the buffer has been switched from LOW level to HI level (step S802). When the value of the counter to be checked is "n", the nth buffers 122a to 122o are the targets for checking the numerical information. For example, when the value of the counter to be checked is "10", the tenth buffer 122j is the target for checking the numerical information, and when the value of the counter to be checked is "5", the fifth buffer 122e is the target for checking the numerical information.

[0237] If the determination in step S802 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S803). Then, a write process to the history memory 117 is executed (step S804). In the write process, the pointer information in the history area 124 currently being written is specified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S803 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information currently being written. In addition, the correspondence information is read from the correspondence areas 123a to 123o corresponding to the current value of the counter to be confirmed, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information currently being written. In addition, if the correspondence information is any one of information indicating the open / close execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information currently being written. When the value of the counter to be checked is "n", the n-th correspondence area 123a to 123o is the target from which the correspondence information is read out. For example, when the value of the counter to be checked is "10", the tenth correspondence area 123j is the target from which the correspondence information is read out, and when the value of the counter to be checked is "5", the fifth correspondence area 123e is the target from which the correspondence information is read out.

[0238] By executing the writing process as described above, when the value of the counter to be checked is any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, the combination of the RTC information and the correspondence relationship information indicating that it is any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Also, when the value of the counter to be checked is any of the opening / closing execution mode, the high frequency support mode, and the front door frame 14, the combination of the RTC information, the correspondence relationship information indicating that it is any of the opening / closing execution mode, the high frequency support mode, and the front door frame 14, and the start information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written.

[0239] Thereafter, a target pointer update process is executed (step S805). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

[0240] When a negative determination is made in step S802, or when the process of step S805 is executed, it is determined whether or not the correspondence information for checking whether the signal output has been switched to a LOW level is stored in the correspondence area 123a-123o corresponding to the current value of the counter to be checked (step S806). Specifically, when the current value of the counter to be checked is "8"-"10", any of information indicating the opening / closing execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14 is stored in the corresponding correspondence area 123h-123j, so that a positive determination is made in step S806.

[0241] If the determination in step S806 is positive, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current counter value to be checked among the first to fifteenth buffers 122a to 122o has been switched from HI level to LOW level by checking whether the numerical information stored in the buffer corresponding to the current counter value to be checked has been changed from "1" to "0" (step S807). If the determination in step S807 is positive, the RTC information is read out as in step S803 (step S808), and further a write process to the history memory 117 is executed (step S809). In the write process, the RTC information read out in step S808 is written into the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, the correspondence information is read out from the correspondence areas 123a to 123o corresponding to the current counter value to be checked, and the correspondence information is written into the history information storage area 125 corresponding to the pointer information to be written. In addition, not only the correspondence relationship information but also the end information is written in the history information storage area 125 corresponding to the pointer information to be written. By executing the writing process in this manner, when the value of the counter to be checked is either the open / close execution mode, the high frequency support mode, or the front door frame 14, a combination of the RTC information, the correspondence relationship information indicating either the open / close execution mode, the high frequency support mode, or the front door frame 14, and the end information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Thereafter, the target pointer update process is executed in the same manner as in step S805 (step S810).

[0242] If a negative determination is made in step S806, if a negative determination is made in step S807, or if the process of step S810 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S811). Then, it is determined whether the value of the confirmation target counter after decrement by 1 is "0" (step S812). If the value of the confirmation target counter is 1 or greater (step S812: NO), the process of step S802 and subsequent steps is executed for the confirmation target corresponding to the new confirmation target counter value.

[0243] Next, the manner in which history information is stored in history memory 117 will be described with reference to the time chart of Fig. 22. Fig. 22(a) shows a period in which a HI level signal is input to any of the first to seventh buffers 122a to 122g, Fig. 22(b) shows a period in which a HI level signal is input to the eighth buffer 122h, Fig. 22(c) shows a period in which a HI level signal is input to the ninth buffer 122i, Fig. 22(d) shows a period in which a HI level signal is input to the tenth buffer 122j, and Fig. 22(e) shows the timing of writing history information to history memory 117.

[0244] At time t1, the output state of a signal input to any one of the first to seventh buffers 122a to 122g is switched from LOW level to HI level as shown in FIG. 22(a). Therefore, at time t1, history information is written to history memory 117 as shown in FIG. 22(e). Thereafter, at time t2, the signal switched to HI level at time t1 as shown in FIG. 22(a) is switched to LOW level. However, since this signal is input to any one of the first to seventh buffers 122a to 122g and the switching to LOW level is not a target for storing history information, writing of history information is not executed at time t2 as shown in FIG. 22(e).

[0245] After that, at times t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to any of the first to seventh buffers 122a to 122g is switched from LOW level to HIGH level as shown in Fig. 22(a). Therefore, at each of these times, history information is written as shown in Fig. 22(e).

[0246] As shown in FIG. 22(b), the output state of the signal input to the eighth buffer 122h is at HI level from t4 to t7. This eighth buffer 122h corresponds to the occurrence or non-occurrence of the open / close execution mode. Therefore, as shown in FIG. 22(e), history information is written at t4, which is the timing when the output state of the signal input to the eighth buffer 122h switches to HI level, and at t7, which is the timing when the output state of the signal switches to LOW level. In this case, the history information written at t4 includes start information, and the history information written at t7 includes end information. This makes it possible to grasp the execution period of the open / close execution mode by checking the history information in the history memory 117.

[0247] Moreover, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening and closing execution mode. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening and closing execution mode by comparing the RTC information.

[0248] As shown in FIG. 22(c), the output state of the signal input to the ninth buffer 122i is at HI level from t8 to t11. This ninth buffer 122i corresponds to the occurrence or non-occurrence of the high frequency support mode. Therefore, as shown in FIG. 22(e), history information is written at t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to HI level, and at t11, which is the timing when the output state of the signal switches to LOW level. In this case, the history information written at t8 includes start information, and the history information written at t11 ​​includes end information. This makes it possible to grasp the execution period of the high frequency support mode by checking the history information in the history memory 117.

[0249] In addition, the history information is written in the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is in the high-frequency support mode or not. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is in the high-frequency support mode or not by comparing the RTC information.

[0250] As shown in FIG. 22(d), the output state of the signal input to the tenth buffer 122j is HI level from t12 to t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or not. Therefore, as shown in FIG. 22(e), at t12, when the output state of the signal input to the tenth buffer 122j is switched to HI level, and at t15, when the output state of the signal is switched to LOW level, history information is written. In this case, the history information written at t12 includes start information, and the history information written at t15 includes end information. This makes it possible to grasp the period during which the front door frame 14 is open by checking the history information in the history memory 117.

[0251] In addition, the history information is written in the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is from the time the front door frame 14 is open or not. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is from the time the front door frame 14 is open or not by comparing the RTC information.

[0252] Next, a process configuration for outputting history information stored in the history memory 117 to a reading device electrically connected to the reading terminal 102 of the MPU 62 will be described. Fig. 23 is a flowchart showing the data output process executed by the main CPU 63. The data output process is executed in step S111 in the main process (Fig. 7).

[0253] In the data output process, first, it is determined whether or not a connection signal indicating that the reading device is electrically connected to the reading terminal 102 is received from the reading terminal 102 (step S901). The reading device is configured to output a connection signal when electrically connected to the reading terminal 102, and if the connection signal is received through the reading terminal 102, a positive determination is made in step S901.

[0254] If a negative determination is made in step S901, the data output process is terminated. In this case, in order to execute the data output process, it is necessary to restart the supply of operating power to the MPU 62. In order to output the history information externally, it is necessary to start the supply of operating power to the MPU 62 with a reading device electrically connected to the reading terminal 102. Since the power supply operation unit for stopping and starting the supply of operating power to the MPU 62 is provided on the back of the back pack unit 15, it is necessary to open the gaming machine main body 12 relative to the outer frame 11 to expose the back of the back pack unit 15 in order to perform the stopping and starting operations. Under such circumstances, by configuring it so that the supply of operating power to the MPU 62 must be started with a reading device electrically connected to the reading terminal 102 in order to output the history information externally, it is possible to make it difficult for anyone other than the manager of the gaming hall to read the history information.

[0255] If the determination in step S901 is affirmative, it is determined whether or not a signal for confirming control information is received from the read terminal 102, and it is determined whether or not the current connection of the reading device to the read terminal 102 corresponds to confirmation of control information (programs and data) of the main ROM 64 (step S902). The reading device is configured to be able to perform both confirmation of control information and confirmation of history information, and when confirmation of control information is selected by manual operation of the reading device, a signal for confirming control information is transmitted from the reading device, and when confirmation of history information is selected by manual operation of the reading device, a signal for confirming history is transmitted from the reading device. Note that this is not limited to this, and a configuration may be adopted in which the reading device for confirming control information and the reading device for confirming history are separate. In this case, when a reading device for confirming control information is electrically connected to the read terminal 102, a signal for confirming control information is transmitted from the reading device, and when a reading device for confirming history is electrically connected to the read terminal 102, a signal for confirming history is transmitted from the reading device.

[0256] If the determination in step S902 is affirmative, an output process for confirming the control information is executed (step S903). In the output process, the program and data are read from the main ROM 64 as control information, and the read control information is output to the read terminal 102. This makes it possible to read the control information in a reading device electrically connected to the read terminal 102, and to confirm whether the control information is authentic or normal.

[0257] If a negative determination is made in step S902, an output instruction signal is sent to the control CPU 112 (step S904). Specifically, the output state of the output instruction signal is switched from a LOW level to a HI level. This HI level output state continues for a specific period of time. This specific period is long enough for the control CPU 112 to determine that a HI level output instruction signal has been input to the sixteenth buffer 122p. As a result of the output state of the output instruction signal being switched to a HI level, a process for outputting history information is executed in the control CPU 112. This process will be described in detail later.

[0258] When the process of step S903 or step S904 is executed, it is determined whether the electrical connection of the reading device to the reading terminal 102 is still continued (step S905). If it is still continued (step S905: YES), the process waits in step S905. This makes it possible to prevent a process set in the execution order after the data output process from being executed until the electrical connection of the reading device to the reading terminal 102 is released. When the electrical connection of the reading device to the reading terminal 102 is released (step S905: NO), the data output process is terminated.

[0259] Next, the external output process executed by the management CPU 112 will be described with reference to the flowchart of Fig. 24. The external output process is executed in step S608 of the management process (Fig. 18).

[0260] When the output state of the output instruction signal received from the main CPU 63 is switched from LOW level to HI level (step S1001: YES), the process for outputting the history information from step S1002 onwards is executed. Specifically, first, the number of history information storage areas 125 in which the correspondence relationship information indicating the out port 24a is stored in the history area 124 of the history memory 117 is counted to calculate the number of balls entering the out port 24a (step S1002). In addition, the number of history information storage areas 125 in which the correspondence relationship information indicating the general winning port 31 is stored in the history area 124 of the history memory 117 is counted to calculate the number of balls entering the general winning port 31 (step S1003). In addition, the number of history information storage areas 125 in which the correspondence relationship information indicating the special winning device 32 is stored in the history area 124 of the history memory 117 is counted to calculate the number of balls entering the special winning device 32 (step S1004). The number of balls that have entered the first operation port 33 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the operation port 33 is stored in the history area 124 of the history memory 117 (step S1005). The number of balls that have entered the second operation port 34 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the operation port 34 is stored in the history area 124 of the history memory 117 (step S1006).

[0261] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating that it is the front door frame 14 are stored, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operation hole 33, and the second operation hole 34 that occurred in the situation where the front door frame 14 is in an open state is calculated (step S1007). The period between the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating that it is the front door frame 14 are stored is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire pointer information with consecutive numbers, if there are multiple sections between the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored and the history information storage area 125 in which the correspondence relationship information and end information indicating that it is the front door frame 14 are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored, but the correspondence relationship information and start information indicating that it is the front door frame 14 are not stored in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored, all the history information in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence relationship information and start information indicating that it is the front door frame 14 are stored is treated as if the front door frame 14 is in an open state.

[0262] After that, various parameters are calculated using the calculation results of steps S1002 to S1007 (step S1008). Specifically, first, the number of balls that entered the gate while the front door frame 14 was open, calculated in step S1007, is subtracted from the number of balls that entered the gate calculated in steps S1002 to S1006. Then, the following parameters are calculated using the number of balls entered after the subtraction. The difference between the number of balls entering the out port 24a calculated in step S1007 and the number of balls entering the port 24a calculated in step S1002 is designated as the number of balls entering the port 24a, the difference between the number of balls entering the port 24a calculated in step S1007 and the number of balls entering the port 24a calculated in step S1002 is designated as the number of balls entering the port 24a, the difference between the number of balls entering the port 24a calculated in step S1002 and the number of balls entering the port 24a calculated in step S1007 is designated as the number of balls entering the port 24a, the difference between the number of balls entering the port 24a calculated in step S1002 and the number of balls entering the port 24a calculated in step S1002 .... First parameter: Total number of game balls dispensed (K2 x "Number of prize balls for winning at the general winning port 31" + K3 x "Number of prize balls for winning at the special winning device 32" + K4 x "Number of prize balls for winning at the first operating port 33" + K5 x "Number of prize balls for winning at the second operating port 34") / Total number of game balls discharged from the skill area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio will be referred to as "D1") Second parameter: The ratio of the total number of game balls entering the general winning port 31 (K2) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) Third parameter: the ratio of the total number of game balls entering the special electric winning device 32 (K3) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) Fourth parameter: the ratio of the total number of game balls entering the first operating port 33 (K4) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) (hereinafter, this ratio will be referred to as "D2") Fifth parameter: the ratio of the total number of game balls entering the second operating port 34 (K5) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) (hereinafter, this ratio will be referred to as "D3") 6th parameter: D1-(D2 x "number of winning balls for winning into the first operating port 33" + D3 x "number of winning balls for winning into the second operating port 34") Seventh parameter: (K3 x "number of prize balls for winning the special electric winning device 32" + K5 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special electric winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") ratio 8th parameter: K3 x "number of prize balls for winning the special electric winning device 32" / total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special electric winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") ratio Thereafter, the oldest RTC information and the newest RTC information in the history area 124 of the history memory 117 are used to calculate the total time required until all the history information currently being calculated is extracted (step S1009). Then, a first output process is executed (step S1010). In the first output process, all the history information stored in the history area 124 of the history memory 117 is output to the reading terminal 102 in sequence. Also, the various parameters calculated in step S1008 are output to the reading terminal 102 in sequence, and the total time calculated in step S1009 is output to the reading terminal 102. As a result, the information to be output in the first output process is read by a reading device electrically connected to the reading terminal 102.

[0263] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the correspondence relationship information and start information indicating the open / close execution mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the open / close execution mode are stored, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operation hole 33, and the second operation hole 34 that occurred in the open / close execution mode is calculated (step S1011). The period between the history information storage area 125 in which the correspondence relationship information and start information indicating the open / close execution mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the open / close execution mode are stored is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire pointer information with consecutive numbers, if there are multiple sections between the history information storage area 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored and the history information storage area 125 in which the correspondence relationship information and end information indicating the opening and closing execution mode are stored, the total number of balls entered for each section is calculated. In addition, if there is a history information storage area 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored, but the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 is stored does not store the correspondence relationship information and start information indicating the opening and closing execution mode, all the history information in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence relationship information and start information indicating the opening and closing execution mode are stored is treated as being in the opening and closing execution mode.

[0264] After that, during the period of the opening / closing execution mode specified in step S1011, the number of balls that entered each of the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state is calculated (step S1012). The method of calculating the number of balls is the same as in step S1007, except that it is based on the period of the opening / closing execution mode specified in step S1011.

[0265] After that, various parameters are calculated using the results of the calculations in steps S1011 and S1012 (step S1013). Specifically, first, the number of balls that entered the front door frame 14 while it was open, calculated in step S1012, is subtracted from the number of balls that entered the front door frame 14 calculated in step S1011. Then, the following parameters are calculated using the number of balls entered after the subtraction. The difference between the number of balls entered the out exit 24a calculated in step S1011 and the number of balls entered the out exit 24a calculated in step S1012 is set as the number of balls entered K11, the difference between the number of balls entered the general winning opening 31 calculated in step S1011 and the number of balls entered the general winning opening 31 calculated in step S1012 is set as the number of balls entered K12, and the difference between the number of balls entered the special winning device 32 calculated in step S1011 and the number of balls entered K13 is set as the number of balls entered K14. The difference between the number of balls that enter the special electric winning device 32 calculated in step S1012 is designated as the number of entering balls K13, the difference between the number of balls that enter the first operating port 33 calculated in step S1011 and the number of balls that enter the first operating port 33 calculated in step S1012 is designated as the number of entering balls K14, and the difference between the number of balls that enter the second operating port 34 calculated in step S1011 and the number of balls that enter the second operating port 34 calculated in step S1012 is designated as the number of entering balls K15. 11th parameter: total number of game balls dispensed (K12 x "number of prize balls for winning at the general winning port 31" + K13 x "number of prize balls for winning at the special winning device 32" + K14 x "number of prize balls for winning at the first operating port 33" + K15 x "number of prize balls for winning at the second operating port 34") / total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) ratio (hereinafter, this ratio will be referred to as "D11") 12th parameter: The ratio of the total number of game balls entering the general winning port 31 (K12) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 13th parameter: the ratio of the total number of game balls entering the special electric winning device 32 (K13) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 14th parameter: the ratio of the total number of game balls entering the first operating port 33 (K14) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) (hereinafter, this ratio will be referred to as "D12") 15th parameter: the ratio of the total number of game balls entering the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) (hereinafter, this ratio will be referred to as "D13") 16th parameter: D11-(D12 x "number of winning balls for winning into the first operating port 33" + D13 x "number of winning balls for winning into the second operating port 34") 17th parameter: (K13 x "number of prize balls for winning the special electric winning device 32" + K15 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K12 x "number of prize balls for winning the general winning port 31" + K13 x "number of prize balls for winning the special electric winning device 32" + K14 x "number of prize balls for winning the first operating port 33" + K15 x "number of prize balls for winning the second operating port 34") ratio 18th parameter: K13 x "number of prize balls for winning the special electric winning device 32" / total number of game balls paid out (K12 x "number of prize balls for winning the general winning port 31" + K13 x "number of prize balls for winning the special electric winning device 32" + K14 x "number of prize balls for winning the first operating port 33" + K15 x "number of prize balls for winning the second operating port 34") ratio Thereafter, a second output process is executed (step S1014). In the second output process, the various parameters calculated in step S1013 are sequentially output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads each piece of information to be output in the second output process.

[0266] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the high-frequency support mode are stored, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operation hole 33, and the second operation hole 34 that occurred in the high-frequency support mode is calculated (step S1015). The period between the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence relationship information and end information indicating the high-frequency support mode are stored is calculated from the RTC information stored in these history information storage areas 125. In addition, in the entire pointer information with consecutive numbers, when there are multiple sections between the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored and the history information storage area 125 in which the correspondence relationship information and end information indicating the high-frequency support mode are stored, the total number of balls entered for each section is calculated. In addition, when the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored exists but the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 is stored does not store the correspondence relationship information and start information indicating the high-frequency support mode, all the history information in the history information storage area 125 in which the RTC information corresponding to a time later than the history information storage area 125 in which the correspondence relationship information and start information indicating the high-frequency support mode are stored is treated as being in the high-frequency support mode.

[0267] Thereafter, the number of balls that entered each of the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34 while the front door frame 14 was in the open state during the period of the high frequency support mode specified in step S1015 is calculated (step S1016). The method of calculating the number of balls is the same as that in step S1007, except that the period of the high frequency support mode specified in step S1015 is the premise.

[0268] After that, various parameters are calculated using the results of the calculations in steps S1015 and S1016 (step S1017). Specifically, first, the number of balls that entered the front door frame 14 while it was open, calculated in step S1016, is subtracted from the number of balls that entered the front door frame 14 calculated in step S1015. Then, the following parameters are calculated using the number of balls entered after the subtraction. The difference between the number of balls entered the out exit 24a calculated in step S1015 and the number of balls entered the out exit 24a calculated in step S1016 is set as the number of balls entered K21, the difference between the number of balls entered the general winning opening 31 calculated in step S1015 and the number of balls entered the general winning opening 31 calculated in step S1016 is set as the number of balls entered K22, and the difference between the number of balls entered the special winning device 32 calculated in step S1015 and the number of balls entered the special winning device 32 calculated in step S1015 is set as the number of balls entered K23. The difference in the number of balls that enter the special electric winning device 32 calculated in step S1016 is designated as the number of entering balls K23, the difference between the number of balls that enter the first operating port 33 calculated in step S1015 and the number of balls that enter the first operating port 33 calculated in step S1016 is designated as the number of entering balls K24, and the difference between the number of balls that enter the second operating port 34 calculated in step S1015 and the number of balls that enter the second operating port 34 calculated in step S1016 is designated as the number of entering balls K25. 21st parameter: Total number of game balls dispensed (K22 x "Number of prize balls for winning at the general winning port 31" + K23 x "Number of prize balls for winning at the special winning device 32" + K24 x "Number of prize balls for winning at the first operating port 33" + K25 x "Number of prize balls for winning at the second operating port 34") / Total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) ratio (hereinafter, this ratio will be referred to as "D11") 22nd parameter: The ratio of the total number of game balls entering the general winning port 31 (K22) to the total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) 23rd parameter: The ratio of the total number of game balls entering the special electric winning device 32 (K23) to the total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) 24th parameter: the ratio of the total number of game balls entering the first operating port 33 (K24) to the total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) (hereinafter, this ratio will be referred to as "D22") 25th parameter: The ratio of the total number of game balls entering the second operating port 34 (K25) to the total number of game balls discharged from the game area PA (K21+K22+K23+K24+K25) (hereinafter, this ratio will be referred to as "D23") 26th parameter: D21-(D22 x "Number of winning balls for winning into the first operating port 33" + D23 x "Number of winning balls for winning into the second operating port 34") Thereafter, a third output process is executed (step S1018). In the third output process, the various parameters calculated in step S1017 are output in sequence to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads each piece of information that was the target of output in the third output process. Thereafter, a clear process is executed (step S1019). In the clear process, the history information storage area 125 of the history memory 117 is cleared to all "0", and the pointer area 126 is cleared to "0". As a result, the history area 124 is initialized.

[0269] According to the present embodiment described above in detail, the following excellent effects are obtained.

[0270] When a game ball enters any of the general winning opening 31, the special winning device 32, the first operating opening 33, and the second operating opening 34, the game ball is paid out, so the player plays the game while hoping that the game ball will enter any of these ball entry sections. In this configuration, when a game ball enters any of the out opening 24a, the general winning opening 31, the special winning device 32, the first operating opening 33, and the second operating opening 34 (hereinafter also referred to as the history target ball entry section), the corresponding history information is stored in the history memory 117 of the management IC 66. This makes it possible to store and hold information for managing the number of game balls entering each history target ball entry section or the ball entry frequency in the pachinko machine 10, and by using this managed information, it becomes possible to appropriately manage the ball entry mode of each history target ball entry section. In addition, since the history information is stored and held in the pachinko machine 10 itself, it becomes possible to prevent unauthorized access to and unauthorized modification of the history information.

[0271] All ball entry sections that eject game balls from the game area PA are subject to execution of the history information storage process and are subject to management using the history information. This makes it possible to manage the frequency of ball entry for any history target ball entry section using the history information. It also makes it possible to manage the ratio of the number of balls that enter each history target ball entry section to the number of game balls that are ejected from the game area PA using the history information.

[0272] The history information includes RTC information, which is information corresponding to the timing of the ball entering the history target ball entry part that triggered the storage of the history information. By using the history information, it is possible to grasp the details of the ball entry history into the history target ball entry part.

[0273] The history memory 117 stores not only history information corresponding to game balls entering the history target ball entry portion, but also history information indicating whether the opening / closing execution mode is in effect, history information indicating whether the high frequency support mode is in effect, and history information indicating whether the front door frame 14 is open or not. This makes it possible to distinguish between these situations and manage the manner in which game balls enter the history target ball entry portion.

[0274] The history information stored in the history memory 117 can be output to a reading device, which is a device outside the pachinko machine 10. This makes it possible to read the history information with the reading device and use the read history information to analyze the manner in which game balls enter the history target ball entry portion.

[0275] The MPU 62 is provided with a read terminal 102, and a reading device electrically connected to the read terminal 102 can read out the program from the main ROM 64. This makes it possible to check whether the program is normal or not. In this configuration, the read terminal 102 for externally outputting the program is used to externally output the history information stored in the history memory 117. This makes it possible to externally output the history information while preventing the configuration from becoming complicated.

[0276] It is determined whether the information to be output from the read terminal 102 is a program or history information, and the information corresponding to the determination result is output to the outside through the read terminal 102. As a result, in a configuration in which history information is output to the outside using the read terminal 102 for externally outputting a program, the pachinko machine 10 determines whether the information to be output to the outside is a program or history information, and outputs the determined information to the outside. Therefore, even in a configuration in which the read terminal 102 is used for both purposes, it is possible to read out only the necessary information.

[0277] Based on information received from a reading device electrically connected to the reading terminal 102, it is specified whether the information to be output from the reading terminal 102 is the program or the history information. This makes it possible to prevent the configuration for selecting the information to be output to the outside from becoming complicated.

[0278] An MPU 62 having a main ROM 64 for storing a program in advance has a management IC 66 and a read terminal 102. This makes it possible to consolidate the signal path to the read terminal 102 within the MPU 62. This makes it possible to achieve the excellent effects already described while making it difficult to make unauthorized access to the signal path to the read terminal 102.

[0279] A management CPU 112 is provided in addition to the main CPU 63 which executes a process for dispensing game balls based on the game balls entering any one of the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34, and the management CPU 112 executes a process for storing history information in the history memory 117. This makes it possible to manage the entry patterns of game balls into each history target ball entry port while preventing the processing load of the main CPU 63 from increasing excessively.

[0280] The master CPU 63 and the control CPU 112 are provided on the same chip as the MPU 62. This makes it possible to prevent unauthorized access to the communication path between the master CPU 63 and the control CPU 112.

[0281] The main CPU 63 transmits information corresponding to the detection results of each of the entrance ball detection sensors 42a-48a to each of the buffers 122a-122g of the input port 121 of the management IC 66, using the signal paths corresponding to each of the entrance ball detection sensors 42a-48a. This results in a correspondence between the type of information transmitted from the main CPU 63 and each of the buffers 122a-122g (i.e., each signal path), making it possible to simplify the configuration for distinguishing each type of information in the management CPU 112.

[0282] The main CPU 63 transmits information corresponding to whether the mode is in the open / close execution mode, information corresponding to whether the mode is in the high frequency support mode, and information corresponding to whether the front door frame 14 is open to each of the buffers 122h-122j of the input port 121 of the management IC 66, using a signal path corresponding to each of these conditions. This allows the type of information corresponding to each of these conditions to correspond to each of the buffers 122h-122j (i.e., each signal path), making it possible to simplify the configuration for distinguishing each type of information in the management CPU 112.

[0283] The master CPU 63 transmits correspondence information indicating which type of information each of the buffers 122a-122j (i.e., each of the signal paths 118a-118j) corresponds to to the management CPU 112. This eliminates the need to store the correspondence information in advance in the management IC 66. This makes it possible to improve the versatility of the management IC 66.

[0284] When the supply of operating power to the master CPU 63 is started, the master CPU 63 transmits correspondence information to the management IC 66. This makes it possible for the management IC 66 to specify the correspondence between the information transmitted from the master CPU 63 and the history target ball entry part in a situation where a game ball may enter the history target ball entry part.

[0285] The correspondence information is transmitted from the main CPU 63 to the management IC 66 using the signal paths 118a to 118g for transmitting information indicating whether or not a game ball has entered the history target entry portion. This makes it possible to simplify the communication configuration compared to a configuration in which a dedicated signal path is provided for transmitting the correspondence information.

[0286] The management IC 66 is provided with a correspondence memory 116, and the correspondence information transmitted from the main CPU 63 to the management IC 66 is stored in the correspondence memory 116. This eliminates the need to provide information that enables the management IC 66 to identify the history target goal location corresponding to the information to be transmitted every time the main CPU 63 transmits information on the detection results of each goal detection sensor 42a-48a. This makes it possible to reduce the amount of information on the detection results of each goal detection sensor 42a-48a transmitted from the main CPU 63.

[0287] When the output state of the output instruction signal output from the main CPU 63 to the management IC 66 switches from LOW level to HI level, information is output from the management IC 66 to the read terminal 102. In this case, the management CPU 112 can specify that the signal path corresponding to the 16th buffer 122p corresponds to the output instruction signal without receiving the correspondence information from the main CPU 63. This makes it possible to prevent the configuration for transmitting the correspondence information from becoming extremely complicated.

[0288] The management IC 66 is provided with buffers 122a-122p capable of receiving information from the master CPU 63, the number of which is greater than the number of types of information that need to be transmitted from the master CPU 63 to the management IC 66. This makes it possible to accommodate an increase or decrease in the number of types of information depending on the model of the pachinko machine 10 without changing the configuration related to the buffers 122a-122p. This makes it possible to increase the versatility of the management IC 66.

[0289] When history information is transmitted from the management IC 66 to the reading terminal 102, the history information includes correspondence information indicating the type of history target ball entry portion that corresponds to the history information. This makes it possible to identify the manner in which game balls enter each history target ball entry portion by using the read history information.

[0290] In the management IC 66, various parameters (parameters 1-8, 11-18, and 21-26) corresponding to the ball entry patterns of the game balls in the game area PA during a predetermined period are calculated by using the history information stored in the history memory 117. This makes it possible to output various parameters, which are the results of calculations using the history information, to the outside.

[0291] Various parameters are calculated with the history information corresponding to the state where the front door frame 14 is open excluded. This makes it possible to derive various parameters in the normal state where the front door frame 14 is closed. Also, various parameters corresponding to the state where the opening and closing execution mode is in effect and the state where the high frequency support mode is in effect are calculated. This makes it possible for the manager of the game hall to grasp the manner in which game balls enter the game machine according to each state.

[0292] When various parameters have been calculated, a process of clearing history memory 117 is executed to initialize history memory 117. This makes it possible to prevent the occurrence of an event in which history information that would normally be stored and held is erased by overwriting, as the amount of history information to be stored in history memory 117 exceeds the storage capacity of history memory 117.

[0293] When various parameters are output to the read terminal 102, the history information stored in the history memory 117 is also output to the read terminal 102. This makes it possible to refer to not only the various parameters but also the history information that is the basis for the calculation of the various parameters when reading out various parameters to analyze the manner in which the game ball enters the game area PA.

[0294] The control CPU 112 calculates various parameters when a reading device is electrically connected to the reading terminal 102. This makes it possible to reduce the frequency of calculating various parameters.

[0295] When the main CPU 63 specifies that a reading device is electrically connected to the reading terminal 102 and the main CPU 63 transmits output instruction information, various parameters are calculated in the management IC 66, and the various parameters resulting from the calculation are output to the reading terminal 102. This makes it possible to output various parameters to a reading device outside the pachinko machine 10 based on instructions from the main CPU 63.

[0296] In the process executed by the main CPU 63 when the supply of operating power is started, it is determined whether or not a reading device is electrically connected to the reading terminal 102, and when it is determined that the reading device is electrically connected, output instruction information is transmitted from the main CPU 63 to the management IC 66. As a result, in a situation where the process when the supply of operating power is started is being executed by the main CPU 63, i.e., in a situation before the main CPU 63 starts normal processing for progressing the game, the calculation of various parameters and the external output of the various parameters of the calculation results are completed. Therefore, it is possible to prevent the calculation of various parameters and the external output of the calculation results from being performed in a situation where a game ball may enter the history target ball entry section, and it is possible to reduce the processing load of the management IC 66.

[0297] In a configuration in which when a game ball enters the first actuation port 33 or the second actuation port 34, a corresponding external output is made through the external terminal board 97, and history information is stored in the history memory 117. This makes it possible to simply grasp the number and frequency of game balls that enter the first actuation port 33 or the second actuation port 34 by using the information outputted to the outside through the external terminal board 97, while accurately grasping the number and frequency of game balls that enter the history target ball entry portion by using the history information stored in the history memory 117.

[0298] <Second embodiment> In this embodiment, among the first to sixteenth buffers 122a to 122p of the input port 121 in the management I / F 111, the type of buffer in which the type of input signal is determined at the design stage of the management IC 66 is different from that of the first embodiment. Also, the processing configuration executed by the main CPU 63 to cause the management CPU 112 to identify the type of input signal is different from that of the first embodiment. The configurations different from the first embodiment will be described below. Note that the description of the same configurations as those in the first embodiment will basically be omitted.

[0299] FIG. 25 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111 in this embodiment.

[0300] The first to seventh buffers 122a to 122g and the sixteenth buffer 122p receive the same types of signals as those in the first embodiment. In detail, a first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a, a second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b, a third signal corresponding to the detection result of the third winning port detection sensor 44a is input to the third buffer 122c, a fourth signal corresponding to the detection result of the special electric detection sensor 45a is input to the fourth buffer 122d, a fifth signal corresponding to the detection result of the first operating port detection sensor 46a is input to the fifth buffer 122e, a sixth signal corresponding to the detection result of the second operating port detection sensor 47a is input to the sixth buffer 122f, a seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g, and an output instruction signal is input to the sixteenth buffer 122p.

[0301] On the other hand, in the first embodiment, the signal corresponding to the opening / closing execution mode is input to the eighth buffer 122h as the eighth signal, the signal corresponding to the high-frequency support mode is input to the ninth buffer 122i as the ninth signal, and the signal corresponding to the front door frame 14 is input to the tenth buffer 122j as the tenth signal, but in this embodiment, the buffers to which these signals are input are different. Specifically, the signal corresponding to the opening / closing execution mode is input to the thirteenth buffer 122m as an opening / closing execution mode signal, the signal corresponding to the high-frequency support mode is input to the fourteenth buffer 122n as a high-frequency support mode signal, and the signal corresponding to the front door frame 14 is input to the fifteenth buffer 122o as a door open signal.

[0302] It is determined in the design stage of the management IC 66 that the open / close execution mode signal is input to the 13th buffer 122m, the high frequency support mode signal is input to the 14th buffer 122n, the door open signal is input to the 15th buffer 122o, and the output instruction signal is input to the 16th buffer 122p, and the management side CPU 112 can specify that the above-mentioned signals corresponding to the 13th to 16th buffers 122m to 122p are input without receiving an instruction from the main side CPU 63. On the other hand, it is not determined in the design stage of the management IC 66 what kind of signals are input to the first to 12th buffers 122a to 122l, and the types of these signals are specified by the management side CPU 112 upon receiving an instruction from the main side CPU 63. The process for specifying the type of signal is executed when the supply of operating power to the main side CPU 63 and the management side CPU 112 is started, as in the first embodiment.

[0303] Fig. 26 is a flowchart showing the recognition process of this embodiment executed by the main CPU 63. Note that the recognition process is executed in step S110 in the main process (Fig. 7) in the same manner as in the first embodiment.

[0304] First, the recognition output counter in the main RAM 65 is set to "12", which is the number of the first to twelfth buffers 122a to 122l to be recognized as signal types (step S1101). Then, output processing of the recognition start signal is executed (step S1102). In this output processing, the output states of the first signal input to the first buffer 122a, the open / close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to HI level, thereby starting output of the recognition start signal. The period during which these signals are maintained at HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

[0305] Thereafter, information on the number of outputs corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64, and the read information on the number of outputs is set in the output counter provided in the main RAM 65 (step S1103). The output counter is a counter for the main CPU 63 to specify the number of times the type identification signal has been output.

[0306] In this embodiment, when the type of signal input to the first buffer 122a to the twelfth buffer 122l is recognized by the management CPU 112, the type identification signal is output the same number of times as the number of prize balls set for the ball entry section corresponding to the type of signal. The management CPU 112 stores information corresponding to the number of times the type identification signal has been received for each of the first buffer 122a to the twelfth buffer 122l in the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116. In other words, the type of signal input to the first buffer 122a to the twelfth buffer 122l is understood as the number of prize balls set for the ball entry section corresponding to the type of signal.

[0307] In step S1103, if the value of the output counter for recognition is any of "12", "11" and "10", the output counter is set to "10" corresponding to the number of prize balls in the general winning port 31. If the value of the output counter for recognition is "9", the output counter is set to "15" corresponding to the number of prize balls in the special winning device 32. If the value of the output counter for recognition is "8", the output counter is set to "1" corresponding to the number of prize balls in the first operating port 33. If the value of the output counter for recognition is "7", the output counter is set to "1" corresponding to the number of prize balls in the second operating port 34. If the value of the output counter for recognition is "6", the output counter is set to "0" since the output counter corresponds to the outlet 24a but the payout of the game balls is not executed even if the game ball enters the outlet 24a. Also, when the value of the recognition output counter is any one of "5" to "1", there is no corresponding ball entry section and it is blank, so the output number counter is set to "0".

[0308] Then, output processing of the start trigger signal is executed (step S1104). In this output processing, the output state of the first signal input to the first buffer 122a is set to a HI level, thereby starting output of the start trigger signal. The period during which the first signal is maintained at the HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the first signal.

[0309] Thereafter, on condition that the value of the output count counter in the main RAM 65 is not "0" (step S1105: YES), that is, on condition that a value of 1 or more has been set in the output count counter in step S1103, the process proceeds to step S1106. In step S1106, output processing of a type identification signal is executed. In this output processing, the output state of the second signal input to the second buffer 122b is set to a HI level, thereby starting output of the type identification signal. The period during which the second signal is maintained at a HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the second signal.

[0310] Thereafter, the value of the output counter in the main RAM 65 is decremented by 1 (step S1107), and it is determined whether the value of the output counter after decrementing by 1 is "0" (step S1108). If the value of the output counter is 1 or more (step S1108: NO), the process returns to step S1106.

[0311] If the determination in step S1105 is affirmative, or if the determination in step S1108 is affirmative, output processing of the end trigger signal is executed (step S1109). In this output processing, the output state of the third signal input to the third buffer 122c is set to a HI level, thereby starting output of the end trigger signal. The period during which the third signal is maintained at the HI level is set to a period sufficient for the management CPU 112 to recognize the output state of the third signal.

[0312] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S1110), and it is determined whether the value of the recognition output counter after decrement is "0" (step S1111). If the value of the recognition output counter is 1 or more (step S1111: NO), the process returns to step S1103, and a process is executed to recognize the type of signal corresponding to the value of the recognition output counter after decrement.

[0313] On the other hand, if the value of the recognition output counter is "0" (step S1111: YES), output processing of the recognition end signal is executed (step S1112). In this output processing, the output states of the third signal input to the third buffer 122c, the open / close execution mode signal input to the thirteenth buffer 122m, and the high frequency support mode signal input to the fourteenth buffer 122n are set to HI level, thereby starting output of the recognition end signal. The period during which these signals are maintained at HI level is set to a period sufficient for the management CPU 112 to recognize the output states of these signals.

[0314] Next, the management process in this embodiment executed by the management CPU 112 will be described with reference to the flowchart in Fig. 27. The management process starts when the supply of operating power to the management CPU 112 starts, similarly to the first embodiment.

[0315] When reception of the identification start signal from the main CPU 63 has ended (step S1201: YES), the value of the counter to be set in the management RAM 114 is cleared to "0" (step S1202). Thereafter, on the condition that a start trigger signal has been received from the main CPU 63 (step S1203: YES), the process proceeds to step S1204. In step S1204, it is determined whether or not a type identification signal has been received from the main CPU 63. When a type identification signal has been received (step S1204: YES), the value of a reception count counter provided in the management RAM 114 is incremented by 1 (step S1205). The reception count counter is a counter for specifying the number of times the type identification signal has been received from the main CPU 63 by the management CPU 112. The value of the reception count counter is cleared to "0" when an affirmative determination is made in step S1203.

[0316] If a negative determination is made in step S1204, or if the process of step S1205 is executed, it is determined whether or not a termination trigger signal has been received from the main CPU 63 (step S1206). If a termination trigger signal has not been received (step S1206: NO), the process returns to step S1204, and if a termination trigger signal has been received (step S1206: YES), a correspondence setting process is executed (step S1207). In the correspondence setting process, the value set in the reception count counter is stored in the correspondence area corresponding to the current value of the setting target counter in the management RAM 114, among the first to twelfth correspondence areas 123a to 123l of the correspondence memory 116. In this case, the first correspondence area 123a, the second correspondence area 123b, and the third correspondence area 123c are set to "10" corresponding to the number of prize balls in the general winning port 31, the fourth correspondence area 123d is set to "15" corresponding to the number of prize balls in the special winning device 32, the fifth correspondence area 123e is set to "1" corresponding to the number of prize balls in the first operating port 33, and the sixth correspondence area 123f is set to "1" corresponding to the number of prize balls in the second operating port 34. Also, "0" is set in the seventh to twelfth correspondence areas 123g to 123l. After that, the value of the setting target counter in the management side RAM 114 is incremented by 1 (step S1208).

[0317] If a negative determination is made in step S1203, or if the process of step S1208 is executed, it is determined whether or not reception of the identification end signal from the main CPU 63 has ended (step S1209). If reception of the identification end signal has not ended (step S1209: NO), the process returns to step S1203, and executes the processes of step S1204 and thereafter on the condition that a start trigger signal is received from the main CPU 63 (step S1203: YES). If reception of the identification end signal from the main CPU 63 has ended (step S1209: YES), the history setting process of step S1210 and the external output process of step S1211 are repeatedly executed.

[0318] FIG. 28 is a time chart showing how information on the correspondence between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l is stored in the correspondence memory 116. In FIG. Figure 28(a) shows a period when the output state of the first signal is at HI level, Figure 28(b) shows a period when the output state of the second signal is at HI level, Figure 28(c) shows a period when the output state of the third signal is at HI level, Figure 28(d) shows a period when the output state of the open / close execution mode signal is at HI level, Figure 28(e) shows a period when the output state of the high frequency support mode signal is at HI level, Figure 28(f) shows an execution period of an identification state in which processing is executed to identify the correspondence between the first to twelfth buffers 122a to 122l and the types of signals input to these buffers 122a to 122l, Figure 28(g) shows the timing when the value of the reception count counter of the management side RAM 114 is incremented by 1, and Figure 28(h) shows the timing when the correspondence setting processing (step S1207) is executed by the management side CPU 112.

[0319] As a result of the start of supply of operating power to the main CPU 63 and the control CPU 112, at the timing of t1, the output states of the first signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from LOW level to HI level as shown in Figs. 28(a), 28(d), and 28(e). As a result, the output of the identification start signal from the main CPU 63 to the control CPU 112 is started. Thereafter, at the timing of t2, the output states of the first signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from HI level to LOW level. As a result, the output of the identification start signal from the main CPU 63 to the control CPU 112 is stopped. At the timing of t2, the control CPU 112 makes a positive determination in step S1201 of the management process (Fig. 27), and enters the identification state as shown in Fig. 28(f).

[0320] Thereafter, the output state of the first signal is maintained at HI level from time t3 to time t4 as shown in Fig. 28(a). As a result, a start trigger signal is output to the control CPU 112. Then, the output state of the second signal is maintained at HI level from time t5 to time t7 as shown in Fig. 28(b). As a result, a type identification signal is output once to the control CPU 112. In this case, at time t6, the value of the reception counter in the control RAM 114 is incremented by 1 as shown in Fig. 28(g).

[0321] Thereafter, the output state of the third signal is maintained at HI level from timing t8 to timing t10 ​​as shown in Fig. 28(c). This results in a state in which a termination trigger signal is output to the control CPU 112. In this case, at timing t9, the control CPU 112 executes a correspondence setting process as shown in Fig. 28(h). Since the value of the reception count counter is "1" at the timing when the correspondence setting process is executed, information of "1" is stored as the correspondence information in the correspondence areas 123a to 123l to be set this time in the correspondence memory 116.

[0322] After that, the output state of the first signal is maintained at HI level from time t11 to time t12 as shown in FIG. 28(a). This results in a state in which a start trigger signal is output to the control CPU 112. Then, the output state of the second signal is maintained at HI level from time t13 to time t15, from time t16 to time t18, from time t19 to time t21, and from time t22 to time t24 as shown in FIG. 28(b). This results in a state in which a type identification signal is output once to the control CPU 112. In this case, the value of the reception counter of the control RAM 114 is incremented by 1 at each of times t14, t17, t20, and t23 as shown in FIG. 28(g).

[0323] Thereafter, the output state of the third signal is maintained at HI level from timing t25 to timing t27 as shown in Fig. 28(c). This results in a state in which a termination trigger signal is output to the control CPU 112. In this case, at timing t26, as shown in Fig. 28(h), the control CPU 112 executes a correspondence setting process. Since the value of the reception count counter is "10" at the timing when the correspondence setting process is executed, information of "10" is stored as the correspondence information in the correspondence areas 123a to 123l to be set this time in the correspondence memory 116.

[0324] After that, at the timing of t28, as shown in Fig. 28(c), Fig. 28(d), and Fig. 28(e), the output states of the third signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from LOW level to HI level. This starts the output of the identification end signal from the main CPU 63 to the control CPU 112. After that, at the timing of t29, the output states of the third signal, the open / close execution mode signal, and the high-frequency support mode signal are changed from HI level to LOW level. This stops the output of the identification end signal from the main CPU 63 to the control CPU 112. At the timing of t29, the control CPU 112 makes an affirmative determination in step S1209 of the control process (Fig. 27), and the identification state is released as shown in Fig. 28(f).

[0325] In this embodiment, since the information on the number of prize balls is stored as the correspondence information, the history information stored in the history memory 117 includes the information on the number of prize balls corresponding to the ball entry part that triggered the storage of the history information as the correspondence information. In this configuration, if there are multiple ball entry parts with the same number of prize balls, the ball entry parts cannot be distinguished in the history information. Specifically, since the first actuation port 33 and the second actuation port 34 each have one prize ball, the first actuation port 33 and the second actuation port 34 cannot be distinguished in the history information. In such a situation, the number of prize balls in the first actuation port 33 and the second actuation port 34 may be made different. As a result, even in a configuration in which history information is stored as in the second embodiment, it is possible to distinguish the first actuation port 33 and the second actuation port 34 in the history information.

[0326] In this embodiment, in step S801 of the history setting process, the confirmation target counter in the management RAM 114 is set to "15." As a result, all of the first to fifteenth buffers 122a to 122o become confirmation targets.

[0327] According to the embodiment described above in detail, not only the output instruction signal, but also the information corresponding to whether the opening / closing execution mode is in progress, the information corresponding to whether the high frequency support mode is in progress, and the information corresponding to whether the front door frame 14 is in progress can be specified by the management side CPU112 as the signal path corresponding to these information without receiving the correspondence information from the main side CPU63. In this case, only the information corresponding to the detection result of each ball entrance detection sensor 42a-48a is the information that the main side CPU63 needs to make the management side CPU112 recognize the correspondence between each information and each signal path 118a-118g. Then, when the correspondence information is made to the management side CPU112, the pulse signal of the same number as the number of winning balls corresponding to each ball entrance detection sensor 42a-48a is output from the main side CPU63 to the management side CPU112 using the second signal. This makes it possible to simplify the configuration related to the transmission of the correspondence information.

[0328] <Third embodiment> In this embodiment, the trigger for executing calculations of various parameters using history information is different from that of the first embodiment. The following describes the configuration that is different from the first embodiment. Note that the description of the same configuration as the first embodiment is basically omitted.

[0329] 29 is a block diagram for explaining the electrical configuration of the management IC 66 in this embodiment. As in the first embodiment, the management IC 66 is provided with a management I / F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, and a history memory 117. These functions are the same as in the first embodiment.

[0330] In addition to the above, the management IC 66 is also provided with a calculation result memory 131. In this embodiment, as will be described later in detail, when a calculation trigger occurs, various parameters are calculated in the management side CPU 112 using the history information stored in the history memory 117 at that time. The calculated various parameters are then sequentially stored in the calculation result memory 131. The various parameters stored in the calculation result memory 131 are output to a reading device electrically connected to the reading terminal 102.

[0331] The timing for calculating various parameters occurs before the reading device is electrically connected to the reading terminal 102. This makes it possible to differentiate the timing for calculating various parameters from the timing for externally outputting the parameters to the reading device, thereby distributing the processing load.

[0332] In addition, by providing a calculation result memory 131 for storing the calculation results of various parameters, it is possible to store not only various parameters for one calculation trigger, but various parameters for multiple calculation triggers collectively, thereby shortening the time required to calculate various parameters at each calculation trigger.

[0333] FIG. 30 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111 in this embodiment.

[0334] The first to tenth buffers 122a to 122j and the sixteenth buffer 122p are input with the same types of signals as in the first embodiment. In detail, the first buffer 122a receives a first signal corresponding to the detection result of the first winning hole detection sensor 42a, the second buffer 122b receives a second signal corresponding to the detection result of the second winning hole detection sensor 43a, the third buffer 122c receives a third signal corresponding to the detection result of the third winning hole detection sensor 44a, the fourth buffer 122d receives a fourth signal corresponding to the detection result of the special electric detection sensor 45a, and the fifth buffer 122e receives a fifth signal corresponding to the detection result of the first operation hole detection sensor 46a. A signal corresponding to the detection result of the second operating port detection sensor 47a is input to the sixth buffer 122f, a sixth signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g, a signal corresponding to the opening / closing execution mode is input to the eighth buffer 122h, a signal corresponding to the high frequency support mode is input to the ninth buffer 122i, a signal corresponding to the front door frame 14 is input to the tenth buffer 122j, and an output instruction signal is input to the sixteenth buffer 122p.

[0335] In this embodiment, in addition to the various signals described above, a calculation instruction signal is input to the fifteenth buffer 122o. The calculation instruction signal is a signal output from the main CPU 63 to provide the management CPU 112 with a calculation opportunity for various parameters. The input of the calculation instruction signal to the fifteenth buffer 122o is determined in the design stage of the management IC 66, as is the input of the output instruction signal to the sixteenth buffer 122p, and the management CPU 112 can specify that the above-mentioned respective signals corresponding to the fifteenth to sixteenth buffers 122o to 122p are input without receiving an instruction from the main CPU 63. On the other hand, what types of signals are input to the first to fourteenth buffers 122a to 122n are not determined in the design stage of the management IC 66, and the types of these signals are specified by the management CPU 112 upon receiving an instruction from the main CPU 63. The process for specifying the type of signal is executed when the supply of operating power to the main CPU 63 and the management CPU 112 is started, as in the first embodiment.

[0336] Next, a process configuration for causing the management CPU 112 to calculate various parameters in response to the occurrence of a calculation trigger will be described. Fig. 31 is a flowchart showing the power failure information storage process executed by the main CPU 63. The power failure information storage process is executed in step S201 in the timer interrupt process (Fig. 8).

[0337] In the power failure information storage process, when a power failure signal corresponding to the occurrence of a power interruption is received from the power failure monitoring board 67 (step S1301: YES), output process of a calculation instruction signal is executed (step S1302). In this output process, the output state of the calculation instruction signal input to the 15th buffer 122o in the input port 121 of the management side I / F 111 is maintained at HI level for a specific period. This specific period is a period sufficient for the management side CPU 112 to recognize that the output state of the calculation instruction signal is at HI level. After that, after executing the power failure process in step S1303, an infinite loop is executed, and the supply of operating power to the main side CPU 63 is waited for completely stopped. In the power failure process, the power failure flag of the main side RAM 65 is set to "1", and the checksum is calculated and the calculated checksum is saved.

[0338] Fig. 32 is a flowchart showing the power failure response process executed by the management CPU 112. The power failure response process is configured to be executed after the external output process in the management process (Fig. 18), and after receiving an identification end command from the main CPU 63 (step S606: YES) in the management process, the history setting process in step S607, the external output process in step S608, and the power failure response process are repeatedly executed in this order.

[0339] In the power failure response process, when the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1401: YES), in steps S1402 to S1406, the number of balls that have entered each of the outlet 24a, the general winning port 31, the special winning device 32, the first operating port 33, and the second operating port 34 is calculated, similar to steps S1002 to S1006 of the external output process (Fig. 24) in the first embodiment described above. Also, in step S1407, the number of balls that have entered each type while the front door frame 14 is open is calculated, similar to step S1007 of the external output process (Fig. 24) in the first embodiment described above. In step S1408, various parameters are calculated in the same manner as in step S1008 of the external output process (FIG. 24) in the first embodiment, and in step S1409, the total time is calculated in the same manner as in step S1009 of the external output process (FIG. 24) in the first embodiment. Then, the calculation result information in step S1408 and the calculation result information in step S1409 are written to the calculation result memory 131 (step S1410). In this case, if other calculation result information is already stored in the calculation result memory 131, the calculation result information is written so as not to overwrite the already stored calculation result information. In addition, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to specify the timing to which the calculation result information written this time corresponds.

[0340] Then, in step S1411, the number of balls entering during the opening / closing execution mode is calculated in the same manner as step S1011 of the external output processing (FIG. 24) in the first embodiment described above, and in step S1412, the number of balls entering during the opening / closing execution mode when the front door frame 14 is open is calculated in the same manner as step S1012 of the external output processing (FIG. 24) in the first embodiment described above. Also, in step S1413, various parameters are calculated in the same manner as step S1013 of the external output processing (FIG. 24) in the first embodiment described above. Then, the information of the calculation result in step S1414 is written to the calculation result memory 131 (step S1414). In this case, the calculation result information is written so as not to overwrite other calculation result information already stored in the calculation result memory 131. Also, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to specify the timing to which the information on the currently written calculation result corresponds.

[0341] Then, in step S1415, the number of balls in the high-frequency support mode is calculated in the same manner as step S1015 of the external output process (FIG. 24) in the first embodiment, and in step S1416, the number of balls in the high-frequency support mode when the front door frame 14 is open is calculated in the same manner as step S1016 of the external output process (FIG. 24) in the first embodiment. In addition, in step S1417, various parameters are calculated in the same manner as step S1017 of the external output process (FIG. 24) in the first embodiment. Then, the information of the calculation result in step S1417 is written to the calculation result memory 131 (step S1418). In this case, the calculation result information is written so as not to overwrite other calculation result information already stored in the calculation result memory 131. In addition, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to identify the timing to which the information on the calculation result written this time corresponds. After that, an infinite loop is entered, and the control CPU 112 waits until the supply of operating power to the control CPU 112 is completely stopped.

[0342] Fig. 33 is a flowchart showing the external output process executed by the management CPU 112. The external output process is executed in step S608 of the management process (Fig. 18).

[0343] When the output state of the output instruction signal from the main CPU 63 becomes HI level (step S1501: YES), an output process of the calculation result is executed (step S1502). In this output process, various calculation results stored in the calculation result memory 131 are output to the reading terminal 102. As a result, the reading device electrically connected to the reading terminal 102 reads various calculation results stored in the calculation result memory 131. In this case, when only various calculation results corresponding to one occurrence of a calculation trigger are stored in the calculation result memory 131, only the various calculation results corresponding to the one occurrence of the calculation trigger are read in the reading device, and when various calculation results corresponding to multiple occurrences of the calculation trigger are stored in the calculation result memory 131, the various calculation results corresponding to the multiple occurrences of the calculation trigger are read in the reading device.

[0344] Thereafter, output processing of the history information is executed (step S1503). In this output processing, all the history information stored in the history area 124 of the history memory 117 is output in sequence to the reading terminal 102. As a result, the various pieces of history information stored in the history area 124 are read by the reading device electrically connected to the reading terminal 102. By outputting not only the various calculation results but also the history information in this way, it becomes possible for the worker using the reading device to perform a detailed analysis of the various calculation results.

[0345] Thereafter, a clearing process is executed (step S1504). In the clearing process, all of the history information storage area 125 in the history memory 117 are cleared to "0", and the pointer area 126 is cleared to "0". As a result, the history area 124 is initialized. Also, in the clearing process, all of the areas in the calculation result memory 131 are cleared to "0". As a result, the calculation result memory 131 is initialized.

[0346] According to the present embodiment described above in detail, the following excellent effects are obtained.

[0347] When the supply of operating power to the main CPU 63 is stopped, various parameters are calculated by the control CPU 112. This makes it possible to manage various parameters on a business day basis.

[0348] When the main CPU 63 determines that the supply of operating power is to be stopped, the output state of the calculation instruction signal is changed to HI level, whereby various parameters are calculated by the control CPU 112. This makes it possible for the control CPU 112 to calculate various parameters based on instructions from the main CPU 63.

[0349] Various parameters calculated by the management CPU 112 are written in sequence to the calculation result memory 131. This makes it possible to accumulate various parameters in the management IC 66, and when reading the various parameters with a reader, it becomes possible to read out various parameters for multiple business days all at once.

[0350] When various parameters are written to the calculation result memory 131, information that enables identification of the time when the various parameters were calculated is attached to the various parameters and written to the calculation result memory 131. This makes it possible to analyze various parameter information while knowing the time when the various parameters were calculated.

[0351] Note that the history memory 117 may be configured to be cleared to "0" when a calculation trigger occurs and the calculation results of various parameters for that trigger are written to the calculation result memory 131. This makes it less likely that new history information will be written to the history memory 117 when the upper limit of history information that can be stored has already been stored in the history memory 117.

[0352] Also, the information to be output to the reading device may be only the information of various parameters stored in the calculation result memory 131, and the history information stored in the history memory 117 may not be output to the outside. This makes it possible to reduce the amount of information to be output to the outside.

[0353] <Fourth embodiment> In this embodiment, the processing configuration of the power failure response processing executed by the management side CPU 112 is different from that of the third embodiment. The configuration different from the third embodiment will be described below. Note that the description of the same configuration as the third embodiment will basically be omitted.

[0354] FIG. 34 is a flowchart showing the power failure response process executed by the control CPU 112 in this embodiment.

[0355] When the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1601: YES), various calculation processes are executed (step S1602). In the various calculation processes, the processes of steps S1402 to S1409, steps S1411 to S1413, and steps S1415 to S1417 of the power failure response process (FIG. 32) in the third embodiment are executed.

[0356] Thereafter, it is determined whether or not a specific parameter among the various parameters calculated in step S1602 is within a reference range (step S1603). Seventh parameter: (K3 x "number of prize balls for winning the special electric winning device 32" + K5 x "number of prize balls for winning the second operating port 34") / total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special electric winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") ratio 8th parameter: K3 x "number of prize balls for winning the special electric winning device 32" / total number of game balls paid out (K2 x "number of prize balls for winning the general winning port 31" + K3 x "number of prize balls for winning the special electric winning device 32" + K4 x "number of prize balls for winning the first operating port 33" + K5 x "number of prize balls for winning the second operating port 34") ratio These two parameters are set as parameters to be judged as to whether they are within the reference range. If the value of the seventh parameter is 0.7 or less and the value of the eighth parameter is 0.6 or less, it is determined that the predetermined parameters are within the reference range and a positive judgment is made in step S1603.

[0357] The predetermined parameters are not limited to the seventh and eighth parameters, and other parameters may be set as the predetermined parameters instead of or in addition to the seventh and eighth parameters. For example, Second parameter: The ratio of the total number of game balls entering the general winning port 31 (K2) to the total number of game balls discharged from the game area PA (K1+K2+K3+K4+K5) may be set as the predetermined parameter. In this case, for example, when the value of the second parameter is equal to or greater than 0.1 and equal to or less than 0.2, the predetermined parameter may be determined to be within the reference range. Also, only the predetermined parameters to be determined in step S1603 may be calculated in the various calculation processes in step S1602.

[0358] If the predetermined parameters are not within the reference range (step S1603: NO), the various parameters calculated in step S1602 are written to the calculation result memory 131 (step S1604). In this case, if other calculation result information is already stored in the calculation result memory 131, the calculation result information is written so as not to overwrite the already stored calculation result information. In addition, the current date information and time information are read from the RTC 115, and the read date information and time information are attached to the calculation result information written this time. This makes it possible to identify the timing to which the calculation result information written this time corresponds.

[0359] On the other hand, if the predetermined parameter is within the reference range (step S1603: YES), the process of step S1604 is not executed. As a result, only the various parameters when the predetermined parameter is not within the reference range are written to the calculation result memory 131. Therefore, when an abnormal situation occurs, the history of the abnormal situation is left in the calculation result memory 131, and the storage capacity required for the calculation result memory 131 can be reduced.

[0360] If a positive determination is made in step S1603, or if the process of step S1604 is executed, a clear process of the history memory 117 is executed (step S1605). In this clear process, the history information storage area 125 of the history memory 117 is cleared to all "0", and the pointer area 126 is cleared to "0". This causes the history area 124 to be initialized. After the process of step S1605 is executed, an infinite loop is entered, and the process waits until the supply of operating power to the control side CPU 112 is completely stopped.

[0361] According to the present embodiment described above in detail, it is determined whether the contents of the various calculated parameters are within a reference range, and only the various parameters determined not to be within the reference range are written to the calculation result memory 131. This makes it possible to reduce the amount of various parameters to be stored in the calculation result memory 131, and therefore the storage capacity required for the calculation result memory 131.

[0362] <Fifth embodiment> In this embodiment, the contents of the calculation trigger that causes the management side CPU 112 to calculate various parameters are different from those of the third embodiment. The following describes the configuration that is different from the third embodiment. Note that the description of the same configuration as the third embodiment is basically omitted.

[0363] Fig. 35(a) is a flowchart showing the trigger identification process executed by the main CPU 63. Note that the trigger identification process is executed as a process when a positive determination is made in step S712 in the management output process (Fig. 20).

[0364] It is determined whether or not a game ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 (step S1701). If a positive determination is made in step S1701, an increment process of the ball entry counter provided in the main RAM 65 is executed (step S1702). In the increment process, the number of game balls that have entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is determined based on the number of times step S705 has been executed in the management output process (FIG. 20) of the current processing round. Then, the determined number of game balls is added to the ball entry counter.

[0365] Then, it is determined whether the value of the ball entry counter is equal to or greater than the trigger reference number of "500" (step S1703). If it is equal to or greater than "500" (step S1703: YES), a subtraction process is executed on the ball entry counter in the main RAM 65 (step S1704). In this subtraction process, the value of the ball entry counter is subtracted by "500". Then, an output process of a calculation instruction signal is executed (step S1705). In this output process, the output state of the calculation instruction signal input to the 15th buffer 122o in the input port 121 of the management side I / F 111 is maintained at a HI level for a specific period of time. This specific period is sufficient for the management side CPU 112 to recognize that the output state of the calculation instruction signal is at a HI level.

[0366] Fig. 35(b) is a flowchart showing the calculation process executed by the management CPU 112. The calculation process is executed in place of the power failure response process in the third embodiment. Therefore, the calculation process is configured to be executed after the external output process in the management process (Fig. 18), and after receiving an identification end command from the main CPU 63 (step S606: YES) in the management process, the history setting process in step S607, the external output process in step S608, and the calculation process are repeatedly executed in this order.

[0367] When the output state of the calculation instruction signal received from the main CPU 63 becomes HI level (step S1801: YES), various calculation processes are executed (step S1802). In the various calculation processes, the same processes as steps S1402 to S1418 of the power failure response process (FIG. 32) in the third embodiment are executed.

[0368] According to the embodiment described above in detail, each time the total number of game balls discharged from the game area PA becomes equal to or exceeds the trigger reference number, various parameters are calculated by the management CPU 112. In this case, since various parameters are calculated each time a calculation trigger occurs, which occurs repeatedly while the main CPU 63 is supplied with operating power, it becomes possible to precisely manage the ball entry state of the game balls in the game area PA within a business day.

[0369] In addition, since the various parameters are calculated based on whether the total number of game balls discharged from the game area PA is equal to or greater than the trigger reference number, the various parameters are calculated on the condition that the game is being played. This makes it possible to prevent the various parameters from being calculated meaninglessly when the game is not being played continuously.

[0370] Sixth embodiment In this embodiment, the contents of the calculation trigger that causes the management side CPU 112 to calculate various parameters are different from those of the fifth embodiment. The following describes the configuration that is different from the fifth embodiment. Note that the description of the same configuration as the fifth embodiment is basically omitted.

[0371] Fig. 36 is a flowchart showing the trigger identification process executed by the main CPU 63. Note that the trigger identification process is executed when a positive determination is made in step S712 in the management output process (Fig. 20).

[0372] It is determined whether or not a game ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 (step S1901). If a negative determination is made in step S1901, the value of a continuation counter provided in the main RAM 65 is incremented by 1 (step S1902). The continuation counter is a counter for the main CPU 63 to identify the period during which a state in which no game ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 continues.

[0373] If the value of the continuation counter after the increment is equal to or greater than the stop reference value (step S1903: YES), the time measurement flag provided in the main RAM 65 is cleared to "0" (step S1904). The stop reference value is set so that a positive judgment is made in step S1903 when a state in which no game ball enters any of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, and the second operating hole 34 continues for 5 seconds. The time measurement flag is a flag for the main CPU 63 to specify whether or not to measure the time to specify the timing to switch the output state of the calculation instruction signal to the HI level, and if the value of the time measurement flag is "0", the time measurement is not made, and if the value of the time measurement flag is "1", the time measurement is made. If a positive judgment is made in step S1901, the time measurement flag is set to "1" (step S1905).

[0374] If a negative determination is made in step S1903, if the process of step S1904 is executed, or if the process of step S1905 is executed, then on condition that the time measurement flag in the main RAM 65 is set to "1" (step S1906: YES), the value of a measurement counter provided in the main RAM 65 is incremented by 1 (step S1907). The measurement counter is a counter used for measuring the time required to determine the timing for switching the output state of the calculation instruction signal to the HI level.

[0375] It is determined whether the value of the measurement counter after incrementing by 1 is equal to or greater than the indication reference value (step S1908). The indication reference value is set so that a positive determination is made in step S1908 when the time measured by the measurement counter reaches 10 hours. If a positive determination is made in step S1908, the value of the measurement counter is cleared to "0" (step S1909), and output processing of a calculation instruction signal is executed (step S1910). In this output processing, the output state of the calculation instruction signal input to the 15th buffer 122o in the input port 121 of the management side I / F 111 is maintained at a HI level for a specific period of time. This specific period is a period sufficient for the management side CPU 112 to recognize that the output state of the calculation instruction signal is at a HI level.

[0376] According to the embodiment described above in detail, since various parameters are calculated every time a predetermined period has elapsed, it is possible to easily adjust the calculation frequency of various parameters by simply adjusting the predetermined period. In this case, when a game is not being played, the measurement of the predetermined period is stopped, and when a game round is started, the measurement of the predetermined period is resumed from the state before the stop. This makes it possible to exclude a situation where a game is not being played from the calculation of various parameters, and it is possible to appropriately derive various parameters when a game is being played.

[0377] Incidentally, instead of using a measurement counter to measure whether or not a predetermined period of time has elapsed, the RTC 115 may be used to measure the same.

[0378] <Seventh embodiment> In this embodiment, the contents of the calculation trigger that causes the control CPU 112 to calculate various parameters are different from those in the first embodiment,...

Claims

[Claim 1] A predetermined storage execution means for causing storage of information corresponding to a predetermined event occurring as a result of a game to be executed in a predetermined storage means, thereby causing the predetermined information to be stored in the predetermined storage means; an information calculation means for calculating behavior information corresponding to a game result during a predetermined period of time using the predetermined information each time a predetermined calculation trigger occurs; a result storage and execution means for sequentially storing the aspect information obtained by the calculation by the information calculation means in a calculation result storage means; Equipped with the result storage execution means includes means for causing the behavior information to be stored among the behavior information obtained by the calculation by the information calculation means to be stored in the calculation result storage means; The aspect information obtained by the calculation by the information calculation means and which is not to be stored is not stored in the calculation result storage means, This gaming machine is A means for generating a specific advantageous period when a specific opportunity occurs; a notification means capable of notifying the user of the content corresponding to the aspect information stored in the calculation result storage means; Equipped with A gaming machine characterized in that the information calculation means calculates the status information corresponding to the result of the game during the specified period by using the specified information during the specific advantageous period.

Images