Pachinko machine

Abstract

To provide a game machine capable of suitably outputting a signal externally.SOLUTION: When setting change operation is performed in the case that supply of operation power is started, processing for changing set value is performed. When the processing for changing set value is started, first RAM clear processing is performed; when processing for changing set value is terminated, second RAM clear processing is performed. Also, an output start timing of a security signal is generated when the processing for changing set value is started, and the output start timing of the security signal is also generated when the processing for changing set value is terminated. When the output start timing of the security signal is generated, the security signal is outputted externally for an output continuous period; when the output start timing is generated in situations where the security signal is externally outputted, the output continuous period is reset.SELECTED DRAWING: Figure 6

Description

[Technical field]

[0001] The present invention relates to a gaming machine. [Background technology]

[0002] Pachinko machines and slot machines are known as gaming machines. For example, a pachinko machine has a tray storage section on the front of the machine for storing game balls given to a player, and the game balls stored in the tray storage section are guided to a game ball launching device and launched toward a game area in response to a launching operation by the player. Then, for example, when a game ball enters a ball entry section provided in the game area, the game ball is paid out from a payout device to the tray storage section. In addition, a configuration in which an upper tray storage section and a lower tray storage section are provided as the tray storage section is also known in pachinko machines, and in this case, the game balls stored in the upper tray storage section are guided to the game ball launching device, and the game balls that are surplus in the upper tray storage section are discharged to the lower tray storage section (see, for example, Patent Document 1).

[0003] In addition, in a slot machine, when a start lever is operated to start a new game while medals have been bet, a lottery process is executed by the control means. When the lottery process is executed, the control means executes a rotation start control to start the rotation of the reels, and when a stop button is operated during the rotation of the reels, the control means executes a rotation stop control to stop the rotation of the reels. Then, if the stop result after the rotation of the reels has stopped corresponds to a winning combination in the lottery process, a bonus corresponding to the winning combination is awarded to the player. [Prior art documents] [Patent documents]

[0004] [Patent Document 1] JP 2013-106772 A Summary of the Invention [Problem to be solved by the invention]

[0005] Here, in gaming machines such as those exemplified above, it is necessary to perform suitable display control of the information display means, and there is still room for improvement in this regard.

[0006] The present invention has been made in consideration of the above-mentioned circumstances, and has an object to provide a gaming machine capable of suitably controlling the display of an information display means. [Means for solving the problem]

[0007] In order to solve the above problem, the invention described in claim 1 comprises: a history storage execution means for executing a history storage process for storing history information of a game corresponding to a game ball flowing down a game area between a door body and a game board and entering a predetermined ball entry means; information derivation means for executing a predetermined derivation process for deriving aspect information corresponding to a game result by utilizing the history information stored in the history storage means; A behavior information storage means capable of storing a plurality of pieces of behavior information derived at different timings by the information derivation means; a shift control means for executing a shift process for shifting the aspect information among a plurality of storage areas in the aspect information storage means, based on the occurrence of a predetermined trigger, so that the plurality of aspect information are stored in the aspect information storage means in a manner corresponding to the order derived by the information derivation means; a display control means for controlling the information display means so that displays corresponding to each of the plurality of pieces of the aspect information stored in the aspect information storage means are sequentially executed; A means for restricting execution of a predetermined process for playing a game in a predetermined situation; Equipped with The history storage execution means is configured to store, in the history storage means, history information corresponding to a game ball entering the predetermined ball entry means, regardless of whether the door body is in a closed state or an open state, The aspect information display control means a specific event response means for changing the information display means to a specific event response state based on the occurrence of a specific event; a predetermined display control means for controlling the information display means to display a predetermined display until a specific situation occurs after the manufacture of the gaming machine; Equipped with The history storage execution means includes a means for executing the history storage process even in the restricted state, The shift control means includes a means for executing the shift processing even in the restricted state, The predetermined display control means is characterized by comprising a means for terminating the predetermined display when the specific situation occurs even in the restricted situation. Effect of the Invention

[0008] According to the present invention, it is possible to preferably control the display of the information display means. [Brief description of the drawings]

[0009] [Figure 1] 1 is a perspective view showing a pachinko machine according to a first embodiment. [Diagram 2] 1 is an exploded perspective view showing the main components of a pachinko machine. [Diagram 3] FIG. 2 is a front view showing the configuration of the game board. [Figure 4] An explanatory diagram to explain the configuration regarding the discharge of game balls that have flowed down the game area. [Diagram 5] FIG. [Figure 6] FIG. 2 is a block diagram showing the electrical configuration of the pachinko machine. [Figure 7] FIG. 13 is an explanatory diagram for explaining the contents of various counters used in lotteries, etc. [Figure 8] 4 is an explanatory diagram for explaining various tables stored in a main ROM. FIG. [Figure 9] 4 is a flowchart showing a main process executed by a main CPU. [Figure 10] 13 is a flowchart showing a setting value update process executed by a main CPU. [Figure 11] 13 is a flowchart showing a timer interrupt process executed by a main CPU. [Figure 12] 13 is a flowchart showing the special chart special power control processing executed by the main CPU. [Figure 13] This is a flowchart showing the special chart change start processing executed by the main CPU. [Figure 14] This is an explanatory diagram to explain the configuration in which the detection results of the ball entry detection sensor are input to the main CPU. [Figure 15] This is a flowchart showing the ball entry detection processing executed by the main CPU. [Figure 16] A block diagram to explain the electrical configuration of a dispensing control device and various devices that communicate with the dispensing control device. [Figure 17] 13 is a flowchart showing the timer interrupt processing executed by the dispensing CPU. [Figure 18] FIG. 2 is a block diagram for explaining an electrical configuration of a management IC. [Figure 19] FIG. 2 is an explanatory diagram for explaining the configuration of an input port of a management side I / F; [Figure 20] FIG. 2 is an explanatory diagram for explaining a configuration of a correspondence relationship memory; [Figure 21] FIG. 2 is an explanatory diagram for explaining a configuration of a history memory; [Figure 22] 13 is a flowchart showing a recognition process executed by a main CPU. [Diagram 23] 13 is a flowchart showing a management process executed by a management CPU. [Figure 24] 13(a) to 13(d) are time charts showing how information on the correspondence between the first to fifteenth buffers and the types of signals is stored in a correspondence memory. [Diagram 25] 13 is a flowchart showing a management output process executed by a main CPU. [Figure 26]13 is a flowchart showing a history setting process executed by a management CPU. [Figure 27] 13(a) to 13(e) are time charts showing how history information is stored in a history memory. [Figure 28] 13 is a flowchart showing a process of outputting a setting value update signal executed by a main CPU. [Figure 29] 13 is a flowchart showing a setting update recognition process executed by a management CPU. [Diagram 30] 13 is a flowchart showing a display output process executed by a management CPU. [Diagram 31] 13 is a flowchart showing a display process executed by a management CPU. [Diagram 32] 13A is a flowchart showing a data output process executed by a main CPU, and FIG. 13B is a flowchart showing an external output process executed by a control CPU. [Diagram 33] FIG. 11 is an explanatory diagram for explaining various tables stored in a main ROM in the second embodiment. [Diagram 34] FIG. 13 is an explanatory diagram for explaining the configuration of a separate storage memory in the third embodiment. [Diagram 35] 13 is a flowchart showing a setting update recognition process executed by a management CPU. [Diagram 36] 13 is a flowchart showing a process of monitoring a repeated change executed by a management CPU. [Figure 37] 13 is a flowchart showing a process of monitoring a repeated change executed by a master CPU in the fourth embodiment. [Figure 38] 13 is a flowchart showing a setting update recognition process executed by a management CPU in the fifth embodiment. [Figure 39] FIG. 23 is an explanatory diagram for explaining the configuration of a history memory in the sixth embodiment. [Diagram 40] 13 is a flowchart showing a history setting process executed by a management CPU. [Diagram 41]13 is a flowchart showing a setting update recognition process executed by a management CPU. [Diagram 42] FIG. 23 is an explanatory diagram for explaining the configuration of a history memory in the seventh embodiment. [Diagram 43] 13 is a flowchart showing a setting update recognition process executed by a management CPU. [Diagram 44] FIG. 23 is an explanatory diagram for explaining the configuration of a history memory in the eighth embodiment. [Diagram 45] 13 is a flowchart showing a setting update recognition process executed by a management CPU. [Figure 46] 13 is a flowchart showing a history setting process executed by a management CPU. [Figure 47] 13 is a flowchart showing a display output process executed by a management CPU. [Figure 48] FIG. 23 is an explanatory diagram for explaining the configuration of an input port of a management side I / F in the ninth embodiment. [Figure 49] 13 is a flowchart showing a recognition process executed by a main CPU. [Figure 50] 13 is a flowchart showing a management process executed by a management CPU. [Figure 51] 13(a) to 13(h) are time charts showing how information on the correspondence between the first to twelfth buffers and the types of signals is stored in a correspondence memory. [Figure 52] A block diagram to explain the configuration of the signal path that transmits the detection results of each ball entry detection sensor to the main CPU and management IC in the 10th embodiment. [Figure 53] A front view of the main control device in the 11th embodiment. [Figure 54] FIG. 4 is a block diagram for explaining an electrical configuration for performing various displays in the first to fourth notification display devices under the control of an MPU. [Figure 55] 13 is a flowchart showing a display process executed by a management CPU. [Figure 56]13 is a flowchart showing a setting value update process executed by a main CPU. [Figure 57] (a) is an explanatory diagram for explaining the display modes of the first to fourth notification display devices when the game history management results are displayed, and (b) is an explanatory diagram for explaining the display modes of the first to fourth notification display devices when the setting state of the pachinko machine is changed. [Figure 58] 13(a) to 13(h) are time charts showing how the first to fourth notification display devices are put into display states. [Figure 59] FIG. 23A is an explanatory diagram for explaining the configuration of a first notification display device in a twelfth embodiment, and FIG. 23B is an explanatory diagram for explaining the configuration of a second notification display device. [Figure 60] This is an explanatory diagram for explaining the display contents of the first alert display device and the second alert display device when the first to fourth alert display devices display the results of game history management and when they display that the setting state of the pachinko machine is in a changeable state in which it is possible to change the setting state. [Figure 61] 13 is a flowchart showing a setting value update process executed by a main CPU. [Figure 62] FIG. 23 is an explanatory diagram for explaining the configuration of an abnormality display area in the thirteenth embodiment. [Figure 63] 13 is a flowchart showing an abnormality setting process executed by a main CPU. [Figure 64] 13 is a flowchart showing an abnormality display process executed by a main CPU. [Figure 65] 23 is a flowchart showing a management output process executed by a main CPU in the fourteenth embodiment. [Figure 66] 13 is a flowchart showing a main process executed by a main CPU in another embodiment. [Figure 67] FIG. 23 is an explanatory diagram for explaining the setting manner of programs and data in a main ROM in the fifteenth embodiment. [Figure 68] FIG. 2 is an explanatory diagram for explaining a setting mode of each area in the main RAM. [Figure 69] 13 is a flowchart showing a timer interrupt process executed by a main CPU. [Figure 70] 13 is a flowchart showing a management process executed by a main CPU. [Figure 71] 13 is a flowchart showing a management execution process executed by a main CPU. [Figure 72] 11 is an explanatory diagram for explaining various areas of a work area for non-specific control used for managing game history. FIG. [Figure 73] 13 is a flowchart showing a check process executed by a main CPU. [Figure 74] This is a flowchart showing the normal goal entry management processing executed by the main CPU. [Figure 75] 13 is a flowchart showing a result calculation process executed by a main CPU. [Figure 76] 13 is a flowchart showing a display process executed by a main CPU. [Figure 77] 23 is a flowchart showing a management process executed by a main CPU in the sixteenth embodiment. [Figure 78] 23 is a flowchart showing a management execution process executed by a main CPU in the seventeenth embodiment. [Figure 79] 23 is a flowchart showing a management execution process executed by a main CPU in the eighteenth embodiment. [Figure 80] 23 is a flowchart showing a management execution process executed by a main CPU in the nineteenth embodiment. [Figure 81] 13 is a flowchart showing a management process executed by a main CPU in the twentieth embodiment. [Figure 82] 13 is a flowchart showing a management execution process executed by a main CPU. [Figure 83] FIG. 23 is an explanatory diagram for explaining the electrical configuration in the twenty-first embodiment. [Figure 84]23 is a flowchart showing a main process executed by a main CPU in the 22nd embodiment. [Figure 85] 13 is a flowchart showing a setting value update process executed by a main CPU. [Figure 86] 13 is a flowchart showing a timer interrupt process executed by a main CPU. [Figure 87] 13 is a flowchart showing a setting confirmation process executed by a main CPU. [Figure 88] 13 is a flowchart showing a RAM monitoring process executed by a main CPU. [Figure 89] 13 is a flowchart showing a main process executed by a main CPU in another embodiment. [Figure 90] 13 is a flowchart showing a setting value update process executed by a main CPU in another embodiment. [Figure 91] 23 is a flowchart showing a main process executed by a main CPU in the 23rd embodiment. [Figure 92] 23 is a flowchart showing a RAM monitoring process executed by a main CPU in the 24th embodiment. [Figure 93] 25 is a flowchart showing a RAM monitoring process executed by a main CPU in the twenty-fifth embodiment. [Figure 94] 13 is a flowchart showing a management execution process executed by a main CPU. [Figure 95] 13 is a flowchart showing another monitoring process executed by a main CPU. [Figure 96] 26 is a flowchart showing a management process executed by a main CPU in the 26th embodiment. [Figure 97] 27 is a flowchart showing a management process executed by a main CPU in the 27th embodiment. [Figure 98] 23 is a flowchart showing the management process executed by the main CPU in the 28th embodiment. [Figure 99]29 is a flowchart showing a management process executed by a main CPU in the twenty-ninth embodiment. [Figure 100] 13 is a flowchart showing a main process executed by a main CPU in the 30th embodiment. [Figure 101] 13 is a flowchart showing a power outage information storage process executed by a main CPU. [Figure 102] FIG. 1A is a block diagram for explaining the configuration of an MPU, and FIG. 1B is a time chart showing the output of a reset signal by a reset signal output unit. [Figure 103] 13 is a flowchart showing a timer interrupt process executed by a main CPU. [Figure 104] 13 is a flowchart showing a setting monitoring process executed by a main CPU. [Figure 105] 13 is a flowchart showing a management process executed by a main CPU. [Fig. 106] 13 is a flowchart showing a management execution process executed by a main CPU. [Figure 107] 13 is a flowchart showing another monitoring process executed by a main CPU. [Figure 108] 13 is a flowchart showing a main process executed by a main CPU in the thirty-first embodiment. [Fig. 109] 13 is a flowchart showing a clearing process executed by a main CPU when an abnormality occurs. [Figure 110] 13 is a flowchart showing a clearing process for non-specific control executed by a main CPU. [Figure 111] 13 is a flowchart showing a power outage information storage process executed by a main CPU in the 32nd embodiment. [Figure 112] 13 is a flowchart showing a checksum monitoring process executed by a main CPU. [Figure 113] 13 is a flowchart showing a clearing process for non-specific control executed by a main CPU. [Fig. 114]33 is a flowchart showing a main process executed by a main CPU in the thirty-third embodiment. [Figure 115] 13 is a flowchart showing a setting confirmation process executed by a main CPU. [Fig. 116] 13 is a flowchart showing a setting value update process executed by a main CPU. [Figure 117] 13 is a flowchart showing a first timer interrupt process executed by a main CPU. [Fig. 118] 13 is a flowchart showing a setting monitoring process executed by a main CPU. [Figure 119] FIG. 2 is a block diagram for explaining a configuration for controlling the display of various display circuits by a main CPU. [Figure 120] FIG. 13A is an explanatory diagram for explaining various buffers provided in a work area for specific control, and FIG. 13B is an explanatory diagram for explaining various memory areas provided in a work area for non-specific control. [Figure 121] FIG. 2 is an explanatory diagram for explaining the electrical configuration of a display IC. [Figure 122] 13(a) to 13(g) are time charts showing how type data and display data are transmitted from the main CPU to the display IC and how the display data transmitted from the display IC is received by the first display circuit or the second display circuit. [Figure 123] 13 is a flowchart showing a second timer interrupt process executed by a main CPU. [Figure 124] (a) is an explanatory diagram for explaining the display contents of the first to fourth notification display devices in a situation where the setting value is updated, and (b) is an explanatory diagram for explaining the display contents of the first to fourth notification display devices in a situation where the setting value is confirmed. [Fig. 125] 33 is a flowchart showing a setting value update process executed by a main CPU in the thirty-fourth embodiment. [Fig. 126] FIG. 23 is an explanatory diagram for explaining the electrical configuration of a calculation result storage area in the thirty-fifth embodiment. [Figure 127]5(a) to 5(d) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. FIG. [Figure 128] 5(a) to 5(c) are explanatory diagrams for explaining the display contents of the first to fourth notification display devices. FIG. [Figure 129] 13(a) to 13(e) are time charts showing how base values ​​for various areas are notified by the first to fourth notification display devices. [Fig. 130] 13 is a flowchart showing a result calculation process executed by a main CPU. [Fig. 131] 13 is a flowchart showing a display process executed by a main CPU. [Fig. 132] 4 is a flowchart showing a main process executed by a main CPU. [Fig. 133] 13 is a flowchart showing a first timer interrupt process executed by a main CPU. [Fig. 134] 13 is a flowchart showing a second timer interrupt process executed by a main CPU. [Fig. 135] 13 is a flowchart showing a normal setting process executed by a main CPU. [Fig. 136] 13 is a flowchart showing a setting confirmation process executed by a main CPU. [Fig. 137] 13 is a flowchart showing a setting value update process executed by a main CPU. [Figure 138] 13(a) to 13(f) are time charts for explaining the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. [Figure 139] 13 is a flowchart showing a main process executed by a main CPU in the 36th embodiment. [Fig. 140] 37 is a flowchart showing a main process executed by a main CPU in the 37th embodiment. [Fig. 141] 38 is a flowchart showing a normal setting process executed by a main CPU in the thirty-eighth embodiment. [Fig. 142]16(a) to 16(d) are explanatory diagrams for explaining a setting corresponding storage area provided in a main ROM in the thirty-ninth embodiment. [Fig. 143] A flowchart showing the win / lose table reading process executed by the main CPU. [Fig. 144] 13 is a flowchart showing a setting process for a fifth display data buffer during setting update executed by a main CPU. [Fig. 145] 13(a) to 13(c) are explanatory diagrams for explaining a setting corresponding storage area provided in a main ROM in the fortieth embodiment. [Fig. 146] (a) An explanatory diagram for explaining various display sections provided in an area visible from the front of the pachinko machine through the window panel in the 41st embodiment, and (b) an explanatory diagram for explaining the display contents of the round display section. [Fig. 147] 13 is a flowchart showing a main process executed by the main CPU in the 42nd embodiment. [Fig. 148] 13 is a flowchart showing a first timer interrupt process executed by a main CPU. [Figure 149] 13 is a flowchart showing a result calculation process executed by a main CPU in the 43rd embodiment. [Fig. 150] 13 is a flowchart showing a display process executed by a main CPU. [Fig. 151] 13(a) to 13(g) are time charts showing how base values ​​for various areas are notified by the first to fourth notification display devices. [Fig. 152] 13(a) to 13(g) are time charts showing how base values ​​for various areas are notified by the first to fourth notification display devices in the forty-fourth embodiment. [Fig. 153] 13 is a flowchart showing a main process executed by the main CPU in the 45th embodiment. [Fig. 154] 11 is an explanatory diagram for explaining the contents of a storage area related to setting values ​​provided in a work area for specific control. FIG. [Fig. 155]13 is a flowchart showing a setting confirmation process executed by a main CPU. [Fig. 156] 13 is a flowchart showing a setting process for a fifth display data buffer during setting confirmation executed by a main CPU. [Fig. 157] 13 is a flowchart showing a setting value update process executed by a main CPU. [Fig. 158] 13 is a flowchart showing a setting process for a fifth display data buffer during setting update executed by a main CPU. [Fig. 159] FIG. 11 is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. [Fig. 160] 13A to 13E are time charts showing end timings of a setting value update process and a setting confirmation process in relation to the operation state of the setting key insertion section. [Fig. 161] 13 is a flowchart showing a main process executed by the main CPU in the 46th embodiment. [Fig. 162] FIG. 11 is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. [Fig. 163] This is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed in a situation where a setting value update processing or setting confirmation processing is being executed in the 47th embodiment. [Fig. 164] This is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed in a situation where a setting value update processing or setting confirmation processing is being executed in the 48th embodiment. [Fig. 165] 13 is a flowchart showing a main process executed by a main CPU in the 49th embodiment. [Fig. 166] 13 is a flowchart showing a setting confirmation process executed by a main CPU. [Fig. 167] 13 is a flowchart showing a setting value update process executed by a main CPU. [Fig. 168] 13(a) to 13(h) are time charts showing how first timer interrupt processing and second timer interrupt processing are permitted in a situation in which processing is being executed at the start of the supply of operating power. [Fig. 169] 13(a) to 13(g) are time charts showing how processing proceeds when an abnormality occurs in relation to the power outage flag, the checksum, or a setting value. [Fig. 170] 13(a) to 13(g) are time charts showing the display contents of the first to fourth notification display devices when the supply of operating power to the main CPU is started. [Fig. 171] FIG. 11 is an explanatory diagram for explaining the contents of the processing executed in the main processing when the supply of operating power is resumed after a power outage processing is executed while a setting value update processing or a setting confirmation processing is being executed. [Fig. 172] FIG. 2 is an explanatory diagram for explaining the electrical configuration of the audio and light emission control device. [Fig. 173] 13 is a flowchart showing the performance control process executed by the sound / light side CPU. [Fig. 174] 10 is an explanatory diagram for explaining the action corresponding to the content of the processing executed in the processing at the start of the supply of operating power in the main CPU. FIG. [Fig. 175] A flowchart showing the performance control processing executed by the sound and light side CPU in the 50th embodiment. [Fig. 176] 10 is an explanatory diagram for explaining the action corresponding to the content of the processing executed in the processing at the start of the supply of operating power in the main CPU. FIG. [Fig. 177] 13 is a flowchart showing a main process executed by the main CPU in the 51st embodiment. [Fig. 178] 13 is a flowchart showing a main process executed by the main CPU in the 52nd embodiment. [Fig. 179] 13 is a flowchart showing a main process executed by the main CPU in the 53rd embodiment. [Fig. 180] 13(a) to 13(g) are time charts showing the state of subsequent processing when the supply of operating power to the main CPU is stopped while a setting value update process is being executed. [Fig. 181] 13 is a flowchart showing a setting value update process executed by a main CPU. [Fig. 182] 11 is an explanatory diagram for explaining the contents of a memory area provided in a work area for specific control. FIG. [Fig. 183] 6A to 6F are time charts showing how setting values ​​to be updated are updated. [Fig. 184] 13 is a flowchart showing a main process executed by the main CPU in the 54th embodiment. [Fig. 185] 13 is a flowchart showing a main process executed by the main CPU in the 55th embodiment. [Fig. 186] FIG. 11 is an explanatory diagram for explaining areas to be cleared and areas not to be cleared that are set in a work area for specific control. [Fig. 187] 13 is a flowchart showing a display start process executed by a main CPU. [Fig. 188] 13 is a flowchart showing a second timer interrupt process executed by a main CPU. [Fig. 189] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation at the time when the supply of operating power begins. [Fig. 190] An explanatory diagram for explaining each area provided in the clear target area of ​​the work area for specific control in the 56th embodiment. [Fig. 191] 13 is a flowchart showing a display start process executed by a main CPU. [Fig. 192] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation at the time when the supply of operating power begins. [Fig. 193] 13 is a flowchart showing a display start process executed by the main CPU in the 57th embodiment. [Fig. 194] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation at the time when the supply of operating power begins. [Fig. 195] An explanatory diagram for explaining each area set in the clear target area and the clear non-target area of ​​the work area for specific control in the 58th embodiment. [Fig. 196] 13 is a flowchart showing a first timer interrupt process executed by a main CPU. [Figure 197] 13 is a flowchart showing a display start process executed by a main CPU. [Figure 198] (a) is an explanatory diagram for explaining the losing display lottery table for special drawings, and (b) is an explanatory diagram for explaining the losing display lottery table for regular drawings. [Figure 199] 13 is a flowchart showing a display start process executed by the main CPU in the fifty-ninth embodiment. [Figure 200] (a) is an explanatory diagram for explaining the initial display lottery table for special drawings, and (b) is an explanatory diagram for explaining the initial display lottery table for regular drawings. [Figure 201] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation at the time when the supply of operating power begins. [Fig. 202] 13 is a flowchart showing a display start process executed by a main CPU in the 60th embodiment. [Fig. 203] This is an explanatory diagram to explain the display contents of the special map display unit and the general map display unit corresponding to the situation at the time when the supply of operating power begins. [Fig. 204] 13 is a flowchart showing a display start process executed by a main CPU in the 61st embodiment. [Fig. 205] 13 is a flowchart showing a setting value update process executed by the main CPU in the 62nd embodiment. [Fig. 206]13 is a flowchart showing a display start process executed by a main CPU. [Fig. 207] (a) is an explanatory diagram for explaining the first display allocation table for special drawings, (b) is an explanatory diagram for explaining the second display allocation table for special drawings, (c) is an explanatory diagram for explaining the first display allocation table for regular drawings, and (d) is an explanatory diagram for explaining the second display allocation table for regular drawings. [Fig. 208] 13 is a flowchart showing a display start process executed by the main CPU in the 63rd embodiment. [Fig. 209] A front view of the game board in the 64th embodiment. [Fig. 210] FIG. 4A is a vertical cross-sectional view of the second actuating part in a non-guided state, and FIG. 4B is a vertical cross-sectional view of the second actuating part in a guiding state. [Fig. 211] 13A and 13B are explanatory diagrams for explaining the display contents of the pattern display device when a game round is being executed. [Fig. 212] 13(a) to (j) are explanatory diagrams for explaining the main patterns and sub-patterns which are variably displayed in each pattern row. [Fig. 213] A vertical cross-sectional view to explain the internal structure of the prize distribution device. [Fig. 214] 1 is an explanatory diagram for explaining the electrical configuration for performing various lotteries by the main CPU. FIG. [Fig. 215] (a) is an explanatory diagram for explaining the win / loss table of the first special chart, and (b) is an explanatory diagram for explaining the win / loss table of the second special chart. [Fig. 216] (a) is an explanatory diagram for explaining the type table for big wins, (b) is an explanatory diagram for explaining the contents of each of the multiple types of big win results, (c) is an explanatory diagram for explaining the type table for small wins, and (d) is an explanatory diagram for explaining the contents of each of the multiple types of small win results. [Fig. 217] 4 is a flowchart showing a normal power control process executed by the main CPU. [Fig. 218]13 is a flowchart showing the special chart special power control processing executed by the main CPU. [Fig. 219] This is a flowchart showing the special chart change start processing executed by the main CPU. [Fig. 220] This is a flowchart showing the processing during special chart determination executed by the main CPU. [Fig. 221] 13 is a flowchart showing an allocation process executed by a main CPU. [Fig. 222] 13 is a flowchart showing a special call termination process executed by the main CPU. [Fig. 223] FIG. 13 is an explanatory diagram for explaining each area provided in the clear target area of ​​the work area for specific control. [Fig. 224] 13 is a flowchart showing a second timer interrupt process executed by a main CPU. [Fig. 225] 13A is a flowchart showing the setting process for the first display data buffer during setting update executed by the main CPU, and FIG. 13B is a flowchart showing the setting process for the sixth display data buffer during setting confirmation executed by the main CPU. [Fig. 226] 13(a) to 13(g) are time charts showing how the display contents of the first special chart display section, the second special chart display section and the special display section change depending on the state of the pachinko machine. [Fig. 227] A flowchart showing the second timer interrupt processing executed by the main CPU in the 65th embodiment. [Fig. 228] A flowchart showing the second timer interrupt processing executed by the main CPU in the 66th embodiment. [Fig. 229] 13 is a flowchart showing a setting value update process executed by a main CPU. [Fig. 230] A flowchart showing the second timer interrupt processing executed by the main CPU in the 67th embodiment. [Fig. 231](a) An explanatory diagram for explaining the configuration of the special display unit in the 68th embodiment, and (b) a time chart showing the display contents of the 15R display unit, 6R display unit and small win display unit when the setting value update process or setting confirmation process is being executed. [Fig. 232] A front view of the game board in the 69th embodiment. [Fig. 233] 1 is an explanatory diagram for explaining the electrical configuration for performing various lotteries by the main CPU. FIG. [Fig. 234] (a) An explanatory diagram for explaining the first win / loss table at low probability, (b) an explanatory diagram for explaining the first win / loss table at high probability, (c) an explanatory diagram for explaining the second win / loss table at low probability, and (d) an explanatory diagram for explaining the second win / loss table at high probability. [Fig. 235] (a) is an explanatory diagram for explaining the type table, (b) is an explanatory diagram for explaining the contents of each of multiple types of jackpot results and the contents of one type of small jackpot result, and (c) is an explanatory diagram for explaining the contents of the support mode. [Fig. 236] FIG. 13 is an explanatory diagram for explaining the setting mode of the display duration of a game round. [Fig. 237] 11 is a flowchart showing a first special symbol special power control process executed by a main CPU. [Fig. 238] 13 is a flowchart showing a second special chart special power control process executed by the main CPU. [Fig. 239] This is a flowchart showing the special chart change start processing executed by the main CPU. [Fig. 240] This is a flowchart showing the processing during special chart determination executed by the main CPU. [Fig. 241] (a) An explanatory diagram for explaining the first win / loss table at low probability in the 70th embodiment, (b) an explanatory diagram for explaining the first win / loss table at high probability, (c) an explanatory diagram for explaining the second win / loss table at low probability, and (d) an explanatory diagram for explaining the second win / loss table at high probability. [Fig. 242](a) An explanatory diagram for explaining the first win / loss table at low probability in the 71st embodiment, (b) an explanatory diagram for explaining the first win / loss table at high probability, (c) an explanatory diagram for explaining the second win / loss table at low probability, and (d) an explanatory diagram for explaining the second win / loss table at high probability. [Fig. 243] A front view of the game board in the 72nd embodiment. [Fig. 244] 2 is an explanatory diagram for explaining the electrical configuration of the main control device and the audio and light emission control device. FIG. [Fig. 245] 4 is a flowchart showing a main process executed by a main CPU. [Fig. 246] 13 is a flowchart showing a setting confirmation process executed by a main CPU. [Fig. 247] 13 is a flowchart showing a setting value update process executed by a main CPU. [Fig. 248] FIG. 2 is an explanatory diagram for explaining a setting mode of each area in the main RAM. [Fig. 249] FIG. 13A is an explanatory diagram for explaining the contents of an address counter, and FIGS. 13B to 13E are explanatory diagrams for explaining how the carry flag is set to “1” as a result of the target address being updated. [Fig. 250] 13 is a flowchart showing a RAM clear process executed by a main CPU. [Fig. 251] 13 is a flowchart showing an addition process of a target address executed by a master CPU. [Fig. 252] 13 is a flowchart showing a clearing process for non-specific control executed by a main CPU. [Fig. 253] 13 is a flowchart showing a checksum calculation process executed by a main CPU. [Fig. 254] 13 is a flowchart showing the performance control process executed by the sound / light side CPU. [Figure 255]13(a) to 13(f) are time charts showing how, when the supply of operating power to the main CPU and the sound / light CPU is started, check displays are displayed on the first to fourth alarm display devices and initial operations are performed by the movable body. [Fig. 256] A flowchart showing the performance control processing executed by the sound and light side CPU in the 73rd embodiment. [Fig. 257] 13 is a flowchart showing a main process executed by a main CPU in the 74th embodiment. [Fig. 258] 13 is a flowchart showing a setting confirmation process executed by a main CPU. [Fig. 259] 13 is a flowchart showing a setting value update process executed by a main CPU. [Fig. 260] 13 is a flowchart showing a RAM clear process executed by a main CPU. [Fig. 261] 13 is a flowchart showing an opening / closing monitoring process executed by a main CPU. [Fig. 262] FIG. 2 is an explanatory diagram for explaining the electrical configuration of the audio and light emission control device. [Fig. 263] 11 is an explanatory diagram for explaining the contents of a post-confirmation notification table; FIG. [Fig. 264] 11 is an explanatory diagram for explaining the relationship between various notification tables and the types of execution areas to be read out; FIG. [Fig. 265] 13(a) to 13(h) are time charts showing the relationship between post-confirmation notification and main body closure notification, and the relationship between post-clearing notification and main body closure notification. [Fig. 266] 13 is a flowchart showing the performance control process executed by the sound / light side CPU. [Fig. 267] 13 is a flowchart showing task processing executed by the sound / light side CPU. [Fig. 268] A flowchart showing the first timer interrupt processing executed by the main CPU in the 75th embodiment. [Fig. 269] 13 is a flowchart showing a check process executed by a main CPU. [Fig. 270] 13 is a flowchart showing a result calculation process executed by a main CPU. [Fig. 271] 13 is a flowchart showing the special chart special power control processing executed by the main CPU. [Fig. 272] 13 is a flowchart showing the special call release processing executed by the main CPU. [Fig. 273] 13 is a flowchart showing an ending process executed by a main CPU. [Fig. 274] 13A and 13B are explanatory diagrams for explaining an example of an ending presentation executed by the pattern display device. [Fig. 275] 10 is an explanatory diagram for explaining the data structure of a main ROM; FIG. [Fig. 276] 13 is an explanatory diagram for explaining the selection probability of the first to fifth suggestive performance information when each of various tables is selected. FIG. [Fig. 277] 13 is a flowchart showing an ending performance control process executed by the audio and light emission control device. [Fig. 278] A flowchart showing the ending process executed by the main CPU in the 76th embodiment. [Fig. 279] A flowchart showing a first timer interrupt process executed by the main CPU in the 77th embodiment. [Fig. 280] FIG. 13A is an explanatory diagram for explaining a sensor for monitoring fraud, and FIG. 13B is a flowchart showing fraud detection processing executed by a main CPU. [Fig. 281] 13 is a flowchart showing a second timer interrupt process executed by a main CPU. [Fig. 282] FIG. 2 is an explanatory diagram for explaining storage areas in an audio / optical side RAM. [Fig. 283] 13 is a flowchart showing an audio / optical side start-up process executed by an audio / optical side CPU. [Fig. 284] 13 is a flowchart showing sound / light side timer interrupt processing executed by the sound / light side CPU. [Fig. 285] 13 is a flowchart showing the start waiting effect processing executed by the sound / light side CPU. [Fig. 286] 13(a) to (i) are time charts showing how a demo performance is executed after the supply of operating power to the pachinko machine begins. [Fig. 287] (a)~(e) are time charts showing how a demo performance starts after a preset period of time has elapsed during which neither the performance for the opening / closing execution mode nor the performance for the game round is being executed. [Fig. 288] 13 is a flowchart showing the sound / light side start-up processing executed by the sound / light side CPU in the 78th embodiment. [Fig. 289] 13 is a flowchart showing the start waiting effect processing executed by the sound / light side CPU. [Fig. 290] (a) An explanatory diagram to explain the memory area provided in the work area for specific control in the 79th embodiment, and (b) an explanatory diagram to explain the areas not to be initialized and the areas to be initialized in the sound-light side RAM. [Fig. 291] 13 is a flowchart showing an audio / optical side start-up process executed by an audio / optical side CPU. [Fig. 292] FIG. 13A is a flowchart showing a timing change lottery process executed by the sound / light side CPU, and FIG. 13B is an explanatory diagram for explaining a timing change lottery table. [Fig. 293] FIG. 13A is a flowchart showing a timing change lottery process executed by the sound / light side CPU in the 80th embodiment, and FIG. 13B is an explanatory diagram for explaining a timing change lottery table. [Fig. 294] FIG. 13 is an explanatory diagram for explaining the configuration of the sound-light side RAM in the 81st embodiment. [Fig. 295] (a) An explanatory diagram illustrating the configuration for external output of representative value data in the 82nd embodiment, and (b) an explanatory diagram illustrating a memory area for external output of representative value data in a work area for specific control. [Fig. 296]13 is a flowchart showing an external information setting process executed by a main CPU. [Fig. 297] 10 is a time chart showing how an abnormality in a base value can be grasped based on representative value data externally output to a data display device. [Figure 298] FIG. 83(a) is a block diagram for explaining a configuration for externally outputting processed representative value data in the 83rd embodiment, and FIG. 83(b) is an explanatory diagram for explaining a memory area for externally outputting processed representative value data provided in a work area for specific control. [Figure 299] 13 is a flowchart showing an external information setting process executed by a main CPU. [Figure 300] (a) A block diagram for explaining the configuration for externally outputting a base value abnormality signal in the 84th embodiment, (b) an explanatory diagram for explaining a memory area for externally outputting a base value abnormality signal provided in a work area for specific control, and (c) an explanatory diagram for explaining the contents of the threshold value table. [Fig. 301] 13 is a flowchart showing an external information setting process executed by a main CPU. [Fig. 302] 4 is a flowchart showing a main process executed by a main CPU. [Fig. 303] 13 is a flowchart showing a base value initial output process executed by a main CPU. [Fig. 304] 11 is a time chart showing how a base value abnormality signal is output to an abnormality alarm based on an abnormality in the base value in the current area. [Fig. 305] 10 is a time chart showing how a base value abnormality signal is externally output to an abnormality alarm based on an abnormality in the base value in the first to third history areas. [Fig. 306] (a) A block diagram for explaining the configuration for externally outputting an upper base value abnormal signal and a lower base value abnormal signal in the 85th embodiment, and (b) an explanatory diagram for explaining a memory area for externally outputting an upper base value abnormal signal and a lower base value abnormal signal provided in a work area for specific control. [Fig. 307] 13 is a flowchart showing an external information setting process executed by a main CPU. [Fig. 308] 13 is a flowchart showing an abnormality flag setting process executed by a main CPU. [Fig. 309] 13 is a flowchart showing an abnormality signal output process executed by a main CPU. [Fig. 310] 13 is a flowchart showing a base value initial output process executed by a main CPU. [Fig. 311] (a) An explanatory diagram for explaining a memory area for external output of an upper base value abnormal signal, a lower first base value abnormal signal, and a lower second base value abnormal signal provided in a work area for specific control in the 86th embodiment, (b) an explanatory diagram for explaining the contents of the threshold value table, and (c) an explanatory diagram for explaining the configuration for external output of an upper base value abnormal signal, a lower first base value abnormal signal, and a lower second base value abnormal signal. [Fig. 312] 6 is a time chart showing how a base value abnormality signal is output to the outside. [Fig. 313] 13 is a flowchart showing an abnormality flag setting process executed by a main CPU. [Fig. 314] 13 is a flowchart showing an abnormality signal output process executed by a main CPU. [Fig. 315] 13(a) and 13(b) are block diagrams illustrating a configuration for externally outputting a common base value abnormal signal, an upper base value abnormal signal, and a lower base value abnormal signal in the 87th embodiment. [Fig. 316] 13 is a flowchart showing an abnormality signal output process executed by a main CPU. [Fig. 317] An explanatory diagram for explaining the electrical configuration of the audio and light emission control board in the 88th embodiment. [Fig. 318] 13 is a flowchart showing an audio / optical side start-up process executed by an audio / optical side CPU. [Fig. 319]FIG. 13A is a flowchart showing a maximum value setting process executed by the sound / light side CPU, and FIG. 13B is an explanatory diagram for explaining a maximum value lottery table. [Fig. 320] 13 is a flowchart showing an update process of a demonstration start timer counter executed by the sound / light side CPU. [Fig. 321] A front view of the main control device in the 89th embodiment. [Fig. 322] 11 is an explanatory diagram for explaining various areas of a work area for non-specific control used for managing game history. FIG. [Figure 323] 13(a) to 13(g) are time charts showing how a first unit update area, a proximate area in a first calculation period, a second unit update area, and a proximate area in a second calculation period are updated. [Fig. 324] 10(a) to 10(d) are explanatory diagrams for explaining the display contents of the first to fifth notification display devices. [Fig. 325] 13 is a flowchart showing a check process executed by a main CPU. [Fig. 326] 13 is a flowchart showing a ball payout rate storage process executed by the main CPU. [Fig. 327] 13 is a flowchart showing a display process executed by a main CPU. [Fig. 328] 13 is a flowchart showing a normal setting process executed by a main CPU. [Fig. 329] 13(a) to 13(k) are time charts showing how the first notification start flag and the second notification start flag are set to "1". [Fig. 330] An explanatory diagram to explain various areas of the work area for non-specific control used to manage game history in the 90th embodiment. [Fig. 331] 13 is a flowchart showing a ball payout rate storage process executed by the main CPU. [Fig. 332] 13 is a flowchart showing a first ball payout rate calculation process executed by the main CPU. [Figure 333]An explanatory diagram to explain various areas of the work area for non-specific control used to manage game history in the 91st embodiment. [Fig. 334] 13 is a flowchart showing a ball payout rate storage process executed by the main CPU. [Figure 335] 13(a) and 13(b) are explanatory diagrams for explaining the display contents of the first, third to fifth notification display devices in the 92nd embodiment. [Fig. 336] (a) An explanatory diagram for explaining various areas of the work area for non-specific control in the 93rd embodiment, and (b) an explanatory diagram for explaining the display contents of the first to fourth notification display devices when the total number information is displayed. [Figure 337] 13(a) to 13(e) are time charts showing how the total number information is displayed on the first to fourth notification display devices. [Figure 338] 13 is a flowchart showing a first timer interrupt process executed by a main CPU. [Figure 339] 13 is a flowchart showing a test firing execution process executed by the main CPU. [Fig. 340] 13 is a flowchart showing a management execution process executed by a main CPU. [Fig. 341] 13 is a flowchart showing a check process executed by a main CPU. [Fig. 342] 13 is a flowchart showing a result calculation process executed by a main CPU. [Figure 343] 13 is a flowchart showing a total number display setting process executed by a main CPU. [Fig. 344] 13 is a flowchart showing a display process executed by a main CPU. [Figure 345] 13 is a flowchart showing a total number display process executed by a main CPU. [Fig. 346] 13 is a flowchart showing a second timer interrupt process executed by a main CPU. [Figure 347]13 is a flowchart showing the remaining process executed by the main CPU. [Fig. 348] 13 is a flowchart showing a tallying and division execution process executed by a main CPU. [Figure 349] 13 is a flowchart showing a tallying and dividing process executed by a main CPU. [Fig. 350] A flowchart showing the first timer interrupt processing executed by the main CPU in the 94th embodiment. [Fig. 351] 13 is a flowchart showing a test firing execution process executed by the main CPU. [Fig. 352] 13 is a flowchart showing a management execution process executed by a main CPU. [Figure 353] A flowchart showing the first timer interrupt processing executed by the main CPU in the 95th embodiment. [Fig. 354] 13 is a flowchart showing a management execution process executed by a main CPU. [Figure 355] (a) is a front view of the game board in the 96th embodiment, and (b) is an explanatory diagram for explaining the state of the special chart display section and the regular chart display section when the total number display is being performed. [Figure 356] 13 is a flowchart showing a display control process executed by a main CPU. [Figure 357] FIG. 13A is an explanatory diagram for explaining the contents of a judgment register in the 97th embodiment, and FIG. 13B is an explanatory diagram for explaining the contents of an area for specifying a state. [Figure 358] 4 is a flowchart showing a main process executed by a main CPU. [Figure 359] 13 is a flowchart showing an abnormality determination process executed by a main CPU. [Figure 360] FIG. 2 is an explanatory diagram for explaining a storage area of ​​a main RAM. [Fig. 361] 13 is a flowchart showing a power outage information storage process executed by a main CPU. [Fig. 362]13 is a flowchart showing a state setting process for a judgment register executed by a main CPU. [Figure 363] 13 is a flowchart showing an operation determination process executed by a main CPU. [Figure 364] 13 is a flowchart showing the remaining process executed by the main CPU. [Figure 365] 13 is a flowchart showing a first timer interrupt process executed by a main CPU. [Fig. 366] 13 is a flowchart showing a setting process executed by a main CPU. [Figure 367] 13 is a flowchart showing a setting response process executed by a main CPU. [Figure 368] 6(a) to 6(d) are time charts showing how processing is executed in a situation where processing for changing a set value or processing for checking a set value is being executed. [Figure 369] 13A to 13F are time charts showing how, in the main processing, execution of a process for changing a setting value based on a setting change operation is prioritized over setting an abnormal state in response to the occurrence of an abnormality. [Figure 370] 13 is a flowchart showing a command transmission process at power-on time executed by the main CPU. [Fig. 371] 5 is a flowchart showing a command response process executed by the audio and light emission control device. [Fig. 372] 13(a) to (g) are time charts showing how commands are sent from the main CPU to the audio and light emission control device when the supply of operating power is started. [Fig. 373] 13A is a flowchart showing a process for starting output of a security signal executed by a main CPU, and FIG. 13B is a flowchart showing a process for responding to a security signal executed by the main CPU. [Fig. 374] 6(a) to 6(f) are time charts showing how a security signal is output to the outside. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0010] <First embodiment> A first embodiment of a pachinko machine 10, which is a type of gaming machine, will be described in detail below with reference to the drawings. Fig. 1 is a perspective view of the pachinko machine 10, and Fig. 2 is a perspective view showing the main components of the pachinko machine 10 in an exploded form. For convenience, Fig. 2 omits the components within the play area PA of the pachinko machine 10.

[0011] As shown in Fig. 1, a pachinko machine 10 has an outer frame 11 that forms the outer shell of the pachinko machine 10, and a gaming machine main body 12 that is attached to the outer frame 11 so as to be rotatable forward. The outer frame 11 is made of wooden boards connected at all four sides, forming a rectangular frame. The pachinko machine 10 is installed in an amusement hall by attaching and fixing the outer frame 11 to an island facility. Note that the outer frame 11 is not a required component of the pachinko machine 10, and the outer frame 11 may be installed in the island facility of the amusement hall.

[0012] 2, the gaming machine body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine body 12 is rotatably supported by the outer frame 11. In detail, the inner frame 13 is rotatable forward with the left side as the base end and the right side as the tip end when viewed from the front.

[0013] A front door frame 14 is rotatably supported by the inner frame 13, and can be rotated forward with the left side as the base end and the right side as the tip end when viewed from the front. A back pack unit 15 is rotatably supported by the inner frame 13, and can be rotated backward with the left side as the base end and the right side as the tip end when viewed from the front.

[0014] The gaming machine body 12 is provided with a locking device at its rotating tip, which has the function of locking the gaming machine body 12 so that it cannot be opened relative to the outer frame 11, and also has the function of locking the front door frame 14 so that it cannot be opened relative to the inner frame 13. Each of these locked states is released by performing an unlocking operation using an unlocking key on a cylinder lock 17 that is exposed on the front of the pachinko machine 10.

[0015] Next, the configuration of the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 having an outer shape substantially identical to that of the outer frame 11. A substantially elliptical window hole 23 is formed in the center of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front side of the game board 24 is exposed to the front side of the inner frame 13 through the window hole 23 of the resin base 21.

[0017] Here, the configuration of the game board 24 will be described with reference to Fig. 3. Fig. 3 is a front view of the game board 24.

[0018] An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and the inner rail section 25 and the outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see FIG. 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0019] Incidentally, the game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeder 27b that supplies game balls stored in the upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c that is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. The solenoid 27c is driven and controlled by rotating a launching operation device (or an operation handle) 28 provided on the front door frame 14. The game balls are launched.

[0020] A number of large and small openings are formed in the game board 24, penetrating in the front-rear direction. Each opening is provided with a general winning port 31, a special electric winning device 32, a first operating port 33, a second operating port 34, a through gate 35, a variable display unit 36, a special chart unit 37, and a general chart unit 38. There are a total of four general winning ports 31, and one of each of the others.

[0021] Even if a ball enters the through gate 35, the payout of game balls is not executed. On the other hand, when balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls are paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball is paid out, when one game ball enters the general winning opening 31, ten prize balls are paid out, and when one game ball enters the special electric winning device 32, fifteen prize balls are paid out.

[0022] The number of prize balls is arbitrary, and for example, the second actuating port 34 may be configured to have a smaller number of prize balls than the first actuating port 33, or the second actuating port 34 may be configured to have a larger number of prize balls than the first actuating port 33.

[0023] In addition, an outlet 24a is provided at the bottom of the game board 24, and game balls that do not enter the various winning holes are discharged from the game area PA through the outlet 24a. In addition, the game board 24 is provided with a large number of nails 24b for appropriately dispersing and adjusting the falling direction of the game balls, and various components such as windmills are also provided.

[0024] Here, the term "entering the ball" means that the game ball passes through a specified opening, and includes not only the state in which the game ball passes through the opening and is discharged from the game area PA, but also the state in which the game ball continues to flow down the game area PA without being discharged from the game area PA after passing through the opening. However, in the following explanation, in order to clearly distinguish from the game ball entering the outlet 24a, the game ball entering the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 will also be expressed as "winning".

[0025] The first actuation port 33 and the second actuation port 34 are unitized as an actuation port device and installed on the game board 24. Both the first actuation port 33 and the second actuation port 34 are open upward. In addition, both actuation ports 33, 34 are aligned vertically with the first actuation port 33 facing upward. The second actuation port 34 is provided with a normal power device 34a as a guide piece consisting of a pair of movable pieces on the left and right. When the normal power device 34a is in a closed state, the game ball cannot enter the second actuation port 34, but when the normal power device 34a is in an open state, the game ball can enter the second actuation port 34.

[0026] A through gate 35 is provided upstream of the second operating port 34 in the flow direction of the game ball. The through gate 35 has a through hole (not shown) that penetrates vertically, and the game ball that enters the through gate 35 flows down the game area PA after entering. This makes it possible for the game ball that enters the through gate 35 to enter the second operating port 34.

[0027] Based on winning the through gate 35, the normal power role 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the winning of the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38 provided in the lower right corner of the play area PA, which is an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role opening and the stop result corresponding to the result is displayed and the variable display of the normal map display section 38a is terminated, the state transitions to the normal power opening state. In the normal power opening state, the normal power role 34a is opened in a predetermined manner.

[0028] The map display unit 38a is composed of a segment display in which a plurality of display segments using LEDs are arranged in a predetermined manner, but is not limited thereto, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display device. As for the pattern displayed variably on the map display unit 38a, a configuration in which a plurality of types of letters are displayed variably, a configuration in which a plurality of types of symbols are displayed variably, a configuration in which a plurality of types of characters are displayed variably, or a configuration in which a plurality of types of colors are displayed in a switched manner may be considered.

[0029] In the normal map unit 38, a normal map reserve display section 38b is provided adjacent to the normal map display section 38a. The number of game balls that enter the through gate 35 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the normal map reserve display section 38b.

[0030] A winning lottery is held by triggering a winning entry into the first operating port 33 or the second operating port 34. The lottery result is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Regarding the special chart unit 37 in detail, the special chart unit 37 is provided with a special chart display section 37a. The display area of ​​the special chart display section 37a is narrower than the display surface 41a of the pattern display device 41. In the special chart display section 37a, a winning lottery is held by triggering the winning of the first operating port 33 or the winning of the second operating port 34, and a variable display or a predetermined display of the pattern is performed. Then, a result corresponding to the lottery result is displayed. The special chart display section 37a is composed of a segment display device in which a plurality of display segments by LEDs are arranged in a predetermined manner, but is not limited to this, and may be composed of other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device. In addition, as the pattern displayed on the special chart display section 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed may be considered.

[0032] In the special chart unit 37, a special chart reserve display section 37b is provided at a position adjacent to the special chart display section 37a. The number of game balls that enter the first operating port 33 or the second operating port 34 is reserved up to a maximum of four, and the number of reserved balls is displayed by lighting up the special chart reserve display section 37b.

[0033] In detail, the pattern display device 41 is configured as a liquid crystal display device equipped with a liquid crystal display, and the display contents are controlled by a display control device described later. The pattern display device 41 is not limited to a liquid crystal display device, and may be other display devices having a display screen such as a plasma display device, an organic EL display device, or a CRT, or may be a dot matrix display device.

[0034] In the pattern display device 41, when the special pattern display section 37a displays a variable or predetermined pattern based on the winning of the first operation port 33 or the winning of the second operation port 34, the pattern display device 41 displays a variable or predetermined pattern accordingly. For example, the display surface 41a of the pattern display device 41 has three pattern rows, an upper row, a middle row, and a lower row, set as a plurality of display areas, and in each pattern row, main patterns numbered "1" to "9" are scrolled and displayed in ascending or descending order. In this scroll display, the scroll display of all pattern rows is started first, and the scroll display is switched to standby display in the order of the upper pattern row → the lower pattern row → the middle pattern row, and finally, the scroll display is ended in a state where a predetermined pattern is statically displayed in each pattern row. Then, in a game round in which the game result is a jackpot result, a combination of predetermined patterns is displayed stationary on a pay line set in advance on the display surface 41a of the pattern display device 41. Specifically, in the case of the most favorable jackpot result described below, the same combination of odd symbols is displayed, in the case of a low probability jackpot result described below, the same combination of even symbols is displayed, and in the case of a low probability jackpot result described below, a combination of symbols that is not the same but would not be displayed in the case of a low probability jackpot result not being a low probability jackpot result is displayed.

[0035] In addition, the pattern display device 41 performs not only a display performance triggered by winning the first operation port 33 or the second operation port 34, but also a display performance during the opening and closing execution mode to which the mode is shifted after a winning is obtained. In addition, based on the winning of either operation port 33, 34, the display is started on the special pattern display unit 37a and the pattern display device 41, and the period from when a predetermined result is displayed until the game ends corresponds to one game. In addition, the manner of the variable display of the patterns on the pattern display device 41 is not limited to the above and is arbitrary, and the number of pattern rows, the direction of the variable display of the patterns in the pattern rows, the number of patterns in each pattern row, etc. can be changed as appropriate. In addition, the patterns displayed by the pattern display device 41 are not limited to the above patterns, and for example, a configuration in which only numbers are displayed as patterns may be used.

[0036] When a big win is won in a lottery based on winning the first operation port 33 or the second operation port 34, the mode shifts to an open / close execution mode in which winning is possible in the special electric winning device 32. The special electric winning device 32 is provided with a large winning port (not shown) that leads to the back side of the game board 24, and is provided with an open / close door 32a that opens and closes the large winning port. The open / close door 32a is arranged in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which the game ball cannot win, and is switched to an open state in which the game ball can win when the internal lottery is selected to switch to the open / close execution mode. Incidentally, the open / close execution mode is a mode to which the mode shifts when a winning result is obtained. It should be noted that the closed state does not mean that winning is impossible, but it may be configured to be in a state in which winning is more difficult than in the open state.

[0037] FIG. 4 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

[0038] As already explained, a game ball that enters any of the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the game area PA. In other words, a game ball that is launched from the game ball launching mechanism 27 and flows into the game area PA is discharged from the game area PA by entering any of the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A game ball that enters any of the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the game board 24.

[0039] On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning port 31, the special winning device 32, the first operating port 33, the second operating port 34, and the outlet 24a, respectively. The game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, and are guided to the lower end of the game board 24 on the back side of the game board 24, and are collected in a discharge ball collection section (not shown). The game balls collected in the discharge ball collection section are then discharged to a ball circulation device of an island facility where a pachinko machine 10 is installed in a game hall.

[0040] Each of the discharge passages 42-48 is provided with various detection sensors 42a-48a for detecting game balls. The discharge passages 42-48 and the detection sensors 42a-48a will be described below. As already described, four general winning openings 31 are provided, and therefore, the discharge passages 42-44 exist corresponding to each of the four general winning openings 31. In this case, one detection sensor 42a, 43a is provided for each of the first discharge passage 42 corresponding to the leftmost general winning opening 31 and the second discharge passage 43 corresponding to the general winning opening 31 adjacent thereto to the right. Specifically, the first winning opening detection sensor 42a is provided so that its detection range is located in the middle of the first discharge passage 42, and the second winning opening detection sensor 43a is provided so that its detection range is located in the middle of the second discharge passage 43. A game ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage section 42, and a game ball that enters the general winning opening 31 adjacent to the left is detected by the second winning opening detection sensor 43a while passing through the second discharge passage section 43. A third discharge passage section 44 is provided for the two general winning openings 31 on the right side, which are formed so as to merge at an intermediate position. The third discharge passage section 44 has an entrance side area corresponding to each of the two general winning openings 31, and the entrance side areas merge at an intermediate position to form one exit side area. A third winning opening detection sensor 44a is provided so that a detection range exists at an intermediate position of the exit side area in the third discharge passage section 44. A game ball that enters one of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage section 44.

[0041] A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists in the middle of the fourth discharge passage section 45, and the game ball that entered the special electric winning device 32 is detected by the special electric detection sensor 45a in the middle of passing through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists in the middle of the fifth discharge passage section 46, and the game ball that entered the first operating port 33 is detected by the first operating port detection sensor 46a in the middle of passing through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second actuation port detection sensor 47a is provided so that a detection range exists in a midway position of the sixth discharge passage section 47, and a game ball that enters the second actuation port 34 is detected by the second actuation port detection sensor 47a in the middle of passing through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that a detection range exists in a midway position of the seventh discharge passage section 48, and a game ball that enters the outlet 24a is detected by the outlet detection sensor 48a in the middle of passing through the seventh discharge passage section 48.

[0042] In addition, a gaming ball that is detected by any one of the various detection sensors 42a to 48a is not detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on the way down the game area PA is detected by the gate detection sensor 49a.

[0043] Although electromagnetic induction type proximity sensors are used as the various detection sensors 42a-49a, any sensor can be used as long as it can detect the game balls individually. The various detection sensors 42a-49a are electrically connected to a main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a game ball, and output a HI level signal when they are detecting a game ball. However, this is not limited to this, and the relationship between HI and LOW may be reversed.

[0044] As shown in FIG. 2, the front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the game board 24 of the above configuration to the resin base 21. As shown in FIG. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of ​​the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into the window portion 51. The window panel 52 is formed of glass so as to be colorless and transparent, but is not limited thereto and may be formed of synthetic resin so as to be colorless and transparent, or may be formed of colored transparency as long as the game area PA can be viewed through the window panel 52 from the front of the pachinko machine 10.

[0045] Above the window 51, a display light-emitting unit 53 is provided. A pair of left and right speaker units 54 are provided to output sound effects according to the game state. Below the window 51, an upper bulge 55 and a lower bulge 56 are arranged vertically side by side, bulging toward the front side. An upper tray 55a opening upward is provided inside the upper bulge 55, and a lower tray 56a opening upward is provided inside the lower bulge 56. The upper tray 55a has a function of temporarily storing game balls dispensed from a dispensing device described later, and guiding the game balls to the game ball launching mechanism 27 while aligning them in a row. The lower tray 56a has a function of storing game balls that are surplus in the upper tray 55a.

[0046] Next, the configuration of the rear side of the gaming machine main body 12 will be described.

[0047] As shown in Fig. 2, a main control device 60 that mainly controls the game is mounted on the back surface of the inner frame 13 (specifically, the game board 24). Fig. 5 is a front view of the main control device 60.

[0048] As shown in FIG. 5, the main control device 60 is configured by housing a main control board 61 in a board box 60a. An MPU 62 is mounted on an element mounting surface, which is one of the board surfaces of the main control board 61. The board box 60a is formed transparent so that the MPU 62 housed in the board box 60a can be seen from the outside of the board box 60a. Although the board box 60a is formed colorless and transparent, it may be formed colored and transparent as long as the MPU 62 housed in the board box 60a can be seen from the outside of the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 such that an opposing wall portion 60b facing the element mounting surface of the main control board 61 in the board box 60a faces the rear of the pachinko machine 10. Therefore, by opening the gaming machine main body 12 toward the front of the pachinko machine 10 relative to the outer frame 11 and exposing the back surface of the resin base 21, it becomes possible to visually observe the opposing wall portion 60b of the base box 60a and the MPU 62 through the opposing wall portion 60b.

[0049] The board box 60a is formed by combining a plurality of case bodies 60c in front and behind, and the plurality of case bodies 60c are provided with joints 60e for preventing separation of the case bodies 60c and leaving a trace when the case bodies 60c are separated. The joints 60e are arranged in a row on one side of the board box 60a having a substantially rectangular parallelepiped shape. As a result, even if some of the joints 60e are used to prevent separation of the case bodies 60c and the case bodies 60c are separated by destroying the part of the joints 60e, it is possible to prevent separation of the case bodies 60c again by connecting another joint 60e thereafter. In addition, since the joints 60e are destroyed when the case bodies 60c are separated and a trace is left, it is possible to visually check the joints 60e to know whether the separation of the case bodies 60c is being performed illegally. In addition, a seal 60f is attached to the side of the board box 60a opposite to the side on which the joints 60e are arranged so as to straddle the boundary between the case bodies 60c. When the seal 60f is peeled off, an adhesive layer remains on the case body 60c. This makes it possible to leave a trace when the seal 60f is peeled off when the case body 60c is separated.

[0050] In the main control device 60 having the above configuration, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the manager of the game hall is inserted and turned on to generate an opportunity to change the setting state of the pachinko machine 10 within the range of "setting 1" to "setting 6", an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned on, a reset button 68c which is operated to clear data in a main RAM 65 (described later) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c for notifying the management result of the game history. In addition, the MPU 62 mounted on the main control board 61 is provided with a read terminal 68d for connecting a connection terminal of an external device to read the management result of the game history or information (programs and data) stored in the main ROM 64 by the external device. The setting state of the pachinko machine 10 is not limited to six stages from "Setting 1" to "Setting 6", but may be any multiple stage.

[0051] The setting key insertion section 68a, the update button 68b, the reset button 68c, the read terminal 68d (i.e., the MPU 62), and the first to third notification display devices 69a to 69c are all provided on the element mounting surface of the main control board 61. As already explained, the element mounting surface of the main control board 61 faces the opposing wall portion 60b of the board box 60a, but the setting key insertion section 68a, the update button 68b, the reset button 68c, and the read terminal 68d are not covered by the opposing wall portion 60b. That is, the opposing wall portion 60b has separate openings in the areas facing the setting key insertion section 68a, the update button 68b, the reset button 68c, and the read terminal 68d. This makes it possible to insert a setting key into the setting key insertion section 68a, to press the update button 68b, to press the reset button 68c, and to connect a connection terminal of an external device to the read terminal 68d, without the need to open the board box 60a.

[0052] By inserting a setting key into the setting key insertion section 68a and rotating it in a predetermined direction, the setting key insertion section 68a is turned ON. In this state, the supply of operating power to the pachinko machine 10 is started (i.e., the supply of operating power to the MPU 62 of the main control device 60 is started), and the setting state of the pachinko machine 10 is changed to a changeable state in which it is possible to change the setting state of the pachinko machine 10. In this state, the setting state of the pachinko machine 10 is changed by one step in ascending order within the range of "Setting 1" to "Setting 6" each time the update button 68b is pressed once. Note that, when the update button 68b is operated in the "Setting 6" state, the setting state is updated to "Setting 1". In addition, by rotating the setting key inserted into the setting key insertion section 68a from the ON operation position in the direction opposite to the predetermined direction and returning it to the initial position, the setting key insertion section 68a is turned OFF. When the setting key insertion section 68a is turned OFF, the changeable state ends, and the game is played with the setting value at that time. In other words, after the changeable state ends, the setting value cannot be changed even if the update button 68b is operated.

[0053] The ON operation of the setting key insertion section 68a is valid only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 is completed, the setting value cannot be changed.

[0054] The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10, and the greater the value of "setting n" (n is an integer between "1" and "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in detail later, there are a low probability mode with a relatively low probability of winning and a high probability mode with a relatively high probability of winning as the win / lose lottery mode that determines the probability of winning a jackpot result, and the higher the setting value, the higher the probability of winning a jackpot result in the low probability mode. On the other hand, regardless of the setting value, the probability of winning a jackpot result in the high probability mode is constant.

[0055] As described above, the reset button 68c is operated to clear the data in the main RAM 65, but in order to clear the data, it is necessary to start the supply of operating power to the pachinko machine 10 while the reset button 68c is pressed (i.e., it is necessary to start the supply of operating power to the MPU 62 of the main control device 60). The ON operation of the reset button 68c is only valid when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the reset button 68c is pressed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 is completed, the data in the main RAM 65 cannot be cleared.

[0056] As already explained, the read terminal 68d is connected to a connection terminal of an external device in order to read the results of game history management or information (programs and data) stored in the main ROM 64 by the external device, but in order to perform external output to the external device, it is necessary to start supplying operating power to the pachinko machine 10 with the connection terminal of the external device connected to the read terminal 68d (i.e., it is necessary to start supplying operating power to the MPU 62 of the main control device 60). The connection of the external device to the read terminal 68d is enabled only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if an external device is connected to the read terminal 68d after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 is completed, no external output to the external device is performed.

[0057] The first to third notification display devices 69a to 69c are all segment displays in which seven LED display segments are arranged, but are not limited thereto and may be a single light-emitting body of a multi-color light-emitting type, a liquid crystal display device, or an organic EL display. The first to third notification display devices 69a to 69c are all installed so that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and are covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparent, it is possible to visually check the display surfaces of the first to third notification display devices 69a to 69c housed in the board box 60a from the outside of the board box 60a. As already explained, the main control device 60 is mounted on the back surface of the resin base 21 so that the opposing wall portion 60b, which faces the element mounting surface of the main control board 61 in the board box 60a, faces the rear of the pachinko machine 10. Therefore, when the gaming machine main body 12 is opened toward the front of the pachinko machine 10 relative to the outer frame 11 and the rear surface of the resin base 21 is exposed toward the front of the pachinko machine 10, it becomes possible to visually observe the display surfaces of the first to third alarm display devices 69a to 69c through the opposing wall portion 60b.

[0058] On the display surface of the first notification display device 69a, not only the numbers "0" to "9" but also various characters including alphabetical characters are displayed. On the other hand, the numbers "0" to "9" are displayed on the second notification display device 69b and the third notification display device 69c. The results of the management of the game history are notified using the first to third notification display devices 69a to 69c, and the contents of this notification will be described in detail later. In addition, in a changeable state in which the setting state of the pachinko machine 10 can be changed, a value corresponding to the current setting value is displayed on the third notification display device 69c. Note that the value corresponding to the setting value may be configured to be displayed on the first notification display device 69a or the second notification display device 69b. In addition, a configuration may be adopted in which the setting value before the changeable state is displayed on one of the first to third notification display devices 69a to 69c and the current setting value is displayed on another of the first to third notification display devices 69a to 69c.

[0059] As shown in Fig. 2, the back pack unit 15 is installed so as to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 has a back pack 72 formed of a transparent synthetic resin, to which a dispensing mechanism section 73 and a control device assembly unit 74 are attached.

[0060] The payout mechanism 73 includes a tank 75 to which game balls are successively replenished from the island equipment of the gaming hall, and a payout device 76 for paying out the game balls stored in the tank 75. The game balls paid out from the payout device 76 are discharged to the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power supply on and off.

[0061] The control device assembly unit 74 includes a payout control device 77 having a function of controlling the payout device 76, and a power supply / launch control device 78 which generates and outputs a predetermined amount of power required by various control devices, etc., and controls the launch of game balls in response to the player's operation of the launch operation device 28. The payout control device 77 and the power supply / launch control device 78 are stacked in front of and behind each other, with the payout control device 77 at the rear of the pachinko machine 10.

[0062] <Electrical configuration of the pachinko machine 10> FIG. 6 is a block diagram showing the electrical configuration of the pachinko machine 10. As shown in FIG.

[0063] The main control device 60 comprises a main control board 61 which is responsible for the main control of the game, and a power failure monitoring board 67 which monitors the power supply. The main control board 61 is equipped with an MPU 62. The MPU 62 has a main CPU 63, which is a processing device including a control unit and a calculation unit, as well as a main ROM 64, a main RAM 65, and a management IC 66. In addition to the above elements, the MPU 62 also has an interrupt circuit, a timer circuit, a data input / output circuit, various counter circuits as random number generators, and the like built in.

[0064] The main ROM 64 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory such as a NOR flash memory or a NAND flash memory, and is used for read-only purposes. The main ROM 64 stores various control programs and fixed value data executed by the main CPU 63.

[0065] The main RAM 65 is a memory (i.e., a volatile storage means) that requires an external power supply to retain memory such as SRAM and DRAM, and is used for both reading and writing. The main RAM 65 is randomly accessible, and when compared with the main ROM 64 for the same data capacity, it takes less time to read data. The main RAM 65 temporarily stores various data for the execution of the control program stored in the main ROM 64.

[0066] The management IC 66 is a management device that manages the game history based on information supplied from the main CPU 63. Although details will be described later, the management IC 66 grasps the ball entry history of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, and grasps the ball entry frequency into the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34 according to the grasped ball entry history. In addition, the management IC 66 grasps the occurrence frequency of the opening / closing execution mode and the high frequency support mode, which will be described later.

[0067] The MPU 62 is provided with an input port and an output port. The input side of the MPU 62 is connected to a power failure monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power failure monitoring board 67 is connected to a power supply / launch control device 78 having a function of supplying operating power, and the MPU 62 is supplied with operating power via the power failure monitoring board 67.

[0068] The input side of the MPU 62 is connected to various sensors such as the ball entry detection sensors 42a to 49a. As already explained, the ball entry detection sensors 42a to 49a include the first winning hole detection sensor 42a, the second winning hole detection sensor 43a, the third winning hole detection sensor 44a, the special electric detection sensor 45a, the first operation hole detection sensor 46a, the second operation hole detection sensor 47a, the out hole detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a to 49a, the main CPU 63 judges whether a ball has entered each entry section. In addition, the main CPU 63 executes various lotteries based on the entry into the first operation hole 33, and executes various lotteries based on the entry into the second operation hole 34.

[0069] The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is located at the ON operation position or the OFF operation position. The main CPU 63 then identifies whether the setting key insertion section 68a is located at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b is pressed. The main CPU 63 then identifies whether the update button 68b is pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c is pressed. The main CPU 63 then identifies whether the reset button 68c is pressed based on the detection result from the sensor.

[0070] The output side of the MPU 62 is connected to the power failure monitoring board 67, the payout control device 77, and the sound and light emission control device 81. For example, a prize ball command is output to the payout control device 77 based on the fact that a game ball has entered a prize ball entry section among the above-mentioned ball entry sections, in which the occurrence of the ball entry corresponds to the payout of the game ball. Various commands such as a variation command, a type command, and an opening command are output to the sound and light emission control device 81.

[0071] The output side of the MPU 62 is connected to the special power drive unit 32b that opens and closes the opening and closing door 32a of the special power winning device 32, the normal power drive unit 34b that opens and closes the normal power role 34a of the second operating port 34, the special chart unit 37, and the normal chart unit 38. Incidentally, the special chart unit 37 is provided with a special chart display unit 37a and a special chart reserved display unit 37b, all of which are connected to the output side of the MPU 62. Similarly, the normal chart unit 38 is provided with a normal chart display unit 38a and a normal chart reserved display unit 38b, all of which are connected to the output side of the MPU 62. Various driver circuits are provided on the main control board 61, and the MPU 62 executes drive control of various drive units and various display units through the driver circuits.

[0072] That is, in the open / close execution mode, the main CPU 63 executes drive control of the special power drive unit 32b so that the special power winning device 32 is opened and closed. Also, when the open state of the normal power role 34a is won, the main CPU 63 executes drive control of the normal power drive unit 34b so that the normal power role 34a is opened and closed. Also, during each game, the main CPU 63 executes display control of the special chart display unit 37a. Also, when the lottery result of whether or not the normal power role 34a is opened is to be clearly indicated, the main CPU 63 executes display control of the normal chart display unit 38a. In addition, when a winning entry occurs at the first operating port 33 or the second operating port 34, or when a changing display starts in the special chart display unit 37a, the main CPU 63 executes display control of the special chart pending display unit 37b, and when a winning entry occurs at the through gate 35, or when a changing display starts in the regular chart display unit 38a, the main CPU 63 executes display control of the regular chart pending display unit 38b.

[0073] The first to third notification display devices 69a to 69c are connected to the output side of the MPU 62. The results of the management of the game history in the management IC 66 are notified through the display on the first to third notification display devices 69a to 69c. When the setting state of the pachinko machine 10 is changed, the current setting value is displayed on the third notification display device 69c. In this case, the display of the first notification display device 69a and the second notification display device 69b is controlled by the management IC 66 and not by the main CPU 63, whereas the display of the third notification display device 69c is controlled by the main CPU 63 and is also controlled by the management IC 66. The display control of the third notification display device 69c by the main CPU 63 takes precedence over the display control by the management IC 66.

[0074] However, without being limited to this, the third notification display device 69c may also be configured to be display-controlled by the management IC 66 and not by the main CPU 63. In this case, when the current setting value is to be displayed on the third notification display device 69c upon changing the setting state of the pachinko machine 10, it is preferable that the main CPU 63 instructs the management IC 66 to display the setting value.

[0075] The MPU 62 is provided with a read terminal 68d. The read terminal 68d is provided with a sensor (not shown), which detects whether or not a connection terminal of an external device is connected to the read terminal 68d. Then, the master CPU 63 determines whether or not a connection terminal of an external device is connected to the read terminal 68d based on the detection result from the sensor. Furthermore, when an external device is connected to the read terminal 68d, the management result of the game history in the management IC 66 or the information (programs and data) stored in the master ROM 64 is output to the external device.

[0076] The power failure monitoring board 67 relays between the main control board 61 and the power supply / launch control device 78, and monitors the voltage of 24 V DC stable, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 controls the payout of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0077] The power supply / launch control device 78 is connected to a commercial power supply (external power supply) in, for example, a game hall. Based on the external power supplied from the commercial power supply, the power supply / launch control device 78 generates the necessary operating power for the main control board 61, the payout control device 77, etc., and supplies the generated operating power. Incidentally, the power supply / launch control device 78 is provided with a power supply unit for power interruption such as a backup capacitor, and even when the power supply of the pachinko machine 10 is in an OFF state, the power supply unit for power interruption supplies power for memory retention to the main RAM 65 of the main control device 60 and the payout control device 77. The power supply / launch control device 78 also controls the launch of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when a predetermined launch condition is met. As already explained, the payout mechanism unit 73 is provided with a power switch, and when the power switch is turned ON, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned OFF, the supply of operating power to the pachinko machine 10 is stopped.

[0078] The audio and light-emitting control device 81 drives and controls the display light-emitting unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and also controls the display control device 82. The display control device 82 executes display control of the pattern display device 41 based on commands received from the audio and light-emitting control device 81.

[0079] <Electrical configuration for performing various lotteries in the main CPU 63> Next, the electrical configuration for performing various lotteries in the main CPU 63 will be described with reference to FIG.

[0080] The master CPU 63 uses various counter information during play to perform a lottery for a big win, setting the display of the special symbol display section 37a, setting the symbol display of the symbol display device 41, setting the display of the normal symbol display section 38a, and the like. Specifically, as shown in FIG. 7, a winning random number counter C1 used for a lottery for a winning occurrence, a big win type counter C2 used for determining a big win type, a reach random number counter C3 used for a reach occurrence lottery when the symbol display device 41 misses and varies, a random number initial value counter CINI used for setting the initial value of the winning random number counter C1, and a variation type counter CS for determining the display duration time in the special symbol display section 37a and the symbol display device 41. Furthermore, a normal power role release counter C4 used for a lottery for whether or not the normal power role 34a of the second operating port 34 is in a normal power open state is used. The above counters C1 to C3, CINI, CS, and C4 are provided in the various counter areas 65b of the master RAM 65.

[0081] Each counter C1-C3, CINI, CS, C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching the maximum value. Each counter is updated at short intervals. Information corresponding to the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored in the reserved storage area 65a provided as acquired information storage means in the main RAM 65 when a winning occurs in the first actuation port 33 or the second actuation port 34.

[0082] The reserved storage area 65a includes a reserved area RE and an execution area AE. The reserved area RE includes a first reserved area RE1, a second reserved area RE2, a third reserved area RE3, and a fourth reserved area RE4, and a combination of numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 is stored as reserved information in one of the reserved areas RE1 to RE4 according to the winning history of the first actuation port 33 or the second actuation port 34.

[0083] In this case, when winning occurs multiple times consecutively in the first actuation port 33 or the second actuation port 34, the numerical information is stored in the first hold area RE1 to the fourth hold area RE4 in the order of the first hold area RE1 → the second hold area RE2 → the third hold area RE3 → the fourth hold area RE4 in chronological order. By providing the four hold areas RE1 to RE4 in this way, up to four winning histories of game balls in the first actuation port 33 or the second actuation port 34 can be reserved and stored.

[0084] In addition, the number of items that can be stored on hold is not limited to four and is arbitrary, and may be other multiples such as two, three, or five or more, or may be singular.

[0085] The execution area AE is an area for moving each piece of numerical information stored in the first holding area RE1 of the holding area RE when the changing display of the special chart display section 37a begins, and when one game round begins, a win / loss determination, etc. is made based on the various numerical information stored in the execution area AE.

[0086] Each of the above counters will now be described in detail.

[0087] First, the normal power accessory opening counter C4 will be described. The normal power accessory opening counter C4 is configured to be incremented by 1 in the range of 0 to 250, for example, and to return to "0" after reaching the maximum value. The normal power accessory opening counter C4 is periodically updated and stored in the normal power reserve area 65c of the main RAM 65 at the timing when the game ball enters the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether or not to control the normal power accessory 34a to an open state based on the value of the stored normal power accessory opening counter C4.

[0088] In the present pachinko machine 10, a plurality of types of support modes are set so that the manner of support by the normal power accessory 34a is different from each other. In detail, the support modes are set to a high frequency support mode and a low frequency support mode so that the frequency with which the normal power accessory 34a of the second operating port 34 is in an open state per unit time is relatively high and low when compared with a situation in which the launch of game balls continues in the same manner in the game area PA.

[0089] In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power role opening counter C4 is the same (for example, both are 4 / 5), but in the high-frequency support mode, the number of times that the normal power role 34a is in the open state when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for one time is set to be longer. In this case, when the normal power opening state is won in the high-frequency support mode and the open state of the normal power role 34a occurs multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for one time. Furthermore, in the high-frequency support mode, the minimum time to be secured between one normal power opening lottery and the next normal power opening lottery (i.e., the display duration of one time in the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0090] As described above, in the high frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the low frequency support mode. In other words, in the low frequency support mode, the probability of a winning entry into the first actuation port 33 is higher than in the second actuation port 34, but in the high frequency support mode, the probability of a winning entry into the second actuation port 34 is higher than in the first actuation port 33. When a winning entry into the second actuation port 34 occurs, a predetermined number of game balls are paid out, so that in the high frequency support mode, the player can play without losing too many balls.

[0091] The configuration for increasing the frequency of the high-frequency support mode becoming in the normal power release state per unit time compared to the low-frequency support mode is not limited to the above, and may be, for example, a configuration for increasing the probability of winning the normal power release state in the normal power release lottery. In addition, in a configuration in which a plurality of types of secured time (for example, the time of variable display executed in the normal power display unit 38a based on winning the through gate 35) are provided for securing from one normal power release lottery to the next normal power release lottery, the high-frequency support mode may be set so that a shorter secured time is more likely to be selected or the average secured time is shorter than in the low-frequency support mode. Furthermore, the advantage of the high-frequency support mode over the low-frequency support mode may be increased by applying any one or any combination of conditions from increasing the number of openings, lengthening the opening time, shortening the secured time secured from one normal power release lottery to the next normal power release lottery, shortening the average secured time, and increasing the winning probability.

[0092] Here, as already explained, the pachinko machine 10 has the setting states of "setting 1" to "setting 6", but the opening frequency and opening mode of the normal power device 34a in the low frequency support mode are the same regardless of the setting value, and the opening frequency and opening mode of the normal power device 34a in the high frequency support mode are the same regardless of the setting value. However, this is not limited to this, and at least one of the opening frequency and opening mode of the normal power device 34a for at least one of the low frequency support mode and the high frequency support mode may be configured to vary depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the opening frequency of the normal power device 34a in the low frequency support mode, and the higher the probability of the game ball entering the second operating port 34 when the normal power device 34a is in a one-time opening state in the low frequency support mode. In addition, the higher the set value, the higher the frequency of opening of the normal power device 34a in the high-frequency support mode, and the higher the probability of a game ball entering the second operating port 34 when the normal power device 34a is opened once in the high-frequency support mode.

[0093] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by one within the range of, for example, 0 to 599, and to return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 goes around once, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. The random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically, and is stored in the reserved storage area 65a of the main RAM 65 at the timing when the game ball enters the first actuation port 33 or the second actuation port 34.

[0094] The random number value that becomes the big win is stored as a win / lose table in the main ROM 64. Fig. 8 is an explanatory diagram for explaining various tables stored in the main ROM 64. As the win / lose table, low-probability win / lose tables 64a to 64f for the low probability mode and high-probability win / lose table 64g for the high probability mode are stored.

[0095] The low-probability winning / losing tables 64a to 64f are provided in one-to-one correspondence with the setting states of "setting 1" to "setting 6." That is, there are a low-probability winning / losing table 64a for setting 1, which is referred to when the setting state of the pachinko machine 10 is "setting 1," a low-probability winning / losing table 64b for setting 2, which is referred to when the setting state of the pachinko machine 10 is "setting 2," a low-probability winning / losing table 64c for setting 3, which is referred to when the setting state of the pachinko machine 10 is "setting 3," a low-probability winning / losing table 64d for setting 4, which is referred to when the setting state of the pachinko machine 10 is "setting 4," a low-probability winning / losing table 64e for setting 5, which is referred to when the setting state of the pachinko machine 10 is "setting 5," and a low-probability winning / losing table 64f for setting 6, which is referred to when the setting state of the pachinko machine 10 is "setting 6."

[0096] These low-probability tables 64a to 64f are set so that the higher the set value, the higher the probability of winning the jackpot. Specifically, when the low-probability table 64a for setting 1 is referenced, the jackpot result is about 1 / 320, when the low-probability table 64b for setting 2 is referenced, the jackpot result is about 1 / 310, when the low-probability table 64c for setting 3 is referenced, the jackpot result is about 1 / 300, when the low-probability table 64d for setting 4 is referenced, the jackpot result is about 1 / 290, when the low-probability table 64e for setting 5 is referenced, the jackpot result is about 1 / 280, and when the low-probability table 64f for setting 6 is referenced, the jackpot result is about 1 / 270. As a result, when the setting state of the pachinko machine 10 is a high setting value, the jackpot result is more likely to occur in the low probability mode, which is advantageous for the player.

[0097] On the other hand, only one type of high probability winning / losing table 64g is provided so that it is common to any of the setting states of "setting 1" to "setting 6". The high probability winning / losing table 64g is set so that the winning probability of the jackpot result is higher than that of the low probability winning / losing tables 64a to 64f regardless of the setting state of "setting 1" to "setting 6". Specifically, when the high probability winning / losing table 64g is referred to, the jackpot result occurs at about 1 / 30. This makes it possible to make the high probability mode more advantageous than the low probability mode regardless of the setting state of the pachinko machine 10. In addition, even if the setting state of the lowest setting state "setting 1" is the high probability mode, it is possible to increase the probability of the jackpot result compared to the low probability mode of the highest setting state "setting 6". In addition, it is possible to prevent the high probability mode from causing an advantage or disadvantage depending on the setting state of the pachinko machine 10, and it is also possible to reduce the storage capacity for storing the high probability winning / losing table 64g in advance in the main ROM 64.

[0098] The big win type counter C2 is configured to be incremented by one within the range of 0 to 29, and to return to "0" after reaching the maximum value. The big win type counter C2 is periodically updated, and is stored in the reserved storage area 65a when a gaming ball enters the first actuation port 33 or the second actuation port 34.

[0099] A plurality of jackpot results are set in this pachinko machine 10. These plurality of jackpot results are set by providing differences in three conditions: (1) the manner of opening and closing control of the special electric prize winning device 32 in the opening and closing execution mode, (2) the lottery mode in the winning / losing lottery means after the opening and closing execution mode ends, and (3) the support mode in the regular electric role 34a of the second operating port 34 after the opening and closing execution mode ends.

[0100] As the manner of opening and closing control of the special line winning device 32 in the opening and closing execution mode, a high frequency winning mode and a low frequency winning mode are set so that the frequency of winning in the special line winning device 32 from the start to the end of the opening and closing execution mode is relatively high and low. Specifically, in either the high frequency winning mode or the low frequency winning mode, a predetermined number of rounds are played up to the upper limit.

[0101] A round game is a game that continues until one of the following conditions is met: a predetermined upper limit duration has elapsed, or a predetermined upper limit number of game balls have entered the special electric winning device 32. In addition, the number of round games in the open / close execution mode triggered by a jackpot result is the same as a fixed number of rounds, regardless of the type of jackpot result that triggered the transition. Specifically, regardless of the jackpot result, the upper limit number of round games is set to 15 rounds.

[0102] In addition, in the present pachinko machine 10, a plurality of types are set for the opening mode of the special electric winning device 32, with different opening durations from when the special electric winning device 32 is opened to when it is closed. In detail, a long-time mode in which the opening duration is set to a long time of 29 seconds and a short-time mode in which the opening duration is set to a short time of 0.06 seconds, which is shorter than the long-time mode, are set.

[0103] In this pachinko machine 10, when the launch operation device 28 is operated by the player, the game ball launch mechanism 27 is driven and controlled so that one game ball is launched toward the game area PA every 0.6 seconds. In addition, the upper limit number of balls for the end condition of the round game is set to nine. Then, in the long-time mode among the above-mentioned opening modes, the opening duration is set to a time longer than the product of the game ball launch cycle and one round game. On the other hand, in the short-time mode, the opening duration is set to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when one opening is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of balls in one round game, and when one opening is performed in the short-time mode, it is expected that no winning will occur in the special electric winning device 32, or that even if a winning occurs, it will be about one ball.

[0104] In the high frequency winning mode, the special electric winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special electric winning device 32 is opened once in each round of play in a short time mode.

[0105] In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of times in one round of play in the high-frequency winning mode and low-frequency winning mode are arbitrary and are not limited to the above values, so long as the frequency of winning in the special electric winning device 32 between the start and end of the opening and closing execution mode is higher in the high-frequency winning mode than in the low-frequency winning mode.

[0106] The allocation destination of the jackpot result for the jackpot type counter C2 is stored as an allocation table 64h in the main ROM 64 as shown in Fig. 8. In the allocation table 64h, a low probability jackpot result, a low prize winning high probability jackpot result, and a most favorable jackpot result are set as the allocation destination of the jackpot result in the case of a jackpot result.

[0107] The low probability jackpot result is a jackpot result in which the open / close execution mode becomes the high frequency winning mode, and after the open / close execution mode ends, the winning / losing lottery mode becomes the low probability mode, and the support mode becomes the high frequency support mode. However, this high frequency support mode will transition to the low frequency support mode if the number of games played after the transition reaches the end reference number (specifically, 100 times).

[0108] The low-prize high-probability jackpot result is a jackpot result in which the open / close execution mode becomes the low-frequency prize mode, and after the open / close execution mode ends, the win / lose lottery mode becomes the high-probability mode and the support mode becomes the high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery becomes a jackpot state win and transitions to the jackpot state.

[0109] The most favorable jackpot result is a jackpot result in which the open / close execution mode becomes a high-frequency winning mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high probability mode and the support mode becomes a high-frequency support mode. These high probability mode and high frequency support mode continue until the lottery result in the win / lose lottery becomes a jackpot state win and transitions to the jackpot state.

[0110] In relation to the above game states, the normal game state refers to a state where the winning / losing lottery mode is not the open / close execution mode, and the win / loose lottery mode is the low probability mode, and the support mode is the low frequency support mode. Also, a configuration may be made in which a low winning high probability jackpot result is not set as a game result. Also, in the open / close execution mode in a low winning high probability jackpot result, the number of rounds of play may be less than the number of rounds of play in the case of a low probability jackpot result and the most favorable jackpot result.

[0111] In the distribution table 64h, of the values ​​of the jackpot type counter C2, which are "0 to 29", "0 to 9" corresponds to a low probability jackpot result, "10 to 14" corresponds to a low probability jackpot result with a high probability of winning, and "15 to 29" corresponds to the most favorable jackpot result.

[0112] Only one type of distribution table 64h is provided so that it is common to any of the setting states of "Setting 1" to "Setting 6." This makes it possible to prevent any advantage or disadvantage from arising in the distribution pattern of the jackpot result depending on the setting state of the pachinko machine 10, and also makes it possible to reduce the storage capacity for storing the distribution table 64h in advance in the main ROM 64.

[0113] In addition, the allocation of the jackpot result may be different depending on the setting state of the pachinko machine 10. For example, the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result, or the higher the setting value, the higher the probability of being allocated to the most favorable jackpot result or the low prize-winning high probability jackpot result. In this case, the higher the setting value, the higher the probability of the high probability mode after the jackpot result. Also, the higher the setting value, the lower the probability of being allocated to the low prize-winning high probability jackpot result, or the higher the setting value, the lower the probability of being allocated to the low prize-winning high probability jackpot result. In this case, the higher the setting value, the higher the probability of the opening and closing execution mode of the high frequency winning mode occurring.

[0114] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to be incremented by one within the range of, for example, 0 to 238, and to return to "0" after reaching the maximum value. In this pachinko machine 10, an expectation effect is set as a type of display effect in the pattern display device 41. The expectation effect refers to a display state for making a player think that the variable display state is likely to result in the award corresponding result from the start of the variable display of the patterns in the pattern display device 41 and before the stop result is derived and displayed in a gaming machine equipped with the pattern display device 41 capable of performing a variable display of the patterns, in which the final stop result in a game round resulting in a predetermined jackpot result is a grant corresponding result. Specifically, the grant corresponding result is displayed by stopping a combination of patterns with the same number on any of the pay lines.

[0115] There are two types of expectation effects: a reach display and a notice display that creates anticipation for the occurrence of a reach display or a corresponding result before the reach display occurs.

[0116] The reach display includes a display state in which a combination of reach symbols is displayed by stopping and displaying symbols for some of the multiple symbol rows displayed on the display surface 41a of the symbol display device 41, and in that state, the remaining symbol rows are displayed with varying symbols. Also, in the state in which the reach symbol combination is displayed as described above, the remaining symbol rows are displayed with varying symbols, and a reach performance is performed by displaying a predetermined character or the like as a moving image on the background screen, and a reach performance is performed by displaying a reduced or non-displayed combination of reach symbols and then displaying a predetermined character or the like as a moving image on almost the entire display surface 41a.

[0117] The advance notice display includes a mode in which characters are displayed separately from the symbols on the symbol rows in a situation in which symbols are displayed in a variable manner in all symbol rows after the display surface 41a of the symbol display device 41 starts displaying the variable manner of symbols, or in a situation in which symbols are displayed in a variable manner in some symbol rows. It also includes a mode in which the background screen is displayed in a predetermined manner different from the previous manner, and a mode in which the symbols on the symbol rows are displayed in a predetermined manner different from the previous manner. Such advance notice display can occur in both a game in which a reach display is performed and a game in which a reach display is not performed, but is set to occur with a higher probability when a reach display is performed than when a reach display is not performed.

[0118] The reach display is executed regardless of the value of the reach random number counter C3 in a game round in which the same symbol combination is finally stopped and displayed. Also, in a game round corresponding to a big win result in which the same symbol combination is not stopped and displayed, it is not executed regardless of the value of the reach random number counter C3. Also, in a game round corresponding to a miss result, it is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main ROM 64 corresponds to the occurrence of the reach display.

[0119] On the other hand, the decision as to whether or not to display a notice is not made by the main control device 60 but by the audio and light emitting control device 81. In this case, the audio and light emitting control device 81 executes a lottery process for the notice display so that a game round corresponding to any jackpot result satisfies at least one of the conditions that a notice display is more likely to occur and that a notice display with a low occurrence rate is more likely to occur in a game round corresponding to a miss result. Incidentally, this lottery result is reflected when the performance for the game round is executed by the symbol display device 41.

[0120] Here, the probability of a reach display occurring in a game that results in a loss is the same regardless of the setting state of "Setting 1" to "Setting 6". This makes it possible to prevent any advantage or disadvantage from arising from the setting state of the pachinko machine 10 with respect to the probability of a reach display occurring in a game that results in a loss. However, this is not limited to this, and a configuration may be adopted in which the higher the setting value, the higher the probability of a reach display occurring in a game that results in a loss.

[0121] Next, the variation type counter CS will be described. The variation type counter CS is configured to be incremented by 1 in the range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variation type counter CS is used in determining the display duration in the special chart display unit 37a and the display duration of the pattern in the pattern display device 41 in the main CPU 63. The variation type counter CS is updated once each time a timer interrupt process described later is executed, and is repeatedly updated within the remaining time until the next timer interrupt process is executed. Then, the buffer value of the variation type counter CS is acquired when determining the variation pattern at the start of the variation display in the special chart display unit 37a and at the start of the variation of the pattern by the pattern display device 41.

[0122] <Processing configuration of the main CPU 63> Next, we will explain each process executed to progress the game by the master CPU 63. The processes of the master CPU 63 are roughly divided into main processes that are started when the power is turned on, and timer interrupt processes that are started periodically (every 4 millisecond period in this embodiment).

[0123] <Main processing> First, the main processing will be described with reference to the flowchart of FIG.

[0124] First, the power-on wait process is executed (step S101). In the power-on wait process, for example, the main process is started and a predetermined wait time (specifically, 1 second) elapses before proceeding to the next process. During the execution period of the power-on wait process, the operation start and initial setting of the pattern display device 41 are completed. After that, access to the main RAM 65 is permitted (step S102).

[0125] Thereafter, it is determined whether the setting key insertion section 68a is turned on (step S103). If the setting key insertion section 68a is not turned on (step S103: NO), it is determined whether the reset button 68c is pressed (step S104). If the reset button 68c is pressed (step S104: YES), each area of ​​the main RAM 65 is cleared to "0" except for the area in which the setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, and the area cleared to "0" is initialized (step S105). In other words, when the supply of operating power to the pachinko machine 10 is started while the reset button 68c is pressed without turning on the setting key insertion section 68a, the clearing process of the main RAM 65 is executed while the setting value information is maintained in the state before the supply of operating power to the pachinko machine 10 is stopped, and the initial setting is executed for the memory area in which the clearing process was executed. This makes it possible to initialize other areas of the main RAM 65 without changing the setting value. In step S105, various registers of the main CPU 63 are also cleared to "0" and then initialized.

[0126] If the reset button 68c is not pressed (step S104: NO), it is determined whether or not the power failure flag is set to "1" (step S106). The power failure flag is provided in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and a predetermined power failure process is normally executed, the power failure flag is set to "1". If the power failure flag is set to "1", it is determined whether or not the calculated checksum matches the checksum saved at the time of power cut, that is, the validity of the stored data (step S107). If the process of step S105 is executed or if a positive determination is made in step S107, it is determined whether or not the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or more, it is determined to be abnormal.

[0127] If a negative determination is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S109), and then an infinite loop is executed. The operation prohibition process is released by executing an all clear process (step S117) described later.

[0128] If the determination is affirmative in all of steps S106 to S108, a power-on setting process is executed (step S110). In the power-on setting process, a predetermined area of ​​the main RAM 65, such as the initialization of a power failure flag, is set to an initial value, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After the process of step S110 is executed, a recognition process (step S111) for making the management IC 66 recognize various information, and a data output process for outputting various data to an external device connected to the read terminal 68d of the MPU 62 are executed (step S112). The details of the recognition process and the data output process will be described later.

[0129] The main CPU 63 is configured to periodically execute timer interrupt processing, but when the main processing is started, timer interrupt processing is prohibited. This state in which timer interrupt processing is prohibited is released when the processing of step S112 is completed and before the processing of step S113 is executed, and execution of timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 is started, the data output processing of step S112 is completed, and timer interrupt processing is not executed until the stage before the processing of step S113 is started. Therefore, processing for progressing the game is not started in the main CPU 63 until the situation is reached.

[0130] Thereafter, the process proceeds to the remaining process of steps S113 to S116. That is, the main CPU 63 is configured to periodically execute timer interrupt processes, but there is a remaining time between one timer interrupt process and the next timer interrupt process. This remaining time varies depending on the processing completion time of each timer interrupt process, but this irregular time is utilized to repeatedly execute the remaining process of steps S113 to S116. In this respect, the remaining process of steps S113 to S116 can be said to be non-periodic processing that is executed non-periodically.

[0131] In the remaining process, first, in step S113, interrupt inhibition is set to inhibit occurrence of timer interrupt processing. In the following step S114, random number initial value update processing is executed to update the random number initial value counter CINI, and in step S115, fluctuation counter update processing is executed to update the fluctuation type counter CS. In these update processing, the current numerical value information is read from the corresponding counter in the main RAM 65, and the read numerical value information is incremented by 1, and then the counter from which it was read is overwritten. In this case, when the counter value exceeds the maximum value, each is cleared to "0". After that, in step S116, interrupt permission is set to switch from a state in which the occurrence of timer interrupt processing is inhibited to a state in which it is permitted. When the processing of step S116 is executed, the process returns to step S113, and the processing of steps S113 to S116 is repeated.

[0132] On the other hand, when the setting key insertion section 68a is turned ON (step S103: YES), all areas of the main RAM 65, including the areas in which the setting value information indicating the setting state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0" and the areas cleared to "0" are initialized (step S117). In other words, when an operation to change the setting state of the pachinko machine 10 is performed, all areas of the main RAM 65 are cleared to "0" even if the reset button 68c is not pressed, and the storage areas in which the clearing process has been performed are initialized. In addition, in step S117, various registers of the main CPU 63 are also cleared to "0" and then initialized. Note that this is not limited to this, and a configuration may be adopted in which, even when an operation to change the setting state of the pachinko machine 10 is performed, if the reset button 68c is not pressed, the all-clear process of the main RAM 65 is not executed, and if an operation to change the setting state of the pachinko machine 10 is performed and the reset button 68c is pressed, the all-clear process is executed.

[0133] Thereafter, in step S118, a set value update process is executed, and in step S119, a set value update signal output process is executed, and then the process proceeds to step S110. The set value update process is described below. The set value update signal output process is described in detail later. Fig. 10 is a flowchart showing the set value update process.

[0134] First, a setting value counter provided in the main RAM 65 is set to "1" (step S201). The setting value counter is a counter for the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the previous setting value.

[0135] Then, a process to start displaying the set value is executed (step S202). In the process to start displaying the set value, the display of the third notification display device 69c is controlled so that the number "1" corresponding to "Setting 1" is displayed. When changing the set value, the manager of the gaming hall can grasp the current setting state of the pachinko machine 10 by checking the third notification display device 69c.

[0136] Thereafter, on condition that the setting key insertion section 68a has not been turned OFF (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from a LOW level to a HI level. If a negative determination is made in step S204, the process returns to step S203, and it is determined whether the setting key insertion section 68a has been turned OFF.

[0137] If the update button 68b has been pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S206: YES), the setting value counter is set to "1" (step S207). As a result, the setting value is updated to the next higher setting every time the update button 68b is pressed once, and if the update button 68b is pressed once when the setting is "setting 6", the setting value will return to "setting 1".

[0138] If a negative determination is made in step S206, or if the process of step S207 is executed, a display update process of the set value is executed (step S208). In the display update process of the set value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the set value counter of the main RAM 65 is displayed. By checking the third notification display device 69c, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

[0139] After executing the process of step S208, the process returns to step S203, and it is determined whether the setting key insertion section 68a has been turned OFF. If the setting key insertion section 68a has not been turned OFF (step S203: NO), the process of step S204 and the following steps is executed again. If the setting key insertion section 68a has been turned OFF (step S203: YES), a process of ending the display of the setting value is executed (step S209). In the process of ending the display of the setting value on the third notification display device 69c, the display of the setting value is ended.

[0140] <Timer interrupt processing> Next, the timer interrupt process will be described with reference to the flowchart of Fig. 11. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

[0141] First, the power failure information storage process is executed (step S301). In the power failure information storage process, it is monitored whether a power failure signal corresponding to the occurrence of a power cut is received from the power failure monitoring board 67, and if the occurrence of a power failure is identified, the power failure process is executed and then an infinite loop is entered. In the power failure process, the power failure flag in the main RAM 65 is set to "1", and the checksum is calculated and the calculated checksum is saved.

[0142] After that, a lottery random number update process is executed (step S302). In the lottery random number update process, the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power role opening counter C4 are updated. Specifically, the current numerical information is read out sequentially from the winning random number counter C1, the big win type counter C2, the reach random number counter C3, and the normal power role opening counter C4, and after executing a process of adding 1 to each of the read numerical information, a process of overwriting the counter from which it was read out is executed. In this case, when the counter value exceeds the maximum value, each is cleared to "0". After that, in step S303, a random number initial value update process is executed as in step S114, and in step S304, a variable counter update process is executed as in step S115.

[0143] Thereafter, a fraud detection process is executed to monitor whether or not a predetermined event set as a target for fraudulent use has occurred (step S305). In the fraud detection process, the occurrence of multiple types of events is monitored, and when it is confirmed that a predetermined event has occurred, a game stop flag provided in the main RAM 65 is set to "1". In the following step S306, it is determined whether or not the game progress has been stopped by determining whether or not the game stop flag has been set to "1". If a negative determination is made in step S306, the process from step S307 onwards is executed.

[0144] In step S307, a port output process is executed. In the port output process, when output information has been set in the previous timer interrupt process, a process is executed to output corresponding to the output information to the various drive units 32b, 34b. For example, when information is set to switch the special power winning device 32 to an open state, the output of a drive signal to the drive unit 32b for special power is started, and when information is set to switch to a closed state, the output of the drive signal is stopped. Also, when information is set to switch the normal power role 34a of the second operating port 34 to an open state, the output of a drive signal to the drive unit 34b for normal power is started, and when information is set to switch to a closed state, the output of the drive signal is stopped.

[0145] After that, a read process is executed (step S308). In the read process, signals other than the power failure signal and the winning signal are read, and the read information is stored for use in the subsequent processes.

[0146] After that, a ball entry detection process is executed (step S309). In the ball entry detection process, signals received from the ball entry detection sensors 42a to 49a are read, and based on the read results, the presence or absence of balls entering the out gate 24a, the general winning gate 31, the special electric winning device 32, the first operating gate 33, the second operating gate 34, and the through gate 35 is identified. Details of the ball entry detection process will be described later.

[0147] Thereafter, a timer update process is executed to collectively update the numerical information of multiple types of timer counters provided in the main RAM 65 (step S310). In this case, the timer counters in which the stored numerical information is updated by subtraction are handled collectively, but it is also possible to collectively update both the subtractive timer counters and the additive timer counters.

[0148] Then, a launch control process is executed to control the launch of game balls (step S311). In a state where the launch operation to the launch operation device 28 is continued, one game ball is launched at a predetermined launch cycle of 0.6 seconds. In the following step S312, as an input state monitoring process, based on the information read in the reading process of step S308, a disconnection check is performed for each ball entry detection sensor 42a to 49a, and an opening check is performed for the gaming machine main body 12 and the front door frame 14.

[0149] Thereafter, a special chart special electricity control process is executed to control the execution of a game round and the execution of an open / close execution mode (step S313). The special chart special electricity control process will be described in detail later.

[0150] Then, the normal map normal power control process is executed (step S314). In the normal map normal power control process, when a winning entry to the through gate 35 occurs, a process is executed to acquire the reserved information on the normal map side, and when the reserved information on the normal map side is stored, an opening judgment is made for the reserved information, and further, a process is executed to perform a performance for the normal map using the opening judgment as a trigger. Also, based on the result of the opening judgment, a process is executed to open and close the normal power role 34a of the second operating port 34. In this case, if the support mode is the low frequency support mode, a corresponding process is executed, and if the support mode is the high frequency support mode, a corresponding process is executed. Also, when the opening and closing execution mode is selected, the support mode immediately before that becomes the low frequency support mode even if it was the high frequency support mode.

[0151] In the next step S315, based on the processing results of the previous steps S313 and S314, output information is set to reflect the increase / decrease in the reserved information related to the special drawing display unit 37a in the special drawing reserved display unit 37b, and output information is set to reflect the increase / decrease in the reserved information related to the ordinary drawing display unit 38a in the ordinary drawing reserved display unit 38b. Also, in step S315, based on the processing results of the previous steps S313 and S314, output information is set to update the display contents of the special drawing display unit 37a, and output information is set to update the display contents of the ordinary drawing display unit 38a.

[0152] Then, the contents of the command and signal received from the payout control device 77 are confirmed, and a payout status receiving process is executed to perform processing corresponding to the confirmation result (step S316). Also, a payout output process is executed to set the prize ball command as an output target (step S317). Also, an external information setting process is executed to control the start and end of the output of an external signal according to the processing results of various processes executed in this timer interrupt process (step S318). Then, a management output process is executed to output information corresponding to the ball entry result in the game area PA to the management IC 66 (step S319). The details of the management output process will be described later.

[0153] Next, the special picture special electricity control process in step S313 will be described with reference to the flowchart of FIG.

[0154] First, the process of acquiring reserved information is executed (step S401). In the process of acquiring reserved information, it is determined whether or not a winning has occurred in the first actuation port 33 or the second actuation port 34, and if a winning has occurred, it is determined whether or not the number of reserved balls in the reserved ball storage area 65a is less than the upper limit ("4" in this embodiment). If the number of reserved balls is less than the upper limit, the number of reserved balls is incremented by 1, and the numerical information of the winning random number counter C1, the big win type counter C2, and the reach random number counter C3 updated in the previous step S302 is stored in the first reserved area among the empty reserved areas RE1 to RE4 in the reserved ball area RE. If winning balls have occurred simultaneously in the first actuation port 33 and the second actuation port 34, the process of acquiring the reserved information is executed multiple times within the range of executing the process of acquiring reserved information once. If new reserved information is acquired, a corresponding acquisition command is sent to the sound and light emission control device 81. When the audio and light emission control device 81 receives this command, it updates the image displayed on the pattern display device 41 indicating the number of pending information items to display content corresponding to the increase in the number of pending information items.

[0155] Then, the information of the special picture special electric counter provided in the main RAM 65 is read (step S402), and the special picture special electric address table provided in the main ROM 64 is read (step S403). Then, a start address corresponding to the information of the special picture special electric counter is obtained from the special picture special electric address table (step S404), and the process jumps to the process indicated by the obtained start address among the processes of steps S406 to S412 (step S405). The special picture special electric counter is a counter for the main CPU 63 to grasp which of the various processes of steps S406 to S412 should be executed, and the special picture special electric address table is set with the start address of the program for executing the processes of steps S406 to S412 in correspondence with the numerical information of the special picture special electric counter.

[0156] In step S406, a special chart change start process is executed. FIG 13 is a flowchart showing the special chart change start process.

[0157] In the special chart change start process, the number of reserved information stored in the reserved area RE is 1 or more (step S501: YES), and the data setting process is executed (step S502). In the data setting process, the reserved number is first subtracted by 1, and the data stored in the first reserved area RE1 of the reserved area RE is moved to the execution area AE. Then, the process of shifting the data stored in each reserved area RE1 to RE4 of the reserved area RE is executed. This data shift process is a process of shifting the data stored in the first reserved area RE1 to the fourth reserved area RE4 to the lower area side in order, and in detail, the data in each area is shifted from the second reserved area RE2 to the first reserved area RE1, the third reserved area RE3 to the second reserved area RE2, the fourth reserved area RE4 to the third reserved area RE3, and then the fourth reserved area RE4 is cleared to "0". At this time, a shift command is sent to the voice light emission control device 81 to recognize that the data in the reserved area has been shifted. When the audio and light emission control device 81 receives this command, it updates the image displayed on the pattern display device 41 indicating the number of pending information items to a display content corresponding to a reduction in the number of pending information items.

[0158] After executing the data setting process, the win / lose table is read from the main ROM 64 (step S503). Specifically, first, information indicating the win / lose selection mode is read from the main RAM 65 to grasp the current win / lose selection mode. If it is the high probability mode, the high probability win / lose table 64g is read from the main ROM 64. On the other hand, if it is the low probability mode, the setting state of the pachinko machine 10 is grasped by reading the value of the setting value counter in the main RAM 65. Then, the low probability win / lose tables 64a to 64f corresponding to the grasped setting value are read from the main ROM 64.

[0159] Then, the winning / losing table 64a-64g read in step S503 is referred to to execute the winning / losing determination process (step S504). In the winning / losing determination process, it is determined whether the winning / losing determination information among the information stored in the execution area AE, that is, the numerical information related to the winning random number counter C1, matches the jackpot numerical information set in the winning / losing table 64a-64g read in step S503.

[0160] If the result of the win / loss determination process is a jackpot winning result (step S505: YES), an allocation determination process is executed (step S506). In the allocation determination process, information for allocation determination from the information stored in the execution area AE, that is, numerical information related to the jackpot type counter C2 is read. Then, by referring to the allocation table 64h provided in the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out above corresponds to. Specifically, it is determined which jackpot result it corresponds to among a low probability jackpot result, a low prize winning high probability jackpot result, and a most favorable jackpot result.

[0161] Then, the stop result setting process for the big win result is executed (step S507). Specifically, the information on the form of the pattern to be finally stopped and displayed on the special chart display unit 37a in the game round related to the start of the current variation is specified from the stop result table for the big win result stored in advance in the main ROM 64, and the specified information is written to the main RAM 65. In this stop result table for the big win result, the information on the form of the pattern to be stopped and displayed on the special chart display unit 37a is set differently for each type of big win result.

[0162] Then, a flag set process corresponding to the distribution determination result is executed (step S508). Specifically, flags corresponding to the types of each jackpot result are provided in the main RAM 65, and in step S508, the flag corresponding to the result of the distribution determination process in step S506 is set to "1".

[0163] On the other hand, if it is determined in step S505 that the result is not a jackpot, a stop result setting process for a loss result is executed (step S509). Specifically, the information on the pattern to be finally stopped and displayed on the special chart display unit 37a in the game round related to the start of the current variation is specified from the stop result table for loss results stored in advance in the main ROM 64, and the specified information is written to the main RAM 65. The information on the pattern type selected in this case is different from the information on the pattern type selected in the case of a jackpot result.

[0164] After executing either the process of step S508 or step S509, a process of grasping the duration of the game round is executed (step S510). In this process, the numerical information of the fluctuation type counter CS is acquired. Also, it is judged whether or not a reach display occurs in the current game round on the pattern display device 41. Specifically, if the game round related to the start of the current fluctuation has a low probability jackpot result or a most favorable jackpot result, it is judged that a reach display will occur. Also, if there is no jackpot result and furthermore the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is judged that a reach display will occur.

[0165] When it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game corresponding to the current numerical information of the variation type counter CS. On the other hand, when it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game corresponding to the current numerical information of the variation type counter CS. Incidentally, the duration of the game that can be obtained by referring to the reach non-occurrence duration table is different from the duration of the game that can be obtained by referring to the reach occurrence duration table.

[0166] The duration of the game rounds when the reach does not occur is set so that the more the number of reserved information stored in the reserved area RE, the shorter the duration of the game rounds. In addition, the non-reach duration table is set so that a shorter duration of the game rounds is selected in a situation where the support mode is a high-frequency support mode than in a situation where the number of reserved information is the same, compared with a situation where the support mode is a low-frequency support mode. However, this is not limited to this, and the duration of the game rounds may not change depending on the number of reserved information or the support mode, and the above relationship may be reversed. Furthermore, the above configuration may be applied to the duration of the game rounds when the reach occurs. In addition, the duration table may be set separately for each of various jackpot results, the case of a miss reach, and the case of a miss result without the reach occurring. In this case, the duration of the game rounds is allocated according to each game result.

[0167] Then, the information on the duration of the game acquired in step S510 is set in the special chart special electricity timer counter provided in the main RAM 65 (step S511). The update of the numerical information set in the special chart special electricity timer counter is executed in the timer update process (step S310). Incidentally, as a performance for a game, the display of the variation of the pattern in the special chart display unit 37a and the display of the variation of the pattern in the pattern display device 41 are performed, and when each of these variation displays is ended, the final stop display is performed for the final stop period (for example, 0.5 seconds) in a state in which the stop result of the game is displayed (in the pattern display device 41, a predetermined combination of patterns is waiting on the effective line). In this case, the duration of the game acquired in step S510 is the total time for one game.

[0168] Thereafter, the variation command and the type command are transmitted to the sound and light emission control device 81 (step S512). The variation command includes information on the duration of the game round. Here, as described above, the duration of the game round obtained by referring to the non-reach duration table is different from the duration of the game round obtained by referring to the reach duration table. Therefore, even if the variation command does not include information on the occurrence of a reach, the sound and light emission control device 81 can identify the occurrence of a reach from the information on the duration of the game round. In this regard, it can be said that the variation command includes information indicating the occurrence of a reach. Note that the variation command may include information directly indicating the occurrence of a reach. Also, the type command includes information on the game result.

[0169] When the sound and light emission control device 81 receives the variation command and the type command from the main CPU 63, it causes the display light emitting unit 53, the speaker unit 54, and the pattern display device 41 to execute the presentation for the game round. In this case, the presentation for the game round is executed in a manner corresponding to the contents of the variation command and the type command. Also, the pattern display device 41 displays the variation of the patterns as the presentation for the game round, and when the presentation for the game round ends, the combination of patterns corresponding to the results of the win / loss determination process and the allocation determination process is displayed in a stopped state.

[0170] Then, the display of the changing pattern in the special chart display section 37a is started (step S513). Then, the special chart special electricity counter is incremented by 1 (step S514). In this case, since the numerical information of the special chart special electricity counter is "0" when the special chart change start process is executed, the numerical information of the special chart special electricity counter becomes "1". Then, the eleventh output flag provided in the main RAM 65 is set to "1" (step S515). The eleventh output flag is a flag for specifying in the main CPU 63 that information output indicating that a game round has started should be executed to the management IC 66.

[0171] Returning to the explanation of the special chart special electricity control process (FIG. 52), in step S407, a special chart change process is executed. In the special chart change process, it is determined whether or not it is during the duration of the game round and before the final stop display, and if it is before the final stop display, a process is executed to regularly change the display mode of the picture in the special chart display section 37a. When it is time to display the final stop, the numerical information of the special chart special electricity counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart change process to that corresponding to the special chart determination process. In this embodiment, the final stop command is not transmitted from the main CPU 63 to the sound and light emission control device 81.

[0172] In step S408, a special chart determination process is executed. In the special chart determination process, the display mode of the image on the special chart display unit 37a is changed to a display mode corresponding to the lottery result of the current game round. In addition, in the special chart determination process, it is determined whether the final stop period has elapsed, and if the period has elapsed, it is determined whether a transition to the opening and closing execution mode will occur. If a transition to the opening and closing execution mode does not occur, the numerical information of the special chart special electricity counter is cleared to "0". If a transition to the opening and closing execution mode occurs, the numerical information of the special chart special electricity counter is incremented by 1, thereby updating the numerical information of the counter from that corresponding to the special chart determination process to that corresponding to the special electricity start process.

[0173] In step S409, the special power start process is executed. In the special power start process, if the process for starting the opening period in the current open / close execution mode has not yet been executed, the process for setting the opening period is executed. In addition, an opening command is sent to the sound and light emission control device 81. By receiving the opening command, the sound and light emission control device 81 causes the display light-emitting unit 53, the speaker unit 54, and the pattern display device 41 to execute the opening performance. If the opening period has elapsed, a start process for starting the first round of play is executed. In the start process, the special power winning device 32 is opened and the end condition of the round of play is set. When setting this end condition, the upper limit continuation period for continuing the special power winning device 32 in the open state in the current first round of play is set, and the upper limit number of game balls that can be won in the special power winning device 32 in the current first round of play is set in the winning number counter provided in the main RAM 65.

[0174] In step S410, the special line open process is executed. In the special line open process, it is determined whether or not the end condition of the round game is satisfied. If the end condition is satisfied, the special line winning device 32 is closed. If the currently ended round game is not the last round game executed, the numerical information of the special chart special line counter is incremented by 1 to update the numerical information of the counter from that corresponding to the special line open process to that corresponding to the special line closed process, and if the currently ended round game is the last round game executed, the numerical information of the special chart special line counter is incremented by 2 to update the numerical information of the counter from that corresponding to the special line open process to that corresponding to the special line end process.

[0175] In step S411, special line closed processing is executed. In the special line closed processing, it is determined whether or not the interval period between rounds of play has elapsed. The interval period is set when the previous round of play ends. When the interval period has elapsed, the special line winning device 32 is opened and the end condition of the round of play is set. Then, the numerical information of the special chart special line counter is subtracted by 1, thereby updating the numerical information of the counter from that corresponding to the special line closed processing to that corresponding to the special line open processing.

[0176] In step S412, a special call termination process is executed. In the special call termination process, if the process for starting the ending period in the current opening / closing execution mode has not yet been executed, the ending period (e.g., 5 seconds) is set and an ending command is sent to the sound and light emission control device 81. By receiving the ending command, the sound and light emission control device 81 causes the display light emitting unit 53, the speaker unit 54, and the pattern display device 41 to execute an ending performance. When the ending period has elapsed, the win / lose lottery mode and the support mode after the end of the opening / closing execution mode are each set to a mode corresponding to the jackpot result that triggered the start of the current opening / closing execution mode.

[0177] Next, a configuration will be described for the main CPU 63 to determine whether or not game balls have entered the out hole 24a, the general winning hole 31, the special winning device 32, the first operating hole 33, the second operating hole 34, and the through gate 35 based on the detection results of the ball entry detection sensors 42a to 49a. Fig. 14 is an explanatory diagram for explaining a configuration for inputting the detection results of the ball entry detection sensors 42a to 49a to the main CPU 63.

[0178] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so as to be able to handle eight types of signals simultaneously. An area in which information "0" or "1" is stored according to the voltage of each signal is provided in one-to-one correspondence with each terminal. That is, the area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals are input to the input port 63a, in order to limit the number of signals that are input simultaneously to eight types, the group of signals to be input to the input port 63a is switched through switching control by a driver IC.

[0179] In the ball entry detection process (step S309) of the timer interrupt process (FIG. 11), the signal group to be input to the input port 63a is set to the signal group from each ball entry detection sensor 42a-49a. In a situation where such a setting is made, the 0th bit D0 stores information corresponding to the detection signal from the first winning opening detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the second winning opening detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the third winning opening detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special electric detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the first operation opening detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the second operation opening detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the out opening detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0180] When the ball entrance detection sensors 42a to 49a do not detect the passage of a game ball, they output a LOW level signal indicating that the ball is not being detected as a detection signal, and when the ball entrance detection sensors 42a to 49a detect the passage of a game ball, they output a HI level signal indicating that the ball is being detected as a detection signal. When the ball entrance detection sensors 42a to 49a receive a LOW level signal, they store "0" information in the corresponding bit, and when the ball entrance detection sensors 42a to 49a receive a HI level signal, they store "1" information in the corresponding bit. In other words, when the ball entrance detection sensors 42a to 49a do not detect the passage of a game ball, they store "0" information in the corresponding bit, which corresponds to the information indicating that the ball is not being detected, and when the ball entrance detection sensors 42a to 49a detect the passage of a game ball, they store "1" information in the corresponding bit, which corresponds to the information indicating that the ball is being detected.

[0181] FIG. 15 is a flowchart showing the ball scoring detection process executed in step S309 of the timer interrupt process (FIG. 11).

[0182] When it is confirmed that the 0th bit D0 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first winning hole detection sensor 42a (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S603). The first output flag is a flag for the main CPU 63 to specify that information output indicating that one game ball has been detected by the first winning hole detection sensor 42a should be executed to the management IC 66. The 10-ball counter is a counter for the main CPU 63 to specify the number of times that the 10 game balls should be paid out. If the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (FIG. 11), and when the 10 prize ball command is output once, the value of the 10 prize ball counter is decremented by 1. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0183] When it is confirmed that the first bit D1 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second winning hole detection sensor 43a (step S604: YES). In this case, the second output flag provided in the main RAM 65 is set to "1" (step S605), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S606). The second output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the second winning hole detection sensor 43a should be executed to the management IC 66.

[0184] When it is confirmed that the second bit D2 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the third winning hole detection sensor 44a (step S607: YES). In this case, the third output flag provided in the main RAM 65 is set to "1" (step S608), and the value of the 10-ball counter provided in the main RAM 65 is incremented by 1 (step S609). The third output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the third winning hole detection sensor 44a should be executed to the management IC 66.

[0185] When it is confirmed that the third bit D3 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the special electric detection sensor 45a (step S610: YES). In this case, the special electric winning flag provided in the main RAM 65 is set to "1" (step S611), the fourth output flag provided in the main RAM 65 is set to "1" (step S612), and the value of the 15-ball counter provided in the main RAM 65 is incremented by 1 (step S613). The special electric winning flag is a flag for the main CPU 63 to specify that one game ball has entered the special electric winning device 32 in a round game in the open / close execution mode. In the special chart special electric control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the special electric winning flag is set to "1", it is determined that one game ball has entered the special electric winning device 32, and the number of remaining balls that can enter the special electric winning device 32 in a round game is subtracted by 1. When the process of subtracting 1 from the number of balls that can enter is executed, the special electric winning flag is cleared to "0". The fourth output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the special electric detection sensor 45a should be executed to the management IC 66. The 15-ball counter is a counter for specifying in the main CPU 63 the number of times that 15 game balls should be paid out. If the value of the 15 prize ball counter is 1 or more, a 15 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (FIG. 11), and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0186] When it is confirmed that the fourth bit D4 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the first actuation port detection sensor 46a (step S614: YES). In this case, the first actuation winning flag provided in the main RAM 65 is set to "1" (step S615), the fifth output flag provided in the main RAM 65 is set to "1" (step S616), and the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S617). The first actuation winning flag is a flag for the main CPU 63 to specify that one game ball has entered the first actuation port 33. In the special chart special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the first operation winning flag is set to "1", a process for newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit number of 4. In the special power special power control process (step S313), it is confirmed that the first operation winning flag is set to "1", and when the process corresponding to the confirmation is executed, the first operation winning flag is cleared to "0". The fifth output flag is a flag for specifying in the main CPU 63 that the information output indicating that one game ball has been detected by the first operation port detection sensor 46a should be executed to the management IC 66. The one prize ball counter is a counter for specifying in the main CPU 63 the number of times that one game ball should be paid out. When the value of the 1 prize ball counter is 1 or more, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (FIG. 11), and when the 1 prize ball command is output once, the value of the 1 prize ball counter is decremented by 1. When the payout control device 77 receives the 1 prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0187] When it is confirmed that the fifth bit D5 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the second operation port detection sensor 47a (step S618: YES). In this case, the second operation winning flag provided in the main RAM 65 is set to "1" (step S619), the sixth output flag provided in the main RAM 65 is set to "1" (step S620), and the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S621). The second operation winning flag is a flag for the main CPU 63 to specify that one game ball has entered the second operation port 34. In the special chart special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the second operation winning flag is set to "1", a process for newly storing the reserved information is executed on the condition that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power special power control process (step S313), it is confirmed that the second operation winning flag is set to "1", and when the process corresponding to the confirmation is executed, the second operation winning flag is cleared to "0". The sixth output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the second operation port detection sensor 47a should be executed to the management IC 66.

[0188] When it is confirmed that the sixth bit D6 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one game ball has been detected by the outlet detection sensor 48a (step S622: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S623). The seventh output flag is a flag for specifying in the main CPU 63 that information output indicating that one game ball has been detected by the outlet detection sensor 48a should be executed to the management IC 66.

[0189] When it is confirmed that the seventh bit D7 has switched from a state in which "0" information is stored to a state in which "1" information is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, the gate winning flag provided in the main RAM 65 is set to "1" (step S625). The gate winning flag is a flag for the main CPU 63 to specify that one game ball has entered the through gate 35. In the normal map normal power control process (step S314) of the timer interrupt process (FIG. 11), by confirming that the gate winning flag is set to "1", the process is executed to store the current numerical information of the normal power role release counter C4 as the normal map side reserved information in the normal power reserve area 65c, provided that the number of reserved information on the normal map side stored in the normal power reserve area 65c is less than the upper limit of four. In the normal map normal power control process (step S314), it is confirmed that the gate winning flag is set to "1", and when the process corresponding to that confirmation is executed, the gate winning flag is cleared to "0".

[0190] As already explained, the timer interrupt process (FIG. 11) is started at a 4 millisecond cycle, so when one ball entry sensor 42a-49a starts detecting one game ball, the main CPU 63 specifies that one game ball has been detected by the ball entry sensor 42a-49a while the ball entry sensor 42a-49a continues to detect the one game ball. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0191] Next, a description will be given of the processing executed by the dispensing control device 77. First, the electrical configuration of the dispensing control device 77 and various devices that communicate with the dispensing control device 77 will be described with reference to the block diagram of FIG.

[0192] The dispensing control device 77 is equipped with an MPU 91. In addition to a dispensing side CPU 92, which is a processing device including a control unit and a calculation unit, the MPU 91 also includes a dispensing side ROM 93, a dispensing side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, and the like.

[0193] The dispensing ROM 93 is a memory (i.e., a non-volatile memory means) that does not require an external power supply to retain memory such as a NOR type flash memory or a NAND type flash memory, and is used for read-only purposes. The dispensing ROM 93 stores various control programs and fixed value data executed by the dispensing CPU 92.

[0194] The dispensing side RAM 94 is a memory (i.e., a volatile memory means) that requires an external power supply to retain memory such as SRAM and DRAM, and is used for both reading and writing. The dispensing side RAM 94 is randomly accessible, and when compared with the dispensing side ROM 93 for the same data capacity, it takes less time to read data. The dispensing side RAM 94 temporarily stores various data for the execution of the control program stored in the dispensing side ROM 93.

[0195] The payout side CPU 92 is capable of two-way communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout side CPU 92 drives and controls the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. In addition, the payout side CPU 92 monitors whether or not the game balls can be paid out normally, and when it is determined that the game balls cannot be paid out normally, it stops the payout device 76 even if the payout side RAM 94 stores information on the number of prize balls that have not been paid out. In addition, the payout side CPU 92 transmits a payout limit command to the main CPU 63 indicating that the game balls cannot be paid out normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the sound and light emission control device 81 so that a notification indicating that the game balls cannot be paid out normally is executed by the pattern display device 41, the display light emission unit 53, and the speaker unit 54. States in which it is not possible to normally dispense game balls include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been replenished with game balls, an abnormal dispense state in which the dispensing device 76 is not operating normally, a main body open state in which the gaming machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

[0196] A full tank detection sensor (not shown) is provided in the middle of the game ball passage leading from the payout device 76 to the lower tray 56a, and the detection result of the full tank detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

[0197] A no-ball detection sensor (not shown) is provided at a midpoint of the game ball passage leading from tank 75 to payout device 76, and the detection result of the no-ball detection sensor is input to payout side CPU 92. Payout side CPU 92 determines that a no-ball state exists when the no-ball detection sensor continues to not detect a game ball, and determines that the no-ball state has been released when the state in which the no-ball detection sensor continues to not detect a game ball is released.

[0198] The payout device 76 is provided with a payout detection sensor (not shown) for detecting game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout side CPU 92. When a game ball is detected by the payout detection sensor, the payout side CPU 92 determines that one game ball has been paid out from the payout device 76. Furthermore, the payout side CPU 92 determines that an abnormal payout state exists when a game ball is continuously not detected by the payout detection sensor despite the payout device 76 being driven and controlled so that a game ball is paid out, and determines that the abnormal payout state has been released when the state in which a game ball is continuously not detected by the payout detection sensor is released.

[0199] A front door open sensor 95 is provided on the front part of the inner frame 13 (see FIG. 2), and the detection result of the front door open sensor 95 is input to the dispensing side CPU 92. In this case, when the front door frame 14 is in a closed state relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing side CPU 92, and when the front door frame 14 is in an open state relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing side CPU 92. When the dispensing side CPU 92 receives a closed detection signal from the front door open sensor 95, it determines that the front door frame 14 is in a closed state, and when it receives an open detection signal from the front door open sensor 95, it determines that the front door frame 14 is in an open state. In addition, the dispensing side CPU 92 transmits a front door open command to the main side CPU 63 at the timing when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main side CPU 63 at the timing when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when a front door open command is received, and determines that the front door frame 14 is in a closed state when a front door close command is received.

[0200] A main body open sensor 96 is provided on the front part of the back pack unit 15 (see FIG. 2), and the detection result of the main body open sensor 96 is input to the payout side CPU 92. In this case, when the gaming machine main body 12 is in a closed state relative to the outer frame 11, the main body open sensor 96 transmits a closed detection signal to the payout side CPU 92, and when the gaming machine main body 12 is in an open state relative to the outer frame 11, the main body open sensor 96 transmits an open detection signal to the payout side CPU 92. When the payout side CPU 92 receives a closed detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in a closed state, and when the payout side CPU 92 receives an open detection signal from the main body open sensor 96, it determines that the gaming machine main body 12 is in an open state. In addition, the payout side CPU 92 transmits a main body open command to the main side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body close command to the main side CPU 63 at the timing when it determines that the gaming machine main body 12 has changed from an open state to a closed state. The main CPU 63 determines that the gaming machine main body 12 is in the open state when it receives a main body open command, and determines that the gaming machine main body 12 is in the closed state when it receives a main body close command.

[0201] The timer interrupt process executed by the dispensing CPU 92 will be described with reference to the flowchart of Fig. 17. The timer interrupt process is repeatedly started at a predetermined cycle (for example, every 2 milliseconds).

[0202] First, the full tank process is executed (step S701). In the full tank process, as already explained, it is determined whether the tank is full based on the detection result of the full tank detection sensor, and if the tank is full, it executes a process to stop the payout of game balls and transmits a command indicating the full tank state to the main CPU 63. Also, if the full tank state is released, it executes a process to enable the payout of game balls and transmits a command indicating that the full tank state has been released to the main CPU 63.

[0203] Thereafter, the no-ball process is executed (step S702). In the no-ball process, as already explained, it is determined whether or not the state is a no-ball state based on the detection result of the no-ball detection sensor, and if the state is a no-ball state, it executes a process to stop the payout of game balls and transmits a command indicating the no-ball state to the main CPU 63. In addition, if the no-ball state is released, it executes a process to enable the payout of game balls and transmits a command indicating that the no-ball state has been released to the main CPU 63.

[0204] Thereafter, a payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already described, it is determined whether or not a payout abnormality state exists based on the detection result of the payout detection sensor, and if a payout abnormality state exists, a process for stopping the payout of game balls is executed and a command indicating that a payout abnormality state exists is sent to the main CPU 63. In addition, if the payout abnormality state is released, a process for enabling the payout of game balls is executed and a command indicating that the payout abnormality state has been released is sent to the main CPU 63.

[0205] Thereafter, a front door open monitoring process is executed (step S704). In the front door open monitoring process, as already described, it is determined whether the front door frame 14 is open or not based on the detection result of the front door open sensor 95, and if the front door frame 14 is open, a process for stopping the payout of game balls is executed and a front door open command is sent to the main CPU 63. In addition, if the front door frame 14 is closed, a process for enabling the payout of game balls is executed and a front door close command is sent to the main CPU 63.

[0206] Thereafter, a main body open monitoring process is executed (step S705). In the main body open monitoring process, as already described, it is determined whether the gaming machine main body 12 is in an open state based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is in an open state, a process for stopping the payout of game balls is executed and a main body open command is sent to the main CPU 63. In addition, if the gaming machine main body 12 is closed, a process for enabling the payout of game balls is executed and a main body close command is sent to the main CPU 63.

[0207] Then, a command read process is executed (step S706). In the command read process, a process of reading the prize ball command transmitted by the main CPU 63 is executed, and the prize ball command is stored in the payout RAM 94. Then, after executing a prize ball setting process for adding the number corresponding to the received prize ball command to the unpaid prize ball number information in the payout RAM 94 (step S707), a payout control process for controlling the execution of the payout of game balls by the payout device 76 is executed (step S708). In the payout control process, when the unpaid prize ball number information stored in the payout RAM 94 is a value of 1 or more, the payout device 76 is driven and controlled, and when the payout detection sensor detects one game ball, the value of the prize ball number information is subtracted by 1. Then, when the value of the prize ball number information becomes "0", the drive control of the payout device 76 is stopped. Thereafter, an external information setting process is executed to control the start and end of output of an external signal according to the results of various processes executed in the current timer interrupt process (step S709).

[0208] Next, a configuration for externally outputting information from the pachinko machine 10 to a hall computer HC installed in the gaming hall will be described.

[0209] As shown in Fig. 2, the back pack unit 15 is provided with an external terminal board 97. The external terminal board 97 is provided with a large number of external terminals, some of which, i.e., a plurality of external terminals, are electrically connected to the main CPU 63, and some of which, i.e., a plurality of external terminals, are electrically connected to the dispensing CPU 92. In this manner, each of the main CPU 63 and the dispensing CPU 92 is electrically connected to the external terminal board 97, so that the main CPU 63 and the dispensing CPU 92 can externally output information to the hall computer HC, as shown in Fig. 16.

[0210] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and one external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. In detail, a signal relay board 98 is provided at a midpoint of the signal path from the front door open sensor 95 to the dispensing side CPU 92. The signal relay board 98 is provided with a branch path SL2 that branches from the signal path SL1 from the front door open sensor 95 to the dispensing side CPU 92. The branch path SL2 is connected to an external terminal for opening the front door on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the front door open sensor 95 is not only input to the dispensing side CPU 92, but also input to the external terminal for opening the front door on the external terminal board 97. This makes it possible to externally output a signal indicating whether the front door frame 14 is in an open state to the hall computer HC without being controlled by the dispensing side CPU 92.

[0211] Regarding the main body open sensor 96 in detail, a branch path SL4 is provided on the signal relay board 98, which branches off from a signal path SL3 extending from the main body open sensor 96 toward the payout side CPU 92. The branch path SL4 is connected to an external terminal for main body opening on the external terminal board 97. Therefore, an electric signal corresponding to the detection result of the main body open sensor 96 is not only input to the payout side CPU 92, but also input to the external terminal for main body opening on the external terminal board 97. This makes it possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through the control of the payout side CPU 92.

[0212] Next, a description will be given of the contents of information externally output from the main CPU 63 and the payout CPU 92 to the hall computer HC. First, a description will be given of the contents of information externally output from the main CPU 63 to the hall computer HC.

[0213] In the external information setting process (step S318) in the timer interrupt process (FIG. 11), the main CPU 63 performs information output settings to each external terminal assigned to the main CPU 63 on the external terminal board 97. The information output from the main CPU 63 to the external terminal board 97 includes information indicating that the opening / closing execution mode is in progress, information indicating that the support mode is in the high frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (e.g., 100 balls) of game balls have been discharged from the game area PA through any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34, information indicating that a game ball has entered the first operating port 33, and information indicating that a game ball has entered the second operating port 34.

[0214] In the external information setting process (step S709) in the timer interrupt process (FIG. 17), the payout side CPU 92 performs setting for outputting information to each external terminal assigned to the payout side CPU 92 in the external terminal board 97. The information output from the payout side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0215] The hall computer HC can grasp the manner in which the game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, The payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10 - Ball payout rate in normal game mode other than the open / close execution mode and the high frequency support mode (hereinafter, this ball payout rate will be referred to as "B") -Ball payout rate in open / close execution mode - Payout rate in high frequency support mode The number of times a game is played until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S") BS x "number of winning balls for winning into the first actuation port 33 and the second actuation port 34" The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S1") The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio is referred to as "S2") B-(S1 x "number of winning balls for winning into the first operating port 33" + S2 x "number of winning balls for winning into the second operating port 34") Probability of opening / closing execution mode occurring per unit of play Probability of high frequency support mode occurring per unit of play The hall computer HC is thereby able to manage the manner in which game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are paid out when one game ball enters the corresponding ball entry section.

[0216] <Configuration for managing winning status of gaming balls> Next, a description will be given of a configuration for managing a game history using the management IC 66. First, the electrical configuration of the management IC 66 will be described with reference to the block diagram of FIG.

[0217] As already explained, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition to these, the MPU 62 also includes an I / F 101, and the read terminal 68d already explained.

[0218] The I / F 101 is an interface for transmitting and receiving signals between the MPU 62 and external devices. The I / F 101 is electrically connected to the main CPU 63 via the internal bus 103. Through the input port of the I / F 101, the detection results from the sensors such as the ball entry detection sensors 42a-49a and the commands from the payout side CPU 92 are input to the MPU 62, and various processes are executed by the main CPU 63 as described above based on the input detection results and the contents of the commands. In addition, when a signal is output to a device such as the special power drive unit 32b as a result of the execution of various processes by the main CPU 63, the signal output is performed through the output port of the I / F 101, and when a command is output to the payout side CPU 92 and the sound and light emission control device 81 as a result of the execution of various processes by the main CPU 63, the command output is performed through the output port of the I / F 101.

[0219] The management IC 66 includes a management I / F 111, a management CPU 112, a management ROM 113, a management RAM 114, an RTC 115, a correspondence memory 116, a history memory 117, and a calculation result memory 131. These devices are connected to each other via an internal bus 66a provided in the management IC 66 so as to be capable of two-way communication.

[0220] The management side I / F 111 is an interface for receiving various signals from the main CPU 63 via a group of signal paths 118 for one-way communication built in the MPU 62, and for transmitting various signals to the reading terminal 68d via a group of signal paths 119 for one-way communication built in the MPU 62. Various signals from the main CPU 63 are input to an input port of the management side I / F 111, and various signals to the reading terminal 68d are output from an output port of the management side I / F 111. The main CPU 63 is electrically connected to the reading terminal 68d via a group of signal paths 120 for two-way communication built in the MPU 62.

[0221] The management CPU 112 is an arithmetic processing device including a control unit and an arithmetic unit. The management ROM 113 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain memory such as a NOR flash memory and a NAND flash memory, and is used for reading only. The management ROM 113 stores various control programs and fixed value data executed by the management CPU 112. The management RAM 114 is a memory (i.e., a volatile storage means) that requires an external power supply to retain memory such as an SRAM and a DRAM, and is used for both reading and writing. The management RAM 114 is randomly accessible, and when compared with the same data capacity, the time required for reading is faster than that of the management ROM 113. The management RAM 114 temporarily stores various data and the like for the execution of the control programs stored in the management ROM 113.

[0222] The RTC 115 is a real-time clock that constantly measures date information and time information, and is configured to be able to output the measured date information and time information (hereinafter also referred to as date and time information) according to instructions from the management side CPU 112. The RTC 115 is provided with a backup power supply, so that it is possible to measure date information and time information even when the power of the pachinko machine 10 is cut off.

[0223] The correspondence memory 116 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as SRAM and DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a-122p provided in the input port 121 of the management side I / F 111 and the types of signals input to those buffers 122a-122p. Details of the contents of the correspondence memory 116 will be described later.

[0224] The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information related to the game history received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be described later.

[0225] The calculation result memory 131 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain memory such as a NOR type flash memory or a NAND type flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management side CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c, and are also output to an external device connected to the reading terminal 68d.

[0226] Next, a description will be given of the configuration of the input port 121 provided in the management side I / F 111. Fig. 19 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111.

[0227] The input port 121 is provided with a plurality of buffers 122a-122p. Specifically, first to sixteenth buffers 122a-122p are provided. One type of signal can be input to each of the first to sixteenth buffers 122a-122p via signal paths 118a-118p, and each of the first to sixteenth buffers 122a-122p stores information of "0" as the first data when the input signal is at a LOW level, and stores information of "1" as the second data when the input signal is at a HI level. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0228] A first signal corresponding to the detection result of the first winning hole detection sensor 42a is input to the first buffer 122a. In this case, the master CPU 63 outputs a first signal of LOW level when the first winning hole detection sensor 42a does not detect a new game ball, and outputs a first signal of HI level for a specific period when the first winning hole detection sensor 42a detects one game ball. This specific period is a period sufficient for the management CPU 112 to identify that a first signal of HI level has been input to the first buffer 122a.

[0229] The second buffer 122b receives a second signal corresponding to the detection result of the second winning hole detection sensor 43a. In this case, the master CPU 63 outputs a LOW level second signal when the second winning hole detection sensor 43a detects no new game ball, and outputs a HI level second signal for a specific period when the second winning hole detection sensor 43a detects one game ball. This specific period is sufficient for the management CPU 112 to determine that a HI level second signal has been input to the second buffer 122b.

[0230] The third buffer 122c receives a third signal corresponding to the detection result of the third winning hole detection sensor 44a. In this case, the main CPU 63 outputs a LOW level third signal when the third winning hole detection sensor 44a detects no new game ball, and outputs a HI level third signal for a specific period when the third winning hole detection sensor 44a detects one game ball. This specific period is sufficient for the management CPU 112 to determine that a HI level third signal has been input to the third buffer 122c.

[0231] A fourth signal corresponding to the detection result of the special electric detection sensor 45a is input to the fourth buffer 122d. In this case, the master CPU 63 outputs a LOW level fourth signal when the special electric detection sensor 45a does not detect a new game ball, and outputs a HI level fourth signal for a specific period when the special electric detection sensor 45a detects one game ball. This specific period is sufficient for the management CPU 112 to determine that a HI level fourth signal has been input to the fourth buffer 122d.

[0232] A fifth signal corresponding to the detection result of the first actuation port detection sensor 46a is input to the fifth buffer 122e. In this case, the master CPU 63 outputs a LOW level fifth signal when the first actuation port detection sensor 46a does not detect a new game ball, and outputs a HI level fifth signal for a specific period when the first actuation port detection sensor 46a detects one game ball. This specific period is a period sufficient for the management CPU 112 to identify that a HI level fifth signal has been input to the fifth buffer 122e.

[0233] A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the master CPU 63 outputs a sixth signal of LOW level when the second actuation port detection sensor 47a does not detect a new game ball, and outputs a sixth signal of HI level for a specific period when the second actuation port detection sensor 47a detects one game ball. This specific period is a period sufficient for the management CPU 112 to determine that a sixth signal of HI level has been input to the sixth buffer 122f.

[0234] A seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g. In this case, the master CPU 63 outputs a LOW level seventh signal when the outlet detection sensor 48a does not detect a new game ball, and outputs a HI level seventh signal for a specific period when the outlet detection sensor 48a detects one game ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0235] The eighth buffer 122h receives an eighth signal corresponding to whether or not the open / close execution mode is in progress. In this case, the main CPU 63 continuously outputs the eighth signal at a LOW level when the open / close execution mode is not in progress, and continuously outputs the eighth signal at a HI level when the open / close execution mode is in progress.

[0236] A ninth signal corresponding to whether or not the high-frequency support mode is in effect is input to the ninth buffer 122i. In this case, the main CPU 63 continuously outputs a LOW-level ninth signal when the high-frequency support mode is not in effect, and continuously outputs a HI-level ninth signal when the high-frequency support mode is in effect.

[0237] A tenth signal corresponding to whether or not the front door frame 14 is open is input to the tenth buffer 122j. In this case, the main CPU 63 continuously outputs a LOW level tenth signal when the front door frame 14 is closed, and continuously outputs a HI level tenth signal when the front door frame 14 is open.

[0238] An eleventh signal corresponding to whether a game round has started or not is input to the eleventh buffer 122k. In this case, the master CPU 63 continues to output a LOW level eleventh signal until a game round starts, and outputs a HI level eleventh signal for a specific period when a game round starts. This specific period is a period sufficient for the management CPU 112 to determine that a HI level eleventh signal has been input to the eleventh buffer 122k.

[0239] A setting value update signal is input to the fifteenth buffer 122o to make the management CPU 112 recognize that the setting state of the pachinko machine 10 has been newly set by the main CPU 63. In this case, the main CPU 63 outputs a LOW level setting value update signal when the setting state of the pachinko machine 10 has not been newly set, and outputs a pulse signal in which a HI level setting value update signal is maintained for a specific period of time for the number of pulses corresponding to the newly set setting value when the setting state of the pachinko machine 10 has been newly set. This specific period is a period sufficient for the management CPU 112 to identify that a HI level setting value update signal has been input to the fifteenth buffer 122o.

[0240] An output instruction signal is input to the 16th buffer 122p to make the management CPU 112 recognize the opportunity to output the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d. In this case, the main CPU 63 outputs a LOW level output instruction signal when there is no need to output the history information, and outputs a HI level output instruction signal for a specific period when there is a need to output the history information. This specific period is a period sufficient for the management CPU 112 to identify that a HI level output instruction signal has been input to the 16th buffer 122p.

[0241] Although the twelfth buffer 122l, the thirteenth buffer 122m, and the fourteenth buffer 122n can receive signals from the main CPU 63, they are blank in this pachinko machine 10 and do not receive normal signals. In this way, the number of buffers 122a-122p provided as the input port 121 of the management I / F 111 is greater than the number of types of signals output from the main CPU 63 to the management IC 66 in this pachinko machine 10, so that the management IC 66 can be used in models other than this pachinko machine 10. This makes it possible to increase the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main CPU 63 and the first to sixteenth buffers 122a to 122p, respectively, so as to correspond one-to-one to the first to sixteenth buffers 122a to 122p, but this is not limited to this, and a configuration in which the signal paths 118l to 118n are not formed between the main CPU 63 and the buffers 122l to 122n to be blanked may also be used.

[0242] It is determined in the design stage of the management IC 66 that a set value update signal is input to the 15th buffer 122o and that an output instruction signal is input to the 16th buffer 122p, and the management CPU 112 can specify that a set value update signal is input to the 15th buffer 122o and that an output instruction signal is input to the 16th buffer 122p without receiving an instruction from the main CPU 63. On the other hand, it is not determined in the design stage of the management IC 66 what kind of signals are input to the first to fourteenth buffers 122a to 122n, and the types of these signals are specified by the management CPU 112 upon receiving an instruction from the main CPU 63. The types of these signals are specified in the management CPU 112 by transmitting a type identification command from the main CPU 63 to the management CPU 112 when control is started in the main CPU 63 and the management CPU 112 with the start of supply of operating power to the MPU 62, as will be described in detail later. In this case, information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of various signals when operating power is being supplied, the information stored in the correspondence memory 116 is referenced.

[0243] 20 is an explanatory diagram for explaining the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to fourteenth correspondence areas 123a to 123n in one-to-one correspondence with the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I / F 111.

[0244] The first correspondence area 123a stores information indicating that the general winning opening 31 is the information for the management CPU 112 to specify the type of signal input to the first buffer 122a. The first correspondence area 123a also stores information indicating that the general winning opening 31 is the information indicating the number of game balls paid out when one game ball enters the general winning opening 31 (10 balls). The second correspondence area 123b stores information indicating that the general winning opening 31 is the information for the management CPU 112 to specify the type of signal input to the second buffer 122b. The second correspondence area 123b also stores information indicating that the general winning opening 31 is the information indicating the number of game balls paid out when one game ball enters the general winning opening 31 (10 balls). The third correspondence area 123c stores information indicating that the general winning opening 31 is the information for specifying the type of signal input to the third buffer 122c by the management CPU 112. In addition, the third correspondence area 123c stores information indicating that the general winning opening 31 is the number of game balls (10) that will be paid out when one game ball enters the general winning opening 31, in addition to the information indicating that the general winning opening 31 is the information.

[0245] The fourth correspondence area 123d stores information indicating that the device is the special electric winning device 32 as information for the management side CPU 112 to specify the type of signal input to the fourth buffer 122d. The fourth correspondence area 123d also stores information indicating that the device is the special electric winning device 32, as well as information on the number of game balls (15) that will be paid out when one game ball enters the special electric winning device 32. The fifth correspondence area 123e stores information indicating that the device is the first operating port 33 as information for the management side CPU 112 to specify the type of signal input to the fifth buffer 122e. The fifth correspondence area 123e also stores information indicating that the device is the first operating port 33, as well as information on the number of game balls (1) that will be paid out when one game ball enters the first operating port 33. The sixth correspondence area 123f stores information indicating that the signal is the second actuation port 34, as information for the management CPU 112 to identify the type of signal input to the sixth buffer 122f. The sixth correspondence area 123f also stores information indicating that the signal is the second actuation port 34, as well as information on the number of game balls (one) that will be paid out when one game ball enters the second actuation port 34. The seventh correspondence area 123g stores information indicating that the signal is the outlet 24a, as information for the management CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0246] The eighth correspondence area 123h stores information indicating that the mode is the open / close execution mode as information for the management CPU 112 to specify the type of signal input to the eighth buffer 122h. The ninth correspondence area 123i stores information indicating that the mode is the high frequency support mode as information for the management CPU 112 to specify the type of signal input to the ninth buffer 122i. The tenth correspondence area 123j stores information indicating that the front door frame 14 is the information for the management CPU 112 to specify the type of signal input to the tenth buffer 122j. The eleventh correspondence area 123k stores information indicating that a game round has started as information for the management CPU 112 to specify the type of signal input to the eleventh buffer 122k.

[0247] The twelfth correspondence area 123l stores information indicating that the signal type input to the twelfth buffer 122l is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the twelfth buffer 122l. The thirteenth correspondence area 123m stores information indicating that the signal type input to the thirteenth buffer 122m is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the fourteenth buffer 122n. The fourteenth correspondence area 123n stores information indicating that the signal type input to the fourteenth buffer 122n is blank and does not correspond to any of the above, as information for the management CPU 112 to specify the type of signal input to the fourteenth buffer 122n.

[0248] As described above, by configuring the management CPU 112 to specify what kind of signals are input to the first to fourteenth buffers 122a to 122n by receiving an instruction from the main CPU 63, it becomes possible to use the management IC 66 for models other than the present pachinko machine 10. This makes it possible to increase the versatility of the management IC 66.

[0249] Moreover, instead of outputting information for recognizing the type of signal every time a signal corresponding to storage of history information is output to the first to fourteenth buffers 122a to 122n, information for recognizing the type of signal is output in advance, and information for specifying the type of signal input to the first to fourteenth buffers 122a to 122n by the management CPU 112 based on the output information is stored in the correspondence memory 116. This makes it possible to reduce the amount of information output from the main CPU 63 to the management CPU 112 each time a signal is output, compared to a configuration in which information for recognizing the type of signal is output every time a signal corresponding to storage of history information is output to the first to fourteenth buffers 122a to 122n.

[0250] Moreover, the information for the management CPU 112 to specify the types of signals input to the first to fourteenth buffers 122a to 122n is output when the supply of operating power starts. This allows the management CPU 112 to specify the types of signals input to the first to fourteenth buffers 122a to 122n when a game is started in the pachinko machine 10.

[0251] In addition, the information setting that the set value update signal is input to the 15th buffer 122o and the information setting that the output instruction signal is input to the 16th buffer 122p are set at the design stage of the management IC 66. This makes it possible to omit the process for identifying the type of signal input to the 15th buffer 122o and the 16th buffer 122p for the set value update signal and the output instruction signal that are used reliably not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load of the process for identifying the type of such signal.

[0252] Next, a description will be given of the history memory 117 of the management IC 66. FIG.

[0253] The history memory 117 is provided with a history area 124 for sequentially storing the history information. In the history area 124, a plurality of pointer information are set with consecutive numbers, and a history information storage area 125 is set in one-to-one correspondence with each pointer information. The history information storage area 125 can store a combination of RTC information and correspondence information. In this case, each history information storage area 125 has a data capacity of 2 bytes, a data capacity of 1 byte is assigned as an area for storing RTC information, and a data capacity of 1 byte is assigned as an area for storing correspondence information. When it becomes necessary to store correspondence information according to a signal input to the first to fourteenth buffers 122a to 122n (actually the first to eleventh buffers 122a to 122k in the case of this pachinko machine 10), first, the date and time information measured by the current RTC 115 is stored in an area for storing RTC information in the history information storage area 125 corresponding to the pointer information currently being written. Thereafter, the correspondence information corresponding to the buffer 122a-122n that triggered the current information storage is read from the correspondence area 123a-123n corresponding to the buffer 122a-122n in the correspondence memory 116, and the read correspondence information is stored in an area for storing correspondence information in the history information storage area 125 that corresponds to the pointer information currently being written.

[0254] Specifically, regarding the correspondence information stored in the history information storage area 125, since the first to seventh buffers 122a to 122g receive signals corresponding to the detection results of the ball entry detection sensors 42a to 48a as already explained, the first to seventh correspondence areas 123a to 123g in the correspondence memory 116 store information corresponding to the types of the ball entry detection sensors 42a to 48a. More specifically, information corresponding to the types of ball entry sections corresponding to the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. As already explained, in this pachinko machine 10, the first to third winning hole detection sensors 42a to 44a all detect game balls that have entered the general winning hole 31, so the first to third correspondence areas 123a to 123c corresponding to these first to third winning hole detection sensors 42a to 44a all store information indicating that they are the general winning hole 31. Also, the fourth correspondence area 123d stores information indicating that it is the special electric winning device 32, the fifth correspondence area 123e stores information indicating that it is the first operating port 33, the sixth correspondence area 123f stores information indicating that it is the second operating port 34, and the seventh correspondence area 123g stores information indicating that it is the outlet 24a. If the buffer 122a-122n that triggered the current information storage is any of the first to seventh buffers 122a-122g, information on the type of ball entry part corresponding to that buffer 122a-122g is read out from any of the first to seventh correspondence areas 123a-123g, and the read information on the type of ball entry part is stored as it is in the area for storing the correspondence information in the history information storage area 125.

[0255] On the other hand, the eighth buffer 122h receives a signal indicating whether or not it is in the open / close execution mode, the ninth buffer 122i receives a signal indicating whether or not it is in the high frequency support mode, the tenth buffer 122j receives a signal indicating whether or not the front door frame 14 is open, and the eleventh buffer 122k receives a signal indicating whether or not a game round has started. Therefore, the eighth correspondence area 123h stores information indicating the open / close execution mode, the ninth correspondence area 123i stores information indicating the high frequency support mode, the tenth correspondence area 123j stores information indicating the front door frame 14, and the eleventh correspondence area 123k stores information indicating a game round.

[0256] As already explained, the main CPU 63 continuously outputs the 8th signal at a LOW level when the open / close execution mode is not in effect, and continuously outputs the 8th signal at a HI level when the open / close execution mode is in effect, so that the control CPU 112 can determine that the open / close execution mode has started when the 8th signal changes from a LOW level to a HI level, and can determine that the open / close execution mode has ended when the 8th signal changes from a HI level to a LOW level. In addition, in both cases where the 8th signal changes from a LOW level to a HI level and where the HI level changes from a LOW level to a LOW level, the control CPU 112 determines that a trigger for storing the correspondence information in the history information storage area 125 has occurred. In other words, when the 8th signal changes from a LOW level to a HI level, not only the information indicating the open / close execution mode read from the 8th correspondence area 123h but also the start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the eighth signal changes from HI level to LOW level, not only the information indicating the opening / closing execution mode read from the eighth correspondence area 123h but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

[0257] As already explained, the main CPU 63 continuously outputs the ninth signal at a LOW level when the high-frequency support mode is not in effect, and continuously outputs the ninth signal at a HI level when the high-frequency support mode is in effect, so that the control CPU 112 can determine that the high-frequency support mode has started when the ninth signal changes from a LOW level to a HI level, and can determine that the high-frequency support mode has ended when the ninth signal changes from a HI level to a LOW level. In addition, in both cases where the ninth signal changes from a LOW level to a HI level and where the HI level changes from a LOW level to a LOW level, the control CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from a LOW level to a HI level, not only the information indicating the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the 9th signal changes from HI level to LOW level, not only the information indicating that it is the high-frequency support mode read from the 9th correspondence area 123i but also the end information are stored in an area for storing correspondence information in the history information storage area 125.

[0258] As already explained, the main CPU 63 continuously outputs the tenth signal at a LOW level when the front door frame 14 is in a closed state, and continuously outputs the tenth signal at a HI level when the front door frame 14 is in an open state, so that the management CPU 112 can determine that the front door frame 14 is opened when the tenth signal changes from a LOW level to a HI level, and can determine that the front door frame 14 is closed when the tenth signal changes from a HI level to a LOW level. In addition, in both cases where the tenth signal changes from a LOW level to a HI level and where it changes from a HI level to a LOW level, the management CPU 112 determines that an opportunity to store the correspondence information in the history information storage area 125 has occurred. In other words, when the tenth signal changes from a LOW level to a HI level, not only the information indicating that it is the front door frame 14 read from the tenth correspondence area 123j but also the opening start information are stored in the area for storing the correspondence information in the history information storage area 125. In addition, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence area 123j but also the opening end information are stored in an area for storing correspondence information in the history information storage area 125.

[0259] As already explained, the master CPU 63 continues to output the LOW level 11th signal until the start timing of a game round, and outputs the HI level 11th signal for a specific period when the start timing of a game round is reached. Therefore, the management CPU 112 determines that a game round has started when the 11th signal changes from the LOW level to the HI level. In other words, when the 11th signal changes from the LOW level to the HI level, information indicating that it is the game round read from the 11th correspondence area 123k is stored in the area for storing correspondence information in the history information storage area 125.

[0260] The history information storage area 125 is provided for a number of times that allows all the history information generated during the ten consecutive business days during which the shooting of game balls continues in the pachinko machine 10 from opening to closing to be stored. For example, if history information is generated 60,000 times a day, more than 600,000 history information storage areas 125 are provided. This makes it possible to store and hold all the history information in the history memory 117 for at least ten days.

[0261] The history memory 117 is provided with a pointer area 126 in addition to the history area 124. The pointer area 126 stores information for the management CPU 112 to specify the pointer information currently being written in the history memory 117. Specifically, at the time of shipping the pachinko machine 10, information is set in the pointer area 126 specifying the pointer information of "0" as the writing target. Then, every time one piece of history information is newly stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information to be written is incremented by 1. When the last pointer information becomes the writing target and history information is stored in the history information storage area 125 corresponding to the last pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the writing target. As a result, when a storage trigger for history information occurs in which the number of pieces of history information that can be stored is exceeded, the history information storage area 125 in which the oldest history information is stored is overwritten with the new history information in order.

[0262] Furthermore, when an external device reads history information from history memory 117, the history information storage area 125 is cleared to all "0"s, and the information in pointer area 126 is updated so that pointer information of "0" becomes the write target. This makes it possible to prevent history information that has once been read from becoming the read target again.

[0263] Next, a specific processing configuration for managing game history using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence between the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management I / F 111 and the types of signals in the correspondence memory 116 will be described. Fig. 22 is a flowchart showing the recognition processing executed by the main CPU 63. The recognition processing is executed in step S111 in the main processing (Fig. 9).

[0264] First, "14" is set to a recognition output counter provided in the main RAM 65 (step S801). The recognition output counter is a counter for the main CPU 63 to identify the remaining number of times information output is required to make the management CPU 112 recognize which type of signal the first to fourteenth buffers 122a to 122n of the input port 121 in the management I / F 111 correspond to. As already explained, the first to fourteenth buffers 122a to 122n are the 14 buffers to be recognized as the types of signals, so the recognition output counter is set to "14".

[0265] Thereafter, output processing of the identification start command is executed (step S802). The main CPU 63 outputs various commands to the management CPU 112 to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n correspond to. When outputting these commands, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 to store history information are used to output a command to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n correspond to. This makes it possible to reduce the number of signal paths and simplify the configuration, compared to a configuration in which the signal paths for outputting the commands are provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In the output process of the identification start command, the output state of the ninth signal is switched to HI level at the timing of starting the output of the identification start command in order to make the management CPU 112 recognize that a new command has been transmitted. The output period of the identification start command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 specifies that a process should be started for storing information on the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals in the correspondence memory 116.

[0266] Then, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and then the n+1-th buffer is set as the signal type, so that recognition setting of the signal types corresponding to the first to fourteenth buffers 122a to 122n is performed. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is the general winning port 31 and the number of prize balls therein is read out, if the recognition output counter is "11", a type identification command indicating that it is the special winning device 32 and the number of prize balls therein is read out, if the recognition output counter is "10", a type identification command indicating that it is the first operating port 33 and the number of prize balls therein is read out, if the recognition output counter is "9", a type identification command indicating that it is the second operating port 34 and the number of prize balls therein is read out, if the recognition output counter is "8", a type identification command indicating that it is the out port 31 and the number of prize balls therein is read out, If the recognition output counter is "7", a type identification command indicating that it is the open / close execution mode is read out; if the recognition output counter is "6", a type identification command indicating that it is the high frequency support mode is read out; if the recognition output counter is "5", a type identification command indicating that it is the front door frame 14 is read out; if the recognition output counter is "4", a type identification command indicating that it is a play round is read out; if the recognition output counter is "3" to "1", a type identification command indicating that it is blank is read out.

[0267] Then, the output process of the read type identification command is executed (step S804). The type identification command has a data capacity of 8 bits like the identification start command, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In the output process of the identified type command, the output state of the ninth signal is switched to HI level at the timing of starting output of the identified type command to make the management CPU 112 recognize that a new command has been transmitted. The output period of the identified type command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management CPU 112 to recognize the identified type command and the output state of the ninth signal. By receiving the identified type command, the management CPU 112 stores information corresponding to the identified type command in the correspondence areas 123a to 123n corresponding to the buffer that is the current setting target among the first to fourteenth buffers 122a to 122n.

[0268] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after decrement is "0" (step S806). If the value of the recognition output counter is 1 or more (step S806: NO), a process is executed to output a type identification command corresponding to the value of the recognition output counter after decrement (steps S803 and S804).

[0269] On the other hand, if the value of the recognition output counter is "0" (step S806: YES), output processing of the recognition end command is executed (step S807). The recognition end command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In addition, in the recognition end command output processing, the output state of the ninth signal is switched to HI level at the timing of starting output of the recognition end command in order to make the management side CPU 112 recognize that a new command has been transmitted. In addition, the output period of the recognition end command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the management side CPU 112 to recognize the recognition end command and the output state of the ninth signal. By receiving the recognition end command, the management side CPU 112 determines that the process for storing information on the correspondence relationship between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence relationship memory 116 has been completed.

[0270] Next, the management processing executed by the management CPU 112 will be described with reference to the flowchart of Fig. 23. The management processing is started when the supply of operating power to the management CPU 112 is started. The processing speed of the management CPU 112 is faster than the processing speed of the main CPU 63, and the combination of processing from step S908 onwards in the management processing is executed 16 or more times from the start of one timer interrupt processing (Fig. 11) in the main CPU 63 to the start of the next timer interrupt processing (Fig. 11).

[0271] First, it is determined whether or not an identification start command has been received from the main CPU 63 (step S901). If an identification start command has not been received (step S901: NO), a setting update recognition process is executed (step S902), and then the process returns to step S901. In the setting update recognition process, which will be described in detail later, when a new setting is made to the setting status of the pachinko machine 10 in the main CPU 63, a process corresponding to the new setting is executed.

[0272] When an identification start command is received from the main CPU 63 (step S901: YES), the value of a setting target counter provided in the management RAM 114 is cleared to "0" (step S903). The setting target counter is a counter for the management CPU 112 to specify the type of buffers 122a to 122n for which a signal type is to be set. The first buffer 122a is the first buffer for which a signal type is to be set, and thereafter the nth buffer and then the (n+1)th buffer are the next buffers for which a signal type is to be set.

[0273] Thereafter, on condition that a type identification command has been received from the main CPU 63 (step S904: YES), a correspondence setting process is executed (step S905). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter of the control RAM 114, among the first to fourteenth correspondence areas 123a to 123n of the correspondence memory 116. Thereafter, the value of the setting target counter of the control RAM 114 is incremented by 1 (step S906).

[0274] If a negative determination is made in step S904, or if the process of step S906 is executed, it is determined (step S907) whether or not an identification end command has been received from the main CPU 63. If an identification end command has not been received (step S907: NO), the process returns to step S904, and the processes of steps S905 and S906 are executed again on the condition that a new type identification command is received from the main CPU 63 (step S904: YES).

[0275] When an identification end command is received from the main CPU 63 (step S907: YES), the processes of steps S908 to S910 are repeatedly executed. In step S908, details of which will be described later, a history setting process is executed for storing history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S909, details of which will be described later, various parameters are calculated using the history information stored in the history memory 117, and a display output process is executed for notifying the first to third notification display devices 69a to 69c of the calculation results. In step S910, details of which will be described later, an external output process is executed for outputting the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d.

[0276] Fig. 24 is a time chart showing how information on the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence memory 116. Fig. 24(a) shows a period during which a command is output from the main CPU 63 to the control CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Fig. 24(b) shows a period during which the output state of the ninth signal is at HI level, Fig. 24(c) shows an execution period of an identification state during which a process for identifying the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is executed, and Fig. 24(d) shows the timing at which the correspondence setting process (step S905) is executed by the control CPU 112.

[0277] As the supply of operating power to the main CPU 63 and the control CPU 112 is started, output of the identification start command using the first to eighth signals is started at the timing of t1 as shown in FIG. 24(a). Also, at the timing of t1, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 24(b). Thereafter, at the timing of t2 in which the output of the identification start command is continued, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 24(b). The control CPU 112 identifies that a command is being sent from the main CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the identification start command has been received, the control CPU 112 makes an affirmative decision in step S901 of the management process (FIG. 23) to enter the identification state. Thereafter, output of the identification start command is stopped at the timing of t3 as shown in FIG. 24(a).

[0278] After that, at the timing of t4, the output of the first type identification command using the first to eighth signals is started as shown in FIG. 24(a). Also, at the timing of t4, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 24(b). After that, at the timing of t5, in which the output of the type identification command is continued, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 24(b). The management side CPU 112 identifies that a command has been sent from the main side CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main side CPU 63 by confirming the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command has been received, the management side CPU 112 executes the correspondence setting process as shown in FIG. 24(d) at the timing of t5. In the correspondence setting process, the information indicating that it is the general winning port 31 and the information on the number of winning balls are stored in the first correspondence area 123a of the correspondence memory 116. After that, at timing t6, the output of the type identification command is stopped as shown in FIG. 24(a).

[0279] Thereafter, from time t7 to time t9, from time t10 to time t12, from time t13 to time t15, and from time t16 to time t18, similar to the time t4 to time t6, the correspondence setting process corresponding to the type identification command output from the master CPU 63 is executed by the management CPU 112. In this case, the correspondence setting process corresponding to the 14th type identification command is completed from time t16 to time t18.

[0280] After that, at the timing of t19, the output of the identification end command using the first to eighth signals is started as shown in FIG. 24(a). Also, at the timing of t19, the output state of the ninth signal is changed from LOW level to HI level as shown in FIG. 24(b). After that, at the timing of t20, in which the output of the identification end command is continued, the output state of the ninth signal is changed from HI level to LOW level as shown in FIG. 24(b). The control side CPU 112 identifies that a command has been sent from the main side CPU 63 by confirming that the output state of the ninth signal has been changed from HI level to LOW level, and grasps the contents of the command received from the main side CPU 63 by confirming the information of the first to eighth buffers 122a to 122h. In this case, since the identification end command has been received, the identification state of the control side CPU 112 is ended at the timing of t20 as shown in FIG. 24(c). After that, the output of the identification end command is stopped at the timing of t21 as shown in FIG. 24(a).

[0281] As described above, the configuration allows the management CPU 112 to recognize whether or not a command is being output using the 9th signal, so that the management CPU 112 can clearly recognize that a command is being output even in a configuration in which the command is output using the 1st to 8th signals (i.e., the 1st to 8th signal paths) used to instruct the management CPU 112 to store history information.

[0282] Next, a description will be given of a process configuration for storing history information in the history memory 117. Fig. 25 is a flowchart showing the output process for management executed by the main CPU 63. The output process for management is executed in step S319 in the timer interrupt process (Fig. 11).

[0283] First, the managed object counter provided in the main RAM 65 is set to "11" (step S1001). The managed object counter is a counter for the main CPU 63 to determine whether there is a managed object that is not the target of the determination of whether the signal output state to the management CPU 112 should be changed in the current management output process, and for the main CPU 63 to determine whether the signal output state to the management CPU 112 should be changed. In one management output process, the managed objects that are the targets of the determination of whether the signal output state to the management CPU 112 should be changed are the seven ball entry detection sensors 42a to 48a, whether the opening and closing execution mode is executed, whether the high frequency support mode is executed, whether the front door frame 14 is opened and closed, and whether a game round has started, totaling 11 objects. Therefore, the managed object counter is set to "11" first.

[0284] Then, it is determined whether the output state of the signal to the management side CPU 112 for the managed object corresponding to the current value of the managed counter is at HI level (step S1002). If it is not at HI level (step S1002: NO), it is determined whether the value of the managed counter is 5 or more, thereby identifying which of the seven ball entry detection sensors 42a to 48a is the managed object corresponding to the value of the managed counter (step S1003).

[0285] If the answer is "yes" in step S1003, it is determined whether the output flag of the main RAM 65 corresponding to the value of the managed counter is set to "1" (step S1004). Specifically, if the value of the managed counter is "11" and corresponds to the first winning hole detection sensor 42a, it is determined whether the first output flag is set to "1", if the value of the managed counter is "10" and corresponds to the second winning hole detection sensor 43a, it is determined whether the second output flag is set to "1", if the value of the managed counter is "9" and corresponds to the third winning hole detection sensor 44a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 45a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 46a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 47a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 48a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 49a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "8" and corresponds to the special power detection sensor 49a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 48a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 49a, it is determined whether the third output flag is set to "1", if the value of the managed counter is "9" and corresponds to the special power detection sensor 49b, it is determined whether the third output flag is set a, it is determined whether the fourth output flag is set to "1", if the value of the managed counter is "7" and corresponds to the first actuation port detection sensor 46a, it is determined whether the fifth output flag is set to "1", if the value of the managed counter is "6" and corresponds to the second actuation port detection sensor 47a, it is determined whether the sixth output flag is set to "1", if the value of the managed counter is "5" and corresponds to the out port 24a, it is determined whether the seventh output flag is set to "1". As already explained, these first to seventh output flags are set to "1" in the ball entry detection process (Fig. 15).

[0286] If the output flag corresponding to the value of the managed counter is set to "1" (step S1004: YES), the output state of the signal corresponding to the value of the managed counter among the first to seventh signals is set to HI level (step S1005). After that, the output flag corresponding to the value of the managed counter is cleared to "0" (step S1006).

[0287] If a negative judgment is made in step S1003, it is judged whether or not an opportunity to switch the output state of the signal corresponding to the value of the managed counter to a HI level has occurred (step S1007). Specifically, if the value of the managed counter is "4", it is judged whether or not a transition to the open / close execution mode has occurred; if the value of the managed counter is "3", it is judged whether or not a transition to the high frequency support mode has occurred; if the value of the managed counter is "2", it is judged whether or not the front door frame 14 has been opened; if the value of the managed counter is "1", it is judged whether or not the eleventh output flag is set to "1" to judge whether or not a game round has started. If a positive judgment is made in step S1007, the output state of the signal corresponding to the value of the managed counter is set to a HI level (step S1008). Note that, if the process of step S1008 is executed when the value of the managed counter is "1", the eleventh output flag is cleared to "0".

[0288] If the determination in step S1002 is affirmative, it is determined whether or not a trigger has occurred to switch the output state of the signal corresponding to the value of the managed counter to a LOW level (step S1009). Specifically, if the value of the managed counter is 5 or more or "1" and the current managed object is any of the ball entry detection sensors 42a-48a or the start of a game round, it is determined whether or not a HI output duration (specifically, 10 milliseconds) has elapsed since the output state of the signal corresponding to the value of the managed counter among the 1st to 7th signals and the 11th signal was switched from a LOW level to a HI level. This HI output duration is set in the management side CPU 112 to a period longer than the longest processing interval of the history setting process (step S908) of the management process (FIG. 23), and is a period during which the management side CPU 112 can reliably identify the output state of the signal that has switched from a LOW level to a HI level. Also, if the value of the managed counter is "4" and the current managed object is in the open / close execution mode, it is determined whether the open / close execution mode has ended, if the value of the managed counter is "3" and the current managed object is in the high-frequency support mode, it is determined whether the high-frequency support mode has ended, and if the value of the managed counter is "2" and the current managed object is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. If an opportunity has occurred to switch the output state of the signal corresponding to the value of the managed counter to a LOW level (step S1009: YES), the output state of the signal corresponding to the value of the managed counter is set to a LOW level (step S1010).

[0289] If a negative determination is made in step S1004, if the process of step S1006 is executed, if a negative determination is made in step S1007, if the process of step S1008 is executed, if a negative determination is made in step S1009, or if the process of step S1010 is executed, the value of the managed object counter in the main RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the managed object counter after the decrement is "0" (step S1012). If the value of the managed object counter is 1 or more (step S1012: NO), the process of step S1002 and subsequent steps is executed for the managed object corresponding to the new managed object counter value.

[0290] Next, the history setting process executed by the management side CPU 112 will be described with reference to the flowchart of Fig. 26. The history setting process is executed in step S908 of the management process (Fig. 23).

[0291] First, the number of buffers to be checked by the management CPU 112 among the first to fourteenth buffers 122a to 122n is set in a check target counter provided in the management RAM 114 (step S1101). Specifically, the number of correspondence areas in which information other than information indicating that they are blank is stored among the first to fourteenth correspondence areas 123a to 123n in the correspondence memory 116 is identified, and the information of the identified number is set in the check target counter. As already explained, in this pachinko machine 10, information other than information indicating that they are blank is stored in the first to eleventh correspondence areas 123a to 123k, so in step S1101, the check target counter is set to "11".

[0292] Thereafter, by checking whether the numerical information stored in the buffer corresponding to the current value of the counter to be checked among the first to fourteenth buffers 122a to 122n has changed from "0" to "1", it is determined whether the output state of the input signal from the main CPU 63 to the buffer has been switched from LOW level to HI level (step S1102). When the value of the counter to be checked is "n", the nth buffers 122a to 122n are the targets for checking the numerical information. For example, when the value of the counter to be checked is "11", the eleventh buffer 122k is the target for checking the numerical information, and when the value of the counter to be checked is "5", the fifth buffer 122e is the target for checking the numerical information.

[0293] If the determination in step S1102 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S1103). Then, a write process to the history memory 117 is executed (step S1104). In the write process, the pointer information in the history area 124 currently being written is specified by referring to the pointer area 126 of the history memory 117, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information currently being written. In addition, the correspondence information is read from the correspondence areas 123a to 123n corresponding to the current value of the counter to be confirmed, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information currently being written. In addition, if the correspondence information is any one of information indicating the open / close execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information currently being written. When the value of the counter to be checked is "n", the n-th correspondence area 123a to 123n is the target for reading out the correspondence information. For example, when the value of the counter to be checked is "11", the eleventh correspondence area 123k is the target for reading out the correspondence information, and when the value of the counter to be checked is "5", the fifth correspondence area 123e is the target for reading out the correspondence information.

[0294] By executing the writing process as described above, when the value of the counter to be checked is any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the number of times of play, the combination of the RTC information and the correspondence relationship information indicating that it is any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, the second operating port 34, and the number of times of play is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Also, when the value of the counter to be checked is any of the opening / closing execution mode, the high frequency support mode, and the front door frame 14, the combination of the RTC information, the correspondence relationship information indicating that it is any of the opening / closing execution mode, the high frequency support mode, and the front door frame 14, and the start information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written.

[0295] Thereafter, a target pointer update process is executed (step S1105). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as the new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

[0296] When a negative determination is made in step S1102, or when the process of step S1105 is executed, it is determined whether or not the correspondence information for checking whether the signal output has been switched to a LOW level is stored in the correspondence area 123a-123n corresponding to the current value of the counter to be checked (step S1106). Specifically, when the current value of the counter to be checked is "8"-"10", any of information indicating the opening / closing execution mode, information indicating the high frequency support mode, and information indicating the front door frame 14 is stored in the corresponding correspondence area 123h-123j, so an affirmative determination is made in step S1106.

[0297] If the determination in step S1106 is positive, it is determined whether the output state of the input signal from the main CPU 63 to the buffer corresponding to the current counter value to be checked among the first to fourteenth buffers 122a to 122n has been switched from HI level to LOW level by checking whether the numerical information stored in the buffer corresponding to the current counter value to be checked has been changed from "1" to "0" (step S1107). If the determination in step S1107 is positive, the RTC information is read out as in step S1103 (step S1108), and further a write process to the history memory 117 is executed (step S1109). In the write process, the RTC information read out in step S1108 is written into the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. In addition, the correspondence information is read out from the correspondence areas 123a to 123n corresponding to the current counter value to be checked, and the correspondence information is written into the history information storage area 125 corresponding to the pointer information to be written. Moreover, not only the correspondence relationship information but also the end information is written in the history information storage area 125 corresponding to the pointer information to be written. By executing the writing process in this manner, when the value of the counter to be checked is either the open / close execution mode, the high frequency support mode, or the front door frame 14, a combination of the RTC information, the correspondence relationship information indicating either the open / close execution mode, the high frequency support mode, or the front door frame 14, and the end information is stored as history information in the history information storage area 125 corresponding to the pointer information to be written. Thereafter, the target pointer update process is executed in the same manner as in step S1105 (step S1110).

[0298] If a negative determination is made in step S1106, if a negative determination is made in step S1107, or if the process of step S1110 is executed, the value of the confirmation target counter in the management RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the confirmation target counter after decrement by 1 is "0" (step S1112). If the value of the confirmation target counter is 1 or more (step S1112: NO), the process of step S1102 and subsequent steps is executed for the confirmation target corresponding to the new confirmation target counter value.

[0299] Next, the manner in which history information is stored in history memory 117 will be described with reference to the time chart of Fig. 27. Fig. 27(a) shows a period in which a HI level signal is input to any of the first to seventh and eleventh buffers 122a to 122g, 122k, Fig. 27(b) shows a period in which a HI level signal is input to the eighth buffer 122h, Fig. 27(c) shows a period in which a HI level signal is input to the ninth buffer 122i, Fig. 27(d) shows a period in which a HI level signal is input to the tenth buffer 122j, and Fig. 27(e) shows the timing of writing history information to history memory 117.

[0300] At time t1, the output state of a signal input to any one of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from LOW level to HI level as shown in FIG. 27(a). Therefore, at time t1, history information is written to the history memory 117 as shown in FIG. 27(e). Thereafter, at time t2, the signal switched to HI level at time t1 is switched to LOW level as shown in FIG. 27(a). However, since the signal is input to any one of the first to seventh and eleventh buffers 122a to 122g, 122k and the switching to LOW level is not a storage target for history information, writing of history information is not executed at time t2 as shown in FIG. 27(e).

[0301] Thereafter, at times t3, t5, t6, t9, t10, t13, and t14, the output state of the signal input to any of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from LOW level to HIGH level as shown in Fig. 27(a). Therefore, at each of these times, history information is written as shown in Fig. 27(e).

[0302] As shown in FIG. 27(b), the output state of the signal input to the eighth buffer 122h is at HI level from t4 to t7. This eighth buffer 122h corresponds to the occurrence or non-occurrence of the open / close execution mode. Therefore, as shown in FIG. 27(e), history information is written at t4, which is the timing when the output state of the signal input to the eighth buffer 122h switches to HI level, and at t7, which is the timing when the output state of the signal switches to LOW level. In this case, the history information written at t4 includes start information, and the history information written at t7 includes end information. This makes it possible to grasp the execution period of the open / close execution mode by checking the history information in the history memory 117.

[0303] Moreover, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening and closing execution mode. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is during the opening and closing execution mode by comparing the RTC information.

[0304] As shown in FIG. 27(c), the output state of the signal input to the ninth buffer 122i is at HI level from t8 to t11. This ninth buffer 122i corresponds to the occurrence or non-occurrence of the high frequency support mode. Therefore, as shown in FIG. 27(e), history information is written at t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to HI level, and at t11, which is the timing when the output state of the signal switches to LOW level. In this case, the history information written at t8 includes start information, and the history information written at t11 ​​includes end information. This makes it possible to grasp the execution period of the high frequency support mode by checking the history information in the history memory 117.

[0305] In addition, the history information is written in the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is in the high-frequency support mode or not. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is in the high-frequency support mode or not by comparing the RTC information.

[0306] As shown in FIG. 27(d), the output state of the signal input to the tenth buffer 122j is HI level from t12 to t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or not. Therefore, as shown in FIG. 27(e), at t12, when the output state of the signal input to the tenth buffer 122j is switched to HI level, and at t15, when the output state of the signal is switched to LOW level, history information is written. In this case, the history information written at t12 includes start information, and the history information written at t15 includes end information. This makes it possible to grasp the period during which the front door frame 14 is open by checking the history information in the history memory 117.

[0307] In addition, the history information is written in the history memory 117 in chronological order. Therefore, it is possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is from the time the front door frame 14 is open or not. In addition, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the outlet 24a, the general winning port 31, the special electric winning device 32, the first operating port 33, and the second operating port 34 is from the time the front door frame 14 is open or not by comparing the RTC information.

[0308] Next, a description will be given of the output process of the set value update signal executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Fig. 28 is a flowchart showing the output process of the set value update signal executed by the main CPU 63. The output process of the set value update signal is executed in step S119 in the main process (Fig. 9).

[0309] A value corresponding to the currently set setting value of the pachinko machine 10 is set in a pulse number counter provided in the main RAM 65 (step S1201). Specifically, the value of the setting value counter in the main RAM 65 is set in the pulse number counter. Then, it is determined whether or not the setting value update signal directed to the management CPU 112 is at HI level (step S1202). As already described, the setting value update signal is input to the fifteenth buffer 122o of the input port 121 in the management IC 66. Here, the output process of the setting value update signal is executed at a timing prior to the recognition process, which is a process for making the management CPU 112 identify the types of signals input to the first to fourteenth buffers 122a to 122n of the input port 121 in the main process (FIG. 9). In contrast, since the setting value update signal is set in the management IC 66 during the design stage of the pachinko machine 10 to be input to the 15th buffer 122o, even if the setting value update signal output process is executed prior to the recognition process, it is possible for the management CPU 112 to identify that the signal input to the 15th buffer 122o is a setting value update signal.

[0310] If the determination in step S1202 is negative, the value of a LOW level counter provided in the main RAM 65 is decremented by 1 (step S1203), and it is determined whether the value of the LOW level counter after decrement by 1 is "0" (step S1204). The LOW level counter is a counter for the main CPU 63 to determine whether the set value update signal has been maintained at a LOW level for a predetermined period while multiple pulses at which the set value update signal is at a HI level are output. If the value of the LOW level counter is "0" (step S1204: YES), this means that it is time to set the set value update signal to a HI level, and therefore the set value update signal is set to a HI level (step S1205).

[0311] Thereafter, the HI level counter provided in the main RAM 65 is set to "20" (step S1206). The HI level counter is a counter for the main CPU 63 to specify the period during which the setting value update signal is maintained at the HI level. The value set in the HI level counter is decremented by 1 at approximately 10 microsecond intervals, so that the setting value update signal is maintained at the HI level for 200 microseconds when one pulse is output. This period during which the HI level is maintained is sufficient for the control CPU 112 to specify that the setting value update signal has been changed from the LOW level to the HI level.

[0312] If the set value update signal is at HI level (step S1202: YES), the value of the HI level counter in the main RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI level counter after decrementing by 1 is "0" (step S1208). If the value of the HI level counter is "0" (step S1208: YES), this means that it is time to set the set value update signal to LOW level, so the set value update signal is set to LOW level (step S1209).

[0313] Then, the value of the pulse number counter in the main RAM 65 is decremented by 1 (step S1210), and it is determined whether the value of the pulse number counter after decrement is "0" (step S1211). If the value of the pulse number counter is not "0" (step S1211: NO), this means that the output of the pulse signal by the set value update signal for the number of times corresponding to the set value of the pachinko machine 10 set this time has not been completed, so "20" is set in the LOW level counter in the main RAM 65 (step S1212). The value set in the LOW level counter is decremented by 1 at approximately 10 microsecond intervals, so that the LOW level is maintained for 200 microseconds between multiple pulse outputs by the set value update signal. This period of maintaining the LOW level is sufficient for the management CPU 112 to identify that the set value update signal has been changed from the HI level to the LOW level.

[0314] If the value of the pulse number counter is "0" (step S1211: YES), this means that the output of the pulse signal by the setting value update signal corresponding to the currently set setting value of the pachinko machine 10 has been completed, so output processing of the setting value identification end command is executed (step S1213). The setting value identification end command is a command for making the management side CPU 112 recognize that the output of the setting value update signal for making the management side CPU 112 recognize the currently set setting value of the pachinko machine 10 has been completed. When outputting the setting value identification end command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used in the same way as the identification start command, the type identification command, and the identification end command. However, the signal pattern of the setting value identification end command is different from that of the identification start command, the type identification command, and the identification end command.

[0315] As described above, in the output process of the setting value update signal, a number of pulse signals due to the setting value update signal corresponding to the value of the setting value of the pachinko machine 10 that was set when the current supply of operating power began is output to the management IC 66. The management side CPU 112 executes the setting update recognition process to grasp the number of pulse signals due to the setting value update signal, and based on that, grasps the setting value of the pachinko machine 10 that was set this time.

[0316] Fig. 29 is a flowchart showing the setting update recognition process executed by the management CPU 112. The setting update recognition process is executed in step S902 of the management process (Fig. 23).

[0317] It is determined whether the setting value update signal input to the fifteenth buffer 122o of the input port 121 has switched from a low level to a high level (step S1301). If a positive determination is made in step S1301, the value of a setting value grasp counter provided in the management RAM 114 is set to "1" (step S1302). The setting value grasp counter is a counter for specifying the setting value of the pachinko machine 10 by the management CPU 112; for example, a setting value grasp counter value of "1" means "setting 1," and a setting value grasp counter value of "6" means "setting 6."

[0318] Thereafter, it is determined whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from LOW level to HI level again (step S1303). If the determination is affirmative in step S1303, the value of the setting value grasp counter in the management RAM 114 is incremented by 1 (step S1304). As a result, the setting value of the pachinko machine 10 identified in the management CPU 112 is increased by one step.

[0319] If a negative determination is made in step S1303 or if the process of step S1304 is executed, it is determined whether or not a setting value identification end command has been received from the main CPU 63 based on the input states of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, the process returns to step S1303.

[0320] If the determination in step S1305 is affirmative, RTC information, which is date information and time information, is read from the RTC 115 (step S1306). Then, a write process to the history memory 117 is executed (step S1307). In the write process, the pointer information in the history area 124 currently being written is identified by referring to the pointer area 126 in the history memory 117, and the RTC information read in step S1306 is written to the history information storage area 125 in the history area 124 corresponding to the pointer information being written. In addition, both information for identifying the setting value and information on the value of the setting value grasp counter are written to the history information storage area 125 corresponding to the pointer information being written. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the setting value when the setting was made is stored as history information.

[0321] Thereafter, a target pointer update process is executed (step S1308). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by one. It is determined whether the pointer information after the increment of one has exceeded the maximum value of the pointer information in the history area 124. If the maximum value has not been exceeded, the pointer information after the increment of one is overwritten in the pointer area 126 as new pointer information to be written. If the maximum value has been exceeded, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the initial pointer information.

[0322] As described above, when the setting state of the pachinko machine 10 is newly set by executing the setting update recognition process, the fact that the setting was made, the date and time when the setting was made, and the combination of setting values ​​when the setting was made are stored as history information in the history area 124. This makes it possible to grasp the date and time when the setting state of the pachinko machine 10 was newly set and the contents of the setting values ​​when the setting was made by reading and analyzing the information stored in the history memory 117 using an external device connected to the reading terminal 68d.

[0323] Here, even if the setting state of the pachinko machine 10 is newly set, the information stored in the history memory 117 is maintained as is. This makes it possible to prevent the history information in the history memory 117 from being erased even if the setting state of the pachinko machine 10 is newly set, and various parameters described below are calculated using history information that exists across the timing of changing the setting state of the pachinko machine 10. In this case, since the date and time when the setting state of the pachinko machine 10 is newly set as described above is stored in the history memory 117, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters for the period after the timing when the setting state of the pachinko machine 10 is newly set and during which the setting state is maintained.

[0324] Next, the display output process executed by the management CPU 112 will be described with reference to the flowchart of Fig. 30. The display output process is executed in step S909 of the management process (Fig. 23).

[0325] First, it is determined whether it is the calculation timing (step S1401). If 51 seconds have passed since the supply of operating power to the management CPU 112 started, or if 51 seconds have passed since the previous positive determination in step S1401, a positive determination is made in step S1401. If a positive determination is made in step S1401, the number of balls entering during normal times is calculated (step S1402). Specifically, the number of balls entering the out hole 24a is calculated by first counting the number of history information storage areas 125 in which correspondence information indicating that the ball is the out hole 24a is stored in the history area 124 of the history memory 117. In addition, the number of balls entering the general winning hole 31 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the ball is the general winning hole 31 is stored in the history area 124 of the history memory 117. Also, the number of balls that have entered the special electric winning device 32 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that it is the special electric winning device 32 is stored in the history area 124 of the history memory 117. Also, the number of balls that have entered the first operating port 33 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that it is the first operating port 33 is stored in the history area 124 of the history memory 117. Also, the number of balls that have entered the second operating port 34 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that it is the second operating port 34 is stored in the history area 124 of the history memory 117.

[0326] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 in which the corres...

Claims

[Claim 1] a history storage execution means for executing a history storage process for storing history information of a game corresponding to a game ball flowing down a game area between the door body and the game board and entering the predetermined ball entry means; information derivation means for executing a predetermined derivation process for deriving aspect information corresponding to a game result by utilizing the history information stored in the history storage means; A behavior information storage means capable of storing a plurality of pieces of behavior information derived at different timings by the information derivation means; a shift control means for executing a shift process for shifting the aspect information among a plurality of storage areas in the aspect information storage means, based on the occurrence of a predetermined trigger, so that the plurality of aspect information are stored in the aspect information storage means in a manner corresponding to the order derived by the information derivation means; a display control means for controlling the information display means so that displays corresponding to each of the plurality of pieces of the aspect information stored in the aspect information storage means are sequentially executed; A means for restricting execution of a predetermined process for playing a game in a predetermined situation; Equipped with The history storage execution means is configured to store, in the history storage means, history information corresponding to a game ball entering the predetermined ball entry means, regardless of whether the door body is in a closed state or an open state, The aspect information display control means a specific event response means for changing the information display means to a specific event response state based on the occurrence of a specific event; a predetermined display control means for controlling the information display means to display a predetermined display until a specific situation occurs after the manufacture of the gaming machine; Equipped with The history storage execution means includes a means for executing the history storage process even in the restricted state, The shift control means includes a means for executing the shift processing even in the restricted state, The gaming machine is characterized in that the specified display control means includes a means for terminating the specified display when the specific situation occurs even if the regulated situation exists.

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