Pachinko machine

Abstract

To improve efficiency of a configuration of boards for various presentation drives.SOLUTION: A game machine has a first board mounting electronic components related to game operation. A first electronic component mounted on the first board has unused terminals that do not require electrical connection. On the first board, pads are formed that correspond to all the terminals, including the unused terminals, of the first electronic component. All the terminals of the first electronic components are soldered to corresponding pads. Pads corresponding to the unused terminals are not electrically connected except to the unused terminals. The pads corresponding to the unused terminals are formed close to a solid ground and the solid ground is formed on a board surface facing a bottom surface of a chip as the first electronic component.SELECTED DRAWING: Figure 111

Description

Technical Field

[0001] The present invention relates to a gaming machine and a technology contributing to the performance improvement of the gaming machine.

Background Art

[0002] In a pachinko machine or a rotating gaming machine, various effects using a liquid crystal display screen, a speaker, an LED, a device, a vibrator, a blower, etc. are performed to liven up the game. In the following patent documents, technologies for controlling various effect operations are disclosed.

Prior Art Documents

Patent Documents

[0003]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0004] In such a gaming machine, it is desirable to realize a more interesting effect without causing an increase in the number of substrates, complication or difficulty of wiring, etc. as much as possible. Therefore, an object of the present invention is to propose a configuration capable of obtaining an effective effect without causing complication of these configurations.

Means for Solving the Problems

[0005] The gaming machine of the present invention is a gaming machine that conducts games based on lottery results, and has a first substrate on which electronic components related to game operations are mounted. The first electronic component mounted on the first substrate has unused terminals that do not require electrical connection. On the first substrate, pads corresponding to all terminals including the unused terminals of the first electronic component are formed. All terminals of the first electronic component are soldered to the corresponding pads. The pads corresponding to the unused terminals are not electrically connected to anything other than the unused terminals. The pads corresponding to the unused terminals are formed close to the solid ground. The bottom surface of the chip as the first electronic component Directly below Substrate surface Non-linear in almost the entire area of A solid ground is formed. Also, for an LED chip in which N LED elements of different emission colors are packaged, a circuit configuration is adopted in which a plurality of the N LED elements have emission drive current flowing through them and at least one LED element has no emission drive current flowing through it, so that an LED chip with some LED elements unused is provided on the first substrate as a light-emitting device. However, "N" is a natural number of 3 or more. Also, on the first substrate, pads corresponding to all anode terminals and cathode terminals of the N LED elements of the LED chip are formed, and all anode terminals and cathode terminals are soldered to the corresponding pads. Also, the anode terminal and cathode terminal of the unused LED element of the LED chip are configured to be both connected to the power line or both connected to the ground. Also, the unused LED elements in a plurality of the LED chips are connected in series, and the anode terminal of the first LED element and the cathode terminal of the last LED element among the plurality of serially connected LED elements are both configured to be connected to the power line or both connected to the ground. Also, the anode terminal and cathode terminal of the unused LED element of the LED chip are configured to be both electrically unconnected.

Advantages of the Invention

[0006] According to the gaming machine of the present invention, an interesting effect is realized with an efficient configuration.

Brief Description of the Drawings

[0007]

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Embodiments for Carrying Out the Invention

[0008] Hereinafter, with reference to the accompanying drawings, embodiments of the present invention will be described in the following order. <1. Structure of the gaming machine> <2. Control configuration of the gaming machine> [2.1 Main control board] [2.2 Effect control board] <3. Outline description of the operation> [3.1 Gaming state] [3.2 Symbol variation display game] [3.3 Regarding winning] [3.4 Regarding effects] <4. Opening / closing structure and arrangement of the boards> <5. Connection configuration of the boards> [5.1 Connection state of each board] [5.2 Inner frame LED relay board 400] [5.3 Front frame LED connection board 500] [5.4 Relay board 550] [5.5 Side unit upper right LED board 600] [5.6 Side unit lower right LED substrate 620] [5.7 Side unit upper LED substrate 630] [5.8 Button LED connection substrate 640] [5.9 Button LED substrate 660] [5.10 LED connection substrate 700] [5.11 Backside left relay substrate 720] [5.12 Decorative substrate 740] [5.13 Relay substrate 760] [5.14 LED substrate 780] [5.15 LED substrate 790] [5.16 Backside lower relay substrate 800] [5.17 Decorative substrate 820] <6. Other examples of the connection configuration of the substrates> [6.1 Connection state of each substrate] [6.2 LED connection substrate 1500] [6.3 LED substrate 1600] <7. Explanation of the notable configuration> [7.1 Relationship between the connector terminal and the terminal of the effect driving means] [7.2 Slave address] [7.3 Unused terminals of the chip] [7.4 Others]

[0009] <1. Structure of the pachinko machine> Referring to FIGS. 1 and 2, the structure of the pachinko machine 1 as an embodiment according to the present invention will be described. FIG. 1 is a front perspective view showing the appearance of the pachinko machine 1, and FIG. 2 is a view showing the front side of the game board 3 of the pachinko machine 1. In the case of the pachinko machine 1, it has a frame member, a door member provided to be openable and closable with respect to the frame member, and an exchange member attached to the frame member so as to be replaceable. In the pachinko machine 1 described below, it will have an inner frame 2 as a configuration corresponding to the frame member, a door 6 as a configuration corresponding to the door member, and a game board 3 as a configuration corresponding to the exchange member.

[0010] The pachinko gaming machine 1 shown in FIG. 1 (hereinafter sometimes abbreviated as "gaming machine 1") has a frame-shaped inner frame 2 attached to the front surface of a wooden outer frame 4 so as to be openable and closable, and a game board storage frame (not shown) attached to the back surface of the inner frame 2. A game board 3 (see FIG. 2) is mounted therein, and a game area 3a formed on the surface of the game board 3 faces the opening of the inner frame 2. Since the game board 3 can be detachably attached to and detached from the inner frame 2, it can be called an exchange member. In front of this game area 3a, a door 6 supporting transparent glass is provided. Also, on the back side of the game board 3, various control boards (see FIG. 3) for controlling the game operation are arranged.

[0011] On the front side (the player side) of the door 6, a side unit 10 is formed as a decoration unit that surrounds all or part of the periphery of the game board 3, for example. The side unit 10 has a decorative shape that matches the theme of the gaming machine 1 itself, and may be provided with effect members such as LEDs and accessories inside, and exhibits an effect of conveying the atmosphere of the game to the player. This side unit 10 is a unit that is detachably attached to the door 6.

[0012] On the front side of the door 6, a key cylinder (not shown) for unlocking the door is provided. By inserting a key into this key cylinder and operating it on one side, the locked state of the door 6 with respect to the inner frame 2 can be released and the door 6 can be opened to the front side. Also, by operating it on the other side, the locked state of the inner frame 2 with respect to the outer frame 4 can be released and the inner frame 2 can be opened to the front side.

[0013] Below the door 6, a front operation panel 7 pivotally supported on the inner frame 2 by a hinge (not shown) so as to be openable and closable is arranged. An upper tray unit 8 is provided on the front operation panel 7, and an upper tray 9 for storing the discharged game balls is formed in this upper tray unit 8.

[0014] In addition, the upper tray unit 8 is provided with a ball extraction button 14 for extracting the game balls stored in the upper tray 9 below the gaming machine 1, a ball lending button 11 for requesting the payout of game balls from a game ball lending device (not shown), and a card return button 12 for requesting the return of a valuable medium inserted into the game ball lending device. In addition, the upper tray unit 8 is provided with an effect button 13 (operation means) configured to be operable by the player. During a predetermined input reception period, the built-in lamp (button LED 75) is lit and the button becomes operable (input reception possible). By performing a predetermined operation (pressing, continuous hitting, long pressing, etc.) while the built-in lamp is lit, it is possible to bring about a change in the effect. In addition, the upper tray unit 8 is provided with operators such as a cross key 15a for a user such as a player or a hall staff to select various items and give direction instructions, and a decision button 15b for instructing the determination of a selected item.

[0015] In addition, on the right end side of the front operation panel 7, a firing operation handle 15 for operating the firing device 32 (see FIG. 3) is provided.

[0016] Also Door 6 On both sides of the upper part of and above the firing operation handle 15, speakers 46 that produce a sound effect (sound effect) by sound are provided. In FIG. 1, Door 6 only two speakers 46 on the upper part of are shown. With a plurality of speakers 46, so-called stereo sound reproduction and more multi-channel sound reproduction can be performed for sounds related to the effect, etc.

[0017] In addition, at appropriate positions on the door 6, a plurality of decorative lamps 45 (for example, LEDs for light effects such as full-color LEDs: see FIG. 3) that produce a light effect by light decoration are provided. As the decorative lamps 45 such as full-color LEDs (LEDs for light effects), a plurality are provided around the pachinko gaming machine 1, for example, on the periphery of the door 6 or inside the side unit 10.

[0018] Referring to FIG. 2, the configuration of the game board 3 will be described. In the illustrated game board 3, a ball guide rail 5 for guiding the launched game balls is annularly mounted as a board surface partitioning member, and a substantially circular region surrounded by the ball guide rail 5 is a game area 3a, and the four corners are non-game areas.

[0019] At substantially the center of this game area 3a, for example, in three (left, middle, right) display areas (symbol variation display areas), a liquid crystal display device (LCD) 36 capable of independently performing a variation display operation (variation display and stop display) of a plurality of types of decorative symbols (for example, a left symbol (corresponding to the left display area), a middle symbol (corresponding to the middle display area), and a right symbol (corresponding to the right display area)) using numbers, characters, symbols, etc. is provided. Under the control of an effect control board 30 described later, this liquid crystal display device 36 displays various effects as images in addition to the variation display operation of the decorative symbols.

[0020] Also, in the game area 3a, a center decoration 48 is provided so as to surround the periphery of the display surface of the liquid crystal display device 36 in a circumferential manner. The center decoration 48 is provided along the front side of the game board 3, protects the display surface of the liquid crystal display device 36 from the surrounding game balls, and serves as a flow path distribution means capable of distributing the flow path of the game balls to the left and right according to the hitting strength or stroke length of the game balls. In the present embodiment, the center decoration 48 is disposed substantially at the center of the game area 3a so that game ball flow paths are formed on both upper sides (left side and right side) within the game area 3a due to the presence of the center decoration 48. The game balls driven into the upper side of the game area 3a by the launching device 32 are distributed left and right on the upper side of the armor frame portion 48b, and flow down through either the left downward flow path 3b on the left side or the right downward flow path 3c on the right side of the center decoration 48.

[0021] Also, the non-game area at the lower part of the game board 3 serves as various function display portions, and a special symbol display device 38a (first special symbol display means) and a special symbol display device 38b (second special symbol display means) using a dot display are provided. The various function display units including the special symbol display devices 38a and 38b are shown enlarged in FIG. 4.

[0022] In the special symbol display devices 38a and 38b, a special symbol variation display game is executed by the variation display operation of the "special symbol" expressed by the dot display. And in the liquid crystal display device 36 described above, in synchronization with the variation display of the special symbol by the special symbol display devices 38a and 38b, a decorative symbol is variably displayed by an image, and a decorative symbol variation display game is executed together with various preview effects (effect images) (details of these symbol variation display games will be described later).

[0023] In addition, a composite display device (LED display for holding composite display) 38c composed of dot displays, similar to the special symbol display devices 38a and 38b, is provided in the various function display units. The reason for calling it "composite" is that it is a holding / time - shortening / high - probability composite display device (hereinafter simply referred to as the "composite display device") having five display functions, namely, the display of the number of balls held in operation for special symbols 1 and 2 and normal symbols, the state notification during the operation of the variation time - shortening function (during time - shortening) and during the high - probability state (during high - probability).

[0024] In addition, a composite display device 38d composed of dot displays is provided in the various function display units. In this composite display device 38d, a round number display for notifying the specified number of rounds (maximum number of rounds) related to a big win is performed by the combination of the lighting and extinguishing states of four LEDs. For example, the specified number of rounds (maximum number of rounds) related to a big win is notified by the combination of the lighting and extinguishing states of four LEDs. In addition, in the composite display device 38d, as a normal symbol display, a normal symbol variation display game is executed by the variation display operation of the normal symbol expressed by one LED. In addition, in the composite display device 38d, a right - hand hit display is performed by three LEDs.

[0025] Below the center decoration 48 in FIG. 2, a starting port 34 (first special symbol starting port: first starting means) is provided inside. Inside the starting port 34, a detection sensor 34a (starting port sensor 34a, see FIG. 3) for detecting the passage of a game ball is formed. Also, in the right downward flow path 3c, a starting port 35 (second special symbol starting port: second starting means) that performs an opening and closing operation is provided, and inside, a detection sensor 35a (starting port sensor 35a: see FIG. 3) for detecting the passage of a game ball is formed.

[0026] The starting port 34, which is the first special symbol starting port, is a winning port related to the starting condition of the variation display operation of the first special symbol (hereinafter, the first special symbol is referred to as "special symbol 1" and may be abbreviated as "special figure 1" in some cases) in the special symbol display device 38a, and is configured as a winning rate fixed type winning device that does not have a starting port opening and closing means (means for opening or expanding the starting port). In this embodiment, due to the action of the game ball dropping direction conversion member (for example, game nails, windmill 44, center decoration 48, etc.) in the game area 3a, for the game balls flowing down through the left downward flow path 3b, it is easy for them to enter the starting port 34 (win), while for the game balls flowing down through the right downward flow path 3c, it is difficult or impossible for them to enter.

[0027] The starting port 35 is a winning port related to the starting condition of the variation display operation of the second special symbol (hereinafter, the second special symbol is referred to as "special symbol 2" and may be abbreviated as "special figure 2" in some cases) in the special symbol display device 38b, and the winning area of this starting port 35 is configured to be openable and closable between an open state where winning is possible and a closed state where winning is impossible.

[0028] The starting port 35 is a winning port related to the starting condition of the variation display operation of the special symbol 2 in the special symbol display device 38b, and is configured as a variable starting port whose opening and closing is controlled by the normal electric accessory 41. The normal electric accessory 41 is controlled between an open state that allows a game ball to enter the starting port 35 and a closed state that makes it difficult or impossible for a game ball to enter the starting port 35.

[0029] In addition, two general winning openings 43 are provided in the lower left and right of the game area 3a, and inside each of them, a general winning opening sensor 43a for detecting the passage of the game balls is formed. In addition, in a position within the area of the game board that does not obstruct the flow-down of the game balls, a movable accessory (not shown) that produces a visual effect is arranged.

[0030] In addition, above the diagonal of the normal electric accessory 41, that is, on the upper side from the middle part of the right flow-down path 3c, a normal symbol start opening 37 (third starting means) composed of a passage gate (specific passage area) through which the game balls can pass is provided. This normal symbol start opening 37 is a winning opening related to the variable display operation of the normal symbol of the composite display device 38d, and inside it, a normal symbol start opening sensor 37a (see FIG. 3) for detecting the passing game balls is formed. In this embodiment, the normal symbol start opening 37 is formed only on the right flow-down path 3c side and not on the left flow-down path 3b side. However, the present invention is not limited to this, and it may be formed only on the left flow-down path 3b, or may be formed on both flow-down paths respectively.

[0031] In the middle of the path from the normal symbol start opening 37 in the right flow-down path 3c, a special variable winning device 52 (special electric accessory) configured to be able to open or expand the big winning opening 50 by an opening door 52b is provided, and inside it, a big winning opening sensor 52a (see FIG. 3) for detecting the game balls that have entered the big winning opening 50 is formed. Around the big winning opening 50, a guide part 55 and a windmill 53 that function to direct the flowing-down game balls in the direction of the big winning opening 50 are provided.

[0032] The process of the game balls entering the big winning opening 50 is as follows. The game balls that have passed through the floating area between the upper surface of the center decoration 48 and the ball guiding rail 5 and passed through the right flow-down path 3c are guided in the direction of the big winning opening 50 by the guide part 55. If the big winning opening 50 is in an open state (big winning opening open state), the game balls are guided into the big winning opening 50.

[0033] In the gaming machine 1 of the present embodiment, when a player aims at the firing position on the side of the special variable winning device 52 (when aiming so that the game ball passes through the right downward flow path 3c), it is configured such that it is difficult or impossible to guide the game ball to the starting port 34 side. Therefore, if it is in the "big winning port closed state", winning at the starting port 34 is made difficult or impossible. In addition, when the gaming state with electric support described later is entered, the starting port 35 operates with an opening / closing pattern more advantageous than the normal state.

[0034] In the case of the present embodiment, how the player should play to get an advantageous situation changes according to the gaming state. Specifically, in the gaming state with "no electric support" described later, "left hitting" which aims so that the game ball passes through the left downward flow path 3b is advantageous, and in the gaming state with "electric support" described later, "right hitting" which aims so that the game ball passes through the right downward flow path 3c is advantageous.

[0035] In the gaming machine 1 of the present embodiment, when there is a winning at a winning port other than the normal symbol starting port 37 among the various winning ports provided in the gaming area 3a, the number of prize balls per winning ball (for example, 3 for the starting port 34 or the starting port 35, 13 for the big winning port 50, 10 for the general winning port 43) promised for each winning port is paid out from the game ball payout device 19 (see FIG. 3). The game balls that did not win at the above-mentioned winning ports are discharged from the gaming area 3a through the out port 49.

[0036] Here, "winning" means that when the winning opening takes in a game ball into its interior, or when the winning opening consists of a through-type gate rather than a structure that takes in a game ball into its interior (for example, the normal symbol start opening 37), it means that the game ball passes through that gate. In practice, when a game ball is detected by each winning detection switch formed for each winning opening, it is regarded that "winning" has occurred at that winning opening. The game ball related to this winning is also referred to as a "winning ball". Note that if a game ball enters the winning opening, the game ball will be detected by the winning detection switch. Therefore, in this specification, unless otherwise specified, regardless of whether a game ball is detected by the winning detection switch, the case where a game ball enters the winning opening may be referred to as "winning".

[0037] <2. Control Configuration of the Gaming Machine> Referring to the block diagram of FIG. 3, the configuration (control configuration) for realizing the game operation control of the gaming machine 1 will be described. The gaming machine 1 of this embodiment includes a main control board (main control means) 20 that comprehensively controls the control related to all game operations (game operation control), an effect control board 30 (effect control means) that receives an effect control command from the main control board 20 and comprehensively controls the execution control (appearance control) of the effect by the effect means, a payout control board (payout control means) 29 that performs the payout control of the prize balls, and a power supply board (power supply control means (not shown)) that generates and supplies the power required for the gaming machine 1 from an external power supply (not shown). In addition, in FIG. 3, the power supply routes to each part are omitted.

[0038] [2.1 Main Control Board] The main control board 20 is equipped with a microprocessor incorporating a CPU (Central Processing Unit) 20a (main control CPU), and in addition to a control program describing the game operation control procedure, it also has a ROM (Read Only Memory) 20b (main control ROM) that stores various data necessary for game operation control, and a RAM (Random Access Memory) 20c (main control RAM) that functions as a work area and buffer memory, and as a whole, it constitutes a microcomputer.

[0039] Although not shown in the figure, the main control board 20 also has a CTC (Counter Timer Circuit) for realizing functions such as periodic interrupts, creating pulse outputs with a fixed period (bit rate generator), and time measurement, and an interrupt controller circuit that exhibits an interrupt enable / interrupt disable function such as timer interrupts that give an interrupt signal to the main control CPU 20a, and a reset circuit that can detect power-on, power-off, power abnormalities, etc., output a system reset signal, and reset the main control CPU 20a, and a watchdog timer (WDT) circuit that monitors the abnormal operation of the control program, and a designated area outside running prohibition (IAT) circuit that monitors whether the program is being correctly executed within a preset address range, and a counter circuit for generating a certain range of random numbers in hardware, etc.

[0040] The above counter circuit is composed of a random number generation circuit that generates random numbers and a sampling circuit that samples the random number value from the random number generation circuit at a predetermined timing, and functions as a 16-bit counter as a whole. The main control CPU 20a sends an instruction to the above sampling circuit according to the processing state, and acquires the numerical value indicated by the random number generation circuit as an internal lottery random number value (big win determination random number (random number size: 65536)), and uses this random number value for big win lottery. Note that the internal lottery random number is obtained by adding a soft random number value generated by appropriate software processing to prevent blatant acts such as aiming for wins and a hard random number value.

[0041] On the main control board 20, a start port sensor 34a for detecting a winning (a ball entering) at the start port 34, a start port sensor 35a for detecting a winning at the start port 35, a normal symbol start port sensor 37a for detecting the passage through the normal symbol start port 37, a big winning port sensor 52a for detecting a winning at the big winning port 50, a general winning port sensor 43a for detecting a winning at the general winning port 43, and an OUT monitoring switch 49a for detecting a game ball (an out ball) discharged from the out port 49 are connected, and the main control board 20 is enabled to receive detection signals output from these. Based on the detection signals from each sensor, the main control board 20 can grasp which winning port the game ball has entered.

[0042] Also, on the main control board 20, a normal electric accessory solenoid 41c for opening and closing the movable wing piece of the start port 35 and a big winning port solenoid 52c for opening and closing the opening door 52b of the big winning port 50 are connected, and the main control board 20 can transmit control signals for controlling these.

[0043] Furthermore, on the main control board 20, a special symbol display device 38a and a special symbol display device 38b are connected, and the main control board 20 can transmit control signals for controlling the display of special symbols 1 and 2. Furthermore, on the main control board 20, a composite display device 38c is connected, and the main control board 20 can transmit control signals for controlling the hold number display and the status display.

[0044] Also, on the main control board 20, a composite display device 38d is connected, and the main control board 20 can transmit control signals for controlling the display of the normal symbol display, the right hitting display, and the round display displayed on the composite display device 38d.

[0045] Furthermore, on the main control board 20, a frame external centralized terminal board 21 is connected, and the main control board 20 can transmit predetermined game information (for example, jackpot information, prize ball number information, symbol variation execution information, etc.) to a hall computer HC provided outside the gaming machine via the frame external centralized terminal board 21. The hall computer HC is an information processing device (computer device) that monitors game information from the main control board 20 and comprehensively manages the operating status of the gaming machines in the pachinko hall.

[0046] Furthermore, a payout control board (payout control unit) 29 is connected to the main control board 20. When it is necessary to pay out bonus balls, a control command regarding payout (a payout control command specifying the number of bonus balls) can be transmitted to the payout control board 29.

[0047] Connected to the payout control board 29 are a launch control board (launch control unit) 28 that controls the launcher 32 and a game ball payout device (game ball payout means) 19 that pays out game balls. The main roles of this payout control board 29 are to receive a payout control command from the main control board 20, control the payout of bonus balls by the game ball payout device 19 based on the payout control command, and transmit a status signal to the main control board 20.

[0048] The game ball payout device 19 is provided with a replenishment shortage detection sensor 19a that detects a shortage in the supply of game balls and a ball counting sensor 19b that detects the game balls (bonus balls) being paid out. The payout control board 29 is capable of receiving these respective detection signals. Also, the game ball payout device 19 is provided with a payout motor 19c that drives a ball payout mechanism section (not shown) for paying out game balls. The payout control board 29 is capable of transmitting a control signal for controlling the payout motor 19c.

[0049] Furthermore, connected to the payout control board 29 are a full cup detection sensor 60 that detects when the upper receiving tray 9 is full of game balls (in this embodiment, a detection sensor that detects the storage state of the game balls stored in the upper receiving tray 9) and a front door open sensor 61 (for example, a detection sensor that detects the open state of the door 6 or the inner frame 2).

[0050] The payout control board 29 is capable of transmitting various status signals to the main control board 20 based on detection signals from the full detection sensor 60, the front door open sensor 61, the supply shortage detection sensor 19a, and the ball counting sensor 19b. These status signals include a ball jamming signal indicating a full state, a door open signal indicating that at least the inner frame 2 is open, a supply shortage signal indicating a shortage in the supply of game balls from the game ball payout device 19, a counting error signal indicating a shortage in the payout of bonus balls or an abnormality in the ball counting sensor 19b, a payout completion signal indicating that the payout operation has been completed, and so on, and is configured to be able to transmit various status signals. Based on these status signals, the main control board 20 monitors the open state of the inner frame 2 (door open error), whether the payout operation of the game ball payout device 19 is normal (supply shortage error), the full state of the upper tray 9 (ball jamming error), etc.

[0051] Furthermore, a firing control board 28 is connected to the payout control board 29, and the payout control board 29 is capable of transmitting a permission signal to permit firing to the firing control board 28. Based on the fact that a permission signal is output from the payout control board 29, the firing control board 28 controls the energization of a firing solenoid (not shown) provided in the firing device 32 to realize the firing operation of the game ball by operating the firing operation handle 15. Specifically, the firing operation is permitted on the condition that a firing permission signal is output from the payout control board 29 (firing permission signal ON state), it is detected by a touch sensor provided on the firing operation handle 15 that the player is touching the handle, and a firing stop switch (not shown) provided on the firing operation handle 15 is not operated. Therefore, when the firing permission signal is not output (firing permission signal OFF state), the firing operation is not executed even if the firing operation handle 15 is operated, and the game ball is not fired. Also, the strength of the game ball being launched can be changed according to the amount of operation of the firing operation handle 15. When the payout control board 29 detects the above-mentioned ball jamming error, it transmits a ball jamming signal to the main control board 20 and stops the output of the firing permission signal to the firing control board 28 (firing permission signal OFF), and performs control to stop the firing operation until the full state of the upper tray 9 is resolved. In addition, the payout control board 29 outputs an emission permission signal to the emission control board 28 on the condition that emission permission is instructed from the main control board 20.

[0052] A RAM clear switch 98 is connected to the main control board 20, and the main control board 20 is enabled to receive a detection signal from these switches.

[0053] The RAM clear switch 98 is, for example, a push-button type switch for instructing an input to initialize a predetermined area of the main control RAM 20c.

[0054] The RAM clear switch 98 is turned ON / OFF in response to an operation of a RAM clear button provided so as to be operable when the inner frame 2 is open. The RAM clear switch 98 is provided at an appropriate position inside the gaming machine 1. For example, it is arranged on the main control board 20.

[0055] In addition, a performance display 97 is connected to the main control board 20. The performance display 97 is configured to have, for example, a seven-segment display, and functions as display means capable of displaying performance information (described later). The performance display 97 is mounted, for example, at a position on the main control board 20 where it is easily visible.

[0056] (Regarding performance display) The main control board 20 is enabled to transmit a control signal for causing the performance display 97 to display predetermined performance information. The performance information is information that a pachinko parlor or related agencies want to confirm. Representative examples thereof include the presence or absence of illegal winning balls such as excessive winning balls for the gaming machine 1 and the original ball payout performance of the gaming machine 1. Therefore, unlike a pre-announcement effect or the like, the performance information itself is information that has no direct relation to the progress of the game when a player enjoys the game.

[0057] Therefore, the performance display 97 is provided at a position where the display information can be visually recognized when the inner frame 2 is in an open state, inside the gaming machine 1, for example, on the main control board 20, the payout control board 29, the emission control board 28, the above relay board, the effect control board 30, or in the board case (protective cover for protecting the board).

[0058] Here, specifically, the following information can be adopted as the performance information.

[0059] (1) Information (specific ratio information) based on the value (α / β) obtained by dividing the total number of payouts (specific total prize balls: α) paid out due to winning during a specific state by the total number of out balls (specific out number: β) discharged from the game area 3a during the specific state can be adopted as the performance information. The above "total number of payouts" is the total value of the game balls (prize balls) paid out when winning at the winning ports (starting ports 34 and 35, general winning port 43, big winning port 50). In the case of this embodiment, there are 3 starting ports 34 or 35, 13 big winning ports 50, and 10 general winning ports 43. Also, regarding which state to adopt as the specific state, it can be appropriately determined according to what performance information in what state is to be grasped. In the case of this embodiment, any of the normal state, potential probability state, time-saving state, probability variation state, and big win game state can be adopted. Also, multiple types of states may be the measurement targets. For example, the normal state and the probability variation state, or all game states except during the win game, etc., and the types to be the measurement targets can be appropriately determined. Also, as the period during the specific state, a period in which the big win lottery probability is either in the low probability state or the high probability state may be adopted. Also, the total number of payouts excluding one or more specific winning ports from the measurement targets (total number of payouts excluding specific winning ports) may be used. For example, among each winning port, the one excluding the big winning port 50 from the measurement targets may be used as the total number of payouts.

[0060] (2) Alternatively, only any one of the total number of payouts, the total number of payouts excluding specific winning ports, and the total number of out balls may be measured, and the measurement result may be used as the performance information.

[0061] In this embodiment, the total number of payouts during the normal state (number of payouts during normal times) and the total number of out balls during the normal state (number of out balls during normal times) are measured in real time, and the value obtained by multiplying the value obtained by dividing the number of payouts during normal times by the number of out balls during normal times by 100 (the value calculated by number of payouts during normal times ÷ number of out balls during normal times × 100) is displayed as performance information (hereinafter referred to as "normal ratio information"). Note that the displayed value at this time is a value obtained by rounding off the first digit after the decimal point. Therefore, each data of the number of payouts during normal times, the number of out balls during normal times, and the normal ratio information is stored (memorized) in the corresponding area (specific total prize ball number storage area, specific out ball number storage area, specific ratio information storage area) of the main control RAM 20c. However, it does not simply measure permanently and display the performance information. When the total number of out balls reaches a predetermined specified number (for example, 60,000), the measurement is once terminated. This specified number is not the total number of out balls in the normal state, but the total number of out balls during all game states (including during winning games) (hereinafter referred to as "total state out ball number"). This total state out ball number is also measured in real time and stored in the corresponding area (total state out ball number storage area) of the main control RAM 20c. Hereinafter, for convenience of explanation, the specific total prize ball number storage area, the specific out ball number storage area, the specific ratio information storage area, and the total state out ball number storage area are abbreviated as "measurement information storage area".

[0062] Then, the normal ratio information at the end time is stored in a predetermined area (performance display storage area) of the main control RAM 20c (store the normal ratio information this time), and then, after clearing the measurement information storage area (number of payouts during normal times, number of out balls during normal times, and total state out ball number), the measurement is started again (start the measurement of the number of payouts during normal times, the number of out balls during normal times, the normal ratio information, and the total state out ball number). And on the performance display 97, the previous normal ratio information (measurement history information) and the normal ratio information currently being measured are displayed. Note that not only the previous information but also the history such as the one before the previous time or the one before that (three times before) may be configured to be displayable, and it can be appropriately determined how many times before the information is to be displayed.

[0063] (Performance control command) The main control board 20 can transmit various performance control commands including information related to the special symbol variation display game and information related to errors, etc. to the performance control board 30 according to the processing state. However, in order to prevent fraud such as GOT behavior, etc., the main control board 20 is configured for one-way communication that only transmits signals to the performance control board 30 and cannot receive signals from the performance control board 30.

[0064] Here, the performance control command defines its function by a 2-byte configuration consisting of a 1-byte mode (MODE) and also a 1-byte event (EVENT). In order to distinguish between MODE and EVENT, Bit7 of MODE is ON and Bit7 of EVENT is OFF. When transmitting these valid pieces of information, strobe signals are output corresponding to each of the mode (MODE) and event (EVENT). That is, when there is a command to be transmitted, the main control CPU 20a sets and outputs the mode (MODE) information for transmitting the command to the performance control board 30, and transmits the first strobe signal after a predetermined time has elapsed from this setting. Further, after a predetermined time has elapsed from the transmission of this strobe signal, the event (EVENT) information is set and output, and the second strobe signal is transmitted after a predetermined time has elapsed from this setting. The strobe signal is controlled to be in an active state by the main control CPU 20a for a predetermined period during which the performance control CPU 30a can surely receive the command.

[0065] [2.2 Performance control board] The performance control board 30 is mainly composed of a microcomputer equipped with a microprocessor incorporating a performance control CPU 30a, and also equipped with a performance control ROM 30b storing performance data required for performance control processing and a performance control RAM 30c functioning as a work area and a buffer memory. In addition, an acoustic control unit (sound source IC), an RTC (Real Time Clock) function unit, a counter circuit, an interrupt controller circuit, a reset circuit, a WDT circuit, etc. are provided to control the entire performance operation.

[0066] The performance control CPU 30a performs arithmetic processing for various performance operations and controls each performance means based on the performance control program and the performance control commands received from the main control unit 20. The performance means, in the case of the pachinko gaming machine 1 of the present embodiment, includes a liquid crystal display device 36 (main liquid crystal display device 36M, sub liquid crystal display device 36S), a light display device 45a, an acoustic generator 46a, and a movable accessory (not shown).

[0067] The performance control ROM 30b stores a control program for performance operations by the performance control CPU 30a and various data necessary for performance operation control. The performance control RAM 30c is used as a work area for the performance control CPU 30a to perform various arithmetic processes, a table data area, a buffer area for various input / output data and processing data, and the like. Note that the performance control board 30 is configured to mount, for example, a one-chip microcomputer and its peripheral circuits, but various configurations of the performance control board 30 are conceivable. For example, in addition to the microcomputer, an interface circuit with each unit, a random number generation circuit for generating lottery random numbers for performances, a CTC for various time counts, a watchdog timer (WDT) circuit, an interrupt controller circuit for giving an interrupt signal to the performance control CPU 30a, etc. may be provided.

[0068] The main roles of this performance control board 30 are to receive performance control commands from the main control unit 20, select and determine performances based on the performance control commands, control the display of the liquid crystal display device 36 (supply display data), control the voice output of the acoustic generator 46a, control the light emission of the light display device 45a (LED), control the operation of the movable accessory (drive control of the movable accessory motor 80c), and so on.

[0069] Since this performance control board 30 also has a function as a control device for the liquid crystal display device 36, the performance control board 30 is also provided with functions as a so-called VDP (Video Display Processor), an image ROM, and a VRAM (Video RAM), and the performance control CPU 30a also functions as a liquid crystal control unit. The VDP refers to a function that controls all video output processes such as image expansion processing and image drawing. The image ROM refers to the memory in which image data (production image data) for the VDP to perform image expansion processing is stored. VRAM is an image memory area that temporarily stores the image data expanded by the VDP.

[0070] With these configurations, the production control board 30 generates various image data based on commands from the main control unit 20 and outputs it to the main liquid crystal display device 36M and the sub liquid crystal display device 36S. As a result, various production images are displayed on the main liquid crystal display device 36M and the sub liquid crystal display device 36S. Here, the "liquid crystal display device 36" shown in FIG. 2 is the "main liquid crystal display device 36M". The illustration of the sub liquid crystal display device 36S is omitted in FIG. 2.

[0071] The production control board 30 also has an acoustic control unit (for example, the sound controller 230 in FIG. 4) for the acoustic generating device 46a including a plurality of speakers 46. The acoustic signal output by the acoustic control unit is amplified by the amplifier unit 46d and supplied to the speaker 46. Although the sound controller 230 as the acoustic control unit is described as being built into the production control board 30, the acoustic control unit may use a separate sound source IC from the production control board 30. The production control board 30 is also connected to a lamp driver unit 45d that functions as a light display control unit for the light display device 45a including a decorative lamp 45 and various LEDs, and a motor driver unit 80d (motor drive circuit) that functions as a drive control unit for the movable object actuator motor 80c that operates a movable object (not shown). The production control board 30 controls the light display operation by the light display device 45a and the operation of the movable object actuator motor 80c by giving instructions to these lamp driver unit 45d and motor driver unit 80d.

[0072] The production control board 30 is also connected to a home position switch 81 and a position detection sensor 82 for monitoring the operation of the movable object actuator. The home switch 81 is composed of, for example, a photo interrupter or the like, and detects whether or not the movable object actuator motor 80c is at the home position. The home position is, for example, a position where the movable object does not normally appear on the board surface of FIG. 2. The effect control board 30 is capable of determining whether or not the movable object actuator motor 80c is at the home position based on the detection information of this home switch 81. Also, the effect control board 30 controls the operation mode of the movable object actuator while monitoring the current operation position (for example, the amount of movement from the home position) of the movable object actuator based on the detection information from the position detection sensor 82. Further, the effect control board 30 monitors malfunctions in the operation of the movable object actuator based on the detection information from the position detection sensor 82, and if a malfunction occurs, it detects this as an error.

[0073] Also, switches of the effect buttons 13, the cross keys 15a, and the enter button 15b shown as the operation unit 17 in the figure, that is, operation detection switches of the effect buttons 13, the cross keys 15a, and the enter button 15b, are connected to the effect control board 30, and the effect control board 30 is capable of receiving operation detection signals from the effect buttons 13, the cross keys 15a, and the enter button 15b, respectively.

[0074] Furthermore, a handle sensor 83 (touch sensor) for detecting whether or not the firing operation handle 15 shown in FIG. 1 is touched by a user such as a player is provided on the effect control board 30. The effect control board 30 is capable of determining whether or not the firing operation handle 15 is touched by the user based on the detection information of this handle sensor 83.

[0075] The performance control board 30 selects (determines) a performance pattern by lottery or uniquely from a plurality of types of prepared performance patterns based on the performance control commands sent from the main control unit 20, and controls various performance means at the necessary timing to present the target performance. As a result, the display of the performance image by the liquid crystal display device 36 corresponding to the performance pattern, the reproduction of sound from the speaker 46, and the lighting and blinking drive of the decorative lamp 45 and the LED are realized. By sequentially developing various performance patterns (such as the variable display operation of the decorative pattern and the preview performance), a "performance scenario" in a broad sense is realized.

[0076] Here, regarding the performance control command, the performance control board 30 (performance control CPU 30a) generates an interrupt process based on the input of the above-described strobe signal transmitted by the main control unit 20 (main control CPU 20a) and receives and analyzes it. Specifically, the performance control CPU 30a executes a control program for command reception interrupt processing based on the input of the above-described strobe signal, and in the interrupt process realized thereby, acquires the performance control command and analyzes the command content. At this time, when an interrupt occurs based on the input of the strobe signal, the performance control CPU 30a interrupts the process and performs command reception interrupt processing even during the execution of an interrupt process based on another interrupt (timer interrupt process that is periodically executed), and preferentially performs command reception interrupt processing even if another interrupt occurs simultaneously.

[0077] <3. Overview of the operation> Next, an overview of the gaming operation of the gaming machine 1 realized by the above control configuration (Figure 3) will be described.

[0078] [3.1 Gaming state] In the gaming machine 1, in addition to the big win game which is a special gaming state, a plurality of types of gaming states can be set. For the sake of easy understanding of this embodiment, first, various gaming states will be described.

[0079] The gaming machine 1 conducts games in any of the gaming states in which either the low-probability state or the high-probability state is combined with either the non-time-limit state or the time-limit state.

[0080] The low-probability state is a state where the winning probability of the jackpot lottery is relatively low, and the high-probability state is a state where the winning probability of the jackpot lottery is relatively high. The non-time-limit state is a state where it is relatively difficult for game balls to enter the start port 35, and the time-limit state is a state where it is relatively easy for game balls to enter the start port 35. For example, in the time-limit state, the opening time of the start port 35 when winning the normal pattern lottery is set longer than that in the non-time-limit state. However, if game balls are more likely to enter the start port 35 in the time-limit state than in the non-time-limit state, in the time-limit state, for example, the winning probability of the normal pattern lottery may be increased or the variation time of the normal symbol may be shortened compared to the non-time-limit state.

[0081] In the present embodiment, the "normal state" refers to the low-probability state and the non-time-limit state, corresponding to the initial state.

[0082] [3.2 Symbol Variation Display Game] The symbol variation display game will be described.

[0083] (Special Symbol Variation Display Game) In the pachinko gaming machine 1 of the present embodiment, based on a predetermined start condition, specifically, when a game ball enters (wins) the start port 34 or the start port 35, a "jackpot lottery" by random number lottery is conducted on the main control board 20. Based on the lottery result, the main control board 20 variably displays the special symbol 1 and the special symbol 2 on the special symbol display devices 38a and 38b to start the special symbol variation display game, and after a predetermined time has elapsed, the result is derived and displayed on the special symbol display device, thereby ending the special symbol variation display game.

[0084] Here, in the present embodiment, the jackpot lottery based on winning at the start port 34 and the jackpot lottery based on winning at the start port 35 are carried out separately and independently. For this reason, the jackpot lottery result regarding the start port 34 is derived on the special symbol display device 38a side, and the jackpot lottery result regarding the start port 35 is derived on the special symbol display device 38b side. Specifically, on the special symbol display device 38a side, on the condition that a game ball enters the start port 34, the special symbol 1 is variably displayed and the first special symbol variable display game is started. On the other hand, on the special symbol display device 38b side, on the condition that a game ball enters the start port 35, the special symbol 2 is variably displayed and the second special symbol variable display game is started. Then, when the special symbol variable display game in the special symbol display device 38a or the special symbol display device 38b is started, after a predetermined variable display time has elapsed, if the jackpot lottery result is "jackpot", it is in a predetermined "jackpot" mode, and in other cases, it is in a predetermined "losing" mode, and the special symbol during variable display stops being displayed, whereby the game result (jackpot lottery result) is derived.

[0085] In this specification, for convenience of explanation, the first special symbol variable display game on the special symbol display device 38a side is referred to as "special symbol variable display game 1", and the second special symbol variable display game on the special symbol display device 38b side is referred to as "special symbol variable display game 2". Also, unless particularly necessary, "special symbol 1" and "special symbol 2" are simply referred to as "special symbol" (abbreviated as "special drawing" in some cases), and "special symbol variable display game 1" and "special symbol variable display game 2" are simply referred to as "special symbol variable display game".

[0086] (Decoration symbol variable display game) Also, when the above special symbol variation display game is started, accordingly, a decorative symbol (an effect game symbol) is variably displayed on the main liquid crystal display device 36M to start the decorative symbol variation display game, and various effects are developed accordingly. Then, when the special symbol variation display game ends, the decorative symbol variation display game also ends, and a predetermined special symbol indicating the jackpot lottery result is displayed on the special symbol display device, and a decorative symbol reflecting the jackpot lottery result is derived and displayed on the main liquid crystal display device 36M. That is, the result of the special symbol variation display game is reflected and displayed by the effect decorative symbol variation display game including the variable display operation of the decorative symbol.

[0087] Therefore, for example, when the result of the special symbol variation display game is a "jackpot" (when the jackpot lottery result is a "jackpot"), an effect reflecting the result is developed in the decorative symbol variation display game. Then, when the special symbol is stopped and displayed in a display mode indicating a jackpot (for example, the 7-segment is in the display state of "7") on the special symbol display device, on the main liquid crystal display device 36M, in each of the display areas of "left", "middle", and "right", the decorative symbol is stopped and displayed in a display mode reflecting the "jackpot" (for example, in each of the display areas of "left", "middle", and "right", the three decorative symbols are in the display state of "7", "7", and "7").

[0088] When such a "big win" occurs, specifically, after the special symbol variation display game ends, the decorative symbol variation display game also ends accordingly, and as a result, after the symbol pattern of the "big win" is derived and displayed, the big winning opening solenoid 52c of the special variation winning device 52 activates and the opening / closing door 52b performs an opening / closing operation in a predetermined pattern, thereby opening and closing the big winning opening 50, and a special gaming state (big win game) that is more advantageous to the player than the normal gaming state is generated. In this big win game, by the opening / closing door 52b, until the opening time of the big winning opening elapses for a predetermined time (maximum opening time: for example, 29.8 seconds), or until the number of game balls that have won in the big winning opening (winning balls in the big winning opening 50) reaches a predetermined number (maximum number of wins: the upper limit number of winning balls allowed for a winning opening whose entrance has opened or expanded due to one operation of the accessory: for example, 9 balls), the winning area is opened or expanded, and when any of these conditions are met, the big winning opening is closed, and a "round game" like this is repeated a predetermined number of specified rounds (for example, a maximum of 16 rounds).

[0089] When the above big win game starts, first, an opening performance notifying that the big win has started is performed. After the opening performance ends, the round game is performed a plurality of times with a predetermined number of specified rounds as the upper limit. Then, after the specified number of rounds ends, an ending performance notifying that the big win has ended is performed, and thereby the big win game ends.

[0090] Regarding the information necessary for executing the above-described decorative symbol variation display game, first, based on the fact that a game ball has entered (won a prize) the start port 34 or the start port 35, specifically, on the condition that the game ball is detected by the start port sensor 34a or the start port sensor 35a and the start condition (start condition regarding special symbols) is satisfied, a 'win / loss lottery (win / loss type lottery)' for determining whether it is a 'big win' or a 'loss' is conducted, and if it is a 'big win', the big win type is selected, and if it is a 'loss', the loss type is selected. A big win lottery including a'symbol lottery (winning type (big win type) lottery)' is performed (when there is only one type of loss, it is not necessary to conduct a type lottery for the loss, so this lottery may be omitted). Based on the lottery result information, the variation pattern of the special symbol and the special symbol (hereinafter referred to as the 'Special Stop Symbol') that is finally stopped and displayed according to the winning type are determined.

[0091] Then, the main control board 20 transmits a 'Variation Pattern Designation Command' including at least the variation pattern information of the special symbol (for example, information regarding the big win lottery result and the variation time of the special symbol, etc.) to the effect control board 30 side as an effect control command for specifying the processing state. Thereby, the basic information necessary for the decorative symbol variation display game is sent to the effect control board 30. In this embodiment, in order to make the effects more diverse, a 'Decorative Symbol Designation Command' including the information of the Special Stop Symbol (symbol lottery result information (information regarding the big win type)) is also transmitted to the effect control board 30.

[0092] The variable pattern information of the special symbol can include information specifying the occurrence or non-occurrence of a specific pre-announcement effect (for example, the "reach effect" or "pseudo-consecutive effect" described later). Specifically, the variable pattern of the special symbol is broadly classified into a "win variable pattern" in the case of a win and a "loss variable pattern" in the case of a loss according to the jackpot lottery result. These variable patterns include, for example, a "reach variable pattern" that designates the occurrence of the reach effect described later, a "normal variable pattern" that does not designate the occurrence of the reach effect, a "pseudo-consecutive with reach variable pattern" that designates the occurrence of both the pseudo-consecutive effect and the reach effect (duplicate occurrence), a "pseudo-consecutive with normal variable pattern" that designates the occurrence of the pseudo-consecutive effect and does not designate the occurrence of the reach effect, and other multiple types of variable patterns. In relation to ensuring the performance time of the reach effect and the pseudo-consecutive effect, usually, the variable patterns that designate the reach effect and the pseudo-consecutive effect are set to have a longer variable time than the normal variable pattern.

[0093] Based on the information included in the effect control commands (here, the variable pattern designation command and the decorative symbol designation command) sent from the main control board 20, the effect control board 30 determines the effect content (effect scenario such as pre-announcement effect) to be developed in chronological order during the decorative symbol variable display game and the decorative symbol (decorative stop symbol) to be finally stopped and displayed, and executes the decorative symbol variable display game by variably displaying the decorative symbol according to the time schedule based on the variable pattern of the special symbol. As a result, in synchronization with the variable display of the special symbol by the special symbol display devices 38a and 38b in terms of time, the decorative symbol is variably displayed by the main liquid crystal display device 36M, and the period of the special symbol variable display game and the period during the decorative symbol variable display game have substantially the same time width. Also, the effect control board 30 controls the main liquid crystal display device 36M, the light display device 45a, or the sound generation device 46a respectively so as to correspond to the effect scenario, and develops various effects in the decorative symbol variable display game. Thereby, the reproduction of the image (image effect) on the main liquid crystal display device 36M, the reproduction of the sound effect (sound effect), and the lighting and blinking drive of the decorative lamp 45, the LED, etc. (light effect) are realized.

[0094] In this way, the special symbol variable display game and the decorative symbol variable display game have an inseparable relationship, and what reflects the display result of the special symbol variable display game is expressed in the decorative symbol variable display game. Therefore, these two symbol variable display games may be regarded as equivalent symbol games. In this specification, unless particularly necessary, the above two symbol variable display games may sometimes be simply referred to as the "symbol variable display game".

[0095] (Normal symbol variable display game) Also, in the gaming machine 1, based on the fact that a game ball has passed (won) through the normal symbol start port 37, a "subsidy winning lottery" by random number lottery is performed on the main control board 20. Based on the lottery result, the normal symbol expressed by the LED is variably displayed by the composite display device 38d to start the normal symbol variable display game, and after a certain period of time has elapsed, the result is stopped and displayed in a combination of lighting and non-lighting of the LED. For example, when the result of the normal symbol variable display game is "with subsidy", the display part of the normal symbol of the composite display device 38d is stopped and displayed in a specific lighting state (for example, all 2 LEDs 39 are in the lighting state, or the LED on the "○" side among the LEDs expressing "○" and "×" is in the lighting state).

[0096] When this "with subsidy" occurs, the normal electric accessory solenoid 41c (see FIG. 3) operates, whereby the movable vane piece opens and the start port 35 is opened or enlarged to a state where it is easy for game balls to flow in (start port open state), and an auxiliary gaming state (hereinafter referred to as the "normal electric open gaming") that is more advantageous to the player than the normal gaming state occurs. In this normal electric open gaming, by the movable vane piece, until a predetermined time (for example, 0.2 seconds) has elapsed for the opening time of the start port 35, or until the number of game balls winning in the start port 35 reaches a predetermined number (for example, 4), the winning area is opened or enlarged, and the operation of closing the start port 35 when any of these conditions is satisfied is repeated a predetermined number of times (for example, up to 2 times).

[0097] (Regarding suspension) Here, in the present embodiment, during a special / decorative symbol variable display game, a normal symbol variable display game, a big win game, or a general electric release game, etc., when a winning occurs at the start port 34 or the start port 35 or the normal symbol start port 37, that is, when there is an input of a detection signal from the start port sensor 34a or the start port sensor 35a or the normal symbol start port sensor 37a and the corresponding start condition (symbol game start condition) is satisfied, this is used as data related to the start right of the variable display game and is stored in reservation up to a predetermined upper limit value, the maximum number of reserved memories (for example, a maximum of 4), excluding those related to during the variable display. The reserved data that is not being used for this symbol variable display operation, or the game balls related to that reserved data, is also referred to as "activated reserved balls". To make the number of these activated reserved balls clear to the player, a dedicated reservation display (not shown) provided at an appropriate location on the gaming machine 1, or a reservation display provided as an icon image on the screen by the liquid crystal display device 36 (main liquid crystal display device 36M or sub-liquid crystal display device 36S) is lit and displayed.

[0098] Also, in the present embodiment, the activated reserved balls related to the special symbol 1, the special symbol 2, and the normal symbol are each stored in reservation in the corresponding storage area of the main control RAM 20c up to a maximum of 4, and are reserved as the number of times the special symbol or the normal symbol is determined to vary. Note that the maximum storage number (maximum reserved memory number) of the number of activated reserved balls related to the special symbol 1, the special symbol 2, and the normal symbol is not particularly limited. Also, all or part of the maximum reserved memory numbers of each symbol may be different, and the number can be appropriately determined according to the game properties.

[0099] [Regarding 3.3 Hits] Subsequently, the "hit" in the gaming machine 1 will be described. In the gaming machine 1 of the present embodiment, a big win lottery (hit lottery) is performed for a plurality of types of hits. In this example, the types of hits include big wins belonging to the big win type, such as "normal 4R", "normal 6R", "certain variation 6R", and "certain variation 10R". Note that the notation "R" means the specified number of rounds (maximum number of rounds).

[0100] The big win type is the win that triggers the operation of the condition device. Here, the "condition device" refers to a device whose operation is required for the operation of the continuous operation device of the accessories for the round game, and which operates when a specific combination of special symbols is displayed or when the game ball passes through a specific area within the big winning opening.

[0101] The above-mentioned certain probability variation state becomes a so-called "number-of-times cut certain probability machine (ST machine)" that ends the high probability state and shifts to the low probability when the number of executions of the special symbol variation display game ends without winning the big win type (for example, 70 times: specified ST number of times). When the specified ST number of times ends, it shifts to the normal state from the next game. However, it may be a "general certain probability machine" of the type that continues until the next big win is won.

[0102] Note that the number of executions of the special symbol variation display game may be the total number of executions of the special symbol variation display game 1 and the special symbol variation display game 2 (the total number of variations of special figure 1 and special figure 2), or the number of executions of either one (for example, the number of executions of the special symbol variation display game 2). Also, the number of times in the time-saving state is not limited to 60 times or 100 times, and can be appropriately determined according to the game characteristics. Also, there are no particular restrictions on what types of wins are provided, and they can be appropriately determined.

[0103] Here, in this example, similar to the big win type, a plurality of types are provided for "losing". Specifically, three types of losing types, namely "losing 1", "losing 2", and "losing 3", are provided. As described above, when the result of the win / loss lottery is "losing", the lottery for the losing type is conducted in the symbol lottery.

[0104] [3.4 Regarding the effects] (Effect mode) Next, the presentation mode (presentation state) will be described. The gaming machine 1 of the present embodiment is provided with a plurality of types of presentation modes for presenting presentations related to the gaming state, and is configured to be able to move back and forth between the presentation modes. Specifically, a normal presentation mode, a time-saving presentation mode, a potential-win confirmation presentation mode, and a probability-variable presentation mode corresponding to the normal state, the time-saving state, the potential-win confirmation state, and the probability-variable state, respectively, are provided. In each presentation mode, the background display as the background of the variable display screen of the decorative symbol is displayed by different background presentations, so that the player can grasp what kind of gaming state he / she is currently staying in.

[0105] The presentation control board 30 (presentation control CPU 30a) has a functional unit (presentation state transition control means) for controlling the transition between a plurality of types of presentation modes. The presentation control board 30 (presentation control CPU 30a) is based on a specific presentation control command sent from the main control board 20 (main control CPU 20a), specifically, a presentation control command including the gaming state information managed on the main control board 20 side, and grasps the current gaming state in a manner that maintains consistency with the gaming state managed on the main control board 20 side, and is configured to be able to control the transition between a plurality of types of presentation modes. Examples of the above specific presentation control commands include a variable pattern designation command, a decorative symbol designation command, a gaming state designation command sent when a change occurs in the gaming state, and the like.

[0106] (Preview Presentation) Next, the pre-announcement performance will be described. The performance control board 30 is configured to be able to control the appearance of various "pre-announcement performances" related to the current performance mode and the jackpot lottery result based on the content of the performance control command from the main control board 20, specifically, at least the variation pattern information included in the variation pattern designation command. Such a pre-announcement performance serves as a "stimulating performance" that suggests (pre-announces) the degree of expectation of winning a winning category (hereinafter referred to as "winning expectation degree") and stirs up the player's winning expectation feeling. Representative examples of the pre-announcement performance include a "reach performance", a "pseudo-consecutive performance", and further a "foresight pre-announcement performance", etc. The performance control board 30 functions as pre-announcement performance control means capable of controlling the execution (appearance) of these performances.

[0107] The "reach performance" refers to a performance mode accompanied by a reach state (a variation display mode accompanied by a reach state: a reach variation pattern), specifically, a performance mode that derives and displays the final game result via the reach state. The reach performance includes a plurality of types of reach performances associated with the winning expectation degree. For example, there are those in which the winning expectation degree relatively increases compared to the case where a normal reach performance appears. Such a reach performance is called a "super reach performance". Many of these "super reaches" have a relatively longer performance time (variation time) than the normal reach in order to stir up the winning expectation feeling. Also, the normal reach and the super reach include a plurality of types of reach performances. In this example, the super reach includes a plurality of types of reach performances such as super reach 1, 2, 3, and 4, and the winning expectation degrees of these super reaches 1 to 4 have a relationship of "super reach 1 < super reach 2 < super reach 3 < super reach 4".

[0108] "Pseudo - continuous performance" refers to a performance mode accompanied by a pseudo - continuous variation display state (pseudo - continuous variation) of a decorative pattern. "Pseudo - continuous variation" refers to a variation display mode in which, during a decorative pattern variation display game, part or all of the decorative pattern is temporarily stopped once, and the display operation of re - varying the decorative pattern is executed one or more times from the temporarily stopped state. In this regard, it is different from the "preview notice performance (continuous notice performance)" described later, which is developed across multiple symbol variation display games. Such "pseudo - continuous" basically has its occurrence rate (appearance rate) determined so that the winning expectation increases as the number of pseudo - variations increases. For example, according to the number of pseudo - variations, an effect for stimulating the expectation of a super reach or the like is likely to be selected for the performance.

[0109] "Preview notice performance" (hereinafter sometimes abbreviated as "preview notice" or "preview performance") means a performance that notifies the possibility of being controlled to an advantageous state before the variation display of the symbol to be judged is performed based on the result of the preview judgment. Note that the "advantageous state" means a state advantageous to the player. Specifically, the preview performance in this example mainly uses the hold display mode and the background performance of the symbol variation display game executed previously for the hold balls in reserve (undigested hold balls) that have not yet been used for the execution of the symbol variation display game (the variation display operation of the special symbol), and is performed in a performance mode that can notify the winning expectation in advance before the hold balls in reserve are used for the symbol variation display game. In the symbol variation display game, in addition to the above "reach performance", various performances such as the so - called "SU (step - up) notice performance", "timer notice performance", "revival performance", "premium notice performance", etc. occur to enliven the game content.

[0110] Here, referring to FIG. 4, the "hold change notice performance" as an example of the above preview notice performance will be described. In the case of the gaming machine 1 of this embodiment, in the upper display area within the screen of the main liquid crystal display device 36M, there is provided a display area (a display area for presenting a variable display effect and a preview effect of a decorative symbol) that presents a decorative symbol variable display game. Also, in the lower display area within the screen, there are provided a hold display area 76 (hold display parts a1 to d1) for displaying the number of active hold balls on the special symbol 1 side and a hold display area 77 (hold display parts a2 to d2) for displaying the number of active hold balls on the special symbol 2 side. Regarding the presence or absence of active hold balls, that fact is notified by a predetermined hold display mode. In FIG. 5, an example is shown in which information regarding the current number of active hold balls is notified in a lit state (there is an active hold ball: the "○ (white circle mark)" shown in the figure) or an unlit state (there is no active hold ball: the dashed circle mark shown in the figure).

[0111] The display (hold display) regarding the presence or absence of active hold balls is sequentially displayed in the order of their occurrence (winning order). In each hold display area 76, 77, the leftmost active hold ball is displayed as the active hold ball that occurred first (i.e., the oldest) on the time axis among all the active hold balls within the hold display. Also, on the left side of the hold display areas 76, 77, there is provided a display area 78 during variation for indicating the active hold balls currently being used in the special symbol variable display game. In the case of this embodiment, the display area 78 during variation is configured such that an image in the form of an icon of the in-game hold K currently being used in the game appears on the icon of the receiving seat J. That is, when the variable display of the special symbol 1 or the special symbol 2 is started, the icon (icon image) of the oldest hold a1 or a2 displayed in the hold display areas 76, 77 moves as the icon of the in-game hold K onto the icon of the receiving seat J in the display area 78 during variation, and that state is maintained for a predetermined display time.

[0112] When an active hold ball occurs, a "hold addition command" that designates the prediction determination information related to the jackpot lottery result and the number of active hold balls at the time of prediction determination (including the currently generated active hold ball, the existing number of active hold balls) is transmitted from the main control board 20 to the effect control board 30 (see steps S1309 to S1312 in FIG. 28). In the case of this embodiment, the hold addition command is composed of two bytes, and the hold addition command is composed of upper byte side data that can specify the number of balls on hold during pre-reading determination and lower byte side data that can specify pre-reading determination information.

[0113] Here, as can be understood from the above description, in this embodiment, based on a prize occurring at the start port 34 or the start port 35 and a new ball on hold being generated, as a pre-reading determination for the ball on hold, a jackpot lottery for the symbol variation display game related to the ball on hold is conducted. As will be described later, the main control board 20 temporarily stores information representing the result of the jackpot lottery conducted as such a pre-reading determination in the corresponding storage area of the main control RAM 20c. The information on the jackpot lottery result obtained at the time of pre-reading determination is used to select (lottery) the symbol variation pattern in the symbol variation display game, and can be paraphrased as so-called "information for selecting the variation pattern". Therefore, it can be said that the main control board 20 conducts a pre-reading determination and temporarily stores the "information for selecting the variation pattern" obtained as a result thereof in a predetermined area of the main control RAM 20c.

[0114] When the effect control board 30 receives the above-described hold addition command transmitted by the main control board 20, based on the pre-reading determination information included therein, as part of the display control process related to the above-described hold display, it conducts an effect control process related to the "pre-reading notice effect". Specifically, it conducts a "pre-reading notice lottery" to lottery whether to execute the pre-reading notice effect, and when winning this lottery, it causes the pre-reading notice effect to appear.

[0115] Here, the prediction determination information is, specifically, in the main control board 20, gaming information obtained by predicting the jackpot lottery result (the jackpot lottery result at the start of variation) or the variation pattern at the start of variation when the operation hold ball is used in the symbol variation display game. That is, this information includes at least the information obtained by predicting the winning / losing lottery result at the start of variation (predicted winning / losing information), and in addition, information obtained by predicting the symbol lottery result (predicted symbol information) and information obtained by predicting the variation pattern at the start of variation (predicted variation pattern information) can be included. Regarding what information to include in the hold addition command sent to the effect control board 30, it can be appropriately determined according to the content notified in the prediction notice. In this example, it is assumed that the hold addition command includes predicted winning / losing information, predicted symbol information, and predicted variation pattern information.

[0116] Note that the "predicted variation pattern" obtained by the prediction determination at the time of the generation of the operation hold ball does not necessarily have to be the "variation pattern at the start of variation" itself obtained when the operation hold ball is actually used in the variation display operation. For example, taking the case where the variation pattern at the start of variation is a variation pattern designating "Super Reach 1" as a representative example, in this case, it can be specified that the content specified by the predicted variation pattern is not the type of reach effect itself of "Super Reach 1", but the essence thereof, "Super Reach type".

[0117] In the case of this embodiment, when winning the prediction notice lottery, among the hold icons of the hold display units a1~d1, a2~d2, the hold icon targeted for the prediction notice can change, for example, from the white color of the normal hold display (normal hold display mode) to the hold display (special hold display mode) in blue, green, red, danger pattern (or special colors and patterns such as rainbow color), and a prediction notice effect of the "hold display change system" (also referred to as "hold change notice") is performed. FIG. 5 shows an example in which the operation hold balls in the hatched hold display section b1 have changed to special hold displays. Here, the display of the hold icons in blue, green, red, and the danger pattern indicates, in this order, a high probability of winning, and in particular, the display of the hold icon with the danger pattern is a premium hold icon that indicates an extremely high probability of a jackpot win.

[0118] (Presentation means) Various presentations in the gaming machine 1 are manifested by presentation means disposed in the gaming machine 1. This presentation means may be any stimulus transmission means that can exert a presentation effect by appealing to human perception such as vision, hearing, and touch, and may be a light generation means such as a decorative lamp 45 or an LED device (light display device 45a: light presentation means), an acoustic generation device such as a speaker 46 (acoustic generation device 46a: sound presentation means), a presentation display device such as a main liquid crystal display device 36M or a sub liquid crystal display device 36S (display means), a pressurizing device that transmits a contact pressure to the operator's body, a wind pressure device that applies wind pressure to the player's body, a movable object accessory that exerts a visual presentation effect by its operation, etc., which are representative examples thereof. Here, the presentation display device is a display device that appeals to vision like an image display device, but is different from the image display device in that it includes those that do not depend on images (for example, a 7-segment display). When referring to an image display device, it mainly refers to a type that presents a presentation by image display, and those that present a presentation by means other than an image like a 7-segment display are included in the concept of the above presentation display device.

[0119] <4. Opening / closing structure and arrangement of substrates> The configuration of FIG. 3 described above is actually realized via a plurality of substrates. Below, some of the substrates mounted on the gaming machine 1 will be excerpted and their arrangements will be described. Also, the opening / closing structure of the gaming machine 1 will be described for the mounting positions of the substrates.

[0120] FIG. 5 shows the state where the door 6 is open. When the door 6 is opened, the inner frame 2 and the game board 3 mounted on the inner frame 2 are directly exposed. Note that the substrate disposed on the door 6 and the substrate disposed on the inner frame 2 are connected by wiring with a harness as a transmission line H8.

[0121] In addition, the gaming machine 1 is configured such that the inner frame 2 can be opened with respect to the outer frame 4. FIG. 6 shows a state in which the inner frame 2 is opened. When the inner frame 2 is opened, the game board 3 attached to the inner frame 2 is also in a state of being released from the outer frame 4. FIG. 6 shows a state in which the back cover 18 attached to the position on the back side of the game board 3 is visible. Although the game board 3 is not shown in FIG. 6, when the back cover 18 is removed (opened), the back side of the game board 3 is exposed. Actually, since the back cover 18 is transparent or translucent, the back side of the game board 3 can be visually recognized in the state of FIG. 6. Note that the game board 3 can be further removed from the inner frame 2.

[0122] Thus, the gaming machine 1 is roughly composed of an outer frame 4, an inner frame 2 attached to the outer frame 4, a game board 3 attached to the inner frame 2, and a door 6 located on the front side of the game board 3 and the inner frame 2. Various substrates are attached to any of the game board 3, the inner frame 2, and the door 6.

[0123] FIG. 7 shows the positions of some of the substrates attached to the game board 3. Note that FIG. 7 shows a state in which the game board 3 is viewed from the back side and shows the substrates mounted on the back side of the game area 3a. Therefore, the right side of the figure is the left side when the game board 3 is viewed from the front side. In the figure, for the sake of a position reference, the outline of the frame of the game board 3 is shown by a dashed line.

[0124] As shown in the figure, on the back side of the game board 3, an effect control board 30 is disposed slightly above the center, and a main control board 20 is disposed below it. Also, a liquid crystal control board 901 is disposed so as to overlap the effect control board 30, and a ROM board 902 and a liquid crystal interface board 903 are disposed in the vicinity thereof.

[0125] An LED connection board 700 is disposed on the left side of the back surface of the game board 3, and a power module board 904 is disposed in the vicinity of the upper part thereof. Also, an upper connection board 905 is arranged above the game board 3.

[0126] Near the main control board 20, a relay board 760, a decoration board 740, a backside left relay board 720, a game board connection board 906, a backside lower relay board 800, and a frame LED relay board 840 are arranged.

[0127] Also, as boards attached to a movable accessory (not shown) attached to the game board, there are LED boards 780, 790 and a decoration board 820.

[0128] FIG. 8 shows the positions of some of the boards attached to the door 6 as seen from the front side of the gaming machine 1. As a configuration within the gaming machine 1, for the purpose of indicating the position reference, the door 6, the effect button 13, the firing operation handle 15, and the upper speaker 46 are shown by a one-dot chain line.

[0129] A relay board 550 is provided above the door 6. Also, a side unit upper LED board 630 is provided above the door 6 as well. A side unit upper right LED board 600 is provided at the upper right of the door 6, and a side unit lower right LED board 620 is provided below it. Note that these side unit upper right LED board 600, side unit lower right LED board 620, and side unit upper LED board 630 are attached within the side unit 10 (see FIG. 1), and each board assumes the position state shown in FIG. 8 when the side unit 10 is attached to the door 6.

[0130] A frame left LED board 907 is arranged at the upper left of the door 6, and a frame lower left LED board 908 is arranged below it. Also, a front frame LED connection board 500 is arranged below the door 6. Also, a button LED connection board 640 is arranged at the lower right, and a button LED board 660 is arranged inside the effect button 13.

[0131] Next, the position of the substrate attached to the inner frame 2 will be described. FIG. 9 is a view of the gaming machine 1 seen from the back. Most of the back side of the gaming machine 1 is protected by a back cover 18 that is transparent or translucent. Below this back side, a power supply board 300 and a payout control board 29 are arranged one behind the other. Also, an inner frame LED relay board 400 is attached to the lower right side as seen from the back side.

[0132] FIG. 10 shows the arrangement positions of various devices arranged on the door 6 and the game board 3. For reference of the positions of the respective devices, the outlines of the game board 3 and the door 6 are shown by dashed-dotted lines.

[0133] In FIG. 10, as the devices provided in the side unit 10 of the door 6, a side unit device 101, a side unit lower right movable object position detection switch 102, a side unit lower right movable object motor 103, a side unit upper right movable object motor 104, a side unit upper right movable object solenoid 105, a blower 106, and photocouplers PC1F, PC2F, and PC3F are arranged at the illustrated positions respectively. The photocouplers PC1F, PC2F, and PC3F are attached to the side unit lower right LED board 620.

[0134] Also, in FIG. 10, as the devices attached to the game board 3, a lower back movable object upper position detection switch 120, a lower back movable object right position detection switch 121, a sorting position detection switch 122, a lower front movable object position detection switch 123, a lower front movable object motor 124, a lower back movable object left position detection switch 125, a lower back movable object left motor 126, a lower back movable object lower right position detection switch 127, a lower back movable object lower left position detection switch 128, an upper movable object left motor 129, an upper movable object left position detection switch 130, a left movable object motor 131, an upper movable object position detection switch 132, an upper movable object right motor 133, a left movable object position detection switch 134, and a lower back movable object right motor 135 are arranged at the illustrated positions respectively.

[0135] Note that the substrates shown in FIGS. 7, 8, and 9 above are only a part of the substrates provided in the gaming machine 1. In particular, the main substrates targeted in the following description are illustrated. Also, the device shown in FIG. 10 is only a part of the devices provided in the gaming machine 1.

[0136] <5. Connection Configuration of Substrates> [5.1 Connection States of Each Substrate] The connection configuration of each substrate arranged as described above will be described, and the supply path of the power supply voltage will be mentioned.

[0137] FIG. 11 shows an example of the substrates respectively arranged on the game board 3, the inner frame 2, and the door 6. In this case, as the substrates mounted on the game board 3, the main control board 20, the effect control board 30, the frame LED relay board 840, the LED connection board 700, the backside left relay board 720, the decorative board 740, the relay board 760, the LED board 780, the LED board 790, the backside lower relay board 800, and the decorative board 820 are shown. As the substrates mounted on the inner frame 2, the power supply board 300, the payout control board 29, and the inner frame LED relay board 400 are shown. As the substrates mounted on the door 6, the front frame LED connection board 500, the relay board 550, the side unit upper right LED board 600, the side unit lower right LED board 620, the side unit upper LED board 630, the button LED connection board 640, and the button LED board 660 are shown.

[0138] These substrates are a part of the substrates mounted on the gaming machine 1, and there are various other substrates in addition to those shown mounted on the game board 3, the inner frame 2, and the door 6. This FIG. 11 shows an extracted connection system of the substrates for use in the description of the technology as an embodiment of the present invention, and does not show all the substrates.

[0139] The power supply board 300 is a board that serves as the source for supplying the DC voltage that becomes the operating power to each part based on the AC input power supply. The main control board 20, the effect control board 30, and the payout control board 29 are as described with reference to FIG. 3.

[0140] The front frame LED connection board 500 is a board for supplying an operation control signal and a power supply voltage to the LEDs provided on the door 6 and the effect means such as the motor, solenoid, and blower of the movable body.

[0141] The upper right side unit LED board 600, the lower right side unit LED board 620, and the upper side unit LED board 630 of the side unit are boards arranged inside the side unit 10, and constitute a drive control system for the modes of the LEDs and the movable body fixtures. These boards also constitute a detection system for transmitting the detection signals of the position sensor, touch sensor, and other various sensors of the motor to the effect control board 30. As described above, the side unit 10 is attached to the door 6 as one of the decoration units, and the side unit 10 is detachable and replaceable with respect to the door 6. The upper right side unit LED board 600, the lower right side unit LED board 620, and the upper side unit LED board 630 of the side unit will be detached and attached together with the side unit 10. When the side unit 10 is attached and the transmission line H10 between the relay board 550 and the upper right side unit LED board 600 is connected, the electrical configuration becomes as shown in FIG. 11.

[0142] The button LED board 660 constitutes the LEDs inside the effect button 13 and its light emission drive system, and also constitutes a circuit for transferring the detection signals of various detection sensors. The button LED connection board 640 relays the control signal and power supply voltage to the button LED board 660, and also transfers the detection signals of various sensors.

[0143] The inner frame LED relay board 400 relays between the frame LED relay board 840 connected to the effect control board 30 and the front frame LED connection board 500, performs necessary signal processing, and also generates and supplies a power supply voltage. The frame LED relay board 840 relays the signal path between the inner frame LED relay board 400 and the effect control board 30.

[0144] The LED substrates 780 and 790 are mounted with LEDs on the game board 3 and drive their light emission. The relay substrate 760 relays the light emission drive signals of the LEDs. These LED substrates 780 and 790 and the relay substrate 760 are attached to the movable object device. The decorative substrate 740 relays and drives other LED substrates. The bottom left relay substrate 720 performs relaying. The decorative substrate 820 is mounted with LEDs. The bottom back relay substrate 800 performs relaying. The LED connection substrate 700 performs various necessary signal processes for driving the light emission of the effect means such as LEDs and motors based on the control signals from the effect control substrate 30.

[0145] Between these respective substrates, they are electrically connected by transmission lines H made of harnesses and cables. The "transmission line H" is a general term for the illustrated transmission lines H1, H2, ··· H31. In each transmission line H, the individual wiring paths for transmitting signals, power supply voltages, etc. are also simply referred to as "lines". The transmission line H refers to a set of one or more lines. The transmission line H includes various forms such as flexible harnesses, flexible substrates, and wire harnesses. Also, the transmission line H may be one in which a plurality of lines are integrated, or may be one in which individual lines are bundled with binders, tapes, etc. Furthermore, when connectors are directly connected to each other, the terminals of each connector become the transmission line H. That is, even when there is no wire material such as a harness, it is included in the "transmission line H". That is, the transmission line H does not refer to a specific type or shape, but broadly refers to what forms an electrical wiring between substrates, etc.

[0146] The power supply substrate 300 and the payout control substrate 29 are connected by the transmission line H1. Also, the power supply substrate 300 and the inner frame LED relay substrate 400 are connected by the transmission line H3. These transmission lines H1 and H3 are formed by harnesses, etc. disposed within the inner frame 2.

[0147] The power supply board 300 and the effect control board 30 are connected by a transmission line H2. The payout control board 29 and the main control board 20 are connected by a transmission line H4. The inner frame LED relay board 400 and the frame LED relay board 840 are connected by a transmission line H7. These transmission lines H2, H4, and H7 are formed by a harness or the like that connects across between the inner frame 2 and the game board 3.

[0148] The main control board 20 and the effect control board 30 are connected by a transmission line H5. The effect control board 30 and the frame LED relay board 840 are connected by a transmission line H6. The effect control board 30 and the LED connection board 700 are connected by a transmission line H20. The LED connection board 700 and the backside left relay board 720 are connected by a transmission line H21. The backside left relay board 720 and the decoration board 740 are connected by a transmission line H22. The decoration board 740 and the relay board 760 are connected by a transmission line H23. For connection with the relay board 760 attached to the movable accessory, the transmission line H23 may be a flexible cable. The relay board 760 and the LED board 780 are connected by a transmission line H24. The LED board 780 and the LED board 790 are connected by a transmission line H25. The LED connection board 700 and the backside bottom relay board 800 are connected by a transmission line H30. The backside bottom relay board 800 and the decoration board 820 are connected by a transmission line H31. These transmission lines H5, H6, H20, H21, H22, H23, H24, H25, H30, and H31 are formed by a harness disposed within the game board 3.

[0149] The inner frame LED relay board 400 and the front frame LED connection board 500 are connected by a transmission line H8. This transmission line H8 is formed by a harness or the like that connects across between the inner frame 2 and the door 6.

[0150] The front frame LED connection board 500 and the relay board 550 are connected by a transmission line H9. The relay board 550 and the side unit upper right LED board 600 are connected by a transmission line H10. The side unit upper right LED board 600 and the side unit lower right LED board 620 are connected by a transmission line H11. The side unit upper right LED board 600 and the side unit upper LED board 630 are connected by a transmission line H12. The front frame LED connection board 500 and the button LED connection board 640 are connected by a transmission line H15. The button LED connection board 640 and the button LED board 660 are connected by a transmission line H16. These transmission lines H9, H10, H11, H12, H15, and H16 are formed by harnesses or the like arranged inside the door 6.

[0151] The power supply board 300 supplies power voltage to each part through transmission lines H1, H2, and H3. FIG. 12 shows the power input / output of the power supply board 300. The power supply board 300 is equipped with connectors CN1A to CN7A. The transmission line ends of transmission lines H40, H41, and H42 (not shown in FIG. 11) are connected to connectors CN5A, CN6A, and CN7A.

[0152] Hereinafter, when collectively referring to these connectors CN1A to CN7A or other connectors shown in other figures, they are denoted as "connector CN". In this specification, "connector CN" refers to a connector terminal component provided on the board. And the terminal part for connector connection formed at the end of the transmission line H is called the "transmission line end". "Connector CN" is connected to the "transmission line end". Or "connector CN" may be directly connected to another connector CN with a corresponding shape.

[0153] The 3-terminal connector CN5A is supplied with AC 24V power from the power plug 301 of the gaming machine 1 through the transmission line H40 (AC-IN(A), AC-IN(B)). Also, an FG (frame ground) path (FG) is formed through the ground terminal 302, the transmission line H40, and the connector CN5A. The ground terminal 302 is connected, for example, outside the gaming machine body.

[0154] The transmission line H41 is connected to the 2-terminal connector CN6A, and an FG path (FG-1) is formed through the ground terminals 303 and 304. The ground terminals 303 and 304 are connected, for example, to the gaming machine body. The transmission line H42 is connected to the 2-terminal connector CN7A, and an FG path (FG-2) is formed through the ground terminals 305 and 306. The ground terminals 305 and 306 are connected, for example, to the gaming machine body.

[0155] The transmission line H1-1 is connected to the 14-terminal connector CN1A. Also, the transmission line H1-1 is connected to the 3-terminal connector CN4A. These two transmission lines H1-1 and H1-2 as harnesses etc. were shown as the transmission line H1 in Fig. 11 above. A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the payout control board 29 through the transmission line H1-1, and a ground path (GND) is formed. Two systems of 24V DC voltage (DC24VA, DC24VB) are supplied to the payout control board 29 through the transmission line H1-2, and an FG path (FG) is formed.

[0156] A 35V DC voltage (DC35VA), a 12V DC voltage (DC12VA), and a 5V DC voltage (DC5VA) are supplied to the main control board 20 through the payout control board 29, and a ground path (GND) is formed.

[0157] The transmission line H2 is connected to the 20-terminal connector CN2A. A 5V DC voltage (DC5VB), a 12V DC voltage (DC12VB), and a 35V DC voltage (DC35VB) are supplied to the effect control board 30 through the transmission line H2, and a ground path (GND) is formed.

[0158] Based on the power supply through this transmission line H2, a 5V DC voltage (DC5VB), a 12V DC voltage (DC12VB), and a 35V DC voltage (DC35VB) are supplied from the effect control board 30 to the LED connection board 700 and used as the operating power for the LED connection board 700 and each downstream board (such as the back panel left relay board 720 and the back panel lower relay board 800). On the other hand, the frame LED relay board 840 is a board having only relay wiring and does not require a power supply voltage, and no power supply voltage is supplied from the effect control board 30.

[0159] For the sake of explanation, the expressions "upstream" and "downstream" are used. Regarding data and control signals, the main control board 20 is the most upstream, followed by the effect control board 30, and "downstream" is towards the actual effect devices such as LEDs and motors from the effect control board 30. Regarding the power supply voltage, the power supply board 300 is the most upstream, and "downstream" is towards the actual effect devices.

[0160] The transmission line H3 is connected to the 6-terminal connector CN3A. A 12V DC voltage (DC12VB) is supplied to the inner frame LED relay board 400 through the transmission line H3, and a ground path (GND) is formed. That is, the inner frame LED relay board 400 is a board controlled by the effect control board 30, but is configured to directly receive a power supply voltage from the power supply board 300. Each board (such as the front frame LED connection board 500) provided on the door 6 downstream of the inner frame LED relay board 400 receives a power supply voltage from the inner frame LED relay board 400.

[0161] [5.2 Inner Frame LED Relay Board 400] Next, some circuit configurations of the substrate shown in FIG. 11 will be described. First, the inner frame LED relay substrate 400 will be described with reference to FIGS. 13 and 14. FIGS. 13 and 14 separately show the circuit configurations provided on the inner frame LED relay substrate 400.

[0162] Connectors CN1B, CN2B, CN3B shown in FIG. 13 and connector CN4B shown in FIG. 14 are mounted on the inner frame LED relay substrate 400.

[0163] The transmission line end of the transmission line H7 that connects to the frame LED relay substrate 840 is connected to the connector CN1B. Details of the frame LED relay substrate 840 are omitted, but as described above, it is a substrate having only relay wiring. Therefore, the connector CN1B substantially forms the wiring between the production control substrate 30 via the transmission line H7, the frame LED relay substrate 840, and the transmission line H6.

[0164] This connector CN1B has a 28-terminal configuration from the first pin to the 28th pin as numbered "1" to "28". For convenience of explanation, the term "pin" of the connector CN includes not only male terminals of pin shape, but also both male and female terminals, and also includes so-called contact patterns on a plane and corresponding terminals.

[0165] The first pin, the third pin, the fifth pin, the seventh pin, the eighth pin, the seventeenth pin, and the eighteenth pin are ground terminals. The second pin is assigned as the terminal for the clock signal S_IN_CLK, the fourth pin is assigned as the load signal S_IN_LOAD, and the sixth pin is assigned as the terminal for the serial data signal S_IN_DATA.

[0166] Pin 9 is assigned as the clear signal CLR_L, pin 10 is assigned as the clear signal CLR_M, pin 11 is assigned as the clock signal CLK_L, pin 12 is assigned as the clock signal CLK_M, pin 13 is assigned as the data signal DATA_L, pin 14 is assigned as the data signal DATA_M, pin 15 is assigned as the enable signal ENABLE_L, and pin 16 is assigned as the enable signal ENABLE_M. Pins 19 to 28 are assigned as the + terminals and - terminals for the upper right speaker, upper middle speaker, lower right speaker, upper left speaker, upper middle speaker, and lower speaker of the speaker 46, respectively.

[0167] Here, the serial data signal S_IN_DATA is serial data received from the front frame LED connection board 500 and transmitted from the inner frame LED relay board 400 to the effect control board 30. The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied from the effect control board 30 to the inner frame LED relay board 400 and further sent to the front frame LED connection board 500. These are used for the serial data transmission operation from the downstream front frame LED connection board 500.

[0168] The clear signals CLR_L, CLR_M, the clock signals CLK_L, CLK_M, the data signals DATA_L, DATA_M, and the enable signals ENABLE_L, ENABLE_M are signals used for driving and controlling the effect devices supplied from the effect control board 30. For example, the data signals DATA_L, DATA_M are light emission drive signals indicating the gradation of the LED or motor drive signals, etc., and the clear signals CLR_L, CLR_M, etc., the clock signals CLK_L, CLK_M, etc., and the enable signals ENABLE_L, ENABLE_M, etc. are signals for controlling the operations of the LED driver and the motor driver. Note that the ending "_L" of the clock signals CLK_L, CLK_M, etc. mainly indicates signals used for controlling the operation of the LED, and "_M" mainly indicates signals used for controlling the operation of the motor.

[0169] The transmission line end of the transmission line H8 that connects the connector CN2B to the front frame LED connection board 500 is connected. This connector CN2B has a configuration of 30 terminals from the first pin to the 30th pin, as numbered from "1" to "30".

[0170] The first pin and the third pin are terminals for a 5V DC voltage (DC5VB). The four pins from the 27th pin to the 30th pin are terminals for a 12V DC voltage (DC12VB). The fifth pin, the seventh pin, the eighth pin, the seventeenth pin, and the eighteenth pin are ground terminals. Note that the conductor points P1 and P2 on the housing of the connector CN2B are connected to ground. This is for the mounting strength of the connector. The conductor points P1 and P2 are not connected to the ground terminal inside the connector. For all the other connectors CN shown in the figure, the conductor points P1 and P2 on the housing are not connected to the ground terminal inside the connector.

[0171] The second pin is assigned as the terminal for the clock signal S_IN_CLK, the fourth pin is assigned as the terminal for the load signal S_IN_LOAD, and the sixth pin is assigned as the terminal for the serial data signal S_IN_DATA. The ninth pin is assigned as the terminal for the clear signal CLR_L, the tenth pin is assigned as the terminal for the clear signal CLR_M, the eleventh pin is assigned as the terminal for the clock signal CLK_L, the twelfth pin is assigned as the terminal for the clock signal CLK_M, the thirteenth pin is assigned as the terminal for the data signal DATA_L, the fourteenth pin is assigned as the terminal for the data signal DATA_M, the fifteenth pin is assigned as the general-purpose output port, and the sixteenth pin is assigned as the terminal for the enable signal ENABLE_M. The pins from the 19th pin to the 26th pin are assigned as the + terminals and - terminals for the upper right speaker, the upper middle speaker, the lower right speaker, the upper left speaker, and the upper middle speaker of the speaker 46, respectively, as shown in the figure.

[0172] Connector CN3B is a connector for connecting to the lower speaker, which is one of the speakers 46 not shown in Fig. 11. For this connector CN3B, the first pin and the second pin with the numbers "1" and "2" are assigned to the + terminal and the - terminal for the lower speaker, and are connected to the 27th pin and the 28th pin of connector CN1B.

[0173] The connector CN4B in Fig. 14 has the transmission line end of the transmission line H3 connected to the power supply board 300 and will be connected to the connector CN3A of the power supply board 300 shown in Fig. 12. This connector CN4B has a six-terminal configuration from the first pin to the sixth pin as numbered "1" to "6", and is assigned in the same way as the connector CN3A of the power supply board 300. That is, the first pin, the second pin, and the third pin are terminals to which a 12V DC voltage (DC12VA) is supplied from the power supply board 300. The fourth pin, the fifth pin, and the sixth pin are ground terminals.

[0174] In this case, the inner frame LED relay board 400 is configured to input the 12V DC voltage (DC12VA) from the first pin, the second pin, and the third pin to the voltage regulator 401 via the fuse F1B, and obtain a 5V DC voltage (DC5VB) as the output of the voltage regulator 401. Capacitors C3B, C4B, C5B, and C6B are connected in parallel between the input terminal side of the voltage regulator 401 and the ground. Capacitor C7B and resistor R24B are connected in parallel between the output terminal side of the voltage regulator 401 and the ground. That is, a 5V generation unit 410 for generating a 5V DC voltage (DC5VB) from a 12V DC voltage (DC12VA) is formed.

[0175] From the first pin and the third pin of the connector CN2B in Fig. 13, the 5V DC voltage (DC5VB) generated by the inner frame LED relay board 400 in this way will be supplied to the downstream board. The 12V DC voltage (DC12VB) supplied to the downstream substrate via pins 27 to 30 of the connector CN2B is the voltage supplied from the power supply substrate 300 via pins 1, 2, and 3 of the connector CN4B in FIG. 14.

[0176] As shown in FIG. 13, buffer circuits 402 and 403 using ICs are arranged on the inner frame LED relay substrate 400. As the buffer circuits 402 and 403, an IC that functions as an inverter when the CONT terminal of the first pin is at the L level and as a buffer when at the H level is used. In this case, the H level is applied by a 5V DC voltage (DC5VB) to function as a buffer. Also, as the operating power supply, a 5V DC voltage (DC5VB) is applied to the VCC terminal of the 20th pin.

[0177] The buffer circuits 402 and 403 are Schmitt trigger buffers with a CMOS8 circuit, and perform buffering, that is, signal compensation (repair of deteriorated H / L signal waveforms) on the signals input from the second pin (A1 terminal) to the ninth pin (A8 terminal), and output from the 18th pin (Y1 terminal) to the 11th pin (Y8 terminal), respectively. That is, the signal input to the A1 terminal is buffer-processed and output from the Y1 terminal, the signal input to the A2 terminal is buffer-processed and output from the Y2 terminal, ··· the signal input to the A8 terminal is buffer-processed and output from the Y8 terminal. Note that buffer processing is signal compensation processing such as signal amplification and waveform shaping. Since it mainly targets pulse signals as digital data, the meaning of waveform shaping is significant. Hereinafter, these processes are referred to as "buffer processing" or "signal compensation".

[0178] The buffer circuit 402 performs signal compensation on the clock signal S_IN_CLK, load signal S_IN_LOAD, and serial data signal S_IN_DATA. The clock signal S_IN_CLK from the second pin of connector CN1B is input to terminal A3 of buffer circuit 402, output from terminal Y3, and supplied to the second pin of connector CN2B. The load signal S_IN_LOAD from the fourth pin of connector CN1B is input to terminal A1 of buffer circuit 402, output from terminal Y1, and supplied to the fourth pin of connector CN2B. The serial data signal S_IN_DATA input to the sixth pin of connector CN2B from the downstream side is input to terminal A5 of buffer circuit 402, output from terminal Y5, and supplied to the sixth pin of connector CN1B.

[0179] Also, for buffer circuit 402, the third pin (terminal A2), the fifth pin (terminal A4), the seventh pin (terminal A6), the eighth pin (terminal A7), the ninth pin (terminal A8), the tenth pin (GND terminal), and the nineteenth pin (G￣ terminal) are connected to ground. The eleventh pin (terminal Y8), the twelfth pin (terminal Y7), the thirteenth pin (terminal Y6), the fifteenth pin (terminal Y4), and the seventeenth pin (terminal Y2) are open.

[0180] Buffer circuit 403 performs signal compensation for the clear signals CLR_L, CLR_M, the clock signals CLK_L, CLK_M, the data signals DATA_L, DATA_M, the fifteenth pin which is the enable signal ENABLE_L, and the sixteenth pin which is the enable signal ENABLE_M. These signals input from the ninth to sixteenth pins of connector CN1B are respectively input to any one of terminals A1 to A8 of buffer circuit 402, output from terminals Y1 to Y8, and supplied to the ninth to sixteenth pins of connector CN2B. Also, for buffer circuit 403, the tenth pin (GND terminal) and the nineteenth pin (G￣ terminal) are connected to ground.

[0181] As described above, the inner frame LED relay board 400 has the following configuration. · The clock signal S_IN_CLK and load signal S_IN_LOAD supplied from the performance control board 30 (frame LED relay board 840) to the connector CN1B are signal-compensated by the buffer circuit 402 and transmitted downstream by the connector CN2B. · The serial data signal S_IN_DATA supplied from the downstream front frame LED connection board 500 to the connector CN2B is signal-compensated by the buffer circuit 402 and transmitted upstream by the connector CN1B. · The clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M supplied from the performance control board 30 (frame LED relay board 840) to the connector CN1B are signal-compensated by the buffer circuit 403 and transmitted downstream by the connector CN2B.

[0182] · Relay the audio signal to the speaker and transmit it directly to the downstream board or speaker unit. · No power voltage is supplied from the connector CN1B (transmission line H7) connected to the performance control board 30 side (frame LED relay board 840). · Receive a 12V DC voltage (DC12V) from the power supply board 300 via the connector CN4B, and supply it as a 12V DC voltage (DC12VB) downstream via the fuse F1B. · Use the 12V DC voltage (DC12V) to generate a 5V DC voltage (DC5VB) for use in the inner frame LED relay board 400 and downstream, and use it as the operating power supply for the buffer circuits 402 and 403 and supply it downstream.

[0183] Note that in the inner frame LED relay board 400, in addition to the above, as shown in FIGS. 13 and 14, resistors R1B to R26B, resistances by chip resistors RA1B and RA2B, and capacitors C1B to C17B are connected at required locations. For example, for the clock signal S_IN_CLK, load signal S_IN_LOAD, clear signals CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, and enable signals ENABLE_L, ENABLE_M, resistors R25B, R26B, R8B, R9B, R10B, R11B, R12B, R13B, R14B, R15B are inserted as damping resistors on the input side (connector CN1B side). Also, resistors R3B, R2B, chip resistors RA1B, RA2B are inserted as damping resistors on the output side (connector CN2B side). In this case, when the wiring distance between the connector and the damping resistor is LA, and the wiring distance between the damping resistor and the buffer circuits 402, 403 is LB, LA < LB such a relationship holds. That is, the damping resistors are arranged closer to the connector (CN1B or CN2B) than the buffer circuits 402, 403. This enhances the signal noise reduction performance.

[0184] [5.3 Front Frame LED Connection Substrate 500] The front frame LED connection substrate 500 will be described with reference to FIGS. 15, 16, 17, 18, 19, and 20. These figures separately show the circuit configurations provided on the front frame LED connection substrate 500.

[0185] On the front frame LED connection substrate 500, connectors such as connector CN2C, CN5C, CN6C, CN8C in FIG. 15, connector CN1C, CN4C in FIG. 16, connector CN3C in FIG. 17, connector CN7C, CN9C in FIG. 18, and connector CN10C in FIG. 20 are mounted.

[0186] The connector CN2C in FIG. 15 is connected to the transmission line end of the transmission line H8 that connects to the connector CN2B of the inner frame LED relay substrate 400 in FIG. 13. Therefore, this connector CN2C has a 30-terminal configuration from the first pin to the 30th pin as if numbered from "1" to "30", and the terminal assignment is the same as that of the above-described connector CN2B. The conductor points P1 and P2 in the housing of the connector CN2C are also connected to the ground. This is for the mounting strength of the connector, and the conductor points P1 and P2 are not connected to the ground terminal inside the connector. Although not mentioned repeatedly, the conductor points P1 and P2 in the housings of the connectors CN1C, CN3C, CN4C, CN7C, CN8C, CN9C, and CN10C described later are also connected to the ground for mounting strength.

[0187] The connector CN5C is a connector for connection to the right middle speaker, which is one of the speakers 46. The first and second pins numbered "1" and "2" of this connector CN3B are assigned to the + terminal and - terminal for the right middle speaker, and are connected to the 20th and 22nd pins of the connector CN2C.

[0188] The connector CN6C is a connector for connection to the left middle speaker, which is one of the speakers 46. The first and second pins numbered "1" and "2" of this connector CN6B are assigned to the + terminal and - terminal for the left middle speaker, and are connected to the 24th and 26th pins of the connector CN2C.

[0189] The connector CN8C is a connector for connection to the upper right speaker and the upper left speaker, which are two of the speakers 46. The first and second pins numbered "1" and "2" of this connector CN6B are assigned to the + terminal and - terminal for the upper right speaker, and are connected to the 19th and 21st pins of the connector CN2C. Also, the third and fourth pins numbered "3" and "4" are assigned to the + terminal and - terminal for the upper left speaker, and are connected to the 23rd and 25th pins of the connector CN2C.

[0190] The connector CN1C in Fig. 16 is a connector connected to the LED board, which is not shown in Fig. 11. Also, the connector CN4C is connected to an in-handle LED board (not shown).

[0191] The connector CN1C has a 13-terminal configuration from the first pin to the 13th pin, marked with numbers "1" to "13". The first pin and the sixth pin are ground terminals, the second pin is the terminal for the clock signal CLK, the third pin is the terminal for the 5V DC voltage (DC5V), the fourth pin is the terminal for the data signal DATA, the fifth pin is the terminal for the reset signal RESET, and the seventh pin is the terminal for the 12V DC voltage (DC12V).

[0192] The eighth pin to the 13th pin are the input terminals for the R, G, and B LED emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) supplied from an LED driver provided on a downstream LED board (not shown) to which the connector CN1C is connected. This LED emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) is directly supplied from the second pin to the seventh pin of the connector CN4C to another downstream in-handle LED board (not shown).

[0193] That is, on the downstream side of the front frame LED connection board 500, an LED board (not shown) and an in-handle LED board are connected by the connector CN1C and the connector CN4C, and an LED driver is mounted on the LED board. The LED driver operates using the clock signal CLK, 5V DC voltage (DC5V), data signal DATA, reset signal RESET terminal, and 12V DC voltage (DC12V) from the connector CN1C to drive the LEDs on the LED board and also generate the LED emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) for the LEDs on the in-handle LED board. The LED emission drive current (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7) is supplied to the LEDs on the in-handle LED board through the relay of the front frame LED connection board 500.

[0194] Since they serve as the paths for the LED emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7), Zener diodes D8C to D15C are connected as protection circuits to the second to seventh pins of connector CN4C respectively. Also, a 12V DC voltage (DC12VB) is applied to the first pin of connector CN4C, and a power supply voltage is supplied to the LED substrate side within a handle (not shown).

[0195] Such a configuration is used to connect two LED substrates downstream of the front frame LED connection board 500 and to provide an LED driver on only one side. That is, the front frame LED connection board 500 outputs a clock signal CLK, a 5V DC voltage (DC5V), a data signal DATA, a reset signal RESET, and a 12V DC voltage (DC12V) for the operation of the LED driver. Then, the LED emission drive current by the LED driver is returned and relayed to the other LED substrate.

[0196] In this case, for driving the two LED substrates on the downstream side, only one LED driver is required. Particularly when performing emission control with a common LED drive control signal, it is only necessary to transmit the LED drive control signal to only one LED substrate, which can promote simplification of the wiring configuration. That is, it is not necessary to transmit the clock signal CLK, the 5V DC voltage (DC5V), the data signal DATA, the reset signal RESET, and the 12V DC voltage (DC12V) to both LED substrates. Also, by relaying the LED emission drive currents (17-R6, 17-G6, 17-B6, 17-R7, 17-G7, 17B-7), a harness for transmitting these between the two downstream LED substrates becomes unnecessary.

[0197] The connector CN3C in FIG. 17 is connected to the transmission line end of the transmission line H9 that connects to the relay board 550 on the downstream side. This connector CN3C has a 22-terminal configuration from the first pin to the 22nd pin as numbered "1" to "22".

[0198] The five pins of the first pin, the third pin, the eleventh pin, the thirteenth pin, and the eighteenth pin are ground terminals. The second pin is a terminal for a 5V DC voltage (DC5VB). The three pins of the fifth pin, the seventh pin, and the ninth pin are terminals for a 12V DC voltage (DC12VB).

[0199] The fourth pin is assigned as a terminal for the serial data signal S_IN_DATAx, the sixth pin is assigned as a terminal for the load signal S_IN_LOAD, and the eighth pin is assigned as a terminal for the clock signal S_IN_CLK.

[0200] The tenth pin is assigned as an enable signal ENABLE_L, the twelfth pin is assigned as a clear signal CLR_P, the fourteenth pin is assigned as a reset signal RESET_P, the fifteenth pin is assigned as a clock signal CLK_M, the sixteenth pin is assigned as a data signal DATA_P, the seventeenth pin is assigned as a reset signal RESET_M, the nineteenth pin is assigned as a data signal DATA_M, the twentieth pin is assigned as a drive general-purpose signal 1, the twenty-first pin is assigned as an enable signal ENABLE_M, and the twenty-second pin is assigned as a drive general-purpose signal 2.

[0201] The connector CN7C in FIG. 18 is connected to a substrate (not shown) for detecting the cross keys 15a, the enter key 15b, volume buttons (not shown), light quantity buttons (not shown), etc. This connector CN7C has a nine-terminal configuration from the first pin to the ninth pin indicated by "1" to "9". The first pin is a ground terminal, and sense signals SENS0 to SENS7, which are detection signals for operations such as the cross keys 15a, are input to each of the pins from the second pin to the ninth pin. Regarding the sense signals SENS0 to SENS7 of the second pin to the ninth pin, they are pulled up by a 5V DC voltage (DC5VB) via chip resistors RA3C and RA4C.

[0202] The connector CN9C is connected to a touch sensor (not shown) provided on the emission operation handle 15. This connector CN9C has a two-terminal configuration indicated by "1" and "2". The first pin receives the sense signal SENS14 from the touch sensor, and the second pin is a ground terminal. Regarding the sense signal SENS14, it is pulled up by a 5V DC voltage (DC5VB) via the resistor R26C.

[0203] The connector CN10C in FIG. 20 is connected to the transmission line end of the transmission line H15 that connects to the button LED connection board 640 in FIG. 11. This connector CN10C has a 20-terminal configuration from the first pin numbered "1" to the 20th pin.

[0204] Five pins, namely the second pin, the fourth pin, the twelfth pin, the thirteenth pin, and the nineteenth pin, are grounded terminals. The eighth pin is a terminal for a 5V DC voltage (DC5VB). The sixth pin is a terminal for a 12V DC voltage (DC12VB). The fifth pin and the seventh pin are terminals for a 12V motor drive voltage (MOT12V).

[0205] The first pin is assigned as a terminal for the motor drive signal MOTφ / 2, the third pin is assigned as a terminal for the motor drive signal MOTφ / 1, the ninth pin is assigned as a terminal for the motor drive signal MOTφ2, the tenth pin is assigned as a terminal for the motor drive signal DCMOT3, and the eleventh pin is assigned as a terminal for the motor drive signal MOTφ1.

[0206] The fourteenth pin is assigned as a terminal for the clear signal CLR_L, the sixteenth pin is assigned as a terminal for the clock signal CLK_L, and the eighteenth pin is assigned as a terminal for the data signal DATA_L. The fifteenth pin, the seventeenth pin, and the twentieth pin are terminals to which the sense signals SENS8, SENS9, and SENS11, which are detection signals from the downstream side, are input. Regarding the sense signals SENS8, SENS9, and SENS11, they are pulled up by a 5V DC voltage (DC5VB) via the chip resistor RA5C.

[0207] The power supply voltage on this front frame LED connection board 500 will be described. On the front frame LED connection board 500, as ICs, there are buffer circuits 501, 502, 503, 507, 508 which are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 described in FIG. 13 before, and buffer circuits 504, 512, 513 which are triple buffer gates are mounted. As the power supply voltage for these, a 5V DC voltage (DC5VB) supplied from the first pin of the connector CN2C is used.

[0208] Also, as ICs, parallel / serial (hereinafter referred to as "P / S") conversion circuits 505, 506 in FIG. 18 are mounted, and the power supply voltage for these is also a 5V DC voltage (DC5VB) supplied from the first pin of the connector CN2C.

[0209] Also, as an IC, an S / P conversion circuit 509 (LED driver) in FIG. 19 is mounted, and as the power supply voltage for this, a 12V DC voltage (DC12VB) supplied from the 27th to 30th pins of the connector CN2C is used.

[0210] Also, as ICs, motor drivers 510, 511 in FIG. 19 are mounted, and for these, a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) are used as the power supply voltage. The 12V motor drive voltage (MOT12V) is used as the power supply voltage for motor drive, and the 12V DC voltage (DC12VS) is used as the power supply voltage for motor drivers such as the motor drivers 510, 511.

[0211] The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB). As shown in FIG. 15, for pins 27 to 30 of connector CN2C, a capacitor C11 is inserted between them and ground, and the anode side of the Schottky barrier diode D18C is connected to the positive electrode side of capacitor C11. Between the cathode side of the Schottky barrier diode D18C and ground, a resistor R27C, capacitors C12C, C13C, and chip varistor 515 are connected in parallel. With this configuration, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage with overvoltage protection. That is, a power supply separation / protection circuit 520 for separating the 12V motor drive voltage (MOT12V) from the 12V DC voltage (DC12VA) is formed.

[0212] Regarding the 12V DC voltage (DC12VS), it is separated from the 12V DC voltage (DC12VB) using a power supply separation / protection circuit 521 composed of diode D19C, resistor R34C, and capacitor C21C shown in FIG. 19.

[0213] The flow of various signals in the front frame LED connection board 500 will be described below. From the inner frame LED relay board 400, a clear signal CLR_L, CLR_M, clock signals CLK_L, CLK_M, data signals DATA_L, DATA_M, a signal of the general-purpose output port (general-purpose signal HANYOU), and an enable signal ENABLE_M are transmitted to the connector CN2C in FIG. 15. These respective signals are input to terminals A1 to A8 of the buffer circuit 501 and signal-compensated. Note that the clear signals CLR_L, CLR_M supplied from the inner frame LED relay board 400 are shown as reset signals RESET_L, RESET_M within the front frame LED connection board 500.

[0214] The clock signal CLK_L, data signal DATA_L, and reset signal RESET_L are supplied to the buffer circuit 504 in FIG. 16 via the chip resistor RA1C after being signal-compensated by the buffer circuit 501. After being buffer-processed, they are output from the connector CN1C to an LED substrate (not shown).

[0215] Also, these clock signal CLK_L, general-purpose signal HANYOU, data signal DATA_L, and reset signal RESET_L, which have been signal-compensated by the buffer circuit 501 in FIG. 15, are supplied to the A5 terminal, A6 terminal, A7 terminal, and A8 terminal of the buffer circuit 502 in FIG. 17. Then, the outputs of the Y5 terminal, Y6 terminal, Y7 terminal, and Y8 terminal of the buffer circuit 502 after signal compensation are output from the connector CN3C to the relay board 550 as the clock signal CLK_P, enable signal ENABLE_L (from the general-purpose signal HANYOU), data signal DATA_P, and reset signal RESET_P.

[0216] That is, on the downstream side after the relay board 550, signals for LED control and the like output from the upstream inner-frame LED relay board 400 are signal-compensated by the buffer circuits 501 and 502 and then transmitted.

[0217] Note that the clock signal CLK_P is output from the connector CN3C via a constant-voltage / protection circuit composed of a Zener diode D5C and a resistor R19C, the enable signal ENABLE_L is output via a constant-voltage / protection circuit composed of a Zener diode D4C and a resistor R15C, the data signal DATA_P is output via a constant-voltage / protection circuit composed of a Zener diode D6C and a resistor R20C, and the reset signal RESET_P is output via a constant-voltage / protection circuit composed of a Zener diode D7C and a resistor R21C.

[0218] Also, the clock signal CLK_L, data signal DATA_L, and reset signal RESET_L compensated for signals by the buffer circuit 501 in FIG. 15 are supplied to the buffer circuit 512 in FIG. 20. Then, after being amplified, they are output as the clock signal CLK_L, data signal DATA_L, and clear signal CLR_L (reset signal RESET_L) from the connector CN10C to the button LED connection board 640.

[0219] Therefore, downstream of the button LED connection board 640, signals for LED control and the like output from the upstream inner frame LED relay board 400 are compensated for signals by the buffer circuits 501 and 512 and then transmitted.

[0220] Also, the clock signal CLK_L, data signal DATA_L, and general-purpose signal HANYOU_L compensated for signals by the buffer circuit 501 in FIG. 15 are supplied to the serial / parallel (S / P) conversion circuit 509 in FIG. 19. This S / P conversion circuit 509 is configured using a chip as an LED driver. The LED driver is a device that outputs a light emission drive current according to the clock signal CLK_L and data signal DATA_L. In this case, it is mainly used for serial / parallel conversion for motor drive. That is, the LED driver chip is used as part of the motor drive means.

[0221] The S / P conversion circuit 509 composed of the LED driver chip has output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 for the light emission drive current and can output 24 channels of drive current. In this case, however, seven terminals, namely LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3, are used. As shown in the figure, the other output terminals are connected to the ground. Then, the outputs of output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 (currents 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, 23-R3) are buffer-processed by buffer circuit 508 and then supplied to input terminals IN1, IN2, IN3, IN4 of motor driver 510 and input terminals IN1, IN3, IN4 of motor driver 511.

[0222] Note that output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, and LEDR3 are connected to a 5V DC voltage (DC5VB) via chip resistors RA6C and RA7C to allow currents 23-R1, 23-G1, 23-B1, 23-R2, 23-G2, 23-B2, 23-R3 to flow.

[0223] Based on the signals at input terminals IN1, IN2, IN3, IN4, motor driver 510 outputs motor drive signals MOT1-1, MOT1- / 1, MOT1-2, MOT1- / 2 from output terminals OUT1, OUT2, OUT3, OUT4. Based on the signals at input terminals IN1, IN3, IN4, motor driver 511 outputs motor drive signals MOT3-1, MOT3-3, MOT3-4 from output terminals OUT1, OUT3, OUT4.

[0224] Motor drive signals MOT1-1, MOT1- / 1, MOT1-2, MOT1- / 2, MOT3-1 are supplied to connector CN10 in Figure 20 and output as motor drive signals MOTφ1, MOTφ / 1, MOTφ2, MOTφ / 2, DCMOT3 to button LED connection board 640 as described above. Motor drive signals MOT3-3, MOT3-4 are supplied to connector CN3C in Figure 17 and output as drive general-purpose signals 1 and drive general-purpose signal 2 to relay board 550.

[0225] The above constitutes a circuit system in the front frame LED connection board 500 that generates a motor drive signal for the downstream button LED connection board 640 and subsequent components using the clock signal CLK_L-, data signal DATA_L-, and general-purpose signal HANYOU_L-.

[0226] The clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and clear signal CLR_M (reset signal RESET_M) input from the connector CN2C in FIG. 15 are signal-compensated by the buffer circuit 501 and then supplied to the A1 terminal, A3 terminal, A5 terminal, and A7 terminal of the buffer circuit 503 in FIG. 17 via the chip resistor RA2C. The outputs of the Y1 terminal, Y3 terminal, Y5 terminal, and Y7 terminal of the signal-compensated buffer circuit 503 are output as the clock signal CLK_M, data signal DATA_M, enable signal ENABLE_M, and reset signal RESET_M to the relay board 550 from the connector CN3C.

[0227] Therefore, signals for motor control from the upstream inner frame LED relay board 400 are signal-compensated by the buffer circuits 501 and 503 and transmitted to the downstream side after the relay board 550.

[0228] Note that the clock signal CLK_M is output from the connector CN3C via a constant voltage / protection circuit formed by the Zener diode D12C and resistor R22C, the enable signal ENABLE_M is output via a constant voltage / protection circuit formed by the Zener diode D16C and resistor R24C, the data signal DATA_M is output via a constant voltage / protection circuit formed by the Zener diode D14C and resistor R23C, and the reset signal RESET_M is output via a constant voltage / protection circuit formed by the Zener diode D17C and resistor R25C.

[0229] The clock signal S_IN_CLK and load signal S_IN_LOAD input from the connector CN2C in FIG. 15 are supplied to the A3 terminal and A2 terminal of the buffer circuit 502 in FIG. 17. Then, the outputs of the Y3 terminal and Y2 terminal of the buffer circuit 502 with signal compensation are output as the clock signal S_IN_CLK and load signal S_IN_LOAD from the connector CN3C to the relay board 550. Therefore, on the downstream side after the relay board 550, signals for serial data transmission are compensated by the buffer circuits 501 and 502 and then transmitted.

[0230] Note that the clock signal S_IN_CLK is output from the connector CN3C through a constant voltage / protection circuit composed of a Zener diode D3C and a resistor R11C, and the load signal S_IN_LOAD is output from the connector CN3C through a constant voltage / protection circuit composed of a Zener diode D2C and a resistor R9C.

[0231] The serial data signal S_IN_DATAx input from the relay board 550 on the downstream side to the connector CN3C in FIG. 17 is supplied to the A1 terminal of the buffer circuit 502. Then, the output of the Y1 terminal of the buffer circuit 502 with signal compensation is input to the SI terminal (serial input terminal) of the P / S conversion circuit 505 in FIG. 18.

[0232] The P / S conversion circuit 505 and the P / S conversion circuit 506 in the same figure are CMOS 8-bit shift registers, which have 8-bit parallel input / output, serial input, and serial output, and perform parallel-to-serial conversion of data. When the P / S CONT terminal = L, the 8 terminals of the Q / D1 terminal to Q / D8 terminal are parallel outputs, and the data at the SI terminal is stored in each register at the rising edge of the input waveform of the CK terminal and output to the Q / D1 terminal to Q / D8 terminal. Also, by setting the CLR / LOAD terminal = L, each register is reset asynchronously to the input of the CK terminal. When the P / S CONT terminal = H, the 8 terminals of the Q / D1 terminal to Q / D8 terminal are parallel inputs, and when the CLR / LOAD terminal = L, the input data of the Q / D1 terminal to Q / D8 terminal is stored in each register asynchronously to the input of the CK terminal.

[0233] In this case, the P / S conversion circuits 505 and 506 are set to P / S CONT terminal = H when a 5V DC voltage (DC5VB) is applied to the P / S CONT terminal, and the eight terminals of the Q / D1 to Q / D8 terminals are parallel inputs. Also, the clock signal S_IN_CLK and the load signal S_IN_LOAD input from the connector CN2C in FIG. 15 are buffer-processed by the buffer circuit 513 and input to the P / S conversion circuits 505 and 506. That is, the clock signal S_IN_CLK is input to the CK terminal, and the load signal S_IN_LOAD is input to the CLR / LOAD terminal.

[0234] At the Q / D1 to Q / D8 terminals, which are the parallel input terminals of the P / S conversion circuit 505, the sense signal SENS8 is input to the Q / D1 terminal, the sense signal SENS9 is input to the Q / D2 terminal, the sense signal SENS11 is input to the Q / D4 terminal, and the sense signal SENS14 is input to the Q / D7 terminal. The Q / D3 terminal, Q / D5 terminal, Q / D6 terminal, and Q / D8 terminal are connected to the ground. That is, each input becomes "0" (L level). The sense signals SENS8, SENS9, and SENS11 are detection signals of a switch sensor that detects button operations and a sensor that detects the rotational position and origin position of a movable body inside the button, which are input from the downstream button LED connection board 640 to the connector CN10C in FIG. 20. The sense signal SENS14 is a detection signal of a touch sensor input from the connector CN9C in FIG. 18.

[0235] The P / S conversion circuit 505 combines the serial data signal S_IN_DATAx, the sense signals SENS8, SENS9, SENS11, and SENS14 input as described above, converts them into serial data, and outputs it as the serial data signal SDT1 from the Q8C terminal. This serial data signal SDT1 is input to the SI terminal of the P / S conversion circuit 506.

[0236] At the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 506, the sense signal SENS0 is input to the Q / D1 terminal, the sense signal SENS1 is input to the Q / D2 terminal, the sense signal SENS2 is input to the Q / D3 terminal, the sense signal SENS3 is input to the Q / D4 terminal, the sense signal SENS4 is input to the Q / D5 terminal, the sense signal SENS5 is input to the Q / D6 terminal, the sense signal SENS6 is input to the Q / D7 terminal, and the sense signal SENS7 is input to the Q / D8 terminal. These sense signals SENS0 to SENS7 are detection signals such as the cross key 15a that are input to the connector CN7C in FIG. 18. The sense signals SENS0 to SENS7 from the connector CN7C are signal-compensated by the buffer circuit 507 and then input to the respective terminals of the P / S conversion circuit 506.

[0237] As described above, the P / S conversion circuit 506 combines the serial data signal SDT1 from the P / S conversion circuit 505 input to the SI terminal and the sense signals SENS0 to SENS7, converts them into serial data, and outputs them as a serial data signal SDT2 from the Q8 terminal. This serial data signal SDT2 is input to the buffer circuit 513 via a filter composed of the resistor R35C and the capacitor C27C and is buffer-processed. This output is transmitted upstream from the connector CN2C in FIG. 15 as the serial data signal S_IN_DATA from the front frame LED connection board 500.

[0238] As described above, the front frame LED connection board 500 has the following configuration. FIG. 21 summarizes the flow of the clock signals CLK_L, CLK_M, the clear signals CLR_L, CLR_M (reset signals RESET_L, RESET_M), the data signals DATA_L, DATA_M, the general-purpose signal HANYOU, and the enable signal ENABLE_M supplied from the upstream inner frame LED relay board 400 to the connector CN2C.

[0239] · The clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), data signal DATA_L, and general-purpose signal HANYOU are transmitted downstream as the clock signal CLK_P, reset signal RESET_P, data signal DATA_P, and enable signal ENABLE_L via buffer circuits 501 and 502 by connector CN3C. · The clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), and data signal DATA_L are transmitted downstream as the clock signal CLK, reset signal RESET, and data signal DATA via buffer circuit 504 by connector CN1C. · The clock signal CLK_L, clear signal CLR_L (reset signal RESET_L), and data signal DATA_L are transmitted downstream as the clock signal CLK_L, clear signal CLR_L, and data signal DATA_L via buffer circuit 512 by connector CN10C. · The clock signal CLK_L, data signal DATA_L, and general-purpose signal HANYOU are supplied to the S / P conversion circuit 509 and used to generate the motor drive current.

[0240] · The clock signal CLK_M, clear signal CLR_M (reset signal RESET_M), data signal DATA_M, and enable signal ENABLE_M are transmitted downstream as the clock signal CLK_M, reset signal RESET_M, data signal DATA_M, and enable signal ENABLE_M via buffer circuits 501 and 503 by connector CN3C.

[0241] · The S / P conversion circuit 509, buffer circuit 508, and motor drivers 510 and 511, which are configured as motor drive means, generate motor drive signals MOTφ1, MOTφ / 1, MOTφ2, MOTφ / 2, and DCMOT3 and transmit them downstream from connector CN10C.

[0242] Also, in FIG. 22, the flows of the serial data signal S_IN_DATA, the clock signal S_IN_CLK, the load signal S_IN_LOAD, and the sense signals SENS0 to SENS7, SENS8, SENS9, SENS11, SENS14 are summarized.

[0243] · The clock signal S_IN_CLK and the load signal S_IN_LOAD are transmitted downstream from the connector CN3C via the buffer circuit 502. · The clock signal S_IN_CLK and the load signal S_IN_LOAD are supplied to the P / S conversion circuits 505 and 506 via the buffer circuit 513 and are used for parallel / serial conversion processing.

[0244] · The serial data signal S_IN_DATAx input from the downstream side to the connector CN3C is input to the P / S conversion circuit 505 via the buffer circuit 502, and is serially dataized together with the sense signals SENS8, SENS9, SENS11, SENS14 in the P / S conversion circuit 505, and is input to the P / S conversion circuit 506 as the serial data signal SDT1. Also, the sense signals SENS0 to SENS7 input from the downstream side to the connector CN7C are input to the P / S conversion circuit 506 via the buffer circuit 507. In the P / S conversion circuit 506, the serial data signal SDT1 from the P / S conversion circuit 505 and the sense signals SENS0 to SENS7 are combined and serially dataized, and the serial data signal SDT2 is output. This serial data signal SDT2 is transmitted upstream from the connector CN2C via the buffer circuit 513 as the serial data signal S_IN_DATA from the front frame LED connection board 500.

[0245] The front frame LED connection board 500 further has the following configuration. · Relay the audio signal to the speaker and transmit it to the speaker unit. · Receive the 12V DC voltage (DC12VB) and 5V DC voltage (DC5VB) by the connector CN2C and use them as the operating power supply. ·Separate the 12V motor drive voltage (MOT12V) and the 12V DC voltage (DC12VS) used for generating the motor drive signal from the 12V DC voltage (DC12VB). By dividing the power supply according to the application for the 12V DC voltage (DC12VB) for the LED and the LED driver, the 12V motor drive voltage (MOT12V) for motor drive, and the 12V DC voltage (DC12VS) for the motor driver, the adverse effects caused by noise are prevented. ·Supply the 12V DC voltage (DC12VB) and the 5V DC voltage (DC5VB) as the operating power supply voltage to the downstream side.

[0246] In the front frame LED connection board 500, including those mentioned above, as shown in FIGS. 15 to 20, resistors such as resistors R1C, R2C ···, chip resistors RA1C, RA2C ···, capacitors C1C, C2C ···, diodes (including Zener diodes and Schottky barrier diodes) D1C, D2C ··· and other electronic elements are connected to the required locations. As the damping resistors for signal lines such as the clear signals CLR_L, CLR_M, the clock signals CLK_L, CLK_M, the data signals DATA_L, DATA_M, the signals of the general-purpose output port (general-purpose signal HANYOU), and the enable signal ENABLE_M, resistors R8C, R10C, R12C, R13C, R14C, R16C, R17C, R18C are inserted on the connector CN2C side in FIG. 15, and further chip resistors RA1C, RA2C are inserted. That is, a configuration is adopted in which the waveform is shaped by inserting damping resistors near the connector CN2C and before the signal branch. Also, as shown in the figure, taps TP1C to TP14C are provided and used for connection to the required locations. Although not shown in the figure, capacitors for reducing power supply noise and the like are appropriately arranged between the power supply lines of DC 5V and DC 12V and the ground.

[0247] [5.4 Relay board 550] The configuration of the relay board 550 is shown in FIG. 23. Connectors CN1D and CN2D are mounted on the relay board 550.

[0248] The connector CN1D has the transmission line end of the transmission line H9 connected thereto, which connects between the connector CN3C of the front frame LED connection board 500 in FIG. 17. Therefore, this connector CN1D has a configuration of 22 terminals from the first pin to the 22nd pin as numbered from "1" to "22", and the terminal assignment is the same as that of the above-described connector CN3C. The conductor points P1 and P2 in the housing of the connector CN1D are also connected to the ground for mounting strength.

[0249] The connector CN2D has the transmission line end of the transmission line H10 connected thereto, which connects between the upper right LED board 600 of the downstream side unit. This connector CN2D has a configuration of 20 terminals from the first pin to the 20th pin as numbered from "1" to "20".

[0250] Four pins, namely the third pin, the ninth pin, the eleventh pin, and the sixteenth pin, are ground terminals. The first pin is a terminal for a 5V DC voltage (DC5VB). Two pins, namely the fifth pin and the seventh pin, are terminals for a 12V DC voltage (DC12VB).

[0251] The second pin is assigned as a terminal for the serial data signal S_IN_DATAx, the fourth pin is assigned as a terminal for the load signal S_IN_LOAD, and the sixth pin is assigned as a terminal for the clock signal S_IN_CLK.

[0252] The eighth pin is assigned as a terminal for the enable signal ENABLE_L, the tenth pin is assigned as a terminal for the clock signal CLK_P, the twelfth pin is assigned as a terminal for the reset signal RESET_P, the thirteenth pin is assigned as a terminal for the clock signal CLK_M, the fourteenth pin is assigned as a terminal for the data signal DATA_P, the fifteenth pin is assigned as a terminal for the reset signal RESET_M, the seventeenth pin is assigned as a terminal for the data signal DATA_M, the eighteenth pin is assigned as a terminal for the drive general-purpose signal 1, the nineteenth pin is assigned as a terminal for the enable signal ENABLE_M, and the twentieth pin is assigned as a terminal for the drive general-purpose signal 2.

[0253] In this relay board 550, the 12V DC voltage (DC12VB) assigned to the three terminals of the 5th pin, 7th pin, and 9th pin of the connector CN1D is aggregated to the two terminals of the 5th pin and 7th pin on the connector CN2D side and transferred downstream. Also, for the connector CN1D, the five terminals of the 1st pin, 3rd pin, 11th pin, 13th pin, and 18th pin are used as ground terminals, while on the connector CN2D side, the four terminals of the 3rd pin, 9th pin, 11th pin, and 16th pin are used. This reduces the number of terminals of the connector CN2D on the downstream side. Also, the connector CN1D and the connector CN2D are of different types. The connector CN2D has a larger rated current per pin, so the number of power terminals and ground terminals of the connector CN2D can be reduced. Also, the connector CN2D is easier to plug and unplug than the connector CN1D, has thicker terminals, and a larger housing.

[0254] [5.5 Side Unit Upper Right LED Board 600] The side unit upper right LED board 600 will be described with reference to FIGS. 24, 25, 26, 27, 28, and 29. These figures separately show the circuit configurations provided on the side unit upper right LED board 600.

[0255] On the side unit upper right LED board 600, connectors such as the connector CN1E in FIG. 24, the connector CN7E in FIG. 25, the connectors CN2E and CN3E in FIG. 26, and the connectors CN4E, CN5E, and CN6E in FIG. 28 are mounted.

[0256] The connector CN1E in FIG. 24 is connected to the transmission line end of the transmission line H10 that connects to the connector CN2D of the relay board 550 in FIG. 23. Therefore, this connector CN1E has a 20-terminal configuration from the 1st pin to the 20th pin as numbered "1" to "20", and the terminal assignment is the same as that of the above-mentioned connector CN2D.

[0257] The connector CN7E in FIG. 25 is connected to the sensor in the side unit device 101 shown in FIG. 10, and the sense signal SENS2X is input to the third pin. This sensor 101S is, for example, a sensor that detects the operation of a player of the side unit device 101. The sense signal SENS2X of the sensor 101S is pulled up by a 5V DC voltage (DC5V) via the resistor R64E. A 12V DC voltage (DC12VB), which is the power supply voltage on the sensor 101S side of the side unit device 101, is applied to the first pin. The second pin is a ground terminal.

[0258] The connector CN2E in FIG. 26 is a 6-terminal connector to which the transmission line end of the transmission line H12 connecting to the downstream side unit upper LED board 630 is connected. For this connector CN2E, the first pin to the sixth pin are assigned as a ground terminal, a terminal for the clock signal CLK, a terminal for the data signal DATA, a terminal for the reset signal RESET, a ground terminal, and a terminal for a 12V DC voltage (DC12VB).

[0259] The connector CN3E has the transmission line end of the transmission line H11 connecting to the downstream side unit lower right LED board 620 connected thereto. This connector CN3E has a 16-terminal configuration from the first pin to the sixteenth pin, as numbered "1" to "16".

[0260] The first pin is a terminal for a 5V DC voltage (DC5VB). The eighth pin and the thirteenth pin are ground terminals. The fifteenth pin is a terminal for a 12V motor drive voltage (MOT12V). A Zener diode D11E is connected between the fifteenth pin and the ground as a protection circuit.

[0261] The second pin is assigned as the terminal for the clock signal CLK, the third pin is for the sense signal SENS1X, the fourth pin is for the data signal DATA, the fifth pin is for the sense signal SENS_A, the sixth pin is for the reset signal RESET, the seventh pin is for the sense signal SENS_B, and the ninth pin is for the sense signal SENS_C. Note that as shown in Fig. 25, the sense signal SENS1X is pulled up by a 5V DC voltage (DC5V) via the resistor R13E. Also, the sense signals SENS_A, SENS_B, and SENS_C are each pulled up by a 5V DC voltage (DC5V) via the resistors R29E, R27E, and R21E, respectively.

[0262] Also, for the connector CN3E in Fig. 26, the tenth pin is assigned as the terminal for the motor drive signal MOT1- / 2, the twelfth pin is for the motor drive signal MOT1- / 1, the fourteenth pin is for the motor drive signal MOT1-2, and the sixteenth pin is for the motor drive signal MOT1-1. Note that Zener diodes D10E, D12E, D13E, and D14E are connected between the tenth pin, the twelfth pin, the fourteenth pin, the sixteenth pin and the ground as protection circuits, respectively.

[0263] The connector CN4E in Fig. 28 is connected to the side unit upper right movable object motor 104 (see Fig. 10). For this connector CN4E, the first pin is the terminal for the 12V motor drive voltage (MOT12V), and the second pin is the terminal for the vibration control signal L_VIB.

[0264] The connector CN5E is connected to the side unit upper right movable object solenoid 105 (see Fig. 10). For this connector CN5E, the first pin is the terminal for the 12V motor drive voltage (MOT12V), and the second pin is the terminal for the solenoid control signal L_SOL_01.

[0265] The connector CN6E is connected to the blower 106 on the side unit (see Fig. 10). For this connector CN6E, the first pin is the terminal for the 12V motor drive voltage (MOT12V), and the second pin is the terminal for the blower control signal L_BRO.

[0266] In addition, the conductor points P1 and P2 on the housings of the connectors CN2E, CN3E, CN4E, CN5E, CN6E, and CN7E are connected to the ground for mounting strength.

[0267] The power supply voltage on the upper right LED board 600 of this side unit will be described. On the upper right LED board 600 of the side unit, buffer circuits 601 shown in FIG. 25, buffer circuit 604 shown in FIG. 26, and buffer circuit 607 shown in FIG. 28 are mounted as ICs. These are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 described above with reference to FIG. 13. As the power supply voltage for these, a 5V DC voltage (DC5V) is used. The 5V DC voltage (DC5V) is the voltage on the positive electrode side of the capacitor C1E via the fuse F1E with respect to the 5V DC voltage (DC5VB) supplied from the first pin of the connector CN1E in FIG. 24.

[0268] Also, P / S conversion circuits 602 and 603 shown in FIG. 25 are mounted as ICs, and the power supply voltage for these is also set to 5V DC voltage (DC5V). The P / S conversion circuits 602 and 603 are the same ICs as the P / S conversion circuit 505 in FIG. 18.

[0269] Also, an LED driver 605 shown in FIG. 27 and an S / P conversion circuit (LED driver) 606 shown in FIG. 28 are mounted as ICs, and as the power supply voltage for these, a 12V DC voltage (DC12VB) supplied from the fifth pin and the seventh pin of the connector CN1E is used. In this case, the 12V DC voltage (DC12VB) is taken out as the voltage on the positive electrode side of the capacitor C2E via the fuse F2E from the fifth pin and the seventh pin of the connector CN1E in FIG. 24.

[0270] Also, motor drivers 608 and 609 shown in FIG. 28 are mounted as ICs, and for these, a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) are used as the power supply voltage.

[0271] The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB). As shown in Fig. 29, the anode side of the Schottky barrier diode D8E is connected to the line of the 12V DC voltage (DC12VB). Between the cathode side of the Schottky barrier diode D8E and the ground, a resistor R23E, capacitors C10E, C11E, and a chip varistor 611 are connected in parallel. With this configuration, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage with overvoltage protection. As shown in the same figure, the 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a circuit composed of a diode D7E, a resistor R17E, and a capacitor C8E.

[0272] The flow of various signals in the upper right LED board 600 of the side unit will be described below. To the connector CN1E in Fig. 24, from the relay board 550, a load signal S_IN_LOAD, a clock signal S_IN_CLK, an enable signal ENABLE_L (reset signal RESET_M), a clock signal CLK_P, a reset signal RESET_P, and a data signal DATA_P are input. These signals are supplied to the buffer circuit 601 in Fig. 25 via damping resistors R66E, R9E, R11E, and R12E, and the signals are compensated. Note that protection circuits composed of a resistor R3E and a Zener diode D2E, a resistor R6E and a Zener diode D3E, a resistor R66E and a Zener diode D15E, a resistor R9E and a Zener diode D6E, a resistor R11E and a Zener diode D5E, and a resistor R12E and a Zener diode D15E are provided in the signal paths of these respective signals as shown in Fig. 24.

[0273] The clock signal CLK_P, data signal DATA_P, and reset signal RESET_P are output as the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A after being signal-compensated by the buffer circuit 601, and are input to the buffer circuit 604 in FIG. 26. In this case, the clock signal CLK_A is input to terminals A1 and A5, the data signal DATA_A is input to terminals A2 and A6, and the reset signal RESET_A is input to terminals A3 and A7. Then, the signals that are buffer-processed and output from terminals Y1, Y2, and Y3 are output as the clock signal CLK, data signal DATA, and reset signal RESET from the connector CN2E via the damping resistors R18E, R19E, and R20E. Also, the signals that are buffer-processed and output from terminals Y5, Y6, and Y7 are output as the clock signal CLK, data signal DATA, and reset signal RESET from the connector CN3E via the damping resistors R24E, R25E, and R26E.

[0274] That is, the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A shown in FIG. 26 are each branched into two systems before being input to the buffer circuit 604 and are each buffer-processed. Moreover, each is output as the clock signal CLK, data signal DATA, and reset signal RESET from the connectors CN2E and CN3E to separate substrates. Therefore, the buffer circuit 604 performs buffer processing while branching into two systems, enabling appropriate buffer processing after each branch. Also, the clock signal CLK, data signal DATA, and reset signal RESET output from the connectors CN2E and CN3E in this way were originally the clock signal CLK_P, data signal DATA_P, and reset signal RESET_P input from the connector CN1E in FIG. 24. These are buffer-processed by the buffer circuit 601 in FIG. 25 as described above, and then output as the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A, and are branched into two systems at the stage of the buffer circuit 604 in FIG. 26. That is, before branching, they are also buffer-processed, so that attenuation in the previous transmission path is compensated and then they are branched. Stable signal supply is realized when distributing a common signal to two substrates.

[0275] The clock signal CLK_A, data signal DATA_A, and reset signal RESET_A output from the buffer circuit 601 in FIG. 25 are also supplied to the LED driver 605 in FIG. 27. The LED driver 605 outputs a light emission drive current corresponding to the clock signal CLK_A, data signal DATA_A, and reset signal RESET_A. The LED driver 605 has output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 and can output 24-system drive currents. In this case, however, 14 terminals of the output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, LEDG5 are used. As shown in the figure, the other output terminals are connected to the ground.

[0276] And the output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4, LEDR5, LEDG5 are connected to each of the 14-system LED circuits formed as the light emitting unit 612, and a light emission drive current (25-R1, 25-G1, 25-B1 ··· 25-R5, 25-G5, 25-B5) flows through them. Each system of the LED circuits in the light-emitting unit 612 is configured by connecting two or three LEDs (LED1, LED2, ···) in series and a resistive element as shown in the figure. The LED circuits of each system are in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side of each.

[0277] In this configuration, the clock signal CLK_P, data signal DATA_P, and reset signal RESET_P input from the connector CN1E in FIG. 24 are buffered by the buffer circuit 601 in FIG. 25 and then branched. The clock signal CLK_A, data signal DATA_A, and reset signal RESET_A after the buffering are supplied to the LED driver 605 in FIG. 27 as one of the branches. The other branch is supplied to the buffer circuit 604 in FIG. 26, further branched, and transmitted to the downstream substrate from the connectors CN2E and CN3E after buffering. In this case, by branching the signal for light-emitting drive control into signals for the LED driver and for transmission to the downstream substrate after buffering by the buffer circuit 601, stable transmission is achieved and the buffer circuit configuration is made more efficient.

[0278] Also, the clock signal CLK_A, data signal DATA_A, and reset signal RESET_M output from the buffer circuit 601 in FIG. 25 are supplied to the S / P conversion circuit 606 in FIG. 28. This S / P conversion circuit 606 is configured using a chip as an LED driver. The LED driver is a device that outputs a light-emitting drive current according to the clock signal CLK_L and data signal DATA_L. In this case, it is mainly used for serial / parallel conversion for motor drive. That is, the LED driver chip is used as part of the motor drive means.

[0279] The S / P conversion circuit 606 composed of an LED driver chip is a device that outputs a light emission drive current according to the clock signal CLK_A, the data signal DATA_A, and the reset signal RESET_M. In this case, it mainly functions as a serial / parallel conversion circuit for motor drive. The S / P conversion circuit 606 has output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 for the light emission drive current and can output 24 channels of drive current. In this case, however, seven terminals, namely LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3, are used. As shown in the figure, the other output terminals are connected to the ground. Then, the outputs (currents 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, 30-G3) of the output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are buffered by the buffer circuit 607 and then supplied to the input terminals IN2, IN3, IN4 of the motor driver 608 and the input terminals IN1, IN2, IN3, IN4 of the motor driver 609.

[0280] Note that the output terminals LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, and LEDG3 are connected to a 5V DC voltage (DC5V) via resistors R60E, R61E, R62E, R56E, R57E, R58E, and R59E. This is to allow currents 30-G1, 30-B1, 30-R2, 30-G2, 30-B2, 30-R3, and 30-G3 to flow using the 5V DC voltage (DC5V) as the power source.

[0281] Based on the signals at the input terminals IN2, IN3, and IN4, the motor driver 608 outputs a blower control signal L_BRO, a solenoid control signal L_SOL01, and a vibration control signal L_VIB from the output terminals OUT2, OUT3, and OUT4. These blower control signal L_BRO, solenoid control signal L_SOL01, and vibration control signal L_VIB are supplied to connectors CN6E, CN5E, and CN4E, respectively.

[0282] The motor driver 609 outputs motor drive signals MOT1-1, MOT1-2, MOT1- / 1, and MOT1- / 2 from output terminals OUT1, OUT2, OUT3, and OUT4 based on the signals of input terminals IN1, IN2, IN3, and IN4. These motor drive signals MOT1-1, MOT1-2, MOT1- / 1, and MOT1- / 2 are supplied to the connector CN3E in FIG. 26. Therefore, the circuit from the LED driver 605 to the motor driver 609 becomes a circuit system that generates the motor drive signal of the lower right LED board 620 of the side unit on the downstream side within the upper right LED board 600 of the side unit.

[0283] The load signal S_IN_LOAD and the clock signal S_IN_CLK input from the connector CN1E in FIG. 24 are signal-compensated by the buffer circuit 601 in FIG. 25 via the damping resistors R3E and R6E, and then input to the CLR / LOAD terminals and CK terminals of the P / S conversion circuits 602 and 603 respectively to control the parallel / serial conversion process. When a 5V DC voltage (DC5V) is applied to the P / S CONT terminal of the P / S conversion circuits 602 and 603, the P / S CONT terminal becomes P / S CONT terminal = H, and the eight terminals of the Q / D1 terminal to Q / D8 terminal are parallel inputs.

[0284] At the parallel input terminals Q / D1 terminal to Q / D8 terminal of the P / S conversion circuit 603, the sense signal SENS_C is input to the Q / D1 terminal, the sense signal SENS_B is input to the Q / D2 terminal, the sense signal SENS_A is input to the Q / D4 terminal, the sense signal SENS1X is input to the Q / D4 terminal, and the sense signal SENS2X is input to the Q / D5 terminal. The Q / D6 terminal, Q / D7 terminal, and Q / D8 terminal are connected to the ground. The sense signals SENS_A, SENS_B, SENS_C, and SENS1X are input from the connector CN3E. The sense signal SENS2X is input from the connector CN7E.

[0285] As described above, the P / S conversion circuit 603 combines the input sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X and converts them into serial data (serial data signal SDT3), which is then output from the Q8C terminal. This serial data signal SDT3 is input to the SI terminal of the P / S conversion circuit 602.

[0286] At the parallel input terminals Q / D1 to Q / D8 of the P / S conversion circuit 602, a 5V DC voltage (DC5V) is applied to the Q / D1 terminal, Q / D2 terminal, and Q / D8 terminal, and the others are connected to ground. The P / S conversion circuit 602 combines the serial data signal SDT3 from the P / S conversion circuit 603 input to the SI terminal and the logic (H / L) of the Q / D1 to Q / D8 terminals, converts them into serial data (serial data signal SDT4), and outputs it from the Q8 terminal. This serial data signal SDT4 is input to the buffer circuit 601 and undergoes buffer processing. This output is transmitted upstream from the connector CN1E via the damping resistor R1E in FIG. 24 as the serial data signal S_IN_DATAx from the upper right LED board 600 of the side unit.

[0287] As described above, the upper right LED board 600 of the side unit has the following configuration. · The enable signal ENABLE_L (reset signal RESET_M), clock signal CLK_P, reset signal RESET_P, and data signal DATA_P are input, and buffer processing is performed on them by the buffer circuit 601. Then, the signals after buffer processing are used for LED emission, for generating motor drive signals, or transferred to the downstream side.

[0288] · The clock signal S_IN_CLK and load signal S_IN_LOAD are supplied to the P / S conversion circuits 602 and 603 via the buffer circuit 601 and are used for parallel / serial conversion processing. · Various sense signals SENS_A, SENS_B, SENS_C, SENS1X, and SENS2X are collectively converted into serial data to generate a serial data signal S_IN_DATAx. This serial data signal S_IN_DATAx is transmitted upstream. As described above, this serial data signal S_IN_DATAx is further serialized together with sense signals SENS8, SENS9, SENS11, and SENS1 on the front frame LED connection board 500 to become a serial data signal S_IN_DATA, and is transmitted to the effect control board 30 via the inner frame LED relay board 400.

[0289] · The connector CN1E receives a 12V DC voltage (DC12VB) and a 5V DC voltage (DC5VB) as the operating power supply. · The 12V DC voltage (DC12VB) is separated into a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) used for generating a motor drive signal. · The 12V DC voltage (DC12VB) and the 5V DC voltage (DC5VB) are supplied as operating power supply voltages to the downstream side.

[0290] In the right upper LED board 600 of the side unit, as shown in FIGS. 24 to 29 including what has been mentioned above, electronic elements such as resistors R1E, R2E ···, capacitors C1E, C2E ···, diodes (including Zener diodes) D1E, D2E ··· are connected to the required locations. Also, as shown in the figure, taps TP1E, TP2E ··· are provided and used for connection to the required locations. Although not shown in the figure, capacitors for reducing power supply noise and the like are appropriately arranged between the power supply lines of DC 5V and DC 12V and the ground.

[0291] [5.6 Right lower LED board 620 of the side unit] The right lower LED board 620 of the side unit will be described with reference to FIGS. 30 and 31. These figures separately show the circuit configurations provided on the right lower LED board 620 of the side unit.

[0292] On the right - lower LED board 620 of the side unit, connectors CN1F, CN3F, CN4F shown in FIG. 30 and connector CN2F shown in FIG. 31 are mounted as connectors.

[0293] The connector CN3F in FIG. 30 is connected to the transmission - line end of the transmission line H11 that connects to the connector CN3E of the upper - right LED board 600 of the side unit in FIG. 26. Therefore, this connector CN3F has a 16 - terminal configuration from the first pin to the 16th pin as numbered "1" to "16", and the terminal assignment is the same as that of the above - mentioned connector CN3E.

[0294] The connector CN1F is connected to the right - lower movable - object motor 103 of the side unit shown in FIG. 10. A 12V motor drive voltage (MOT12V) is applied to the third pin and the fourth pin. The motor drive signals MOT1 - / 2, MOT1 - / 1, MOT1 - 2, MOT1 - 1 input from the connector CN3F are output from the first pin, the second pin, the fifth pin, and the sixth pin.

[0295] The connector CN4F is connected to the right - lower movable - object position - detection switch 102 of the side unit shown in FIG. 10. The first pin is a 12V DC voltage (DC12VB) terminal, and the second pin is a ground terminal. The third pin is the input terminal of the sense signal SENS1X from the connected position - detection switch.

[0296] The connector CN2F in FIG. 31 is connected to an LED board (not shown) arranged in the side unit 10. The first pin is a 12V DC voltage (DC12VB) terminal. The second pin to the fifth pin are terminals of the light - emission drive signal.

[0297] Note that the conductor points P1 and P2 in the housings of the connectors CN1F, CN2F, CN3F, and CN4F are connected to the ground for mounting strength.

[0298] The power supply voltage of the lower right LED board 620 of this side unit will be described. The lower right LED board 620 of the side unit is equipped with photocouplers PC1F, PC2F, and PC3F. As the power supply voltage for these, a 5V DC voltage (DC5V) is used. The 5V DC voltage (DC5V) is supplied from the first pin of the connector CN3F.

[0299] Also, on the lower right LED board 620 of the side unit, as an IC, the LED driver 621 shown in FIG. 31 is mounted, and as the power supply voltage for this, a 12V DC voltage (DC12VB) supplied from the 11th pin of the connector CN1E is used. Also, the 12V motor drive voltage (MOT12V) output from the connector CN1F shown in FIG. 30 is supplied from the 15th pin of the connector CN3F.

[0300] The flow of various signals on the lower right LED board 620 of the side unit will be described. The clock signal CLK, data signal DATA, and reset signal RESET are input to the connector CN3F from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 621 shown in FIG. 31. The LED driver 621 outputs a light emission drive current according to the clock signal CLK, data signal DATA, and reset signal RESET.

[0301] The LED driver 621 has output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 and can output 24 channels of drive current. In this case, 12 terminals of the output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, LEDB4 are used to drive the LED to emit light. Also, 4 terminals of the output terminals LEDR7, LEDG7, LEDB7, LEDR8 are used to drive the LED to emit light on an LED board (not shown) connected to the connector CN2F. As shown in the figure, the other output terminals are connected to the ground.

[0302] The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3, LEDR4, LEDG4, and LEDB4 are connected to each of the 12 systems of LED circuits formed as the light emitting unit 622, and drive currents for light emission (27-R1, 27-G1, 27-B1 ··· 27-R4, 27-G4, 27-B4) are passed through. Each system of LED circuits in the light emitting unit 622 is configured by a series connection of one or three LEDs and a resistor element as shown in the figure. Each system of LED circuits is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side thereof. The output terminals LEDR7, LEDG7, LEDB7, and LEDR8 are connected to four systems of the light emission driving unit 623. In the light emission driving unit 623, drive currents for light emission of four systems (27-R7, 27-G7, 27-B7 ··· 27-R8) are output from the connector CN2F.

[0303] The sense signals SENS_A, SENS_B, and SENS_C are obtained by the photocouplers PC1F, PC2F, and PC3F in FIG. 30. These are transmitted from the connector CN3F to the side unit upper right LED substrate 600. The sense signal SENS1X obtained from the connector CN4F is also transmitted from the connector CN3F to the side unit upper right LED substrate 600. These sense signals SENS_A, SENS_B, SENS_C, and SENS1X are serialized as described above.

[0304] In the side unit lower right LED substrate 620, electronic elements such as resistors R1F, R2F ···, capacitors C1F, C2F ··· are connected to required locations as shown in FIGS. 30 and 31, including those mentioned above. Also, taps TP1F, TP2F ··· are provided as shown in the figure and are used for connection to required locations.

[0305] [5.7 Side Unit Upper LED Substrate 630] The LED substrate 630 on the side unit will be described with reference to FIG. 32. A connector CN1T is mounted on the LED substrate 630 on the side unit. The connector CN1T is connected to the transmission line end of a transmission line H12 that connects to the connector CN2E of the upper right LED substrate 600 of the side unit in FIG. 26.

[0306] Therefore, this connector CN1T has a six-terminal configuration from the first pin to the sixth pin as numbered "1" to "6", and the terminal assignment is the same as that of the above-mentioned connector CN2E. Note that the conductor points P1 and P2 in the housing of the connector CN1T are connected to the ground for mounting strength.

[0307] An LED driver 631 is mounted on this LED substrate 630 on the side unit as an IC, and a 12V DC voltage (DC12VB) supplied from the sixth pin of the connector CN1T is used as the power supply voltage for this.

[0308] The flow of various signals will be described. A clock signal CLK, a data signal DATA, and a reset signal RESET are input to the connector CN1T from the upper right LED substrate 600 of the side unit, and these signals are supplied to the LED driver 631. The LED driver 631 outputs a light emission drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

[0309] The LED driver 631 has output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 for the light emission drive current, and can output 24 systems of drive currents. In this case, however, the nine terminals of the output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, LEDB3 are used for the LED light emission drive. As shown in the figure, the other output terminals are connected to the ground.

[0310] The output terminals LEDR1, LEDG1, LEDB1, LEDR2, LEDG2, LEDB2, LEDR3, LEDG3, and LEDB3 are connected to each of the nine LED circuits formed as the light emitting unit 632, and drive a light emitting current (27-R1, 27-G1, 27-B1 ··· 27-R3, 27-G3, 27-B3) to flow. Each LED circuit of each system of the light emitting unit 632 is composed of a series connection of two LEDs and a resistor element as shown in the figure. Each LED circuit of each system is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side thereof.

[0311] On the LED substrate 630 on the side unit, electronic elements such as resistors R1T, R2T ···, capacitors C1T, C2T ··· are connected to required locations as shown in Fig. 32, including those mentioned above. Also, as shown in the figure, taps TP1T, TP2T ··· are provided and used for connection to required locations.

[0312] [5.8 Button LED Connection Substrate 640] The button LED connection substrate 640 will be described with reference to Fig. 33. Connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G are mounted on the button LED connection substrate 640 as connectors.

[0313] The transmission line end of the transmission line H15 that connects between the connector CN1G and the connector CN10C of the front frame LED connection substrate 500 in Fig. 20 is connected. Therefore, this connector CN1E has a 20-terminal configuration from the first pin to the 20th pin as numbered "1" to "20", and the terminal assignment is the same as that of the above-mentioned connector CN10C.

[0314] The transmission line end of the transmission line H16 that connects between the connector CN2G and the button LED substrate 660 shown in Fig. 11 is connected. A 12V DC voltage (DC12VB), which is the power supply voltage of the button LED board 660, is applied to the 3rd pin and the 7th pin. The 1st pin and the 6th pin are grounded. The 2nd pin, the 4th pin, and the 5th pin are terminals for the clock signal CLK, the data signal DATA, and the reset signal RESET, respectively.

[0315] The connector CN3G is connected to a motor (not shown). The motor drive signals MOTφ1, MOTφ / 1, MOTφ2, and MOTφ / 2 input from the connector CN1G are output from the 6th pin, the 2nd pin, the 5th pin, and the 1st pin of the connector CN3G. Also, the 12V motor drive voltage (MOT12V) input from the connector CN1G is applied to the 3rd pin and the 4th pin as the 12V motor drive voltage (MOT12VA) shown in the figure.

[0316] The connector CN4G is connected to a vibration device (not shown). A 12V motor drive voltage (MOT12VA) is applied to the 1st pin as the power supply voltage of the vibration device, and the motor drive signal DCMOT3 input from the connector CN1G is output to the 2nd pin as the drive signal of the vibration device. A DC motor is used for the vibration device.

[0317] The connector CN5G is connected to the push button sensor inside the effect button 13. The 1st pin is a 12V DC voltage (DC12VB), and the 2nd pin is a grounded terminal. The 3rd pin is the input terminal for the sense signal SENS8 from the connected push button sensor.

[0318] The connector CN6G is connected to the rotation origin sensor. The 1st pin is a 12V DC voltage (DC12VB), and the 3rd pin is a grounded terminal. The 2nd pin is the input terminal for the sense signal SENS9 from the connected rotation origin sensor.

[0319] The connector CN8G is connected to the rotation effect light sensor. The first pin is for 12V DC voltage (DC12VB), and the third pin is for the ground terminal. The second pin is the input terminal for the sense signal SENS11 from the connected rotation effect light sensor.

[0320] Note that the conductor points P1 and P2 on the housings of the connectors CN1G, CN2G, CN3G, CN4G, CN5G, CN6G, and CN8G are connected to the ground for mounting strength.

[0321] A buffer circuit 641 is mounted on this button LED connection board 640. As the power supply voltage for this, 5V DC voltage (DC5V) is used. The 5V DC voltage (DC5V) is supplied from the eighth pin of the connector CN1G.

[0322] The flow of various signals on the button LED connection board 640 will be described. The clock signal CLK_L, clear signal CLR_L, and data signal DATA_L supplied from the upstream front frame LED connection board 500 to the connector CN1G are input to the buffer circuit 641 via the chip resistor RA1G and are buffer-processed. Then, they are sent to the connector CN2G via the chip resistor RA2G and transmitted to the downstream button LED board 660. A capacitor C1G is inserted between the 5V DC voltage (DC5V) and the ground of the buffer circuit 641.

[0323] Although not shown in the figure, on the button LED connection board 640, capacitors for power noise reduction and the like are appropriately arranged between the power supply lines of DC 5V and DC 12V and the ground.

[0324] [5.9 Button LED Board 660] The button LED board 660 will be described with reference to FIGS. 34 and 35. These figures separately show the circuit configuration provided on the button LED board 660.

[0325] The connector CN1H in FIG. 34 of the button LED board 660 is mounted. Connector CN1H has the transmission line end of transmission line H16 connected between it and connector CN2G on the button LED connection board 640 in Fig. 33. Therefore, this connector CN1H has a 7-terminal configuration from the first pin to the seventh pin as numbered "1" to "7", and the terminal assignment is the same as that of the above-mentioned connector CN2G. Also, the conductor points P1 and P2 on the housing of connector CN1H are connected to the ground for mounting strength.

[0326] A 12V DC voltage (DC12VB) is supplied to this button LED board 660 as the power supply voltage input to connector CN1H. On the button LED board 660, as ICs, the LED driver 661 in Fig. 34 and the LED driver 663 in Fig. 35 are mounted, and a 12V DC voltage (DC12VB) is used as the power supply voltage for them. A 12V DC voltage (DC12VB) is also used as the power supply voltage for the light-emitting parts 664 and 662.

[0327] The flow of various signals on the button LED board 660 will be described. To connector CN1H, a clock signal CLK, a data signal DATA, and a reset signal RESET are input from the upper right LED board 600 of the side unit, and these signals are supplied to the LED driver 661 via the chip resistor RA1H in Fig. 34. The LED driver 661 outputs a light-emitting drive current according to the clock signal CLK, the data signal DATA, and the reset signal RESET.

[0328] The LED driver 661 performs 24-system LED light-emitting drive using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 of the light-emitting drive current. That is, the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 are connected to each of the 24 systems of LED circuits formed as the light emitting unit 662, and drive currents for light emission (19-R1, 19-G1, 19-B1 ··· 19-R8, 19-G8, 19-B8) are passed through. Each system of LED circuits in the light emitting unit 662 is configured by a series connection of two or three LEDs and a resistor element as shown in the figure. Each system of LED circuits is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side thereof.

[0329] The clock signal CLK, data signal DATA, and reset signal RESET are also supplied to the LED driver 663 in FIG. 35. The LED driver 663 performs LED light emission driving for six systems using three output terminals each of the output terminals for drive currents for light emission, i.e., LEDR1, LEDG1, LEDB1 ··· LEDR6, LEDG6, LEDB6. That is, the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR6, LEDG6, LEDB6 are connected to each of the six systems of LED circuits formed as the light emitting unit 664, and drive currents for light emission (20-R1, 20-G1, 20-B1 ··· 20-R6, 20-G6, 20-B6) are passed through. Each system of LED circuits in the light emitting unit 664 is configured by a series connection of two or three LEDs and a resistor element as shown in the figure. A Zener diode is connected in parallel to each LED. Each system of LED circuits is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side thereof.

[0330] In addition, in the lower right LED board 620 of the side unit, in addition to those mentioned above, as shown in FIGS. 34 and 35, electronic elements such as resistors R1H, R2H ···, capacitors C1H, C2H ···, diodes (including Zener diodes) D1H, D2H ··· are connected at required locations. Also, as shown in the figure, taps TP1H, TP2H ··· are provided and used for connection to required locations.

[0331] [5.10 LED Connection Substrate 700] Next, the substrate arranged on the game board 3 side will be described. First, the LED connection substrate 700 will be described with reference to FIGS. 36, 37, 38, 39, 40, and 41. These figures separately show the circuit configurations provided on the LED connection substrate 700. As shown in FIG. 11, the LED connection substrate 700 is a substrate connected to the effect control substrate 30 on the game board 3.

[0332] The LED connection substrate 700 is equipped with connectors such as connector CN1J in FIG. 36, connectors CN5J and CN6J in FIG. 37, connectors CN2J, CN3J, CN4J, and CN12J in FIG. 38, connector CN10J in FIG. 39, connectors CN7C and CN11J in FIG. 40, and connectors CN8J and CN9J in FIG. 41.

[0333] The connector CN1J in FIG. 36 is connected to the transmission line end of the transmission line H20 that connects to the effect control substrate 30 as shown in FIG. 11. This connector CN1J has a 40-terminal configuration from the first pin to the 40th pin as numbered from "1" to "40".

[0334] The first pin, second pin, eighth pin, ninth pin, tenth pin, sixteenth pin, eighteenth pin, nineteenth pin, twentieth pin, twenty-second pin, twenty-ninth pin, thirty-first pin, thirty-second pin, thirty-third pin, thirty-fourth pin, thirty-ninth pin, and fortieth pin of the connector CN1J are connected to the ground. The fourth pin and sixth pin are terminals for a 5V DC voltage (DC5VB). The twelfth pin, fourteenth pin, twenty-fourth pin, twenty-sixth pin, twenty-eighth pin, and thirtieth pin are terminals for a 12V DC voltage (DC12VB). The eleventh pin, seventeenth pin, thirty-fifth pin, and thirty-seventh pin are unused.

[0335] The third pin is assigned as the terminal for the clock signal P_S_IN_CLK, the fifth pin is assigned as the terminal for the serial data signal P_S_IN_DATA, and the seventh pin is assigned as the terminal for the load signal P_S_IN_LOAD. The serial data signal P_S_IN_DATA is serial data transmitted from the LED connection board 700 to the effect control board 30, and the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are signals supplied from the effect control board 30 for transmitting the serial data signal P_S_IN_DATA.

[0336] The 13th pin is assigned as the terminal for the clock signal P_S_OUT_CLK, and the 15th pin is assigned as the terminal for the serial data signal P_S_OUT_DATA. The serial data signal P_S_OUT_DATA is serial data transmitted from the effect control board 30 together with the clock signal P_S_OUT_CLK.

[0337] The 21st pin is assigned as the terminal for the clear signal M_S_CLR (reset signal RESET_M), the 23rd pin is assigned as the terminal for the clock signal M_S_OUT_CLK (clock signal CLK_M), the 25th pin is assigned as the terminal for the serial data signal M_S_OUT_DATA (serial data signal DATA_M), and the 27th pin is assigned as the terminal for the enable signal M_S_ENABLEP (latch signal LATCH_M). The serial data signal M_S_OUT_DATA is serial data transmitted from the effect control board 30 together with the clock signal M_S_OUT_CLK.

[0338] The conductor points P1 and P2 in the housings of the connector CN1J and the connectors CN2J, CN3J, CN4J, CN5J, CN6J, CN7J, CN8J, CN9J, CN10J, CN11J, and CN12J described later are connected to the ground for mounting strength.

[0339] The connector CN5J in FIG. 37 is connected to a motor of a movable object (not shown). A DC voltage of 18V (MOT18VA), which is the power supply voltage for the motor, is applied to the third and fourth pins. The first pin is assigned as the terminal for motor drive signal MOT6- / 2, the second pin for motor drive signal MOT6- / 1, the fifth pin for motor drive signal MOT6-2, and the sixth pin for motor drive signal MOT6-1.

[0340] The connector CN6J in Fig. 37 is also connected to the motors of other movable objects (not shown). A DC voltage of 18V (MOT18VA), which is the power supply voltage for the motors, is applied to the third and fourth pins. The first pin is assigned as the terminal for motor drive signal MOT7- / 2, the second pin for motor drive signal MOT7- / 1, the fifth pin for motor drive signal MOT7-2, and the sixth pin for motor drive signal MOT7-1.

[0341] The connector CN2J in Fig. 38 is connected to the position detection switch of the accessory. A DC voltage of 12V (DC12VB), which is the power supply voltage on the position detection switch side, is applied to the first pin. The third pin is the ground terminal. A sense signal SENSv0, which is the detection signal of the lower lower movable object right position detection switch 121 (see Fig. 10), for example, is input to the second pin of this connector CN2J. The sense signal SENSv0 is pulled up by a DC voltage of 5V (DC5V) via the resistor R5J.

[0342] The connector CN4J is also connected to the position detection switch of the accessory. The first pin is the terminal for a DC voltage of 12V (DC12VB), which is the power supply voltage on the position detection switch side, and the third pin is the ground terminal. A sense signal SENSv1, which is the detection signal of the lower lower movable object left position detection switch 125 (see Fig. 10), for example, is input to the second pin of this connector CN4J. The sense signal SENSv1 is pulled up by a DC voltage of 5V (DC5V) via the resistor R29J.

[0343] The connector CN12J is also connected to the position detection switch of the accessory. The first pin is the terminal for a DC voltage of 12V (DC12VB), which is the power supply voltage on the position detection switch side, and the third pin is the ground terminal. For example, a sense signal SENSv9, which is a detection signal of the lower movable object position detection switch 120 (see FIG. 10), is input to the second pin of the connector CN12J. The sense signal SENSv9 is pulled up by a 5V DC voltage (DC5V) via a resistor R31J.

[0344] The connector CN3J is connected to the power supply module board 904 in FIG. 7. The first pin, the second pin, and the fourth pin are used as terminals for an 18V DC voltage Vout, the seventh pin, the ninth pin, and the tenth pin are used as terminals for a 35V DC voltage (DC35V), and the fifth pin, the sixth pin, and the eighth pin are used as ground terminals.

[0345] The connector CN10J in FIG. 39 is connected to a relay board (not shown). It has a 32-terminal configuration from the first pin to the 32nd pin, numbered "1" to "32". The first pin is a terminal to which a 12V DC voltage (DC12VB) is applied via a fuse F6J, the second pin is a terminal to which a 5V DC voltage (DC5V) is applied via a fuse F9J, and the third pin, the fourth pin, and the fifth pin are terminals to which a 12V motor drive voltage (MOT12V) is applied. The ninth pin, the thirteenth pin, the seventeenth pin, the twenty-first pin, the twenty-fifth pin, the twenty-seventh pin, the twenty-ninth pin, the thirtieth pin, the thirty-first pin, and the thirty-second pin are connected to ground.

[0346] The seventh pin is assigned as a terminal for the motor drive signal MOT1- / 2, the eighth pin is assigned as a terminal for the motor drive signal MOT1- / 1, the tenth pin is assigned as a terminal for the motor drive signal MOT1-2, and the twelfth pin is assigned as a terminal for the motor drive signal MOT1-1. The fourteenth pin is assigned as a terminal for the motor drive signal MOT2- / 2, the sixteenth pin is assigned as a terminal for the motor drive signal MOT2- / 1, the eighteenth pin is assigned as a terminal for the motor drive signal MOT2-2, and the twentieth pin is assigned as a terminal for the motor drive signal MOT2-1. The twenty-second pin is assigned as a terminal for the motor drive signal MOT3- / 2, the twenty-fourth pin is assigned as a terminal for the motor drive signal MOT3- / 1, the twenty-sixth pin is assigned as a terminal for the motor drive signal MOT3-2, and the twenty-eighth pin is assigned as a terminal for the motor drive signal MOT3-1.

[0347] The 7th pin is the terminal of the clock signal CLK_B, and the 11th pin is the terminal of the data signal DATA_B. The 15th pin is the terminal of the sense signal SENSv2, the 19th pin is the terminal of the sense signal SENSv3, and the 23rd pin is the terminal of the sense signal SENSv4. The sense signal SENSv2 is, for example, the detection signal of the upper movable object position detection switch 132 in FIG. 10, the sense signal SENSv3 is, for example, the detection signal of the upper movable object left position detection switch 130, and the sense signal SENSv4 is, for example, the detection signal of the left movable object position detection switch 134.

[0348] The connector CN7J in FIG. 40 is connected to an LED board (not shown). The 1st pin is the terminal of the 12V DC voltage (DC12VB). The 5th and 6th pins are the terminals of the 18V LED drive voltage (LED18V). The 4th, 7th, and 8th pins are connected to the ground. The 2nd pin is the terminal of the clock signal CLK_E, and the 3rd pin is the terminal of the data signal DATA_E.

[0349] The connector CN11J is connected to the transmission line end of the transmission line H30 that connects to the backside lower middle relay board 800 shown in FIG. 11. It has a 16-terminal configuration from the 1st pin to the 16th pin as numbered "1" to "16".

[0350] The 4th and 6th pins are the terminals to which a 12V DC voltage (DC12VB) is applied via the fuse F10J, and the 7th and 9th pins are the terminals to which a 12V motor drive voltage (MOT12V) is applied via the fuse F11J. The 1st, 15th, and 16th pins are connected to the ground.

[0351] The 3rd pin is the terminal of the motor drive signal MOT4- / 2, the 5th pin is the terminal of the motor drive signal MOT4- / 1, the 11th pin is the terminal of the motor drive signal MOT4-2, and the 13th pin is the terminal of the motor drive signal MOT4-1. The 14th pin is the terminal of the sense signal SENSv7. The sense signal SENSv7 is, for example, the detection signal of the lower front movable object position detection switch 123 in FIG. 10. The second pin, eighth pin, tenth pin, and twelfth pin are terminals that output the light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 to the back bottom relay board 800 side.

[0352] The connector CN9J in FIG. 41 is connected to an LED board (not shown). The first pin is a terminal for a 12V DC voltage (DC12VB). The tenth pin is a terminal for a 5V DC voltage (DC5V). The fourth pin and ninth pin are connected to ground. The second pin is a terminal for the clock signal CLK_D, and the third pin is a terminal for the data signal DATA_D.

[0353] The eighth pin, seventh pin, sixth pin, and fifth pin are terminals for the light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8. These light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are passed through by an LED driver mounted on an LED board (not shown). The clock signal CLK_D and data signal DATA_D from the second pin and third pin of the connector CN9J are supplied to the LED driver mounted on the LED board (not shown), and based on this, the light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 are passed through by the LED driver. These light emission drive currents 13-B7, 13-R8, 13-G8, and 13-B8 flow from the connector CN11J in FIG. 40, through the back bottom relay board 800, to the LEDs in the light emitting part 821 (see FIG. 48) of the decorative board 820 described later, causing those LEDs to emit light.

[0354] The eleventh pin of the connector CN9J is a terminal for the sense signal SENSv8. The sense signal SENSv8 is, for example, a detection signal of the sorting position detection switch 122 in FIG. 10.

[0355] The connector CN8J in FIG. 41 is connected to the transmission line end of the transmission line H21 that connects to the back left relay board 720 shown in FIG. 11. It has a 24-terminal configuration from the first pin to the twenty-fourth pin with numbers "1" to "24" attached.

[0356] Pins 1 to 4 are the terminals to which the 18V motor drive voltage (MOT18VB) is applied via fuse F12J. Pins 5 and 9 are the terminals to which the 12V DC voltage (DC12VB) is applied via fuse F7J. Pin 11 is the terminal to which the 5V DC voltage (DC5VB) is applied via fuse F8J. Pins 7, 13, 14, 19, and 20 are connected to ground.

[0357] Pin 15 is the terminal for the clock signal CLK_C, and pin 17 is the terminal for the data signal DATA_C. Pins 6 and 8 are for the motor drive signal MOT5- / 2, pins 10 and 12 are for the motor drive signal MOT5- / 1, pins 16 and 18 are for the motor drive signal MOT5-2, and pins 22 and 24 are for the motor drive signal MOT5-1. In this case, the motor to be driven is a high-torque motor and is driven by the 18V motor drive voltage (MOT18VB). And because the power consumption is high, the motor drive signals MOT5- / 2, MOT5- / 1, MOT5-2, and MOT5-1 each use two pins / lines. Pin 21 is the terminal for the sense signal SENSv6, and pin 23 is the terminal for the sense signal SENSv5. The sense signal SENSv6 is, for example, the detection signal of the lower back movable object lower left position detection switch 128 in FIG. 10, and the sense signal SENSv5 is, for example, the detection signal of the lower back movable object lower right position detection switch 127.

[0358] The power supply voltage on this LED connection board 700 will be described. On the LED connection board 700, as ICs, there are buffer circuits 703 and 704 in FIG. 36, which are 8-circuit Schmitt trigger buffers similar to the buffer circuit 402 described in FIG. 13, buffer circuit 705 in FIG. 39 which is a triple buffer gate, and buffer circuits 707 and 708 in FIG. 41. As the power supply voltage for these, as shown in FIG. 36, a 5V DC voltage (DC5V) based on the 5V DC voltage (DC5VB) from the connector CN1J is used.

[0359] In addition, as an IC, the P / S conversion circuits 701 and 702 in FIG. 36 are mounted, and a power supply voltage of 5V DC voltage (DC5V) is also used for them. The 5V DC voltage (DC5VB) is taken out from the positive electrode side of the capacitor C4J via the fuse F1J from the connector CN1J. Note that the P / S conversion circuits 701 and 702 are the same ICs as the P / S conversion circuit 505 in FIG. 18.

[0360] Note that the 12V DC voltage (DC12VB) output downstream from the connectors CN2J, CN4J, CN7J, CN8J, CN10J, CN11J, and CN12J is taken out from the positive electrode side of the capacitor C5J via the fuse F2J from the connector CN1J.

[0361] In addition, on the LED connection board 700, as an IC, the motor drivers 710 to 713 in FIG. 37 are mounted, and a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) are used as the power supply voltage for them. Furthermore, motor drivers 714, 715, and 716 are mounted, and an 18V motor drive voltage (MOT18VA) and a 12V DC voltage (DC12VS) are used as the power supply voltage for them.

[0362] The 12V motor drive voltage (MOT12V) is separated from the 12V DC voltage (DC12VB) by the power supply separation / protection circuit 719. As shown in FIG. 36, the anode side of the Schottky barrier diode D5J is connected to the 12th, 14th, 24th, 26th, 28th, and 30th pins of the connector CN1J. Between the cathode side of the Schottky barrier diode D5J and the ground, a resistor R6J, capacitors C14J and C15J, and the chip varistor 709 are connected in parallel. With this configuration as the power supply separation / protection circuit 719, the 12V motor drive voltage (MOT12V) is separated as a power supply voltage with overvoltage protection.

[0363] The 12V DC voltage (DC12VS) is separated from the 12V DC voltage (DC12VB) using a circuit consisting of diode D1J, resistor R1J, and capacitor C3J shown in FIG. 38.

[0364] The 18V motor drive voltages (MOT18VA, MOT18VB) and the 18V LED drive voltage (LED18V) are separated from the 18V DC voltage Vout input from connector CN3J as also shown in FIG. 38. The anode side of the Schottky barrier diode D7J is connected via fuse F3J to the first, second, and fourth pins to which the 18V DC voltage Vout is applied. Resistors R7J, capacitors C17J and C18J are connected in parallel between the cathode side of the Schottky barrier diode D7J and ground. With this configuration, the 18V motor drive voltage (MOT18VA) is extracted. Also, the anode side of the Schottky barrier diode D9J is connected via fuse F4J to the first, second, and fourth pins to which the 18V DC voltage Vout is applied. Resistors R8J, capacitors C20J and C21J are connected in parallel between the cathode side of the Schottky barrier diode D9J and ground. With this configuration, the 18V motor drive voltage (MOT18VB) is extracted. Also, the anode side of the Schottky barrier diode D11J is connected via fuse F5J to the first, second, and fourth pins to which the 18V DC voltage Vout is applied. Resistors R9J, capacitors C23J and C24J are connected in parallel between the cathode side of the Schottky barrier diode D11J and ground. With this configuration, the 18V LED drive voltage (LED18V) is extracted.

[0365] The flow of various signals in the LED connection board 700 will be described below. The clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA are transmitted from the effect control board 30 to the connector CN1J in FIG. 36. These are signals used for operation control downstream from the LED connection board 700.

[0366] The clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA are input to terminals A5 and A7 of the buffer circuit 703 and signal-compensated as shown as the clock signal CLK_P and the serial data signal DATA_P in FIG. 36. Then, they are output from terminals Y5 and Y7 of the buffer circuit 703, input to the buffer circuit 706 in FIG. 40 as the clock signal CLK_A and the serial data signal DATA_A, and buffer-processed. Then, they are transmitted downstream as the clock signal CLK_E and the serial data signal DATA_E from the connector CN7J.

[0367] Also, the clock signal CLK_A and the serial data signal DATA_A output from terminals Y5 and Y7 of the buffer circuit 703 are also input to the buffer circuit 705 in FIG. 39, buffer-processed, and transmitted downstream as the clock signal CLK_B and the serial data signal DATA_B from the connector CN10J. Furthermore, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 707 in FIG. 41, buffer-processed, and transmitted downstream as the clock signal CLK_D and the serial data signal DATA_D from the connector CN9J. Furthermore, the clock signal CLK_A and the serial data signal DATA_A are also input to the buffer circuit 708 in FIG. 41, buffer-processed, and transmitted to the relay board 720 on the back left middle of the downstream side as the clock signal CLK_C and the serial data signal DATA_C from the connector CN8J.

[0368] From the effect control board 30, a clear signal M_S_CLR (reset signal RESET_M), a clock signal M_S_OUT_CLK (clock signal CLK_M), a serial data signal M_S_OUT_DATA (serial data signal DATA_M), and an enable signal M_S_ENABLEP (latch signal LATCH_M) are transmitted to the connector CN1J in FIG. 36. These are used for control for motor drive. These signals are input to the A7 terminal, A1 terminal, A3 terminal, and A5 terminal of the buffer circuit 704 for signal compensation. Then, they are respectively input to the motor drivers 710 to 716 in FIG. 37 via the chip resistor RA4J. That is, in each of the motor drivers 710 to 716, the reset signal RESET_M is input to the RESET terminal, the latch signal LATCH_M is input to the LATCH terminal, the clock signal CLK_M is input to the SCLK terminal, and the serial data signal DATA_M is input to the SDIN terminal.

[0369] In response to these inputs, the motor drivers 710 to 713 generate 12V system motor drive signals respectively. That is, the motor driver 710 generates the motor drive signals MOT1- / 2, MOT1- / 1, MOT1-2, and MOT1-1 output from the connector CN10J. The motor driver 711 generates the motor drive signals MOT2- / 2, MOT2- / 1, MOT2-2, and MOT2-1 output from the connector CN10J. The motor driver 712 generates the motor drive signals MOT3- / 1, MOT3-2, and MOT3-1 output from the connector CN10J. The motor driver 713 generates the motor drive signals MOT4- / 2, MOT4- / 1, MOT4-2, and MOT4-1 output from the connector CN11J.

[0370] Also, in response to the input of the reset signal RESET_M, latch signal LATCH_M, clock signal CLK_M, and serial data signal DATA_M, the motor drivers 714 to 716 generate 18V system motor drive signals respectively. That is, the motor driver 714 generates the motor drive signals MOT5- / 2, MOT5- / 1, MOT5-2, and MOT5-1 output from the connector CN8J. The motor driver 715 generates the motor drive signals MOT6- / 2, MOT6- / 1, MOT6-2, and MOT6-1 output from the connector CN5J. The motor driver 716 generates motor drive signals MOT7- / 2, MOT7- / 1, MOT7-2, and MOT7-1 output from the connector CN6J.

[0371] The clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are transmitted from the effect control board 30 to the connector CN1J in FIG. 36. The clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD are input to the A3 terminal and the A2 terminal of the buffer circuit 703 for signal compensation, and then input from the Y3 terminal and the Y2 terminal of the buffer circuit 703 to the CK terminal and the CLR / LOAD terminal of the P / S conversion circuits 701 and 702 via the chip resistor RA1J. A 5V DC voltage (DC5V) is applied to the P / S CONT terminal of the P / S conversion circuits 701 and 702, making the P / S CONT terminal = H, and the eight terminals of the Q / D1 terminal to the Q / D8 terminal are parallel inputs. Then, the P / S conversion circuits 701 and 702 perform parallel-to-serial conversion according to the clock signal P_S_IN_CLK and the load signal P_S_IN_LOAD.

[0372] The sense signal SENSv8 from the connector CN9J in FIG. 41 is input to the Q / D1 terminal of the P / S conversion circuit 701. As shown in FIG. 36, this sense signal SENSv8 is pulled up by a 5V DC voltage (DC5V) via the resistor R23J. Also, the sense signal SENSv9 from the connector CN12J in FIG. 38 is input to the Q / D2 terminal of the P / S conversion circuit 701. The inputs of the Q / D3 terminal to the Q / D7 terminal are at the ground level "0" (L level), and the Q / D8 terminal is at the 5V level "1" (H level). The P / S conversion circuit 702 converts the above parallel input into serial data (serial data signal SDT5) and outputs it from the Q8C terminal. This serial data signal SDT5 is input to the SI terminal of the P / S conversion circuit 702.

[0373] The sense signals SENSv0 to SENSv7 are input to the eight terminals of the Q / D1 terminal to Q / D8 terminal of the P / S conversion circuit 702. The sense signal SENSv0 is input from the connector CN2J. The sense signal SENSv1 is input from the connector CN4J. The sense signals SENSv2 to SENSv4 are input from the connector CN10J. The sense signals SENSv5 and SENSv6 are input from the connector CN8J. The sense signals SENSv5 and SENSv7 are input from the connector CN11J. The sense signals SENSv2 to SENSv7 are pulled up by a 5V DC voltage (DC5V) through the resistors R24J, R2J, and chip resistor RA3J, respectively.

[0374] As described above, the P / S conversion circuit 702 combines the serial data signal SDT5 from the P / S conversion circuit 701 input to the SI terminal and the sense signals SENSv0 to SENSv7, converts them into serial data (serial data signal SDT6), and outputs the result from the Q8C terminal. This serial data signal SDT6 is input to the A1 terminal of the buffer circuit 703 and undergoes buffer processing. Then, the Y1 output is supplied to the third pin of the connector CN1J through the chip resistor RA1J and is transmitted as the serial data signal P_S_IN_DATA from the LED connection board 700 to the upstream production control board 30.

[0375] As described above, the LED connection board 700 has the following configuration. · Serialize the sense signals SENSv0 to SENSv9 input from the downstream side and transmit them as the serial data signal P_S_IN_DATA from the connector CN1J to the upstream side through the buffer circuit 703. · Transfer the clock signal P_S_OUT_CLK and the serial data signal P_S_OUT_DATA transmitted from the production control board 30 to the downstream side through the buffer circuit 703 and one of the buffer circuits (705, 706, 707, 708).

[0376] · The clear signal M_S_CLR (reset signal RESET_M), clock signal M_S_OUT_CLK (clock signal CLK_M), serial data signal M_S_OUT_DATA (serial data signal DATA_M), and enable signal M_S_ENABLEP (latch signal LATCH_M) sent from the performance control board 30 are supplied to the motor drivers 710 to 716 via the buffer circuit 704, and motor drive signals (MOT1- / 2, MOT1- / 1, MOT1-2, MOT1-1 ··· MOT7- / 2, MOT7- / 1, MOT7-2, MOT7-1) are generated and transmitted to the downstream side (motor).

[0377] · The connector CN1J receives a 12V DC voltage (DC12VB) and a 5V DC voltage (DC5VB) as the operating power supply. · The connector CN3J receives an 18V DC voltage Vout as the operating power supply for the 18V system (operating power supply for high-brightness LEDs and high-torque motors). · A 12V DC voltage (DC12VB), a 5V DC voltage (DC5V), a 12V motor drive voltage (MOT12V), an 18V motor drive voltage (MOT18V), and an 18V LED drive voltage (LED18V) are supplied to the downstream side as the operating power supply voltage.

[0378] In the LED connection board 700, including those mentioned above, as shown in FIGS. 36 to 41, resistors such as resistors R1J, R2J ···, chip resistors RA1J, RA2J ···, capacitors C1J, C2J ···, diodes (including Zener diodes and Schottky barrier diodes) D1J, D2J ··· and other electronic elements are connected at the required locations. Also, as shown in the figure, taps TP1J, TP2J ··· are provided and used for connection to the required locations. Although not shown in the figure, capacitors for reducing power supply noise and the like are appropriately arranged between the power supply lines of DC 5V and DC 12V and the ground.

[0379] [5.11 Rear left relay board 720] The configuration of the rear left relay board 720 is shown in Fig. 42. Connectors CN1K and CN2K are mounted on the rear left relay board 720.

[0380] The connector CN1K is connected to the transmission line end of the transmission line H21 that connects to the connector CN8J of the LED connection board 700 in Fig. 41. Therefore, this connector CN1K has a 24-terminal configuration from the first pin to the 24th pin as numbered "1" to "24", and the terminal assignment is the same as that of the above-mentioned connector CN8J.

[0381] The connector CN2K is connected to the transmission line end of the transmission line H22 that connects to the downstream decorative board 740. This connector CN1B has a 22-terminal configuration from the first pin to the 22nd pin as numbered "1" to "22".

[0382] The fourth pin, the seventh pin, and the tenth pin are ground terminals. The sixth pin is a terminal for a 5V DC voltage (DC5V). The eighth pin and the ninth pin are terminals for a 12V DC voltage (DC12VB). The eleventh pin, the twelfth pin, the thirteenth pin, and the fourteenth pin are terminals for an 18V motor drive voltage (MOT18VB).

[0383] The fifth pin is a terminal for the clock signal CLK_C, and the third pin is a terminal for the data signal DATA_C. The fifteenth pin and the sixteenth pin are terminals for the motor drive signal MOT5- / 2, the seventeenth pin and the eighteenth pin are terminals for the motor drive signal MOT5- / 1, the nineteenth pin and the twentieth pin are terminals for the motor drive signal MOT5-2, and the twenty-first pin and the twenty-second pin are terminals for the motor drive signal MOT5-1. The second pin is a terminal for the sense signal SENSv6, and the first pin is a terminal for the sense signal SENSv5.

[0384] Note that the conductor points P1 and P2 on the housings of the connectors CN1K and CN2K are connected to the ground for mounting strength.

[0385] On the back left relay board 720, the ground terminals of the 7th, 13th, 14th, 19th, and 20th pins of the connector CN1K are converted into three terminals of the 4th, 7th, and 10th pins on the connector CN2K side, converting from a 24-terminal connector to a 22-terminal connector. This reduces the number of terminals of the downstream connector CN2D.

[0386] [5.12 Decorative board 740] The decorative board 740 will be described with reference to FIG. 43. Connectors CN1L, CN2L, CN3L, CN4L, CN5L, and CN6L are mounted on the decorative board 740.

[0387] The connector CN1L is connected to the transmission line end of the transmission line H22 that connects to the connector CN2K of the back left relay board 720 in FIG. 42. Therefore, this connector CN1L has a 22-terminal configuration from the 1st pin to the 22nd pin as numbered "1" to "22", and the terminal assignment is the same as that of the above-mentioned connector CN2K. Note that the conductor points P1 and P2 in the housings of the connectors CN1K to CN6K are connected to the ground for mounting strength.

[0388] The connector CN2L is connected to a position detection switch of a movable object (not shown). The 1st pin is a 12V DC voltage (DC12VB), and the 3rd pin is a ground terminal. The 2nd pin is an input terminal for the sense signal SENSv5 from the connected position detection switch.

[0389] The connector CN3L is connected to another position detection switch of a movable object (not shown). The 1st pin is a 12V DC voltage (DC12VB), and the 3rd pin is a ground terminal. The 2nd pin is an input terminal for the sense signal SENSv6 from the connected position detection switch.

[0390] Connector CN4L has the transmission line end of transmission line H23 connected thereto for connection to relay substrate 760 shown in Fig. 11. It has a configuration of 14 terminals from the first pin to the fourteenth pin, marked with numbers "1" to "14".

[0391] The first pin, the second pin, and the third pin are terminals to which a 12V DC voltage (DC12VB) is applied. The twelfth pin, the thirteenth pin, and the fourteenth pin are terminals to which a 5V DC voltage (DC5V) is applied. The fourth pin, the fifth pin, the seventh pin, the eighth pin, the tenth pin, and the eleventh pin are connected to ground. The sixth pin is the terminal for clock signal CLK_C, and the ninth pin is the terminal for data signal DATA_C. Connector CN4L has a flexible cable (e.g., a flexible flat cable) connected thereto as transmission line H23. Since the flexible cable has a small rated current, the number of power supply terminals and ground terminals is made larger than that of connector CN1L.

[0392] Connector CN5L is connected to a motor of a movable object (not shown). The third pin and the fourth pin are terminals to which an 18V motor drive voltage (MOT18V) is applied. The first pin is the terminal for motor drive signal MOT5- / 2, the second pin is the terminal for motor drive signal MOT5- / 1, the fifth pin is the terminal for motor drive signal MOT5-2, and the sixth pin is the terminal for motor drive signal MOT5-1.

[0393] Connector CN6L is connected to an LED substrate of a movable object (not shown). The first pin and the second pin are terminals to which a 12V DC voltage (DC12VB) is applied. The third pin to the twenty-fourth pin are the terminals for 22 systems of light emission drive currents from light emission drive currents 09-R1, 09-G1, 09-B1 ··· 09-R8, 09-G8.

[0394] The decorative substrate 740 is equipped with a buffer circuit 741 which is a triple buffer gate. As the power supply voltage for this, a 5V DC voltage (DC5V) is used. The 5V DC voltage (DC5V) is supplied from the 6th pin of the connector CN1L.

[0395] Also, an LED driver 742 is mounted. As the power supply voltage for this, a 12V DC voltage (DC12VB) is used. The 12V DC voltage (DC12VB) is supplied from the 8th and 9th pins of the connector CN1L.

[0396] Note that the 18V motor drive voltage (MOT18V) supplied from the connector CN5L to the downstream side is obtained from the 11th to 14th pins of the connector CN1L.

[0397] The flow of various signals in the decorative substrate 740 will be described. The clock signal CLK_C and the data signal DATA_C supplied from the upstream backside left relay board 720 to the connector CN1L are input to the buffer circuit 741 and subjected to buffer processing. Then they are sent to the connector CN4L and transmitted to the downstream relay board 760.

[0398] Also, the clock signal CLK_C and the data signal DATA_C are supplied to the LED driver 742 as well. The LED driver 742 performs 22 - system LED emission driving using the output terminals for the emission driving current LEDR1, LEDG1, LEDB1 ··· LEDR7, LEDG7, LEDR8, LEDG8. These output terminals LEDR1, LEDG1, LEDB1 ··· LEDR7, LEDG7, LEDR8, LEDG8 are connected to the 3rd to 24th pins of the connector CN6L, and are configured to supply an emission driving current (09 - R1, 09 - G1, 09 - B1 ··· 09 - R6, 09 - G6, 09 - B6) to the 22 - system LED circuits on the LED substrate of a movable object (not shown).

[0399] As described above, the decorative substrate 740 has the following configuration. · Transfer the clock signal CLK_C and the data signal DATA_C transmitted from the upstream to the downstream via the buffer circuit 703. · The clock signal CLK and the data signal DATA are also used by the LED driver 742. The LED driver 742 drives the light emission of the light emitting parts of other LED substrates.

[0400] · Receive the 12V DC voltage (DC12VB) and the 5V DC voltage (DC5V) through the connector CN1L and use them as the operating power supply. · Supply the 12V DC voltage (DC12VB) and the 18V motor drive voltage (MOT18VB) to the downstream as the operating power supply voltage.

[0401] In addition to the above-mentioned components, on the decorative substrate 740, as shown in FIG. 43, electronic elements such as resistors R1L, R2L ···, capacitors C1L, C2L ··· are connected to the required locations. Also, as shown in the figure, taps TP1L and TP2L are provided and used for connection to the required locations.

[0402] [5.13 Relay Substrate 760] The configuration of the relay substrate 760 is shown in FIG. 44. Connectors CN1M, CN2M, and CN3M are mounted on the relay substrate 760.

[0403] The connector CN1M is connected to the transmission line end of the transmission line H23 that connects to the connector CN4L of the decorative substrate 740 in FIG. 43. Therefore, this connector CN1M has a 14-terminal configuration from the first pin to the fourteenth pin as numbered "1" to "14", and the terminal assignment is the same as that of the above-mentioned connector CN4L.

[0404] The connector CN2M is connected to an LED substrate (not shown). The fourth pin and the sixth pin are ground terminals. The fifth pin is the terminal for the 5V DC voltage (DC5V). The first pin is the terminal for the 12V DC voltage (DC12VB). The second pin is the terminal of the clock signal CLK, and the third pin is the terminal of the data signal DATA.

[0405] The connector CN3M is connected to the transmission line end of the transmission line H24 that connects to the downstream LED substrate 780. This connector CN1B has a six-terminal configuration from the first pin to the sixth pin as numbered "1" to "6". The fourth pin and the sixth pin are ground terminals. The fifth pin is the terminal of the 5V DC voltage (DC5V). The first pin is the terminal of the 12V DC voltage (DC12VB). The second pin is the terminal of the clock signal CLK, and the third pin is the terminal of the data signal DATA.

[0406] Note that the conductor points P1 and P2 in the housings of the connectors CN1M, CN2M, and CN3M are connected to the ground for mounting strength.

[0407] This relay substrate 760 is mounted with a buffer circuit 761 which is a Schmitt trigger buffer with a CMOS8 circuit, similar to the buffer circuit 402 in FIG. 13. As the power supply voltage for this, a 5V DC voltage (DC5V) is used. The 5V DC voltage (DC5V) is supplied from the 12th pin, 13th pin, and 14th pin of the connector CN1M.

[0408] The clock signal CLK_C and the data signal DATA_C supplied from the upstream decorative substrate 740 to the connector CN1M are input to the A1 terminal and A2 terminal of the buffer circuit 761, and the signals are compensated. Then they are output from the Y1 terminal and Y2 terminal, and transmitted downstream as the clock signal CLK and the data signal DATA by the connector CN2M. Also, the clock signal CLK_C and the data signal DATA_C are input to the A5 terminal and A6 terminal of the buffer circuit 761, and the signals are compensated. Then they are output from the Y5 terminal and Y6 terminal, and transmitted to the downstream LED substrate 780 as the clock signal CLK and the data signal DATA by the connector CN3M.

[0409] Therefore, the decorative substrate 740 buffers the clock signal CLK_C and the data signal DATA_C, and then transmits them to the two downstream LED substrates (LED substrate 780 and an LED substrate not shown).

[0410] [5.14 LED Substrate 780] The LED substrate 780 is disposed within a movable body (not shown), and is a substrate that causes the LEDs in the movable body portion to emit light. The configuration of the LED substrate 780 is shown in FIG. 45. Connectors CN1N and CN2N are mounted on the LED substrate 780.

[0411] The connector CN1N is connected to the transmission line end of a transmission line H24 that connects to the connector CN3M of the relay substrate 760 in FIG. 44. Therefore, this connector CN1N has a six-terminal configuration from the first pin to the sixth pin as if numbered "1" to "6", and the terminal assignment is the same as that of the above-described connector CN3M.

[0412] The connector CN2N is connected to the LED substrate 790. The first pin is a terminal for a 12V DC voltage (DC12VB). The fourth pin is a ground terminal. The second pin is a terminal for the clock signal CLK, and the third pin is a terminal for the data signal DATA.

[0413] Note that the conductor points P1 and P2 in the housings of the connectors CN1N and CN2N are connected to ground for mounting strength.

[0414] A buffer circuit 781, which is a triple buffer gate, is mounted on the LED substrate 780. As the power supply voltage for this, a 5V DC voltage (DC5V) is used. The 5V DC voltage (DC5V) is supplied from the fifth pin of the connector CN1N.

[0415] An LED driver 782 is also mounted, and a 12V DC voltage (DC12VB) is used as the power supply voltage for this. The 12V DC voltage (DC12VB) is supplied from the first pin of the connector CN1N.

[0416] The flow of various signals in the LED substrate 780 will be described. The clock signal CLK and data signal DATA supplied from the upstream relay substrate 760 to the connector CN1N are input to the buffer circuit 781 and subjected to buffer processing. Then, they are sent to the connector CN2N and transmitted to the downstream LED substrate 790.

[0417] Also, the clock signal CLK and data signal DATA are supplied to the LED driver 782. The LED driver 782 performs 22-channel LED emission driving using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR7, LEDG7, LEDB7, LEDR8 for the emission driving current. These output terminals LEDR1, LEDG1, LEDB1 ··· LEDR7, LEDG7, LEDB7, LEDR8 are connected to each of the 22-channel LED circuits formed as the light emitting unit 783, and an emission driving current (03-R1, 03-G1, 03-B1 ··· 03-G7, 03-B7, 03-R8) flows through them. Each channel of the LED circuit in the light emitting unit 783 is composed of a series connection of two or three LEDs (LED1, LED2 ···) and a resistance element as shown in the figure. Each channel of the LED circuit is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side.

[0418] As described above, the LED substrate 780 has the following configuration. · Transfer the clock signal CLK and data signal DATA transmitted from the upstream to the downstream via the buffer circuit 781. · The clock signal CLK and data signal DATA are also used by the LED driver 782 to drive the light emission of the light emitting unit 783.

[0419] · The connector CN1N receives a 12V DC voltage (DC12VB) and a 5V DC voltage (DC5V) and uses them as the operating power supply. · It supplies the 12V DC voltage (DC12VB) as the operating power supply voltage to the downstream side.

[0420] In addition to those mentioned above, on the LED board 780, as shown in FIG. 45, electronic elements such as resistors R1N, R2N ···, capacitors C1N, C2N ··· are connected to the required locations. Also, as shown in the figure, taps TP1N and TP2N are provided and used for connection to the required locations.

[0421] [5.15 LED board 790] The LED board 790 is arranged inside a movable body (not shown) and is a board for performing LED emission of the movable body part. The configuration of the LED board 790 is shown in FIG. 46. A connector CN1X is mounted on the LED board 790.

[0422] The connector CN1X is connected to the transmission line end of the transmission line H25 that connects to the connector CN2N of the LED board 780 in FIG. 45. Therefore, this connector CN1X has a 4 - terminal configuration from the first pin to the fourth pin as numbered "1" to "4", and the terminal assignment is the same as that of the above - mentioned connector CN2N.

[0423] Note that the conductor points P1 and P2 in the housing of the connector CN1X are connected to the ground for mounting strength.

[0424] An LED driver 791 is mounted on the LED board 790. A 12V DC voltage (DC12VB) is used as the power supply voltage for the LED driver 791. The 12V DC voltage (DC12VB) is supplied from the first pin of the connector CN1X.

[0425] The flow of various signals in the LED board 790 will be described. The clock signal CLK and data signal DATA supplied from the upstream LED substrate 780 to the connector CN1X are supplied to the LED driver 791. The LED driver 791 performs 16-channel LED emission driving using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR5, LEDG5, LEDB5, LEDR6 for the emission driving current. These output terminals LEDR1, LEDG1, LEDB1 ··· LEDR5, LEDG5, LEDB5, LEDR6 are connected to each of the 16-channel LED circuits formed as the light emitting unit 792, and pass the emission driving current (02-R1, 02-G1, 02-B1 ··· 02-G5, 02-B5, 02-R6). Each channel of the LED circuit of the light emitting unit 792 is composed of a series connection of two or three LEDs (LED1, LED2 ···) and a resistor element as shown in the figure. Each channel of the LED circuit is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side.

[0426] The above LED substrate 790 has the following configuration. · Use the clock signal CLK and data signal DATA transmitted from the upstream in the LED driver 791 to drive the light emission of the light emitting unit 792.

[0427] · Receive a 12V DC voltage (DC12VB) through the connector CN1X and use it as the operating power supply.

[0428] In addition to what has been mentioned above, in the LED substrate 790, as shown in Fig. 46, electronic elements such as resistors R1X, R2X ···, capacitors C1X, C2X ··· are connected to the required locations. Also, taps TP1X, TP2X are provided as shown in the figure and are used for connection to the required locations.

[0429] The LED substrate 790 is equipped with an LED driver 791 and a light-emitting unit 792, but no buffer circuit is installed. Therefore, only a 12V DC voltage (DC12VB) is supplied from the connector CN2N of the LED substrate 780 to the connector CN1X of the LED substrate 790, and the 5V DC voltage (DC5V) is not supplied. That is, the 5V DC voltage (DC5V) is supplied to the LED substrate 780 provided with a buffer circuit based on the 5V DC voltage (DC5VB) from the effect control board 30 (refer to the 4th and 6th pins of the connector CN1J in Fig. 36).

[0430] [5.16 Under-board middle relay board 800] The configuration of the under-board middle relay board 800 is shown in Fig. 47. Connectors CN1Q, CN2Q, CN3Q, and CN4Q are mounted on the under-board middle relay board 800.

[0431] The connector CN1Q is connected to the transmission line end of the transmission line H30 that connects to the connector CN11J of the LED connection board 700 in Fig. 40. Therefore, this connector CN1Q has a 16-terminal configuration from the 1st pin to the 16th pin as numbered "1" to "16", and the terminal assignment is the same as that of the above-mentioned connector CN11J.

[0432] The connector CN2Q is connected to the movable object motor. The 3rd and 4th pins are the terminals to which a 12V motor drive voltage (MOT12V) is applied. The 1st pin is the motor drive signal MOT4- / 2, the 2nd pin is the motor drive signal MOT4- / 1, the 5th pin is the motor drive signal MOT4-2, and the 6th pin is the terminal of each of the motor drive signals MOT4-1.

[0433] The connector CN3Q is connected to the transmission line end of the transmission line H31 that connects to the downstream decorative board 820. This connector CN3Q has a 10-terminal configuration from the 1st pin to the 10th pin as numbered "1" to "10". Pins 1 to 6 are terminals for a 12V DC voltage (DC12VB). Pins 7, 8, 9, and 10 are terminals for the light emission drive currents 13 - B7, 13 - R8, 13 - G8, and 13 - B8. This connector CN3Q is connected as a transmission line H31 to a flexible cable (for example, a flexible flat cable). Since the rated current is small, it has more power supply terminals than other connectors. For example, the number of terminals for the 12V DC voltage (DC12VB) of connector CN3Q (6) is more than the number of terminals for the 12V DC voltage (DC12VB) of connector CN1Q (2).

[0434] Connector CN4Q is connected to the position detection switch. Pin 1 is for a 12V DC voltage (DC12VB), and Pin 2 is for ground. Pin 3 is the input terminal for the sense signal SENSv7 from the connected position detection switch.

[0435] Note that the conductor points P1 and P2 in the housings of connectors CN1Q, CN2Q, CN3Q, and CN4Q are connected to ground for mounting strength.

[0436] On this back - side lower relay board 800, the signals and voltages supplied by connector CN1Q are distributed downstream by connectors CN2Q, CN3Q, and CN4Q. In connector CN1Q, a 12V DC voltage (DC12VB) is input at two terminals, Pins 4 and 6. However, in connector CN3Q, the 12V DC voltage (DC12VB) is transmitted downstream at six terminals from Pin 1 to Pin 6. As a result, the number of terminals downstream (the total number of terminals of connectors CN2Q, CN3Q, and CN4Q) is more than the number of terminals upstream (the number of terminals of connector CN1Q).

[0437] [5.17 Decorative board 820] The decorative board 820 will be described with reference to FIG. 48. Connector CN1S is mounted on the decorative board 820. The connector CN1S has the transmission line end of the transmission line H31 connected thereto, which connects between the connector CN1S and the connector CN3Q on the backside lower middle relay board 800 in Fig. 47. Therefore, this connector CN1S has a configuration of 10 terminals from the first pin to the tenth pin as numbered from "1" to "10", and the terminal assignment is the same as that of the above-mentioned connector CN3Q.

[0438] The decorative board 820 is provided with a light-emitting part 821 having four systems of LED circuits, and is light-emittingly driven by the light-emitting drive currents 13 - B7, 13 - R8, 13 - G8, and 13 - B8 via the connector CN1S respectively. The anode side of the LED of the light-emitting part 821 has a 12V DC voltage (DC12VB) applied thereto via the connector CN1S. This decorative board 820 is arranged inside a movable body (not shown), and is a board for performing LED light emission of the movable body part.

[0439] Here, the light-emitting part 821 has nine LED chips as shown enclosed by a broken line as LED1, LED2 ··· LED9. As can be seen from the figure, each LED chip is a full-color LED chip that emits light in each of the colors R, G, and B. Note that "GA", "RA", and "BA" in the figure respectively mean the anode of the green LED, the anode of the red LED, and the anode of the blue LED in the full-color LED chip.

[0440] In this decorative board 820, according to the production specifications, it is designed to emit light in two colors, red and green. In this case, instead of using single-color red LED chips and green LED chips, full-color LED chips are used. And as shown in the figure, the series circuit of the blue LED not used in the full-color LED chip has both the anode side and the cathode side connected to the line of the 12V DC voltage (DC12VB), and is configured such that no light-emitting drive current flows. For example, in the series circuit of LED1, LED2, and LED3, three blue LEDs are connected in series, and the anode side and the cathode side of the series circuit are connected to the line of the 12V DC voltage (DC12VB).

[0441] In the case of this configuration, it is possible to reduce the cost by arranging one full-color LED chip instead of usually using two single-color LED chips in red and green. Also, assuming that a light-emitting drive current terminal is connected to each of the three terminals of R, G, and B in the full-color LED chip, the number of terminals (pin numbers) of the connector CN1S increases, and the number of light-emitting drive current terminals used in the LED driver also increases. For this reason, as described above, the light-emitting drive current is not supplied to the unused blue LED. This simplifies the connector configuration, the configuration of the LED driver, and also the wiring, resulting in cost reduction.

[0442] Also, if the terminals (BA) of the unused color are left unconnected, there is a possibility of unintended light emission due to noise or the like. Therefore, the anode side and the cathode side are connected to the 12V DC voltage (DC12VB) line to prevent unintended light emission.

[0443] Note that the unused terminals (anode / cathode of the blue LED) in the full-color LED chip may be left unconnected. Also, if there is a ground on the substrate, the ground may be connected to both ends of the unused terminals in the full-color LED chip.

[0444] Also, in the decorative substrate 820 of FIG. 48, resistors R1S, R3S, and R5S are connected to the green LED system in the full-color LED chip, and resistors R2S, R4S, and R6S are connected to the red LED system. However, since no current flows through the terminals (BA) of the unused blue LED, no resistor is connected to the blue LED system. This also promotes circuit simplification and cost reduction.

[0445] <6. Other Examples of the Connection Configuration of the Substrate> [6.1 Connection Status of Each Substrate] Here, an example alternative to the connection configuration of FIG. 11 is shown in FIG. 49. In FIG. 49, the same blocks as those in FIG. 11 are denoted by the same reference numerals, and the description thereof is omitted. The example of FIG. 49 is an example in which an LED connection board 1500 is used instead of the LED connection board 700 on the game board 3 side of FIG. 11.

[0446] The LED connection board 1500 is connected by a transmission line H50 downstream of the effect control board 30. Then, the LED connection board 1500 performs various necessary signal processes for light emission driving of effect means such as LEDs and motors on the game board 3 based on the control signal from the effect control board 30.

[0447] In FIG. 49, an LED board 1600 is illustrated as being downstream of the LED connection board 1500. The LED board 1600 may be connected from the LED connection board 1500 via a relay board or other LED boards (not shown), or may be directly connected to the LED connection board 1500. In FIG. 49, the LED board 1600 is taken as an example of one of a plurality of boards connected to the downstream side of the LED connection board 1500. In the configuration of FIG. 49, it is also conceivable that each board from the back left relay board 720 to the LED board 790 shown in FIG. 11, and each board of the back lower relay board 800 and the decorative board 820 are connected in parallel with the LED board 1600 downstream of the LED connection board 1500.

[0448] [6.2 LED Connection Board 1500] The LED connection board 1500 will be described with reference to FIGS. 50, 51, 52, 53, 54, 55, 56, and 57. These figures separately show the circuit configurations provided on the LED connection board 1500.

[0449] Connectors such as the connectors CN1V, CN2V, and CN3V in FIG. 50, the connectors CN4V to CN8V in FIG. 51, the connectors CN9V to CN16V in FIG. 52 or FIG. 53, the connectors CN17V to CN20V in FIG. 54, the connectors CN21V to CN25V in FIG. 57, and the connectors CN26V to CN28V in FIG. 56 are mounted on the LED connection board 1500 as connectors.

[0450] The connector CN1V in FIG. 50 has the transmission line end of the transmission line H50 connected thereto for connection to the production control board 30 as shown in FIG. 49. This connector CN1V has a configuration of 40 terminals from the first pin to the fortieth pin, as numbered "1" to "40".

[0451] The first pin, second pin, eighth pin, ninth pin, tenth pin, sixteenth pin, eighteenth pin, nineteenth pin, twentieth pin, twenty-second pin, twenty-ninth pin, thirty-second pin, thirty-third pin, thirty-fourth pin, thirty-ninth pin, and fortieth pin of the connector CN1V are connected to ground. The fourth pin and sixth pin are terminals for a 5V DC voltage (DC5VB). The twelfth pin, fourteenth pin, twenty-fourth pin, twenty-sixth pin, twenty-eighth pin, and thirtieth pin are terminals for a 12V DC voltage (DC12VB). The thirty-sixth pin and thirty-eighth pin are terminals for a 35V DC voltage (DC35V). The seventeenth pin is unused.

[0452] The third pin is the clock signal LSI_SCK for the LSI as the motor driver control unit 1530 in FIG. 55, the fifth pin is the slave select signal LSI_SS of the SPI bus for the above LSI, the seventh pin is the serial data signal LSI_MOSI for the above LSI, the eleventh pin is the hardware reset signal LSI_RESET for the above LSI, and the thirty-fifth pin is assigned as each terminal of the serial data signal LSI_MISO output from the above LSI. The clock signal LSI_SCK and the serial data signal LSI_MOSI are signals transmitted from the production control board 30 for motor drive control. The serial data signal LSI_MISO is the serial data transmitted from this LED connection board 1500 to the upstream production control board 30.

[0453] The thirteenth pin is assigned as the terminal of the clock signal CLK_P, and the fifteenth pin is assigned as the terminal of the serial data signal DATA_P. Pin 31 is assigned as the terminal of the load signal S_IN_LOAD. The load signal S_IN_LOAD is a signal used for P / S conversion.

[0454] The clock signal CLK_P and the serial data signal DATA_P are branched into the following four systems by the buffer circuit 1502 after passing through the buffer circuit 1501. The clock signal CLK_A and the serial data signal DATA_A The clock signal CLK_B and the serial data signal DATA_B The clock signal CLK_C and the serial data signal DATA_C The clock signal CLK_D and the serial data signal DATA_D

[0455] The clock signal CLK_A and the serial data signal DATA_A are supplied as signals for effect control to the LED drivers 1510 and 1511 in FIG. 52. The clock signal CLK_B and the serial data signal DATA_B are supplied as signals for effect control to the LED drivers 1520, 1521, and 1522 in FIGS. 53 and 54.

[0456] The clock signal CLK_C and the serial data signal DATA_C are signals for effect control to be transmitted to the effect driving means on the downstream substrate, and are transmitted from the connector CN2V in FIG. 50 to the downstream substrate. The clock signal CLK_D and the serial data signal DATA_D are signals for effect control to be transmitted to the effect driving means on the downstream substrate, and are transmitted from the connector CN3V to the downstream substrate.

[0457] Pin 21 of the connector CN1V in FIG. 50 is assigned as the terminal of the reset signal RESET_M, pin 23 is assigned as the terminal of the clock signal CLK_M / S, pin 25 is assigned as the terminal of the serial data signal DATA_M, and pin 27 is assigned as the terminal of the latch signal LATCH_M. The reset signal RESET_M, the clock signal CLK_M / S, the serial data signal DATA_M, and the latch signal LATCH_M are signals used in the motor driver 1505 of FIG. 51. The clock signal CLK_M / S is supplied to the motor driver 1505 as the clock signal CLK_M via the buffer circuit 1503 of FIG. 50.

[0458] The 37th pin of the connector CN1V is assigned as the terminal of the serial data signal S_IN_DATA. The serial data signal S_IN_DATA is serial data transmitted from this LED connection board 1500 to the effect control board 30. For the output of the serial data signal S_IN_DATA, the clock signal CLK_M / S is supplied to the P / S conversion circuit 1504 as the clock signal S_IN_CLK via the buffer circuit 1503.

[0459] Note that the conductor points P1 and P2 in the housings of the connector CN1V and other connectors CN2V to CN28V are connected to the ground for mounting strength.

[0460] The connector CN2V in FIG. 50 is a connector connected to the downstream board. The 4th pin, 6th pin, and 8th pin of the connector CN2V are connected to the ground. The 1st pin is used as the terminal of the 12V DC voltage (DC12VB). The 2nd pin is used as the terminal of the 5V DC voltage (DC5VB). The 3rd pin is used as the terminal of the clock signal CLK (CLK_C). The 5th pin is used as the terminal of the serial data signal DATA (DATA_C). The 7th pin is used as the terminal to which the sense signal +P0x from the downstream side is input. The 9th pin, 10th pin, 11th pin, and 12th pin are used as the terminals of the motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+.

[0461] Connector CN3V is also a connector connected to the downstream substrate, and is provided with terminals for 12V DC voltage (DC12VB), serial data signal DATA (DATA_D), clock signal CLK (CLK_D), and ground.

[0462] The connector CN4V in Fig. 51 is connected to a motor of a movable object (not shown). A 12V DC voltage (MOT12V) serving as the power supply voltage of the motor is applied to the third pin. And terminals for motor drive signals MOT1- / 2, MOT1- / 1, MOT1- / 2, MOT1-1 are provided. Connectors CN6V, CN7V, and CN8V are connectors to which sense signals SENS0, SENS1, and SENS2 are input from various sensors, respectively.

[0463] The connectors CN9V~CN16V in Fig. 52 or Fig. 53 are connectors connected to the downstream LED substrate (not shown). These are each provided with terminals for outputting a light emission drive current to the corresponding LED substrate. The connectors CN17V~CN20V in Fig. 54 are also connectors connected to the downstream LED substrate (not shown). These are each provided with terminals for outputting a light emission drive current to the corresponding LED substrate.

[0464] The connectors CN21V~CN25V in Fig. 57 are connectors to which sense signals sense signal +P0y, +P0z, +P0u, +P1z, +P1u are input from various sensors, respectively. The connectors CN26V~CN28V in Fig. 56 are connectors connected to the downstream motor (not shown), respectively. Connector CN26V is provided with terminals for motor drive signals MOTuA+, MOTuB-, MOTuA-, MOTuB+. Connector CN27V is provided with terminals for motor drive signals MOTzB+, MOTzA-, MOTzB-, MOTzA+. Connector CN28V is provided with terminals for motor drive signals MOTyB+, MOTyA-, MOTyB-, MOTyA+.

[0465] The power supply voltage of this LED connection board 1500 will be described. On the LED connection board 1500, as ICs, buffer circuits 1501, 1502, 1503 with eight circuits, which are the same as the buffer circuit 402 described in FIG. 13, and the buffer circuit 1540 in FIG. 57 are mounted. Also, the P / S conversion circuit 1504 in FIG. 50 is mounted. As the power supply voltage for these, a 5V DC voltage (DC5V) based on the 5V DC voltage (DC5VB) from the connector CN1V is used. The 5V DC voltage (DC5VB) is taken out from the positive electrode side of the capacitor C3V via the fuse F1J from the connector CN1V. Note that the P / S conversion circuit 1504 is the same IC as the P / S conversion circuit 505 in FIG. 18.

[0466] Also, on the LED connection board 1500, as an IC, the motor driver 1505 in FIG. 51 is mounted, and as the power supply voltage for this, a 12V motor drive voltage (MOT12V) and a 12V DC voltage (DC12VS) are used.

[0467] The 12V motor drive voltage (MOT12V) and the 12V DC voltage (DC12VS) are separated from the 12V DC voltage (DC12VB) by the power supply separation / protection circuits 1551 and 1552 shown in FIG. 51.

[0468] Also, on the LED connection board 1500, as an IC, the motor driver control unit 1530 in FIG. 55 is mounted, and as the power supply voltage for this, a 5V motor drive voltage (DC5V) is used.

[0469] In addition, on the LED connection board 1500, as stepping motor drivers, the motor driver 1532 in FIG. 55 and the motor drivers 1533, 1534, 1535 in FIG. 56 are mounted. As the power supply voltages for these, 35V motor drive voltages (MOT35Vx)(MOT35Vy)(MOT35Vz)(MOT35Vu), 5V DC voltage (DC5V), voltage VCCx, voltage VCCy, voltage VCCz, and voltage VCCu are used.

[0470] The 35V motor drive voltages (MOT35Vx)(MOT35Vy)(MOT35Vz)(MOT35Vu) are separated from the 35V DC voltage (DC35V) by the power supply separation / protection circuit 1553 shown in FIG. 57. The voltages VCCx, VCCy, VCCz, and VCCu are the voltages obtained from the 34th terminals (monitor terminals of the internal regulator) of the motor drivers 1532, 1533, 1534, and 1535, respectively.

[0471] In addition, on the LED connection board 1500, as ICs, the LED drivers 1510, 1511, 1520, 1521, 1522 shown in FIGS. 52, 53, and 54 are mounted, and as the power supply voltage for these, 12V DC voltage (DC12VB) is used.

[0472] The flow of various signals on the LED connection board 1500 will be described below. From the effect control board 30 to the connector CN1V in FIG. 50, the clock signal LSI_SCK, the serial data signal LSI_MOSI, the slave selection signal LSI_SS, and the hardware reset signal LSI_RESET are transmitted from the effect control board 30 for motor drive control.

[0473] After these signals are compensated by the buffer circuit 1501, they are supplied to the motor driver control unit 1530 in FIG. 55 via the chip resistors RA1V or RA2V. The motor driver control unit 1530 controls the motor drivers 1532, 1533, 1534, 1535 based on the clock signal LSI_SCK and the serial data signal LSI_MOSI.

[0474] Specifically, the motor driver control unit 1530 outputs the X-axis output pulses OUTx, DIRx, and P3x to the motor driver 1532. In response thereto, the motor driver 1532 generates motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+ and supplies them to the connector CN2V in FIG. 50.

[0475] Also, the motor driver control unit 1530 outputs the Y-axis output pulses OUTy, DIRy, and P3y to the motor driver 1533 in FIG. 56. Note that the connections between FIGS. 55 and 56 are indicated by "c2", "c3", and "c4". The motor driver 1533 generates motor drive signals MOTyB+, MOTyA-, MOTyB-, and MOTyA+ in response to the Y-axis output pulses OUTy, DIRy, and P3y and supplies them to the connector CN28V. Also, the motor driver control unit 1530 outputs the Z-axis output pulses OUTz, DIRz, and P3z to the motor driver 1534. In response thereto, the motor driver 1534 generates motor drive signals MOTzB+, MOTzA-, MOTzB-, and MOTzA+ and supplies them to the connector CN27V. Also, the motor driver control unit 1530 outputs the U-axis output pulses OUTu, DIRu, and P3u to the motor driver 1535. In response thereto, the motor driver 1534 generates motor drive signals MOTuA+, MOTuB-, MOTuA-, and MOTuB+ and supplies them to the connector CN26V.

[0476] The connectors CN26V, CN27V, and CN28V are connected to a movable object motor (not shown). Also, the connector CN2V in FIG. 50 is connected to a downstream substrate, and the motor drive signals MOTxA+, MOTxB-, MOTxA-, and MOTxB+ from the motor driver 1532 are supplied to a movable object motor (not shown) via the downstream substrate. Therefore, the motor driver control unit 1530 in FIG. 55 has a function of driving these movable object motors based on the clock signal LSI_SCK and the serial data signal LSI_MOSI.

[0477] Sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u from various sensors input from the connector CN2V in FIG. 50 and the connectors CN21V to CN25V in FIG. 57 are input to the motor driver control unit 1530 via the buffer circuit 1540. The sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u are signals for detecting the positions of the respective movable bodies. Note that the connection between FIG. 55 and FIG. 57 is indicated by "c1". The motor driver control unit 1530 serializes these sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u and outputs them as the serial data signal LSI_MISO. That is, the motor driver control unit 1530 also functions as a P / S conversion circuit. The serial data signal LSI_MISO obtained by the motor driver control unit 1530 is signal-compensated by the buffer circuit 1501 in FIG. 50 and supplied to the connector CN1V.

[0478] Sense signals SENS0, SENS1, SENS2 are input from the connectors CN6V, CN7V, CN8V in FIG. 51. These sense signals SENS0, SENS1, SENS2 are also signals for detecting the positions of the respective movable bodies. They may also be signals from a motion sensor for detecting the operation of the player and a proximity sensor for detecting a game ball. The input sense signals SENS0, SENS1, SENS2 are input to the P / S conversion circuit 1504 in FIG. 50 and converted into the serial data signal S_IN_DATA. This serial data signal S_IN_DATA is signal-compensated by the buffer circuit 1503 and supplied to the connector CN1V. These serial data signals, the serial data signal LSI_MISO and the serial data signal S_IN_DATA, will be transmitted to the production control board 30 as signals obtained by serializing the detection signals of various sensors.

[0479] The clock signal CLK_P and the serial data signal DATA_P input from the connector CN1V are compensated for signals by the buffer circuit 1501 and then supplied to the buffer circuit 1502 via the chip resistor RA2V. As described above, the clock signal CLK_P and the serial data signal DATA_P are compensated for signals by the buffer circuit 1502 and branched into four systems. Among them, two systems, the clock signal CLK_C and the serial data signal DATA_C, and the clock signal CLK_D and the serial data signal DATA_D are transmitted to the downstream board from the connectors CN2V and CN3V, respectively.

[0480] The clock signal CLK_A and the serial data signal DATA_A from the buffer circuit 1502 are supplied to the LED drivers 1510 and 1511 in FIG. 52.

[0481] Based on the clock signal CLK_A and the serial data signal DATA_A, the LED driver 1511 performs 20-channel LED emission driving using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR6, LEDG6, LEDB6 and the output terminals LEDR8, LEDG8 for the emission driving current.

[0482] Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR3, LEDG3, LEDB3 are connected to the second pin to the tenth pin of the connector CN10V, and are configured to supply the emission driving current (08-R1, 08-G1, 08-B1 ··· 08-R3, 08-G3, 08-B3) to the nine-channel LED circuits on the LED board (not shown). The output terminals LEDR4, LEDG4, LEDB4 ··· LEDR6, LEDG6, LEDB6 are connected to the second to tenth pins of the connector CN14V, and are configured to supply light-emitting drive currents (08-R4, 08-G4, 08-B4 ··· 08-R6, 08-G6, 08-B6) to nine LED circuits on an LED substrate (not shown).

[0483] Note that the first pin of each of the connectors CN10V and CN14V is a pin for supplying a 5V DC voltage (DC5V) to the downstream LED substrate.

[0484] Based on the clock signal CLK_A and the serial data signal DATA_A, the LED driver 1510 performs 21-channel LED light-emitting drive using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR7, LEDG7, LEDB7 of the light-emitting drive current.

[0485] Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR4, LEDG4, LEDB4 are connected to the second to thirteenth pins of the connector CN9V, and are configured to supply light-emitting drive currents (07-R1, 07-G1, 07-B1 ··· 07-R4, 07-G4, 07-B4) to twelve LED circuits on an LED substrate (not shown). The output terminals LEDR5, LEDG5, LEDB5 ··· LEDR7, LEDG7, LEDB7 are connected to the second to tenth pins of the connector CN13V. The output terminals LEDR8 and LEDG8 of the LED driver 1511 are connected to the eleventh and twelfth pins. Thereby, it is configured to supply light-emitting drive currents (07-R5, 07-G5, 07-B5 ··· 07-R7, 07-G7, 07-B7, and 08-R8, 08-G8) to eleven LED circuits on an LED substrate (not shown). Note that the first pin of each of the connectors CN9V and CN13V is a pin for supplying a 12V DC voltage (DC12VB) to the downstream LED substrate.

[0486] The clock signal CLK_B and the serial data signal DATA_B from the buffer circuit 1502 in FIG. 50 are supplied to the LED drivers 1520, 1521, and 1522 in FIGS. 53 and 54.

[0487] Based on the clock signal CLK_B and the serial data signal DATA_B, the LED driver 1520 performs 24-channel LED emission driving using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 for the emission driving current.

[0488] Among these output terminals, the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR5, LEDG5, LEDB5 are connected to any of the second to sixteenth pins of the connector CN12V, and are configured to supply an emission driving current (09-R1 ··· 09-B5) to 15-channel LED circuits on an LED substrate (not shown). Also, the output terminals LEDR6, LEDG6, LEDB6 ··· LEDR8, LEDG8, LEDB8 are connected to the second to tenth pins of the connector CN16V, and are configured to supply an emission driving current (09-R6, 09-G6, 09-B6 ··· 09-R8, 09-G8, 09-B8) to 9-channel LED circuits on an LED substrate (not shown).

[0489] Note that the first pin of each of the connectors CN12V and CN16V is a pin for supplying a 12V DC voltage (DC12VB) to the downstream LED substrate. A fuse F6V is connected to the first pin of the connector CN16V.

[0490] Based on the clock signal CLK_B and the serial data signal DATA_B, the LED driver 1521 performs 24-channel LED emission driving using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR8, LEDG8, LEDB8 for the emission driving current.

[0491] Among these output terminals, output terminals LEDR1, LEDG1, LEDB1 ··· LEDR5, LEDG5, LEDB5 are connected to any of the second to sixteenth pins of connector CN11V, and configured to supply a light emission drive current (10-R1 ··· 10-B5) to 15 systems of LED circuits on an LED substrate (not shown). Also, output terminals LEDR6, LEDG6, LEDB6 ··· LEDR8, LEDG8, LEDB8 are connected to the second to tenth pins of connector CN15V, and configured to supply a light emission drive current (10-R6, 10-G6, 10-B6 ··· 10-R8, 10-G8, 10-B8) to 9 systems of LED circuits on an LED substrate (not shown).

[0492] Note that the first pin of each of connectors CN11V and CN15V is a pin for supplying a 12V DC voltage (DC12VB) to the downstream LED substrate. A fuse F5V is connected to the first pin of connector CN15V.

[0493] The LED driver 1522 in FIG. 54 performs 17 systems of LED light emission driving using the output terminals LEDR1 ··· LEDR4 of the light emission drive current and the output terminals LEDR5 ··· LEDR7 based on the clock signal CLK_B and the serial data signal DATA_B.

[0494] Output terminals LEDR1 ··· LEDR4 are connected to the second to eleventh pins of connector CN17V, and configured to supply a light emission drive current (11-R1 ··· 11-R4) to 10 systems of LED circuits on an LED substrate (not shown). Also, output terminals LEDR5, LEDG5, LEDB5 are connected to the second to fourth pins of connector CN19V, and configured to supply a light emission drive current (11-R5, 11-G5, 11-B5) to 3 systems of LED circuits on an LED substrate (not shown). Also, output terminals LEDR6, LEDG6, LEDB6 are connected to the second to fourth pins of connector CN20V, and configured to supply a light emission drive current (11-R6, 11-G6, 11-B6) to 3 systems of LED circuits on an LED substrate (not shown). The output terminal LEDR7 is connected to the second pin of the connector CN18V, and is configured to supply a light-emitting drive current (11-R7) to one system of LED circuits on an LED substrate (not shown).

[0495] Note that the first pins of the connectors CN17V, CN18V, CN19V, and CN20V are pins that supply a 12V DC voltage (DC12VB) to the downstream LED substrate.

[0496] The reset signal RESET_M, clock signal CLK_M / S (clock signal CLK_M), serial data signal DATA_M, and latch signal LATCH_M input from the connector CN1V in FIG. 50 are signal-compensated by the buffer circuit 1503 and then supplied to the motor driver 1505 in FIG. 51 via the chip resistor RA3V.

[0497] The motor driver 1505 generates motor drive signals MOT1- / 2, MOT1- / 1, MOT1- / 2, MOT1-1 based on the clock signal CLK_M and the serial data signal DATA_M, and supplies them to the connector CN4V. The connector CN4V is connected to a movable object motor (not shown). Therefore, the motor driver 1505 drives the movable object motor based on the clock signal CLK_M and the serial data signal DATA_M.

[0498] As described above, the LED connection board 1500 has the following configuration. · Serialize the sense signals SENS0, SENS1, SENS2 input from the downstream side by the P / S conversion circuit 1504, and transmit them as a serial data signal S_IN_DATA from the connector CN1V to the upstream side via the buffer circuit 1503. · Supply the sense signals +P0x, +P0y, +P0z, +P0u, +P1z, +P1u input from the downstream side to the motor driver control unit 1530 via the buffer circuit 1540 and serialize them. Transmit the serial data signal LSI_MISO from the connector CN1V to the upstream side via the buffer circuit 1501.

[0499] · Transfer the clock signals CLK_P (CLK_C, CLK_D) and serial data signals DATA_P (DATA_C, DATA_D) sent from the performance control board 30 to the downstream via the buffer circuits 1501 and 1502. · Supply the clock signals CLK_P (CLK_A, CLK_B) and serial data signals DATA_P (DATA_A, DATA_B) sent from the performance control board 30 to the LED drivers 1510, 1511, 1520, 1521, and 1522 to execute LED emission driving.

[0500] · Supply the clock signal LSI_SCK and serial data signal LSI_MOSI sent from the performance control board 30 to the motor driver control unit 1530 to execute motor driving. The driving method is bipolar type. · Supply the clock signal CLK_M and serial data signal DATA_M sent from the performance control board 30 to the motor driver 1505 to generate a motor drive signal and transmit it to the downstream motor / substrate. The driving method is unipolar type. Although there are a mixture of bipolar drive and unipolar drive as motor drive methods, bipolar drive with high torque is adopted for large moving bodies, and unipolar drive with low cost is adopted for small moving bodies, thereby achieving appropriate driving force and cost reduction.

[0501] · Receive 12V DC voltage (DC12VB), 5V DC voltage (DC5VB), and 35V DC voltage (DC35V) through the connector CN1V and use them as the operating power supply. · Supply 12V DC voltage (DC12VB) and 5V DC voltage (DC5V) to the downstream as the operating power supply voltage.

[0502] In the LED connection board 1500, including those mentioned above, as shown in FIGS. 50 to 57, resistors such as resistors R1V, R2V ···, chip resistors RA1V, RA2V ···, capacitors C1V, C2V ···, diodes (including Zener diodes and Schottky barrier diodes) D1V, D2V ···, fuses F1V, F2V ···, transistors (FETs) Q1V, Q2V ···, oscillators X1V and other electronic components are connected at required locations. Also, as shown in the figure, taps TP1V, TP2V ··· are provided and used for connection to required locations. Some of the capacitors C1V, C2V ··· are arranged between the power supply lines of DC 5V and DC 12V and the ground for reducing power supply noise and the like.

[0503] By the way, instead of receiving the 5V DC voltage (DC5VB) from the upstream board, for example, the 5V DC voltage (DC5VB) may be generated based on the 12V DC voltage (DC12VB).

[0504] [6.3 LED board 1600] The configuration of the LED board 1600 shown in FIG. 49 is shown in FIG. 58. A connector CN1W is mounted on the LED board 1600.

[0505] The connector CN1W is connected to the transmission line end of the transmission line that connects to the connector on the downstream board (not shown) of the above-mentioned LED connection board 1500.

[0506] This connector CN1W has a 7-terminal configuration from the first pin to the seventh pin with numbers "1" to "7" attached, and the terminal assignment is, in order from the first pin, a ground terminal, a terminal for the clock signal CLK, a ground terminal, a terminal for the 5V DC voltage (DC5V), a terminal for the serial data signal DATA, a terminal for the reset signal RESET, and a terminal for the 12V DC voltage (DC12VB).

[0507] Note that the conductor points P1 and P2 in the housing of the connector CN1W are connected to the ground for mounting strength.

[0508] An LED driver 1601 is mounted on the LED substrate 1600. A 12V DC voltage (DC12VB) is used as the power supply voltage for the LED driver 1601. The 12V DC voltage (DC12VB) is supplied from the 7th pin of the connector CN1W.

[0509] The flow of various signals in the LED substrate 1600 will be described. The clock signal CLK, data signal DATA, and reset signal RESET supplied from the upstream substrate to the connector CN1W are supplied to the LED driver 1601. The LED driver 1601 performs 15-channel LED emission driving using the output terminals LEDR1, LEDG1, LEDB1 ··· LEDR5, LEDG5, LEDB5 for the emission driving current. These output terminals LEDR1, LEDG1, LEDB1 ··· LEDR5, LEDG5, LEDB5 are connected to each of the 15-channel LED circuits formed as the light emitting unit 1602, and pass the emission driving current (20-R1, 20-G1, 20-B1 ··· 20-R5, 20-G5, 20-B5). Each channel of the LED circuit in the light emitting unit 1602 is composed of a series connection of two LEDs (LED1, LED2 ···) and a resistor element as shown in the figure. Each channel of the LED circuit is in parallel, and a 12V DC voltage (DC12VB) is applied to the anode side.

[0510] As described above, the LED substrate 780 has the following configuration. · Based on the clock signal CLK and data signal DATA transmitted from the upstream, the LED driver 1601 performs emission driving of the light emitting unit 1602.

[0511] · Receives a 12V DC voltage (DC12VB) through the connector CN1W and uses it as the operating power supply.

[0512] In the LED substrate 1600, in addition to those mentioned above, as shown in FIG. 58, electronic elements such as resistors R1W, R2W... and capacitors C1W, C2W... are connected to required locations. Also, taps TP1W, TP2W... are provided as shown in the figure and are used for connection to required locations.

[0513] <7. Description of the Notable Configuration> Hereinafter, the notable configurations among those of the gaming machine 1 described so far will be sequentially described.

[0514] [7.1 Relationship between the Connector Terminals and the Terminals of the Effect Driving Means] First, the relationship between the connector terminals on various substrates and the terminals of the effect driving means will be described. Note that the effect driving means is a general term for the circuit parts that drive effect devices, such as light emission driving means and motor driving means. Specifically, it is a general term for an LED driver, a motor driver, a driver control unit that controls these, and a circuit part that functions as an S / P conversion circuit for motor drive control. And in particular, the "terminals" of the effect driving means refer to the terminals of the chips that function as an LED driver, a motor driver, a driver control unit, an S / P conversion circuit, etc., which are mounted as chip components (IC chips).

[0515] The gaming machine 1 of the embodiment has the following (Configuration A1-1). (Configuration A1-1) The gaming machine 1 has a first effect driving means by chip components, and a first substrate provided with a first connector for inputting a clock and effect driving control data to the first effect driving means, a second effect driving means by chip components, and a second substrate provided with a second connector for inputting a clock and effect driving control data to the second effect driving means, and is equipped with In the first substrate, The first effect driving means and the first connector are arranged on the same surface of the substrate. The left-right relationship of each input terminal of the clock and the effect driving control data in the first effect driving means, when viewed from the pattern wiring side to the chip side, The left-right relationship of each connector terminal of the clock and the effect driving control data in the first connector, when viewed facing the derivation direction of the pattern wiring connected to each connector terminal from each connector terminal side, are the same, In the second substrate, The second effect driving means and the second connector are arranged on the same surface of the substrate. The left-right relationship of each connector terminal of the clock and the effect driving control data in the second connector, when viewed facing the derivation direction of the pattern wiring connected to each connector terminal from each connector terminal side, is the same as that of the first connector. The left-right relationship of each input terminal of the clock and the effect driving control data in the second effect driving means, when viewed from the pattern wiring side to the chip side, is the same as that of the first effect driving means.

[0516] FIG. 59 schematically shows the configurations of the first substrate and the second substrate. In the following, although various configurations are schematically shown, in each figure, mainly the connector and the effect driving means are shown as blocks, and "clock CK", "data DT", and "pattern wiring PTH" are shown. Specific examples of the clock CK and the data DT will be described respectively, but these refer to the clock and the effect driving control data supplied from the connector to the effect driving means on the substrate. The same applies to the figures schematically showing the configurations for (Configuration A1-2) to (Configuration A9-3) described later.

[0517] The pattern wiring PTH refers to the pattern wiring for supplying the clock CK and the data DT from the connector to the effect driving means. Although a resistance element or the like may be interposed between the connector and the effect driving means, such a case does not make the configuration of the schematic diagram inapplicable. That is, even when other elements are interposed between the connector and the effect driving means, as long as the configuration shown in the figure is satisfied between the connector and the effect driving means. More precisely, in the elements interposed between the connector and the effect driving means, as long as the left-right relationship of the wirings of the clock CK and the data DT is not reversed, it can be considered that they are ignored and the following configuration is applicable. Also, the IC chip as a buffer circuit connected to the signal path between the connector and the effect driving means can be considered as part of the effect driving means, but there is also a way of thinking of excluding it from the more narrowly defined effect driving means. Even if the buffer circuit is not included in the effect driving means, as long as the buffer circuit is interposed between the connector and the effect driving means and the left-right relationship of the wirings of the clock CK and the data DT is not reversed, it can be considered that the buffer circuit is ignored and the following configuration is applicable. The above should be considered in the same way for (Configuration A1-2) to (Configuration A9-3) described later.

[0518] As shown in FIG. 59, a first connector and a first effect driving means are mounted on the first substrate. The first connector and the first effect driving means are arranged on the same surface of the first substrate. In the figure, the blocks of the first connector and the first effect driving means are shown by solid lines, which indicates that they are arranged on the illustrated surface. Also, "○" in the blocks serving as the connector and the effect driving means indicates a terminal.

[0519] The first connector inputs the clock CK and the control data for effect driving (data DT) to the first effect driving means. The clock CK and the data DT are supplied to the first effect driving means through the pattern wiring PTH on the substrate. Not only in the case of being connected only by the pattern wiring PTH as described above, but also when a resistor element or a chip is interposed. Further, in some cases, some wirings may be formed on the other surface of the substrate through through-holes. Although these matters are not repeatedly mentioned in each example, the same applies to the pattern wiring PTH in other configuration examples described later.

[0520] A second connector and a second effect driving means are mounted on the second substrate. The second connector and the second effect driving means are arranged on the same surface of the second substrate. The second connector inputs the clock CK and the effect driving control data (data DT) for the second effect driving means. The clock CK and the data DT are supplied to the second effect driving means through the pattern wiring PTH on the substrate. Since the left-right relationship of the terminals of the clock CK and the data DT of the first effect driving means and the second effect driving means is the same, they are shown by the same rectangle.

[0521] In this case, pay attention to the directions DIR1, DIR2, DIR3, and DIR4 indicated by the arrows. The directions DIR1 and DIR3 are the directions facing the derivation directions of the pattern wiring PTH connected to the respective connector terminals from the respective connector terminal sides of the clock CK and the data DT. The directions DIR2 and DIR4 are the directions from the pattern wiring PTH side to the chip side (= the chip that is the effect driving means) of each input terminal of the clock CK and the data DT in the effect driving means.

[0522] The left-right relationship between the terminal of the clock CK and the terminal of the data DT when viewed in the directions DIR1, DIR2, DIR3, and DIR4 is shown at the bottom of FIG. 59.

[0523] The left-right relationship when viewed in the directions DIR1 and DIR3 means "The left - right relationship when looking at each connector terminal of clock CK and data DT in the connector, facing the derivation direction of the pattern wiring PTH connected to each connector terminal from the side of each connector terminal." It is as follows. In the example of FIG. 59, as shown in the figure, the terminal of clock CK is on the left and the terminal of data DT is on the right.

[0524] Note that the left - right relationship when viewed in directions such as DIR1 and DIR3 can also be expressed as in the following examples, and it suffices to correspond to any of them. "The left - right relationship when looking at each connector terminal of clock CK and data DT in the connector, when looking from the connector side to the pattern wiring PTH side." "The left - right relationship when looking at each connector terminal of clock CK and data DT in the connector, facing the direction of the connector side from which the pattern wiring PTH connected to each connector terminal is derived."

[0525] Also, the left - right relationship when viewed in directions DIR2 and DIR4 is "The left - right relationship when looking at each input terminal of clock CK and control data DT for effect driving in the effect driving means, when looking from the pattern wiring PTH side to the chip (= the chip of that effect driving means) side." It is as follows. In the example of FIG. 59, as shown in the figure, the terminal of clock CK is on the left and the terminal of data DT is on the right.

[0526] Note that the left - right relationship when viewed in directions such as DIR2 and DIR4 can also be expressed as in the following examples, and it suffices to correspond to any of them. "The left - right relationship when looking at each input terminal of clock CK and data DT in the effect driving means, when looking in a state where each input terminal faces the side surface of the chip." "The left - right relationship when looking at each input terminal of clock CK and data DT in the effect driving means, when looking at the chip side along the introduction direction of the pattern wiring PTH connected to each input terminal."

[0527] When the left - right relationship of the connector terminals and the left - right relationship of the terminals of the effect driving means are the same in these directions, it can be said that it is a left - right relationship such that, even if we assume that the connector and the effect driving means are arranged on the same surface of the substrate with their corresponding terminals facing each other and wiring is done connecting each terminal at the shortest distance, no crossing of the wiring occurs.

[0528] And in the case of the example in FIG. 59, the left - right relationships of the terminals of the clock CK and the data DT when viewed in the directions DIR1, DIR2, DIR3, and DIR4 are all the same.

[0529] Note that being the same in the left - right relationship means that the terminal of the clock CK may be on the left and the terminal of the data DT may be on the right and be the same, or the terminal of the clock CK may be on the right and the terminal of the data DT may be on the left and be the same. This also applies to each of the following configurations other than (Configuration A1 - 1).

[0530] A configuration like this in FIG. 59 corresponds to the above - mentioned (Configuration A1 - 1). The following (Specific Example 1) is assumed as an example corresponding to this (Configuration A1 - 1).

[0531] (Specific Example 1) · First substrate: LED substrate 780 (see FIG. 45) · Second substrate: LED substrate 790 (see FIG. 46) · Clock (CK) for the first effect driving means: Clock signal CLK · Control data for effect driving (DT) for the first effect driving means: Data signal DATA · First effect driving means: LED driver 782 · Input terminal for the clock in the first effect driving means: Terminal 2 (SCLK terminal) · Input terminal for the control data for effect driving in the first effect driving means: Terminal 3 (SDATA terminal) · First connector: Connector CN1N · Connector terminal for the clock of the first connector: Second pin · Connector terminal for control data for the effect drive of the first connector: Third pin · Second effect drive means: LED driver 791 · Clock (CK) for the second effect drive means: Clock signal CLK · Control data for effect drive (DT) for the second effect drive means: Data signal DATA · Input terminal for the clock in the second effect drive means: Second terminal (SCLK terminal) · Input terminal for the control data for effect drive in the second effect drive means: Third terminal (SDATA terminal) · Second connector: Connector CN1X · Connector terminal for the clock of the second connector: Second pin · Connector terminal for the control data for effect drive of the second connector: Third pin

[0532] In this (Specific Example 1), the LED substrate 780 corresponding to the first substrate is shown in FIGS. 60 and 61. FIG. 60 is the conductor pattern of the surface layer of the LED substrate 780 having the circuit configuration described in FIG. 45, and FIG. 61 is the conductor pattern of the back surface layer. Note that the back surface layer in FIG. 61 is shown as a perspective view seen from the surface layer side of FIG. 60 and is illustrated in a state of being horizontally reversed. In FIGS. 60 and 61, the identification numbers of the components printed on the substrate and the like are omitted from the illustration. The part shown as "○○ + XX△△" is actually the substrate management number displayed.

[0533] The plurality of light-emitting elements mounted on the LED substrate 780 are, as shown in the light-emitting part 783 of FIG. 45, the light-emitting elements LED1 to LED12 as color LED chips and the light-emitting elements LED14 to LED22 as monochromatic LED chips. "pLED1" to "pLED22" in FIG. 60 (surface layer) indicate the positions (pads or lands as contacts, hereinafter collectively referred to as pads) where the light-emitting elements LED1 to LED22 on the LED substrate 780 are respectively arranged. Also, "p782" indicates the position (pad) where the LED driver 782 is arranged, and "pCN1N" and "pCN2N" indicate the positions (pads) where the connectors CN1N and CN2N are arranged. Also, "p781" indicates the position (pad) where the buffer circuit 781 is arranged.

[0534] For the connector CN1N, the pad on the upper left side of the drawing is the first pin side. For the connector CN2N, the pad on the left side of the drawing is the first pin side.

[0535] As shown in FIGS. 60 and 61, a ground pattern 784 as a solid ground is formed in the surface layer and the back layer, and a pattern wiring for realizing the circuit configuration of FIG. 45 is formed. Note that the many small circular portions shown on the pattern represent through holes or vias. Through hole vias (interlayer wiring) with copper foil are also included. These are also generically referred to as "through holes" for the purpose of explanation.

[0536] Also, ...

Claims

【Claim 1】 A gaming machine that conducts a game based on a lottery result, having a first substrate on which electronic components related to game operations are mounted, The first electronic component mounted on the first substrate has unused terminals that do not require electrical connection, On the first substrate, pads corresponding to all terminals including the unused terminals of the first electronic component are formed, All terminals of the first electronic component are soldered to the corresponding pads, The pads corresponding to the unused terminals are not electrically connected except to the unused terminals, The pads corresponding to the unused terminals are formed in proximity to a solid ground, A non-linear solid ground is formed in substantially the entire area of the substrate surface directly below the bottom surface of the chip as the first electronic component Gaming machine.

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