Pachinko machine

Abstract

To provide a game machine in which a performance control operation is further improved.SOLUTION: A display device includes a display driving circuit which drives a group of display elements constituting a display screen, and an illumination circuit which illuminates the display screen. An integrated VRAM area of image producing means is configured so as to be repeatedly refreshed every predetermined refresh cycle and keep a memory content.SELECTED DRAWING: Figure 21

Description

Technical Field

[0001] The present invention relates to a gaming machine that performs a lottery process caused by a gaming operation and executes an image effect corresponding to the lottery result, and particularly to a gaming machine that can stably execute a powerful image effect.

Background Art

[0002] A pachinko machine or other ball game machine is configured to include a symbol start port provided on a game board, a symbol display unit that displays a series of symbol variation modes by a plurality of display symbols, a big winning port where an opening / closing plate is opened / closed, and the like. When a detection switch provided at the symbol start port detects the passage of a game ball, it enters a winning state. After the game ball is paid out as a bonus ball, the display symbols are varied for a predetermined time in the symbol display unit. Then, when the symbols stop in a predetermined mode such as 7·7·7, it enters a jackpot state, and the big winning port is repeatedly opened, generating a gaming state advantageous to the player.

[0003] Whether or not to generate such a gaming state is determined by a jackpot lottery executed on the condition that a game ball has won at the symbol start port, and the above symbol variation operation is based on the lottery result. For example, when the lottery result is a winning state, an effect operation called a reach action or the like is executed for about 20 seconds, and then special symbols are aligned. On the other hand, in the case of a losing state, a similar reach action may be executed. In this case, the player will watch the transition of the effect operation while strongly hoping for a jackpot state. Then, when a predetermined symbol is aligned on the stop line at the end of the symbol variation operation, it is guaranteed to the player that it is in a jackpot state.

[0004] Such a symbol variation operation is usually executed on a liquid crystal display. The liquid crystal display generally consists of a liquid crystal display unit MONI that realizes color display of three primary colors RGB, and a backlight unit BL where LEDs emit light on the back side of the liquid crystal display unit. Generally, the liquid crystal display unit MONI is composed of pixels of horizontal H dots × vertical V dots. Each pixel of H×V dots is composed of basic pixels of three colors RGB respectively. When the backlight unit BL is lit, the colors of each basic pixel are activated.

[0005] The driving of each pixel in the liquid crystal display unit is executed in synchronization with the operation clock CK (= dot clock DCK) of the device. The pixel driving of H dots corresponding to one line in the horizontal direction is repeated in synchronization with the horizontal synchronization signal HS. When the driving for V lines is completed, it is configured to return to the pixel driving of the first line in synchronization with the vertical synchronization signal VS (see Fig. 42). Therefore, it is necessary to supply, from an external device to the liquid crystal display unit, together with an image signal corresponding to the resolution of H×V dots, the horizontal synchronization signal HS, the vertical synchronization signal VS, and the dot clock DCK.

[0006] Here, in order to smoothly execute the display update operation (frame update) of the liquid crystal display unit, predetermined conditions are required for the pulse widths of the synchronization signals HS and Vs, and for the transmission timing between the synchronization signals HS and Vs and the image signal. For example, Fig. 42(g) shows an example of the driving timing conditions required in the case of VGA (Video Graphics Array) of 640×408 dots.

[0007] Under the illustrated driving conditions, first, the pulse width PWh of the horizontal synchronization signal HS is 96 portions of the operation clock CK. The front porch FPh and the back porch BPh required before and after the horizontal synchronization signal PWh are defined as 16 portions and 48 portions of the operation clock CK respectively.

[0008] On the one hand, the pulse width PWv of the vertical synchronization signal VS is for two lines, and the front porch FPv and the back porch BPv required before and after the vertical synchronization signal VS are defined as 19 lines and 33 lines, respectively.

[0009] Therefore, in this liquid crystal display unit, the operation cycle of one line of the driving operation is counted by the operation clock CK and is 16 + 96 + 48 + 640 ( = 800), and by repeating this for 10 + 2 + 33 + 480 lines ( = 525) in the vertical direction, the display for one frame of the display screen is updated.

[0010] The above operation cycle is counted by the operation clock CK and is 800 × 525. For example, when the frequency of the operation clock is 25 MHz, the time required for updating one frame is 800 × 525 / (25 × 10 6 ) = 16.8 mS, which is an operation cycle of about 1 / 60 second.

[0011] And the external control device that controls the liquid crystal display unit supplies an image signal corresponding to the number of pixels of the display screen to the liquid crystal display unit repeatedly together with the horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and the horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh).

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0013] By the way, in this type of gaming machine, various effects are desired to be made more complex and rich. In particular, for the image effects using a liquid crystal display, the demand is high. Therefore, the applicant has made various proposals (Cited Documents 1 to 4), but further sophistication of the image effects and further improvement of various effect control operations centered on the image effect control are desired.

[0014] The present invention has been made in view of the above problems, and an object thereof is to provide a gaming machine in which various effect control operations centered on the image effect control are further improved.

Means for Solving the Problems

[0015] To achieve the above object, the gaming machine according to the present invention is A gaming machine that is provided with a VDP (Video Display Processor) that generates image signals necessary for image rendering, and a VDP circuit that has a VDP register in which setting values that define the operation of the VDP are set, a CPU, an internal circuit that operates under the control of the CPU, and a CPU circuit that has an operation control register in which setting values that define the operation of the internal circuit are set, and in which various rendering operations including image rendering are executed. In the memory space accessible by the CPU, there are included a plurality of external address spaces located outside the CPU circuit including the CPU, each of which can define a data bus width. In the memory space, there are at least located a memory device that stores an initial program to be first executed after reset of the CPU, and the VDP register. On the other hand, in the memory space accessible by the VDP, there are included a CGROM that stores CG compressed data, and a video RAM that is used for generating image data for image rendering. Among the plurality of external address spaces, in a predetermined ROM space, first address information belonging to the external address space and second address information that does not belong to any external address space are stored non-volatilely. After reset of the CPU, the second address information is set in the stack pointer of the CPU, and the first address information is set in the program counter of the CPU, so that execution of a predetermined initial program is started. There is provided a first means for setting necessary setting values in the operation control register in order to optimize an access operation to the memory device, and then, a second means for setting necessary operation parameters in the VDP register based on the operation of the initial program before the start of the image rendering operation in order to optimize an access operation to the CGROM. .

Effects of the Invention

[0016] According to the present invention described above, Various operations centered on image rendering control the effect control operations are further improved.

Brief Description of the Drawings

[0017]

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Embodiments for Carrying Out the Invention

[0018] Hereinafter, the present invention will be described in detail based on embodiments. FIG. 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM is composed of a rectangular frame-shaped wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached via a hinge 2 fixed to the outer frame 1 so as to be openable and closable. A game board 5 is detachably attached to this inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side thereof so as to be openable and closable, respectively. In this specification, the glass door 6 and the front panel 7 are collectively referred to as a front door member. And the inner frame 3 in a state where the front door member (glass door 6 or front panel 7) is pivotally attached may be referred to as a game frame.

[0019] On the outer periphery of the glass door 6, decorative lamps such as LED lamps are arranged in a substantially C shape. On the other hand, a total of three speakers are arranged at the upper left and right positions and the lower side of the glass door 6. The two speakers arranged at the upper part output the sounds of the left and right channels R and L, respectively, and the lower speaker is configured to output bass.

[0020] On the front panel 7, an upper tray 8 for storing game balls for launching is mounted. At the lower part of the inner frame 3, a lower tray 9 for storing game balls that have overflowed or been removed from the upper tray 8 and a launch handle 10 are provided. The launch handle 10 is linked to a launch motor, and the game balls are launched by a striking hammer that operates according to the rotation angle of the launch handle 10.

[0021] On the outer peripheral surface of the upper tray 8, a chance button 11 is provided. This chance button 11 is provided at a position where it can be operated with the player's left hand, and the player can operate the chance button 11 without releasing the right hand from the launch handle 10. This chance button 11 does not function normally, but when the game state becomes the button chance state, the built-in lamp lights up and it becomes operable. Note that the button chance state is a game state provided as needed.

[0022] Also, below the chance button 11, a rotary switch type volume switch VLSW is arranged. By operating the volume switch VLSW by the player, the speaker volume can be adjusted in 8 steps from the silent level (=0) to the maximum level (=7). Note that the volume of the speaker is initially set by a setting switch (not shown) that can only be operated by the staff, and the initial set volume is maintained unless the player operates the volume switch VLSW. Also, the abnormal notification sound for notifying the occurrence of an abnormal situation is emitted at the maximum volume regardless of the initial set volume by the staff or the set volume by the player.

[0023] On the right part of the upper tray 8, an operation panel 12 for the ball lending operation for the card type ball lender is provided, and a frequency display section for displaying the card balance in three digits, a ball lending switch for instructing the lending of game balls for a predetermined amount, and a return switch for instructing the return of the card at the end of the game are provided.

[0024] As shown in FIG. 2, a guide rail 13 composed of a metal outer rail and an inner rail is annularly provided on the surface of the game board 5, and a central opening HO is provided substantially at the center thereof. And below the central opening HO, a movable effect body (not shown) is stored in a concealed state. At the time of a movable pre-announcement effect, the movable effect body rises to an exposed state, thereby realizing a pre-announcement effect with a predetermined reliability. Here, the pre-announcement effect is an effect that uncertainly notifies the player that a big win state advantageous to the player is to be brought about, and the reliability of the pre-announcement effect means the probability that the big win state is to be brought about.

[0025] In the central opening HO, a main display device DS1 composed of a large-sized (for example, 1280 pixels wide × 1024 pixels high) liquid crystal color display is arranged. On the right side of the main display device DS1, a movable sub-display device DS2 composed of a small-sized (for example, 480 pixels wide × 800 pixels high) liquid crystal color display is arranged. The main display device DS1 is composed of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that variably displays specific symbols related to the big win state and animates background images and various characters. This display device DS1 has a special symbol display section Da to Dc at the center and a normal symbol display section 19 at the upper right. And in the special symbol display section Da to Dc, a reach effect that expects the occurrence of the big win state may be executed, and appropriate pre-announcement effects and the like are executed around the special symbol display section Da to Dc and its periphery.

[0026] Normally, the sub-display device DS2 displays image information in a stationary state with its display screen tilted at an angle easy for the player to see. However, at the time of a predetermined pre-announcement effect, while changing the tilt angle to an angle easy for the player to see, it moves to the left side in the figure and displays a predetermined pre-announcement image.

[0027] That is, the sub-display device DS2 of the embodiment functions not only as a simple display device but also as a movable effect body that executes a pre-warning effect. Here, the pre-warning effect by the sub-display device DS2 is set to have a high reliability, and the player will pay attention to the movement operation of the sub-display device DS2 with great anticipation. Note that the sub-display device DS2 is also composed of a sub liquid crystal display unit MONI and an LED backlight unit BL.

[0028] By the way, in the game area where the game balls fall and move, a first symbol start port 15a, a second symbol start port 15b, a first big winning port 16a, a second big winning port 16b, a normal winning port 17, and a gate 18 are arranged. Each of these winning ports 15 to 18 has a detection switch inside and can detect the passage of the game balls.

[0029] Above the first symbol start port 15a, there is an effect stage 14 configured such that the game balls that enter from the inlet IN and move in a seesaw shape or a roulette shape can win the first symbol start port 15. When a game ball wins the first symbol start port 15, the variation operation of the special symbol display units Da to Dc is configured to start.

[0030] The second symbol start port 15b is configured to be opened and closed by an electric tulip equipped with a pair of left and right opening and closing claws. When the stopped symbol after the variation of the normal symbol display unit 19 shows a winning symbol, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0031] Note that the normal symbol display unit 19 displays a normal symbol. When a game ball passing through the gate 18 is detected, the normal symbol varies for a predetermined time and then stops displaying the stop symbol determined by the lottery random number value extracted at the time when the game ball passes through the gate 18.

[0032] The first major winning opening 16a is configured to have a slide plate that moves forward and backward in the front-rear direction, and the second major winning opening 16b is configured to have an opening / closing plate whose lower end is pivotally supported and opens forward. The operations of the first major winning opening 16a and the second major winning opening 16b are not particularly limited, but in this embodiment, the first major winning opening 16a corresponds to the first symbol starting opening 15a, and the second major winning opening 16b is configured to correspond to the first symbol starting opening 15b.

[0033] That is, when a game ball wins a prize in the first symbol starting opening 15a, the variable operation of the special symbol display units Da to Dc is started. Then, when a predetermined jackpot symbol aligns in the special symbol display units Da to Dc, a special game as the first jackpot is started, and the slide plate of the first major winning opening 16a is opened forward to facilitate the winning of the game ball.

[0034] On the other hand, as a result of the variable operation started by the winning of a game ball in the second symbol starting opening 15b, when a predetermined jackpot symbol aligns in the special symbol display units Da to Dc, a special game as the second jackpot is started, and the opening / closing plate of the second major winning opening 16b is opened to facilitate the winning of the game ball. The game value of the special game (jackpot state) varies depending on the jackpot symbol that aligns, etc., but which game value is given is determined in advance based on the lottery result according to the winning timing of the game ball.

[0035] In a typical jackpot state, after the opening / closing plate of the major winning opening 16 is opened, when a predetermined time elapses or a predetermined number (for example, 10) of game balls win a prize, the opening / closing plate closes. Such an operation continues up to a maximum of, for example, 15 times and is controlled to be in a state advantageous to the player. In addition, when the stopped symbol after the variation of the special symbol display units Da to Dc is a specific symbol among the special symbols, a privilege is given that the game after the end of the special game becomes a high-probability state (probability-variable state).

[0036] FIG. 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the above-described operations. Further, FIG. 3(b) is a circuit diagram showing the circuit configuration of the power monitor unit MNI arranged on the payout control board 25, and FIG. 3(c) is a drawing for explaining the specifications of the main display device DS1 used in this embodiment.

[0037] First, based on FIG. 3(c), the specifications of the main display device DS1 used in the embodiment will be described. As described above, this display device DS1 is a liquid crystal color display with 1280 pixels horizontally and 1024 pixels vertically. However, odd pixels (ODD) and even pixels (EVEN) adjacent to each other in the horizontal direction are configured to be received by the receiving unit RV (RVa + RVb) through separate LVDS (Low Voltage Differential Signaling) transmission lines. Therefore, in this embodiment, corresponding to this dual-link specification, the ODD signal is transmitted via the first transmission line LVDS1, and the EVEN signal is transmitted via the second transmission line LVDS2 (lower right part of FIG. 3(a)).

[0038] Also, in this display device DS1, the operation clock CK (see FIG. 42) that defines the internal operation of the display device DS1 is defined so that its frequency ranges from 40 MHz to 70 MHz (typical value = 54 MHz). This operation clock CK corresponds to the LVDS clock CLK described later. However, hereinafter, for convenience of explanation, the frequency of the operation clock CK is assumed to be the typical value of 54 MHz. Also, with the operation clock CK of 54 MHz, a configuration will be described in which the update time FR (Frame Rate) required for updating an image of one frame is made to coincide with approximately 1 / 60 second.

[0039] This display device DS1 is configured to simultaneously process two adjacent pixels in the horizontal direction of the display screen based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2 at one operation clock CK. As a result, the pixel data of 1280 pixels in one horizontal line is updated in an operation time of 640 / 54MHz = 11.85μS, and by repeating this operation for 1024 lines, the image display of 1280×1024 pixels for one frame is updated. Note that the image is updated in a non-interlaced manner line by line, such as from the first line → the second line ··· → the 1024th line.

[0040] However, as shown in FIG. 3(c), as a specification of the display device DS1, it is stipulated that a standby time (blank period) of 204 clocks is provided in the horizontal direction as a typical value, and a standby time (blank period) of 42 lines is provided in the vertical direction as a typical value. Therefore, considering these blank periods, the actual screen update cycle FR is (204 + 640)×(42 + 1024) / 54MHz ≒ 16.66mS in the calculation based on the above typical values, so the frame rate FR is about 1 / 60Hz.

[0041] Note that an allowable range with respect to the typical value is stipulated for the horizontal standby time WTh and the vertical standby time WTv, and actually, values different from the above typical values can be selected. However, in order to make the frame rate FR = 1 / 60 second, it is necessary to accurately set the horizontal / vertical standby times WTh / WTv so that (WTh + 640)×(WTv + 1024) / 54MHz = 1 / 60 second.

[0042] On the other hand, in this display device DS1, it is not particularly necessary to receive the horizontal synchronization signal HS and the vertical synchronization signal VS. On the other hand, when transmitting the ODD signal and the EVEN signal, the transmission of the data valid signal ENAB at the H level is required. That is, at the timing of transmitting a significant signal (ODD / EVEN signal) to the transmission lines LVDS1 and LVDS2, the data valid signal ENAB needs to be at the active level (H).

[0043] Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the effect control board 23 and the main display device DS1 are LVDS-connected via a dual-link transmission path of an LVDS clock CLK with a frequency of 54 MHz (= 1 / 2 of the dot clock DCK) (FIG. 5, FIG. 14(a)). Further, in the VDP circuit 52 of this embodiment, a horizontal blanking period WTh and a vertical blanking period WTv that satisfy the specifications of the main display device DS1 are provided, and when outputting image data (ODD / EVEN signals), the data valid signal ENAB is set to an active level (H level).

[0044] That is, as shown in FIG. 4(b), the data valid signal ENAB is configured such that only the horizontal display period THd is at the H level during the horizontal synchronization period TH. Therefore, the data valid signal ENAB is always at the L level except during the vertical display period TVd within the vertical synchronization period TV. Note that the horizontal blanking period WTh and the vertical blanking period WTv adopt values different from their respective typical values (WTh = 204 / WTv = 42), and the specific design values will be described later based on FIG. 15.

[0045] In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal in each operation cycle of the LVDS clock CLK via the differential signal lines RA2 / RB2. The data valid signal ENAB shown in FIGS. 4(b) and 4(c) is a demodulated signal of the discrete DE signal transmitted by LVDS, and is a continuous signal of the discrete DE signal on the time axis. Note that in the differential signal lines RA2 / RB, the vertical synchronization signal VS and the horizontal synchronization signal HS are also repeatedly transmitted following the DE signal (data valid signal ENAB), but the main display device DS1 used in the embodiment does not utilize these synchronization signals VS, HS.

[0046] However, in the display device DS1, the transmission of the horizontal synchronization signal HS and the vertical synchronization signal VS is not prohibited at all. However, the internal operations defined for these synchronization signals are not executed. That is, the horizontal line feed timing of the display line is independent of the received horizontal synchronization signal HS, and is defined based on the falling timing of the data valid signal ENAB, the number of operation clocks CK (corresponding to the LVDS clock CLK) after the rising timing of the data valid signal ENAB (640 in the embodiment = 1280 / 2), etc., to the optimal timing for the internal circuit of the display device DS1 (downward arrow in Fig. 4(b)).

[0047] This also applies to the vertical line feed timing after the image display for one frame. It is defined based on the number of consecutive data valid signals ENAB with a predetermined pulse width (1024 in the embodiment), etc., to the optimal timing for the internal circuit of the display device DS1 (downward arrow in Fig. 4(c)) and is not affected by the received vertical synchronization signal VS. Thus, in this embodiment, since there is no need to transmit the horizontal synchronization signal HS and the vertical synchronization signal VS to the display device DS1, there is no need to optimally set the pulse widths PWh / PWv of the synchronization signals HS, VS, the front porches FPh / FPv, and the back porches BPh / BPv, and the control burden on the rendering control unit 23 and the VDP circuit 52 is greatly reduced.

[0048] Also, as for the internal operation of the display device DS1, the horizontal and vertical line feed operations are executed at the optimal timing based on its own internal configuration, so the possibility of an unnatural display operation is eliminated. Incidentally, in the case of a display device that operates based on the horizontal synchronization signal HS and the vertical synchronization signal VS received from the outside, if the pulse widths of the synchronization signals HS, VS, the front porch period before and after the synchronization signals HS, VS, and the back porch period are inappropriate, there is a possibility that the normal display operation will be impaired.

[0049] Incidentally, in Fig. 4(a), the first differential signal LVDS1 using differential signal lines RA0 to RA3 and RACLK transmits odd-numbered pixels (ODD signal on the A side), and the second differential signal LVDS2 using differential signal lines RB0 to RB3 and RBCLK transmits even-numbered pixels (EVEN signal on the B side). Thus, in this embodiment, by transmitting two types of ODD signals and EVEN signals through a dual-link transmission path, the frequency of the dot clock DCK can be reduced to 1 / 2, resulting in better noise resistance and an increased transmission distance accordingly.

[0050] On the other hand, the main display device DS1 incorporates a conversion reception unit RV for ODD signals and EVEN signals transmitted through a dual-link transmission path, and restores RGB signals from the two LVDS signals (ODD signal and EVEN signal) to display an image for one frame (1280 × 1024 dots). As described above, since each RGB signal is composed of 8 bits, the main display device DS1 has a color depth of 2 8 ×2 8 ×2 8 full-color image displayed.

[0051] Fig. 5 is a block diagram showing the internal configuration of a display device DS1 composed of a main liquid crystal display unit MONI and an LED backlight unit BL, particularly in relation to the relevant part of the VDP circuit 52. As shown, the ODD signal is transmitted to the LVDS-parallel conversion unit RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS-parallel conversion unit RVb via the second LVDS line (B side). Then, among the RGB data of 8-bit length transmitted on the differential lines RA0 / RB0, the image data R0 to R5, G0 are output, and from the differential lines RA1 / RB1, the image data G1 to G5, B0 to B1 are output.

[0052] Also, image data B2 to B5, the DE signal, the VS signal, and the HS signal are output from the differential lines RA2 / RB2, and image data G6 to G7, R6 to R7, and B6 to B7 are output from the differential lines RA3 / RB3. Here, the DE signal is nothing but the data valid signal ENAB. Also, as described above, the output VS signal and HS signal are not used.

[0053] Next, the LVDS clock CLK of the differential lines RACK / RBCK is supplied to the PLL circuit, thereby generating an operation clock CK having the same frequency of 54 MHz as the LVDS clock CLK. This operation clock CK defines the internal operation of the liquid crystal controller LCD_CTL. The liquid crystal controller LCD_CTL collectively processes the image data corresponding to two RGB pixels (8 bits × 3 × 2) adjacent in the left-right direction of the liquid crystal panel LCD in synchronization with one operation clock CK.

[0054] Therefore, the pixels in the horizontal direction of 1280 (= 640 × 2) dots are processed in a processing time of 11.85 μS (= 640 / 54 MHz) corresponding to 640 operation clocks CK. Note that one pixel is composed of three basic RGB pixels, and the image data of the three basic RGB pixels are each 1 byte long and have a gradation of 2 8 ×2 8 ×2 8 Therefore, the image data of all the pixels (1280 dots) in one line is 3 × 1280 bytes long as a whole.

[0055] As shown in FIG. 5, the liquid crystal controller LCD_CNT has 1280 source signal lines, each of which is 2 8(=256) The source driver SDV driven by a harmonic drive signal and the gate driver GDV that controls the ON / OFF of 1024 gate signal lines are appropriately controlled. Specifically, the liquid crystal controller LCD_CNT realizes an image update operation with a frame rate FR = 1 / 60 Hz by appropriately operating each part based on the DE signal output from the LVDS transmission line and the operation clock CK. As confirmed previously, the DE signal corresponds to the data valid signal ENAB output by the VDP circuit 52.

[0056] In the case of this embodiment, the source driver SDV is configured by arranging 10 driver elements each having 384 output terminals. As described previously, one line of all pixels (1280 dots) of the liquid crystal panel LCD is composed of basic pixels of three colors, RGB, and a total of 3×1280, so 10 driver elements are required to drive them. Note that image data DAT is sequentially supplied to these 10 driver elements from the liquid crystal controller LCD_CNT, and this is appropriately transferred based on the start signal SP and the transfer clock DCLK. Then, in synchronization with the latch signal LT, the analog-converted drive signal is supplied to 3840 source signal lines. As described previously, the time required to update one line of all pixels (1280 dots) of the liquid crystal panel LCD is 11.85 μS (=640 / 54 MHz).

[0057] On the other hand, the liquid crystal controller LCD_CNT updates the gate signal lines to be driven by supplying the gate start signal GS and the gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is configured by arranging 4 driver elements each having 256 output terminals.

[0058] Note that the update timing of the gate signal line is defined based on the falling timing of the DE signal and the operation clock CK. The horizontal blanking period of the gate signal line is counted by the operation clock CK and is set to 640 + 204 clocks in the typical value calculation (see Fig. 3(c)). Also, based on the number of DE signals (1024), the gate signal lines to be driven are reset to the initial state, and at the optimal timing, the gate start signal GS is output, and the output of the gate clock signal GCLK is resumed. The vertical blanking period of the gate signal line is counted by the operation clock CK and is 42 + 1024 clocks in the typical value calculation (see Fig. 3(c)). However, as described above, in this embodiment, the display device DS1 is operated with a design different from the typical value (see Fig. 15).

[0059] Incidentally, the above display operation is conditional on the power supply voltage of 5V being supplied to the main liquid crystal display unit MONI when the LED backlight unit BL is lit. Therefore, in this embodiment, a power supply control circuit SPY is provided to operate the liquid crystal display unit MONI and the backlight unit BL in a coordinated manner. The power supply control circuit SPY receives three types of DC voltages (3.3V, 5V, 12V) from the effect interface board 22 and receives various power supply control signals (STBY, PWM, PS1, PS2) from the effect control CPU 63 of the composite chip 50 (see Fig. 7(a)).

[0060] Then, the power supply control circuit SPY supplies the DC voltage of 5V as the power supply voltage of the main liquid crystal display unit MONI at the optimal timing (see Fig. 6(c) and Fig. 6(g)). Also, the power supply control circuit SPY controls the power supply voltage of the backlight unit BL to be the DC voltage of 12V, and controls the BL_EN terminal and the PWM terminal of the LED backlight unit BL to appropriate H / L levels to realize the optimal lighting operation.

[0061] Fig. 6(a) is a circuit diagram showing the circuit configuration of the power supply control circuit SPY and its relationship with the backlight unit BL and the liquid crystal display unit MONI. As shown in the figure, this power supply control circuit SPY mainly consists of a first switch circuit having a transistor Tr1 and a MOS transistor Q1, a second switch circuit having a transistor Tr2 and a MOS transistor Q2, a third switch circuit having a transistor Tr3 and a MOS transistor Q3, a fourth switch circuit having a transistor Tr4 and a MOS transistor Q4, and a buffer circuit SBUF that receives various control signals.

[0062] The buffer circuit SBUF is a high-speed Schmitt buffer (e.g., TC74VHC9125) using the DC voltage of 3.3V supplied from the effect interface board 22 as the power supply voltage, and operates with a non-inverting input-output relationship. That is, the effect control CPU 63 of the composite chip 50 outputs supply control signals (STBY, PWM, PS1, PS2) with a theoretical H / L width based on the power supply voltage of 3.3V, and the buffer circuit SBUF that receives these outputs control signals (STBY, PWM, PS1, PS2) of the same logic (see Fig. 7(a)).

[0063] As shown in Fig. 6(a), the four input terminals (STBY, PWM, PS1, PS2) of the buffer circuit SBUF are all connected to the ground via pull-down resistors Rpd, and are configured such that all control signals become L level when each control signal is in the HiZ (high impedance) state, such as when the connection connector is in a separated state or when power is turned on.

[0064] Next, in the first to fourth switch circuits, the transistors Tr1 to Tr4 are all NPN bipolar transistors and are driven to perform a switching operation. That is, each of the transistors Tr1 / Tr2 / Tr3 / Tr4 turns on based on the voltage division ratio of the bias resistors when the corresponding control signals PS1 / STBY / PWM / PS2 are at the H level, while turns off when the control signals PS1 / STBY / PWM / PS2 are at the L level because no current flows through the bias resistors.

[0065] Here, when the transistors Tr1 / Tr4 are in the OFF operation, the collector outputs of the respective transistors Tr1 / Tr4 are both at a level higher than 3.3V (12V / 5V). Also, when the MOS transistor Q1 is in the ON state and the transistors Tr2 / Tr3 are in the OFF operation, the collector output of each of the transistors Tr2 / Tr3 is about 12V. In these respects, the transistors Tr1 to Tr4, together with the bias resistors, constitute a level shift circuit that increases the logic H level of the power supply control signals (STBY, PWM, PS1, PS2).

[0066] The bias resistors for the transistors Tr1 to Tr4 are R11 + R12, R21 + R22, R31 + R32, and R41 + R42, respectively, and the voltages defined by the voltage division ratios of the respective bias resistors are supplied to the base terminals of the transistors Tr1 to Tr4.

[0067] In this embodiment, since the above-described level shift circuit (Tr1 to Tr4) is provided, while increasing the emission luminance of the backlight, the power consumption of the effect control unit 23 can be greatly suppressed. That is, while making the power supply voltage (12V) of the backlight unit BL as high as possible, the logic H level of the power supply control signals (STBY, PWM, PS1, PS2) can be set to an arbitrary low level (3.3V).

[0068] On the other hand, all of the MOS transistors Q1 to Q4 are Pch type, and perform a switching operation according to the ON / OFF states of the transistors Tr1 to Tr4. In the ON operation, the source terminal S and the drain terminal D are in a substantially conductive state.

[0069] Specifically, first, the MOS transistor Q1 receives the DC voltage 12V supplied by the effect interface board 22 at its source terminal S. When the transistor Tr1 operates in the ON state based on the H-level control signal PS1, the MOS transistor Q1 also operates in the ON state based on the voltage across the bias resistor Rb1 that transitions to the energized state in response to this, and outputs the DC voltage 12V to the drain terminal D.

[0070] This DC voltage of 12V is supplied to the backlight unit BL via an RC filter circuit and a Zener diode. In this embodiment, in particular, as the MOS transistor Q1, an element with an ON resistance between the source S and the drain D of 25 mΩ or more and 35 mΩ or less is used. Therefore, for example, even when a drive current (drain current ID) of 2.5 A flows constantly, the voltage drop in the MOS transistor Q1 is 0.1 V or less, and the power loss is also suppressed to about 0.22 W (= 2.5 * 2.5 * 35 / 1000). The ON resistance is the measurement result in pulse drive at VGS = -10V and ID = -4.5A.

[0071] Also, the transistors Q2 and Q3 receive the voltage of the drain terminal D of the transistor Q1 at their respective source terminals S. Therefore, when the transistors Tr2 / Tr3 operate in the ON state based on the H-level control signal STBY / PWM while the MOS transistor Q1 is in the ON state, the MOS transistors Q2 and Q3 also operate in the ON state based on the voltage across the bias resistors Rb2 / Rb3 that shift to the energized state in response to this. Therefore, a DC voltage of 12V is output to the drain terminals D of the MOS transistors Q2 and Q3 via the ON-state transistor Q1, respectively.

[0072] This DC voltage of 12V is output as the control signal STBY from the drain terminal D of the MOS transistor Q2, and is output as the control signal PWM from the drain terminal D of the MOS transistor Q3. The control signal STBY is supplied to the BL_EN terminal (back light enable) of the backlight unit BL in a pulled-down state by the pull-down resistor Rpd, and the control signal PWM is supplied to the PWM terminal (pulse width modulation) of the backlight unit BL in a pulled-down state by the pull-down resistor Rpd.

[0073] In this embodiment, by setting the pull-down resistors Rpd to about 33 kΩ each, the current flowing through the pull-down resistors Rpd due to the DC voltage of 12 V (STBY / PWM) is suppressed to about 0.36 mA. Therefore, it is not necessary to select expensive elements for the MOS transistors Q2 and Q3. In this embodiment, elements with an ON resistance between the source S and the drain D of 2.5 Ω or more and 3.8 Ω or less are used. The ON resistance is the measurement result under pulse drive at VGS = -4.5 V and ID = -100 mA.

[0074] Next, the backlight unit BL will be described. The backlight unit BL includes N×M light-emitting diodes (LEDs) arranged in an aligned manner vertically and horizontally, and a driver DVL that outputs a drive pulse of negative logic to synchronously turn on and drive the N×M light-emitting diodes. This driver DVL includes a BL_EN terminal that defines whether to enable the internal operation, a PWM terminal that defines the duty ratio of the drive pulse of negative logic in positive logic in the range of 10% to 100%, and output terminals LED1 to LEDn that output the drive pulse.

[0075] As described above, the control signal STBY is supplied from the power supply control circuit SPY to the BL_EN terminal, and the control signal PWM is supplied to the PWM terminal. When the control signal STBY is at the H level (12 V), the internal circuit of the driver DVL operates, and drive pulses can be output from the output terminals LED1 to LEDn. This drive pulse is a negative logic pulse obtained by logically inverting the control signal PWM.

[0076] Thus, since the drive pulse of the embodiment is a negative logic pulse obtained by logically inverting the control signal PWM supplied to the PWM terminal, the closer the duty ratio of the control signal PWM is to 100%, the longer the L-level period of the output terminals LED1 to LEDn becomes, and the average current flowing through the light-emitting diodes increases, making the backlight light brighter. On the other hand, the closer the duty ratio is to 10%, the lower the average current of the light-emitting diodes becomes, making the backlight light darker.

[0077] Therefore, by appropriately changing the duty ratio of the control signal (control pulse) PWM, the emission intensity of the backlight light can also be changed. For example, in the demo state where the player is absent, the backlight light can be dimmed. However, in this embodiment, in order to avoid such complexity of emission control, the duty ratio of the control signal is maintained at 100%, and the control signal PWM maintains a constant H level (12V) in the operating state without changing in a pulsed manner. Therefore, the output terminals LED1 to LEDn of the driver DVL will constantly maintain an L level in the operating state of the backlight unit BL.

[0078] By the way, both the BL_EN terminal and the PWM terminal are connected to the ground via the pull-down resistor Rpd. Therefore, when the MOS transistor Q2 is in the OFF state and the control signal STBY is in the HiZ state, the driver DVL becomes in the non-operating state and the output terminals LED1 to LEDn become in the HiZ state, so all the light-emitting diodes are in the off state.

[0079] Also, when the MOS transistor Q3 is in the OFF state and the control signal PWM is in the HiZ state, for example, even if the control signal STBY is at the H level, by maintaining the duty ratio at 0%, the output terminals LED1 to LEDn maintain the H level (12V) and all the light-emitting diodes are in the off state. Therefore, at the time of power-on when significant image data is not transferred or when there is an operation abnormality in the power supply control circuit SPY, the backlight will turn off, and as a result, unnatural image display is avoided. Connecting the pull-down resistor Rpd between the four input terminals of the buffer circuit SBUF and the ground is also based on the same intention.

[0080] Subsequently, the relationship between the fourth switch circuit having the transistor Tr4 and the MOS transistor Q4 and the main liquid crystal display unit MONI will be described. As described above, the transistor Tr4 of the fourth switch circuit operates in an ON / OFF manner based on the H / L level of the control signal PS2.

[0081] On one hand, the MOS transistor Q4 receives the DC voltage of 5V supplied by the effect interface board 22 at its source terminal S. When the transistor Tr1 operates in the ON state, in response to this, based on the voltage across the bias resistor Rb4 that transitions to the energized state, the MOS transistor Q4 also operates in the ON state and outputs a DC voltage of 5V at its drain terminal D.

[0082] This DC voltage of 5V is supplied to the liquid crystal display unit MONI shown in FIG. 5 via an RC filter circuit and a Zener diode, and is utilized as the power supply voltage for the liquid crystal display unit MONI. In this embodiment, in particular, as the MOS transistor Q4, an element with an ON resistance between the source S and the drain D of 48 mΩ or more and 65 mΩ or less is used. Therefore, for example, even when a drive current (drain current ID) of 1.5A flows constantly, the voltage drop in the MOS transistor Q1 is 0.1V or less, and the power loss is also suppressed to about 0.15W (=1.5 * 1.5 * 65 / 1000). Note that the ON resistance is the measurement result in pulse drive at VGS = -4.5 and ID = -2.5A.

[0083] Subsequently, based on FIGS. 6(b) to 6(j), the circuit operation of the power supply control circuit SPY will be described. After the power is turned on, the composite chip 50 starts the control operation after passing through an assertion period during which the system reset signal SYS maintains the L level (timing T1 in FIG. 6(d)). Then, the effect control CPU 63 of the composite chip 50 transitions the control signals PS1 and PS2 to the H level 1000 mS after timing T1 (timing T2).

[0084] Then, based on the H-level control signal PS1, the MOS transistor Q1 operates in the ON state, and the supply of DC 12V to the backlight unit BL is started. Also, based on the H-level control signal PS2, the MOS transistor Q4 operates in the ON state, and the supply of DC 5V to the liquid crystal display unit MONI is started. However, at this timing T2, since both the control signals STBY and PWM remain at the L level, the backlight unit BL does not emit light. Therefore, no matter how the liquid crystal display unit MONI operates, there is no risk of an unnatural image being displayed.

[0085] Next, after about 5 mS has elapsed since timing T2, the production control CPU 63 starts the display clock and the initialization operation of the display circuit 74. Although the details of this control content will be described later, these operations are part of the initialization operation until the operation of the VDP circuit 52 starts. At this stage, no significant image signal is output to the display device DS1.

[0086] Thereafter, after appropriately initializing the display register, the production control CPU 63 starts the operations of the display circuit 74 and the LVDS circuit 80 (timing T4). Therefore, after timing T4, the LVDS signal as a significant image signal is repeatedly output to the display device DS1 every 1 / 60 second (see Fig. 6(f)).

[0087] However, at the time of timing T4, since the control signal PWM maintains the L level, the backlight light does not emit. That is, the production control CPU 63 transitions the control signal STBY to the H level at timing T3 to control the driver DVL to an operable state. However, at the time of timing T4, since the control signal PWM = L and the duty ratio of the drive pulse is 0%, the off state of the backlight unit BL is maintained.

[0088] On the other hand, after starting the operations of the display circuit 74 and the LVDS circuit 80 (SS4 in Fig. 21), at the timing T5 when 300 mS or more has elapsed, the production control CPU 63 transitions the control signal PWM to the H level (SS6 in Fig. 21) to transition the backlight unit BL to a light-emitting state with a duty ratio of 100%. When the operation at timing T5 is executed by, for example, timer interrupt processing, at the time of timing T5, the liquid crystal display unit MONI has already repeatedly received the LVDS signal as a significant image signal every 1 / 60 second, so an image based on that image signal will be displayed. That is, since the steady processing (ST4 to ST14 in Fig. 22) starts immediately after the processing of step SS6 in Fig. 21, an initial screen based on the display list DL is displayed at the time of timing T5.

[0089] However, as shown in FIG. 21, when the effect control CPU 63 executes a standby process of 300 mS (step SS5 in FIG. 21), at timing T5, since the display list DL has not yet been issued, the display content is a screen based on the VRAM (frame buffer FBa) after power-on. Therefore, considering this point, it is preferable to zero-clear the VRAM (especially frame buffers FBa and FBb) after power-on. However, even if it is not zero-cleared, the random image will be displayed only for an instant at the start of business at the gaming hall, so there is no problem. That is, immediately after the process of step SS6 in FIG. 21, the steady process (ST4 to ST14 in FIG. 22) is started, and the initial screen based on the display list DL is displayed.

[0090] Incidentally, in this embodiment, the program execution time from timing T2 to timing T4 is designed to be within 20 mS in the program. This is because the display device DS1 used in the embodiment recommends that the transmission of the image signal (LVDS signal) be started within a predetermined time τ (for example, 20 mS) from the power-on of the liquid crystal display unit MONI.

[0091] In this embodiment, delaying the power supply timing to the liquid crystal display unit MONI by about 1 second using the control signal PS2 is also based on the above requirements. If the power supply to the liquid crystal display unit MONI is started simultaneously with the power-on, it is very difficult to start the transmission of the LVDS signal within a predetermined time τ (for example, 20 mS) thereafter, considering the assertion period and the program execution time (processing time of SP1 to SP10) (refer to timing T4).

[0092] The main display device DS1 has been described in detail above. The operation content of the sub-display device DS2 is substantially the same. By operating as shown in FIG. 6(b), the sub liquid crystal display unit MONI and the backlight unit BL are configured to operate in a coordinated manner so that inappropriate display does not occur.

[0093] Also, the sub-display device DS2 operates in the same manner as shown in FIG. 42 based on the horizontal synchronization signal HS and the vertical synchronization signal VS received from the VDP circuit 52. However, it is also preferable that the sub-control device DS2 adopts a configuration in which it operates based on the data valid signal ENAB without relying on the horizontal synchronization signal HS or the vertical synchronization signal VS. Note that the data valid signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB instead of in the form of a discrete DE signal (see the lower right part of FIG. 14(a)).

[0094] Next, returning to FIG. 3(a), the overall circuit configuration of the pachinko machine GM will be described. As shown in FIG. 3(a), this pachinko machine GM includes a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) together with AC24V, a main control board 21 that centrally and comprehensively manages the game control operation, an effect interface board 22 equipped with circuit elements SND for sound effects, an effect control board 23 that uniformly executes lamp effects, sound effects, and image effects based on the control command CMD received from the main control board 21, a liquid crystal interface board 24 located between the effect control board 23 and the display devices DS1 and DS2, a payout control board 25 that controls the payout motor M based on the control command CMD' received from the main control board 21 to payout game balls, and a launch control board 26 that launches game balls in response to the operation of the player. It is mainly composed of these components.

[0095] Note that the effect interface board 22, the effect control board 23, and the liquid crystal interface board 24 are directly connected by a male connector and a female connector without passing through a wiring cable. Therefore, even if the circuit configuration of each electronic circuit becomes more complex and sophisticated, the storage space of the entire board can be minimized, and the noise resistance can be improved by minimizing the connection lines.

[0096] As shown in the figure, the control command CMD’ output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the effect control board 23 via the effect interface board 22. Here, both control commands CMD and CMD’ are 16 bits long, but are transmitted in parallel in two parts for every 8 bits.

[0097] A computer circuit including a one-chip microcomputer is mounted on the main control board 21 and the payout control board 25. Also, a composite chip 50 with built-in computer circuits such as a VDP circuit (Video Display Processor) 52 and a built-in CPU circuit 51 is mounted on the effect control board 23. Therefore, in this specification, the operations realized by these control boards 21, 25, 23, the circuits mounted on the effect interface board 22 and the liquid crystal interface board 24, and their circuits are generically referred to as the main control unit 21, the effect control unit 23, and the payout control unit 25. Note that the effect control unit 23 and the payout control unit 25 are sub-control units with respect to the main control unit 21.

[0098] In addition, this pachinko machine GM is roughly divided into a frame side member GM1 surrounded by the dashed line in Fig. 3(a) and a board side member GM2 fixed to the back of the game board 5. The frame side member GM1 includes an inner frame 3 to which a glass door 6 and a front panel 7 are pivotally attached, and a wooden outer frame 1 outside thereof, and is fixedly installed in the game hall for a long time regardless of the model change. On the other hand, the board side member GM2 is replaced corresponding to the model change, and a new board side member GM2 is attached to the frame side member GM1 instead of the original board side member. Note that all except the frame side member 1 are the board side member GM2.

[0099] As shown by the dashed-line frame in Fig. 3(a), the frame side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are respectively fixed at appropriate positions of the inner frame 3. On the other hand, on the back surface of the game board 5, a main control board 21 and a production control board 23 are fixed together with display devices DS1, DS2 and other circuit boards. And the frame side member GM1 and the board side member GM2 are electrically connected by centralized connection connectors C1 to C3 that are centrally arranged at one location.

[0100] Based on the AC voltage AC24V distributed from the game hall, the power supply board 20 generates three types of DC voltages (35V, 12V, 5V), and distributes each DC voltage to the production interface board 22 via the centralized connection connector C2. Also, the three types of DC voltages (35V, 12V, 5V) are distributed to the payout control board 25 together with the AC voltage AC24V. And the DC voltages (35V, 12V, 5V) distributed to the payout control board 25 are configured to be distributed to the main control board 21 via the centralized connection connector C1 together with the backup power supply BAK.

[0101] DC 35V is used as the drive power supply for the ball feed solenoid, the launch solenoid, the electromagnetic solenoid that drives the electric tulip (variable winning device) and the large winning opening 16 regarding the launch operation of the game ball. Also, DC 12V is used as the drive power supply for the LED lamps and motors controlled from each control board and the power supply voltage of the digital amplifier. On the other hand, DC 5V is used as the power supply voltage of the one-chip microcomputer of the payout control board 25 and the main control board 21, and the power supply voltage of the logic elements mounted on each control board. Also, after the level of DC 5V is dropped by the DC / DC converter of the production interface board 22, the voltages of various levels after the level drop are used as the power supply voltages of various computer circuits (such as the composite chip 50 and the audio processor 27).

[0102] The backup power supply BAK is a DC 5V power supply for retaining the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25 after power-off, and is realized by, for example, an electric double layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double layer capacitor arranged on the backup power supply board 33 is configured to be charged by the DC voltage 5V received from the payout control board 25 during the gaming operation.

[0103] On the other hand, after power-off, since the backup power supply BAK retains the data in the built-in RAM of the one-chip microcomputer of the main control unit 21 and the payout control unit 25, the main control unit 21 and the payout control unit 25 can resume the gaming operation before power-off after power-on. Note that on the backup power supply board 33, an electric double layer capacitor capable of retaining the stored content in the built-in RAM of each one-chip microcomputer is arranged for at least several days.

[0104] By the way, in this embodiment, different from the conventional device configuration, a power supply abnormality signal ABN indicating an abnormal decrease in the AC voltage AC24V is configured to be generated in the power supply monitor unit MNT of the payout control board 25 instead of the power supply board 20. As shown in FIG. 3(b), the power supply monitor unit MNT includes a full-wave rectification circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that emits light when energized in response to the output of the full-wave rectification circuit, a phototransistor TR that operates in the ON state based on the DC voltage 5V received from the power supply board 20 and the light emission of the photodiode D, and an output unit that outputs a detection signal ABN (power supply abnormality signal) at the H level based on the ON operation of the phototransistor TR. Note that the photodiode D and the phototransistor TR constitute a photocoupler PH.

[0105] In the above configuration, after power-on, the photocoupler PH quickly turns ON, causing the power supply abnormality signal ABN to reach the normal level (H). However, if the AC power supply then abnormally drops for some reason (normally power-off), the photocoupler PH changes to the OFF state, causing the power supply abnormality signal ABN to change to the abnormal level (L). This power supply abnormality signal ABN is transmitted to the one-chip microcomputer on the payout control board 25 and is also configured to be transmitted to the one-chip microcomputer on the main control board 21 via the centralized connection connector C1. Therefore, each one-chip microcomputer that receives the power supply abnormality signal ABN at the abnormal level will execute a backup process of storing the necessary information in its built-in RAM. As described earlier, since the information in the built-in RAM is maintained by the backup power supply BAK, the gaming operation before power-off can be resumed after power-on.

[0106] As shown in Fig. 3(a), the effect interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the effect control board 23 is equipped with a composite chip 50 with a built-in computer circuit such as a VDP circuit 52 and a built-in CPU circuit 51. Hereinafter, the built-in CPU circuit may be abbreviated as the CPU circuit.

[0107] The effect interface board 22 is equipped with reset circuits RST3 and RST4 that detect the rise of the power supply voltage at power-on and generate various reset signals RT3 and RT4. First, the reset circuit RST3 generates a reset signal RT3 based on the DC voltages 12V and 5V distributed from the power supply board 20. Then, the reset signal RT3 only power-resets the audio memory 28 and is directly transmitted to the effect control board 23.

[0108] The reset signal RT3 transmitted to the effect control board 23 is AND-operated with the output of the WDT (Watch Dog Timer) circuit 58 in the AND gate G1 as shown in Fig. 7(a), and power-resets the CPU circuit 51 and the VDP circuit 52 as the system reset signal SYS (see Figs. 7(a) and 7(d)).

[0109] The reset signal RT3 generated by the reset circuit RST3 rises to the H level after maintaining the predetermined time L level as the power-on reset signal after power-on. However, when one or more of the DC voltages of 12V or 5V drop (usually when the power is cut off), the system reset signal SYS also drops to the L level in response to the drop in the level of the reset signal RT3, so the CPU circuit 51 and the VDP circuit 52 of the effect control board 23 enter the operation stop state.

[0110] Since this system reset signal SYS also changes based on the output of the WDT circuit 58 (H level during normal operation), when the output of the WDT circuit 58 drops to the L level due to a program runaway or the like in the state where the reset signal RT3 = H, the system reset signal SYS also changes to the L level to abnormally reset the CPU circuit 51 and the VDP circuit 52 (see Fig. 7(d)).

[0111] On the other hand, the reset circuit RST4 generates a reset signal RT4 based on 3.3V generated by dropping the 5V distributed from the power supply board 20. This reset signal RT4 power-on resets the audio processor 27 as the power-on reset signal at power-on.

[0112] As shown in the figure, the system reset signal SYS returned from the effect control board 23 is also supplied to the reset circuit RST4. Therefore, when the CPU circuit 51 and the VDP circuit 52 are abnormally reset, the audio processor 27 is also abnormally reset in synchronization with the abnormal reset of these circuits. As a result, the audio effect returns to the initial state together with the video effect and the lamp effect, and there is no possibility of continuous unnatural audio effects.

[0113] Next, the payout control board 25 as the frame side member GM1 and the main control unit 21 as the board side member GM2 are each equipped with reset circuits RST1 and RST2, and a power-on reset signal is generated at power-on, and each computer circuit is configured to be power-on reset.

[0114] As described above, in this embodiment, reset circuits RST1 to RST4 are respectively arranged in the main control unit 21, the payout control unit 25, and the effect interface board 22, and the system reset signal SYS is not transmitted between circuit boards. That is, since there is no wiring cable for transmitting the system reset signal SYS, the possibility that the computer circuit is abnormally reset due to noise superimposed on the wiring cable is eliminated.

[0115] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each incorporate a watchdog timer. When the CPUs of the respective control units 21 and 25 do not receive periodic clear pulses, the respective CPUs are forcibly reset.

[0116] In addition, an initialization switch SW operable by an attendant is arranged in the main control unit 21, and a RAM clear signal CLR indicating whether the initialization switch SW has been turned on at power-on is configured to be output. This RAM clear signal CLR is transmitted to the one-chip microcomputers of the main control unit 21 and the payout control unit 25, and determines whether to initialize all areas of the built-in RAM of the one-chip microcomputers of the respective control units 21 and 25.

[0117] Also, as described above, the one-chip microcomputers of the main control unit 21 and the payout control unit 25 receive a power failure abnormal signal ABN from the power monitor MNT arranged in the payout control unit 25, and start necessary end processing prior to a power failure or the end of business.

[0118] As shown in FIG. 3(a), the main control unit 21 receives a bonus ball count signal indicating the payout operation of the game balls, a status signal CON related to an abnormality in the payout operation, and an operation start signal BGN from the payout control unit 25. The status signal CON includes, for example, a replenishment depletion signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power-on.

[0119] In addition, the main control unit 21 receives switch signals from detection switches built into each winning port 16-18 on the game board, while driving solenoids such as electric tulips. The solenoids and detection switches are configured to operate with the power supply voltage VB (12V) distributed from the main control unit 21. Also, each switch signal indicating the winning state of the symbol start port 15 and the like is converted into a switch signal of TTL level or CMOS level by an interface IC operating with the power supply voltage VB (12V) and the power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0120] As described above, the effect interface board 22 receives DC voltages of each level (5V, 12V, 35V) from the power supply board 20 via the centralized connection connector C2 (see FIGS. 3(a) and 7(a)). The DC voltage of 12V is the power supply voltage of the digital amplifier 29 and is also used as the drive voltage for LED lamps and the like. Also, the DC voltage of 35V is distributed to appropriate positions on the game frame and used as the drive voltage for solenoids that reciprocate movable objects.

[0121] On the other hand, the DC voltage of 5V is supplied as the power supply voltage for circuit elements at various locations on the effect interface board 22, and is also supplied to two DC / DC converters DC1 and DC2 to generate 3.3V and 1.0V (see FIG. 7(a)). The generated DC voltages of 3.3V and 1.0V are supplied to the audio processor 27 as the power supply voltages for I / O (input / output) and chip core, respectively. Also, the DC voltage of 3.3V serves as the base voltage of the power reset signal RT4 generated by the reset circuit RST4.

[0122] The DC voltage of 5V distributed to the effect interface board 22 is distributed to the effect control board 23 together with the 3.3V generated by the DC / DC converter DC1. Then, the DC voltage of 3.3V distributed to the effect control board 23 is supplied as the power supply voltage to the composite chip 50, the PROM 53, and the CGROM 55.

[0123] As shown in Fig. 7(a), two DC / DC converters DC3 and DC4 are arranged on the effect control board 23, and based on the DC voltage of 5V supplied to each, 1.5V and 1.05V are generated. Here, the DC voltage of 1.05V is the power supply voltage for the chip core of the composite chip 50, and the DC voltage of 1.5V is the power supply voltage for I / O (input / output) with the DRAM 54. Therefore, the DC voltage of 1.5V is also supplied to the DRAM 54 as the power supply voltage.

[0124] As shown in Fig. 3(a), the effect interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and transfers them to the effect control board 23. More specifically, as shown in Fig. 7(a), the control command CMD and the strobe signal STB are transferred to the composite chip 50 (CPU circuit 51) of the effect control board 23 via the input buffer 40. Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the effect control CPU 63 acquires the control command CMD based on the interrupt processing program (interrupt handler) activated by receiving the received interrupt signal IRQ_CMD.

[0125] As shown in Fig. 7(a), the input buffer 44 of the effect interface board 22 receives the switch signals of the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and transmits each switch signal to the CPU circuit 51 of the effect control board 23. Specifically, the 3-bit length of the encoder output indicating the contact position (0 to 7) of the volume switch VLSW and the 1-bit length indicating the ON / OFF state of the chance button 11 are transmitted to the CPU circuit 51.

[0126] In addition, a lamp drive board 30 and a motor lamp drive board 31 are connected to the effect interface board 22, and are also connected to a lamp drive board 37 via frame relay boards 35 and 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. In FIG. 7(a), for the sake of convenience, the input buffer 43a and the output buffer 43b are collectively referred to as an input / output buffer 43. The input buffer 43a receives the outputs SN0 to SNn of the origin sensors that grasp the current positions (rotation positions of the effect motors M1 to Mn) of the movable effect objects and transmits them to the CPU circuit 51 of the effect control board 23.

[0127] The same type of driver ICs are mounted on the lamp drive board 30, the motor lamp drive board 31, and the lamp drive board 37, and the effect interface board 22 transfers the serial signal received from the effect control board 23 to each driver IC. Specifically, the serial signal is a lamp (motor) drive signal SDATA and a clock signal CK. The drive signal SDATA is transmitted to each driver IC in a clock synchronization manner, and lamp effects by a large number of LED lamps and electric decoration lamps and effect performances by the effect motors M1 to Mn are executed.

[0128] In the case of this embodiment, the lamp effect is executed by three systems of lamp groups CH0 to CH2. The lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 in synchronization with the clock signal CK0 via the frame relay boards 35 and 36. Note that a series of lamp drive signals SDATA0 transmitted as the serial signal are output from the driver IC to the lamp group CH0 at the timing when the operation control signal ENABLE0 changes to the active level, and thus the lighting state is updated all at once.

[0129] The above points also apply to the lamp drive board 30. The driver IC on the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and updates the lighting states of the lamp group CH1 all at once at the timing when the operation control signal ENABLE1 changes to the active level.

[0130] On the other hand, the driver IC mounted on the motor lamp drive board 31 drives the lamp group CH2 by receiving the lamp drive signal transmitted in a clock-synchronous manner, and drives the effect motor groups M1 to Mn composed of a plurality of stepping motors by receiving the motor drive signal transmitted in a clock-synchronous manner. The lamp drive signal and the motor drive signal are a series of serial signals SDATA2, which are serially transmitted in synchronization with the clock signal CK1. The driver IC that receives this updates the drive states of the lamp group CH2 and the motor groups M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0131] Next, the audio circuit SND will be described. As shown in Fig. 7(a), on the effect interface board 22, there are mounted an audio processor (audio synthesis circuit) 27 that reproduces an audio signal based on an instruction received from the CPU circuit 51 (effect control CPU 63) of the effect control board 23, an audio memory 28 that stores compressed audio data and the like, which are the original data of the reproduced audio signal, and a digital amplifier 29 that receives the audio signal output from the audio processor 27.

[0132] The audio processor 27 is configured to include a WDT circuit that automatically resets the set value of the internal circuit to the default value (initial value) during abnormal operation of the internal circuit, and an audio control register SRG. Then, the audio processor 27 accesses the audio memory 28 based on the operation parameters (set values by audio commands) received from the effect control CPU 63 to the audio control register SRG, and reproduces and outputs the necessary audio signal.

[0133] As shown in Fig. 7(a), the voice processor 27 and the voice memory 28 are connected by a 26-bit voice address bus and a 16-bit voice data bus. Therefore, the voice memory 28 can store data of 1 Gbit (= 2 26 × 16).

[0134] The voice control register SRG is divided into register banks 1 to 6, and is specified by register numbers 00H to FFH respectively. Therefore, a predetermined setting operation is realized by the production control CPU 63 writing a 1-byte operation parameter to the voice control register SRG with a predetermined register number (1-byte length) after specifying the register bank.

[0135] In the case of this embodiment, the register numbers (00H to FFH) of the voice control register SRG correspond to the address space CS3 of the production control CPU 63. For example, when setting the operation parameter YYH to the voice control register SRG with the register number XXH, the production control CPU 63 writes XXH to the zero address of the address space CS3, and then writes YYH to the first address. That is, the production control CPU 63 writes XXH and YYH to its data bus in this order. In this specification, the suffix H and the prefix 0X / 0x indicate that the numerical value is in hexadecimal notation.

[0136] Also, in this specification, the address spaces CS0 to CS7 mean external memories (excluding built-in memories) for the CPU circuit 51 that can respectively define the memory type including volatility and the data bus width (8 / 16 / 32 bits). These address spaces CS0 to CS7 are selected by different chip select signals CS0 to CS7, and are configured to be set so that the READ / WRITE control signals that function during READ / WRITE access can be optimized according to the memory type. Note that this setting operation is executed for the bus state controller 66.

[0137] Fig. 7(e) illustrates the setting operation of the audio register SRG by the production control CPU 63, showing the content of the 2-bit address bus A1 - A0 and the 1-byte data bus D7 - D0. In this embodiment, the chip select signal CS3 is set at power-on so as to be automatically activated when accessing the address space CS3. This will be described later with reference to Figs. 9 and 16.

[0138] Anyway, in the case of this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data specified by the 13-bit phrase number NUM (000H to 1FFFH). A piece of a series of background music (BGM) or a set of production sounds (preview sounds), etc., up to 8192 types (= 2 13 ) are stored corresponding to the phrase number NUM respectively. And this phrase number NUM is specified by the set value (operation parameter) of the audio command transmitted from the production control CPU 63 to the audio control register SRG of the audio processor 27.

[0139] As described above, the audio memory 28 having the above configuration is power reset by the reset signal RT3, and the audio processor 27 is power reset by the reset signal RT4. As shown in Fig. 7(c), the reset signal RT4 rises to the H level after a predetermined assert period ASRT (L level section) after power-on. In this embodiment, thereafter, the internal circuit of the audio processor 27 automatically functions and is configured to execute the initialization sequence process. Note that this initialization sequence process is an internal operation executed in a predetermined procedure, and during the operation of the initialization sequence process, the production control CPU 63 cannot access the audio register SRG.

[0140] Then, when the initialization sequence process, which is an internal operation, is completed, the interrupt signal IRQ_SND for the CPU circuit 51 changes to the L level, and the CPU circuit 51 (the effect control CPU 63) executes an interrupt processing program based on the interrupt signal IRQ_SND. Then, based on a predetermined instruction, the interrupt signal IRQ_SND is returned to the H level. Details thereof will be further described later with reference to FIG. 18(c).

[0141] As shown in FIG. 7(a), the data bus and the address bus of the CPU circuit 51 of the effect control unit 23 also extend to the clock circuit (real time clock) 38 and the effect data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus of the CPU circuit 51 and the lower 4 bits of the data bus. In a state where the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 is configured to be able to arbitrarily access an internal register (having a 4-bit long address value).

[0142] The effect data memory 39 is a memory element SRAM (Static Random Access Memory) that can be accessed at high speed. It is connected to 16 bits of the address bus of the CPU circuit 51 and the lower 16 bits of the data bus. In a state where the chip is selected by the chip select signal CS4, game achievement information and the like stored in the SRAM (effect data memory) 39 can be appropriately R / W accessed from the CPU circuit 51. Note that in the address space CS4 selected by the chip select signal CS4, the addresses from 0 to 15 are assigned to the clock circuit 38, so they are not used in the SRAM 39.

[0143] The clock circuit 38 and the effect data memory 39 are driven by a secondary battery (not shown), and this secondary battery is appropriately charged by the power supply voltage from the power supply board 20 during the game operation. Therefore, even after the power is cut off, the clocking operation of the clock circuit 38 continues, and the game achievement information stored in the effect data memory 39 is permanently stored (non-volatile is provided). Note that the clock circuit (RTC) 38 is configured to be able to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the day, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. In this embodiment, an alarm interrupt for updating the daily game achievement information is utilized at the end of business every day.

[0144] As shown on the right side of FIG. 7(a), the effect control board 23 is equipped with a composite chip 50 incorporating the CPU circuit 51 and the VDP circuit 52, a control memory (PROM) 53 storing the control program of the CPU circuit 51, a DRAM (Dynamic Random Access Memory) 54 capable of accessing a large amount of data at high speed, and a CGROM 55 storing a large amount of CG data necessary for effect control.

[0145] As will be described later with reference to FIG. 10, in this embodiment, the control memory (PROM) 53 is positioned in the address space CS0 selected by the chip select signal CS0. Also, the DRAM (Dynamic Random Access Memory) 54 configured with DDR (Double-Data-Rate 3) is positioned in the address space CS5 selected by the chip select signal CS5.

[0146] FIG. 8(a) is a circuit block diagram showing the composite chip 50 that constitutes the presentation control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of the embodiment includes a CPU circuit 51 that issues a display list DL every predetermined time, and a VDP circuit 52 that generates image data based on the issued display list DL and drives display devices DS1 and DS2. The CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays the transmission and reception data between them.

[0147] Note that the VDP circuit 52 incorporates an audio circuit SND that exhibits the same functions as the audio processor 27. However, in the first embodiment to be described hereinafter, the audio circuit SND is not utilized. However, if the audio circuit SND incorporated in the VDP circuit 52 is utilized as in the embodiment described last, the arrangement of the audio memory 28 and the audio processor 27 becomes unnecessary.

[0148] First, the CPU circuit 51 receives the oscillation output (e.g., 100 / 3 MHz) of the oscillator OSC1 at the HCLKI terminal, multiplies this frequency (e.g., 8 times), and uses it as a CPU operation clock of about 266.7 MHz (see FIG. 14(b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby taking electromagnetic interference (EMI) countermeasures to prevent radio wave interference / electromagnetic interference.

[0149] By the way, in the case of this embodiment, it is also possible to generate the CPU operation clock based on the output of an oscillator OSC2, which will be described later, instead of the oscillator OSC1, and the oscillator OSC1 can be made unnecessary. However, in a configuration with a single oscillator, the frequency multiplication ratio of the PLL circuit becomes the same fixed value (e.g., 5) as in the case of the system clock described below, so the frequency of the CPU operation clock becomes the same 200 MHz (= 40 MHz × 5) as the system clock of the VDP circuit 52.

[0150] With such a configuration, while there is an advantage that the operation cycles of the built-in CPU circuit 51 and the VDP circuit 52 are made common, it runs counter to the demand for speeding up the operation of the CPU as much as possible. That is, since the operation of the VDP cannot be speeded up beyond a certain level, it cannot surely meet the demand for speeding up the CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the respective operation cycles of the VDP circuit 52 and the CPU circuit 51. Also, by providing a separate oscillator OSC1, it is possible to improve the above-described EMI countermeasures.

[0151] Based on the above, when explaining the VDP circuit 52, the VDP circuit 52 receives the oscillation output (40 MHz) of an oscillator OSC2 different from the oscillator OSC1 at the PLLREF terminal, and uses a PLL (Phase Locked Loop) circuit to multiply the frequency and then uses it as the system clock of the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixedly defined by the set value to a predetermined set terminal. In this embodiment, since the set value to the set terminal (3-bit PLLMD terminal) is the fixed value 5, the system clock of the VDP circuit 52 becomes 200 MHz (= 40 MHz × 5) (see Fig. 14(b)).

[0152] Also, in this embodiment, the dot clocks DCK A ~DCK C that define the operations of the display circuits 74A to 74C, and the DDR clock of the external DRAM 54 are also generated based on the oscillation output (40 MHz) of the oscillator OSC2. That is, the output (40 MHz) of the oscillator OSC2 functions as the reference clock for the entire VDP circuit 52.

[0153] As will be described later with reference to Figs. 14 and 15, since the display circuits 74A to 74C usually drive display devices with different specifications respectively, the dot clocks DCK A ~DCK CIt is necessary to correspond to the specifications of the display device to be driven. Based on such a necessity, in this embodiment, the display circuits 74A to 74C receive any one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillation circuits DCLKA to DCLKC and use it as the dot clock DCK A ~DCK C and are configured to be able to do so.

[0154] When this configuration is utilized, the design of the multiplication ratio and division ratio described later and the setting process for the VDP register RGij become unnecessary, and the frequency of the dot clock DCK A ~DCK C can be easily optimized. That is, a dedicated oscillation circuit DCLKA with an oscillation frequency F DOT1 is provided corresponding to the dot clock frequency F DOT1 of the main display device DS1, and a dedicated oscillation circuit DCLKB with an oscillation frequency F DOT2 is also provided corresponding to the dot clock frequency F DOT2 of the sub-display device DS2.

[0155] However, when such a configuration is adopted, a dedicated oscillation circuit is required corresponding to the number of display devices, and the device configuration becomes complicated. Therefore, in this embodiment, in order to simplify the device configuration, based on the oscillation output (40 MHz) of the oscillator OSC2, the dot clocks DCK A / DCK B of the display circuits 74A / 74B are generated. Specifically, as shown in FIG. 14(b), for the display circuit 74A that drives the main display device DS1, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (×108) and division process (1 / 40) to generate a dot clock DCK A with a frequency of 108 MHz.

[0156] Similarly, for the display circuit 74B that drives the sub-display device DS2, the oscillation output (40 MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (×108) and division process (1 / 160) to generate a dot clock DCK dot with a frequency F B = 27 MHz.is being generated. Designing these multiplication ratios and division ratios is rather complicated, and it is easier to provide a dedicated oscillation circuit. However, in this embodiment, emphasis is placed on simplifying the device configuration, and no dedicated oscillation circuit is provided.

[0157] In any case, the dot clock DCK A ~DCK C is individually set for each of the display circuits 74A to 74C. When these dot clocks DCK A ~DCK C are collectively referred to, in this specification, they may be referred to as "display clock DCK". Also, in the following description, the dot clock DCK A or DCK B may be abbreviated as "dot clock DCK" for convenience.

[0158] Note that in this embodiment, since a low-speed LVDS output configuration is not adopted, the LVDS clock CLK of the LVDS signal output via the display circuit 74A also goes through the same generation process as the dot clock DCK A and has a frequency of 108 MHz. However, in this embodiment, since a dual-link transmission path is adopted, the actual frequency of the LVDS clock CLK is 54 MHz as described with respect to FIG. 4. When a single-link transmission path is adopted, the frequency of the LVDS clock CLK is 108 MHz.

[0159] As described above, in this embodiment, the oscillation output (40 MHz) of the oscillator OSC2 is utilized as the system clock, the dot clock DCK, and the reference clock of the DDR clock. Therefore, considering this importance, the oscillator OSC2 is operated at the same power supply voltage of 3.3 V as the VDP circuit 52, and is configured to oscillate and output the reference clock on the condition that the output enable terminal OE is at the H level (= 3.3 V). And in case the power supply voltage of 3.3 V drops below a predetermined level, then, since a normal rendering operation cannot be expected thereafter, it is configured to generate a non-maskable interrupt (NMI).

[0160] In addition, the composite chip 50 is provided with an HBTSL terminal. Based on the logic level of the HBTSL terminal, it is determined whether the boot program (initial setting program) executed after power-on (CPU reset) is stored in the CGROM 55 (HBTSL = H) or in other memories (HBTSL = L). As shown in the figure, in this embodiment, it is set to the HBTSL = L level, and the zero address of the address space CS0 of the effect control CPU 63 is assigned to other than the CGROM. Specifically, the address space CS0 is assigned to the control memory 53.

[0161] On the other hand, when the HBTSL terminal is set to the H level (refer to the dashed line), the zero address of the address space CS0 of the effect control CPU 63 is assigned to the CGROM 55. In this case, the memory type of the CGROM 55 and the bus width (64 / 32 / 16 bit) are each to be specified based on the input values to the 2-bit long HBTBWD terminal and the 4-bit long HBTRMSL terminal. These points will be further described later with reference to FIG. 39.

[0162] Next, the CPU circuit 51 and the VDP circuit 52 will be described in terms of the CPUIF circuit 56 that relays the transmission and reception data between them. As shown in FIG. 8(a), the CPUIF circuit 56 is connected to a control memory (PROM) 53 that stores control programs and necessary control data non-volatilely and a work memory (RAM) 57 having a storage capacity of about 2 Mbytes, and is configured to be accessible from the CPU circuit 51 respectively. As described above, the control memory (PROM) 53 is located in the address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is located in the address space CS6 selected by the chip select signal CS6.

[0163] In this working memory (RAM) 57, a DL buffer BUF is secured to primarily store a display list DL in which a series of instruction commands for specifying each frame of the display devices DS1 and DS2 is described. In the case of this embodiment, the series of instruction commands includes texture load commands such as a TXLOAD command for reading out and decoding (expanding) a pixel material (texture) from the CGROM 55, texture setting commands such as a SETINDEX command having functions such as preliminarily specifying a VRAM area (index space) as a decoding (expansion) destination, primitive drawing commands such as a SPRITE command for arranging the decoded (expanded) pixel material at a predetermined position in the virtual drawing space, environment setting commands such as a SETDAVR command and a SETDAVF command for specifying a drawing area to be actually drawn on the display devices from among the images drawn in the virtual drawing space by the drawing commands, and index table control commands (WRIDXTBL) regarding an index table IDXTBL for managing the index space.

[0164] Note that FIG. 12(c) illustrates the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), a drawing area that can be arbitrarily set within the virtual drawing space, and the actual drawing areas in the frame buffers FBa and FBb that primarily store the image data output to the display devices DS1 and DS2.

[0165] Next, the CPU circuit 51 is a circuit having performance equivalent to that of a general-purpose one-chip microcomputer, and includes an effect control CPU 63 that comprehensively controls image effects based on the control program in the control memory 53, a watchdog timer (WDT) that forcibly resets the CPU when the program runs wild, a built-in RAM 59 having a storage capacity of about 16 KB and used as a working area for the CPU, a DMAC (Direct Memory Access Controller) 60 that realizes data transfer without passing through the CPU 63, a serial input / output port (SIO) 61 having a plurality of input ports Si and output ports So, a parallel input / output port (PIO) 62 having a plurality of input ports Pi and output ports Po, and an operation control register REG in which set values are set to control the operations of the respective parts. However, in this embodiment provided with an external WDT circuit 58, the watchdog timer (WDT) built in the CPU circuit 51 is not utilized.

[0166] In this specification, for convenience, the expression of input / output ports is used. However, in the effect control unit 23, the input / output ports include an independently operating input port and output port. This also applies to the input / output circuits 64p and 64s described below.

[0167] The parallel input / output port 62 is connected to an external device (effect interface board 22) through the input / output circuit 64p. The effect control CPU 63 receives, via the input circuit 64p, the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p.

[0168] Similarly, the received control command CMD is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. Also, the strobe signal STB is supplied to the interrupt terminal of the effect control CPU 63 via the input / output circuit 64p, thereby activating the reception interrupt process. Therefore, based on the reception interrupt process, the effect control CPU 63 that has grasped the control command CMD will uniformly control the voice effect, lamp effect, motor effect, and image effect corresponding to this control command CMD through effect lottery and the like.

[0169] Although not particularly limited, in this embodiment, for the lamp effect and the motor effect, the SMC unit (Serial Management Controller) 78 of the VDP circuit 52 is used. The SMC unit 78 is a composite controller incorporating an LED controller and a Motor controller, and is configured to be able to output a serial signal in a clock synchronization method. Also, the Motor controller is configured to be able to output a latch pulse at an arbitrary timing based on the set value to a predetermined control register 70, and is also configured to be able to input a serial signal in a clock synchronization method.

[0170] Therefore, in this embodiment, while outputting a motor drive signal and an LED drive signal from the SMC unit 78 in synchronization with the clock signal, a latch pulse is output as an operation control signal ENABLE at an appropriate timing. Also, the origin sensor signals SN0 to SNn from the effect motor group M1 to Mn are configured to be serially input in a clock synchronization method.

[0171] As described with respect to FIG. 7(a), the clock signals CK0 to CK2, the drive signals SDATA0 to SDATA2, and the operation control signals ENABLE0 to ENABLE2 are transmitted to the predetermined drive boards 30, 31, 37 via the output buffers 41 to 43. Also, the origin sensor signals SN0 to SNn are serially input to the SMC unit 78 from the motor lamp drive board 31 via the input / output buffer 43.

[0172] However, in this embodiment, it is not essential to use the SMC unit 78. That is, since the general-purpose serial input / output port SIO61 is built into the CPU circuit 51, it is also possible to execute the lamp effect and the motor effect using these.

[0173] Specifically, as shown by the dashed line in Fig. 8(a), in the configuration shown by the dashed line, the clock signals CK0 to CK2 and the drive signals SDATA0 to SDATA2 are output via the input / output circuit 64s internally connected to the serial input / output port SIO61, and the operation control signals ENABLE0 to ENABLE2 are output via the input / output circuit 64p. For convenience, it is expressed as an input / output port and an input / output circuit, but actually, it is the output port and the output circuit that function.

[0174] Here, the serial output port SO is configured with a built-in 16-stage FIFO register. And the DMAC circuit 60 is activated upon receiving an operation start instruction (see ST18 in Fig. 22(b)) from the effect control CPU 63, and is configured to sequentially read the necessary drive data from the lamp / motor drive table (see Fig. 22(b)) and perform DMA transfer to the FIFO register of the serial output port SO. The drive data accumulated in the FIFO register is serially output from the serial output port SO in a clock synchronization manner. Note that although there are a plurality (for example, 7) of DMA channels in the DMAC circuit, it is configured to perform DMA transfer of the lamp drive data using the third DMA channel with a lower priority and perform DMA transfer of the motor drive data using the first DMA channel with the highest priority.

[0175] The operation control register REG built into the CPU circuit 51 is an 8-bit, 16-bit, or 32-bit long register whose register number (address value) is numbered 0xFF400000 or later, and is configured to be accessible for WRITE / READ appropriately from the effect control CPU 63 (see Fig. 10). Therefore, due to the influence of noise or the like, there is a possibility that an unreasonable value may be set in the operation control register REG.

[0176] However, for example, by intentionally executing an infinite loop process to activate the external WDT circuit 58, the composite chip 50 can be abnormally reset. In this case, the value of the operation control register REG is returned to the same default value (initial value) after power-on, and for the VDP circuit 52 as well, the value of the VDP register RGij is returned to the default value (initial value), thereby eliminating the abnormal state.

[0177] FIG. 7(b) is a circuit configuration related to this reset operation, and is a drawing for explaining the reset mechanism characteristic of this embodiment. In this specification, the VDP register denoted as RGij means any one of the control register group 70 (see FIG. 10) that controls the internal operation of the VDP circuit 52, rather than the operation control register REG built in the CPU circuit 51. Also, the system control circuit 520 shown in FIG. 7(b) means the internal control circuit of the VDP circuit 52 that functions based on the set value to the VDP register RGij (any one of the control register group 70 in FIG. 10) (see FIG. 7(a)). Note that the VDP register RGij is located in the address space CS7 selected by the chip select signal CS7 in the address map of the rendering control CPU 63.

[0178] Based on the above, the reset mechanism will be described. As shown in FIG. 7(b), the internal circuit of the composite chip 50 is configured to be resettable via three OR gates G2 to G4 that receive the logically inverted system reset signal SYS bar. However, in this embodiment, as shown by the dashed line, since the built-in WDT is not activated, the input terminal and the output terminal of the OR gate G2 are in a directly connected state.

[0179] In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is configured to output a reset signal RST on the condition that it receives a predetermined keyword sequence (encryption sequence for reset) from the parallel input / output port (PIO) 62.

[0180] The internal circuit of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the part other than the display circuit in the VDP circuit 52, and is configured to receive the reset signals of the first reset path to the third reset path from the OR gates G2 to G4, respectively.

[0181] First, the OR gate G2 with the input / output terminals directly connected is related to the first reset path, and is configured to system-reset the entire CPU circuit 51 based on the system reset signal SYS bar. Also, the OR gate G3 is related to the second reset path, and is configured to be able to reset the entire VDP circuit 52 based on the OR logic by receiving the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK.

[0182] This second reset path is used not only for the power reset operation at power-on, but also for the production control CPU 63 that detects a predetermined abnormality to abnormally reset the entire VDP circuit 52 and return it to the initial state. Specifically, when it is determined that a serious abnormality has occurred based on a predetermined status register RGij indicating the internal operation of the VDP circuit 52, the reset signal RST is generated from the pattern check circuit CHK to abnormally reset the entire VDP circuit 52. Note that the display circuit 74 is abnormally reset via the OR gate G4 in the second reset path → the third reset path.

[0183] On the other hand, the internal circuit built in the VDP circuit 52 is configured to be individually resettable via the fourth reset path when necessary. The individually resettable internal circuits include the index table IDXTBL shown in FIG. 8(a), the data transfer circuit 72, the preloader 73, the display circuit 74, the drawing circuit 76, the SMC circuit 78, and the audio circuit SND, and the ICM circuit shown in FIG. 13.

[0184] The method for realizing an individual reset operation is as described at the bottom of Fig. 7(b). For example, the display circuit 74 is reset through the fourth reset path 4A → the third reset path by writing a first reset value to a predetermined VDP register RGij (system command register).

[0185] Also, each internal circuit (72, 73, 74, 76, SND, ···) of the VDP circuit 52 is individually reset (fourth reset path 4B) by (1) writing a setting value for specifying the target circuit to a first VDP register RGij (reset RQ register) and then (2) writing a second reset value to a predetermined VDP register RGij (system command register). Although not used in this embodiment, the audio circuit SND can be reset not only by the reset via the fourth reset path 4B but also by writing a reset value to a predetermined VDP register (circuit setting command register) (fourth reset path 4C).

[0186] Since this embodiment has the above configuration, not only does the entire VDP circuit 52 automatically return to the initial state when the power is turned on or when the program runs wild, but also each part can be returned to the initial state as needed to recover from abnormal situations. For example, when the drawing circuit 76 freezes due to no READ / WRITE access to the built-in VRAM 71 for a certain period, the drawing circuit 76 is individually initialized via the fourth reset path 4B (see ST16a in Fig. 22(d)). The same applies to the preloader 73 and the data transfer circuit 72. In the event of a predetermined abnormality, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in Fig. 29), and the data transfer circuit 72 is initialized via the fourth reset path 4B (see ST27 in Figs. 24 and 29).

[0187] Also, regarding the display circuit 74, when an underrun abnormality where the generation of display data cannot keep up continues at the display timing every 1 / 60 second, the display circuit 74 is individually initialized via the fourth reset path 4A or the fourth reset path 4B (see ST10c in FIG. 22). Note that these individual reset operations will be further described later with respect to the program processing described after FIG. 22.

[0188] As described above, the reset mechanism characteristic of this embodiment has been explained. When any of the reset paths 1 to 4 functions and the internal circuit of the composite chip 50 is reset, the set value of the VDP register RGij corresponding to the internal circuit returns to the same default value as after power-on.

[0189] Subsequently, returning to the internal configuration of the CPU circuit 51, the description of the characteristic circuit configuration will be continued. FIG. 9 is a block diagram showing the internal configuration of the CPU circuit 51 in a little more detail. The CPU circuit 51 includes many characteristic circuits in addition to the built-in RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described above.

[0190] First of all, the CPU circuit 51 has a separate CPU fetch bus for instructions and a CPU memory access bus for data, realizing the Harvard architecture. Therefore, the fetch operation in which the CPU core (graphics control CPU) 63 reads instructions from the memory and the memory access operation do not conflict, and high-speed processing is realized by continuous fetch operations.

[0191] Also, the CPU core 63 is configured to have a plurality (for example, 15) of register banks RB0 to RB14, and the use thereof can be selected. And in the operating state where the use of the register bank RBi is permitted, at the start of interrupt processing, the register values (each 32-bit length) of the built-in registers of the CPU (for example, 19) are automatically saved to the empty register bank RBi.

[0192] Also, when a predetermined return instruction is executed at the end of the interrupt process, for example, 19 pieces of saved data are automatically returned to the corresponding built-in register. Therefore, unlike the normal configuration, there is no need to execute the PUSH instruction 19 times at the start of the interrupt process and the POP instruction 19 times at the end of the interrupt process, enabling high-speed processing.

[0193] In addition, the CPU circuit 51 of the embodiment realizes Harvard cache operation by providing an instruction cache memory 67, an operand cache memory 89, and a cache controller 69, and further speeds up program processing by utilizing cached data when accessing the same address. Note that a bus bridge 65, a controller for peripheral bus (1), a controller for peripheral bus (2), and a controller for peripheral bus (3) are provided to appropriately connect the internal bus with peripheral bus (1), peripheral bus (2), and peripheral bus (3).

[0194] Next, in the circuit configuration of FIG. 9, the bus state controller 66 operates based on appropriate setting values in the operation control register REG and optimizes the memory READ operation and memory WRITE operation with various memory devices connected to the CPU circuit 51. The memory READ operation and memory WRITE operation are executed, for example, at the operation timings illustrated in FIG. 40. However, the operation timings of the address data output from the address bus (28 bits), the READ data read from the READ data bus (32 bits), the WRITE data written to the WRITE data bus (32 bits), and control signals such as chip select signals CS0 to CS7 are appropriately defined according to the characteristics of each memory device based on the setting values in the operation control register REG.

[0195] Since the READ data bus and the WRITE data bus are provided separately, high-speed operation based on the Harvard architecture described above is achieved. In this specification, the address bus (28 Bit), the READ data bus (32 Bit), and the WRITE data bus (32 Bit) may be collectively referred to as external buses for the purpose of distinguishing them from the internal buses shown in FIG. 9 and the peripheral buses (1) to (3).

[0196] FIG. 10 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and shows the address map for the rendering control CPU 63 accessed via the bus state controller 66. First, each of the address spaces CS0 to CS7 is defined to be up to 64 Mbytes (= 0x4000000H = 67108864).

[0197] As described above, the address spaces CS0 to CS7 mean external memories for the CPU circuit 51 that can define the memory type including volatility and the data bus width (8 / 16 / 32 bits), respectively. In this embodiment, as shown in FIGS. 9(b) and 10, the control memory (PROM) 53 is located in the address space CS0, the voice control register SRG of the voice processor 27 is located in the address space CS3, the internal registers and SRAM 39 of the clock circuit 38 are located in the address space CS4, the external DRAM (DDR) 54 is located in the address space CS5, the work memory 57 is located in the address space CS6, and the VDP register RGij is located in the address space CS7. Note that the description of the address spaces CS1 and CS2 is omitted.

[0198] Incidentally, as can be confirmed from FIG. 10, the address spaces CS0 to CS7 are reserved not only for the address values 0x00000000 to 0x1FFFFFFF (cache valid space), but also for the address values 0x20000000 to 0x3FFFFFFF (cache invalid space). This allows for the optional selection of whether to utilize the cache function by setting the cache to invalid based on the internal operation of the CPU circuit 51 when the address bit A29 = 1, and setting the cache to valid when the address bit A29 = 0.

[0199] Therefore, in this embodiment, among the entire 32-bit address information (bits A31 to A0), if the values of the remaining 31 bits (bits A31 to A30 and bits A28 to A0) are the same regardless of whether the value of bit A29 is 1 or 0, the same memory address will be indicated. For example, whether accessing the address 0x18000000 or the address 0x38000000 for a READ access, the same data will be read from the zero address of the work memory 57. When accessing the address 0x18000000 for a READ access, the read data is stored in the cache. FIG. 9(b) illustrates the cache valid / invalid access operation.

[0200] However, based on the set value in a predetermined operation control register REG, the cache operation for the instruction cache and / or the operand cache can also be invalidated. However, in this embodiment, after power-on, the cache operation for the instruction cache and the operand cache is enabled first, and then, if necessary, the cache operation is invalidated by accessing the cache invalid space.

[0201] Continuing the explanation of the memory map in Fig. 10, the internal memory space after the address 0x40000000 is where the bus state controller 66 does not function. The address range from 0xF0000000 to 0xFF3FFFFF is allocated to the cache address array space. Also, the address ranges from 0xFF400000 to 0xFFF7FFFF and from 0xFFFC0000 to 0xFFFFFFFF are allocated to the built-in peripheral modules, specifically, to the operation control register REG of the CPU circuit. Note that the address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

[0202] Continuing the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multifunction timer unit MTU are circuits that count external signals supplied to the CPU circuit 51, or count the counted clock obtained by multiplying or dividing the internal clock, and generate an interrupt signal or the like when the count result reaches a predetermined value. Although not particularly limited, in this embodiment, the multifunction timer unit MTU is utilized to generate a 1 mS interrupt signal and a 20 μS interrupt signal. Also, the multifunction timer unit MTU is utilized to implement a timing timer TM that measures the elapsed time after the CPU reset.

[0203] Next, the interrupt controller INTC is a circuit that receives internal interrupts from the VDP circuit 52, the DMAC circuit 60, the multifunction timer unit MTU, etc., and external interrupts such as IRQ_CMD, IRQ_SND, IRQ_RCT, and activates an interrupt process (interrupt handler) based on a pre-defined priority order. Here, IRQ_CMD is a command reception interrupt signal for receiving the control command CMD, IRQ_SND is an end interrupt signal indicating that the audio processor 27 has completed the initialization sequence, and IRQ_RCT is an alarm interrupt signal.

[0204] And in this embodiment, the interrupt priority is such that the command reception interrupt IRQ_CMD has the highest level, and below that, in the order of 20 μS interrupt → 1 mS interrupt → interrupts from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupt → IRQ_SND → IRQ_RCT (see Fig. 18(d)). Note that all of these are maskable interrupts, and the non-maskable interrupt NMI is output to the production control CPU 63 when the reference clock is not output from the oscillator OSC2 as described above.

[0205] And in any interrupt processing, the register values (each 32-bit long) of a plurality of built-in registers of the CPU are automatically saved in any available register bank RBi in the free state. And when a predetermined return instruction is executed at the end of the interrupt processing, the saved data is automatically restored to the corresponding built-in register.

[0206] Next, the DMAC circuit 60 will be described. The DMAC circuit 60 of the embodiment is a circuit that repeats data transfer a predetermined number of times in a predetermined DMA transfer mode for each predetermined data transfer unit from a transfer source (Source) to a transfer destination (Destination) based on the set value in a predetermined operation control register REG. Note that a plurality of channels of DMAC0 to DMACn having the same internal configuration are prepared and can operate in parallel. However, the priority is determined (channel 0 > ··· > channel n), and during the parallel operation in the channel arbitration operation mode, the operation of the DMACi with the highest priority is prioritized by channel arbitration at a predetermined timing.

[0207] As for the utilization of the DMAC circuit 60, for example, in the embodiment where the serial output port SO functions (refer to the broken line part in Fig. 10(a)), in the operation control register REG of the CPU circuit 51, the start address of the lamp / motor drive table (the first value of the transfer source address), the address of the input register of the serial output port SO (the fixed value of the transfer destination address), the data transfer unit (8 bits), and the number of transfers are specified. Then, upon receiving an operation start instruction in a predetermined operation control register REG, the DMAC circuit 60 performs DMA transfer of drive data to a predetermined transfer destination address while updating the transfer source address. And when all the DMA transfers are completed, a DMAC interrupt (operation end interrupt) is configured to occur.

[0208] This point is almost the same in the embodiment where the DMAC circuit 60 issues the display list DL (Figs. 25 and 29(c)). That is, the effect control CPU 63 sets the start address of the transfer source (DL buffer BUF), the address of the transfer destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, the number of transfers, and other conditions in a predetermined operation control register REG of the CPU circuit 51. Note that these points will be further described later with respect to Fig. 25.

[0209] By the way, generally, for the DMA transfer mode, there are considered a cycle steal transfer mode in which the DMA operation does not occupy the memory bus, such as releasing the bus control right during the unit operation (R operation / W operation) of the DMA transfer; a burst transfer (pipeline transfer) mode in which the bus control right is not released until the specified number of transfers is completed, such as continuous multiple R operations or W operations; a demand transfer mode in which the DMA operation continues while a DMA transfer request (demand) received from another device is active, and so on. However, the DMAC circuit 60 in this embodiment functions in a cycle steal transfer mode with at least one cycle of memory release period provided between the start of the read access (R operation) and the start of the write access (W operation) during the DMA transfer, so as not to interfere with the operation of the effect control CPU 63.

[0210] FIG. 11 is a drawing for explaining the cycle steal transfer operation (a1) and the pipeline transfer (a2). As shown in FIG. 11(a1), the DMAC circuit 60 that functions in the cycle steal transfer mode operates with at least one cycle between the start of a read access (R) and a write access (W) of a single data transfer. During this empty cycle, the bus can be used by the effect control CPU 63. As is clear from the comparison between FIG. 11(a1) and FIG. 11(a2), in the pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in the cycle steal transfer mode, the bus is released to the CPU for each read access, so the operation of the CPU is not significantly delayed.

[0211] And, for example, when issuing to the VDP circuit 52 of the display list DL, in an embodiment using the DMAC circuit 60, a single cycle data transfer unit (one operand) is set to 32×2 bits, and while appropriately increasing the source address of the built-in RAM 59 in which the display list DL is stored (+8 for each one operand transfer), a DMA transfer operation is executed on the transfer port register TR_PORT (see FIG. 13) of the data transfer circuit 72 specified by a fixed address.

[0212] As will be described later, in the embodiment, by adding a necessary number of NOP (no operation) commands to the display list DL, the overall data size is adjusted to a fixed value (for example, 4×64 = 256 bytes, or an integer multiple thereof), and the issuance of the display list DL is completed by repeating the one operand transfer of 32 bits × 2 times 32 times (or an integer multiple thereof). Note that even if the drawing circuit 76 executes the NOP command, it is in a no operation state and practically no change occurs.

[0213] Also, when classifying the operation mode regarding the DMA transfer conditions, generally, a single operand transfer (see FIG. 11(b1)), a continuous operand transfer (see FIG. 11(b2)), and a non-stop transfer (see FIG. 11(b3)) can be considered.

[0214] Here, single operand transfer means an operation mode in which, as shown in FIG. 11(b1), every time a DMA transfer request is given, the transfer of one operand is repeated, and a DMA interrupt request occurs when the byte count for counting the number of transferred bytes becomes zero. Next, continuous operand transfer means an operation mode in which, as shown in FIG. 11(b2), in one DMA request, the DMA transfer is repeated until the byte count becomes zero.

[0215] In these continuous operand transfer (b2) and single operand transfer (b1), channel arbitration is performed every time one operand transfer is completed, and the transfer of the current channel is continued on the condition that there is no DMA request for the channel with the highest priority (channel arbitration operation mode). Therefore, in this embodiment, the issuance of the display list DL to the VDP circuit, and the DMA transfer of the lamp drive data and the motor drive data adopt the single operand transfer method. And during parallel operation, for example, the optimal channel DMACi is used so that channel arbitration is performed in the order of motor data > display list DL > lamp data in terms of priority.

[0216] On the other hand, non-stop transfer is an operation mode in which channel arbitration is not executed, and as described in FIG. 11(b3), in one DMA request, the DMA transfer is continuously repeated until the byte count becomes zero. In this embodiment, in the memory section initialization process (SP8 in FIG. 16) at power-on, the program and data are DMA transferred in non-stop transfer.

[0217] Having described the CPU circuit 51 above, next, regarding the VDP circuit 52, a CGROM 55 for storing compressed data that is a component of still images and moving images constituting image rendering, an external DRAM (Dynamic Random Access Memory) 54 having a storage capacity of about 4 Gbit, a main display device DS1, and a sub-display device DS2 are connected to the VDP circuit 52. Note that the DRAM 54 is preferably composed of DDR3 (Double-Data-Rate3 SDRAM).

[0218] Here, the fact that the DRAM 54 receives the DDR clock generated based on the oscillation output (40 MHz) of the oscillator OSC2 is as shown in FIG. 14(b). Also, the DRAM 54 of the embodiment incorporates a Refresh Counter, and at the initial setting (SP4 in FIG. 16), the Self-Refresh Operation is enabled, so the refresh control operation by the production control CPU 63 is unnecessary.

[0219] Although not particularly limited, in this embodiment, the CGROM 55 is composed of a flash SSD (solid state drive) composed of a NAND-type flash memory with a storage capacity of about 62 Gbit, and is configured to acquire the necessary compressed data by serial transmission. Therefore, the problem of skew (difference in transmission speed for each bit data) that inevitably occurs in parallel transmission is solved, and an extremely high-speed transmission operation becomes possible. Although not particularly limited, in this embodiment, the CGROM 55 is accessed at high speed by the HSS (High Speed Serial) method compliant with Serial ATA.

[0220] Regardless of whether the HSS method compliant with Serial ATA is adopted or not, the NAND-type flash memory is mechanically more stable than a hard disk and enables high-speed access. On the other hand, since it is a sequential access memory, there is a problem with random access performance compared to DRAM and SRAM (Static Random Access Memory). Therefore, in this embodiment, a preload operation is executed to read a group of compressed data (CG data) into the DRAM 54 prior to the drawing operation, thereby realizing smooth random access to the CG data during the drawing operation. Incidentally, the access speed becomes slower in the order of built-in VRAM > external DRAM > CGROM.

[0221] Specifically, the VDP circuit 52 includes a control register group 70 in which various operation parameters defining the operation of the VDP (Video Display Processor) can be set by the production control CPU 63, a built-in VRAM (video RAM) 71 of about 48 megabytes used when generating image data to be displayed on the display devices DS1 and DS2, a data transfer circuit 72 that executes data transmission and reception between each part inside the chip and data transmission and reception with the outside of the chip, an index table IDXTBL that can specify the address information of the Source and Destination regarding the built-in VRAM 71, a preloader 73 that can execute a preload operation for READ access to the CGROM 55 prior to the drawing operation, a graphics decoder (GDEC) 75 that decodes (decompresses / expands) the compressed data read from the CGROM 55, a drawing circuit 76 that appropriately combines the still image data and video data after decoding (expansion) to generate image data for one frame of each of the display devices DS1 and DS2, a geometry engine 77 that generates a stereoscopic image by appropriate coordinate transformation as part of the operation of the drawing circuit 76, three systems (A / B / C) of display circuits 74A to 74C that read the image data of the frame buffers FBa and FBb generated by the drawing circuit 76 and can execute appropriate image processing in parallel, an output selection unit 79 that appropriately selects and outputs the outputs of the three systems (A / B / C) of display circuits 74, an LVDS unit 80 that converts the image data output by the output selection unit 79 into an LVDS signal, an SMC unit 78 capable of serial data transmission and reception, a CPUIF unit 81 that relays data transmission and reception with the CPUIF circuit 56, a CG bus IF unit 82 that relays data reception from the CGROM 55, a DRAMIF unit 83 that relays data transmission and reception with the external DRAM 54, and a VRAMIF unit 84 that relays data transmission and reception with the built-in VRAM 71 (see Fig. 8(a)). Note that an audio circuit SND is also built in.

[0222] Figure 8(b) shows the relationship between the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, and the VRAMIF unit 84, and the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. As shown, the CG data obtained from the CGROM 55 is transferred, for example, as preload data, via the data transfer circuit 72 and the DRAMIF unit 83, to the preload area of the external DRAM 54.

[0223] However, the above-described preloading operation is not an essential operation at all, and the data transfer destination is not limited to the external DRAM 54, and may be the built-in VRAM 71. Therefore, for example, in an embodiment where the preloading operation is not executed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAMIF unit 84 (Figure 8(b)).

[0224] Incidentally, in this embodiment, the built-in VRAM 71 requires an expansion area for the compressed data read from the CGROM 55, a frame buffer area for storing image data that specifies the ARGB information (32 bits = 8 × 4) of each of the W × H display pixels of the display device, and a Z buffer area for storing the depth information of each display pixel. In the ARGB information, A means 8-bit alpha plane data, and RGB means 8-bit data of the three primary colors.

[0225] Here, each of the above-described areas of the built-in VRAM 71 is indirectly accessed based on various instruction commands (such as the textures and sprites described above) described in the display list DL by the rendering control CPU 63. However, in the READ / WRITE access, it is cumbersome to specify the Destination address and the Source address of the built-in VRAM 71 one by one. Therefore, in this embodiment, in the initial process after CPU reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as an index space) required for the drawing operation is secured, and index numbers are assigned to each index space, enabling access based on the index numbers.

[0226] Specifically, after the CPU is reset, the built-in VRAM 71 is roughly divided into three types of memory areas, and a required number of index spaces are secured in each memory area. Then, by constructing an index table IDXTBL (see Fig. 12(a)) that associates and stores the index space with the index number, operations based on the subsequent index number are realized.

[0227] This index space needs to be (1) added after the initial processing or, conversely, (2) released. Therefore, a flag area FG that can determine whether it is possible to perform the addition / release process and whether the processes such as addition / release have actually been completed is provided in the index table IDXTBL during the operation of the production control CPU 63 for these addition / releases. The built-in VRAM 71 is roughly divided into three types of memory areas: two AAC areas (a1, a2) described below, a page area (b), and an arbitrary area (c). Corresponding to these three types of memory areas (a1, a2)(b)(c), the index table IDXTBL is divided into three sections (Fig. 12(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are secured as the AAC area (a), but it is not particularly limited, and only one of them may be sufficient. In the following description, when the first and second AAC areas (a1, a2) are collectively referred to, they may be referred to as the AAC area (a).

[0228] In the case of this embodiment, the built-in VRAM 71 is configured to be divisible into: (a) an AAC area in which an index space and its index number are automatically assigned by internal processing and which has a memory cache function; (b) a page area in which an index space can be secured within a range that is an integral multiple of a two-dimensional space of, for example, 4096 bits × 128 lines as a unit space; and (c) an arbitrary area in which a start address (space start address) STx and a horizontal size Hx can be arbitrarily set (see FIG. 12(b)). However, in order to smooth the internal operation of the VDP circuit 52, the space start address STx of the index space arbitrarily set in the arbitrary area (c) must have its lower 11 bits set to 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

[0229] After the CPU reset, the maximum value of the address space required for each and the area start address (lower 11 bits = 0) are defined, and an AAC area (a1), a second AAC area (a2), and a page area (b) are secured, and the remaining memory area becomes the arbitrary area (c). In order to smooth the internal operation of the VDP circuit 52, the maximum value of the address space of the AAC area is defined in units of 2048 bits, and the maximum value of the address space of the page area is an integral multiple of the above-mentioned unit space of 4096 bits × 128 lines.

[0230] Next, the required number of index spaces are set in each of the areas (a1, a2), (b), and (c) secured in this way. When using the arbitrary area (c), in order to smooth the internal operation of the VDP circuit 52, the horizontal size Hx of the index space for handling two-dimensional data can be arbitrarily set as a multiple of 256 bits, while its vertical size is a fixed value (for example, 2048 lines).

[0231] In any case, the first and second AAC regions (a1, a2) are automatically assigned an index space and an index number by the VDP circuit 52. For example, if the decoding destination is specified as the AAC region (a) by the SETINDEX command of the texture setting command, in the TXLOAD (texture load) command for reading CG data from the CGROM 55, it is only necessary to specify the source address of the CGROM 55 and the horizontal and vertical sizes after expansion (decoding). Therefore, in this embodiment, for still images (textures) such as characters that temporarily appear during a preview effect or I-stream videos, the decoding destination is set to the AAC region (a).

[0232] All of these AAC regions (a) are provided with a memory cache function. For example, when the same texture of the CGROM 55 is read into the AAC region (a) multiple times, the decoded data cached in the AAC region (a) can be utilized for the second and subsequent times, and redundant READ access and decoding processing can be suppressed. However, when the AAC region (a) is exhausted, the old data is automatically destroyed. Therefore, in this embodiment, when using the AAC region (a), in principle, the first AAC region (a1) is used, and only specific textures that are repeatedly used are acquired in the second AAC region (a2).

[0233] Examples of textures that are repeatedly used include, for example, characters that repeatedly appear during a predetermined preview effect and background images when the background screen is constructed with still images. In such a case, after setting the decoding destination to the second AAC region (a2) by the SETINDEX command of the texture setting command and decoding the textures such as characters and background images into the second AAC region (a2) by the TXLOAD command, the decoding result is protected by not using the second AAC region (a2).

[0234] After that, if the same TXLOAD command is executed to re-acquire the acquired texture after specifying the decoding destination as the second AAC area (a2) using the SETINDEX command, the acquired texture will hit the cache, so the READ access to CGROM55 and the time required for the decoding process can be eliminated. As will be described later, such a cache hit function is also exhibited by preloaded data pre-read into the preload area. However, the preloaded data that hits the cache in the preload area is compressed data before decoding, while the significance lies in the fact that the data that hits the cache in the AAC area is the decompressed data after decoding.

[0235] By the way, a texture generally refers to a concept such as the texture and feel of an object's surface. However, in this specification, it is used as a concept that includes not only sprite image data constituting a still image, image data constituting a single frame of a video, and image data attached to drawing primitives such as triangles and rectangles, but also image data after decoding. When copying image data (hereinafter referred to as moving for convenience) inside the built-in VRAM71, the SETINDEX command of the texture setting command is used to set the source image data as a texture, and then the SPRITE command is executed.

[0236] Note that when the SPRITE command is executed, the source image data of the source is drawn in the virtual drawing space shown in Fig. 12(c) formally. However, if the correspondence relationship between the drawing area in the virtual drawing space actually drawn on the display device and the index space serving as the frame buffer is set in advance by the environment setting commands (SETDAVR, SETDAVF) or the texture setting commands (SETINDEX), for example, by drawing in the virtual drawing space by the SPRITE command, the source image data of the source will be drawn in a predetermined index space (frame buffer) (see Fig. 12(c)).

[0237] In any case, in this embodiment, the built-in VRAM 71 is roughly divided into an AAC region (a1, a2), a page region (b), and an arbitrary region (c), and an appropriate number of index spaces can be secured for each, and each index space is specified by an independent index number for each of the regions (a), (b), and (c). The index number is, for example, 1 byte long, and for the page region (b) and the arbitrary region (c) (excluding the AAC region (a) automatically assigned by the internal circuit), the production control CPU 63 can freely assign the index number within the range of 0 to 255.

[0238] Therefore, in this embodiment, as shown in FIG. 12(a), for the display device DS1, a pair of frame buffers FBa are secured in the arbitrary region (c), and index numbers 255 and 254 are assigned to both of the double buffer structures. That is, as the frame buffer FBa for the main display device DS1, an index space 255 and an index space 254 that are toggled and used are secured. Although not particularly limited, these index spaces 255 and 254 have a horizontal size of 1280 corresponding to the number of horizontal pixels of the display device DS1. Since each pixel is specified by 32-bit ARGB information, the horizontal size 1280 means 32 × 1280 = 40960 bit (a multiple of 256 bit).

[0239] Also, for the display device DS2, another pair of frame buffers FBb are secured in the arbitrary region (c), and index numbers 252 and 251 are assigned to both of the double buffer structures. That is, as the frame buffer FBb for the sub-display device DS2, an index space 252 and an index space 251 are secured. These index spaces 252 and 251 have a horizontal size of 480 corresponding to the number of horizontal pixels of the display device DS2. Also in this case, since each pixel is specified by 32-bit ARGB information, the horizontal size 480 means 32 × 480 = 15360 bit (a multiple of 256 bit).

[0240] Note that securing the frame buffers FBa and FBb in the arbitrary area (c) is because the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels). As described above, if it matches the horizontal pixel numbers of the display devices DS1 and DS2, there will be no waste in the secured area. On the other hand, in the page area (b), only horizontal / vertical sizes that are integer multiples of the unit space of 128 pixels × 128 lines can be set.

[0241] However, the two-dimensional index space secured in the arbitrary area (c) has a fixed vertical size (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area with a horizontal size of 1280 × a vertical size of 1024 becomes the valid data area for the main display device DS1. The same applies to the sub-display device DS2. In the frame buffer FBb, only the area with a horizontal size of 480 × a vertical size of 800 becomes the valid data area for the sub-display device DS2 (see FIGS. 12(c) and 22(e)).

[0242] This point will be further described later. In any case, the frame buffers FBa and FBb are used alternately by each double buffer (255 / 254, 252 / 251) as the drawing area for the drawing circuit 76, and also used alternately by each double buffer (255 / 254, 252 / 251) as the display area for the display circuits 74A and 74B. In this embodiment, since the Z buffer for storing the depth information of the display pixels is not used, there is a missing number (253). However, when the Z buffer is used, the index spaces 253 and 250 with index numbers 253 and 250 in the arbitrary area (c) become the Z buffers for the display device DS1 and the display device DS2.

[0243] Also, in this embodiment, when an additional index space (memory area) is secured in an arbitrary area (c) where frame buffers FBa and FBb are secured, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, an index space (0) is secured in the arbitrary area (c) as a work area for a preview effect in which an effect image composed of characters and other still images appears in a part of the display screen in an appropriate rotation posture as needed.

[0244] However, the use of the work area is not essential, and instead of the arbitrary area (c), an index space as a work area may be secured in the page area (b). If the page area (b) is used, an index space having a multiple dimension of a square unit space with a horizontal size of 12 8 (=4096 bit) × vertical size of 128 can be secured, which is suitable for handling small effect images.

[0245] By the way, in this embodiment, the background image is also composed of a video including a moving image, and the image effect is realized almost only by the moving image. In particular, during a variable effect, a large number (usually 10 or more) of moving images are drawn simultaneously. These moving images are all stored in the CGROM 55 in a compressed state as a series of moving image frames, and are classified into an I-stream moving image composed only of I-frames and an IP-stream moving image composed of I-frames and P-frames. Here, an I-frame (Intra coded frame) means a frame that compresses the input image as it is independently of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame that performs forward prediction coding, and an I-frame or P-frame located in the past in terms of time is required.

[0246] Therefore, in this embodiment, for the IP-stream moving image, it is expanded not in the AAC area (a) where there is a concern about destruction of old data, but in the page area (b). That is, in the page area (b) where an index space having a multiple dimension of a horizontal size of 128 × vertical size of 128 can be secured, a large number of index spaces (IDX0 to IDX NTo ensure this, a series of video frames are decoded using the same index space IDXi corresponding to each video MVi. That is, video MV1 is expanded into index space IDX1, video MV2 is expanded into index space IDX2, and similarly, video MVi is configured to be expanded into index space IDXi.

[0247] More specifically for video MVi, after specifying in advance by the SETINDEX command that "the decoding destination of the IP stream video MVi is the index space (i) with index number i in the page area (b)", the TXLOAD command for acquiring one video frame of the IP stream video MVi is executed.

[0248] Then, one video frame (any one of the series of video frames) on the CGROM55 specified by the TXLOAD command is first acquired in the AAC area (a), and then, by the automatically started GDEC (Graphics Decoder) 75, the acquired video frame is decoded and expanded into the index space (i) of the page area (b).

[0249] On the other hand, in this embodiment, for the I-stream video, it is treated the same as a still image. By the SETINDEX command, it is specified that "the decoding destination of the I-stream video MVj is the first AAC area (a1)", and the TXLOAD command is executed. As a result, the video frame is acquired in the first AAC area (a1), and then, the automatically started GDEC75 expands the decoded data in the first ACC area (a1). As described above, since the index space of the AAC area (a) is automatically generated, there is no need to specify an index number. Note that the expansion volume required for the index space, that is, the horizontal size and vertical size of the decoded texture (video frame), are specified by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b).

[0250] Incidentally, the IP stream video MVi and the I stream video MVj are generally composed of N video frames (I frames and P frames). Therefore, in the TXLOAD command, for example, the Source address of the k-th (1 ≦ k ≦ N) video frame stored in the CGROM55 and the horizontal and vertical sizes after expansion are specified. Although not limited in any way, in an embodiment where still images are hardly used, most of the 48 M bytes of the address space of the built-in VRAM71 (about 30 M bytes) are allocated to the page area (b). And in an embodiment where still images are hardly used, only the first AAC area (a1) is secured as the AAC area, the second AAC area (a2) is not secured, and the cache hit function of the above-mentioned AAC area is not utilized either.

[0251] Note that in order to speed up the decoding process of the compressed video data, it is also conceivable to provide a dedicated GDEC (Graphics Decoder) circuit. And if the dedicated GDEC circuit is built into the VDP circuit 52, in the decoding process of the compressed video data composed of N compressed video frames, it is sufficient to instruct the GDEC circuit with the start address of the video compressed data. Therefore, it is not necessary to specify the start address for each of the N compressed video frames.

[0252] However, if a plurality of such dedicated GDEC circuits are built in for each compression algorithm, the internal configuration of the VDP circuit 52 will become even more complicated. Therefore, in this embodiment, it is a software GDEC, and for data such as IP stream video, I stream video, still images, and other α values, the decoding process is realized by software processing corresponding to each compression algorithm. Note that the difference in processing time between hardware processing and software processing is not much of a problem. The processing time that becomes a problem is solely the access (READ) time from the CGROM55.

[0253] Next, returning to FIG. 8(a) and continuing the explanation, the data transfer circuit 72 is a circuit that performs a data transfer operation between the resources (storage media) inside the VDP circuit and an external storage media in a DMA (Direct Memory Access) manner, using these as the transfer source port or the transfer destination port. FIG. 13 is a block diagram showing the internal configuration of this data transfer circuit 72 together with related circuit configurations.

[0254] As shown in FIG. 13, the data transfer circuit 72 is configured to transmit and receive data with the CGROM 55, the DRAM 54, and the built-in VRAM 71 via an integrated connection bus ICM having a router function. Note that the CGROM 55 and the DRAM 54 are accessed via the CG bus IF unit 82 and the DMAMIF unit 83.

[0255] On the other hand, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and the preloader 73 via a transfer port register TR_PORT built into the data transfer circuit 72. Note that although the CPU circuit 51 and the data transfer circuit 72 are connected bidirectionally, when issuing the display list DL, the transfer port register TR_PORT functions as a data write port that receives one unit of data constituting the display list DL. Note that the write unit (one unit data length) of the transfer port register TR_PORT is 32 bits corresponding to the FIFO structure of the CPU bus control unit 72d.

[0256] As shown in the figure, the effect control CPU 63 can perform a WRITE access to the transfer port register TR_PORT via the CPUIF unit 81. On the other hand, when using the DMAC circuit 60, the DMAC circuit 60 directly performs a WRITE access to the transfer port register TR_PORT. Then, a series of instruction commands written to the transfer port register TR_PORT (that is, the instruction command sequence constituting the display list DL) is configured to be automatically accumulated in the CPU bus control unit 72d having a FIFO buffer with a FIFO structure (32 bits × 130 stages) in 32-bit units.

[0257] Also, this data transfer circuit 72 executes data transmission and reception operations through transmission paths of three channels ChA to ChC, and includes a ChA control circuit 72a (N = 130 stages) having a FIFO buffer with a FIFO structure (64 bits × N stages), a ChB control circuit 72b (N = 1026 stages), and a ChC control circuit 72c (N = 130 stages).

[0258] Then, the instruction command sequence (display list DL) stored in the CPU bus control unit 72d is transferred to the drawing circuit 76 or the preloader 73 based on the set value to the data transfer register RGij (a type of various control registers 70) by the rendering control CPU 63. As shown by the arrows, the display list DL is configured to be transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b and to the preloader 73 via the FIFO buffer of the ChC control circuit 72c.

[0259] In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL, and the data stored in the FIFO buffer of the CPU bus control unit 72d is transferred to the display list analyzer of the drawing circuit 76 or the preloader 73 as a part of the display list DL via the FIFO buffers of the ChB control circuit 72b and the ChC control circuit 72c, respectively.

[0260] Then, the drawing circuit 76 starts a drawing operation based on the transferred display list DL. On the other hand, the preloader 73 executes a necessary preloading operation based on the transferred display list DL. By the preloading operation, the CG data in the CGROM 55 is pre-read into the preloaded area secured in the DRAM 54, and a display list DL (hereinafter referred to as a rewritten list DL') with the source address of the texture changed for commands such as the TXLOAD command is stored in the DL buffer area BUF' secured in the DRAM 54.

[0261] On the other hand, for data transfer between storage media such as the CGROM 55, DRAM 54, and built-in VRAM 71, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function. Also, when accessing the built-in VRAM 71 that requires the address information of the index table IDXTBL, the IDXTBL access arbitration circuit 72f functions. Specifically, upon confirmation, the ChA control circuit 72a functions, for example, in cases where (a) the compressed data of the CGROM 55 is transferred to the built-in VRAM 71, (b) the compressed data of the CGROM 55 is preloaded (read-ahead) and transferred to the external DRAM 54, or (c) the read-ahead data in the preload area is transferred to the built-in VRAM 71.

[0262] Here, the ChA control circuit 72a is configured to be operable in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the operations (a) to (c) described above can be executed in parallel with the issue operation of the display list DL (ST8 in FIG. 22, PT11 in FIG. 27) and the transfer operation of the rewrite list DL' (PT10 in FIG. 27). Also, the ChB control circuit 72b and the ChC control circuit 72c can be executed simultaneously. For example, the process of step PT10 in FIG. 27 where the ChB control circuit 72b functions and the process of step PT11 where the ChC control circuit 72c functions can be executed in parallel. However, since the transfer port register TR_PORT is single, at the timing when either one (72b / 72c) is using the transfer port register TR_PORT, the other one (72c / 72b) cannot access the transfer port register TR_PORT.

[0263] During the operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates (Arbitration) data transmission with each memory element (CGROM55, DRAM54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates data communication with the built-in VRAM71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the case of the embodiment where the pre-loader 73 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b (see Fig. 28(b)).

[0264] As described above, the data transfer circuit 72 of this embodiment realizes high-speed data transfer between a data transfer source arbitrarily selected from various memory resources (Resource) and a data transfer destination arbitrarily selected from various memory resources (Resource). As can be confirmed from Fig. 13, the memory resources in which the data transfer circuit 72 functions include not only the built-in VRAM71 but also external devices via the CPUIF unit 56, the CG bus IF unit 82, and the DRAMIF unit 83.

[0265] And the data transfer amount between the external device in which the ChA control circuit 72a functions, such as the amount of data to be acquired at one time from the CGROM55 (memory sequential READ), is huge compared to the case of the display list DL in which the ChB control circuit 72b and the ChC control circuit 72c function, and the data transfer amounts are greatly different from each other.

[0266] Here, regarding these various data transfers, it may be considered to configure the unit data amount and the total transferred data amount so that they can be finely set. However, this would complicate the control operations inside the VDP and hinder the smooth transfer operation. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total transferred data amount is restricted to be an integer multiple of the minimum data amount DTmin, thereby realizing a high-speed and smooth data transfer operation. Although not particularly limited, in the data transfer circuit 72 of the embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total transferred data amount is restricted to an integer multiple of this.

[0267] Therefore, the instruction command sequence of the display list DL accumulated in the FIFO buffer of the CPU bus control unit 72d for every 32 bits is transferred to the ChB control circuit 72b and the ChC control circuit 72b at the timing when the total amount reaches the minimum data amount Dmin, and is accumulated in their respective FIFO buffers.

[0268] The display list DL is composed of a series of instruction commands. In this embodiment, corresponding to the write unit (32 bits) of the transfer port register TR_PORT, the display list DL is composed only of instruction commands whose command length is an integer N times (N>0) of 32 bits. Therefore, the drawing circuit 76 and the preloader 73 that receive the instruction commands of the display list DL via the data transfer circuit 72 can quickly and smoothly start the command analysis process (DL analyze). Note that the command length that is an integer N times of 32 bits does not necessarily mean that all of them are significant bits, and includes don't care bits, meaning an integer N times of 32 bits.

[0269] Next, the pre-loader 73 will be described. As briefly described above, the pre-loader 73 interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b), and transfers the CG data on the CGROM 55 referred to by the TXLOAD command to the pre-load area of the DRAM 54 in advance. Also, regarding this TXLOAD command, the pre-loader 73 stores a rewritten list DL' in which the reference destination of the CG data is rewritten to the address after transfer, in the DL buffer BUF' of the DRAM 54. Note that the DL buffer BUF' and the pre-load area are secured in advance during the initial processing after CPU reset (SS3 in FIG. 21).

[0270] Then, at the start of the drawing operation of the drawing circuit 76, the rewritten list DL' is transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e of the data transfer circuit 72 and the ChB control circuit 72b. Then, the drawing circuit 76 executes the drawing operation based on the rewritten list DL'. Therefore, based on the TXLOAD command or the like, the CG data that should originally be obtained from the CGROM 55 is obtained from the pre-load area of the DRAM 54 as pre-loaded data that has been pre-read into the pre-load area. In this case, the pre-loaded data can be repeatedly used unless it is overwritten and erased, and the pre-loaded data that has a cache hit in the pre-load area is repeatedly reused.

[0271] In this embodiment, since the pre-load area is set in the external DRAM 54 having a sufficient storage capacity, the above cache hit function functions effectively. Also, since the storage capacity of the external DRAM 54 is large, for example, multiple pre-loads for pre-loading CG data for a plurality of frames at once are also possible. That is, regarding the operation period of the pre-loader 73, multiple pre-loads are realized by appropriately setting the operation period of a series of pre-load operations including the pre-reading operation of the CG data within a range that is an integer multiple of the operation cycle δ during the intermittent operation of the VDP circuit 52.

[0272] However, in the following description, for the sake of convenience, an example without multiple preloads will be described. Therefore, the preloader 73 of the example will complete the preload operation for one frame during one operation cycle (δ). As will be described later with reference to FIG. 22, in this example, the operation cycle δ during the intermittent operation of the VDP circuit 52 is 1 / 30 second, which is twice the period of the vertical synchronization signal of the display device DS1.

[0273] Next, the drawing circuit 76 sequentially analyzes the instruction command sequences of the display list DL and the rewrite list DL' transferred via the data transfer circuit 72, and in cooperation with the graphics decoder 75, the geometry engine 77, etc., draws the images for one frame of each of the display devices DS1 and DS2 on the frame buffer formed in the VRAM 71.

[0274] As described above, in the example where the preloader 73 functions, the reference destination of the CG data in the rewrite list DL' is not the CGROM 55 but the preload area set in the DRAM 54. Therefore, sequential access to the CG data that occurs during the execution of drawing by the drawing circuit 76 can be quickly executed, and even for high-resolution videos with intense movement, drawing can be performed without problems. That is, according to this example, as the CGROM 55, an inexpensive SATA module can be utilized while performing complex and advanced image rendering.

[0275] By the way, regardless of whether the preloader 73 functions or not, when data corruption occurs during the transfer of the display list DL or the rewrite list DL', the drawing circuit 76 cannot detect this. Also, due to the influence of noise, etc., the drawing circuit 76 may freeze and the READ / WRITE access to the built-in VRAM 71 may abnormally stop. Therefore, in this example, when the drawing circuit 76 detects an unreasonable instruction command (bit sequence that cannot be analyzed) or when there is no READ / WRITE access to the built-in VRAM 71 for a certain period, it is configured to generate a drawing abnormality interrupt (the drawing abnormality interrupt is in an enabled state). This point will be described later with reference to FIG. 22(d).

[0276] Next, as described with reference to FIG. 12, the frame buffer FB secured in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a reading area, and the two areas are used by alternately switching their uses. Also, in this embodiment, since two display devices DS1 and DS2 are connected, as shown in FIG. 12, two-section frame buffers FBa / FBb are secured. Therefore, the drawing circuit 76 draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS1 and also draws image data for one frame in the drawing area (writing area) of the frame buffer FBa for the display device DS2. When image data is being written in the drawing area, the display circuit 74 reads out the image data in the other reading area (display area) and outputs it to each of the display devices DS1 and DS2.

[0277] The display circuit 74 is a circuit that reads out the image data of the frame buffers FBa and FBb, performs final image processing, and then outputs it (see FIG. 14(a)). The final image processing includes, for example, scaling processing by a scaler that enlarges / shrinks an image, delicate color correction processing, and dithering processing that minimizes the quantization error of the entire image. Then, the digital RGB signal (a total of 24 bits) that has undergone these image processes is usually output together with a horizontal synchronization signal HS, a vertical synchronization signal VS, and the like.

[0278] As shown in FIG. 14(a), in this embodiment, three systems of display circuits A / B / C that execute the above operations in parallel are provided, and each display circuit 74A to 74C reads out the image data of the corresponding frame buffers FBa / FBb / FBc and executes the above final image processing. However, in this embodiment, since there are two display devices, the frame buffer FBc is not secured and the display circuit 74C does not function.

[0279] Here, when checking the specifications of the main display device DS1, the main display device DS1 needs to receive adjacent odd pixels (ODD) and even pixels (EVEN) in the horizontal direction through separate LVDS (Low Voltage Differential Signaling) transmission lines at the receiving unit RV (RVa + RVb). Also, the frequency of the operation clock CK of the main display device DS1 needs to be set to about 40 to 70 MHz (typical value 54 MHz), and it is necessary to set the horizontal / vertical standby times WTh / WTv so that (WTh + 640) × (WTv + 1024) / 54 MHz ≒ 1 / 60 second. Furthermore, at the timing of outputting image data (ODD / EVEN signals) to the main display device DS1, it is necessary to output an active-level data valid signal ENAB.

[0280] Therefore, the display circuit 74A needs to output signals that satisfy all of the above specifications. FIGS. 15(a) to 15(e) illustrate various signals output from the display circuit 74A. First, it is necessary to determine the frequency of the dot clock (LVDS clock) DCK. In this embodiment, since the main display device DS1 operates with an operation clock CK of a typical value of 54 MHz, correspondingly, the design dot clock DCK (in the VDP circuit 52) is set to 108 MHz (= 54 × 2).

[0281] This is because in a display panel LCD of 1280 dots horizontally × 1024 lines vertically (see FIG. 15(f)), two adjacent pixels on the left and right are processed all at once in synchronization with the 54 MHz operation clock CK. Substantially, it is equivalent to operating with a dot clock DCK of 108 MHz.

[0282] Then, various operation parameters that define the operation of the display circuit 74A are defined based on the dot clock DCK with a frequency of 108 MHz. First, it is necessary to set the horizontal / vertical standby times WTh / WTv so that (WTh + 640) × (WTv + 1024) / 54 MHz ≒ 1 / 60 second. However, as the operation parameters WTh and WTv for the display circuit 74A, it is necessary to satisfy (WTh + 1280) × (WTv + 1024) / 108 MHz ≒ 1 / 60 second.

[0283] Also, regarding the horizontal / vertical standby times WTh / WTv, it is necessary to consider the allowable range in the specifications of the display device DS1. Therefore, in this embodiment, the horizontal standby time WTh is counted with the dot clock DCK of 108 MHz and set to 382 clocks, and the vertical standby time WTv is set to 59 lines. Therefore, the time required for updating the image of one frame is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) becomes 1 / 60 second.

[0284] This relationship defines the update period FR [seconds] of the display device DS1. Using the frequency F of the dot clock DCK, the number of cycles THc of the horizontal synchronization, and the number of lines TVl of the vertical synchronization described later, FR = THc × TVl / F dot will be obtained. Here, if the update period FR is too long, there is a risk of abnormalities such as flicker. On the other hand, if the update period FR is too short, the display device cannot execute normal update processing. Therefore, it should be defined within the range of 0.95 / 60 < FR [seconds] < 1.05 / 60. dot

[0285] ​In response to this setting, in the image update operation of each line, the data valid signal ENAB has a standby time WTh (= 382 / 108 MHz) corresponding to 382 clocks at the L level, and then an active section (= 1280 / 108 MHz) corresponding to 1280 clocks becomes the active level (H) (Fig. 15(c)). As shown in Fig. 15(d) and Fig. 15(e), in the active section of the data valid signal ENAB, for 1280 pixels per line, image data is output so that the image update operation is completed in a predetermined time (11.85 μS = 1280 / 108 MHz). That is, 1280 pixel data (Pixel Data) is output in synchronization with 1280 dot clocks DCK. Note that the display device DS1 displays a full-color image with a color matching degree of 8 ×2 8 ×2 8 so the pixel data of one pixel is 3 × 8 bits long.

[0286] By the way, in this embodiment, although not required in the main display device DS1, the vertical synchronization signal VS and the horizontal synchronization signal HS are output. The vertical synchronization signal VS is output within the vertical standby time WTv, and the horizontal synchronization signal HS is output within the horizontal standby time WTh. In Fig. 15(a) and Fig. 15(b), for convenience of understanding, each operation cycle is shown. In Fig. 15(f), at the upper left and lower right vertices of the rectangular frame specified by TH × TV (= 1083 × 1662 clocks), a ○ mark is shown and described as "start of display operation" and "end of display operation", but this ○ mark means "start of V blanking" that defines the operation cycle of the display circuit 74A started every 1 / 60 second. Since the 1083 × 1662 clocks defining the display operation match 1 / 60 second, the elapsed time from the "start of display operation" to the "end of display operation" (the operation cycle of the display circuit 74A) is 1 / 60 second. Note that the "start of V blanking" will be described later based on Fig. 22.

[0287] Returning to FIG. 14 and continuing the description, the output selection unit 79 of the embodiment divides the output signal of the display circuit 74A into a dual link that divides the 108 MHz dot clock DCK by two, and transmits it to the LVDS unit 80a and the LVDS unit 80b, respectively (see FIGS. 14(a) and 5). Then, each of the LVDS units 80a and 80b converts the image data (a total of 24-bit digital RGB signal) into first and second LVDS signals, and adds a pair of clock signals (54 MHz = 108 / 2) to this, and outputs them as a total of five pairs of differential signals LVDS1 and LVDS2 to the main display device DS1 via two paths (see FIGS. 14(a) and 4).

[0288] As described above, in the main display device DS1, since the ODD signal for one pixel and the EVEN signal for the adjacent pixel are processed at the same timing, the frequency of the substantial operation clock CK matches the 108 MHz dot clock DCK output by the display circuit 74A.

[0289] As described above, the display circuit 74A that generates the image to be transmitted to the main display device DS1 has been described. The display circuit 74B generates the image data to be transmitted to the sub-display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB unit 80c via the output selection unit 79, and is transmitted to the sub-display device DS2 together with the vertical synchronization signal VS and the horizontal synchronization signal HS.

[0290] Note that together with the synchronization signals VS and HS, the data valid signal ENAB is also transmitted via the digital RGB unit 80c. Of course, these signals are transmitted as continuous signals, not discrete values as in the case of the LVDS transmission line (see FIG. 14(a)).

[0291] Incidentally, in the case of this embodiment, each display circuit 74A to 74B is provided with underrun counters URCNTa to URCNTc that count Underrun abnormalities where the generation of display data could not keep up with the display timing (see FIG. 15). And the counter values of these underrun counters URCNTa to URCNTc are configured to be automatically incremented for each VBLANK when an underrun abnormality occurs.

[0292] Next, the SMC unit 78 (Serial Management Controller) is a composite controller incorporating an LED controller and a Motor controller. And while outputting an LED drive signal and a motor drive signal in synchronization with a clock signal to an LED / Motor driver (driver IC incorporating a shift register) mounted on an external board, it is configured to be able to output a latch pulse at an appropriate timing.

[0293] Regarding the internal circuit of the above-described VDP circuit 52 and its operation, the operation content to be executed by the internal circuit is defined by operation parameters (set values) set by the production control CPU 63 in the control register group 70, and the execution state of the VDP circuit 52 can be specified by reading the operation status value of the control register group 70. The control register group 70 means a number of VDP registers RGij mapped to an address space of about 1 Mbyte (0 to FFFFFFH) on the memory map of the production control CPU 63, and the production control CPU 63 executes a WRITE (setting) operation of operation parameters and a READ operation of the operation status value via the CPUIF unit 81 (see FIG. 8(b)).

[0294] In the control register group 70 (VDP register RGij), there are a "system control register" into which initial setting values related to system operations such as interrupt operations are written, an "index table register" that determines the AAC area (a) and page area (b) in the built-in VRAM and is related to constructing or changing the index table IDXTBL, a "data transfer register" into which setting values related to data transfer processing by the data transfer circuit 72 between the internal circuits of the production control CPU 63 and the VDP circuit 52 are written, a "GDEC register" that specifies the execution status of the graphics decoder 75, a "drawing register" into which setting values related to instruction commands and the drawing circuit 76 are written, a "preloader register" into which setting values related to the operation of the preloader 73 are written, a "display register" into which setting values related to the operation of the display circuit 74 are written, an "LED control register" into which setting values related to the LED controller (SMC unit 78) are written, a "motor control register" into which setting values related to the Motor controller (SMC unit 78) are written, and an "audio control register SRG" into which setting values related to the audio circuit SND are written. However, in this embodiment, the audio circuit SND is not utilized.

[0295] In any case, in the following description, one or more registers RGij included in the control register group 70 may be referred to by the above individual names or collectively as the VDP register RGij. In any case, the production control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate setting values into a predetermined VDP register RGij. Specifically, the production control CPU 63 realizes a predetermined image production based on the display list DL updated at appropriate time intervals and the setting values for a predetermined VDP register RGij. In this embodiment, since the production control CPU 63 is responsible for lamp production and motor production as well, the VDP register RGij includes an LED control register and a motor control register.

[0296] Subsequently, a unified production control operation for image production, audio production, motor production, and lamp production realized by the composite chip 50 incorporating the above-described CPU circuit 51 and VDP circuit 52 will be described.

[0297] In the case of this embodiment, the operation of the composite chip 50 is started by a power-on reset operation (see Fig. 16(a)) due to power-on or abnormal reset, and after passing through an initial setting process (SP1 to SP9) by an initial setting program (boot program) Pinit, it is configured to shift to a main control process (SP10) by a production control program Main and an interrupt processing program (vector handler) Vopt. Regarding the main control process, the processing content of its introduction part is described in Fig. 18(a), and the processing content of the main body part is described in Fig. 22(a). Note that the process of step SP27 in Fig. 18 does not include the processes of steps SS1 to SS3 in Fig. 21(a).

[0298] Based on the above, the power-on reset operation will be described with reference to Fig. 16(a). When the system reset signal SYS maintains the L level for a predetermined period (assert period) such as at power-on, all operation control registers REG and all VDP registers RGij are automatically set to predetermined default values.

[0299] Then, thereafter, when the system reset signal SYS changes to the H level (negative level) (see the timing T1 in Fig. 6(d)), in this embodiment, the operation of the timing timer TM (Fig. 9(a)) is started (SP1) in order to measure the elapsed time after the CPU reset. Also, 32-bit data from the head address of the address space CS0 is set to the program counter PC of the production control CPU 63, and the subsequent 32-bit data is configured to be set to the stack pointer SP (SP1). Note that in Figs. 10 and 17(c), the head area of the memory that stores the initial values of the program counter PC and the stack pointer SP is referred to as the vector table VECT.

[0300] As shown in FIG. 16(b), in this vector table VECT, a vector number that identifies a priority, an interrupt cause, etc. and address information are stored in correspondence. The smaller the vector number, the higher the priority. For example, vector number 11 is a non-maskable interrupt (NMI), and as the address information, the start address of the interrupt processing program executed at the time of NMI interrupt is stored. Also, vector number 64 is an internal interrupt from the VDP (VDP_IRQ0), and as the address information, the start address of the interrupt processing program executed at the time of VDP_IRQ0 interrupt is stored.

[0301] Since the interrupt priorities are as shown in FIG. 18(d), in the columns of vector numbers smaller than vector number 64, the start addresses of the interrupt processing programs for the control command reception interrupt IRQ_CMD, the 20 μS timer interrupt, and the 1 mS timer interrupt are each stored. On the other hand, in the columns of vector numbers larger than vector number 64, the start addresses of the interrupt processing programs (such as IRQ_SND, IRQ_RTC) with lower priorities than VDP_IRQ 1 are each stored.

[0302] Also, in the vector table VECT, for vector number 0 and vector number 1, the set values that should be automatically set to the program counter and the stack pointer of the CPU at the time of power-on reset are defined. As shown in FIG. 16(b), in this embodiment, as the internal operation at the time of power-on reset (reset assert period), the 4-byte data "****" is set to the program counter PC, and the 4-byte data "++++" is set to the stack pointer SP. Note that "****" is the start address value of the initial setting program Pinit (SP1 to SP9 in FIG. 16) that is stored non-volatilely in the address space CS0, and "++++" is the address value of the tip or the end of the stack area that functions in a LIFO (Last-In First-Out) manner and is secured in the built-in RAM59.

[0303] Note that in this embodiment, since the register bank RBi is effectively utilized, during interrupt processing, the stack area is not consumed and not much memory capacity is required. That is, in this embodiment, the stack area is exclusively utilized in function processing and subroutine processing.

[0304] As a result of the above operations, subsequently, the effect control CPU 63 will execute the initial setting program Pinit described after the address value "****". However, the memory READ operation of the address space CS0 is executed based on the default value (initial value) of the operation control register REG that defines the operation of the bus state controller 66 (Fig. 9). The initial value of this operation control register REG is a value automatically set during the reset assert period (the period shown in Fig. 7(d) where the system reset signal SYS maintains the L level), and is set to the latest READ access operation (default access operation) so that the address space CS0 can be READ accessed without problems regardless of the memory device configuration.

[0305] Therefore, in order to change this default access operation to an optimal access operation, first, an optimal value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (Fig. 9) for the address space CS0 (SP1). That is, in order to optimize the memory READ operation when accessing the PROM 53 that stores the initial setting program Pinit (SP1~SP9), the effect control program MainB (SP10 and below), constant data, etc., the bus width and the presence or absence of page access are set, and the chip select signal CS0, the READ control signal, the WRITE control signal, and other operation timings are optimally set (see Fig. 40).

[0306] As a result of the above settings, the processing after step SP2 will optimally read and execute the program stored in the address space CS0. Therefore, next, in order to optimize the READ / WRITE access operation when the rendering control CPU 63 accesses the VDP register RGij, an optimal value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (Fig. 9) with respect to the VDP register RGij (SP2).

[0307] As described above, in this embodiment, since the VDP register RGij is located in the address space CS7 of the rendering control CPU 63, a predetermined value is written to a predetermined operation control register REG in order to optimally set the operation timing of the chip select signal CS7 and other control signals.

[0308] Subsequently, the register value of a specific VDP register RGij is read out, and it is determined whether the value is a predetermined value (device code) (SP3). This is a confirmation determination that the system clock of the VDP circuit 52 has stabilized. That is, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, and this is a determination as to whether the VDP circuit 52 can normally receive a command from the CPU circuit 51 (that is, a setting to the VDP register RGij, etc.).

[0309] If it can be confirmed by the device code readout process (SP3) that the system clock has stabilized, then thereafter, since normal operation of the VDP circuit 52 can be expected, setting processing for a predetermined VDP register RGij is executed (SP4 to SP6). In the process of step SP4, first, the endian setting (big / little) and the data bus width are set when the rendering control CPU 63 accesses the VDP register RGij (SP40), and for the internal interrupts (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) from the VDP circuit to the CPU circuit, the interrupt significance level (H / L) is set (SP41).

[0310] In this embodiment, the most significant bit of the set value is set to big-endian and stored in the most significant bit of the VDP register RGij, and the data 32-bit bus width is set to 32 bits. However, if these set values happen to be the same as the default values, these setting processes can be omitted (the same applies to the following processes).

[0311] Also, in the process of step SP4, the frequency of the display clock is set based on the set value for a predetermined system control register RGij (SP42~SP44). Specifically, for the display circuit 74A and the display circuit 74B, based on a 40 MHz reference clock (output of the oscillator OSC2), generating the dot clocks DCKA and DCKB is set in a predetermined system control register RGij respectively (SP42), and the multiplication ratio and division ratio with respect to this reference clock are appropriately defined for each display circuit (SP43). Also, the start of operation of the display circuit 74B is set in a predetermined system control register RGij so as to be synchronized with the start of operation of the display circuit 74A (SP44). Furthermore, the LVDS sampling clock is set to be the same as the dot clock DCKA of the display circuit A (SP43).

[0312] In these processes, the dot clocks DCK are set separately for the display circuit 74A and the display circuit 74B. The frequency of the dot clock DCKA for the main display device DS1 applied to the display circuit 74A is set to 108 MHz as described above. On the other hand, the frequency of the dot clock DCKB for the sub-display device DS2 applied to the display circuit 74B is set to 27 MHz corresponding to 480 (horizontal) × 800 (vertical) pixels.

[0313] Also, in the process of step SP4, it is set to use the LVDS unit 80 as a dual link (a pair of LVDS transmission paths) (SP45), and based on the set value to a predetermined system control register RGij, the operating state of the LVDS unit 80 is switched from a mask state (Defult state) that outputs zero to an unmasked state following the output of the display circuit 74 (SP45). When using the LVDS unit 80 as a single link (a single LVDS transmission path), in the process of step SP45, a setting to that effect will be made.

[0314] As shown in FIG. 6(f), as a result of the process of step SP45, since the operation of the LVDS unit 80 is switched from the defult state to the unmasked state, thereafter, after the timing T4 when the display circuit 74 starts operating (see SS4 in FIG. 21), the ODD signal and the EVEN signal are supplied to the LVDS units 80a and 80b via the output selection unit 79, and the LVDS signal (LVDS1 / LVDS2) is transmitted to the display device DS1 via the dual link (see FIG. 14(a)). The LVDS sampling clock is set to the same 108 MHz as the dot clock DCKA of the display circuit A. However, in this embodiment, since a dual link configuration is adopted, the LVDS sampling clock in each dual link is 54 MHz (see FIG. 4).

[0315] Also, in the process of step SP4, it is set that the DDR (DRAM54) is to be made to function based on the clock signal (reference clock) to the PLLREF terminal (see Fig. 8(a)) (SP46). Note that, as described with respect to Fig. 8(a), the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal. Also, by setting appropriate values in the registers built into the DDR (DRAM54), the self-refresh function (Self-Refresh Operation) of the DRAM54 is enabled, and other settings for the normal operation of the DRAM54 are made (SP47). Through the above processes, the DRAM54 becomes in a state where it can operate normally, and subsequent data transfer operations from the PROM53 to the DRAM54 (SP8) and the execution of the control program transferred to the DRAM54 (SP10) will be realized without any problems.

[0316] Subsequently, in order to realize the memory map shown in Fig. 10, address spaces CS1 to CS6 are defined (SP5). As described above, the address space CS3 is assigned to the internal registers of the audio processor 27, the address space CS4 is assigned to the internal registers of the RTC38 and the address space of the SRAM39, the address space CS5 is assigned to the external DRAM (DDR) 54, and the address space CS6 is assigned to the work memory 57 of the built-in CPU.

[0317] Note that since it is fixedly specified that the VDP register RGij is assigned to the address space CS7, the definition process of the address space CS7 is unnecessary. Also, it is fixedly specified in advance that the address space CS0 is the memory map of the CPU circuit 51 from the address 0x000000000 and later. On the premise of this specification, whether the address space CS0 is secured in the CGROM55 or assigned to other memory devices is defined by the H / L level of the HBTSL terminal.

[0318] As described above, in this embodiment, the HBTSL terminal = L, and it is shown that the address space CS0 is defined in addition to the CGROM55. And since the specific bus width and the optimal access operation of the control memory 53 other than the CGROM55 have been set in step SP1, the process of step SP5 is unnecessary for the address space CS0 as well.

[0319] Subsequently, regarding the address spaces CS1 to CS6 defined in the process of step SP5, for the bus width and the presence or absence of page access when accessing each address space CSi, a predetermined value is written to a predetermined operation control register REG (SP6). Also, in order to optimally set the chip select signal CSi and others, a predetermined value is written to a predetermined operation control register REG (SP6). These processes are the same as the processes of step SP1 and SP2, and by writing to the operation control register that defines the operation of the bus state controller 66 (FIG. 9), the chip select signal CSi, the READ control signal, the WRITE control signal, and other operation timings are optimally set.

[0320] Subsequently, regarding the WDT circuit 58 that has already started operating, by outputting a clear signal to the WDT circuit 58, abnormal reset is avoided (SP7). This is in consideration of the fact that the WDT circuit 58 automatically starts operating after power-on, and the same process will be repeatedly executed thereafter. Note that the process of step SP9 is stored in the control memory 53 as a subroutine SP7, but until the end of step SP9, the subroutine SP7 of the control memory 53 is called, and after the end of step SP9, another subroutine SP7' transferred to the external DRAM 54 is called and executed.

[0321] Subsequently, among the programs and data stored in the address space CS0, the vector handler Vopt (interrupt processing program), error return processing program Piram, effect control program MainB, variable D with an initial value, and constant data C shown in FIGS. 16(b) and 17(c) are transferred to the external DRAM 54 and the built-in RAM 59 (SP8). Note that the variable D with an initial value means initial value data stored in a predetermined variable area. The initialization process (SP8) of this memory section is a process of transferring programs and data in order to speed up the effect control process and is a process for avoiding access to the ROM with inferior access speed.

[0322] Next, a setting indicating the use of the register bank RBi is made (SP9). Therefore, thereafter, during interrupt processing, the register banks RB0 to RB14 will function, the interrupt processing will be speeded up, and the consumption of the stack area will be alleviated.

[0323] The above processes are realized by executing the "initial setting program Pinit" stored in the control memory 53 which is the address space CS0 (see FIG. 17(c)). When the execution of this initial setting program Pinit is completed, subsequently, the main control process by the effect control program Main is executed (SP10). Here, the execution of the main control process means the execution of the "effect control program Main" transferred from the control memory 53 to the external DRAM 54 by the transfer process of step SP8 (see FIG. 16(b)).

[0324] The process of the "effect control program Main" is divided into the main introduction process shown in FIGS. 18(a) and the upper part of FIG. 21 and the main body process shown in the lower part of FIG. 21 and FIGS. 22(a). The specific content will be described based on FIGS. 18(a) and FIGS. 21 to 22. Prior to that, the initialization process (SP8) of the memory section will be described. As shown in FIG. 17(a), in the initialization process (SP8) of the memory section, first, the DMACs of a plurality of channels are initially set to the operation stop state. Note that this process is only a formal process for safety.

[0325] Once the above processing is completed, start the DMACi of the predetermined channel, and transfer the vector handler Vopt (interrupt processing program) stored in the control memory 53 to the built-in RAM 59 by DMA transfer in the non-stop transfer method (see Fig. 11(b3)). In this embodiment, since the interrupt processing program Vopt is transferred to the built-in RAM 59, appropriate error handling can be performed even when the external DRAM 54 malfunctions.

[0326] The subsequent processing is the same. Using the DMACi of the predetermined channel, it is executed in the non-stop transfer method, and the error return processing program Piram is DMA transferred to the built-in RAM 59 (SP62). In this embodiment, since the error return processing program Piram is transferred to the built-in RAM 59, in the error return processing, the peripheral circuits can be surely reset. For example, if the error return processing program Piram is transferred to, for example, the external DRAM 54 other than the built-in RAM 59, the external DRAM 54 cannot be reset during the error return processing.

[0327] Next, transfer the production control program Main to the external DRAM 54 by DMA transfer (SP63), and transfer the constant data C to the external DRAM 54 by DMA transfer (SP64). The constant data includes lottery data used for production lottery and lamp drive data and motor drive data in various drive data tables shown in Fig. 22(b). Also, transfer the variable D with an initial value to the external DRAM 54 by DMA transfer (SP65), and all of these are executed in the non-stop transfer method using the DMACi of the predetermined channel.

[0328] Finally, write clear data to the head of the variable area B of the external DRAM (SP66). Assuming that the head address is ADb, in the subsequent DMA transfer process, after initially setting the transfer source address to ADb and the transfer destination address to ADb + 1, while incrementing each address value ADb, ADb + 1, the clear data is diffused to execute the clear process of the variable area B (SP67).

[0329] The processes of steps SP61 to SP66 and step SP67 described above are all similar operations as shown in Fig. 17(b). That is, first, for DMACi of a predetermined channel, as DMA transfer conditions, (1) a cycle steal transfer mode, (2) a non-stop transfer method are adopted, and (3) when the address values of Source and Destination are incrementally updated, they are set (SP68).

[0330] Next, the initial values of the transfer source Source address and the transfer destination Destination address are set (SP69), the transfer size is set, and after setting interrupt inhibition, etc. (SP70), the operation of DMA transfer is started (SP71). Note that the settings of steps SP68 to SP71 are all realized by setting operations to a predetermined operation control register REG.

[0331] In the initialization process of this memory section, since the interrupt at the end of DMA transfer is prohibited from being set (SP70), after starting the operation of DMA transfer, the status flag of a predetermined operation control register REG is repeatedly READ accessed to wait for the end of DMA transfer (SP72). However, considering the processing time until the operation ends, a clear signal is repeatedly output to the WDT circuit 58 (SP73). And at the end of DMA transfer, DMACi is set to stop based on the setting operation to a predetermined operation control register REG.

[0332] Subsequently, the operation contents of the main control process (main introduction process + main body process) will be described based on Figs. 18(a) to 22. Regarding the main control process (main introduction process + main body process), the main introduction process (SP20 to SP27) is described at the upper parts of Figs. 18(a) and 21, and the initial setting process (SS1 to SS6), which is a part of the main body process, is described at the lower part of Fig. 21. Also, the contents of the steady process (ST4 to ST14), which is the remainder of the main body process, are described in Fig. 22.

[0333] As shown in FIG. 18(a), in the main introduction process, first, for the CGROM 55, its bus width and the type of ROM device are specified (SP20). Specifically, as shown in FIG. 19(a), a predetermined VDP register RGij (for example, the CG bus Status register) that controls the interface with the CGROM 55 is accessed by READ (SP80), and it is determined whether the operation settings can be made for the CG bus (SP81).

[0334] Here, if the value of the CG bus Status register is 1, it means that the internal circuit of the CG bus is in the reset operation, and it means that the set value to the VDP register RGij cannot be received. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), for each device section (SPA0 to SPAn) that can be defined corresponding to the memory device constituting the CGROM, the operation parameters such as (1) the validity / invalidity of each device section SPAi, (2) the type of ROM device, and (3) the data bus width are set in the predetermined VDP register RGij (SP82).

[0335] As shown in FIG. 18(a), in this embodiment, the CGROM 55 can be divided into a plurality of regions (device sections). For example, for each device section (SPA0 to SPAn), the memory device and the data bus width can be selectively configured. The memory devices are roughly classified into, for example, (1) the SATA module (AHSI / F) adopted in this embodiment, (2) the memory element adopting the parallel I / F (Interface) format, and (3) the memory element adopting the sequential I / F format. For each of the roughly classified memory devices, the memory device can be specifically selected, and the data bus width and the like can be arbitrarily defined.

[0336] Next, in order to optimize the memory READ operation with the selected memory device for each device section (SPA0 to SPAn), predetermined operation parameters are set in a predetermined VDP register RGij (SP83). The operation parameters include setting values that define the operation timing between the chip select signal and other control signals (such as the READ control signal). Also, when a memory element adopting the sequential I / F format is selected, in order to realize the operation shown in FIG. 19(b) as well, the output timing of the address latch, the number of read clocks, etc. are also specified.

[0337] Therefore, it is also possible to configure the CGROM55 by combining different types of memory devices. However, in this embodiment, the CGROM55 is configured using only the SATA module, only the device section (SPA0) is enabled, and the other device sections (SPA1 to SPAn) are disabled.

[0338] In any case, once the setting process of steps SP82 to SP83 is completed, in order to effectuate the setting process, a predetermined value is written into a predetermined VDP register RGij (SP84). This is considered because the internal circuit of the CG bus requires a predetermined time to be able to operate corresponding to the setting process of steps SP82 to SP83, and during the operation of the internal circuit, the value of the above-mentioned CG bus Status register (refer to SP80) becomes 0.

[0339] Therefore, thereafter, the CG bus Status register is repeatedly READ accessed (SP85), and it is confirmed that the value of the Status register returns from 1 to 0 and the process ends (SP86). Note that, regardless of the determination for a predetermined number of times, if the value of the Status register does not return from 1 to 0, the process of step SP66 may be ended. However, in that case, the game process starts in a state where the CGROM cannot be accessed normally, and thereafter, the WDT circuit 58 is activated at some timing and the composite chip 50 enters an abnormal reset state. And in this case, the power-on reset operation is executed again.

[0340] On one hand, after the process of step SP20 in FIG. 18 is executed normally, built-in circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing (SP21).

[0341] Next, for the multifunction timer unit MTU, after starting a predetermined timer measurement operation (SP22), for internal interrupts and internal interrupts, a permission setting value is written to a predetermined operation control register REG to set it to an interrupt permission state (SP23).

[0342] As a result, various interrupts shown in FIG. 18(d) can occur thereafter. Usually, at this timing, since the audio processor 27 has completed its initialization sequence, as shown in FIG. 7(c), the end interrupt signal IRQ_SND should have dropped to the L level. Therefore, the interrupt process shown in FIG. 18(c) is activated, and the production control CPU 63 initializes the error flag ERR to 1 and performs a READ access to the address space CS3 (SP30) to obtain the value of a predetermined audio register SRG of the audio processor 27 and determine whether the initialization sequence has ended normally (SP31).

[0343] And if, by any chance, the initialization sequence has not ended normally, the production control CPU 63 writes a reset command to a predetermined audio register SRG of the audio processor 27 (SP32) and sets the error flag ERR, which is initially set to 1, to 2 (SP33). This error flag ERR defines whether to execute the audio processor initialization process (SP26), and the condition for executing step SP26 is that the error flag ERR = 1.

[0344] On the other hand, in response to receiving a reset command, the audio processor 27 starts the initialization sequence again with the end interrupt signal IRQ_SND at the =H level, and when the initialization sequence ends, the end interrupt signal IRQ_SND is lowered to the L level. As a result, the process of Fig. 18(c) will be executed again.

[0345] As described above for the exceptional case where the initialization sequence has not ended normally, usually, following step SP31, the process of step SP32 is executed, and the effect control CPU 63 returns the end interrupt signal IRQ_SND from the L level to the H level by writing a predetermined value to a predetermined audio register SRG (SP34).

[0346] Finally, by writing a predetermined value to a predetermined audio register SRG, READ / WRITE access to all audio registers SRG is permitted (SP35). As a result of this process, in the subsequent audio processor initialization process (SP26), necessary setting processes can be executed.

[0347] As described above for an example of Maskable Interrupt corresponding to the interrupt permission setting of step SP23, the non-maskable interrupt (Non Maskable Interrupt) based on the oscillation stop of the oscillator OSC2 can be activated at any timing. As described earlier, the operation clock (CPU system clock) of circuits other than the built-in CPU (effect control CPU 63) is generated by frequency multiplying the output clock of the oscillator OSC2 with a PLL (Phase Locked Loop), and if the oscillation of the oscillator OSC2 stops, the subsequent normal operation of the VDP circuit 52 becomes impossible.

[0348] On the one hand, the operating clock of the rendering control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 by the PLL, and program processing can continue. Moreover, the interrupt processing program is stored in the built-in RAM 59. Therefore, the rendering control CPU 63 notifies an abnormality by voice or a lamp (SP28), and continues to output a clear signal to the WDT circuit 58 (SP29). The abnormality notification is, for example, a voice notification saying "An abnormal situation has occurred. Please contact the staff immediately." Note that continuing to output a clear signal to the WDT circuit 58 is to avoid an abnormal reset operation. That is, in the event of a serious abnormality where the oscillator OSC1 stops operating, it is considered that normal recovery of the device cannot be expected even if the abnormal reset process is repeated.

[0349] As described above for FIGS. 18(b) and 18(c), the description will continue by returning to FIG. 18(a). In step SP24, in order to protect the program area of the external DRAM 54, the necessary area is set to write prohibition. Next, for the clock circuit 38 driven by the battery during power-off, the normal operation during power-off is confirmed, and the alarm interrupt is reset as a precaution (SP25).

[0350] Then, on the condition that the error flag ERR = 1, necessary setting values are written into the built-in register (voice register SRG) of the voice processor 27 to execute the initialization process (SP26). If the error flag ERR = 0, it waits for a predetermined time until the error flag ERR = 1. If the limit time is exceeded, it shifts to an infinite loop process to activate the WDT circuit 58.

[0351] Next, the power supply control circuit SPY is controlled to prepare for the activation of the display device DS1, and necessary setting values are written into the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP27). Note that the process of step SP27 is shown in detail as the processes of steps SP50 to SP57 in FIG. 21.

[0352] The above has described the embodiment of receiving the end interrupt signal IRQ_SND from the audio processor. However, it is also preferable to omit the interrupt processing of FIG. 18(c). FIG. 20 shows a modified embodiment, which utilizes the 1ms timer interrupt signal generated by the multifunction timer unit MTU instead of the end interrupt signal IRQ_SND.

[0353] FIG. 20 illustrates a part of the 1ms timer interrupt processing, and realizes four-stage operations based on the value (0 / 1 / 2 / 3) of the operation management flag FLG whose initial state is zero. Note that the IRQ_SND output terminal of the audio processor 27 is in an open state, and the IRQ_SND input terminal of the CPU circuit 51 is fixed at the H level.

[0354] In the 1mS timer interrupt processing, first, in the process of step SP42, when it is determined that the operation management flag FLG = 0, it is confirmed that the initialization sequence of the audio processor 27 has ended normally (SP43). And when it has ended normally, the interrupt signal (IRQ_SND) is cleared by writing a predetermined value to a predetermined audio register (SP46), and the operation management flag FLG is set to 1 (SP47). Note that the processes of steps SP43 and SP46 are the same as the processes of steps SP31 and SP34 in FIG. 18(c).

[0355] On the other hand, when the initialization sequence has not ended normally, the initialization sequence of the audio processor 27 is started by writing a reset command to a predetermined audio register (SP44), and the operation management flag FLG is reset to zero (SP45). Note that the process of step SP44 corresponds to the process of step SP32 in FIG. 18(c).

[0356] Normally, after the process of step SP47, the operation management flag FLG = 1. Therefore, in the next 1ms timer interrupt, access to all audio registers is permitted by writing a predetermined value to a predetermined audio register (SP48), and the operation management flag FLG is set to 2 (SP49). The process of step SP48 corresponds to the process of step SP35 in FIG. 18(c).

[0357] Next, in the 1 ms timer interrupt with the operation management flag FLG = 2, similar to the case of step SP26 in Fig. 18(a), necessary setting values are written to the built-in register (voice register SRG) of the voice processor 27 to execute the initialization process (SP50), and the operation management flag FLG is set to 3.

[0358] The operation management flag FLG = 3 means the normal voice control state, and voice control is advanced by setting necessary operation parameters to the necessary voice register SRG (SP52).

[0359] As described above, the method of confirming the normal end of the initialization sequence of the voice processor 27 by the interrupt process caused by the interrupt signal (IRQ_SND) (SP31 in Fig. 18(c)) and the method of confirming by the 1 mS timer interrupt process (SP43 in Fig. 20) are not limited to these methods. For example, it is also suitable to determine whether the initialization sequence of the voice processor 27 has ended normally as part of the process of step SP26 in Fig. 18.

[0360] As described above, the outline of the main introduction process (SP20 to SP26 in Fig. 18) has been explained. Therefore, below, based on Figs. 21 to 22, the details of the process of step SP27 (startup preparation process + initialization process) and the operations of the main body process (SS1 to SS6, and ST4 to ST14) will be explained.

[0361] As shown in FIG. 21, as the process of step SP27, the effect control CPU 63 first determines the timing timer TM and checks that one second has elapsed since the start of the operation of the effect control CPU 63 (timing T1 in FIG. 6(d)) while outputting a clear signal to the WDT circuit 58 (SP50). This is to keep the display device DS1 in a non-operating state until the VDP circuit 52 starts its substantial operation. Also, since a clear signal is output to the WDT circuit 58, the activation of the WDT circuit 58 is surely prevented, and there is no possibility that the initialization process up to this point, such as the composite chip 50 being abnormally reset, becomes wasted (this significance is the same in the following standby process).

[0362] Next, the effect control CPU 63 transitions the control signals PS1 and PS2 to the power supply control circuit SPY from the L level to the H level (SP51). This process is the operation at timing T2 shown in FIGS. 6(g) and 6(h), and the control signals PS1 and PS2 are maintained at the H level thereafter.

[0363] When the control signal PS1 becomes the H level, the MOS transistor Q1 becomes the ON state, and the power supply voltage 12V is supplied to the backlight unit BL. However, at this timing T2, since both the BL_EN terminal and the PWM terminal of the driver DVL of the backlight unit BL are at the L level, the backlight unit BL does not emit light.

[0364] Also, when the control signal PS2 becomes the H level, the MOS transistor Q4 becomes the ON state, and the power supply voltage 5 is supplied to the liquid crystal display unit MONI. However, at this timing T2, since the backlight unit BL is in the off state, there is no possibility that an unnatural image is displayed.

[0365] When the process of step SP51 is completed, next, the effect control CPU 63 defines the refresh mode based on the set value in the predetermined VDP register RGij, sets the refresh cycle of the built-in VRAM 71 and the initial value of the row address (refresh address), and executes the initialization process of the built-in VRAM 71 (SP52).

[0366] The VRAM71 in the embodiment is composed of a DRAM (Dynamic Random Access Memory), and the electric charge stored in the memory cell is gradually lost due to the leakage current inside the element. Therefore, in this embodiment, for example, an interleaved refresh method of refreshing one row at a time is adopted, and all rows (ROW) in the element are refreshed at the refresh cycle defined in the process of step SP52 to prevent the electric charge of the memory cell from disappearing. Therefore, even if there are memory cells in the VRAM71 that are not accessed for a long time, there is no risk of their data disappearing. Note that the refresh mode is not limited to the interleaved refresh method, and a burst refresh method can also be adopted.

[0367] Next, the necessary setting values are written to the VDP register RGij to initialize the display clock DCK and initialize the display circuit 74 (SP54). Note that this process is nothing but an operation of hardware resetting the corresponding internal circuit.

[0368] Subsequently, the control signal STBY to the power supply control circuit SPY is transitioned from the L level to the H level (SP56). This process is the operation at the timing T3 shown in FIG. 6(i), and the H level of the control signal STBY is maintained thereafter. Note that at this timing T3, since the power supply voltage of 12V has been supplied to the driver DVL of the backlight unit BL (timing T2), the driver DVL is in an operable state. However, since the control signal PWM still maintains the L level, the backlight unit BL does not emit light.

[0369] Next, the activation of the process of step SP4 in FIG. 16 and the activation of the process of step SP54 in FIG. 21 are confirmed by performing a Read access on a predetermined VDP register (status register STS) RGij (SP57). Specifically, first, it is confirmed by the status register STS(1) that the display clock set in the process of step SP4 in FIG. 16 is stabilized.

[0370] Next, the status register STS(2) checks that the initialization of the display circuit has been completed normally corresponding to the process of step SP54. Subsequently, for the LVDS circuit 80 with dual-link set in the process of step SP45, the status register STS(3) checks that the initialization of each part LVDS1 / LVDS2 has been completed normally. When it is confirmed that all initializations have been completed normally, the main introduction process ends (SP57).

[0371] Subsequently, regarding the subsequent process, an example where the preloader does not function will be described. As shown in FIGS. 21 to 22(a), the main body process is divided into a VDP initial setting process (SS1 to SS6) executed after CPU reset and a steady process (ST4 to ST14) repeatedly executed every 1 / 30 second thereafter.

[0372] And since the steady process (ST4 to ST14) starts at the timing when the interrupt counter VCNT becomes VCNT≧2 (ST4), the operation period δ of the steady process is 1 / 30 second. This operation period δ is nothing but the substantial operation period δ for the VDP circuit 52 that operates intermittently based on the control of the effect control CPU 63. Note that the determination condition is set to VCNT≧2 in consideration of the possibility that the steady process (ST4 to ST14) may be abnormally prolonged and the timing of VCNT = 2 may be missed, but it is designed so that the situation where VCNT = 3 does not occur.

[0373] Based on the above, the VDP initial setting process will be described. As shown in FIG. 21, in this embodiment, in the VDP initial setting process, the built-in VRAM 71 with a storage capacity of 48 Mbytes is appropriately divided into an ACC area (a), a page area (b), and an arbitrary area (c) (SS1). Specifically, for the ACC areas (a1, a2) and the page area (b), the start address of each area and the required total data size are set in a predetermined index table register RGij (SS1). Then, the remaining area not included in the secured ACC areas (a1, a2) and the page area (b) becomes the arbitrary area (c).

[0374] Here, for the first and second ACC regions (a1, a2) and the page region (b), the leading addresses of the regions must each have the lower 11 bits not equal to 0, but can be arbitrarily selected in 2048-bit units (with selection every 256 addresses, assuming 1 address = 1 byte). Also, the total data size can be arbitrarily selected within the range of an integer multiple of the unit size. Although not particularly limited, the unit size of the ACC region (a) is 2048 bits, and the unit size of the page region (b) is 512 kbits.

[0375] Thus, in this embodiment, certain conditions are set for the region settings of the ACC regions (a1, a2) and the page region (b). This is to eliminate as much wasted area as possible for the built-in VRAM 71 with limited memory capacity, while facilitating the smooth internal operation of the VDP circuit 52. That is, if the storage capacity of the built-in VRAM 71 is increased without reason, there are concerns about increased manufacturing costs and a larger chip area. On the other hand, if a free region setting that completely eliminates wasted areas is allowed, the internal processing becomes complicated and the processing time of VRAM access cannot be shortened. The same reason applies to imposing certain restrictions on ensuring the index space described below.

[0376] Continuing the explanation based on the above, following the processing of step SS1, for the page region (b) and the arbitrary region (c), the necessary index space IDXi is ensured (SS2). Specifically, the index space IDXi for each region (b)(c) is ensured by setting the necessary information in a predetermined index table register RGij.

[0377] For example, when providing the index space IDXi in the page region (b), for an arbitrary index number i, information on an arbitrary horizontal size Hx and an arbitrary multiple of the vertical size Wx (vertical and horizontal multiple information with respect to the unit space) is set in a predetermined index table register RGij (SS2).

[0378] As described above, the index space IDXi of the page area (b) has a unit space of horizontal size 128 × vertical size 128 lines. Also, since 1 pixel is specified by 32-bit information, based on the settings of the horizontal size Hx and the vertical size Wx, it means that an index space IDXi with a data size (bit length) = 32 × 128 × Hx × 128 × Wx has been secured. Note that the starting address (space starting address) of the index space IDXi of the page area (b) is automatically assigned internally.

[0379] Also, when providing an index space IDXi in the arbitrary area (c), for an arbitrary index number i, an arbitrary starting address (space starting address) STx and multiple information of multiples of an arbitrary horizontal size Hx are set in a predetermined index table register RGij (SS2). Here, "arbitrary" is based on predetermined conditions. The horizontal size Hx is arbitrarily determined in 256-bit units, the lower 11 bits of the starting address STx are 0, and it is arbitrarily determined in 2048-bit units. As described above, since the vertical size of the arbitrary area is fixed at 2048 lines, based on the setting of the horizontal size Hx, an index space with a data size (bit length) = 2048 × Hx is secured after the starting address STx.

[0380] Specifically, as the frame buffer FBa of the main display device DS1, a pair of index spaces with a horizontal size of 1280 × 2048 vertical lines are each specified by an index number and set in one or more predetermined index table registers RGij. As the frame buffer FBb of the sub-display device DS2, a pair of index spaces with a horizontal size of 480 × 2048 vertical lines are each specified by an index number and set in one or more predetermined index table registers RGij. Note that if the number of horizontal pixels of the display device does not match an integer multiple of 256 bit / 32 bit, the horizontal size of each index space is set to a value larger than the number of horizontal pixels of the display device and an integer multiple of 256 / 32 = 8 to minimize the generation of wasted memory areas.

[0381] As described above, for the page area (b) and the optional area (c), by setting the necessary size information and address information in the predetermined index table register RGij respectively, the necessary number of index spaces IDXi are generated (SS2). Then, corresponding to this setting process (SS2), an index table IDXTBL for specifying the address information and size information of each index space IDXi is automatically constructed. As shown in Fig. 12(a), the index table IDXTBL stores the start address of each index space IDXi together with other necessary information, and is referred to during data transfer inside the VDP circuit 52 or when acquiring data from an external storage resource (see Fig. 13). Note that since the index space IDXi of the AAC area (a) is automatically generated and automatically disappears when necessary, the setting process of step SS2 is unnecessary.

[0382] As shown in Figs. 12(a) and (b), a pair of frame buffers FBa and FBb are secured in the optional area (c), and each is assigned an index number. In an embodiment that does not use a Z buffer, as the frame buffer FBa, a pair of index spaces 255 and 254 to which index numbers 255 and 254 are assigned are secured. Also, as the frame buffer FBb, a pair of index spaces 252 and 251 to which index numbers 252 and 251 are assigned are secured. Note that in this embodiment, a work area (index space 0) with an index number 0 is also secured in the optional area (c).

[0383] Also, in this embodiment, in the page area (a), the necessary number of index space IDs Xi that will be the decoding area of the IP stream video is secured, and the index number i is assigned. However, initially, only the index space IDX0 for the background video (IP stream video) is secured. Then, according to the necessity in the image rendering (fluctuating rendering or preview rendering), based on the setting process for the index table register RGij and the instruction command of the display list DL, the index space IDXj in the page area (a) is increased, and then, if it becomes unnecessary, the index space IDXj is released. That is, Fig. 12(a) shows the index table IDXTBL during the steady operation.

[0384] Note that the index space in the ACC area (a) is automatically generated as needed based on the instruction command described in the display list DL, and the start address of the automatically generated index space IDXj and other necessary information are automatically set in the index table IDXTBL. In this embodiment, this AAC area (a) is used as the decoding area for still images and other textures.

[0385] The above operation of securing the index space is realized solely by the setting operation to the index table register RGij included in the control register group 70. However, following the processing of steps SS1 to SS2, by executing the necessary setting operation (SS3) to other VDP registers RGij, the steady operation (intermittent operation) of the VDP circuit 52 shown in Figs. 30 to 31 is enabled.

[0386] In this embodiment, the necessary setting process (SS3) includes at least SS30 to SS39. Note that steps SS30 to SS37 are not limited in any processing order and can be executed in any order regardless of the following explanation order.

[0387] In this embodiment, first, by writing predetermined operation parameters (the number of lines and the number of pixels) to a predetermined display register RGij that defines the operation of the display circuit 74, the number of display lines and the number of horizontal pixels are set for each display device DS1 and SD2 (SS30). In the case of this embodiment, the number of horizontal pixels of the main display device DS1 is 1280 dots, and the number of display lines is 1024 lines. Also, the number of horizontal pixels of the sub-display device DS2 is 480 dots, and the number of display lines is 80 lines. As a result of the setting process in step SS34, the vertical and horizontal dimensions of the valid data area (the dashed line part in FIG. 22(e)) that the display circuits 74A and 74B should perform READ access to are specified in each frame buffer FBa and FBb.

[0388] Next, by writing predetermined operation parameters (THc, WTh) to a predetermined display register RGij that defines the operation of the display circuit 74, the number of cycles THc of the horizontal period TH and the horizontal standby time WTh are set for each display device DS1 and SD2 (SS31). Also, by writing predetermined operation parameters (TVl, WTv) to a predetermined display register RGij, the number of lines TVl of the vertical period TV and the vertical standby time WTv are set for each display device DS1 and SD2 (SS32).

[0389] As described with reference to FIG. 15, for the main display device DS1, the number of cycles THc of the horizontal period TH is set to 1662, and the number of lines TVl of the vertical period TV is set to 1083. Also, the horizontal standby time WTh is set to 382, and the vertical standby time WTv is set to 59 lines. On the other hand, for the sub-display device DS2, for example, the number of cycles THc of the horizontal period TH is set to 519, the number of lines TVl of the vertical period TV is set to 867, the horizontal standby time WTh is set to 39, and the vertical standby time WTv is set to 67 lines. Note that THc - WTh = 519 - 39 = 480, and TVl - WTv = 867 - 67 = 800, which is consistent with the number of pixels of the sub-display device (480 horizontal × 800 vertical).

[0390] In any case, the frequency F of the dot clock DCK is determined by the process of step SP4 in FIG. 16. dot(=108 MHz) is determined, and as a result of the processes in steps SS30 to SS32, for the main display device DS1, the number of cycles THc (=1662) of the horizontal period TH and the number of lines TVl (=1083) of the vertical period TV are defined. Consequently, the display period of one frame is THc × TVl / F dot and will be determined as such. Specifically, the display period of one frame is 1083 × 1662 / 108 MHz = 16.667 mS, and it is determined that the frame rate FR is 1 / 60 second.

[0391] Regarding the sub-display device DS2 as well, for example, based on the frequency F dot = 27 MHz, the number of cycles THc = 519 of the horizontal period TH, and the number of lines TVl = 867 of the vertical period TV, it is determined to be 519 × 867 / 27 MHz = 16.66 mS.

[0392] Next, in this embodiment, for the sub-display device DS2, the pulse width of the horizontal synchronization signal HS and the number of cycles from the V-blank start timing of the pulse rising edge are set in a predetermined display register RGij (SS33). Also, for the sub-display device DS2, the pulse width of the vertical synchronization signal VS and the number of cycles from the V-blank start timing of the pulse rising edge are set (SS34).

[0393] As described above, since the main display device DS1 does not require the horizontal synchronization signal HS or the vertical synchronization signal VS, the above processes (SS33 to SS34) for the main display device DS1 are unnecessary. However, when the setting processes in steps SS33 to SS34 are omitted, the default values set at power reset will function. So, actually, the display device 74A will also output the horizontal synchronization signal HS and the vertical synchronization signal VS.

[0394] According to the default values, for example, a horizontal synchronization signal HS with a pulse width of 40 clocks that becomes active 16 clocks after the V-blank start timing is output, and a vertical synchronization signal VS with a pulse width of 3 lines that becomes active in synchronization with the V-blank start timing is output.

[0395] This operation means that, for the main display device DS1, a horizontal synchronization signal HS with a horizontal front porch HPv = 16, a pulse width PWh = 40, and a horizontal back porch BPv = 326 is output during a horizontal standby time WTh = 382 clocks, and a vertical synchronization signal VS with a vertical front porch HPv = 0, a pulse width PWv = 3, and a vertical back porch BPv = 56 is output during a vertical standby time WTv = 59 lines. However, as described above, these synchronization signals are ignored in the main display device.

[0396] Note that, in order to prevent the synchronization signals HS and VS based on the default values from being output, a configuration may be adopted in which a predetermined system control register RGij is set so as not to output the horizontal synchronization signal HS and the vertical synchronization signal VS. When such a mask setting is provided, the output terminals of the horizontal synchronization signal HS and the vertical synchronization signal VS of the VDP circuit 52 can maintain a fixed value of H level or L level.

[0397] Subsequently, a predetermined system control register RGij is set to permit V blank interrupts (SS35). As a result, in this embodiment, corresponding to the V blank start timing that occurs every 16.667 mS = 1 / 60 second, a VBLANK start interrupt shown in FIG. 22(c) will occur. This V blank interrupt timing defines the start timing of the steady processing (ST5 to ST14) of the effect control CPU 63 and also means the start timing of the display period (the end timing of the previous display period) for the display circuits 74A and 74B.

[0398] Next, a predetermined operation parameter (address value) is written into a predetermined display register RGij to specify the vertical display start position and the horizontal display start position for each frame buffer FBa, FBb (SS36). As a result, the valid data area whose vertical and horizontal dimensions are specified in the process of step SS34 is determined on the frame buffers FBa, FBb. Here, the vertical display start position and the horizontal display start position are relative address values in each index space, and in the embodiment shown in FIG. 22(e), the display start position is (0, 0).

[0399] Here, the "display area" means the index space (frame buffers FBa, FBb) from which the display circuits 74A, 74B should read image data in order to drive the display devices DS1, DS2, and means either one of the double buffers in the frame buffers FBa, FBb each having a double buffer structure. However, the display circuits 74A, 74B actually read the image data only from the "valid data area" specified in steps SS30 and SS36 in the display area (0) or the display area (1).

[0400] Next, "display area (0)" and "display area (1)" are set in the display register RGij (DSPAINDEX) related to the display circuit 74A that drives the main display device DS1 and the display register RGij (DSPBINDEX) related to the display circuit 74B that drives the sub-display device DS2, respectively, to define each display area (SS37).

[0401] Although not limited in any way, in this embodiment, for the frame buffer FBa, the index space 254 with index number 254 in the arbitrary area (c) of the VRAM is defined as the "display area (0)", and the index space 255 with index number 255 in the arbitrary area (c) of the VRAM is defined as the "display area (1)" (SS37).

[0402] Also, for frame buffer FBb, index space 251 of index number 251 in VRAM arbitrary area (c) is set as "display area (0)", and index space 252 of index number 252 in VRAM arbitrary area (c) is set as "display area (1)" (SS37). Note that there is no particular limitation on defining the "display area" in the initial processing (SS3), and the index space (display area) to which display circuit 74 should access image data for READ may be toggled for each operation cycle δ. Note that it is also preferable to clear the respective display areas (0) and (1) of frame buffers FBa and FBb to zero at this timing, in which case unnatural images will not be displayed on the display device.

[0403] In this embodiment, once the initial setting including the above processes (SS30 to SS37) is completed, a predetermined prohibition value is set in the first type prohibition setting register RGij so that the setting value in the predetermined system control register RGij is not subsequently changed due to the influence of noise or the like (first prohibition setting SS38).

[0404] Here, the setting values ​​that are prohibited from being written in the future include (1) setting values ​​related to the display clock DCK of the display devices DS1 and DS2, (2) setting values ​​related to the sampling clock of the LVDS, (3) setting values ​​related to the selection operation of the output selection circuit 79, and (4) the synchronous relationship of the multiple display devices DS1 and DS2 (the display circuit 74B is subordinate to the operation cycle of the display circuit 74A). Although there is software processing for canceling the first prohibition setting, it is not used in this embodiment. However, it is preferable to use it as necessary.

[0405] Next, a predetermined inhibit value is set in the second type inhibit setting register RGij, thereby inhibiting writing to the VDP register RGij of the initial setting system (second inhibit setting SS39). Here, the registers to be inhibited include the VDP register RGij related to step SP4 and steps SS30 to SS37.

[0406] On the other hand, by setting a predetermined prohibition value in the third prohibition setting register RGij, it is also possible to prohibit setting to a number of VDP registers including the VDP register related to the setting process of steps SS1 to SS3 (third prohibition setting). However, this is not used in principle in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily canceled by writing a cancellation value in a predetermined cancellation register RGij, and it is also possible to change the set value during the steady operation.

[0407] When the above processing is completed, next, in the process of step SP52 in FIG. 21, regarding the end of initialization of the built-in VRAM 71 that defines the refresh cycle, the status register (4) is referred to, and it is confirmed that the operation is stable (normal end of initialization) (SS40).

[0408] By the above processing, it is confirmed based on the values of the status registers (1) to (4) that all of the built-in VRAM 71, the display circuit 74, and the LVDS circuit 30 have normally completed the initialization process. Next, by writing a specified value in a predetermined display register RGij (DSPACTL / DSPBCTL), the operations of the display circuits 74A and 74B are started (SS4a), and by writing a specified value in a predetermined system control register RGij (SYSDSPLVDS1MD / SYSDSPLVDS2MD), the output data from the display circuit 74A is output from the LVDS circuit 80 (LVDS1 / LVDS2) (SS4b).

[0409] This operation is nothing but the processing at timing T4 in FIG. 6(e). In this embodiment, the program is designed such that the processing of steps SS4a to SS4b is executed within a predetermined time τ (for example, 20 mS) from timing T2. Then, corresponding to the start of operation (timing T4) of the display circuits 74A and 74B and the LVDS circuit 80, the timing timer TM is restarted from zero (SS4c). Note that the processing procedures of steps SS4a to SS4b are not necessarily limited. Even if the processing of steps SS4a to SS4b is executed in reverse order, at most only a momentary amount of useless image data is output from the LVDS circuit 80, and moreover, since the backlight unit BL is turned off, there is no problem.

[0410] In any case, in this embodiment, corresponding to the processing of steps SS4a to SS4b above, the display circuit 74 enters the V blank start state every 1 / 60 second, and when the LVDS circuit (LVDS1 / LVDS2) 80 operates, the display operation shown in FIG. 15 is repeated. In FIG. 15, the start timing and the end timing of the display operation indicated by the ○ mark indicate the V blank start timing.

[0411] Based on this V blank start timing, a horizontal reference point TH0 (= horizontal reference time) and a vertical reference point (= vertical reference time) TV0 in the operation of the display circuit 74 are defined. The display circuit 74 waits without outputting image data corresponding to each pixel of the display device until the horizontal standby time WTh elapses from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait without outputting image data corresponding to each pixel of the display device until the vertical standby time WTv elapses from the vertical reference point TV0.

[0412] In addition, since the display circuit 74B operates in synchronization with the display device 74A (SP4 in FIG. 16), the start and end timings of the display operation for the sub-display device DS2 are also the same as those of the main display device DS1. Therefore, by setting the frame period for the sub-display device DS2 (519×867 / 27) to be shorter than the frame period for the sub-display device DS2 (1083×1662 / 108), it is set such that the update process of the sub-display device DS2 is completed at the start of the V blank.

[0413] When the processing of step SS4 with the above significance is completed, next, it waits for 300 mS to elapse based on the timing timer TM (SS5), and then transitions the control signal PWM to the power supply control circuit SPY from the L level to the H level (SS6). As a result, the backlight unit BL becomes the light-emitting state, and the liquid crystal display unit MONI that has started operating previously starts the display operation based on the image data received from the display circuit 74A. At this timing, since the display list has not been issued, as previously explained, the content of the VRAM is directly displayed. Therefore, it is also preferable to delegate the processing of steps SS5 to SS6 to the timer interrupt processing (see the dashed line). With such a configuration, at the time of timing T5, since the display list DL has been issued, a predetermined initial screen is displayed on the display device DS1.

[0414] Subsequently, the remainder of the main body processing, which is the steady processing repeatedly executed every predetermined time, will be described based on FIG. 22. As shown in FIG. 22, the operation of the effect control CPU 63 includes a main control process (a), a timer interrupt process (b) that starts every 1 mS, a reception interrupt process (not shown) that starts upon receiving a control command CMD, a VBLANK interrupt process (c) that starts upon receiving a VBLANK signal generated at the start timing of the V blank (vertical retrace period) of the display device DS1, and a drawing abnormality interrupt process (d) that occurs during operation freeze or when an unreasonable instruction command is detected. The description of the 20 μS interrupt process is omitted.

[0415] In the reception interrupt process, the control command CMD received from the main control unit 21 is stored in a predetermined reception buffer so that it can be referenced in the main control process (ST13), and the process ends. Also, in the VBLANK interrupt process (Fig. 22(b)), the interrupt counter VCNT is incremented every VBLANK interrupt (ST15), and at the start timing of the main control process, based on the value of the interrupt counter VCNT, after grasping the operation start timing of 1 / 30 seconds, the interrupt counter VCNT is cleared to zero (ST4).

[0416] On the other hand, as shown in Fig. 22(b), the timer interrupt process includes the progress process of lamp effects and motor effects (ST18), and the sensor signal acquisition process (ST19) for acquiring the origin sensor signals SN0 to SNn signals, the chance button signal, etc. The lamp effects and motor effects are controlled based on an effect scenario that centrally manages all effect operations. When the effect start time managed by the effect counter EN is reached, in the effect scenario update process (ST11), the motor drive table and the lamp drive table are specified.

[0417] After that, based on the specified motor drive table, the motor effect progresses, and based on the specified motor drive table, the lamp effect progresses. As described above, there is also an embodiment in which the DMAC circuit (the first and second DMA channels) 60 functions during the operation of step ST18. Note that the motor effect progresses every 1 mS, while the lamp effect progresses at an appropriate timing longer than 1 mS.

[0418] On the other hand, as shown in Fig. 22(d), in the drawing abnormality interrupt process, the status register RGij indicating the operation state of the drawing circuit 76 is READ-accessed to identify the cause of the interrupt. Specifically, it is determined whether the drawing abnormality interrupt is due to (1) detection of an abnormal instruction command (bit error) or (2) an operation abnormality (freeze) of the drawing circuit 76 (ST16a). When the drawing abnormality interrupt is due to detection of an abnormal instruction command, the drawing circuit 76 is initialized by writing a predetermined value to a predetermined system control register RGij (ST16b). This operation is nothing but the individual reset operation of the reset path 4B shown in Fig. 7(b).

[0419] Next, after confirming the normal completion of the individual reset operation with a predetermined status register RGij, a group of operation parameters that define the operation of the drawing circuit 76 are reset to a predetermined drawing register RGij to end the process (ST16c). Then, after adjusting the stack area that stores the return address (release process to erase the return address after the interrupt process), the process proceeds to step ST13 (ST16c).

[0420] On the other hand, in the case of a drawing abnormality interrupt based on an operation abnormality of the drawing circuit 76, the WDT circuit 58 is activated and the entire composite chip 50 is reset by shifting to an infinite loop process (ST16d). If it is not desired to reset the CPU circuit 51, a predetermined keyword sequence may be output to the pattern check circuit CHK to reset only the VDP circuit 52 with the reset signal RST (see Fig. 7(b)). In this case, after confirming the normal completion of the reset operation of the VDP circuit 52, the process proceeds to steps ST4 or ST13. In order to avoid reading out the control command CMD as much as possible, it is better to proceed to step ST13 from step ST4 in other cases as well.

[0421] When the entire composite chip 50 is reset, the previous effects disappear and the effect control returns completely to the initial state (power-on state). However, when only the VDP circuit 52 is reset, although a predetermined waiting time occurs until the reset operation of the VDP circuit 52 is completed, a series of effect controls can be continued. Note that since the effect control CPU 63 uniformly controls image effects, lamp effects, and sound effects, no unnatural deviation occurs in each effect.

[0422] Note that the initial setting process of steps SS1 to SS3 described above is executed based on an initial value setting table SETTABLE (see FIG. 36) that associates the register address value of the VDP register RGij with the setting value for the register RGij. Since the initial setting process has been described above, next, before explaining the steady-state processing (ST4 to ST14), the steady-state operation (intermittent operation) of the VDP circuit 52 controlled by the effect control CPU 63 will be schematically explained based on FIGS. 30(a) and 31(b).

[0423] The intermittent operation of the VDP circuit 52 is as shown in FIGS. 30 and 31. In an embodiment that does not use the preloader 73, as shown in FIG. 30(a), the display list DLi completed by the effect control CPU 63 is issued to the drawing circuit 76 in its operation cycle (T1), and the drawing circuit 76 completes the image data in the frame buffers FBa and FBb by a drawing operation based on the display list DLi. Then, the image data completed in the frame buffers FBa and FBb is output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle T1 + δ, and based on the subsequent drawing operations of the display devices DS1 and DS2, a display screen that can be perceived by the player is formed.

[0424] On the other hand, in the embodiment using the preloader 73, as shown in Fig. 31(a), the display list DLi completed by the effect control CPU 63 is issued to the preloader 73 in its operation cycle (T1). The preloader 73 interprets the display list DLi, executes the necessary prefetch operation, and rewrites a part of the display list DLi to complete the rewrite list DL'. The prefetched CG data and the rewrite list DL' are stored in appropriate locations of the DRAM 54.

[0425] Next, in its next operation cycle (T1 + δ), the drawing circuit 76 acquires the rewrite list DL' from the DRAM 54, and completes the image data in the frame buffers FBa and FBb by the drawing operation based on the rewrite list DL'. Then, the image data completed in the frame buffers FBa and FBb is output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle (T1 + 2δ), and based on the subsequent drawing operations of the display devices DS1 and DS2, it becomes the display screen that the player perceives.

[0426] The intermittent operation of the VDP circuit 52 has been schematically described above. To realize the operations shown in Figs. 30 to 31 above, after the initial processing (SS1 to SS3), the effect control CPU 63 repeatedly refers to the value of the interrupt counter VCNT and waits for the operation start timing to be reached. When the operation start timing (the start timing of every other V blank) is reached, the interrupt counter VCNT is cleared to zero (ST4).

[0427] After that, the steady operation is started. In this embodiment, first, it is determined whether the operation start condition for starting the steady operation is satisfied (ST5). Note that this determination timing is the timing of T1, T1 + δ, T1 + 2δ,... shown in Figs. 30 to 31, that is, the start timing of the vertical blanking period (VBLANK) of the display device DS1. The display timing of the display device DS2 is set at the initial setting (ST3) so as to be subordinate to the display timing of the display device DS1.

[0428] The operation start conditions determined at the start timing of the vertical blanking period (VBLANK) differ depending on whether or not the preloader 73 is utilized. First, an embodiment (Fig. 22) that does not utilize the preloader 73 will be described. In this case, originally, the circuit configuration and program are designed so that the internal operation of the VDP proceeds as shown in the time chart of Fig. 30(a). That is, based on the display list DL1 completed in the operation period (T1), the drawing circuit 76 should finish the drawing operation during that operation period (T1 to T1+δ). However, for example, it cannot be said that there is no case where the drawing operation is not completed during the operation period (T1+2δ to T1+3δ), such as the display list DL3 completed in the operation period (T1+2δ) of Fig. 30(a). Also, regarding the display circuit 74, there is a possibility that an Underrun abnormality may occur where the generation of display data cannot keep up with the display timing.

[0429] The determination process in step ST5 takes such a situation into consideration. The effect control CPU 63 accesses the status register RGij (a type of control register group 70) indicating the operation state of the drawing circuit 76 and determines whether the drawing circuit 76 has completed the necessary operations and whether there is an Underrun abnormality at the timing of step ST5. The presence or absence of the Underrun abnormality is determined based on the underrun counters URCNTa to URCNTc. Also, in an embodiment that does not utilize the preloader 73, for example, at the timing T1+δ in Fig. 30(a), a READ access is made to the status information of the drawing register regarding the drawing circuit 76 to confirm that the drawing operation based on the display list DL1 has been completed.

[0430] When the operation start conditions are not met (abnormality / incompatibility), the exception flag ER that counts the number of exceptions is incremented, and the processing in steps ST6 to ST8 is skipped. The exception flag ER, together with the other critical exception flag ABN, is determined in the processing of steps ST9 and ST10. On the premise that the critical exception flag ABN is in the reset state, when the number of consecutive exceptions is not large (ER≦2), the effect command analysis process is executed in the same way as in the normal case (ST13).

[0431] Even in the case of an underrun abnormality, similarly, the processes of steps ST6 to ST8 are skipped. Then, by writing a predetermined clear value to a predetermined system control register RGij, the display clock DCK (frequency) and the display circuit 74 are initialized (ST10c). After confirming the normal completion of this initialization process, the frequency of the display clock DCK and the values of a group of system control registers RGij that define the operation of the display circuit 74 are reset to the specified values (ST10c), and then the effect command analysis process is executed (ST13).

[0432] In the effect command analysis process (ST13), it is determined whether the control command CMD is received from the main control board 21. If the control command CMD is received, the control command CMD is analyzed and the necessary processes are executed (ST13). Here, the necessary processes include the start preparation process of a new variable effect based on the control command CMD that instructs the start of the variable effect and the start process of error notification based on the control command CMD indicating the occurrence of an error. Subsequently, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

[0433] As described above, in the case of a minor underrun abnormality or when the operation start condition is not met and the error flag ER is ER ≦ 2, in such a case, in that operation cycle, the process of toggling the display area read by the display circuit 74 (ST6) and the process of creating the display list (ST7) are skipped, and the effect scenario does not progress (see ST8 to ST12). This is to prevent the output of the image data of the incomplete frame buffers FBa and FBb. Therefore, for example, in the operation cycle (T1 + 3δ) of FIG. 30(a), the image effect does not progress, and a frame drop occurs where the original screen (the screen based on DL2) is redisplayed.

[0434] Here, in order to avoid frame drops, a configuration that waits until the operation start condition is satisfied can also be considered. However, since there are many control processes (ST6 to ST12) that the production control CPU 63 should execute and it is necessary to secure the processing time for each, in this embodiment, frame drops are caused when the operation start condition is not satisfied.

[0435] However, even if a frame drop occurs, compared to the lamp production and motor production that progress by the interrupt process (Fig. 22(b)), the progress of the image production is only delayed by about 1 / 30 to 2 / 30 seconds, and the player will not notice this. Moreover, when a frame drop occurs, the production scenario process (ST11) including the update process of the production counter EN and the voice progress process (ST12) are also skipped together, so in the reach production, preview production, and accessory production that are started thereafter, there is no possibility that the start timings of the image production, voice production, lamp production, and motor production will deviate.

[0436] That is, in the production scenario, the start timings of the image production, voice production, lamp production, and motor production, and the production contents to be executed thereafter are managed integrally, and the start timings are controlled by the production counter EN that is updated only during normal times, so the synchronization of various productions does not deviate. For example, when there is a production operation that combines an explosion sound, an explosion image, accessory movement, and a lamp flashing operation, even after a frame drop occurs, the above-described production operations start correctly in synchronization.

[0437] As described above, relatively minor abnormalities have been explained. However, when the serious abnormality flag ABN is in the set state, when the number of consecutive abnormalities is large (ER > 2), or when repeated Underrun abnormalities occur, after the determination in step ST10, an infinite loop state is set (ST10b). As a result, the timing operation of the WDT circuit 58 progresses, and the composite chip 50 including the production control CPU 63 is abnormally reset, and thereafter, the initial processes (SS1 to SS3) are re-executed, expecting to eliminate the root cause of the occurrence of the abnormal situation.

[0438] Note that since this reset operation is started and executed by the WDT circuit 58, the entire composite chip 50 including the CPU circuit 51 is reset (Fig. 7(b)). Therefore, in order to avoid resetting the CPU circuit 51, it is also preferable that the effect control CPU 63 outputs a predetermined keyword sequence (for example, three 1-byte data) to the pattern check circuit CHK and outputs the reset signal RST to the VDP circuit 52 (see ST100 in Fig. 36). Also in this case, after confirming the normal completion of the reset operation of the VDP circuit 52 (ST101), the process proceeds to the processes of steps ST4 and ST13.

[0439] In any case, in this abnormal situation, since the voice circuit SND is also reset abnormally, all of the image effect, voice effect, lamp effect, and motor effect will return to their initial states. However, these reset operations have no influence on the main control unit 21 and the payout control unit 25, so there is no risk of a situation such as the disappearance of the jackpot state or the disappearance of the bonus ball occurring.

[0440] Although the abnormal situation has been described above, in reality, the above-mentioned abnormalities rarely occur, even including minor cases. After the process of step ST5, based on the setting to the predetermined display register RGij (DSPACTL / DSPBCTL), the "display areas" of the frame buffers FBa and FBb that store the image data to be read by the display circuit 74A and the display circuit 74B are toggled (ST6). As described above, since the "display area (0)" and the "display area (1)" are defined in advance in the initial process (ST3), in the process of step ST6, it is specified whether the current "display area" of the frame buffers FBa and FBb is the display area (0) or the display area (1).

[0441] By executing this step ST6, the display circuit 74A reads out image data alternately from the index space 254 (display area (0)) and the index space 255 (display area (1)) every operation period δ, and drives the display device DS1. Similarly, the display circuit 74B reads out image data alternately from the index space 251 (display area (0)) and the index space 252 (display area (1)) every operation period δ, and drives the sub-display device DS2. Note that as described above, the actual READ access by the display circuit 74 is limited to the valid data area in the display area (0) / display area (1).

[0442] In any case, in this embodiment, since the "display area" is switched every operation period, the display circuits 74A and 74B start the output process to the display devices DS1 and DS2 for the image data completed by the drawing circuit 76 in the previous operation period. However, since the process of step ST5 starts at the start of the vertical blanking period (V blank) of the main display device DS1, actually, the output process of the image data starts after the vertical blanking period is completed. In FIG. 30(a), the arrow shown in the column of the display circuit indicates the operation period of this output process.

[0443] When the process of step ST6 having the above significance is completed, the effect control CPU 63 subsequently completes the display list DL that specifies the image data to be output by the display circuit 74 to the display device in the next operation period (ST7). Although not particularly limited, in this embodiment, the list buffer area (DL buffer BUF) of the RAM 59 is secured, and the display list DL is completed there (see FIG. 13).

[0444] The display list DL is configured by listing a series of instruction commands in an appropriate order and ending with the description of the EODL (End Of DL) command. And in this embodiment, in order to realize the smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all the instruction commands including the EODL command are limited to only the instruction commands whose command length is an integer multiple of 32 bits (N>0). As described above, the instruction commands composed of an integer multiple of 32 bits may include don't care bits.

[0445] In this way, since the display list DL of the embodiment is composed of only the instruction commands whose command length is an integer multiple of 32 bits (N>0), the data volume value (total amount of data) of the entire display list DL is always an integer multiple of the minimum unit of the command length (32 bits = 4 bytes). Furthermore, in this embodiment, considering the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is adjusted to be an integer multiple (1 or more) of the minimum data amount Dmin and also an integer multiple of the minimum unit (4 bytes) of the instruction command. For example, if Dmin = 256 bytes, the data volume value of the display list DL is adjusted to any value such as 256 bytes, 512 bytes...

[0446] Here, depending on the complexity of the production content, it is also suitable to adjust it to 256 bytes or 512 bytes as appropriate. However, in this embodiment, considering that there are two display devices and the sub-display device DS2 does not execute very complex image production, the data volume value of the display list DL is always adjusted to 256 bytes.

[0447] However, this method is not limited in any way. When there are three or more display devices, or in the case of a gaming machine that performs complex image rendering including the sub-display device DS2, it is adjusted to 512 bytes or 768 bytes. Also, during normal rendering, the data volume value of the display list DL is adjusted to 256 bytes, and it is also preferable to adjust the data volume value of the display list DL to 512 bytes or 768 bytes only when performing special rendering.

[0448] However, in the case of this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) defined in advance in each operation cycle δ. As an adjustment method, there is a simple method (A) of filling the insufficient area with a 32-bit long NOP (No Operation) command after a 32-bit long EODL command, or a standard method (B) of filling the insufficient area with 32-bit long NOP commands and then finally describing a 32-bit long EODL command. Note that there is also an unadjusted method (C) of terminating with an EODL command without adjusting the data volume value (total data amount) of the display list DL at all, and adding dummy data during the operation of the data transfer circuit 72 to ensure a transfer amount that is an integer multiple of the minimum data amount Dmin.

[0449] Here, when adopting the standard method (B), first, the command counter CNT is initially set to a specified value (64 - 1 corresponding to 256 bytes). Each time a significant instruction command is written to the DL buffer area BUF, the command counter CNT is appropriately subtracted. After the writing of a series of significant instruction commands is completed, NOP commands are described until the command counter CNT becomes zero, and finally an EODL command is described. In the case of this embodiment, since the instruction command is limited to those whose command length is an integer N times (N > 0) of 32 bits, the above processing is easy, and the subtraction process of the command counter CNT becomes a subtraction process corresponding to the integer N.

[0450] On the one hand, when adopting the simple method (A), when creating the display list DL, first, it seems that just filling the entire list buffer area (DL buffer BUF) with NOP commands is sufficient, so it seems to be superior to the standard method (B) at first glance. Also, from the perspective of simplicity, the unadjusted method (C) also seems to be excellent. However, in this embodiment, basically the standard method (B) is adopted, and the actual data amount from the beginning of the display list DL to the EODL command, that is, the data amount up to the EODL command, is always adjusted to be an integer multiple of the minimum data amount Dmin of the data transfer circuit 72.

[0451] This is considering the embodiment that utilizes the preloader 73. If the simple method (A) or the unadjusted method (C) is adopted, the actual data amount of the display list DL up to the EODL command will be a random value, which will cause problems when transferring the rewritten list DL' rewritten by the preloader 73 to the DRAM 54 or when transferring the rewritten list DL' from the DRAM 54 to the drawing circuit 76. When transferring the rewritten list DL' to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when transferring the rewritten list DL' to the drawing circuit 76, the ChB control circuit 72b functions (see FIG. 28), but in either case, only the rewritten list DL' up to the EODL command will be transferred.

[0452] As described above, the advantages of the standard method (B) for adjusting the data volume value of the display list DL have been explained. In an embodiment that does not use the preloader 73, since the issued display list DL is only processed by the drawing circuit 76, the use of the simple method (A) or the unadjusted method (C) is not prohibited in any way.

[0453] However, in the following description, regardless of the presence or absence of the use of the preloader 73, on the premise of basically adopting the standard method (B) as a principle, the details of the display list DL will be described based on FIG. 23.

[0454] Although not particularly limited, in this embodiment, the display list DL first describes an instruction command sequence (L11 to L16) regarding the main display device DS1, and then describes an instruction command sequence (L17 to L20) regarding the sub-display device DS2. Also, the standard method (B) is adopted to adjust the data volume value of the display list DL to a fixed length (256 bytes). Note that FIG. 23 actually shows the procedure in which the effect control CPU 63 writes instruction commands to the list buffer area of the RAM 59 and the operation of the drawing circuit 76 based on the display list DL.

[0455] As shown in FIG. 23, at the beginning of the display list DL, an environment setting instruction command (SETDAVR) is described to define the upper left base point address (X, Y) on the index space IDX for the frame buffer FBa of the display device DS1 (L11). As described with respect to FIG. 12(a), in this embodiment, a pair of frame buffers FBa are secured in an arbitrary area (c) for the display device DS1. And normally, by setting the base point address (X, Y) = (0, 0) corresponding to the effective data area for the display circuit 74, it is utilized by the drawing circuit 76 from the start position of the frame buffer FBa.

[0456] In FIG. 12(c), it is labeled L11 in the actual drawing area at the lower left. This means that by the instruction command L11, the actual drawing area on the frame buffer FBa is specified to start from the base point address (0, 0) of the frame buffer FBa. However, the vertical and horizontal dimensions of the actual drawing area and the index number specifically specifying the actual drawing area are still undetermined and are determined by the subsequent instruction command (SETINDEX) L13. Note that the use or non-use of the Z buffer is also specified in the instruction command L11.

[0457] Next, by the environmental setting instruction command (SETDAVF), the upper left base point coordinates (Xs, Ys) and the lower right diagonal point coordinates (Xe, Ye) are set on the virtual drawing space to define a drawing area of W×H dimensions (L12). Here, the virtual drawing space is a virtual two-dimensional space of ±8192 in the X direction and ±8192 in the Y direction that can be drawn by a drawing instruction command (such as a SPRITE command) (see Fig. 12(c)).

[0458] By this instruction command L12 (SETDAVF), the virtual drawing space is divided into a drawing area where the drawing content is actually reflected on the display device DS1 and other non-drawing areas. Also, the instruction command L12 (SETDAVF) will associate the actual drawing area whose start position (base address) is defined by the instruction command L11 with the drawing area on the virtual drawing space.

[0459] In other words, by the instruction command L12, in the frame buffer FBa (where the index space is undefined), a W×H actual drawing area starting from the base address corresponding to the drawing area on the virtual drawing space is defined. Therefore, the drawing area specified by the instruction command L12 needs to be the same as or smaller than the horizontal size of the frame buffer FBa. Usually, the drawing area and the actual drawing area are defined to have the same dimensions as the valid data area for the display circuit 74 (Fig. 22(e)).

[0460] After the drawing circuit 76 executes the instruction commands L11 and L12, only the drawing content included in the drawing area among the drawing content drawn on the virtual drawing space will be reflected in the actual drawing area of the frame buffer FBa. Therefore, the drawing content of the part that protrudes from the drawing area or the part described as the work area in Fig. 12(c) will not be reflected in the frame buffer as it is. When securing a work area in the virtual drawing space, the non-drawing area of the virtual drawing space is used.

[0461] Next, in the current operation cycle, the drawing circuit 76 defines where to draw the drawing content to be drawn based on the display list DL to be completed (L13). Specifically, for the frame buffer FBa of the display device DS1 with a double buffer configuration, the index space IDX that becomes the "writing area" of the drawing content based on the current display list DL is specified (L13). Specifically, by the SETINDEX command, which is a texture setting command, (1) the frame buffer FBa is ensured in an arbitrary area, and (2) the index number N on an arbitrary area of the index space IDX N is specified.

[0462] By this instruction command L13, for example, when N = 255 is specified, the actual drawing area corresponding to the drawing area defined on the virtual drawing space is specifically the index space IDX in the frame buffer FBa with a double buffer structure 255 is defined to be so.

[0463] In the case of this embodiment, the index number of the frame buffer FBa is 255 or 254 (Fig. 12(a)), and either one toggled is specified (L13). Note that this index number is the index number of the side other than the display area (0) / (1) specified in step ST6 of the main control process. For example, in the process of step ST6, when the display area (0) is specified for the display circuit 74, the display area (1) becomes the "writing area" for the drawing circuit 76.

[0464] As described above, after the correspondence between the actual drawing area (logical space of W×H) and the drawing area (virtual space of W×H) is generally defined by the instruction command L11 and the instruction command L12, the virtual space of W×H is associated with the logical space of W×H in a specific index space IDX by the instruction command L13 (SETINDEX) that specifically specifies the index space IDX.

[0465] In other words, in the future, based on a series of instruction commands, the content virtually drawn in the W×H virtual space will become the image data of the built-in VRAM 71 (frame buffer) based on the conversion table inside the VDP that defines the correspondence between the virtual space and the actual address of the built-in VRAM 71.

[0466] Subsequently, as the "writing area", an instruction command for executing a frame buffer clear process that fills the specified index space IDX with, for example, black is described (L14, L15). This is nothing but the process of erasing the image data written to the frame buffer FBa two operation periods ago.

[0467] Specifically, for example, black is selected by the SETFCOLOR command, which is a type of environment setting command, and it is defined to fill the rectangular area by the RECTANGLE command, which is a primitive drawing system command. In the RECTANGLE command, for the drawing area set in the virtual drawing space (the virtual space corresponding to the frame buffer FBa), the XY coordinates of its upper left endpoint and lower right endpoint are specified (see Fig. 12(c)).

[0468] Through the above processing, the drawing preparation process is completed. Next, instruction commands for drawing an appropriate texture such as a still image or a single frame of a video in the virtual drawing space are listed. Typically, first, after specifying the index space IDX where the texture will be expanded by the SETINDEX command of the texture setting system, the TXLOAD command, which is an instruction command of the texture loading system, is described in the display list DL so that a predetermined texture read from the CGROM 55 is expanded to the predetermined index space IDX.

[0469] As described above, in this embodiment, the background video is composed of an IP stream video. Therefore, for example, regarding the background video, after identifying the index space IDX to be expanded for this as the index space IDX0 of the page area (b) using the SETINDEX command of the texture setting system, the TXLOAD command of the texture loading system is described. Note that in the TXLOAD command, it is necessary to specify the start address (texture Source address) of the CGROM55 and the data size after expansion (horizontal × vertical) for the video frame to be loaded this time.

[0470] In the VDP circuit 52, when the above TXLOAD command is executed, one video frame (texture) of the background video is first acquired in the AAC area (a), and then is expanded to the index space IDX0 of the page area (b) by the automatically started GDEC75. Next, this one video frame will be drawn in the virtual drawing space. In this case, it may be set by the SETINDEX command (texture setting system) that "the index space IDX0 of the page area (b) is the texture to be processed later", but when processing continuously with the TXLOAD command, the description of this SETINDEX command can be omitted.

[0471] In any case, with the state where "the index space IDX0 of the page area (b) is the texture to be processed later" identified, next, appropriate drawing intermediate operation system instruction commands are described, such as setting parameters for the α-blending process. Note that the α-blending process relates to the transparency / translucency process between the image already described in the drawing area (frame buffer FBa) and the image to overwrite it. Therefore, for the first drawing operation like the video frame of the background video, the use of the drawing intermediate operation system instruction command is unnecessary.

[0472] Subsequently, a SPRITE command, which is an instruction command for primitive drawing, is described to draw the "texture (one video frame of the background video) in the index space IDX0 of the page area (b)" at an appropriate position (rectangular Destination area) in the virtual drawing space. Note that for the Destination area in the virtual drawing space, it is necessary to specify its upper left endpoint and lower right endpoint in the SPRITE command.

[0473] This Destination area is, in advance, the whole or a part of the drawing area (virtual space defined on the virtual drawing space) associated with the actual drawing area (FBa) by the instruction commands L11 and L12. However, since the background video is usually drawn on the entire display screen, in such a case, the Destination area will be the whole or more of the drawing area. Note that the case where the Destination area is larger than the whole of the drawing area is, for example, when the background video is zoomed in.

[0474] Through the above processing, the drawing of the video frame of the background video is completed. Subsequently, instruction commands such as texture load system, texture setting system, drawing intermediate calculation system, and primitive drawing system commands are listed in an appropriate order to construct a display list DL to draw various textures over the background video. As described above, during variable effects, a large number of videos are required. In that case, for the page area (b) of the built-in VRAM71, an instruction command (NEWPIX) of the index table control system is described to increase the index space IDX.

[0475] For example, regarding the second IP stream video, after securing an additional index space IDX1 in the page area (b) by the NEWPIX command, this index space IDX1 is specified (SETINDEX), the expansion of one frame of the second video is instructed (TXLOAD), and the expanded texture is placed at an appropriate position in the drawing area (SPRITE). Usually, the Destination area in this case is a part of the drawing area.

[0476] The following is the same. By the NEWPIX command, the index space IDX is successively secured, and then while performing appropriate alpha blending processing, if a plurality of IP streams are drawn in the drawing area, the drawing content in the drawing area will be sequentially accumulated as image data in the frame buffer FBa which is the actual drawing area. When a plurality of N IP stream videos are being drawn, in the page area (b), a plurality of N index spaces are functioning. k

[0477]

[0478] k

[0479] In addition, when drawing a still image or an I stream video, after specifying by the SETINDEX command that the decoding destination of these textures is the AAC area (a), if the TXLOAD command is executed, the textures acquired in the AAC area (a) will then be automatically expanded in the ACC area (a) by GDEC75 which starts automatically. And the expanded textures may be drawn at appropriate positions in the drawing area by the SPRITE command. Depending on whether the cache hit function is utilized or not, either the first AAC area (a1) or the second AAC area (a2) is used.

[0479] In the description so far, each texture is directly drawn in the drawing area of the main display device DS1, but it is not necessarily limited to such an operation. For example, an appropriate drawing area may be provided (Fig. 12(c)) without overlapping the drawing area already secured for the display device DS1, and if this drawing area is associated with the working area of the built-in VRAM71, an intermediate drawing area can be constructed to complete an appropriate production image. Here, the reason for not overlapping with the drawing area for the display device DS1 is that for the overlapping area, the subsequent association setting takes precedence and the drawing content for that area is not reflected in the frame buffer FBa.

[0480] As shown in Fig. 12(c), the working area of this embodiment is the index space IDX0 in the arbitrary area (c). And at the production timing when this working area is used, an instruction command sequence (SETDAVR, SETDAVF, SETINDEX) for associating the drawing area for the production image (see Fig. 12(c)) with the working area (the actual drawing area of the index space IDX0) is described in advance. As shown in Fig. 12(c), the drawing area for the production image is secured in an area not included in the drawing area for the main display device DS1.

[0481] Then, afterwards, instruction commands similar to the instruction command sequence L16 regarding the frame buffer FBa are listed, and an appropriate production image can be completed in the index space IDX0. In the case of this embodiment, since the production image is composed of still images, an instruction command (SETINDEX) is described so that the decoded data is expanded in the first AAC area (a1), and then an instruction command (SPRITE) of the primitive drawing system with the appropriate position in the drawing area of the index space IDX0 as the Destination is used. Note that such an operation is repeated once or multiple times according to the production content.

[0482] After positioning the index space IDX0, which has completed the rendering image, as a texture (SETINDEX), the rendering image (texture) of the index space IDX0 may be drawn at an appropriate position in the drawing area of the main display device DS1 by the SPRITE command. In such a case, it is conceivable to decompose the rendering image of the index space IDX0 into triangular drawing primitives, rotate them at an appropriate angle, and then draw them in the drawing area. Note that the rotation angle of the texture is associated with, for example, the reliability of the preview effect.

[0483] As described above, the instruction command sequence (L11~L16) for completing one frame of the main display device DS1 has been explained. The same applies to the instruction command sequence (L17~L12) for completing one frame of the sub-display device DS2. That is, the start XY coordinates of the frame buffer FBb are specified (L17) and defined (usually X = 0, Y = 0), and a drawing area for the sub-display device DS2 is defined on the virtual drawing space shown in Fig. 12(c) (L18).

[0484] By the way, in this embodiment, after finishing the generation of the image data for the main display device DS1, the process proceeds to the generation process for the sub-display device DS2. Therefore, even if the drawing area for the sub-display device DS2 overlaps with the drawing area for the main display device DS1, there is no problem, and the drawing area can be freely set. Therefore, when developing the generation program of the display list DL, for example, when appropriately attaching a texture to the newly set drawing area by the SPRITE command, the setting of the operation parameters (Destination area) of the SPRITE command and the like can be standardized to a certain extent.

[0485] Once the definition of such an arbitrary drawing area is completed (L18), next, for the frame buffer FBb of the display device DS2 with a double buffer configuration, an index space IDX that becomes the "writing area" of the drawing content based on the current display list DL is specified (L19). The index number of this index space IDX is the index number that does not correspond to the display area (0) / (1) specified in step ST6 of the main control process with respect to the frame buffer FBb.

[0486] And then, thereafter, the instruction command sequences L20 to L22 for the sub-display device DS2 are listed in the same manner as the instruction command sequences L14 to L16 for the main display device DS1. Also, the production image completed in the index space IDX0 can be used.

[0487] As described above, in this embodiment, all the instruction commands L11 to L22 constituting the display list DL are limited to those whose command length is an integer multiple of 32 bits. And as previously explained, the data volume value (total data amount) of the display list DL of this embodiment is adjusted to a fixed length (256 bytes), and after adding the required number of NOP commands (L23) as dummy commands, it is terminated with an EODL command (L24). That is, in the embodiment of FIG. 23, the above-described standard method (B) is adopted.

[0488] However, even when adopting the standard method (B), it is not always essential to fix the total data amount of the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, when the total data amount of the display list DL excluding the NOP commands exceeds 256 bytes (for example, during a special production period), the total data amount of the display list DL is adjusted to 512 bytes or more, N×256 bytes, by adding NOP commands. Note that when adopting the standard method (B), as previously explained, the end of N×256 bytes is terminated with an EODL command.

[0489] The configuration of the display list DL has been described in detail above. However, the effect control CPU 63 issues the completed fixed-byte-length display list DL to the VDP circuit (ST7 to ST8). FIG. 24 is a flowchart for explaining the DL issuance process (ST8 in FIG. 22) in which the effect control CPU 63 directly performs a WRITE access to the transfer port register TR_PORT of the transfer circuit 72 and issues the display list DL to the drawing circuit 76. Note that the transfer port register TR_PORT is a type of data transfer register RGij that defines the operation details of the data transfer circuit 72.

[0490] To implement the DL issuance process, first, it is necessary to set the necessary set values in a plurality of data transfer registers RGij that define the operation details of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are specified in a predetermined data transfer register RGij. The setting content is not particularly limited, but here, it is set to pass through the ChB control circuit 72b from the CPUIF unit 56 and to execute the data transfer operation while checking the remaining amount of the FIFO buffer for the CPU bus control unit 72d (ST20). In the following description, the ChB control circuit 72b may be abbreviated as the "transfer circuit ChB" for convenience.

[0491] Next, the total transfer size is set in a predetermined data transfer register RGij. As described above, in this embodiment, since the total data amount of the display list DL is adjusted to an integer multiple of 256 bytes, that value is set. Note that the total data amount = 256 × N is also an integer N times the minimum data amount Dmin of the data transfer circuit 72. Usually, the multiple N is 1 or 2, but in the following description, it will be described with N = 1.

[0492] Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as the transfer port) is a 32-bit long register, the rendering control CPU 63 will execute a register WRITE operation on the transfer port TR_PORT for every 32 bits. Therefore, the value of the management counter CN for managing the number of register WRITEs is initially set to 64 (ST21). Note that when the non-adjustment method (C) is adopted, at this timing, the data transfer amount that is an integer multiple of the minimum data amount Dmin is determined and the management counter CN is set.

[0493] Since the initial setting is completed by the above processing, next, the data transfer operation via the transfer circuit ChB is set to the start state (ST22), and based on the set value to the predetermined drawing register RGij that defines the operation of the drawing circuit 76, the drawing operation is started (ST23). As a result, thereafter, for the instruction command sequence in which the rendering control CPU 63 performs a register WRITE operation on the transfer port TR_PORT, a rapid and smooth Analyze process by the drawing circuit 76 (display list analyzer) is ensured.

[0494] Note that for a rapid and smooth Analyze process, the fact that the instruction commands listed in the display list DL are limited to instruction commands that are integer multiples of 32 bits in command length also contributes effectively. The timings t1, t2, t3, t4 in FIG. 30(a) indicate the operation timings of step ST23. Note that since the issuance process (ST8) of the display list DL ends quickly, the time width required for the issuance process is not described in FIGS. 30 to 31.

[0495] Subsequently, it is confirmed whether the setting in step ST22 has functioned (ST24). This is because the initial setting of each part of the data transfer circuit 72 takes longer processing time than the register WRITE operation (setting operation) by the production control CPU 63, so as not to give subsequent instructions to the data transfer circuit 72 in an incomplete state. And if, by any chance, it does not enter the operation start state even after waiting for a predetermined time, the serious abnormality flag ABN is set and the DL issuance process is terminated (ST25). As a result, thereafter, the WDT circuit 58 functions and the composite chip 50 is abnormally reset (ST10).

[0496] Note that, as described above, in order to avoid resetting the CPU circuit 51, the production control CPU 63 may output a predetermined keyword sequence to the pattern check circuit CHK and abnormally reset only the VDP circuit 52 based on the reset signal RST.

[0497] However, normally, the setting in step ST22 is completed quickly. Subsequently, for the FIFO buffer (32 bits × 130 stages) of the CPU bus control unit 72d, after confirming that the FIFO buffer is not full (ST26), instruction commands are written to the transfer port TR_PORT one by one in order from the head line constituting the display list DL (ST28).

[0498] Then, while decrementing the management counter CN (ST29), the processes of steps ST26 to ST29 are repeated until the management counter CN becomes zero (ST30). In the case of this embodiment, since the minimum data amount Dmin is defined in the data transfer circuit 72, the data transfer operation is executed at the timing when the minimum data amount Dmin is accumulated in the FIFO buffer, resulting in an intermittent transfer operation.

[0499] In any case, in this embodiment, the DL issuance process (ST28) is completed quickly. However, if the settings in the VDP register RGij conflict due to the influence of noise or the like, in the determination of step ST26, there may be a case where the FIFO buffer full state is not resolved even after waiting for a predetermined time. And in such a case, after setting the initialization data in the predetermined VDP register RGij, initializing the drawing circuit 76 and the data transfer circuit 72, a critical abnormality flag ABN is set and the DL issuance process is terminated (ST27).

[0500] By the way, at this timing, the data transfer circuit 72 and the drawing circuit 76 have already started operating and have completed a certain degree of processing. Therefore, for the initialization process of the drawing circuit 76, with the content of the drawing register RGij maintained, (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial states, (3) initializing GDEC75, and (4) initializing the cache state of the AAC region are included. Similarly, the initialization process of the data transfer circuit 72 includes the initialization process of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

[0501] Note that in the above initialization process of step ST27, although the content of the drawing register RGij is maintained, for a predetermined drawing register, its content may be initialized. The predetermined drawing registers to be cleared to their initial values include (a) an execution control register for setting the start of drawing execution (see ST23 in FIG. 24), (b) a status register indicating the execution status of the drawing circuit 76, and (c) a status register for specifying the position of the currently processed display list.

[0502] In any case, as a result of setting the critical abnormality flag ABN, subsequently, the WDT circuit 58 and the effect control CPU 63 function, and the composite chip 50 or the VDP circuit 52 is abnormally reset (ST10a). Therefore, the process of initializing the drawing circuit 76 and the data transfer circuit 72 is not necessarily essential. On the other hand, when initializing the drawing circuit 76 and the data transfer circuit 72, as a result, abnormal recovery can be expected. Therefore, it is also preferable to return to the process of step ST20 and re-execute the DL issuance process without setting the critical abnormality flag ABN.

[0503] This is the same in the process of step ST25. It is preferable to return to the process of step ST20 without setting the critical abnormality flag ABN after initializing the data transfer circuit 72 and the drawing circuit 76. However, in such a case, the number of re-executions of the DL issuance process is counted. If the number of re-executions exceeds the limit value, the critical abnormality flag ABN is set and the DL issuance process is terminated.

[0504] FIG. 24(b) schematically shows a normal operating state. As shown, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and the operations based on each instruction command are executed. This operation is executed in parallel with the DL issuance process of the display list DL and the data transfer operation (ST26 to ST30) of the data transfer circuit 72.

[0505] For example, when the instruction command (TXLOAD) is executed, the necessary texture is read from the CGROM 55 and acquired in the AAC area (a). Then, the GDEC 75 is automatically activated to execute the decoding operation, and the decoded data is expanded in a predetermined index space. Also, depending on the instruction command, the geometry engine 77 and others function. In any case, the respective parts of the drawing circuit 76 cooperate to complete the image data corresponding to the display list DL in the frame buffers FBa and FBb.

[0506] Next, a case where the display list DL is issued via the DMAC circuit 60 will be described with reference to FIG. 25. Without any limitation, among the first to fourth DMA channels built in the DMAC circuit 60, the third DMA channel will be used.

[0507] In the embodiment of FIG. 25, first, a predetermined data transfer register RGij and a predetermined drawing register RGij are each set to a clear value to initialize the data transfer circuit 72 and the drawing circuit 76 (ST20). This process is the same as the error process in step ST27 of FIG. 24. The internal circuit of the data transfer circuit 72 including the FIFO buffer is initialized, the status bit of the data transfer register indicating the progress state of data transfer becomes the initial value, and the bit indicating that the entire data transfer is being initialized becomes a predetermined value.

[0508] The same applies to the drawing circuit 76, which includes the processes of (1) setting the internal parameters to the initial values, (2) setting the internal control circuit to the initial state, (3) initializing the GDEC75, and (4) initializing the cache state of the AAC region. Also, in the initialization process of the drawing circuit (ST20 in FIG. 25), the above-mentioned predetermined drawing register RGij may be initialized. In the process of FIG. 24, such an initialization process may be executed first.

[0509] In the process of FIG. 25, next, it is confirmed by reading a predetermined status register RGij that specifies the operating states of the data transfer circuit 72 and the drawing circuit 76 that the initialization process has been completed normally (ST21). And if it cannot be initialized by any chance, the critical abnormality flag ABN is set and the process is terminated (ST22). However, such a situation hardly actually occurs.

[0510] Next, the transfer operation mode of the data transfer circuit 72 and the transmission route inside the data transfer circuit 72 are set in a predetermined data transfer register RGij. The setting content is not particularly limited, but here, it is set to pass through the ChB control circuit 72b from the CPUIF unit 56 and to follow the setting to the DMAC circuit 60 regarding the transfer protocol to the CPU bus control unit 72d (ST23).

[0511] Next, the total transfer size is set in a predetermined data transfer register RGij. Similar to the case of FIG. 24, the total data amount = 256. When the unadjusted method (C) is adopted, at this timing, the total transfer size that is an integer multiple of the minimum data amount Dmin is determined and set. Next, based on the set value to a predetermined drawing register RGij, the drawing operation of the drawing circuit 76 is started (ST25). The timings t1, t2, t3, t4 in FIG. 30(a) are also the operation timings of step ST25. Then, after starting the operation of the DMAC circuit 60 (ST26), the data transfer operation of the data transfer circuit 72 is started (ST27).

[0512] The operation start process of the DMAC circuit 60 is as shown in FIG. 25(b). First, in a state where DMAC transfer is prohibited, it waits for the transfer of one cycle of data transfer unit (one operand) to be completed (ST40). The detailed operation content is the same as the process shown in FIG. 26, and is divided into a process of setting DMAC transfer prohibition (ST53) and a subsequent standby process (ST54).

[0513] Such a process is provided because (1) in other embodiments, there is a possibility of using the DMAC circuit 60 (the third DMA channel) in the main control process or the timer interrupt process (FIG. 22), and (2) in other embodiments where the process of step ST5 in FIG. 22 is not provided, the DMAC circuit 60 that has started issuing the display list DL may not be able to complete the DL issuing operation within its operation cycle (δ).

[0514] In the exceptional situation as described above, if a new set value (such as a conflicting set value) is additionally set for the operating DMAC circuit 60, no normal DMA operation is guaranteed at all, and serious troubles are feared. However, by providing the process of step ST40, normal operation based on subsequent set values is guaranteed. That is, even in a modified embodiment obtained by partially modifying this embodiment, normal DMA operation can be realized regardless of the preceding troubles.

[0515] If the process of step ST40 having the above significance is executed, next, the operating conditions of the DMAC circuit 60 are set (ST41). Specifically, as shown in FIG. 9, the cycle steal transfer mode is selected, and one operand transfer is set to 32-bit transfer × 2 times. Also, since the Source address is the address of the list buffer area (DL buffer BUF) of the RAM 59, it should be recognized as sequentially increasing, while the Destination address should be a fixed value because it is the transfer port TR_PORT.

[0516] Next, the head address of the DL buffer BUF of the RAM 59 is set to a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer port TR_PORT, which is the transfer destination address, is set (ST43). Also, after setting the total transfer size, that is, the total data amount of the display list DL, to 256 bytes (ST44), the DMA operation of the DMAC circuit 60 is started (ST45).

[0517] By the way, the explanations so far have been based on the premise that the actual bit length of the instruction command is an integer multiple of 32 bits for all. However, since the configurations of the display list DL and the instruction command are not necessarily limited, the following describes such cases.

[0518] For example, even when adopting the above-described unadjusted method (C), when the total amount of data X in the display list DL is an arbitrary value X that is not a multiple of 32 bits, in the process of step ST44, this arbitrary value X is adjusted to an appropriate transfer amount MOD, and then the setting process of the total transfer size is executed. Here, the appropriate transfer amount MOD is defined based on the setting content for one-operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

[0519] Specifically, if the one-operand transfer setting is N bytes × M times, the transfer amount MOD is adjusted to a value that is an integer multiple of N×M (bytes) and also an integer multiple of Dmin (bytes). For example, if N×M = 8×4 and Dmin = 256, an arbitrary value X (=300) bytes is adjusted to a transfer amount MOD (=512) bytes.

[0520] As described above, including the general theory, the DMA operation of the DMAC circuit 60 starts a cycle steal transfer operation as shown in FIG. 9, and without particularly inhibiting the operation of the CPU, the display list DL is transferred to the transfer port TR_PORT every 32 bits in the case of the embodiment. Then, the transferred data is transferred to the drawing circuit 76 via the transfer circuit ChB.

[0521] To realize such an operation, in this embodiment, following the process of step ST45, the transfer operation of the data transfer circuit 72 is started to end the process (ST27). After that, the data transfer circuit 72 receives the instruction command sequence of the display list DL from the DMAC circuit 60 with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. Then, the drawing circuit 76 executes a drawing operation based on the instruction commands of the display list DL. Therefore, after the process of step ST27, the effect control CPU 63 can start the process of step ST11 in FIG. 22, and can control voice effects, lamp effects, motor effects, etc. in parallel with the drawing operation by the VDP circuit 52 (DL issuance process by the DMAC circuit 60).

[0522] Figure 25(c) illustrates the details of this operation. Prior to the DMA transfer, the operation of the rendering circuit is started (ST25). The display list analyzer of the rendering circuit 76 executes the Analyze process quickly and smoothly. In addition, based on the operations of the GDEC 75, the geometry engine 77, etc., for each display device DS1, DS2, image data for one frame is generated in the frame buffers FBa, FBb.

[0523] Incidentally, the configuration of FIG. 25 that ends the DL issuance process in the process of step ST27 is not necessarily limited. For example, as shown in FIGS. 32 to 33, when voice effects, lamp effects, and motor effects are controlled by another CPU, it is preferable to confirm the normal operation of the DMAC circuit 60 and the data transfer circuit 72 after the process of step ST27. FIG. 26 is a flowchart for explaining the operation following step ST27 of FIG. 25 and the confirmation process of normal operation.

[0524] First, by referring to a predetermined status register, it is confirmed that the transfer operation of the DMAC circuit 60 has been completed normally (ST50). Also, it is confirmed that the data transfer circuit 72 has completed the transfer operation (ST51). Usually, in such a path, the DL issuance process of FIG. 25 is completed.

[0525] On the other hand, if the operation of the DMAC circuit 60 has not been completed even after waiting for a predetermined time, or if the data transfer circuit 72 has not completed the transfer operation, for the rendering circuit 76 and the data transfer circuit 72, a clear value is set in a predetermined VDP register RGij to initialize t...

Claims

【Claim 1】 A VDP (Video Display Processor) that generates an image signal necessary for image rendering, and a VDP circuit having a VDP register to which setting values that define the operation of the VDP are set, a CPU, an internal circuit that operates under the control of the CPU, and a CPU circuit having an operation control register to which setting values that define the operation of the internal circuit are set, and a gaming machine in which various rendering operations including image rendering are executed, in the memory space accessible by the CPU, there are included a plurality of external address spaces located outside the CPU circuit including the CPU and each capable of defining a data bus width, in the memory space, at least a memory device that stores an initial program to be first executed after reset of the CPU and the VDP register are positioned, in the memory space accessible by the VDP, there are included a CGROM that stores CG compressed data and a video RAM used for generating image data for image rendering, in a predetermined ROM space among the plurality of external address spaces, first address information belonging to the external address space and second address information not belonging to any external address space are stored non-volatilely, after reset of the CPU, the second address information is set to the stack pointer of the CPU and the first address information is set to the program counter of the CPU, so that execution of a predetermined initial program is started, first means for setting necessary setting values to the operation control register in order to optimize the access operation to the memory device, and then, second means for setting necessary operation parameters to the VDP register so as to function based on the operation of the initial program before the start of the image rendering operation and optimize the access operation to the CGROM. A gaming machine characterized by comprising the above.

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