Gaming machine

Abstract

To provide a game machine capable of making a configuration regarding a setting value suitable.SOLUTION: Based on execution of setting change operation when operating power starts to be supplied, setting value update processing is started. By switching of a setting key insertion part 68a from an ON state to an OFF state, setting value update processing is completed. A main-side RAM 65 includes a setting reference area for storing information on a setting value to be used, and a setting update area for storing information on a setting value selected as an update target in setting value update processing. In a stop of supply of operating power during execution of setting value update processing, the setting value update processing can be started even if setting confirmation operation is performed when resuming supply of operating power, and at the same time a setting value is changed from the setting value selected in the last setting value update processing. In the meantime, when RAM clearing operation is performed, the setting value update processing is not performed.SELECTED DRAWING: Figure 6

Description

Technical Field

[0001] The present invention relates to a gaming machine.

Background Art

[0002] As gaming machines, pachinko machines and slot machines are known. For example, a pachinko machine includes a dish storage unit for storing game balls given to a player on the front surface of the gaming machine. The game balls stored in the dish storage unit are guided to a game ball launching device and launched toward the game area according to the player's launching operation. Then, for example, when a game ball enters a ball entry unit provided in the game area, game balls are paid out from a payout device to the dish storage unit. In addition, in a pachinko machine, a configuration including an upper dish storage unit and a lower dish storage unit as dish storage units is also known. In this case, the game balls stored in the upper dish storage unit are guided to the game ball launching device, and the game balls that become surplus in the upper dish storage unit are discharged to the lower dish storage unit (see, for example, Patent Document 1).

[0003] In addition, in a slot machine, when a start lever is operated in a situation where medals are bet and a new game is started, a lottery process is executed by control means. Further, when the lottery process is executed, rotation start control is executed by the control means to start the rotation of the reel. When the stop button is operated during the rotation of the reel, rotation stop control is executed by the control means to stop the rotation of the reel. Then, when the stop result after the rotation stop of the reel corresponds to the winning combination of the lottery process, a privilege corresponding to the winning combination is given to the player.

Prior Art Documents

Patent Documents

[0004]

Patent Document 1

Summary of the Invention

Problems to be Solved by the Invention

[0005] Here, in a gaming machine such as the above-described example, It is necessary to suitably manage the gaming machine, there is still room for improvement in this regard.

[0006] The present invention has been made in view of the above-described circumstances and the like, It is possible to suitably manage the gaming machine and aims to provide a gaming machine.

Means for Solving the Problems

[0007] In order to solve the above problems, the invention according to claim 1 includes a history storage execution means for storing, in a history storage means, history information of a game corresponding to a predetermined event when the predetermined event occurs by executing a game; an information derivation means for deriving mode information corresponding to a game result by using the history information stored in the history storage means; a mode information storage means for storing the mode information derived by the information derivation means; a mode information display control means for performing control so that a display corresponding to the mode information stored in the mode information storage means is performed by an information display means; a predetermined corresponding display control means for performing control so that a predetermined corresponding display is performed by the information display means before a display corresponding to the mode information is newly started based on the occurrence of a predetermined display opportunity; a setting means for setting a set value corresponding to the advantage degree of a player; a situation generation means for making it a settable situation in which the set value can be set by the setting means; and the mode information storage means includes a plurality of specific storage areas so as to be able to store each of the plurality of mode informations, The mode information display control means performs control so that displays corresponding to each of the plurality of pieces of mode information stored in the plurality of specific storage areas are sequentially executed by the information display means according to a predetermined display order. When causing the information display means to perform a display corresponding to the mode information after the predetermined corresponding display has been performed by the information display means, it starts from the display corresponding to the mode information corresponding to the first order in the predetermined display order. The information derivation means derives the mode information by using the history information in a predetermined advantageous period. This gaming machine includes control means for executing various processes, and predetermined storage means for storing information when a process is executed by the control means. It is characterized by The control means An in-area processing execution means for executing in-area processing, which is processing using a program stored in a storage area within a predetermined address range in a program storage means, An out-of-area processing execution means for executing out-of-area processing, which is processing using a program stored in a storage area outside the predetermined address range in the program storage means, When the supply of operating power is started, it includes means for calculating predetermined numerical information corresponding to a predetermined plurality of information stored in the predetermined storage means, and means for specifying whether the predetermined numerical information is normal. It is characterized by Information on the area for storing information on the set value set by the setting means is included in the predetermined plurality of information and this gaming machine has an in-area corresponding storage area where writing and reading of information are possible when the in-area processing is executed, while reading of information is possible but writing of information is not possible when the out-of-area processing is executed, and an out-of-area corresponding storage area where writing and reading of information are possible when the out-of-area processing is executed, while reading of information is possible but writing of information is not possible when the in-area processing is executed, and the in-area processing execution means includes means capable of executing, as the in-area processing, processing for making the set value set as a use target visually confirmable in a situation where the processing at the start of supply of operating power has ended and the game can start. This is characterized.

Effects of the Invention

[0008] According to the present invention, It is possible to suitably manage the gaming machine it becomes

Brief Description of the Drawings

[0009]

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Mode for Carrying Out the Invention

[0010] <First Embodiment> Hereinafter, a first embodiment of a pachinko game machine (hereinafter referred to as a "pachinko machine"), which is a type of gaming machine, will be described in detail with reference to the drawings. FIG. 1 is a perspective view of the pachinko machine 10, and FIG. 2 is a perspective view showing the main components of the pachinko machine 10 disassembled. In FIG. 2, for convenience, the components within the game area PA of the pachinko machine 10 are omitted.

[0011] As shown in FIG. 1, the pachinko machine 10 includes an outer frame 11 that forms the outer shell of the pachinko machine 10, and a game machine main body 12 that is rotatably attached to the front of the outer frame 11. The outer frame 11 is formed by connecting wooden plates on four sides and has a rectangular frame shape. The pachinko machine 10 is installed in a game hall by attaching and fixing the outer frame 11 to the island equipment. Note that the outer frame 11 is not an essential component of the pachinko machine 10, and it may be configured such that the outer frame 11 is provided in the island equipment of the game hall.

[0012] As shown in FIG. 2, the gaming machine main body 12 includes an inner frame 13, a front door frame 14 disposed in front of the inner frame 13, and a back pack unit 15 disposed behind the inner frame 13. The inner frame 13 of the gaming machine main body 12 is rotatably supported by the outer frame 11. Specifically, the inner frame 13 is rotatable forward with the left side as the rotation base end side and the right side as the rotation tip end side in a front view.

[0013] The front door frame 14 is rotatably supported by the inner frame 13 and is rotatable forward with the left side as the rotation base end side and the right side as the rotation tip end side in a front view. Further, the back pack unit 15 is rotatably supported by the inner frame 13 and is rotatable backward with the left side as the rotation base end side and the right side as the rotation tip end side in a front view.

[0014] Note that the gaming machine main body 12 is provided with a locking device at its rotation tip end portion and has a function of locking the gaming machine main body 12 in a non-openable state with respect to the outer frame 11, and also has a function of locking the front door frame 14 in a non-openable state with respect to the inner frame 13. These locked states are each released by performing an unlocking operation using an unlocking key on a cylinder lock 17 provided to be exposed on the front surface of the pachinko machine 10.

[0015] Next, the configuration on the front side of the gaming machine main body 12 will be described.

[0016] The inner frame 13 is mainly composed of a resin base 21 whose outer shape is substantially the same as that of the outer frame 11. A substantially elliptical window hole 23 is formed in the central portion of the resin base 21. A game board 24 is detachably attached to the resin base 21. The game board 24 is made of plywood, and a game area PA formed on the front surface of the game board 24 is exposed on the front side of the inner frame 13 through the window hole 23 of the resin base 21.

[0017] Here, the configuration of the game board 24 will be described with reference to FIG. 3. FIG. 3 is a front view of the game board 24.

[0018] An inner rail section 25 and an outer rail section 26 are attached to the game board 24 so as to define a part of the outer edge of the game area PA, and these inner rail section 25 and outer rail section 26 form a guide rail as a guide means. Game balls launched from a game ball launching mechanism 27 (see Figure 2) attached below the window hole 23 in the resin base 21 are guided to the upper part of the game area PA by the guide rail.

[0019] The game ball launching mechanism 27 includes a launching rail 27a extending toward the guide rail, a ball feeding device 27b that supplies game balls stored in an upper tray 55a (described later) onto the launching rail 27a, and a solenoid 27c that is an electric actuator that launches the game balls supplied onto the launching rail 27a toward the guide rail. When a launching operation device (or operation handle) 28 provided on the front door frame 14 is rotated, the solenoid 27c is driven and controlled, and the game balls are launched.

[0020] A plurality of large and small openings are formed in the game board 24, penetrating in the front-to-rear direction. Each opening is provided with a general winning opening 31, a special electric winning device 32, a first operating opening 33, a second operating opening 34, a through gate 35, a variable display unit 36, a special symbol unit 37, and a general symbol unit 38. There are four general winning openings 31 in total, and one of each of the others.

[0021] Even if a ball enters the through gate 35, no game balls will be paid out. On the other hand, if balls enter the general winning opening 31, the special electric winning device 32, the first operating opening 33, and the second operating opening 34, a predetermined number of game balls will be paid out. Specifically, when one game ball enters the first operating opening 33 or when one game ball enters the second operating opening 34, one prize ball will be paid out; when one game ball enters the general winning opening 31, ten prize balls will be paid out; and when one game ball enters the special electric winning device 32, fifteen prize balls will be paid out.

[0022] Incidentally, the number of prize balls is arbitrary. For example, the second operation port 34 may be configured to have a smaller number of prize balls than the first operation port 33, or the second operation port 34 may be configured to have a larger number of prize balls than the first operation port 33.

[0023] In addition, an out port 24a is provided at the lowermost part of the game board 24, and game balls that have not entered various winning ports or the like are discharged from the game area PA through the out port 24a. Also, a large number of nails 24b are implanted in the game board 24 to appropriately disperse and adjust the falling direction of the game balls, and various members such as windmills are arranged.

[0024] Here, "entering the ball" means that the game ball passes through a predetermined opening, and it includes not only the mode of being discharged from the game area PA after passing through the opening, but also the mode of continuing to flow down in the game area PA without being discharged from the game area PA after passing through the opening. However, in the following description, in order to clearly distinguish from the entry of the game ball into the out port 24a, the entry of the game ball into the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the through gate 35 is also expressed as "winning".

[0025] The first operation port 33 and the second operation port 34 are unitized as an operation port device and installed on the game board 24. Both the first operation port 33 and the second operation port 34 are open upward. Also, the two operation ports 33 and 34 are arranged in the vertical direction with the first operation port 33 above. A general electric accessory 34a as a guide piece composed of a pair of left and right movable pieces is provided at the second operation port 34. In the closed state of the general electric accessory 34a, the game ball cannot win at the second operation port 34, and when the general electric accessory 34a is in the open state, winning at the second operation port 34 becomes possible.

[0026] A through gate 35 is provided on the upstream side in the flowing direction of the game ball from the second operation port 34. The through gate 35 has a through hole (not shown) penetrating in the vertical direction, and the game ball that wins at the through gate 35 flows down in the game area PA after winning. Thereby, it is possible for the game ball that wins at the through gate 35 to win at the second operation port 34.

[0027] Based on a win at the through gate 35, the normal power device 34a of the second operating port 34 is switched from a closed state to an open state. Specifically, an internal lottery is performed with the win at the through gate 35 as a trigger, and a variable picture display is performed on the normal map display section 38a of the normal map unit 38, which is located in the lower right corner of the game area PA, an area where the game ball does not pass. Then, when the result of the internal lottery is a win for the electric role release, the stop result corresponding to that result is displayed, and the variable display on the normal map display section 38a is terminated, the game transitions to the normal power open state. In the normal power open state, the normal power device 34a is opened in a predetermined manner.

[0028] The map display unit 38a is configured with a segment display in which a plurality of LED display segments are arranged in a predetermined manner, but is not limited to this and may be configured with other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT or a dot matrix display device, etc. The image displayed variably on the map display unit 38a may be configured to variably display multiple types of letters, multiple types of symbols, multiple types of characters, or multiple types of colors that are switched between.

[0029] In the normal map unit 38, a normal map reserve display unit 38b is provided adjacent to the normal map display unit 38a. Up to four game balls that enter the through gate 35 are reserved, and the number of reserved balls is displayed by lighting up the normal map reserve display unit 38b.

[0030] A winning lottery is triggered by the entry into the first operating port 33 or the second operating port 34. The result of the lottery is then displayed clearly through the display effects on the special symbol unit 37 and the symbol display device 41 of the variable display unit 36.

[0031] Regarding the special figure unit 37 in detail, the special figure unit 37 is provided with a special figure display section 37a. The display area of the special figure display section 37a is narrower than the display surface 41a of the symbol display device 41. In the special figure display section 37a, a winning lottery is conducted by taking winning at the first operation port 33 or winning at the second operation port 34 as a trigger, and a variable display of the pattern or a predetermined display is performed. Then, a result corresponding to the lottery result is displayed. Note that the special figure display section 37a is configured by a segment display device in which a plurality of display segments by LEDs are arranged in a predetermined manner, but it is not limited thereto, and it may be configured by other types of display devices such as a liquid crystal display device, an organic EL display device, a CRT, or a dot matrix display. Also, as the pattern displayed in the special figure display section 37a, a configuration in which a plurality of types of characters are displayed, a configuration in which a plurality of types of symbols are displayed, a configuration in which a plurality of types of characters are displayed, or a configuration in which a plurality of types of colors are displayed, etc. can be considered.

[0032] In the special figure unit 37, a special figure hold display section 37b is provided at a position adjacent to the special figure display section 37a. The number of game balls that have won at the first operation port 33 or the second operation port 34 is held up to a maximum of 4, and the held number is displayed by lighting the special figure hold display section 37b.

[0033] Regarding the symbol display device 41 in detail, the symbol display device 41 is configured as a liquid crystal display device including a liquid crystal display, and the display content is controlled by a display control device described later. Note that the symbol display device 41 is not limited to a liquid crystal display device, and it may be another display device having a display screen such as a plasma display device, an organic EL display device, or a CRT, or it may be a dot matrix display.

[0034] In the symbol display device 41, when a winning occurs at the first operation port 33 or the second operation port 34, and a special symbol display unit 37a performs a variable display of symbols or a predetermined display, the symbol display device 41 performs a variable display of symbols or a predetermined display accordingly. For example, on the display surface 41a of the symbol display device 41, three symbol columns, namely an upper row, a middle row, and a lower row, are set as a plurality of display areas, and main symbols with numbers from "1" to "9" are arranged in ascending or descending order in each symbol column and are scrolled and displayed. In this scroll display, first, the scroll display in all symbol columns is started, and the scroll display is switched to the standby display in the order of the upper symbol column → the lower symbol column → the middle symbol column, and finally, it ends with a predetermined symbol being stationary displayed in each symbol column. Then, in a game round where the game result is a big win result, a combination of predetermined symbols is stopped and displayed on an effective line preset on the display surface 41a of the symbol display device 41. Specifically, when it is the most advantageous big win result described later, the same combination of odd symbols is stopped and displayed; when it is the low probability big win result described later, the same combination of even symbols is stopped and displayed; when it is the low winning high probability big win result described later, a combination of symbols that is not the same combination but is not stopped and displayed when it is not the low winning high probability big win result is stopped and displayed.

[0035] Note that in the symbol display device 41, not only the display effect triggered by winning at the first operation port 33 or the second operation port 34, but also the display effect during the opening and closing execution mode that transitions after winning and being selected is performed. Also, based on winning at any of the operation ports 33, 34, the display is started by the special symbol display unit 37a and the symbol display device 41, and one game round corresponds to the period from the start of the display until a predetermined result is displayed and ended. Also, the mode of the variable display of symbols in the symbol display device 41 is not limited to the above and is arbitrary, and the number of symbol columns, the direction of the variable display of symbols in the symbol column, the number of symbols in each symbol column, etc. can be changed as appropriate. Also, the symbols that are variably displayed by the symbol display device 41 are not limited to the symbols as described above, and for example, a configuration where only numbers are variably displayed as symbols may be adopted.

[0036] If a jackpot is won in a lottery based on a win through the first actuation port 33 or the second actuation port 34, the system transitions to an open / close execution mode in which a prize can be won in the special electric prize winning device 32. The special electric prize winning device 32 includes a large prize winning port (not shown) that leads to the back side of the game board 24, and an open / close door 32a that opens and closes the large prize winning port. The open / close door 32a is positioned in either a closed state or an open state. Specifically, the open / close door 32a is normally in a closed state in which game balls cannot win, and is switched to an open state in which game balls can win if an internal lottery is selected to transition to the open / close execution mode. The open / close execution mode is a mode that is transitioned to when a win is achieved. Note that while a prize can be won in the closed state, it may be configured to be less likely to win than in the open state.

[0037] FIG. 4 is an explanatory diagram for explaining the configuration regarding the discharge of game balls that have flowed down the game area PA.

[0038] As already explained, a gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is discharged from the gaming area PA. In other words, a gaming ball that is launched from the gaming ball launching mechanism 27 and flows into the gaming area PA is discharged from the gaming area PA by entering any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a. A gaming ball that enters any of the general winning opening 31, the special electric winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a is guided to the back side of the gaming board 24.

[0039] On the back of the game board 24, discharge passages 42-48 are formed corresponding to the general winning opening 31, the special winning device 32, the first operating opening 33, the second operating opening 34, and the outlet 24a, respectively. The game balls that flow into the discharge passages 42-48 flow down the discharge passages 42-48, and are guided to the lower end of the game board 24 on the back side of the game board 24, where they are collected by a discharge ball collection section (not shown). The game balls collected by the discharge ball collection section are then discharged to a ball circulation device of the island equipment where the pachinko machine 10 is installed in the game hall.

[0040] Each of the discharge passage portions 42 to 48 is provided with various detection sensors 42a to 48a for detecting game balls. These discharge passage portions 42 to 48 and the detection sensors 42a to 48a will be described below. Since four general winning openings 31 are provided as already described, there are discharge passage portions 42 to 44 corresponding to each of the four. In this case, one detection sensor 42a and 43a is provided for each of the first discharge passage portion 42 corresponding to the leftmost general winning opening 31 and the second discharge passage portion 43 adjacent to the right thereof corresponding to the general winning opening 31. Specifically, the first winning opening detection sensor 42a is provided at an intermediate position in the first discharge passage portion 42 so that a detection range exists, and the second winning opening detection sensor 43a is provided at an intermediate position in the second discharge passage portion 43 so that a detection range exists. A game ball that enters the leftmost general winning opening 31 is detected by the first winning opening detection sensor 42a while passing through the first discharge passage portion 42, and a game ball that enters the general winning opening 31 adjacent to the right thereof is detected by the second winning opening detection sensor 43a while passing through the second discharge passage portion 43. Further, a third discharge passage portion 44 is provided so as to merge at an intermediate position with respect to the two general winning openings 31 on the right side. The third discharge passage portion 44 has an entrance-side region corresponding to each of the two general winning openings 31, and has one exit-side region by the merging of these entrance-side regions in the middle. The third winning opening detection sensor 44a is provided at an intermediate position in the exit-side region of the third discharge passage portion 44 so that a detection range exists. A game ball that enters any one of the two general winning openings 31 on the right side is detected by the third winning opening detection sensor 44a while passing through the third discharge passage portion 44.

[0041] A fourth discharge passage section 45 exists corresponding to the special electric winning device 32. A special electric detection sensor 45a is provided so that a detection range exists at a position midway through the fourth discharge passage section 45, and a gaming ball that enters the special electric winning device 32 is detected by the special electric detection sensor 45a as it passes through the fourth discharge passage section 45. A fifth discharge passage section 46 exists corresponding to the first operating port 33. A first operating port detection sensor 46a is provided so that a detection range exists at a position midway through the fifth discharge passage section 46, and a gaming ball that enters the first operating port 33 is detected by the first operating port detection sensor 46a as it passes through the fifth discharge passage section 46. A sixth discharge passage section 47 exists corresponding to the second operating port 34. A second operating port detection sensor 47a is provided so that its detection range exists at a midpoint of the sixth discharge passage section 47, and a gaming ball that enters the second operating port 34 is detected by the second operating port detection sensor 47a as it passes through the sixth discharge passage section 47. A seventh discharge passage section 48 exists corresponding to the outlet 24a. An outlet detection sensor 48a is provided so that its detection range exists at a midpoint of the seventh discharge passage section 48, and a gaming ball that enters the outlet 24a is detected by the outlet detection sensor 48a as it passes through the seventh discharge passage section 48.

[0042] A gaming ball that is detected by one of the various detection sensors 42a to 48a will not be detected by the other detection sensors 42a to 48a. A gate detection sensor 49a is also provided for the through gate 35, and a gaming ball that passes through the through gate 35 on its way down the gaming area PA is detected by the gate detection sensor 49a.

[0043] Although electromagnetic induction type proximity sensors are used as the various detection sensors 42a-49a, any sensor can be used as long as it can detect gaming balls individually. The various detection sensors 42a-49a are electrically connected to the main control device 60, which will be described later, and the detection results of the various detection sensors 42a-49a are output to the main control device 60. Specifically, the various detection sensors 42a-49a output a LOW level signal when they are not detecting a gaming ball, and output a HI level signal when they are detecting a gaming ball. However, this is not a limitation, and the relationship between HI and LOW may be reversed.

[0044] As shown in Fig. 2, a front door frame 14 is provided so as to cover the entire front side of the inner frame 13 formed by attaching the game board 24 having the above-described configuration to the resin base 21. As shown in Fig. 1, the front door frame 14 is formed with a window portion 51 that allows almost the entire area of the game area PA to be viewed from the front. The window portion 51 has a substantially elliptical shape, and a window panel 52 is fitted into the window portion 51. The window panel 52 is formed of colorless and transparent glass, but is not limited to this and may be formed of colorless and transparent synthetic resin, or may be formed of colored and transparent as long as the game area PA is visible through the window panel 52 from the front of the pachinko machine 10.

[0045] A display light-emitting unit 53 is provided above the window 51. A pair of left and right speakers 54 are also provided to output sound effects according to the game status. An upper bulge 55 and a lower bulge 56, which bulge toward the front, are arranged vertically below the window 51. An upper tray 55a that opens upward is provided inside the upper bulge 55, and a lower tray 56a that also opens upward is provided inside the lower bulge 56. The upper tray 55a has the function of temporarily storing game balls dispensed from the dispensing device (described later) and guiding them in a row toward the game ball launching mechanism 27. The lower tray 56a also has the function of storing surplus game balls in the upper tray 55a.

[0046] Next, the configuration of the rear side of the gaming machine main body 12 will be described.

[0047] As shown in FIG. 2, a main control device 60 that controls the main game operations is mounted on the back surface of the inner frame 13 (specifically, the game board 24). FIG. 5 is a front view of the main control device 60.

[0048] As shown in FIG. 5, the main control device 60 includes a main control board 61 housed in a board box 60a. An MPU 62 is mounted on the element mounting surface, which is one of the board surfaces of the main control board 61. The board box 60a is formed transparently so that the MPU 62 housed in the board box 60a can be visually observed from the outside of the board box 60a. Although the board box 60a is formed colorlessly transparent, it may be formed in a colored transparent manner as long as the MPU 62 housed in the board box 60a can be visually observed from the outside of the board box 60a. The main control device 60 is mounted on the back surface of the resin base 21 such that the opposing wall portion 60b of the board box 60a facing the element mounting surface of the main control board 61 faces the rear of the pachinko machine 10. Therefore, by opening the game machine main body 12 forward with respect to the outer frame 11 to expose the back surface of the resin base 21, the opposing wall portion 60b of the board box 60a can be visually observed, and the MPU 62 can be visually observed through the opposing wall portion 60b.

[0049] The board box 60a is formed by combining multiple case bodies 60c one behind the other. These multiple case bodies 60c are provided with connecting portions 60e that prevent the case bodies 60c from being separated and leave traces of the separation. The connecting portions 60e are arranged side by side along one side of the roughly rectangular board box 60a. This allows for the case bodies 60c to be prevented from being separated by destroying some of the connecting portions 60e, and then the case bodies 60c can be separated by reconnecting other connecting portions 60e. Furthermore, because the connecting portions 60e are destroyed when the case bodies 60c are separated, it is possible to visually check the connecting portions 60e to determine whether the case bodies 60c have been separated fraudulently. Furthermore, a sealing sticker 60f is attached to the side of the board box 60a opposite to the side on which the connecting portions 60e are arranged, so as to straddle the boundary between the case bodies 60c. When the sealing sticker 60f is peeled off, an adhesive layer remains on the case body 60c. This makes it possible to leave a trace when the sealing sticker 60f is peeled off when the case bodies 60c are separated.

[0050] In the main control device 60 configured as described above, the main control board 61 is provided with a setting key insertion section 68a into which a setting key owned by the gaming hall manager is inserted and turned ON to trigger an opportunity to change the setting state of the pachinko machine 10 within the range of "Setting 1" to "Setting 6," an update button 68b which is operated to sequentially change the setting state of the pachinko machine 10 after the setting key insertion section 68a is turned ON, a reset button 68c which is operated to clear data in a main RAM 65 (described later) provided in the MPU 62 of the main control device 60, and first to third notification display devices 69a to 69c which notify the results of game history management. In addition, the MPU 62 mounted on the main control board 61 is provided with a read terminal 68d for connecting to a connection terminal of an external device so that the external device can read the game history management results or the information (programs and data) stored in the main ROM 64. The setting state of the pachinko machine 10 is not limited to six stages from "Setting 1" to "Setting 6" and may be any number of stages.

[0051] The setting key insertion portion 68a, the update button 68b, the reset button 68c, the reading terminal 68d (i.e., the MPU 62), and the first to third notification display devices 69a to 69c are all provided on the device mounting surface of the main control board 61. As already explained, the device mounting surface of the main control board 61 faces the opposing wall portion 60b of the board box 60a, but the setting key insertion portion 68a, the update button 68b, the reset button 68c, and the reading terminal 68d are not covered by the opposing wall portion 60b. That is, the opposing wall portion 60b has separate openings in the areas facing the setting key insertion portion 68a, the update button 68b, the reset button 68c, and the reading terminal 68d. This allows the setting key to be inserted into the setting key insertion portion 68a, the update button 68b to be pressed, and the reset button 68c to be pressed, and the reading terminal 68d to be connected to a connection terminal for an external device, without the need to open the board box 60a.

[0052] By inserting a setting key into the setting key insertion portion 68a and rotating it in a predetermined direction, the setting key insertion portion 68a is turned on. In this state, by starting the supply of operating power to the pachinko machine 10 (i.e., by starting the supply of operating power to the MPU 62 of the main control device 60), the pachinko machine 10 enters a changeable state in which the setting state can be changed. In this state, each time the update button 68b is pressed once, the setting state of the pachinko machine 10 changes by one step in ascending order within the range of "Setting 1" to "Setting 6." Note that if the update button 68b is operated when the setting key is in the "Setting 6" state, the setting state is updated to "Setting 1." Furthermore, by rotating the setting key inserted into the setting key insertion portion 68a from the ON position in the direction opposite to the predetermined direction and returning it to its initial position, the setting key insertion portion 68a enters an OFF state. When the setting key insertion portion 68a enters an OFF state, the changeable state ends, and the game becomes playable with the setting values at that time. In other words, after the changeable state has ended, the set value cannot be changed even if the update button 68b is operated.

[0053] The ON operation of the setting key insertion section 68a is valid only when the supply of operating power to the pachinko machine 10 starts (i.e., when the supply of operating power to the MPU 62 of the main control device 60 starts). Therefore, even if the ON operation of the setting key insertion section 68a is performed after the processing at the start of the supply of operating power in the MPU 62 of the main control device 60 has finished, the setting value cannot be changed.

[0054] The setting state of the pachinko machine 10 determines the degree of advantage per unit time in the pachinko machine 10, and the larger the value of "setting n" (n is an integer between "1" and "6") (i.e., the higher the setting value), the higher the degree of advantage. As will be described in detail later, there are two winning / losing lottery modes that determine the probability of winning a jackpot result: a low probability mode in which the probability of winning is relatively low, and a high probability mode in which the probability of winning is relatively high, and the higher the setting value, the higher the probability of winning a jackpot result in the low probability mode. On the other hand, regardless of the setting value, the probability of winning a jackpot result in the high probability mode is constant.

[0055] The reset button 68c is operated to clear the data in the main-side RAM 65 as described above. However, in order to cause the clearing of the data, it is necessary to start supplying operating power to the pachinko machine 10 while the reset button 68c is being pressed (that is, it is necessary to start supplying operating power to the MPU 62 of the main control device 60). The ON operation for the reset button 68c is valid only when starting to supply operating power to the pachinko machine 10 (that is, when starting to supply operating power to the MPU 62 of the main control device 60). Therefore, even if the reset button 68c is pressed after the processing at the start of supplying operating power in the MPU 62 of the main control device 60 is completed, the data in the main-side RAM 65 cannot be cleared.

[0056] As already described, the read terminal 68d is where the connection terminal of an external device is connected to read the management result of the game history or the information (programs and data) stored in the main-side ROM 64 by the external device. However, in order to perform an external output to the external device, it is necessary to start supplying operating power to the pachinko machine 10 while the connection terminal of the external device is connected to the read terminal 68d (that is, it is necessary to start supplying operating power to the MPU 62 of the main control device 60). The connection of the external device to the read terminal 68d is valid only when starting to supply operating power to the pachinko machine 10 (that is, when starting to supply operating power to the MPU 62 of the main control device 60). Therefore, even if an external device is connected to the read terminal 68d after the processing at the start of supplying operating power in the MPU 62 of the main control device 60 is completed, no external output to the external device is performed.

[0057] The first to third notification display devices 69a to 69c are all segment displays in which seven display segments using LEDs are arranged, but are not limited thereto, and may be a single light emitter of a multicolor light emission type, a liquid crystal display device, or an organic EL display. The first to third notification display devices 69a to 69c are all installed such that their display surfaces face the direction in which the element mounting surface of the main control board 61 faces, and are covered by the opposing wall portion 60b of the board box 60a. In this case, since the board box 60a is formed transparently, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c accommodated in the board box 60a from the outside of the board box 60a. Also, as already described, since the main control device 60 is mounted on the back surface of the resin base 21 such that the opposing wall portion 60b facing the element mounting surface of the main control board 61 in the board box 60a faces the rear of the pachinko machine 10, when the game machine main body 12 is opened forward of the pachinko machine 10 with respect to the outer frame 11 and the back surface of the resin base 21 is exposed forward of the pachinko machine 10, it is possible to visually observe the display surfaces of the first to third notification display devices 69a to 69c through the opposing wall portion 60b.

[0058] The display surface of the first notification display device 69a displays not only the numbers "0" through "9" but also various characters, including alphabetic characters. Meanwhile, the second notification display device 69b and the third notification display device 69c display the numbers "0" through "9." The first through third notification display devices 69a through 69c are used to notify the results of game history management; the details of these notifications will be described later. In addition, when the setting state of the pachinko machine 10 is in a changeable state, in which it is possible to change the setting state, a value corresponding to the current setting value is displayed on the third notification display device 69c. The value corresponding to the setting value may be displayed on the first notification display device 69a or the second notification display device 69b. Alternatively, the setting value before the changeable state may be displayed on one of the first through third notification display devices 69a through 69c, and the current setting value may be displayed on another of the first through third notification display devices 69a through 69c.

[0059] As shown in Figure 2, a back pack unit 15 is installed to cover the back side of the inner frame 13, including the main control device 60. The back pack unit 15 includes a back pack 72 formed of a transparent synthetic resin, to which a dispensing mechanism 73 and a control device assembly unit 74 are attached.

[0060] The payout mechanism 73 includes a tank 75 to which gaming balls supplied from the island equipment of the gaming hall are successively replenished, and a payout device 76 for paying out the gaming balls stored in the tank 75. The gaming balls paid out from the payout device 76 are discharged into the upper tray 55a or the lower tray 56a through a payout passage provided downstream of the payout device 76. The payout mechanism 73 is supplied with a main power supply of, for example, 24 volts AC, and is equipped with a back pack board having a power switch for turning the power on and off.

[0061] The control device set unit 74 includes a payout control device 77 having a function of controlling the payout device 76, and a power supply / launch control device 78 that generates and outputs predetermined power required by various control devices and controls the launching of game balls accompanying the operation of the launch operation device 28 by the player. The payout control device 77 and the power supply / launch control device 78 are arranged one on top of the other in the front - rear direction so that the payout control device 77 is at the rear of the pachinko machine 10.

[0062] <Electrical Configuration of Pachinko Machine 10> FIG. 6 is a block diagram showing the electrical configuration of the pachinko machine 10.

[0063] The main control device 60 includes a main control board 61 that controls the main game and a power failure monitoring board 67 that monitors the power supply. The main control board 61 is equipped with an MPU 62. In the MPU 62, in addition to the main - side CPU 63 which is an arithmetic processing device including a control unit and an arithmetic unit, a main - side ROM 64, a main - side RAM 65, and a management IC 66 are built - in. Note that, in addition to the above elements, the MPU 62 also has a built - in interrupt circuit, timer circuit, data input / output circuit, and various counter circuits as random number generators.

[0064] The main - side ROM 64 is a memory (i.e., non - volatile storage means) such as a NOR - type flash memory and a NAND - type flash memory that does not require external power supply for storage retention, and is used as read - only. The main - side ROM 64 stores various control programs and fixed - value data executed by the main - side CPU 63.

[0065] The main - side RAM 65 is a memory (i.e., volatile storage means) such as SRAM and DRAM that requires external power supply for storage retention, and is used for both reading and writing. The main - side RAM 65 allows random access and has a shorter read time than the main - side ROM 64 when compared with the same data capacity. The main - side RAM 65 temporarily stores various data for the execution of the control programs stored in the main - side ROM 64.

[0066] The management IC 66 is a management device that manages the game history based on information supplied from the main CPU 63. As will be described in detail later, the management IC 66 grasps the ball entry history of game balls into the general winning opening 31, the special electric winning device 32, the first actuation opening 33, the second actuation opening 34, and the outlet 24a, and grasps the ball entry frequency into the general winning opening 31, the special electric winning device 32, the first actuation opening 33, and the second actuation opening 34 based on the grasped ball entry history. The management IC 66 also grasps the occurrence frequency of the opening / closing execution mode and the high frequency support mode, which will be described later.

[0067] The MPU 62 is provided with an input port and an output port. The input side of the MPU 62 is connected to a power outage monitoring board 67 and a dispensing control device 77 provided in the main control device 60. The power outage monitoring board 67 is connected to a power supply / launch control device 78 having the function of supplying operating power, and operating power is supplied to the MPU 62 via the power outage monitoring board 67.

[0068] Various sensors, such as the ball entry detection sensors 42a-49a, are connected to the input side of the MPU 62. As already explained, the ball entry detection sensors 42a-49a include the first prize entry detection sensor 42a, the second prize entry detection sensor 43a, the third prize entry detection sensor 44a, the special electric current detection sensor 45a, the first operation port detection sensor 46a, the second operation port detection sensor 47a, the outlet detection sensor 48a, and the gate detection sensor 49a. Based on the detection results of these ball entry detection sensors 42a-49a, the main CPU 63 determines whether a ball has entered each entry area. In addition, the main CPU 63 executes various lotteries based on whether a ball has entered the first operation port 33, and also executes various lotteries based on whether a ball has entered the second operation port 34.

[0069] The input side of the MPU 62 is provided with a setting key insertion section 68a, an update button 68b, and a reset button 68c, which are provided on the main control board 61. The setting key insertion section 68a is provided with a sensor (not shown), which detects whether the setting key insertion section 68a is positioned at the ON operation position or the OFF operation position. The main CPU 63 then determines whether the setting key insertion section 68a is positioned at the ON operation position or the OFF operation position based on the detection result from the sensor. The update button 68b is provided with a sensor (not shown), which detects whether the update button 68b has been pressed. The main CPU 63 then determines whether the update button 68b has been pressed based on the detection result from the sensor. The reset button 68c is provided with a sensor (not shown), which detects whether the reset button 68c has been pressed. The main CPU 63 then determines whether the reset button 68c has been pressed based on the detection result from the sensor.

[0070] The output side of the MPU 62 is connected to a power outage monitoring board 67, a payout control device 77, and an audio / light emitting control device 81. A prize ball command is output to the payout control device 77, for example, when a gaming ball enters a prize ball entry section among the entry sections, where the occurrence of the ball entry corresponds to the payout of the gaming ball. Various commands such as a variation command, a type command, and an opening command are output to the audio / light emitting control device 81.

[0071] On the output side of the MPU62, a special-electricity drive unit 32b for opening and closing the opening / closing door 32a of the special-electricity winning device 32, a general-electricity drive unit 34b for opening and closing the general-electricity component 34a of the second operation port 34, a special-diagram unit 37, and a general-diagram unit 38 are connected. Incidentally, the special-diagram unit 37 is provided with a special-diagram display unit 37a and a special-diagram hold display unit 37b, and all of these are connected to the output side of the MPU62. Similarly, the general-diagram unit 38 is provided with a general-diagram display unit 38a and a general-diagram hold display unit 38b, and all of these are connected to the output side of the MPU62. Various driver circuits are provided on the main control board 61, and through the driver circuits, the MPU62 executes drive control of various drive units and various display units.

[0072] That is, in the opening / closing execution mode, drive control of the special-electricity drive unit 32b is executed in the main CPU 63 so that the special-electricity winning device 32 is opened and closed. Also, when the general-electricity component 34a is selected as the open state winner, drive control of the general-electricity drive unit 34b is executed in the main CPU 63 so that the general-electricity component 34a is opened and closed. Also, in each game round, display control of the special-diagram display unit 37a is executed in the main CPU 63. Also, when indicating the lottery result of whether to set the general-electricity component 34a to the open state, display control of the general-diagram display unit 38a is executed in the main CPU 63. Also, when a winning occurs at the first operation port 33 or the second operation port 34, or when variable display starts in the special-diagram display unit 37a, display control of the special-diagram hold display unit 37b is executed in the main CPU 63, and when a winning occurs at the through gate 35, or when variable display starts in the general-diagram display unit 38a, display control of the general-diagram hold display unit 38b is executed in the main CPU 63.

[0073] On the output side of the MPU62, first to third notification display devices 69a to 69c are connected. Further, the management result of the game history in the management IC66 is notified through the displays in the first to third notification display devices 69a to 69c. Also, when changing the setting state of the pachinko machine 10, the current setting value is displayed on the third notification display device 69c. In this case, the first notification display device 69a and the second notification display device 69b are controlled for display by the management IC66 and not by the main CPU63, while the third notification display device 69c is controlled for display by the main CPU63 and also by the management IC66. The display control by the main CPU63 takes precedence over the display control by the management IC66 for the third notification display device 69c.

[0074] However, it is not limited to this, and the third notification display device 69c may also be configured to be controlled for display by the management IC66 and not by the main CPU63. In this case, when displaying the current setting value on the third notification display device 69c when changing the setting state of the pachinko machine 10, it is advisable to adopt a configuration in which an instruction to display the setting value is sent from the main CPU63 to the management IC66.

[0075] The MPU62 is provided with a reading terminal 68d. A sensor (not shown) is provided at the reading terminal 68d, and whether a connection terminal of an external device is connected to the reading terminal 68d is detected by the sensor. Then, the main CPU63 identifies whether a connection terminal of an external device is connected to the reading terminal 68d based on the detection result from the sensor. Also, when an external device is connected to the reading terminal 68d, the management result of the game history in the management IC66 or the information (programs and data) stored in the main ROM64 is externally output to the external device.

[0076] The power failure monitoring board 67 relays between the main control board 61 and the power supply / launch control device 78, and monitors the voltage of 24 VDC stabilized power, which is the maximum voltage output from the power supply / launch control device 78. The payout control device 77 performs payout control of prize balls and loan balls by the payout device 76 based on the prize ball command received from the main control device 60.

[0077] The power supply / launch control device 78 is connected to a commercial power supply (external power supply) in, for example, a game hall. Then, based on the external power supplied from the commercial power supply, it generates the necessary operating power for the main control board 61, the payout control device 77, etc., respectively, and supplies the generated operating power. Incidentally, the power supply / launch control device 78 is provided with a power supply unit for power failure such as a backup capacitor. Even when the power of the pachinko machine 10 is in the OFF state, power for storage retention is supplied from the power supply unit for power failure to the main side RAM 65 of the main control device 60 and the payout control device 77. In addition, the power supply / launch control device 78 is responsible for the launch control of the game ball launch mechanism 27, and the game ball launch mechanism 27 is driven when predetermined launch conditions are met. Further, as already described, the payout mechanism unit 73 is provided with a power switch. When the power switch is turned on, the supply of operating power to the pachinko machine 10 is started, and when the power switch is turned off, the supply of operating power to the pachinko machine 10 is stopped.

[0078] The sound and light control device 81 drives and controls the display light emitting unit 53 and the speaker unit 54 provided on the front door frame 14 based on various commands received from the main control device 60, and controls the display control device 82. The display control device 82 executes the display control of the symbol display device 41 based on the command received from the sound and light control device 81.

[0079] <Electrical configuration for performing various lotteries by the main side CPU 63> Next, the electrical configuration for performing various lotteries by the main side CPU 63 will be described with reference to FIG. 7.

[0080] During the game, the main CPU 63 uses various counter information to perform jackpot generation lottery, setting the display of the special figure display unit 37a, setting the symbol display of the symbol display device 41, setting the display of the normal figure display unit 38a, etc. Specifically, as shown in FIG. 7, a jackpot random number counter C1 used for the lottery of jackpot occurrence, a jackpot type counter C2 used for determining the jackpot type, a reach random number counter C3 used for the reach generation lottery when the symbol display device 41 varies out, a random number initial value counter CINI used for setting the initial value of the jackpot random number counter C1, and a variation type counter CS for determining the display duration in the special figure display unit 37a and the symbol display device 41 are used. Further, a general electric accessory release counter C4 used for the lottery of whether to set the general electric accessory 34a of the second operation port 34 to the general electric open state is used. Each of the above counters C1 to C3, CINI, CS, and C4 is provided in various counter areas 65b of the main RAM 65.

[0081] Each of the counters C1 to C3, CINI, CS, and C4 is a loop counter that adds 1 to the previous value each time it is updated and returns to "0" after reaching the maximum value. Each counter is updated at short time intervals. Information corresponding to the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored in a hold storage area 65a provided as acquisition information storage means in the main RAM 65 when a winning occurs at the first operation port 33 or the second operation port 34.

[0082] The hold storage area 65a includes a hold area RE and an execution area AE. The hold area RE includes a first hold area RE1, a second hold area RE2, a third hold area RE3, and a fourth hold area RE4. In accordance with the winning history at the first operation port 33 or the second operation port 34, a combination of the numerical information of the jackpot random number counter C1, the jackpot type counter C2, and the reach random number counter C3 is stored as hold information in any of the hold areas RE1 to RE4.

[0083] In this case, when a winning entry into the first operation port 33 or the second operation port 34 occurs continuously multiple times, the numerical information is stored in chronological order in the first hold area RE1 → the second hold area RE2 → the third hold area RE3 → the fourth hold area RE4. By providing these four hold areas RE1 to RE4 in this way, the winning history of the game balls entering the first operation port 33 or the second operation port 34 can be stored in hold memory up to a maximum of four.

[0084] Note that the number that can be stored in hold memory is not limited to four and can be arbitrary, and can be other plural numbers such as two, three, or five or more, or can also be a single number.

[0085] The execution area AE is an area for moving the numerical information stored in the first hold area RE1 of the hold area RE when starting the variable display of the special figure display unit 37a. At the start of one game round, a win / loss determination or the like is performed based on the various numerical information stored in the execution area AE.

[0086] The above-mentioned counters will be described in detail.

[0087] First, the general electric accessory release counter C4 will be described. The general electric accessory release counter C4 is configured to be incremented by one in order within a range of, for example, 0 to 250, and to return to "0" after reaching the maximum value. The general electric accessory release counter C4 is updated periodically and is stored in the general electric hold area 65c of the main side RAM 65 at the timing when a game ball wins in the through gate 35. Then, at a predetermined timing, a lottery is performed to determine whether to control the general electric accessory 34a to the open state based on the value of the stored general electric accessory release counter C4.

[0088] In the present pachinko machine 10, a plurality of types of support modes are set so that the manner of support by the normal power device 34a differs from one another. In detail, the support modes are set to a high frequency support mode and a low frequency support mode so that the frequency with which the normal power device 34a of the second operating port 34 is opened per unit time is relatively high or low when compared in a situation where game balls are continuously launched in the same manner into the game area PA.

[0089] In the high-frequency support mode and the low-frequency support mode, the probability of winning the normal power opening state in the normal power opening lottery using the normal power device opening counter C4 is the same (for example, 4 / 5 in both), but in the high-frequency support mode, the number of times the normal power device 34a opens when the normal power opening state is won is set to be more than in the low-frequency support mode, and the opening time for each opening is set to be longer.In this case, if the normal power opening state is won in the high-frequency support mode and the normal power device 34a opens multiple times, the closing time from the end of one opening state to the start of the next opening state is set to be shorter than the opening time for each opening.Furthermore, in the high-frequency support mode, the minimum time ensured between one normal power opening lottery and the next normal power opening lottery (i.e., the duration of one display on the normal power display unit 38a) is set to be shorter than in the low-frequency support mode.

[0090] As described above, in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in the low-frequency support mode. In other words, in the low-frequency support mode, the probability of a winning entry into first actuation port 33 is higher than in second actuation port 34, but in the high-frequency support mode, the probability of a winning entry into second actuation port 34 is higher than in first actuation port 33. When a winning entry into second actuation port 34 occurs, a predetermined number of game balls are paid out, so in the high-frequency support mode, the player can play without losing too many balls.

[0091] Note that the configuration for making the frequency of the general power release state per unit time higher in the high-frequency support mode than in the low-frequency support mode is not limited to the above, and for example, it may be a configuration for increasing the probability of winning the general power release state in the general power release lottery. Further, in a configuration in which a plurality of types of guaranteed times (for example, the time of the variable display executed by the general drawing display unit 38a based on winning in the through gate 35) are prepared for the next general power release lottery to be held after one general power release lottery is held, in the high-frequency support mode, a shorter guaranteed time may be more likely to be selected or the average guaranteed time may be set to be shorter than in the low-frequency support mode. Furthermore, by applying any one condition or an arbitrary combination of conditions among increasing the number of release times, increasing the release time, shortening the guaranteed time ensured for the next general power release lottery to be held after one general power release lottery is held, shortening the average time of such guaranteed times, and increasing the winning probability, the advantage of the high-frequency support mode over the low-frequency support mode may be enhanced.

[0092] Here, as already described, the pachinko machine 10 has setting states of "Setting 1" to "Setting 6", but the release frequency and release mode of the general power accessory 34a in the low-frequency support mode are the same regardless of the set value, and the release frequency and release mode of the general power accessory 34a in the high-frequency support mode are also the same regardless of the set value. However, it is not limited to this, and a configuration may be adopted in which at least one of the release frequency and release mode of the general power accessory 34a varies according to the setting state of the pachinko machine 10 for at least one of the low-frequency support mode and the high-frequency support mode. For example, a configuration may be adopted in which the higher the set value, the higher the release frequency of the general power accessory 34a in the low-frequency support mode, or a configuration may be adopted in which the probability of a game ball entering the second operating port 34 when the general power accessory 34a is in the one-time release state in the low-frequency support mode is increased. Also, a configuration may be adopted in which the higher the set value, the higher the release frequency of the general power accessory 34a in the high-frequency support mode, or a configuration may be adopted in which the probability of a game ball entering the second operating port 34 when the general power accessory 34a is in the one-time release state in the high-frequency support mode is increased.

[0093] Next, the winning random number counter C1 will be described. The winning random number counter C1 is configured to be incremented by 1 in sequence within a range of, for example, 0 to 599, and to return to "0" after reaching the maximum value. In particular, when the winning random number counter C1 makes one full cycle, the value of the random number initial value counter CINI at that time is read as the initial value of the winning random number counter C1. Note that the random number initial value counter CINI is a loop counter similar to the winning random number counter C1 (value = 0 to 599). The winning random number counter C1 is updated periodically and is stored in the reserved storage area 65a of the main side RAM 65 at the timing when the game ball wins the first operation port 33 or the second operation port 34.

[0094] The values of the random numbers for a big win are stored as a win / loss table in the main side ROM 64. FIG. 8 is an explanatory diagram for explaining various tables stored in the main side ROM 64. As the win / loss table, low probability win / loss tables 64a to 64f for the low probability mode and a high probability win / loss table 64g for the high probability mode are stored.

[0095] The low probability win / loss tables 64a to 64f are provided in a one-to-one correspondence with the setting states of "Setting 1" to "Setting 6". That is, the low probability win / loss table 64a for setting 1 to be referred to when the setting state of the pachinko machine 10 is "Setting 1", the low probability win / loss table 64b for setting 2 to be referred to when the setting state of the pachinko machine 10 is "Setting 2", the low probability win / loss table 64c for setting 3 to be referred to when the setting state of the pachinko machine 10 is "Setting 3", the low probability win / loss table 64d for setting 4 to be referred to when the setting state of the pachinko machine 10 is "Setting 4", the low probability win / loss table 64e for setting 5 to be referred to when the setting state of the pachinko machine 10 is "Setting 5", and the low probability win / loss table 64f for setting 6 to be referred to when the setting state of the pachinko machine 10 is "Setting 6" exist.

[0096] These low probability winning / losing tables 64a to 64f are set such that the higher the setting value, the higher the winning probability of a big win result. Specifically, when the low probability winning / losing table 64a for setting 1 is referred to, the big win result occurs at about 1 / 320, when the low probability winning / losing table 64b for setting 2 is referred to, the big win result occurs at about 1 / 310, when the low probability winning / losing table 64c for setting 3 is referred to, the big win result occurs at about 1 / 300, when the low probability winning / losing table 64d for setting 4 is referred to, the big win result occurs at about 1 / 290, when the low probability winning / losing table 64e for setting 5 is referred to, the big win result occurs at about 1 / 280, and when the low probability winning / losing table 64f for setting 6 is referred to, the big win result occurs at about 1 / 270. As a result, the higher the setting state of the pachinko machine 10, the easier it is for a big win result to occur in the low probability mode, which is advantageous for the player.

[0097] On the other hand, only one type of high probability winning / losing table 64g is provided so as to be common in any setting state from "setting 1" to "setting 6". The high probability winning / losing table 64g is set such that the winning probability of a big win result is higher than that of the low probability winning / losing tables 64a to 64f in any setting state from "setting 1" to "setting 6". Specifically, when the high probability winning / losing table 64g is referred to, the big win result occurs at about 1 / 30. As a result, it becomes possible to make the high probability mode more advantageous than the low probability mode regardless of the setting state of the pachinko machine 10. Also, even in the lowest setting state of "setting 1", by setting it to the high probability mode, it becomes possible to increase the probability of getting a big win result compared to the low probability mode of the highest setting state of "setting 6". Also, regarding the high probability mode, it becomes possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10, and it becomes possible to suppress the storage capacity for preliminarily storing the high probability winning / losing table 64g in the main side ROM 64.

[0098] The jackpot type counter C2 is configured to be incremented by 1 in sequence within the range of 0 to 29 and return to "0" after reaching the maximum value. The jackpot type counter C2 is updated periodically and stored in the hold storage area 65a at the timing when a game ball wins a prize at the first activation port 33 or the second activation port 34.

[0099] In this pachinko machine 10, a plurality of jackpot results are set. These plurality of jackpot results are set with differences in three conditions: (1) the opening and closing control mode of the special electric prize device 32 in the opening and closing execution mode, (2) the lottery mode in the winning or losing lottery means after the end of the opening and closing execution mode, and (3) the support mode in the general electric accessory 34a of the second activation port 34 after the end of the opening and closing execution mode.

[0100] As the opening and closing control mode of the special electric prize device 32 in the opening and closing execution mode, a high-frequency winning mode and a low-frequency winning mode are set so that the frequency of prize winning at the special electric prize device 32 becomes relatively high or low from the start to the end of the opening and closing execution mode. Specifically, in either the high-frequency winning mode or the low-frequency winning mode, the round game is executed with a predetermined number of rounds as the upper limit.

[0101] The round game is a game that continues until either a predetermined upper limit duration elapses or a predetermined upper limit number of game balls win a prize at the special electric prize device 32. Also, the number of rounds of the round game in the opening and closing execution mode triggered by the jackpot result is the same fixed number of rounds regardless of the type of jackpot result that triggered the transition. Specifically, the upper limit number of rounds of the round game is set to 15 rounds regardless of which jackpot result occurs.

[0102] Furthermore, in this pachinko machine 10, a plurality of types are set for one opening mode of the special electric winning device 32, with different opening durations from when the special electric winning device 32 is opened until when it is closed. In detail, a long-time mode in which the opening duration is set to 29 seconds, which is a long time, and a short-time mode in which the opening duration is set to 0.06 seconds, which is a short time shorter than the long time, are set.

[0103] In this pachinko machine 10, when the launch operation device 28 is operated by a player, the game ball launching mechanism 27 is driven and controlled so that one game ball is launched toward the play area PA every 0.6 seconds. The upper limit for the number of balls required to complete a round game is set to nine. In this case, the long-time mode among the above-mentioned release modes sets the release duration to a time longer than the product of the game ball launch cycle and one round game. On the other hand, the short-time mode sets the release duration to a time shorter than the product of the game ball launch cycle and one round game, more specifically, shorter than the game ball launch cycle. Therefore, when a single release is performed in the long-time mode, it is expected that the special electric winning device 32 will win the maximum number of prizes in one round game. When a single release is performed in the short-time mode, it is expected that the special electric winning device 32 will not win, or that only one prize will be won, even if one is won.

[0104] In the high frequency winning mode, the special power winning device 32 is opened once in each round of play in a long time mode. On the other hand, in the low frequency winning mode, the special power winning device 32 is opened once in each round of play in a short time mode.

[0105] In addition, the number of times the special electric winning device 32 is opened and closed, the number of rounds of play, the duration of opening for one opening, and the upper limit number of rounds of play in one round in the high frequency winning mode and low frequency winning mode are not limited to the above values and are arbitrary, as long as the frequency of winning in the special electric winning device 32 from the start to the end of the opening and closing execution mode is higher in the high frequency winning mode than in the low frequency winning mode.

[0106] The allocation destination of the jackpot result for the jackpot type counter C2 is stored as an allocation table 64h in the main ROM 64 as shown in Fig. 8. In the allocation table 64h, a low probability jackpot result, a low winning high probability jackpot result, and a most advantageous jackpot result are set as the allocation destination of the jackpot result in the event of a jackpot result.

[0107] A low probability jackpot result is a jackpot result in which the opening / closing execution mode becomes a high frequency winning mode, and after the opening / closing execution mode ends, the winning / losing lottery mode becomes a low probability mode and the support mode becomes a high frequency support mode. However, this high frequency support mode will transition to a low frequency support mode if the number of games played after the transition reaches the termination reference number (specifically, 100 times).

[0108] A low-prize, high-probability jackpot result is a jackpot result in which the open / close execution mode becomes a low-frequency win mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0109] The most favorable jackpot result is a jackpot result in which the open / close execution mode becomes a high-frequency winning mode, and after the open / close execution mode ends, the win / lose lottery mode becomes a high-probability mode and the support mode becomes a high-frequency support mode. These high-probability mode and high-frequency support mode continue until the lottery result in the win / lose lottery is a jackpot state win and the game transitions to the jackpot state.

[0110] In addition, in relation to each of the above game states, the normal game state refers to a state where the opening / closing execution mode is not in effect, the winning / losing lottery mode is the low-probability mode, and the support mode is the low-frequency support mode. Also, as a game result configuration, it may be set such that there is no low-win high-probability jackpot result. Further, in the opening / closing execution mode for the low-win high-probability jackpot result, the number of rounds of the round game may be configured to be less than that in the case of the low-probability jackpot result and the most advantageous jackpot result.

[0111] In the distribution table 64h, among the values of the jackpot type counter C2 from "0 to 29", "0 to 9" correspond to the low-probability jackpot result, "10 to 14" correspond to the low-win high-probability jackpot result, and "15 to 29" correspond to the most advantageous jackpot result.

[0112] There is only one type of distribution table 64h provided in common regardless of the setting state of "Setting 1" to "Setting 6". This makes it possible to prevent the setting state of the pachinko machine 10 from causing an advantage or disadvantage in the distribution mode of the jackpot result, and also makes it possible to suppress the storage capacity for pre-storing the distribution table 64h in the main-side ROM64.

[0113] Note that the distribution mode of the jackpot result may also be configured to differ according to the setting state of the pachinko machine 10. For example, it may be configured such that the higher the setting value, the higher the probability of being distributed to the most advantageous jackpot result. Or it may be configured such that the higher the setting value, the higher the probability of being distributed to the most advantageous jackpot result or the low-win high-probability jackpot result. In this case, it becomes possible to increase the probability of entering the high-probability mode after achieving the jackpot result as the setting value increases. Also, it may be configured such that the higher the setting value, the lower the probability of being distributed to the low-win high-probability jackpot result. Or it may be configured such that at a high setting value, it cannot be distributed to the low-win high-probability jackpot result, while at a low setting value, it can be distributed to the low-win high-probability jackpot result. In this case, it becomes possible to increase the probability of the opening / closing execution mode of the high-frequency winning mode occurring as the setting value increases.

[0114] Next, the reach random number counter C3 will be described. The reach random number counter C3 is configured to increment by one within a range of, for example, 0 to 238, and return to "0" after reaching a maximum value. In the present pachinko machine 10, an expectation effect is set as one type of display effect in the symbol display device 41. In a gaming machine equipped with a symbol display device 41 capable of displaying varying symbols, in which the final stop result in a game round resulting in a predetermined jackpot result is a prize-related result, the expectation effect refers to a display state that makes the player believe that the variable display state is likely to result in the prize-related result from the start of the variable display of symbols on the symbol display device 41 until the stop result is derived and displayed. Specifically, the prize-related result is the display of a combination of symbols with the same number on one of the pay lines.

[0115] There are two types of expectation effects: a reach display and a notice display that is set to anticipate the occurrence of a reach display or a corresponding result before the reach display occurs.

[0116] The reach display includes a display state in which a reach symbol combination is displayed by stopping the display of symbols in some of the multiple symbol rows displayed on the display surface 41a of the symbol display device 41, and in that state, a variable display of symbols is performed in the remaining symbol rows. Also included are a reach effect in which, in a state in which a reach symbol combination is displayed as described above, a variable display of symbols is performed in the remaining symbol rows, and a reach effect is performed by displaying predetermined characters or the like as a moving image on the background screen, and a reach effect in which a reach symbol combination is displayed in a reduced size or is not displayed, and then a predetermined character or the like is displayed as a moving image on almost the entire display surface 41a.

[0117] The preliminary display includes a mode of displaying a character separately from the symbols on the symbol display column in a situation where the variable display of symbols has started on the display surface 41a of the symbol display device 41, in a situation where the symbols are being variably displayed in all the symbol columns, or in a situation where the symbols are being variably displayed in some of the symbol columns, i.e., in a plurality of symbol columns. Also included are those that change the background screen to a predetermined mode different from the previous mode, and those that change the symbols on the symbol display column to a predetermined mode different from the previous mode. Such a preliminary display can occur in any game round, whether or not a reach display is performed, but it is set to occur with a higher probability when a reach display is performed than when a reach display is not performed.

[0118] The reach display is executed regardless of the value of the reach random number counter C3 in a game round where the same combination of symbols is finally stopped and displayed. Also, in a game round corresponding to a jackpot result where the same combination of symbols is not stopped and displayed, it is not executed regardless of the value of the reach random number counter C3. Further, in a game round corresponding to a non-winning result, it is executed when the reach random number counter C3 obtained at a predetermined timing by referring to the reach table stored in the main-side ROM 64 corresponds to the occurrence of the reach display.

[0119] On the other hand, the decision of whether to perform the preliminary display is not made by the main control device 60 but by the audio-visual control device 81. In this case, the audio-visual control device 81 executes a lottery process for the preliminary display so as to satisfy at least one of the conditions that a preliminary display is more likely to occur in a game round corresponding to any jackpot result than in a game round corresponding to a non-winning result, and that a preliminary display with a low appearance rate is more likely to occur. Incidentally, the lottery result is reflected when the game effect is executed by the symbol display device 41.

[0120] Here, the probability of the occurrence of the reach display in a game turn resulting in a losing outcome is the same regardless of the setting state of any of "Setting 1" to "Setting 6". This makes it possible to prevent any advantage or disadvantage due to the setting state of the pachinko machine 10 regarding the probability of the occurrence of the reach display in a game turn resulting in a losing outcome. However, it is not limited to this, and it may be configured such that the higher the setting value, the higher the probability of the occurrence of the reach display in a game turn resulting in a losing outcome.

[0121] Next, the variable type counter CS will be described. The variable type counter CS is configured to be incremented by 1 in order within a range of, for example, 0 to 198, and to return to "0" after reaching the maximum value. The variable type counter CS is used in the main CPU 63 to determine the display duration in the special figure display unit 37a and the display duration of the symbols in the symbol display device 41. The variable type counter CS is updated once each time the timer interrupt process described later is executed once, and is repeatedly updated even within the remaining time until the next timer interrupt process is executed. Then, the buffer value of the variable type counter CS is acquired when determining the variable pattern at the start of the variable display in the special figure display unit 37a and at the start of the symbol variation by the symbol display device 41.

[0122] <Regarding the processing configuration of the main CPU 63> Next, each process executed by the main CPU 63 to advance the game will be described. The processes of such main CPU 63 are roughly classified into a main process started with the power-on and a timer interrupt process started periodically (in this embodiment, at a cycle of 4 milliseconds).

[0123] <Main process> First, the main process will be described with reference to the flowchart of FIG. 9.

[0124] First, execute the power-on wait process (step S101). In this power-on wait process, for example, the main process is started, and then the process waits without proceeding to the next process until a predetermined time for waiting (specifically, 1 second) has elapsed. During the execution period of such a power-on wait process, the operation start and initial setting of the symbol display device 41 will be completed. After that, access to the main-side RAM 65 is permitted (step S102).

[0125] After that, it is determined whether the setting key insertion part 68a has been turned on (step S103). When the setting key insertion part 68a has not been turned on (step S103: NO), it is determined whether the reset button 68c has been pressed (step S104). When the reset button 68c has been pressed (step S104: YES), except for the area in the main-side RAM 65 where the information of the setting value indicating the setting state of the pachinko machine 10 is set, each area of the main-side RAM 65 is cleared to "0" and initial setting is performed on the "0"-cleared area (step S105). That is, when the supply of operating power to the pachinko machine 10 is started while pressing the reset button 68c without the ON operation of the setting key insertion part 68a, the clear process of the main-side RAM 65 is executed while maintaining the information of the setting value in the state before the supply of operating power to the pachinko machine 10 is stopped, and initial setting is performed on the storage area where the clear process has been executed. As a result, it is possible to initialize other areas of the main-side RAM 65 without requiring a change in the setting value. In step S105, various registers of the main-side CPU 63 are also cleared to "0" and then initial setting is performed.

[0126] If the reset button 68c is not pressed (step S104: NO), it is determined whether the power outage flag is set to "1" (step S106). The power outage flag is provided in the main RAM 65, and if the supply of operating power to the main CPU 63 is stopped and a predetermined power outage process is executed normally, the power outage flag is set to "1". If the power outage flag is set to "1", it is determined whether the checksum calculation result matches the checksum saved at the time of power outage, that is, the validity of the stored data (step S107). If the process of step S105 is executed or if a positive determination is made in step S107, it is determined whether the setting value of the pachinko machine 10 is normal by checking the main RAM 65 (step S108). Specifically, if the setting value is any of "Setting 1" to "Setting 6", it is determined to be normal, and if it is "0" or 7 or greater, it is determined to be abnormal.

[0127] If a negative determination is made in any of steps S106 to S108, an operation prohibition process is executed. In the operation prohibition process, an error notification process is executed to notify the hall manager or the like of the occurrence of an error (step S109), and then an infinite loop is executed. The operation prohibition process is released by executing an all-clear process (step S117) described later.

[0128] If the determinations in all of steps S106 to S108 are affirmative, a power-on setting process is executed (step S110). In the power-on setting process, predetermined areas of the main RAM 65 are set to initial values, such as initializing the power outage flag, and a command corresponding to the current game state is sent to the sound and light emission control device 81. After executing the process of step S110, a recognition process (step S111) is executed to cause the management IC 66 to recognize various information, and a data output process is executed to output various data to an external device connected to the read terminal 68d of the MPU 62 (step S112). The details of the recognition process and the data output process will be described later.

[0129] The main CPU 63 is configured to periodically execute timer interrupt processing, but the occurrence of timer interrupt processing is prohibited when the main processing is started. This state in which the occurrence of timer interrupt processing is prohibited is released when the processing of step S112 is completed and before the processing of step S113 is executed, and execution of the timer interrupt processing is permitted. As a result, when the supply of operating power to the main CPU 63 starts, the data output processing of step S112 ends and the timer interrupt processing is not executed until before the processing of step S113 is started. Therefore, processing for progressing the game in the main CPU 63 is not started until this situation is reached.

[0130] Thereafter, the process proceeds to the remaining process of steps S113 to S116. In other words, the main CPU 63 is configured to periodically execute timer interrupt processing, but there is a remaining time between one timer interrupt processing and the next timer interrupt processing. This remaining time varies depending on the processing completion time of each timer interrupt processing, but this irregular time is used to repeatedly execute the remaining process of steps S113 to S116. In this respect, the remaining process of steps S113 to S116 can be said to be non-periodic processing that is executed non-periodically.

[0131] In the residual process, first, in step S113, an interrupt disable setting is performed to prohibit the occurrence of timer interrupt processing. In the subsequent step S114, a random number initial value update process for updating the random number initial value counter CINI is executed, and in step S115, a variable counter update process for updating the variation type counter CS is executed. In these update processes, the current numerical information is read from the corresponding counter in the main RAM 65, and after executing the process of adding 1 to the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value exceeds the maximum value, it is cleared to "0" respectively. Then, in step S116, an interrupt enable setting is performed to switch from the state where the occurrence of timer interrupt processing is prohibited to the enabled state. When the process of step S116 is executed, it returns to step S113, and the processes of steps S113 to S116 are repeated.

[0132] On the other hand, when the setting key insertion part 68a is in the ON operation state (step S103: YES), all areas of the main RAM 65, including the area where the information of the set value indicating the set state of the pachinko machine 10 is set in the main RAM 65, are cleared to "0", and initial settings are performed on the cleared areas (step S117). That is, when an operation for changing the set state of the pachinko machine 10 is performed, all areas of the main RAM 65 are cleared to "0" and initial settings are performed on the storage areas where the clear process has been executed even if the reset button 68c is not pressed. Also, in step S117, various registers of the main CPU 63 are cleared to "0" and then initial settings are performed. Note that it is not limited to this, and even when an operation for changing the set state of the pachinko machine 10 is performed, if the reset button 68c is not pressed, the all-clear process of the main RAM 65 is not executed, and it may be configured such that the all-clear process is executed when an operation for changing the set state of the pachinko machine 10 is performed and the reset button 68c is pressed.

[0133] Thereafter, in step S118, a set value update process is executed, and in step S119, a set value update signal output process is executed, and then the process proceeds to step S110. The set value update process will be described below. The set value update signal output process will be described in detail later. Figure 10 is a flowchart showing the set value update process.

[0134] First, a setting value counter provided in the main RAM 65 is set to "1" (step S201). The setting value counter is a counter that allows the main CPU 63 to identify which setting value the setting state of the pachinko machine 10 is. By setting the setting value counter to "1", when the setting value update process is executed, the setting value becomes "Setting 1" regardless of the setting value up to that point.

[0135] Thereafter, a process for starting display of the set value is executed (step S202). In the process for starting display of the set value, the third notification display device 69c is controlled to display the number "1" corresponding to "Setting 1". When changing the set value, the manager of the gaming hall can grasp the current setting status of the pachinko machine 10 by checking the third notification display device 69c.

[0136] Thereafter, on the condition that the setting key insertion section 68a has not been turned OFF (step S203: NO), it is determined whether the update button 68b has been pressed once (step S204). Specifically, it is determined whether the signal from the sensor that detects the pressing of the update button 68b has switched from LOW level to HI level. If the determination in step S204 is negative, the process returns to step S203, and it is determined whether the setting key insertion section 68a has been turned OFF.

[0137] If the update button 68b has been pressed once (step S204: YES), the value of the setting value counter in the main RAM 65 is incremented by 1 (step S205). If the value of the setting value counter after incrementing by 1 exceeds "6" (step S206: YES), the setting value counter is set to "1" (step S207). As a result, the setting value is updated to the next higher setting each time the update button 68b is pressed once, and if the update button 68b is pressed once when the setting is "6," the setting will return to "1."

[0138] If a negative determination is made in step S206, or if the processing of step S207 is executed, a display update process of the setting value is executed (step S208). In the display update process of the setting value, the display of the third notification display device 69c is controlled so that a number corresponding to the value of the setting value counter of the main RAM 65 is displayed. By checking the third notification display device 69c, the manager of the gaming hall can grasp the setting state of the pachinko machine 10 after pressing the update button 68b.

[0139] After executing the process of step S208, the process returns to step S203, and it is determined whether the setting key insertion unit 68a has been turned OFF. If the setting key insertion unit 68a has not been turned OFF (step S203: NO), the process from step S204 onwards is executed again. If the setting key insertion unit 68a has been turned OFF (step S203: YES), a process of ending the display of the setting value is executed (step S209). In the process of ending the display of the setting value, the display of the setting value on the third notification display device 69c is ended.

[0140] <Timer interrupt processing> Next, the timer interrupt process will be described with reference to the flowchart in Fig. 11. The timer interrupt process is executed periodically (for example, every 4 milliseconds).

[0141] First, execute the power failure information storage process (step S301). In the power failure information storage process, it is monitored whether a power failure signal corresponding to the occurrence of power interruption is received from the power failure monitoring board 67. When the occurrence of a power failure is identified, after executing the power failure processing, an infinite loop is entered. In the power failure processing, a "1" is set in the power failure flag of the main-side RAM 65, and a checksum is calculated and the calculated checksum is saved.

[0142] Thereafter, execute the lottery random number update process (step S302). In the lottery random number update process, updates are executed for the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power accessory release counter C4. Specifically, the current numerical information is sequentially read from the winning random number counter C1, the jackpot type counter C2, the reach random number counter C3, and the normal power accessory release counter C4, and after executing the process of adding 1 to each of the read numerical information, the process of overwriting the original counter is executed. In this case, when the counter value exceeds the maximum value, it is cleared to "0" respectively. Thereafter, in step S303, the random number initial value update process is executed in the same manner as in step S114, and in step S304, the variable counter update process is executed in the same manner as in step S115.

[0143] Thereafter, execute the fraud detection process of monitoring whether a predetermined event set as a monitoring target for fraud has occurred (step S305). In this fraud detection process, the occurrence of a plurality of types of events is monitored, and by confirming that a predetermined event has occurred, a "1" is set in the game stop flag provided in the main-side RAM 65. In the subsequent step S306, by determining whether a "1" is set in the game stop flag, it is determined whether the game is in a stopped state. If a negative determination is made in step S306, the processes after step S307 are executed.

[0144] In step S307, port output processing is executed. In the port output processing, if output information has been set in the previous timer interrupt processing, processing is executed to output corresponding to that output information to the various drive units 32b, 34b. For example, if information to switch the special power winning device 32 to an open state is set, output of a drive signal to the special power drive unit 32b is started, and if information to switch to a closed state is set, output of the drive signal is stopped. Also, if information to switch the normal power device 34a of the second operating port 34 to an open state is set, output of a drive signal to the normal power drive unit 34b is started, and if information to switch to a closed state is set, output of the drive signal is stopped.

[0145] Then, a read process is executed (step S308). In the read process, signals other than the power outage signal and the winning signal are read, and the read information is stored for use in subsequent processes.

[0146] Thereafter, a ball entry detection process is executed (step S309). In the ball entry detection process, signals received from each ball entry detection sensor 42a-49a are read, and based on the read results, it is determined whether or not a ball has entered the out gate 24a, the general winning gate 31, the special electric winning device 32, the first operating gate 33, the second operating gate 34, and the through gate 35. Details of the ball entry detection process will be explained later.

[0147] Thereafter, a timer update process is executed (step S310) for collectively updating the numerical information of the multiple types of timer counters provided in the main RAM 65. In this case, the timer counters in which the stored numerical information is updated by subtraction are handled collectively, but it is also possible to collectively update both the subtraction type timer counters and the addition type timer counters.

[0148] Thereafter, a launch control process is executed to control the launch of gaming balls (step S311). While the launch operation to the launch operation device 28 continues, one gaming ball is launched at a predetermined launch cycle of 0.6 seconds. In the following step S312, as an input status monitoring process, based on the information read in the reading process of step S308, a disconnection check is performed for each ball entry detection sensor 42a-49a and whether the gaming machine main body 12 and the front door frame 14 are open is performed.

[0149] Thereafter, a special symbol special power control process is executed to control the execution of the game round and the execution of the open / close execution mode (step S313). The special symbol special power control process will be described in detail later.

[0150] Then, a normal map normal power control process is executed (step S314). In the normal map normal power control process, if a winning entry has occurred in the through gate 35, a process is executed to acquire the reserved information on the normal map side, and if the reserved information on the normal map side is stored, an opening judgment is made for the reserved information, and further, a process is executed to perform a normal map performance triggered by the opening judgment. Also, based on the result of the opening judgment, a process is executed to open and close the normal power device 34a of the second operating port 34. In this case, if the support mode is the low frequency support mode, a corresponding process is executed, and if the support mode is the high frequency support mode, a corresponding process is executed. Also, if the opening / closing execution mode is selected, the support mode immediately before will be the low frequency support mode even if it was the high frequency support mode.

[0151] In the subsequent step S315, based on the processing results of the immediately preceding steps S313 and S314, output information for reflecting the increase or decrease in the number of pieces of pending information related to the special drawing display section 37a in the special drawing pending display section 37b is set, and output information for reflecting the increase or decrease in the number of pieces of pending information related to the general drawing display section 38a in the general drawing pending display section 38b is set. Also, in step S315, based on the processing results of the immediately preceding steps S313 and S314, output information for updating the display content of the special drawing display section 37a is set, and output information for updating the display content of the general drawing display section 38a is set.

[0152] Thereafter, the content of the commands and signals received from the payout control device 77 is confirmed, and a payout state reception process for performing processing corresponding to the confirmation result is executed (step S316). Also, a payout output process for setting a payout command as an output target is executed (step S317). Also, an external information setting process for controlling the start and end of the output of an external signal according to the processing results of the various processes executed in this timer interrupt process is executed (step S318). Thereafter, a management output process for outputting information corresponding to the result of the entry of game balls in the game area PA to the management IC 66 is executed (step S319). Details of the management output process will be described later.

[0153] Next, the special drawing special power control process of step S313 will be described with reference to the flowchart of FIG. 12.

[0154] First, the process of acquiring hold information is executed (step S401). In the process of acquiring hold information, it is determined whether a winning has occurred at the first operation port 33 or the second operation port 34. If a winning has occurred, it is determined whether the number of holds in the hold storage area 65a is less than the upper limit value (in this embodiment, "4"). If the number of holds is less than the upper limit value, the number of holds is incremented by 1, and the numerical information of the hit random number counter C1, the jackpot type counter C2, and the reach random number counter C3 updated in the previous step S302 is stored in the first available hold area among the available hold areas RE1 to RE4 in the hold area RE. When a winning occurs simultaneously at the first operation port 33 and the second operation port 34, within the range of executing the process of acquiring hold information once, the process for acquiring the above hold information is executed multiple times. Also, when new hold information is acquired, the corresponding acquisition command is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the command, it causes the display of the image indicating the number of hold information in the symbol display device 41 to be updated to the display content corresponding to the increase in hold information.

[0155] After that, the information of the special figure special electric counter provided in the main side RAM 65 is read (step S402), and the special figure special electric address table provided in the main side ROM 64 is read (step S403). Then, the start address corresponding to the information of the special figure special electric counter is acquired from the special figure special electric address table (step S404), and a jump is made to the process indicated by the acquired start address among the processes of steps S406 to S412 (step S405). The special figure special electric counter is a counter for the main side CPU 63 to grasp which of the various processes of steps S406 to S412 should be executed, and the special figure special electric address table has the start address of the program for executing the processes of steps S406 to S412 set corresponding to the numerical information of the special figure special electric counter.

[0156] In step S406, the special figure change start process is executed. FIG. 13 is a flowchart showing the special figure change start process.

[0157] In the special drawing change start process, on the condition that the number of pending information stored in the pending area RE is 1 or more (step S501: YES), data setting processing is executed (step S502). In the data setting process, first, the number of pendings is decremented by 1, and the data stored in the first pending area RE1 of the pending area RE is moved to the execution area AE. After that, a process of shifting the data stored in each of the pending areas RE1 to RE4 of the pending area RE is executed. This data shift process is a process of shifting the data stored in the first pending area RE1 to the fourth pending area RE4 in order to the lower area side. Specifically, after shifting the data in each area such as the second pending area RE2 → the first pending area RE1, the third pending area RE3 → the second pending area RE2, and the fourth pending area RE4 → the third pending area RE3, the fourth pending area RE4 is cleared to "0". At this time, a shift command for recognizing that the data in the pending area has been shifted is transmitted to the voice and light control device 81. When the voice and light control device 81 receives the command, it updates the display of the image indicating the number of pending information in the symbol display device 41 to the display content corresponding to the decrease in the pending information.

[0158] After executing the data setting process, the pass / fail table is read from the main side ROM64 (step S503). Specifically, first, the information indicating the pass / fail lottery mode of the main side RAM65 is read to grasp the current pass / fail lottery mode. When it is the high probability mode, the high probability pass / fail table 64g is read from the main side ROM64. On the other hand, when it is the low probability mode, the setting state of the pachinko machine 10 is grasped by reading the value of the setting value counter of the main side RAM65. Then, the low probability pass / fail tables 64a to 64f corresponding to the grasped setting values are read from the main side ROM64.

[0159] Thereafter, the winning / losing table 64a-64g read in step S503 is referred to in order to execute the winning / losing determination process (step S504). In the winning / losing determination process, it is determined whether or not the winning / losing determination information stored in the execution area AE, i.e., the numerical information related to the winning random number counter C1, matches the jackpot numerical information set in the winning / losing table 64a-64g read in step S503.

[0160] If the result of the win / loss determination process is a jackpot winning result (step S505: YES), an allocation determination process is executed (step S506). In the allocation determination process, information for allocation determination from the information stored in the execution area AE, i.e., the numerical information related to the jackpot type counter C2, is read out. Then, by referring to the allocation table 64h provided in the main ROM 64, it is determined which jackpot result the numerical information related to the jackpot type counter C2 read out corresponds to. Specifically, it is determined which jackpot result it corresponds to: a low-probability jackpot result, a low-prize-winning high-probability jackpot result, or a most advantageous jackpot result.

[0161] Thereafter, a stop result setting process for the jackpot result is executed (step S507). Specifically, information on the form of the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for the jackpot result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. In this stop result table for the jackpot result, information on the form of the pattern to be stopped and displayed on the special symbol display unit 37a is set differently for each type of jackpot result.

[0162] Thereafter, a flag set process corresponding to the distribution determination result is executed (step S508). Specifically, flags corresponding to the types of each jackpot result are provided in the main RAM 65, and in step S508, the flag corresponding to the result of the distribution determination process in step S506 is set to "1".

[0163] On the other hand, if it is determined in step S505 that the result is not a jackpot, a stop result setting process for a loss result is executed (step S509). Specifically, information on the pattern to be finally stopped and displayed on the special symbol display unit 37a in the game round related to the start of the current variation is identified from a stop result table for a loss result stored in advance in the main ROM 64, and the identified information is written to the main RAM 65. The information on the pattern pattern selected in this case is different from the information on the pattern pattern selected in the case of a jackpot result.

[0164] After executing either the process of step S508 or step S509, a process for determining the duration of the game round is executed (step S510). In this process, the numerical information of the fluctuation type counter CS is acquired. Also, it is determined whether or not a reach display will occur on the pattern display device 41 in the current game round. Specifically, if the game round related to the start of the current fluctuation results in a low-probability jackpot result or a most favorable jackpot result, it is determined that a reach display will occur. Also, if neither of the jackpot results are obtained and the numerical information related to the reach random number counter C3 stored in the execution area AE is numerical information corresponding to the occurrence of a reach, it is determined that a reach display will occur.

[0165] If it is determined that a reach display will occur, the reach occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game round corresponding to the numerical information of the current variation type counter CS. On the other hand, if it is determined that a reach display will not occur, the reach non-occurrence duration table stored in the main ROM 64 is referenced to obtain the duration of the game round corresponding to the numerical information of the current variation type counter CS. Incidentally, the duration of the game round that can be obtained by reference to the reach non-occurrence duration table is different from the duration of the game round that can be obtained by reference to the reach occurrence duration table.

[0166] In addition, the duration of a game round when a reach does not occur is set such that the longer the number of hold information stored in the hold area RE, the shorter the duration of the game round. Also, in a situation where the support mode is the high-frequency support mode, a reach non-occurrence duration table is set so that a shorter game round duration is selected compared to a situation where the support mode is the low-frequency support mode when the number of hold information is the same. However, it is not limited to this, and the configuration may be such that the duration of the game round does not vary according to the number of hold information and the support mode, or it may be the reverse of the above relationship. Furthermore, the above configuration may be applied to the duration of a game round when a reach occurs. Also, for each case of various jackpot results, a duration table may be set individually for the case of an off-reach, the case of a reach non-occurrence off result. In this case, the duration of the game round corresponding to each game result is allocated.

[0167] Thereafter, the information on the duration of the game round obtained in step S510 is set in the special figure special power timer counter provided in the main-side RAM 65 (step S511). The update of the numerical information set in the special figure special power timer counter is executed in the timer update process (step S310). Incidentally, as an effect for the game, a pattern change display is performed on the special figure display unit 37a and a pattern change display is performed on the pattern display device 41. When each of these change displays ends, the stop result of that game round is displayed (in the pattern display device 41, a state where a predetermined combination of patterns is waiting on the active line), and the final stop display is performed for a final stop period (for example, 0.5 seconds). In this case, the duration of the game round obtained in step S510 is the total time for one game round.

[0168] Thereafter, the variable command and the type command are transmitted to the audio-visual control device 81 (step S512). The variable command includes information on the duration of the game round. Here, since the duration of the game round obtained by referring to the non-reach occurrence duration table as described above is different from the duration of the game round obtained by referring to the reach occurrence duration table, even if the variable command does not include information on the presence or absence of reach occurrence, the audio-visual control device 81 can specify the presence or absence of reach occurrence from the information on the duration of the game round. In this regard, it can be said that the variable command includes information indicating the presence or absence of reach occurrence. Note that the variable command may directly include information indicating the presence or absence of reach occurrence. Further, the type command includes information on the game result.

[0169] When the audio-visual control device 81 receives the variable command and the type command from the main CPU 63, the display light-emitting unit 53, the speaker unit 54, and the symbol display device 41 perform effects for the game. In this case, the effects for the game are performed in a manner corresponding to the contents of the variable command and the type command. Further, in the symbol display device 41, variable display of symbols is performed as an effect for the game, and when the effect for the game ends, the combination of symbols corresponding to the result of the win / loss determination process and the allocation determination process is stopped and displayed.

[0170] Thereafter, the variable display of the picture in the special figure display unit 37a is started (step S513). Then, the special figure special power counter is incremented by 1 (step S514). In this case, since the numerical information of the special figure special power counter when the special figure variable start process is executed is "0", the numerical information of the special figure special power counter becomes "1". Thereafter, "1" is set in the 11th output flag provided in the main RAM 65 (step S515). The 11th output flag is a flag for the main CPU 63 to specify that the information output indicating that the game round has started should be executed for the management IC 66.

[0171] Returning to the description of the special drawing special power control process (Figure 52), in step S407, the process during special drawing change is executed. In the process during special drawing change, it is determined whether it is during the continuation time of the game round and before the final stop display timing. If it is before the final stop display, a process for regularly changing the display mode of the pattern on the special drawing display unit 37a is executed. When it becomes the timing to perform the final stop display, the numerical information of the special drawing special power counter is incremented by 1, and the numerical information of the counter is updated from the one corresponding to the process during special drawing change to the one corresponding to the process during special drawing determination. Note that in this embodiment, the main CPU 63 does not send the final stop command to the audio and light emission control device 81.

[0172] In step S408, the process during special drawing determination is executed. In the process during special drawing determination, the display mode of the pattern on the special drawing display unit 37a is set to the display mode corresponding to the lottery result of the current game round. Also, in the process during special drawing determination, it is determined whether the final stop period has elapsed. If the period has elapsed, it is determined whether a transition to the opening / closing execution mode occurs. If the transition to the opening / closing execution mode does not occur, the numerical information of the special drawing special power counter is cleared to "0". If the transition to the opening / closing execution mode occurs, the numerical information of the special drawing special power counter is incremented by 1, and the numerical information of the counter is updated from the one corresponding to the process during special drawing determination to the one corresponding to the special power start process.

[0173] In step S409, special power start processing is executed. In the special power start processing, if the processing for starting the opening period in the current opening / closing execution mode has not yet been executed, the opening period setting processing is executed. An opening command is also sent to the audio and light-emitting control device 81. Upon receiving the opening command, the audio and light-emitting control device 81 causes the display light-emitting unit 53, speaker unit 54, and symbol display device 41 to execute an opening effect. If the opening period has elapsed, a start processing is executed to start the first round of play. In this start processing, the special power winning device 32 is set to an open state and the end conditions for the round of play are set. When setting this end condition, an upper limit duration for continuing the special power winning device 32 in an open state in the current first round of play is set, and the upper limit number of game balls that can win the special power winning device 32 in the current first round of play is set in a winning number counter provided in the main RAM 65.

[0174] In step S410, special line open processing is executed. In the special line open processing, it is determined whether the end condition for the round game has been met. If the end condition has been met, the special line winning device 32 is closed. Then, if the round game that has just finished is not the last round game executed, the numerical information of the special line counter is incremented by 1 to update the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line closed processing. If the round game that just finished is the last round game executed, the numerical information of the special line counter is incremented by 2 to update the numerical information of the counter from that corresponding to the special line open processing to that corresponding to the special line end processing.

[0175] In step S411, the special power-off closing process is executed. In the special power-off closing process, it is determined whether or not the interval period between round games has elapsed. The interval period is set when the previous round game ends. When the interval period has elapsed, the special power winning device 32 is set to the open state and the end condition of the round game is set. Then, by subtracting 1 from the numerical information of the special figure special power counter, the numerical information of the counter is updated from the one corresponding to the special power-off closing process to the one corresponding to the special power-open process.

[0176] In step S412, the special power end process is executed. In the special power end process, if the process for starting the ending period in the current opening / closing execution mode has not been executed yet, an ending period (for example, 5 seconds) is set and an ending command is transmitted to the audio-visual control device 81. When the audio-visual control device 81 receives the ending command, an ending effect is executed by the display and lighting unit 53, the speaker unit 54, and the symbol display device 41. When the ending period has elapsed, each of the win / loss lottery mode and the support mode after the end of the opening / closing execution mode is set to the mode corresponding to the jackpot result that triggered the start of the current opening / closing execution mode.

[0177] Next, a configuration for specifying the presence or absence of game balls entering the out port 24a, the general winning port 31, the special power winning device 32, the first operating port 33, the second operating port 34, and the through gate 35 based on the detection results of the ball entry detection sensors 42a to 49a by the main CPU 63 will be described. FIG. 14 is an explanatory diagram for explaining a configuration in which the detection results of the ball entry detection sensors 42a to 49a are input to the main CPU 63.

[0178] The main CPU 63 is provided with an input port 63a. The input port 63a is configured as an 8-bit parallel interface so that it can handle eight types of signals simultaneously. An area in which information "0" or "1" is stored according to the voltage of each signal is provided in one-to-one correspondence with each terminal. That is, this area includes the 0th bit D0 to the 7th bit D7. Although more than eight types of signals are input to the input port 63a, in order to limit the number of signals that can be input simultaneously to eight, the group of signals to be input to the input port 63a is switched through switching control by a driver IC.

[0179] In the ball entry detection process (step S309) of the timer interrupt process (FIG. 11), the signal group to be input to the input port 63a is set to the signal group from each ball entry detection sensor 42a-49a. In such a setting, the 0th bit D0 stores information corresponding to the detection signal from the first winning opening detection sensor 42a, the 1st bit D1 stores information corresponding to the detection signal from the second winning opening detection sensor 43a, the 2nd bit D2 stores information corresponding to the detection signal from the third winning opening detection sensor 44a, the 3rd bit D3 stores information corresponding to the detection signal from the special power detection sensor 45a, the 4th bit D4 stores information corresponding to the detection signal from the first operating opening detection sensor 46a, the 5th bit D5 stores information corresponding to the detection signal from the second operating opening detection sensor 47a, the 6th bit D6 stores information corresponding to the detection signal from the outlet detection sensor 48a, and the 7th bit D7 stores information corresponding to the detection signal from the gate detection sensor 49a.

[0180] Each of the ball entry detection sensors 42a-49a outputs a LOW-level signal indicating that it is not detecting a ball when it has not detected the passage of a game ball, and outputs a HI-level signal indicating that it is detecting a ball when it has detected the passage of a game ball. The input port 63a stores "0" in the corresponding bit when it receives a LOW-level signal, and stores "1" in the corresponding bit when it receives a HI-level signal. In other words, when the ball entry detection sensors 42a-49a have not detected the passage of a game ball, the corresponding bit stores "0" indicating that it is not detecting a game ball, and when it has detected the passage of a game ball, the corresponding bit stores "1" indicating that it is detecting a game ball.

[0181] FIG. 15 is a flowchart showing the ball scoring detection process executed in step S309 of the timer interrupt process (FIG. 11).

[0182] When it is confirmed that the 0th bit D0 has switched from a state in which "0" is stored to a state in which "1" is stored, it is determined that one gaming ball has been detected by the first winning opening detection sensor 42a (step S601: YES). In this case, the first output flag provided in the main RAM 65 is set to "1" (step S602), and the value of the 10-prize ball counter provided in the main RAM 65 is incremented by 1 (step S603). The first output flag is a flag that specifies to the main CPU 63 that information indicating that one gaming ball has been detected by the first winning opening detection sensor 42a should be output to the management IC 66. The 10-prize ball counter is a counter that specifies to the main CPU 63 the number of times that 10 gaming balls should be paid out. If the value of the 10 prize ball counter is 1 or more, a 10 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Fig. 11), and when the 10 prize ball command is output once, the value of the 10 prize ball counter is decremented by 1. When the payout control device 77 receives the 10 prize ball command, it drives and controls the payout device 76 so that 10 game balls are paid out.

[0183] When it is confirmed that the situation has switched from the situation where the information “0” is stored in the first bit D1 to the situation where the information “1” is stored, if it is determined that one game ball has been detected by the second winning port detection sensor 43a (step S604: YES). In this case, “1” is set to the second output flag provided in the main-side RAM 65 (step S605), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S606). The second output flag is a flag for the main CPU 63 to specify that the information output indicating that one game ball has been detected by the second winning port detection sensor 43a should be executed for the management IC 66.

[0184]

[0185] When it is confirmed that the situation has switched from the situation where the information “0” is stored in the second bit D2 to the situation where the information “1” is stored, if it is determined that one game ball has been detected by the third winning port detection sensor 44a (step S607: YES). In this case, “1” is set to the third output flag provided in the main-side RAM 65 (step S608), and the value of the 10 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S609). The third output flag is a flag for the main CPU 63 to specify that the information output indicating that one game ball has been detected by the third winning port detection sensor 44a should be executed for the management IC 66.When it is confirmed that the situation has switched from the state where the information "0" is stored in the third bit D3 to the state where the information "1" is stored, it is determined that one game ball has been detected by the special power detection sensor 45a (step S610: YES). In this case, "1" is set to the special power winning flag provided in the main-side RAM 65 (step S611), "1" is set to the fourth output flag provided in the main-side RAM 65 (step S612), and further, the value of the 15 prize ball counter provided in the main-side RAM 65 is incremented by 1 (step S613). The special power winning flag is a flag for the main-side CPU 63 to identify that one game ball has entered the special power winning device 32 in the round game of the opening / closing execution mode. In the special feature special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the special power winning flag, it is identified that one game ball has entered the special power winning device 32, and the remaining number of balls that can enter the special power winning device 32 in the round game is decremented by 1. When the process of decrementing the number of balls that can enter by 1 is executed, the special power winning flag is cleared to "0". The fourth output flag is a flag for the main-side CPU 63 to identify that the information output indicating that one game ball has been detected by the special power detection sensor 45a should be executed for the management IC 66. The 15 prize ball counter is a counter for the main-side CPU 63 to identify the number of times the payout of 15 game balls should be executed. When the value of the 15 prize ball counter is 1 or more, in the payout output process of step S317 in the timer interrupt process (FIG. 11), a 15 prize ball command is output to the payout control device 77, and when the 15 prize ball command is output once, the value of the 15 prize ball counter is decremented by 1. When the payout control device 77 receives the 15 prize ball command, it drives and controls the payout device 76 so that 15 game balls are paid out.

[0186] When it is confirmed that the fourth bit D4 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the first actuation port detection sensor 46a (step S614: YES). In this case, the first actuation winning flag provided in the main RAM 65 is set to "1" (step S615), the fifth output flag provided in the main RAM 65 is set to "1" (step S616), and further the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S617). The first actuation winning flag is a flag for the main CPU 63 to identify that one gaming ball has entered the first actuation port 33. In the special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the first activation winning flag is set to "1," a process for storing new reserved information is executed, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power control process (step S313), it is confirmed that the first activation winning flag is set to "1," and when a process corresponding to that confirmation is executed, the first activation winning flag is cleared to "0." The fifth output flag is a flag for specifying in the main CPU 63 that information indicating that one game ball has been detected by the first activation port detection sensor 46a should be output to the management IC 66. The single prize ball counter is a counter for specifying in the main CPU 63 the number of times one game ball should be paid out. If the value of the 1 prize ball counter is 1 or more, a 1 prize ball command is output to the payout control device 77 in the payout output process of step S317 in the timer interrupt process (Fig. 11), and when the 1 prize ball command is output once, the value of the 1 prize ball counter is decremented by 1. When the payout control device 77 receives the 1 prize ball command, it drives and controls the payout device 76 so that one game ball is paid out.

[0187] When it is confirmed that the fifth bit D5 has switched from a state in which information "0" is stored to a state in which information "1" is stored, it is determined that one gaming ball has been detected by the second actuation port detection sensor 47a (step S618: YES). In this case, the second actuation winning flag provided in the main RAM 65 is set to "1" (step S619), and the sixth output flag provided in the main RAM 65 is set to "1" (step S620), and further the value of the one winning ball counter provided in the main RAM 65 is incremented by 1 (step S621). The second actuation winning flag is a flag that allows the main CPU 63 to identify that one gaming ball has entered the second actuation port 34. In the special power control process (step S313) of the timer interrupt process (FIG. 11), by confirming that the second activation winning flag is set to "1," a process for storing new reserved information is executed, provided that the number of reserved information stored in the reserved area RE of the reserved storage area 65a is less than the upper limit of four. In the special power control process (step S313), it is confirmed that the second activation winning flag is set to "1," and when a process corresponding to that confirmation is executed, the second activation winning flag is cleared to "0." The sixth output flag is a flag for specifying in the main CPU 63 that information indicating that one game ball has been detected by the second activation port detection sensor 47a should be output to the management IC 66.

[0188] When it is confirmed that the sixth bit D6 has changed from a state in which the information "0" is stored to a state in which the information "1" is stored, it is determined that one gaming ball has been detected by the outlet detection sensor 48a (step S622: YES). In this case, the seventh output flag provided in the main RAM 65 is set to "1" (step S623). The seventh output flag is a flag for specifying in the main CPU 63 that information indicating that one gaming ball has been detected by the outlet detection sensor 48a should be output to the management IC 66.

[0189] When it is confirmed that the situation has switched from the situation where the information "0" is stored in the 7th bit D7 to the situation where the information "1" is stored, it is determined that one game ball has been detected by the gate detection sensor 49a (step S624: YES). In this case, "1" is set in the gate winning flag provided in the main side RAM 65 (step S625). The gate winning flag is a flag for the main side CPU 63 to identify that one game ball has entered the through gate 35. In the general diagram general power control process (step S314) of the timer interrupt process (FIG. 11), by confirming that "1" is set in the gate winning flag, on the condition that the number of pieces of hold information on the general diagram side stored in the general power hold area 65c is less than the upper limit number of 4, the process of storing the numerical information of the current general power accessory release counter C4 as the hold information on the general diagram side in the general power hold area 65c is executed. When it is confirmed in the general diagram general power control process (step S314) that "1" is set in the gate winning flag and the process corresponding to the confirmation is executed, the gate winning flag is cleared to "0".

[0190] Note that since the timer interrupt process (FIG. 11) is activated at a cycle of 4 milliseconds as already described, when the detection of one game ball is started by one of the ball entry detection sensors 42a to 49a, in the situation where the detection of that one game ball is continued by the ball entry detection sensors 42a to 49a, the main side CPU 63 identifies that one game ball has been detected by the ball entry detection sensors 42a to 49a. Therefore, it is sufficient to provide one each of the first to seventh output flags.

[0191] Next, the processing content executed by the payout control device 77 will be described. First, the electrical configuration of the payout control device 77 and various devices that communicate with the payout control device 77 will be described with reference to the block diagram of FIG. 16.

[0192] The payout control device 77 includes an MPU 91. In the MPU 91, in addition to the payout side CPU 92 which is an arithmetic processing device including a control unit and an arithmetic unit, a payout side ROM 93, a payout side RAM 94, an interrupt circuit, a timer circuit, a data input / output circuit, and the like are built in.

[0193] The payout-side ROM 93 is a memory that does not require external power supply for data retention, such as a NOR-type flash memory and a NAND-type flash memory (i.e., non-volatile storage means), and is used as read-only. The payout-side ROM 93 stores various control programs and fixed-value data executed by the payout-side CPU 92.

[0194] The payout-side RAM 94 is a memory that requires external power supply for data retention, such as SRAM and DRAM (i.e., volatile storage means), and is used for both reading and writing. The payout-side RAM 94 allows random access and has a shorter read time than the payout-side ROM 93 when compared with the same data capacity. The payout-side RAM 94 temporarily stores various data for the execution of the control programs stored in the payout-side ROM 93.

[0195] The payout CPU 92 is capable of bidirectional communication with the main CPU 63. By receiving a prize ball command from the main CPU 63, the payout CPU 92 controls the operation of the payout device 76 so that the number of game balls corresponding to the prize ball command is paid out. The payout CPU 92 also monitors whether the payout device 76 is in a state where game balls can be paid out normally, and if it determines that the payout device 76 is in a state where game balls cannot be paid out normally, it stops the payout device 76 even if information on the number of unpaid prize balls is stored in the payout RAM 94. The payout CPU 92 also transmits a payout limit command to the main CPU 63 indicating that the payout device 76 is in a state where game balls cannot be paid out normally. When the main CPU 63 receives the payout limit command, it transmits a notification command to the audio / light-emitting control device 81 so that the symbol display device 41, the display light-emitting unit 53, and the speaker unit 54 issue a notification indicating that the payout device 76 is in a state where game balls cannot be paid out normally. The states in which game balls cannot be dispensed normally include a full state in which the lower tray 56a is full of game balls, a no-ball state in which the tank 75 has not been replenished with game balls, an abnormal dispense state in which the dispenser 76 does not operate normally, a main body open state in which the game machine main body 12 is open from the outer frame 11, and a front door open state in which the front door frame 14 is open from the inner frame 13.

[0196] A full tank detection sensor (not shown) is provided midway along the game ball passageway leading from the payout device 76 to the lower tray 56a, and the detection result of the full tank detection sensor is input to the payout side CPU 92. The payout side CPU 92 determines that the tank is full when game balls are continuously detected by the full tank detection sensor, and determines that the full tank state has been released when the state in which game balls are continuously detected by the full tank detection sensor is released.

[0197] A ball non-detection sensor (not shown) is provided at an intermediate position of the game ball passage leading from the tank 75 to the payout device 76, and the detection result of the ball non-detection sensor is input to the payout-side CPU 92. When the game ball is not continuously detected by the ball non-detection sensor, the payout-side CPU 92 identifies that it is in a ball non-state, and when the state where the game ball is not continuously detected by the ball non-detection sensor is released, the payout-side CPU 92 identifies that the ball non-state has been released.

[0198] The payout device 76 is provided with a payout detection sensor (not shown) for detecting the game balls paid out from the payout device 76, and the detection result of the payout detection sensor is input to the payout-side CPU 92. When the game ball is detected by the payout detection sensor, the payout-side CPU 92 identifies that one game ball has been paid out from the payout device 76. Further, even though the payout-side CPU 92 is driving and controlling the payout device 76 so that the game balls are paid out, when the game ball is not continuously detected by the payout detection sensor, the payout-side CPU 92 identifies that it is in a payout abnormal state, and when the state where the game ball is not continuously detected by the payout detection sensor is released, the payout-side CPU 92 identifies that the payout abnormal state has been released.

[0199] A front door open sensor 95 is provided on the front portion of the inner frame 13 (see FIG. 2), and the detection result of the front door open sensor 95 is input to the dispensing-side CPU 92. In this case, when the front door frame 14 is closed relative to the inner frame 13, the front door open sensor 95 transmits a closed detection signal to the dispensing-side CPU 92, and when the front door frame 14 is open relative to the inner frame 13, the front door open sensor 95 transmits an open detection signal to the dispensing-side CPU 92. The dispensing-side CPU 92 determines that the front door frame 14 is closed when it receives a closed detection signal from the front door open sensor 95, and determines that the front door frame 14 is open when it receives an open detection signal from the front door open sensor 95. In addition, the dispensing-side CPU 92 transmits a front door open command to the main-side CPU 63 when it determines that the front door frame 14 has changed from a closed state to an open state, and transmits a front door close command to the main-side CPU 63 when it determines that the front door frame 14 has changed from an open state to a closed state. The main CPU 63 determines that the front door frame 14 is in an open state when it receives a front door open command, and determines that the front door frame 14 is in a closed state when it receives a front door close command.

[0200] A main body opening sensor 96 is provided on the front portion of the inner pack unit 15 (see FIG. 2), and the detection result of the main body opening sensor 96 is input to the payout-side CPU 92. In this case, when the gaming machine main body 12 is in a closed state with respect to the outer frame 11, the main body opening sensor 96 transmits a closed detection signal to the payout-side CPU 92, and when the gaming machine main body 12 is in an open state with respect to the outer frame 11, the main body opening sensor 96 transmits an open detection signal to the payout-side CPU 92. The payout-side CPU 92 identifies that the gaming machine main body 12 is in a closed state when receiving a closed detection signal from the main body opening sensor 96, and identifies that the gaming machine main body 12 is in an open state when receiving an open detection signal from the main body opening sensor 96. Further, the payout-side CPU 92 transmits a main body opening command to the main-side CPU 63 at the timing when it is identified that the gaming machine main body 12 has changed from a closed state to an open state, and transmits a main body closing command to the main-side CPU 63 at the timing when it is identified that the gaming machine main body 12 has changed from an open state to a closed state. The main-side CPU 63 identifies that the gaming machine main body 12 is in an open state when receiving the main body opening command, and identifies that the gaming machine main body 12 is in a closed state when receiving the main body closing command.

[0201] With reference to the flowchart of FIG. 17, the timer interrupt process executed by the payout-side CPU 92 will be described. The timer interrupt process is repeatedly started at a predetermined cycle (for example, 2 milliseconds).

[0202] First, the full state process is executed (step S701). In the full state process, based on the detection result of the full state detection sensor as already described, it is identified whether it is in a full state, and when it is in a full state, a process for stopping the payout of the game balls is executed, and a command indicating that it is in a full state is transmitted to the main-side CPU 63. Further, when the full state is released, a process for enabling the payout of the game balls is executed, and a command indicating that the full state has been released is transmitted to the main-side CPU 63.

[0203] Thereafter, no-ball processing is executed (step S702). In the no-ball processing, as already explained, it is determined whether or not the no-ball state is present based on the detection result of the no-ball detection sensor, and if the no-ball state is present, it executes processing to stop the payout of game balls and sends a command indicating the no-ball state to the main CPU 63. Furthermore, if the no-ball state is released, it executes processing to enable the payout of game balls and sends a command indicating that the no-ball state has been released to the main CPU 63.

[0204] Thereafter, a payout abnormality monitoring process is executed (step S703). In the payout abnormality monitoring process, as already explained, it is determined whether or not a payout abnormality state exists based on the detection result of the payout detection sensor, and if a payout abnormality state exists, a process to stop the payout of game balls is executed, and a command indicating that a payout abnormality state exists is sent to the main CPU 63. Furthermore, if the payout abnormality state is released, a process to enable the payout of game balls is executed, and a command indicating that the payout abnormality state has been released is sent to the main CPU 63.

[0205] Thereafter, a front door open monitoring process is executed (step S704). In the front door open monitoring process, as already explained, it is determined whether or not the front door frame 14 is in the open state based on the detection result of the front door open sensor 95, and if the front door frame 14 is in the open state, a process to stop the payout of game balls is executed and a front door open command is sent to the main CPU 63. Furthermore, if the front door frame 14 is closed, a process to enable the payout of game balls is executed and a front door close command is sent to the main CPU 63.

[0206] Thereafter, a main body open monitoring process is executed (step S705). In the main body open monitoring process, as already explained, it is determined whether or not the gaming machine main body 12 is in the open state based on the detection result of the main body open sensor 96, and if the gaming machine main body 12 is in the open state, a process to stop the payout of game balls is executed and a main body open command is sent to the main CPU 63. Furthermore, if the gaming machine main body 12 is closed, a process to enable the payout of game balls is executed and a main body close command is sent to the main CPU 63.

[0207] Then, a command read process is executed (step S706). In the command read process, a process is executed to read the prize ball command sent by the main CPU 63, and the prize ball command is stored in the payout RAM 94. Then, a prize ball setting process is executed to add the number corresponding to the received prize ball command to the unpaid prize ball number information in the payout RAM 94 (step S707), and then a payout control process is executed to control the execution of the payout of game balls by the payout device 76 (step S708). In the payout control process, when the unpaid prize ball number information stored in the payout RAM 94 is a value of 1 or more, the payout device 76 is driven and controlled, and when the payout detection sensor detects one game ball, the value of the prize ball number information is decremented by 1. Then, when the value of the prize ball number information becomes "0," the drive control of the payout device 76 is stopped. Thereafter, an external information setting process is executed to control the start and end of output of an external signal according to the results of the various processes executed in this timer interrupt process (step S709).

[0208] Next, a configuration for externally outputting information from the pachinko machine 10 to the hall computer HC installed in the gaming hall will be described.

[0209] As shown in FIG. 2, an external terminal board 97 is provided in the back pack unit 15. A number of external terminals are provided on the external terminal board 97. A plurality of some of the external terminals are electrically connected to the main CPU 63, and a plurality of some of the external terminals are electrically connected to the payout CPU 92. Since each of the main CPU 63 and the payout CPU 92 is electrically connected to the external terminal board 97 in this way, as shown in FIG. 16, the main CPU 63 and the payout CPU 92 can externally output information to the whole computer HC.

[0210] One external terminal of the external terminal board 97 is electrically connected to the front door open sensor 95, and one external terminal of the external terminal board 97 is electrically connected to the main body open sensor 96. Regarding the configuration of this electrical connection in detail, a signal relay board 98 is provided at an intermediate position in the signal path from the front door open sensor 95 toward the payout CPU 92. A branch path SL2 is provided on the signal relay board 98 by branching from the signal path SL1 from the front door open sensor 95 toward the payout CPU 92. And the branch path SL2 is connected to the external terminal for front door opening on the external terminal board 97. Therefore, an electrical signal corresponding to the detection result of the front door open sensor 95 is input not only to the payout CPU 92 but also to the external terminal for front door opening on the external terminal board 97. Thereby, it becomes possible to externally output a signal indicating whether or not the front door frame 14 is in an open state to the whole computer HC without going through the control by the payout CPU 92.

[0211] Regarding the main body opening sensor 96 in detail, a branch path SL4 is provided in the signal relay board 98 by branching from the signal path SL3 directed from the main body opening sensor 96 toward the payout-side CPU 92. And the branch path SL4 is connected to the external terminal for main body opening in the external terminal board 97. Therefore, the electrical signal corresponding to the detection result in the main body opening sensor 96 is input not only to the payout-side CPU 92 but also to the external terminal for main body opening in the external terminal board 97. As a result, it becomes possible to externally output a signal indicating whether the gaming machine main body 12 is in an open state to the hall computer HC without going through the control by the payout-side CPU 92.

[0212] Next, the content of the information externally output from the main-side CPU 63 and the payout-side CPU 92 to the hall computer HC will be described. First, the content of the information externally output from the main-side CPU 63 to the hall computer HC will be described.

[0213] The main-side CPU 63 performs output setting of information to each external terminal assigned to the main-side CPU 63 in the external terminal board 97 in the external information setting process (step S318) in the timer interrupt process (FIG. 11). Information output from the main-side CPU 63 to the external terminal board 97 includes information indicating that it is in the opening / closing execution mode, information indicating that the support mode is the high-frequency support mode, information indicating that one game round has ended, information indicating that a predetermined number (for example, 100) of game balls have been discharged from the game area PA through any one of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34, information indicating that a game ball has entered the first operation port 33, and information indicating that a game ball has entered the second operation port 34.

[0214] The payout-side CPU 92 performs output setting of information to each external terminal assigned to the payout-side CPU 92 in the external terminal board 97 in the external information setting process (step S709) in the timer interrupt process (FIG. 17). Information output from the payout-side CPU 92 to the external terminal board 97 includes information indicating that 10 game balls have been paid out.

[0215] The hall computer HC can grasp the manner in which game balls are paid out in the pachinko machine 10 in accordance with various information received from the pachinko machine 10 via the external terminal board 97. For example, The payout rate, which is the ratio of the number of game balls paid out until 100 game balls are discharged from the game area PA of the pachinko machine 10. - Ball payout rate in normal game mode, not in open / close execution mode or high frequency support mode (hereinafter, this ball payout rate will be referred to as "B") Ball payout rate in open / close execution mode - Ball payout rate in high frequency support mode The number of times a game is played until 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S"). BS x "Number of winning balls for winning into the first actuation port 33 and the second actuation port 34" The number of game balls that enter the first operating port 33 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S1") The number of game balls that enter the second operating port 34 before 100 game balls are discharged from the game area PA of the pachinko machine 10 (hereinafter, this ratio will be referred to as "S2") B-(S1 x "number of winning balls for winning into the first operating port 33" + S2 x "number of winning balls for winning into the second operating port 34") Probability of opening / closing execution mode occurring per unit play Probability of high frequency support mode occurring per unit play This allows the hall computer HC to manage the manner in which game balls enter the game area PA of the pachinko machine 10. The number of prize balls refers to the number of game balls that are paid out when one game ball enters the corresponding ball entry section.

[0216] <Configuration for managing winning status of gaming balls> Next, a configuration for managing game history using the management IC 66 will be described. First, the electrical configuration of the management IC 66 will be described with reference to the block diagram of FIG. 18.

[0217] As already described, the MPU 62 of the main control device 60 includes a main CPU 63, a main ROM 64, a main RAM 65, and a management IC 66. In addition, the MPU 62 includes an I / F 101 and the already-described reading terminal 68d.

[0218] The I / F 101 is an interface for transmitting and receiving signals between the MPU 62 and external devices. The I / F 101 is electrically connected to the main CPU 63 via an internal bus 103. Detection results from sensors such as the ball entry detection sensors 42a to 49a and commands from the payout-side CPU 92 are input to the MPU 62 through the input port of the I / F 101, and various processes are executed by the main CPU 63 as already described based on the input detection results and command contents. Also, when a signal output is performed to a device such as the special power drive unit 32b as a result of various processes being executed by the main CPU 63, the signal output is performed through the output port of the I / F 101, and when a command output is performed to the payout-side CPU 92 and the sound and light control device 81 as a result of various processes being executed by the main CPU 63, the command output is performed through the output port of the I / F 101.

[0219] The management IC 66 includes a management-side I / F 111, a management-side CPU 112, a management-side ROM 113, a management-side RAM 114, an RTC 115, a correspondence relation memory 116, a history memory 117, and a calculation result memory 131. These devices are connected so as to be capable of two-way communication through an internal bus 66a provided in the management IC 66.

[0220] The management-side I / F 111 is an interface for receiving various signals from the main-side CPU 63 via the signal path group 118 for unidirectional communication built into the MPU 62, and for transmitting various signals to the reading terminal 68d via the signal path group 119 for unidirectional communication built into the MPU 62. Various signals from the main-side CPU 63 are input to the input port of the management-side I / F 111, and various signals to the reading terminal 68d are output from the output port of the management-side I / F 111. Note that the main-side CPU 63 is electrically connected to the reading terminal 68d via the signal path group 120 for bidirectional communication built into the MPU 62.

[0221] The management-side CPU 112 is an arithmetic processing unit including a control unit and an arithmetic unit. The management-side ROM 113 is a memory (i.e., non-volatile storage means) such as a NOR-type flash memory and a NAND-type flash memory that does not require external power supply for storage retention, and is used as read-only. The management-side ROM 113 stores various control programs and fixed-value data executed by the management-side CPU 112. The management-side RAM 114 is a memory (i.e., volatile storage means) such as an SRAM and a DRAM that requires external power supply for storage retention, and is used for both reading and writing. The management-side RAM 114 allows random access and has a shorter read time than the management-side ROM 113 when compared with the same data capacity. The management-side RAM 114 temporarily stores various data and the like for the execution of the control programs stored in the management-side ROM 113.

[0222] The RTC 115 is a real-time clock, which is configured to constantly measure year / month / day information and time information and output the measured year / month / day information and time information (hereinafter also referred to as date / time information) according to an instruction from the management-side CPU 112. Note that the RTC 115 is provided with a backup power supply, and can measure year / month / day information and time information even when the power of the pachinko machine 10 is cut off.

[0223] The correspondence memory 116 is a memory (i.e., a volatile storage means) that requires an external power supply to retain data, such as an SRAM or DRAM, and is used for both reading and writing. The correspondence memory 116 is used to store information on the correspondence between each of the buffers 122a-122p provided in the input port 121 of the management side I / F 111 and the types of signals input to those buffers 122a-122p. The contents of the correspondence memory 116 will be described in detail later.

[0224] The history memory 117 is a memory (i.e., a non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The history memory 117 is used to store information related to the game history received from the main CPU 63 via the management I / F 111. Details of the contents of the history memory 117 will be explained later.

[0225] The calculation result memory 131 is a memory (i.e., non-volatile storage means) that does not require an external power supply to retain data, such as a NOR flash memory or a NAND flash memory, and is used for both reading and writing. The calculation result memory 131 is used to sequentially store various parameters calculated by the management CPU 112 using the history information stored in the history memory 117. The contents of the various parameters stored in the calculation result memory 131 are sequentially displayed on the first to third notification display devices 69a to 69c, and are also output to an external device connected to the reading terminal 68d.

[0226] Next, a description will be given of the configuration of the input port 121 provided in the management side I / F 111. Fig. 19 is an explanatory diagram for explaining the configuration of the input port 121 of the management side I / F 111.

[0227] A plurality of buffers 122a to 122p are provided in the input port 121. Specifically, the first to sixteenth buffers 122a to 122p are provided. Each of the first to sixteenth buffers 122a to 122p can input one type of signal through signal paths 118a to 118p. When the signal to be input is at the LOW level, the information of "0" is stored as the first data in each of the first to sixteenth buffers 122a to 122p, and when the signal to be input is at the HI level, the information of "1" is stored as the second data. Note that the relationship between LOW and HI and the first and second data may be reversed.

[0228] A first signal corresponding to the detection result of the first winning port detection sensor 42a is input to the first buffer 122a. In this case, the main CPU 63 outputs a LOW-level first signal when no new game ball is detected by the first winning port detection sensor 42a, and outputs a HI-level first signal for a specific period when one game ball is detected by the first winning port detection sensor 42a. This specific period is sufficient for the management-side CPU 112 to identify that the HI-level first signal is input to the first buffer 122a.

[0229] A second signal corresponding to the detection result of the second winning port detection sensor 43a is input to the second buffer 122b. In this case, the main CPU 63 outputs a LOW-level second signal when no new game ball is detected by the second winning port detection sensor 43a, and outputs a HI-level second signal for a specific period when one game ball is detected by the second winning port detection sensor 43a. This specific period is sufficient for the management-side CPU 112 to identify that the HI-level second signal is input to the second buffer 122b.

[0230] A third signal corresponding to the detection result of the third winning opening detection sensor 44a is input to the third buffer 122c. In this case, the main CPU 63 outputs a third signal at a LOW level when no new game ball is detected by the third winning opening detection sensor 44a, and outputs a third signal at a HI level for a specific period when one game ball is detected by the third winning opening detection sensor 44a. This specific period is long enough for the management CPU 112 to identify that a HI-level third signal is input to the third buffer 122c.

[0231] A fourth signal corresponding to the detection result of the special electric detection sensor 45a is input to the fourth buffer 122d. In this case, the main CPU 63 outputs a fourth signal at a LOW level when no new game ball is detected by the special electric detection sensor 45a, and outputs a fourth signal at a HI level for a specific period when one game ball is detected by the special electric detection sensor 45a. This specific period is long enough for the management CPU 112 to identify that a HI-level fourth signal is input to the fourth buffer 122d.

[0232] A fifth signal corresponding to the detection result of the first operating opening detection sensor 46a is input to the fifth buffer 122e. In this case, the main CPU 63 outputs a fifth signal at a LOW level when no new game ball is detected by the first operating opening detection sensor 46a, and outputs a fifth signal at a HI level for a specific period when one game ball is detected by the first operating opening detection sensor 46a. This specific period is long enough for the management CPU 112 to identify that a HI-level fifth signal is input to the fifth buffer 122e.

[0233] A sixth signal corresponding to the detection result of the second actuation port detection sensor 47a is input to the sixth buffer 122f. In this case, the main CPU 63 outputs a LOW-level sixth signal when the second actuation port detection sensor 47a does not detect a new gaming ball, and outputs a HI-level sixth signal for a specific period when the second actuation port detection sensor 47a detects one gaming ball. This specific period is long enough for the management CPU 112 to determine that a HI-level sixth signal has been input to the sixth buffer 122f.

[0234] A seventh signal corresponding to the detection result of the outlet detection sensor 48a is input to the seventh buffer 122g. In this case, the main CPU 63 outputs a LOW level seventh signal when the outlet detection sensor 48a does not detect a new gaming ball, and outputs a HI level seventh signal for a specific period when the outlet detection sensor 48a detects one gaming ball. This specific period is a period sufficient for the management CPU 112 to determine that a HI level seventh signal has been input to the seventh buffer 122g.

[0235] An eighth signal corresponding to whether or not the open / close execution mode is in progress is input to the eighth buffer 122h. In this case, the main CPU 63 continuously outputs the eighth signal at a low level when the open / close execution mode is not in progress, and continuously outputs the eighth signal at a high level when the open / close execution mode is in progress.

[0236] A ninth signal corresponding to whether or not the high frequency support mode is in effect is input to the ninth buffer 122i. In this case, the primary CPU 63 continuously outputs a LOW level ninth signal when the high frequency support mode is not in effect, and continuously outputs a HI level ninth signal when the high frequency support mode is in effect.

[0237] A 10th signal corresponding to whether or not the front door frame 14 is open during the period is input to the 10th buffer 122j. In this case, the main CPU 63 continuously outputs a 10th signal at a LOW level when the front door frame 14 is in the closed state, and continuously outputs a 10th signal at a HI level when the front door frame 14 is in the open state.

[0238] A 11th signal corresponding to whether or not a game round has started is input to the 11th buffer 122k. In this case, the main CPU 63 continuously outputs a 11th signal at a LOW level until the game round starts, and outputs a 11th signal at a HI level for a specific period when the game round starts. This specific period is long enough for the management CPU 112 to identify that a HI level 11th signal is input to the 11th buffer 122k.

[0239] A setting value update signal for causing the management CPU 112 to recognize that a new setting of the setting state of the pachinko machine 10 has been made by the main CPU 63 is input to the 15th buffer 122o. In this case, the main CPU 63 outputs a LOW level setting value update signal when no new setting of the setting state of the pachinko machine 10 has been made, and outputs a pulse signal in which a HI level setting value update signal is maintained for a specific period for several minutes corresponding to the newly set setting value when a new setting of the setting state of the pachinko machine 10 has been made. This specific period is long enough for the management CPU 112 to identify that a HI level setting value update signal is input to the 15th buffer 122o.

[0240] An output instruction signal for causing the management-side CPU 112 to recognize an opportunity to output the history information stored in the history memory 117 and various parameters stored in the operation result memory 131 to the read terminal 68d is input to the 16th buffer 122p. In this case, the main-side CPU 63 outputs a LOW-level output instruction signal when there is no need to output the history information, and outputs a HI-level output instruction signal for a specific period when it is necessary to output the history information. This specific period is sufficient for the management-side CPU 112 to identify that a HI-level output instruction signal is input to the 16th buffer 122p.

[0241] Although the 12th buffer 122l, the 13th buffer 122m, and the 14th buffer 122n can receive signals from the main-side CPU 63, they are blank and do not receive normal signals in the pachinko machine 10. As described above, since a larger number of buffers 122a to 122p are provided as the input ports 121 of the management-side I / F 111 than the types of signals output from the main-side CPU 63 to the management IC 66 in the pachinko machine 10, the management IC 66 can be used in models different from the pachinko machine 10. This makes it possible to enhance the versatility of the management IC 66. Incidentally, signal paths 118a to 118p are formed between the main-side CPU 63 and each of the 1st to 16th buffers 122a to 122p so as to correspond one-to-one to the 1st to 16th buffers 122a to 122p, but it is not limited thereto, and a configuration may be adopted in which signal paths 118l to 118n are not formed between the buffers 122l to 122n to be blanked.

[0242] The fact that a set value update signal is input to the fifteenth buffer 122o and that an output instruction signal is input to the sixteenth buffer 122p was determined in the design stage of the management IC 66, and the management CPU 112 can determine that a set value update signal is input to the fifteenth buffer 122o and that an output instruction signal is input to the sixteenth buffer 122p without receiving an instruction from the main CPU 63. On the other hand, the types of signals that are input to the first to fourteenth buffers 122a to 122n were not determined in the design stage of the management IC 66, and the types of these signals are identified by the management CPU 112 upon receiving an instruction from the main CPU 63. The identification of the types of these signals by the management CPU 112 is performed by transmitting a type identification command from the main CPU 63 to the management CPU 112 when control is started in the main CPU 63 and the management CPU 112 following the start of supply of operating power to the MPU 62, as will be described in detail later. In this case, the information on the types of various signals provided by the type identification command is stored in the correspondence memory 116, and when the management CPU 112 identifies the types of various signals while operating power is being supplied, the information stored in the correspondence memory 116 is referenced.

[0243] 20 is an explanatory diagram for explaining the configuration of the correspondence memory 116. The correspondence memory 116 is provided with first to fourteenth correspondence areas 123a to 123n in one-to-one correspondence with the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management side I / F 111.

[0244] In the first correspondence area 123a, information indicating that it is the general winning port 31 is stored as information for the management-side CPU 112 to identify the type of signal input to the first buffer 122a. Further, in the first correspondence area 123a, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored. In the second correspondence area 123b, information indicating that it is the general winning port 31 is stored as information for the management-side CPU 112 to identify the type of signal input to the second buffer 122b. Further, in the second correspondence area 123b, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored. In the third correspondence area 123c, information indicating that it is the general winning port 31 is stored as information for the management-side CPU 112 to identify the type of signal input to the third buffer 122c. Further, in the third correspondence area 123c, information indicating that it is the general winning port 31 and information on the number of game balls (10) to be paid out when one game ball enters the general winning port 31 are also stored.

[0245] In the fourth correspondence area 123d, information indicating that it is the special electric winning device 32 is stored as information for the management-side CPU 112 to identify the type of signal input to the fourth buffer 122d. Further, in the fourth correspondence area 123d, information indicating that it is the special electric winning device 32 and information on the number of game balls paid out when one game ball enters the special electric winning device 32 (15 balls) are also stored. In the fifth correspondence area 123e, information indicating that it is the first operation port 33 is stored as information for the management-side CPU 112 to identify the type of signal input to the fifth buffer 122e. Further, in the fifth correspondence area 123e, information indicating that it is the first operation port 33 and information on the number of game balls paid out when one game ball enters the first operation port 33 (1 ball) are also stored. In the sixth correspondence area 123f, information indicating that it is the second operation port 34 is stored as information for the management-side CPU 112 to identify the type of signal input to the sixth buffer 122f. Further, in the sixth correspondence area 123f, information indicating that it is the second operation port 34 and information on the number of game balls paid out when one game ball enters the second operation port 34 (1 ball) are also stored. In the seventh correspondence area 123g, information indicating that it is the out port 24a is stored as information for the management-side CPU 112 to identify the type of signal input to the seventh buffer 122g.

[0246] In the eighth correspondence area 123h, information indicating that it is the opening / closing execution mode is stored as information for the management-side CPU 112 to identify the type of signal input to the eighth buffer 122h. In the ninth correspondence area 123i, information indicating that it is the high-frequency support mode is stored as information for the management-side CPU 112 to identify the type of signal input to the ninth buffer 122i. In the tenth correspondence area 123j, information indicating that it is the front door frame 14 is stored as information for the management-side CPU 112 to identify the type of signal input to the tenth buffer 122j. In the eleventh correspondence area 123k, information indicating the start of a game round is stored as information for the management-side CPU 112 to identify the type of signal input to the eleventh buffer 122k.

[0247] In the 12th correspondence relation area 123l, information indicating that it is a blank that does not correspond to any information for specifying, by the management-side CPU 112, the type of signal input to the 12th buffer 122l is stored. In the 13th correspondence relation area 123m, information indicating that it is a blank that does not correspond to any information for specifying, by the management-side CPU 112, the type of signal input to the 13th buffer 122m is stored. In the 14th correspondence relation area 123n, information indicating that it is a blank that does not correspond to any information for specifying, by the management-side CPU 112, the type of signal input to the 14th buffer 122n is stored.

[0248] As described above, by adopting a configuration in which the management-side CPU 112 specifies, upon receiving an instruction from the main-side CPU 63, what types of signals are input to the 1st to 14th buffers 122a to 122n, the management IC 66 can be used for different models from this pachinko machine 10. Thereby, it becomes possible to enhance the versatility of the management IC 66.

[0249] Also, instead of outputting information for recognizing the type of the signal each time a signal output corresponding to the storage of history information is performed to the 1st to 14th buffers 122a to 122n, information for recognizing the type of the signal is output in advance, and information for specifying, by the management-side CPU 112, the type of signal input to the 1st to 14th buffers 122a to 122n based on the output information is stored in the correspondence relation memory 116. Thereby, compared with a configuration in which information for recognizing the type of the signal is output each time a signal output corresponding to the storage of history information is performed to the 1st to 14th buffers 122a to 122n, it becomes possible to suppress the amount of information output from the main-side CPU 63 to the management-side CPU 112 at the time of each signal output.

[0250] Furthermore, the information for specifying the types of signals input to the first to fourteenth buffers 122a to 122n by the management CPU 112 is output when the supply of operating power starts. This allows the management CPU 112 to specify the types of signals input to the first to fourteenth buffers 122a to 122n when a game is started in the pachinko machine 10.

[0251] Furthermore, the information that a setting value update signal is input to the 15th buffer 122o and the information that an output instruction signal is input to the 16th buffer 122p are set during the design stage of the management IC 66. This makes it possible to omit the process for identifying the type of signal input to the 15th buffer 122o and the 16th buffer 122p for the setting value update signal and output instruction signal, which are reliably used not only in this pachinko machine 10 but also in other models of pachinko machines that use the management IC 66. This makes it possible to reduce the processing load for the process for identifying the type of such signal.

[0252] Next, a description will be given of the history memory 117 of the management IC 66. FIG.

[0253] The history memory 117 is provided with a history area 124 for sequentially storing history information. In the history area 124, a plurality of pointer information is set in serial numbers, and a history information storage area 125 is set in one-to-one correspondence with each piece of pointer information. The history information storage area 125 can store a combination of RTC information and correspondence relationship information. In this case, each history information storage area 125 has a data capacity of 2 bytes, a data capacity of 1 byte is allocated as an area for storing RTC information, and a data capacity of 1 byte is allocated as an area for storing correspondence relationship information. When it is necessary to store the correspondence relationship information according to the signals input to the first to fourteenth buffers 122a to 122n (in the case of this pachinko machine 10, actually the first to eleventh buffers 122a to 122k), first, the current RTC115 measures the date and time information in the area for storing the RTC information of the history information storage area 125 corresponding to the pointer information that is the current write target. Then, the correspondence relationship information corresponding to the buffers 122a to 122n that triggered this information storage is read from the correspondence relationship areas 123a to 123n corresponding to the buffers 122a to 122n in the correspondence relationship memory 116, and the read correspondence relationship information is stored in the area for storing the correspondence relationship information of the history information storage area 125 corresponding to the pointer information that is the current write target.

[0254] Specifically, regarding the correspondence information stored in the history information storage area 125, since signals corresponding to the detection results of the ball entry detection sensors 42a to 48a are input to the first to seventh buffers 122a to 122g as already described, information corresponding to the types of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g in the correspondence memory 116. More specifically, information corresponding to the types of the ball entry parts corresponding to each of the ball entry detection sensors 42a to 48a is stored in the first to seventh correspondence areas 123a to 123g. In this pachinko machine 10, as already described, since the first to third winning port detection sensors 42a to 44a all detect the game balls that have entered the general winning port 31, information indicating that it is the general winning port 31 is stored in the first to third correspondence areas 123a to 123c corresponding to these first to third winning port detection sensors 42a to 44a. Also, information indicating that it is the special electric winning device 32 is stored in the fourth correspondence area 123d, information indicating that it is the first operating port 33 is stored in the fifth correspondence area 123e, information indicating that it is the second operating port 34 is stored in the sixth correspondence area 123f, and information indicating that it is the out port 24a is stored in the seventh correspondence area 123g. When the buffers 122a to 122n that triggered this information storage are any of the first to seventh buffers 122a to 122g, information on the type of the ball entry part corresponding to that buffer 122a to 122g is read from any of the first to seventh correspondence areas 123a to 123g, and the read information on the type of the ball entry part is stored as it is in the area for storing the correspondence information in the history information storage area 125.

[0255] On the one hand, a signal indicating whether the eighth buffer 122h is in the open / close execution mode is input, a signal indicating whether the ninth buffer 122i is in the high-frequency support mode is input, a signal indicating whether the front door frame 14 is open is input to the tenth buffer 122j, and a signal indicating whether a game round has started is input to the eleventh buffer 122k. Therefore, information indicating that it is in the open / close execution mode is stored in the eighth corresponding relationship area 123h, information indicating that it is in the high-frequency support mode is stored in the ninth corresponding relationship area 123i, information indicating that it is the front door frame 14 is stored in the tenth corresponding relationship area 123j, and information indicating that it is a game round is stored in the eleventh corresponding relationship area 123k.

[0256] As described above, the main CPU 63 continuously outputs the eighth signal at the LOW level in a situation where it is not in the open / close execution mode, and continuously outputs the eighth signal at the HI level in a situation where it is in the open / close execution mode. Therefore, the management CPU 112 can specify that the open / close execution mode has started when the eighth signal changes from the LOW level to the HI level, and can specify that the open / close execution mode has ended when the eighth signal changes from the HI level to the LOW level. And in both cases where the eighth signal changes from the LOW level to the HI level and from the HI level to the LOW level, the management CPU 112 specifies that an opportunity to store the corresponding relationship information in the history information storage area 125 has occurred. That is, when the eighth signal changes from the LOW level to the HI level, not only the information indicating that it is in the open / close execution mode read from the eighth corresponding relationship area 123h but also the start information is stored together in the area for storing the corresponding relationship information in the history information storage area 125. Also, when the eighth signal changes from the HI level to the LOW level, not only the information indicating that it is in the open / close execution mode read from the eighth corresponding relationship area 123h but also the end information is stored together in the area for storing the corresponding relationship information in the history information storage area 125.

[0257] As already explained, the main CPU 63 continuously outputs the ninth signal at a low level when the high-frequency support mode is not active, and continuously outputs the ninth signal at a high level when the high-frequency support mode is active. This allows the management CPU 112 to determine that the high-frequency support mode has started when the ninth signal changes from a low level to a high level, and to determine that the high-frequency support mode has ended when the ninth signal changes from a high level to a low level. When the ninth signal changes from a low level to a high level, or when it changes from a high level to a low level, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the ninth signal changes from a low level to a high level, not only the information indicating the high-frequency support mode read from the ninth correspondence area 123i but also the start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the ninth signal changes from HI level to LOW level, not only the information indicating the high frequency support mode read from the ninth correspondence area 123i but also the termination information are stored in an area for storing correspondence information in the history information storage area 125.

[0258] As already explained, the main CPU 63 continuously outputs a LOW-level tenth signal when the front door frame 14 is closed, and continuously outputs a HI-level tenth signal when the front door frame 14 is open. Therefore, the management CPU 112 determines that the front door frame 14 is open when the tenth signal changes from a LOW level to a HI-level, and determines that the front door frame 14 is closed when the tenth signal changes from a HI-level to a LOW-level. When the tenth signal changes from a LOW level to a HI-level, or when it changes from a HI-level to a LOW-level, the management CPU 112 determines that an opportunity to store correspondence information in the history information storage area 125 has occurred. In other words, when the tenth signal changes from a LOW level to a HI-level, not only the information indicating the front door frame 14 read from the tenth correspondence area 123j but also the opening start information are stored in the area for storing correspondence information in the history information storage area 125. In addition, when the 10th signal changes from HI level to LOW level, not only the information indicating that it is the front door frame 14 read from the 10th correspondence relationship area 123j but also the opening completion information are stored in an area for storing correspondence relationship information in the history information storage area 125.

[0259] As already explained, the main CPU 63 continues to output a LOW level 11th signal until the start timing of a game round arrives, and when the start timing of a game round arrives, it outputs a HI level 11th signal for a specific period of time. Therefore, the management CPU 112 determines that a game round has started when the 11th signal changes from a LOW level to a HI level. In other words, when the 11th signal changes from a LOW level to a HI level, information indicating that this is a game round read from the 11th correspondence area 123k is stored in an area for storing correspondence information in the history information storage area 125.

[0260] The history information storage area 125 is provided with a capacity sufficient to store all the history information generated during a continuous business operation period of 10 days, even if the pachinko machine 10 continuously launches game balls from opening to closing. For example, if 60,000 pieces of history information are generated in one day, more than 600,000 history information storage areas 125 are provided. Thus, it is possible to store and hold all the history information in the history memory 117 for at least 10 days.

[0261] In the history memory 117, a pointer area 126 is provided separately from the history area 124. The pointer area 126 stores information for the management CPU 112 to identify the pointer information that is currently the write target in the history memory 117. Specifically, at the time of shipment of the pachinko machine 10, information designating the pointer information of "0" as the write target is set in the pointer area 126. Then, each time one piece of history information is newly stored in the history information storage area 125, the information in the pointer area 126 is updated so that the value of the pointer information of the write target is incremented by 1. When the last-order pointer information becomes the write target and the history information is stored in the history information storage area 125 corresponding to the last-order pointer information, the information in the pointer area 126 is updated so that the pointer information of "0" becomes the write target. Thus, when a storage trigger for history information occurs beyond the number of storable history information, the old history information is overwritten by the new history information in order from the history information storage area 125 where the old history information is stored.

[0262] Also, when the external device reads the history information from the history memory 117, all the history information storage areas 125 are cleared to "0", and the information in the pointer area 126 is updated so that the pointer information of "0" becomes the write target. This makes it possible to prevent the history information that has once been the read target from becoming the read target again.

[0263] Next, a specific processing configuration for managing game history using the management IC 66 will be described. First, a processing configuration for storing information on the correspondence relationship between the first to fourteenth buffers 122a to 122n provided in the input port 121 of the management-side I / F 111 and the signal types in the correspondence relationship memory 116 will be described. FIG. 22 is a flowchart showing the recognition processing executed by the main CPU 63. Note that the recognition processing is executed in step S111 in the main processing (FIG. 9).

[0264] First, "14" is set in the recognition output counter provided in the main RAM 65 (step S801). The recognition output counter is a counter for the main CPU 63 to specify the remaining required number of times of information output for allowing the management-side CPU 112 to recognize which types of signals the first to fourteenth buffers 122a to 122n in the input port 121 of the management-side I / F 111 correspond to. Since the 14 first to fourteenth buffers 122a to 122n are the recognition targets of the signal types as already described, "14" is set in the recognition output counter.

[0265] Thereafter, an output process of an identification start command is executed (step S802). The primary CPU 63 outputs various commands to the management CPU 112 to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n correspond to. When outputting these commands, the first to eighth signals input to the first to eighth buffers 122a to 122h are used. That is, the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h) used to instruct the management CPU 112 to store history information are used to output commands to make the management CPU 112 recognize which types of signals the first to fourteenth buffers 122a to 122n correspond to. This makes it possible to reduce the number of signal paths and simplify the configuration compared to a configuration in which a signal path for outputting the commands is provided separately from the signal paths 118a to 118p for outputting signals to the first to sixteenth buffers 122a to 122p. The identification start command has a data capacity of 8 bits, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Furthermore, in the output process of the identification start command, the output state of the ninth signal is switched to HI level at the timing when the output of the identification start command is started so that the management CPU 112 recognizes that a new command has been sent. Furthermore, the output period of the identification start command and the period during which the output state of the ninth signal is maintained at HI level are set to be long enough for the management CPU 112 to recognize the identification start command and the output state of the ninth signal. By receiving the identification start command, the management CPU 112 determines that it should start processing to store information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence memory 116.

[0266] Thereafter, a type identification command corresponding to the current value of the recognition output counter in the main RAM 65 is read from the main ROM 64 (step S803). In this case, the first buffer 122a is the first to be set as the signal type, and thereafter, the (n+1)th buffer is set as the signal type, so that recognition setting of the signal types corresponding to the first to fourteenth buffers 122a to 122n is performed. Therefore, if the recognition output counter is "14" to "12", a type identification command indicating that it is the general winning port 31 and the number of prize balls therein is read out; if the recognition output counter is "11", a type identification command indicating that it is the special winning device 32 and the number of prize balls therein is read out; if the recognition output counter is "10", a type identification command indicating that it is the first operating port 33 and the number of prize balls therein is read out; if the recognition output counter is "9", a type identification command indicating that it is the second operating port 34 and the number of prize balls therein is read out; if the recognition output counter is "8", a type identification command indicating that it is the outlet 31 is read out; If the recognition output counter is "7", a type identification command indicating that it is in the open / close execution mode is read out; if the recognition output counter is "6", a type identification command indicating that it is in the high frequency support mode is read out; if the recognition output counter is "5", a type identification command indicating that it is the front door frame 14 is read out; if the recognition output counter is "4", a type identification command indicating that it is a game play; if the recognition output counter is "3" to "1", a type identification command indicating that it is blank is read out.

[0267] Thereafter, the control unit 112 executes an output process of the read type identification command (step S804). The type identification command, like the identification start command, has an 8-bit data capacity, and each bit of data is input to the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. In the output process of the identification type command, the control unit 112 switches the output state of the ninth signal to HI level at the timing when output of the identification type command starts to make the control CPU 112 recognize that a new command has been sent. In addition, the output period of the identification type command and the period during which the output state of the ninth signal is maintained at HI level are set to a period sufficient for the control CPU 112 to recognize the output states of the identification type command and the ninth signal. By receiving the identification type command, the control CPU 112 stores information corresponding to the identification type command in the correspondence areas 123a to 123n corresponding to the buffer currently being set among the first to fourteenth buffers 122a to 122n.

[0268] Thereafter, the value of the recognition output counter in the main RAM 65 is decremented by 1 (step S805), and it is determined whether the value of the recognition output counter after decrementing by 1 is "0" (step S806). If the value of the recognition output counter is 1 or more (step S806: NO), processing is executed to output a type identification command corresponding to the value of the recognition output counter after decrementing by 1 (steps S803 and S804).

[0269] On the other hand, when the value of the recognition output counter is "0" (step S806: YES), the output process of the identification end command is executed (step S807). The identification end command has a data capacity of 8 bits, and the data of each bit is input into the first to eighth buffers 122a to 122h as the first to eighth signals, respectively. Also, in the output process of the identification end command, in order to let the management-side CPU 112 recognize that a new command has been transmitted, the output state of the ninth signal is switched to the HI level at the timing of starting the output of the identification end command. Also, the output period of the identification end command and the period for maintaining the output state of the ninth signal at the HI level are set to a period sufficient for the management-side CPU 112 to recognize these identification end command and the output state of the ninth signal. By receiving the identification end command, the management-side CPU 112 specifies that the process for storing the information on the correspondence between the first to fourteenth buffers 122a to 122n and the signal types in the correspondence memory 116 is completed.

[0270] Next, the management process executed by the management-side CPU 112 will be described with reference to the flowchart of FIG. 23. The management process starts when the supply of operating power to the management-side CPU 112 is started. Note that the processing speed of the management-side CPU 112 is configured to be faster than the processing speed of the main-side CPU 63, and the combination of the processes after step S908 in the management process is executed 16 times or more from the start of one timer interrupt process (FIG. 11) in the main-side CPU 63 until the start of the next timer interrupt process (FIG. 11).

[0271] First, it is determined whether or not an identification start command has been received from the main-side CPU 63 (step S901). If the identification start command has not been received (step S901: NO), after executing the setting update recognition process (step S902), the process returns to step S901. In the setting update recognition process, although details will be described later, when a new setting of the setting state of the pachinko machine 10 is made by the main-side CPU 63, corresponding processing is executed.

[0272] When an identification start command is received from the main CPU 63 (step S901: YES), the value of a setting target counter provided in the control RAM 114 is cleared to "0" (step S903). The setting target counter is a counter that allows the control CPU 112 to identify the type of buffers 122a to 122n for which a signal type is to be set. The first buffer 122a is the first to be set as a signal type, and thereafter the nth buffer and then the (n+1)th buffer are set as signal type settings.

[0273] Thereafter, on the condition that a type identification command has been received from the main CPU 63 (step S904: YES), a correspondence setting process is executed (step S905). In the correspondence setting process, information on the signal type set in the currently received type identification command is stored in the correspondence area corresponding to the current value of the setting target counter in the control RAM 114, among the first to fourteenth correspondence areas 123a to 123n of the correspondence memory 116. Thereafter, the value of the setting target counter in the control RAM 114 is incremented by 1 (step S906).

[0274] If a negative determination is made in step S904, or if the processing of step S906 is executed, it is determined (step S907) whether or not an identification end command has been received from the main CPU 63. If an identification end command has not been received (step S907: NO), the process returns to step S904, and the processing of steps S905 and S906 is executed again on the condition that a new type identification command is received from the main CPU 63 (step S904: YES).

[0275] If an identification end command has been received from the main CPU 63 (step S907: YES), the processes of steps S908 to S910 are repeatedly executed. In step S908, details of which will be described later are executed, a history setting process is executed for storing history information corresponding to the type of signal received from the main CPU 63 in the history memory 117. In step S909, details of which will be described later are executed, a display output process is executed for calculating various parameters using the history information stored in the history memory 117 and notifying the first to third notification display devices 69a to 69c of the calculation results. In step S910, details of which will be described later are executed, an external output process is executed for outputting the history information stored in the history memory 117 and the various parameters stored in the calculation result memory 131 to the read terminal 68d.

[0276] Fig. 24 is a time chart showing how information on the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n is stored in the correspondence memory 116. Fig. 24(a) shows a period during which commands are output from the main CPU 63 to the control CPU 112 using the first to eighth signals (i.e., the first to eighth signal paths 118a to 118h), Fig. 24(b) shows a period during which the output state of the ninth signal is at HI level, Fig. 24(c) shows an execution period of an identification state during which processing is executed to identify the correspondence between the first to fourteenth buffers 122a to 122n and the types of signals input to these buffers 122a to 122n, and Fig. 24(d) shows the timing at which the correspondence setting process (step S905) is executed by the control CPU 112.

[0277] When the supply of operating power to the main CPU 63 and the management CPU 112 is started, the output of the identification start command using the first to eighth signals starts at the timing of t1 as shown in Fig. 24(a). Also, at the timing of t1, the output state of the ninth signal is changed from the LOW level to the HI level as shown in Fig. 24(b). Then, at the timing of t2 when the output of the identification start command is continuing, the output state of the ninth signal is changed from the HI level to the LOW level as shown in Fig. 24(b). The management CPU 112 identifies that a command is being transmitted from the main CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification start command is being received, the management CPU 112 enters the identification state by making an affirmative determination in step S901 of the management process (Fig. 23). Then, at the timing of t3, the output of the identification start command stops as shown in Fig. 24(a).

[0278] Thereafter, at the timing of t4, as shown in FIG. 24(a), the output of the first type identification command using the first to eighth signals is started. Also, at the timing of t4, as shown in FIG. 24(b), the output state of the ninth signal is changed from the LOW level to the HI level. Thereafter, at the timing of t5 when the output of the type identification command is continuing, as shown in FIG. 24(b), the output state of the ninth signal is changed from the HI level to the LOW level. The management-side CPU 112 identifies that a command has been transmitted from the main-side CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main-side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the first type identification command is being received, the management-side CPU 112 executes the correspondence relationship setting process as shown in FIG. 24(d) at the timing of t5. In the correspondence relationship setting process, information indicating that it is the general winning port 31 and information on the number of winning balls are stored in the first correspondence area 123a of the correspondence relationship memory 116. Thereafter, at the timing of t6, as shown in FIG. 24(a), the output of the type identification command is stopped.

[0279] Thereafter, at each of the timings from t7 to t9, from t10 to t12, from t13 to t15, and from t16 to t18, similar to the timings from t4 to t6, the management-side CPU 112 executes the correspondence relationship setting process corresponding to the type identification command output from the main-side CPU 63. In this case, at the timings from t16 to t18, the correspondence relationship setting process corresponding to the 14th type identification command is completed.

[0280] After that, at the timing of t19, as shown in FIG. 24(a), the output of the identification end command using the first to eighth signals is started. Also, at the timing of t19, as shown in FIG. 24(b), the output state of the ninth signal is changed from the LOW level to the HI level. Then, at the timing of t20 when the output of the identification end command is continuing, as shown in FIG. 24(b), the output state of the ninth signal is changed from the HI level to the LOW level. The management-side CPU 112 identifies that a command has been transmitted from the main-side CPU 63 by confirming that the output state of the ninth signal has changed from the HI level to the LOW level, and grasps the content of the command received from the main-side CPU 63 by checking the information in the first to eighth buffers 122a to 122h. In this case, since the identification end command is being received, the identification state of the management-side CPU 112 ends as shown in FIG. 24(c) at the timing of t20. After that, at the timing of t21, the output of the identification end command is stopped as shown in FIG. 24(a).

[0281] By having a configuration that allows the management-side CPU 112 to recognize whether or not a command is being output using the ninth signal as described above, even in a configuration where command output is performed using the first to eighth signals (i.e., the first to eighth signal paths) that are used to instruct the management-side CPU 112 of the opportunity to store history information, it becomes possible to clearly make the management-side CPU 112 recognize that a command is being output.

[0282] Next, a processing configuration for storing the history information in the history memory 117 will be described. FIG. 25 is a flowchart showing the management output processing executed by the main-side CPU 63. Note that the management output processing is executed in step S319 in the timer interrupt processing (FIG. 11).

[0283] First, set "11" in the counter to be managed provided in the main-side RAM 65 (step S1001). The counter to be managed is a counter for the main-side CPU 63 to identify whether there is a management target that is not the target to be identified for changing the signal output state to the management-side CPU 112 in the current management output process, and to identify for which management target the signal output state to the management-side CPU 112 should be changed. In one management output process, the management targets for the main-side CPU 63 to identify whether the signal output state to the management-side CPU 112 should be changed are a total of 11, including the seven ball-in detection sensors 42a to 48a, the presence or absence of execution of the opening / closing execution mode, the presence or absence of execution of the high-frequency support mode, the presence or absence of opening / closing of the front door frame 14, and the presence or absence of start of a game round. Therefore, first set "11" in the counter to be managed.

[0284] Thereafter, it is determined whether the output state of the signal to the management-side CPU 112 for the management target corresponding to the current value of the counter to be managed is at the HI level (step S1002). If it is not at the HI level (step S1002: NO), it is determined whether the value of the counter to be managed is 5 or more, thereby identifying whether the management target corresponding to the value of the counter to be managed is any of the seven ball-in detection sensors 42a to 48a (step S1003).

[0285] When an affirmative determination is made in step S1003, it is determined whether or not "1" is set in the output flag of the main-side RAM 65 corresponding to the value of the counter to be managed (step S1004). Specifically, when the value of the counter to be managed is "11" and corresponds to the first winning port detection sensor 42a, it is determined whether or not "1" is set in the first output flag. When the value of the counter to be managed is "10" and corresponds to the second winning port detection sensor 43a, it is determined whether or not "1" is set in the second output flag. When the value of the counter to be managed is "9" and corresponds to the third winning port detection sensor 44a, it is determined whether or not "1" is set in the third output flag. When the value of the counter to be managed is "8" and corresponds to the special power detection sensor 45a, it is determined whether or not "1" is set in the fourth output flag. When the value of the counter to be managed is "7" and corresponds to the first operation port detection sensor 46a, it is determined whether or not "1" is set in the fifth output flag. When the value of the counter to be managed is "6" and corresponds to the second operation port detection sensor 47a, it is determined whether or not "1" is set in the sixth output flag. When the value of the counter to be managed is "5" and corresponds to the out port 24a, it is determined whether or not "1" is set in the seventh output flag. Note that, as already described, "1" is set in these first to seventh output flags in the ball entry detection process (Figure 15).

[0286] When "1" is set in the output flag corresponding to the value of the counter to be managed (step S1004: YES), the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals is set to the HI level (step S1005). Thereafter, the output flag corresponding to the value of the counter to be managed is cleared to "0" (step S1006).

[0287] When a negative determination is made in step S1003, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the HI level (step S1007). Specifically, when the value of the counter to be managed is "4", it is determined whether a transition to the opening / closing execution mode has occurred. When the value of the counter to be managed is "3", it is determined whether a transition to the high-frequency support mode has occurred. When the value of the counter to be managed is "2", it is determined whether the front door frame 14 has been opened. When the value of the counter to be managed is "1", it is determined whether the game round has started by determining whether "1" is set in the 11th output flag. When an affirmative determination is made in step S1007, the output state of the signal corresponding to the value of the counter to be managed is set to the HI level (step S1008). When the process of step S1008 is executed when the value of the counter to be managed is "1", the 11th output flag is cleared to "0".

[0288] When a positive determination is made in step S1002, it is determined whether an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the LOW level (step S1009). Specifically, when the value of the counter to be managed is 5 or more or "1" and the current management target is any of the ball entry detection sensors 42a to 48a or the start of a game round, it is determined whether the output state of the signal corresponding to the value of the counter to be managed among the first to seventh signals and the eleventh signal has been switched from the LOW level to the HI level and then the HI output duration (specifically, 10 milliseconds) has elapsed. This HI output duration is set to a period longer than the longest processing interval of the history setting process (step S908) of the management process (Figure 23) in the management-side CPU 112, and it is a period during which the management-side CPU 112 can surely identify the output state of the signal switched from the LOW level to the HI level. Also, when the value of the counter to be managed is "4" and the current management target is the open / close execution mode, it is determined whether the open / close execution mode has ended. When the value of the counter to be managed is "3" and the current management target is the high-frequency support mode, it is determined whether the high-frequency support mode has ended. When the value of the counter to be managed is "2" and the current management target is the front door frame 14, it is determined whether the front door frame 14 is in the closed state. When an opportunity has occurred to switch the output state of the signal corresponding to the value of the counter to be managed to the LOW level (step S1009: YES), the output state of the signal corresponding to the value of the counter to be managed is set to the LOW level (step S1010).

[0289] When a negative determination is made in step S1004, when the process of step S1006 is executed, when a negative determination is made in step S1007, when the process of step S1008 is executed, when a negative determination is made in step S1009, or when the process of step S1010 is executed, the value of the management target counter in the main side RAM 65 is decremented by 1 (step S1011). Then, it is determined whether the value of the management target counter after the decrement by 1 is "0" (step S1012). If the value of the management target counter is 1 or more (step S1012: NO), for the management target corresponding to the new value of the management target counter, the processes after step S1002 are executed.

[0290] Next, the history setting process executed by the management side CPU 112 will be described with reference to the flowchart of FIG. 26. The history setting process is executed in step S908 of the management process (FIG. 23).

[0291] First, the number of buffers to be confirmed in the management side CPU 112 among the first to fourteenth buffers 122a to 122n is set in the confirmation target counter provided in the management side RAM 114 (step S1101). Specifically, the number of correspondence relation areas in which information other than the information indicating blank is stored among the first to fourteenth correspondence relation areas 123a to 123n in the correspondence relation memory 116 is specified, and the information of the specified number is set in the confirmation target counter. In this pachinko machine 10, as already described, information other than the information indicating blank is stored in the first to eleventh correspondence relation areas 123a to 123k. Therefore, in step S1101, "11" is set in the confirmation target counter.

[0292] Thereafter, by checking whether the numerical information stored in the buffer corresponding to the value of the current confirmation target counter among the first to fourteenth buffers 122a to 122n has been changed from "0" to "1", it is determined whether the output state of the input signal from the master CPU 63 to the buffer has been switched from the LOW level to the HI level (step S1102). When the value of the confirmation target counter is "n", the nth buffer 122a to 122n is the target for checking the numerical information. For example, if the value of the confirmation target counter is "11", the 11th buffer 122k is the target for checking the numerical information, and if the value of the confirmation target counter is "5", the 5th buffer 122e is the target for checking the numerical information.

[0293] If an affirmative determination is made in step S1102, RTC information, which is the year / month / day information and time information, is read from RTC 115 (step S1103). Then, a writing process to the history memory 117 is executed (step S1104). In this writing process, by referring to the pointer area 126 of the history memory 117, the pointer information of the history area 124 that is currently the writing target is specified, and the RTC information read in step S1103 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information that is the writing target. Also, correspondence information is read from the correspondence areas 123a to 123n corresponding to the value of the current confirmation target counter, and the correspondence information is written to the history information storage area 125 corresponding to the pointer information that is the writing target. Further, when the correspondence information is any one of the information indicating the open / close execution mode, the information indicating the high-frequency support mode, and the information indicating the front door frame 14, not only the correspondence information but also start information is written to the history information storage area 125 corresponding to the pointer information that is the writing target. Note that when the value of the confirmation target counter is "n", the nth correspondence areas 123a to 123n are the reading targets of the correspondence information. For example, if the value of the confirmation target counter is "11", the 11th correspondence area 123k is the reading target of the correspondence information, and if the value of the confirmation target counter is "5", the 5th correspondence area 123e is the reading target of the correspondence information.

[0294] When the writing process is executed as described above, if the value of the confirmation target counter is any one of the output port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the game turn, a combination of the RTC information and the correspondence information indicating that it is any one of the output port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, the second operation port 34, and the game turn is stored as history information in the history information storage area 125 corresponding to the pointer information that is the writing target. Further, if the value of the confirmation target counter is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, a combination of the RTC information, the correspondence information indicating that it is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, and the start information is stored as history information in the history information storage area 125 corresponding to the pointer information that is the writing target.

[0295] Thereafter, an update process for the target pointer is executed (step S1105). In the update process, the numerical information stored in the pointer area 126 of the history memory 117 is read out and incremented by 1. It is determined whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment of 1 is overwritten in the pointer area 126 as the new writing target pointer information. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the writing target pointer information becomes the first pointer information.

[0296] When a negative determination is made in step S1102 or when the process of step S1105 is executed, it is determined whether corresponding correspondence information to be checked for whether the signal output has been switched to the LOW level is stored in the correspondence area 123a to 123n corresponding to the value of the current confirmation target counter (step S1106). Specifically, when the value of the current confirmation target counter is from "8" to "10", since any one of the information indicating the open / close execution mode, the information indicating the high-frequency support mode, and the information indicating the front door frame 14 is stored in the corresponding correspondence areas 123h to 123j, an affirmative determination is made in step S1106.

[0297] When an affirmative determination is made in step S1106, it is determined whether or not the numerical information stored in the buffer corresponding to the value of the current confirmation target counter among the first to fourteenth buffers 122a to 122n has been changed from "1" to "0", thereby determining whether or not the output state of the input signal from the host CPU 63 to the buffer has been switched from the HI level to the LOW level (step S1107). When an affirmative determination is made in step S1107, the RTC information is read out in the same manner as in step S1103 (step S1108), and further, a writing process to the history memory 117 is executed (step S1109). In the writing process, the RTC information read out in step S1108 is written into the history information storage area 125 of the history area 124 corresponding to the pointer information to be written. Also, the correspondence information is read out from the correspondence areas 123a to 123n corresponding to the value of the current confirmation target counter, and the correspondence information is written into the history information storage area 125 corresponding to the pointer information to be written. Further, not only the correspondence information but also the end information is written into the history information storage area 125 corresponding to the pointer information to be written. By executing the writing process in this way, when the value of the confirmation target counter is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, the RTC information, the correspondence information indicating that it is any one of the opening / closing execution mode, the high-frequency support mode, and the front door frame 14, and the end information are stored as a combination as the history information in the history information storage area 125 corresponding to the pointer information to be written. Thereafter, the update process of the target pointer is executed in the same manner as in step S1105 (step S1110).

[0298] When a negative determination is made in step S1106, when a negative determination is made in step S1107, or when the process of step S1110 is executed, the value of the confirmation target counter in the management side RAM 114 is decremented by 1 (step S1111). Then, it is determined whether the value of the confirmation target counter after the decrement by 1 is "0" (step S1112). When the value of the confirmation target counter is 1 or more (step S1112: NO), the processes after step S1102 are executed for the confirmation target corresponding to the value of the new confirmation target counter.

[0299] Next, the state in which the history information is stored in the history memory 117 will be described with reference to the time chart of FIG. 27. FIG. 27(a) shows the period during which a signal of HI level is input to any one of the first to seventh, eleventh buffers 122a to 122g, 122k, FIG. 27(b) shows the period during which a signal of HI level is input to the eighth buffer 122h, FIG. 27(c) shows the period during which a signal of HI level is input to the ninth buffer 122i, FIG. 27(d) shows the period during which a signal of HI level is input to the tenth buffer 122j, and FIG. 27(e) shows the writing timing of the history information to the history memory 117.

[0300] At the timing of t1, as shown in FIG. 27(a), the output state of the signal input to any one of the first to seventh, eleventh buffers 122a to 122g, 122k is switched from the LOW level to the HI level. Therefore, as shown in FIG. 27(e), the history information is written to the history memory 117 at the timing of t1. After that, at the timing of t2, as shown in FIG. 27(a), the signal switched to the HI level at the timing of t1 is switched to the LOW level. However, since the signal is a signal input to any one of the first to seventh, eleventh buffers 122a to 122g, 122k and the switching to the LOW level is not the target for storing the history information, the writing of the history information is not executed at the timing of t2 as shown in FIG. 27(e).

[0301] Thereafter, at each of the timings of t3, t5, t6, t9, t10, t13, and t14, as shown in FIG. 27(a), the output state of the signal input to any one of the first to seventh and eleventh buffers 122a to 122g, 122k is switched from the LOW level to the HI level. Therefore, history information is written as shown in FIG. 27(e) at each of these timings.

[0302] As shown in FIG. 27(b), from the timing of t4 to the timing of t7, the output state of the signal input to the eighth buffer 122h becomes the HI level. This eighth buffer 122h corresponds to the presence or absence of the occurrence of the opening / closing execution mode. Therefore, at the timing of t4 when the output state of the signal input to the eighth buffer 122h switches to the HI level and at the timing of t7 when the output state of the signal switches to the LOW level, both as shown in FIG. 27(e), history information is written. In this case, the history information written at the timing of t4 includes start information, and the history information written at the timing of t7 includes end information. Thereby, it becomes possible to grasp the execution period of the opening / closing execution mode by checking the history information in the history memory 117.

[0303] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any one of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the opening / closing execution mode. Also, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any one of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the opening / closing execution mode by comparing the RTC information.

[0304] As shown in FIG. 27(c), the output state of the signal input to the ninth buffer 122i becomes the HI level from the timing of t8 to the timing of t11. This ninth buffer 122i corresponds to the presence or absence of the occurrence of the high-frequency support mode. Therefore, at the timing of t8, which is the timing when the output state of the signal input to the ninth buffer 122i switches to the HI level as shown in FIG. 27(e), and at the timing of t11, which is the timing when the output state of the signal switches to the LOW level, history information is written. In this case, the history information written at the timing of t8 includes start information, and the history information written at the timing of t11 includes end information. Thereby, it becomes possible to grasp the execution period of the high-frequency support mode by checking the history information in the history memory 117.

[0305] Also, the history information is written in the history memory 117 in the order of the passage of time. Therefore, it becomes possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the high-frequency support mode. Further, since the history information includes RTC information, it is also possible to distinguish whether the history information indicating that a ball has entered any of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 is during the high-frequency support mode by comparing the RTC information.

[0306] As shown in FIG. 27(d), the output state of the signal input to the tenth buffer 122j is HI level from time t12 to time t15. This tenth buffer 122j corresponds to whether the front door frame 14 is open or closed. Therefore, as shown in FIG. 27(e), history information is written at time t12, when the output state of the signal input to the tenth buffer 122j switches to HI level, and at time t15, when the output state of the signal switches to LOW level. In this case, the history information written at time t12 includes start information, and the history information written at time t15 includes end information. This makes it possible to determine the period during which the front door frame 14 is open by checking the history information in the history memory 117.

[0307] Furthermore, the history information is written in chronological order to the history memory 117. Therefore, it is possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open. Furthermore, since the history information includes RTC information, it is also possible to distinguish whether or not the history information indicating that a ball has entered any of the outlet 24a, general winning opening 31, special electric winning device 32, first operating opening 33, and second operating opening 34 occurred while the front door frame 14 was open by comparing the RTC information.

[0308] Next, we will explain the output process of the setting value update signal that is executed when the setting state of the pachinko machine 10 is set by the main CPU 63. Figure 28 is a flowchart showing the output process of the setting value update signal that is executed by the main CPU 63. The output process of the setting value update signal is executed in step S119 in the main processing (Figure 9).

[0309] Set a value corresponding to the set value of the pachinko machine 10 currently set in the pulse number counter provided in the main-side RAM 65 (step S1201). Specifically, set the value of the set value counter in the main-side RAM 65 to the pulse number counter. Then, determine whether the set value update signal directed to the management-side CPU 112 is at the HI level (step S1202). As already described, the set value update signal is input to the 15th buffer 122o of the input port 121 in the management IC 66. Here, the output process of the set value update signal is executed at a timing earlier than the recognition process, which is a process for allowing the management-side CPU 112 to identify the types of signals input to the 1st to 14th buffers 122a to 122n of the input port 121 in the main process (Figure 9). On the other hand, since the set value update signal is input to the 15th buffer 122o being set in the management IC 66 at the design stage of the pachinko machine 10, even if the output process of the set value update signal is executed before the recognition process, it is possible for the management-side CPU 112 to identify that the signal input to the 15th buffer 122o is the set value update signal.

[0310] If a negative determination is made in step S1202, decrement the value of the LOW level counter provided in the main-side RAM 65 by 1 (step S1203), and determine whether the value of the LOW level counter after the decrement by 1 is "0" (step S1204). The LOW level counter is a counter for the main CPU 63 to identify whether the set value update signal has been maintained at the LOW level for a predetermined period while a plurality of pulses at which the set value update signal becomes the HI level are output. When the value of the LOW level counter is "0" (step S1204: YES), it means that it is the timing to set the set value update signal to the HI level, so set the set value update signal to the HI level (step S1205).

[0311] After that, "20" is set in the HI level counter provided in the main-side RAM 65 (step S1206). The HI level counter is a counter for the main-side CPU 63 to specify the period during which the set value update signal is maintained at the HI level. Since the value set in the HI level counter is decremented by 1 at a cycle of about 10 microseconds, the set value update signal is maintained at the HI level for 200 microseconds when outputting one pulse. This period of maintaining the HI level is sufficient for the management-side CPU 112 to specify that the set value update signal has changed from the LOW level to the HI level.

[0312] When the set value update signal is at the HI level (step S1202: YES), the value of the HI level counter in the main-side RAM 65 is decremented by 1 (step S1207), and it is determined whether the value of the HI level counter after the decrement is "0" (step S1208). When the value of the HI level counter is "0" (step S1208: YES), it means that it is time to set the set value update signal to the LOW level, so the set value update signal is set to the LOW level (step S1209).

[0313] After that, the value of the pulse number counter in the main-side RAM 65 is decremented by 1 (step S1210), and it is determined whether the value of the pulse number counter after the decrement is "0" (step S1211). When the value of the pulse number counter is not "0" (step S1211: NO), it means that the output of the pulse signal by the set value update signal corresponding to the set value of the pachinko machine 10 set this time is not completed, so "20" is set in the LOW level counter of the main-side RAM 65 (step S1212). Since the value set in the LOW level counter is decremented by 1 at a cycle of about 10 microseconds, it is maintained at the LOW level for 200 microseconds between multiple pulse outputs by the set value update signal. This period of maintaining the LOW level is sufficient for the management-side CPU 112 to specify that the set value update signal has changed from the HI level to the LOW level.

[0314] When the value of the pulse counter is "0" (step S1211: YES), it means that the output of the pulse signal by the set value update signal corresponding to the number of minutes of the set value of the pachinko machine 10 set this time has been completed. Therefore, the output process of the set value identification end command is executed (step S1213). The set value identification end command is a command for causing the management-side CPU 112 to recognize that the output of the set value update signal for causing the management-side CPU 112 to recognize the set value of the pachinko machine 10 set this time has been completed. When outputting the set value identification end command, the first to eighth signals input to the first to eighth buffers 122a to 122h are used in the same manner as the identification start command, the type identification command, and the identification end command. However, the signal pattern of the set value identification end command is different from that of the identification start command, the type identification command, and the identification end command.

[0315] As described above, in the output process of the set value update signal, a pulse signal by the set value update signal corresponding to the number of minutes of the set value of the pachinko machine 10 set at the start of the supply of the current operating power is output to the management IC 66. The management-side CPU 112 executes the set update recognition process to grasp the number of pulse signals by the set value update signal, and based on this, grasps the set value of the pachinko machine 10 set this time.

[0316] FIG. 29 is a flowchart showing the set update recognition process executed by the management-side CPU 112. The set update recognition process is executed in step S902 of the management process (FIG. 23).

[0317] Determine whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from the LOW level to the HIGH level (step S1301). If an affirmative determination is made in step S1301, set the value of the setting value grasping counter provided in the management-side RAM 114 to "1" (step S1302). The setting value grasping counter is a counter for the management-side CPU 112 to identify the setting value of the pachinko machine 10. For example, if the value of the setting value grasping counter is "1", it means "Setting 1", and if the value of the setting value grasping counter is "6", it means "Setting 6".

[0318] Thereafter, determine whether the setting value update signal input to the 15th buffer 122o of the input port 121 has switched from the LOW level to the HIGH level again (step S1303). If an affirmative determination is made in step S1303, increment the value of the setting value grasping counter in the management-side RAM 114 by 1 (step S1304). As a result, the setting value of the pachinko machine 10 identified by the management-side CPU 112 will increase by one step.

[0319] If a negative determination is made in step S1303, or if the process of step S1304 is executed, determine whether a setting value identification end command has been received from the main-side CPU 63 based on the input states of the first to eighth signals input to the first to eighth buffers 122a to 122h of the input port 121 (step S1305). If a negative determination is made in step S1305, return to the process of step S1303.

[0320] If an affirmative determination is made in step S1305, RTC information, which is year / month / day information and time information, is read from RTC 115 (step S1306). Then, a writing process to the history memory 117 is executed (step S1307). In this writing process, by referring to the pointer area 126 of the history memory 117, the pointer information of the history area 124 that is currently the writing target is specified, and the RTC information read in step S1306 is written to the history information storage area 125 of the history area 124 corresponding to the pointer information that is the writing target. Further, both information for identifying that it is a set value and information on the value of the set value grasping counter are written to the history information storage area 125 corresponding to the pointer information that is the writing target. As a result, a combination of information indicating that the setting state of the pachinko machine 10 has been newly set, RTC information corresponding to the date and time when the setting was made, and information on the set value when the setting was made is stored as history information.

[0321] Thereafter, an update process for the target pointer is executed (step S1308). In this update process, the numerical information stored in the pointer area 126 of the history memory 117 is read and incremented by 1. It is determined whether the pointer information after the increment of 1 exceeds the maximum value of the pointer information in the history area 124. If it does not exceed the maximum value, the pointer information after the increment of 1 is overwritten to the pointer area 126 as the new writing target pointer information. If it exceeds the maximum value, the pointer area 126 is cleared to "0" so that the pointer information to be written becomes the first pointer information.

[0322] When the setting update recognition process is executed as described above and the setting state of the pachinko machine 10 is newly set, the fact that the setting has been made, the date and time when the setting was made, and the combination of setting values when the setting was made are stored as history information in the history area 124. Thus, by reading and analyzing the information stored in the history memory 117 using an external device connected to the reading terminal 68d, it becomes possible to grasp the date and time when the setting state of the pachinko machine 10 was newly set and the content of the setting values when the setting was made.

[0323] Here, even if the setting state of the pachinko machine 10 is newly set, the information stored in the history memory 117 is maintained as it is. As a result, it becomes possible to prevent the history information in the history memory 117 from being erased even if the setting state of the pachinko machine 10 is newly set, and various parameters described later are calculated using the history information existing across the timing before and after the change of the setting state of the pachinko machine 10. In this case, since the date and time when the setting state of the pachinko machine 10 was newly set is stored in the history memory 117 as described above, by connecting an external device to the reading terminal 68d and reading the information stored in the history memory 117, it becomes possible to calculate various parameters in the period after the timing when the setting state of the pachinko machine 10 was newly set and during which the setting state is maintained.

[0324] Next, the display output process executed by the management side CPU 112 will be described with reference to the flowchart of FIG. 30. Note that the display output process is executed in step S909 of the management process (FIG. 23).

[0325] First, it is determined whether it is time for calculation (step S1401). If 51 seconds have passed since the supply of operating power to the management CPU 112 started, or if 51 seconds have passed since the previous affirmative determination in step S1401, a positive determination is made in step S1401. If a positive determination is made in step S1401, the number of balls that enter during normal times is calculated (step S1402). Specifically, the number of balls that enter the outlet 24a is calculated by first counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the ball is the outlet 24a. In addition, the number of balls that enter the general winning opening 31 is calculated by counting the number of history information storage areas 125 in the history area 124 of the history memory 117 that store correspondence information indicating that the ball is the general winning opening 31. In addition, the number of balls that have entered the special power winning device 32 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the device is the special power winning device 32 is stored in the history area 124 of the history memory 117. In addition, the number of balls that have entered the first operating port 33 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the device is the first operating port 33 is stored in the history area 124 of the history memory 117. In addition, the number of balls that have entered the second operating port 34 is calculated by counting the number of history information storage areas 125 in which correspondence information indicating that the device is the second operating port 34 is stored in the history area 124 of the history memory 117.

[0326] Thereafter, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored and the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the end information are stored in the history area 124 of the history memory 117, the number of balls entering each of the out ports 24a, general winning ports 31, special electric winning devices 32, first operating ports 33, and second operating ports 34 that occurred in the situation where the front door frame 14 is in the open state is calculated (step S1403). The period between the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored and the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the end information are stored in the history area 124 of the history memory 117 is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the pointer information with consecutive numbers, when there are a plurality of sections between the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored and the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the end information are stored, the number of balls entering each is calculated for the total of those sections. Further, although the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored exists, when the correspondence information indicating that it is the front door frame 14 and the end information are not stored in the history information storage area 125 storing the RTC information corresponding to the time after the said history information storage area 125, all of the history information in the history information storage area 125 storing the RTC information corresponding to the time after the history information storage area 125 in which the correspondence information indicating that it is the front door frame 14 and the start information are stored is treated as being in the state where the front door frame 14 is open.

[0327] Thereafter, various parameters are calculated using the calculation results of step S1402 and step S1403 (step S1404). Specifically, first, the number of balls entering in each case calculated in step S1403 while the front door frame 14 is open is subtracted from the number of balls entering in each case calculated in step S1402. Then, the following first to eighth parameters are calculated using the number of balls entering in each case after the subtraction. Note that the difference between the number of balls entering the out port 24a calculated in step S1403 and the number of balls entering the out port 24a calculated in step S1402 is defined as the number of balls entering K1, the difference between the number of balls entering the general winning port 31 calculated in step S1403 and the number of balls entering the general winning port 31 calculated in step S1402 is defined as the number of balls entering K2, the difference between the number of balls entering the special electric winning device 32 calculated in step S1403 and the number of balls entering the special electric winning device 32 calculated in step S1402 is defined as the number of balls entering K3, the difference between the number of balls entering the first operation port 33 calculated in step S1403 and the number of balls entering the first operation port 33 calculated in step S1402 is defined as the number of balls entering K4, and the difference between the number of balls entering the second operation port 34 calculated in step S1403 and the number of balls entering the second operation port 34 calculated in step S1402 is defined as the number of balls entering K5. · First parameter: The ratio of the total number of payout game balls (K2 × "number of prize balls for winning in the general winning port 31" + K3 × "number of prize balls for winning in the special electric winning device 32" + K4 × "number of prize balls for winning in the first operation port 33" + K5 × "number of prize balls for winning in the second operation port 34") to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D1") · Second parameter: The ratio of the total number of game balls K2 entering the general winning port 31 to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) · Third parameter: The ratio of the total number of game balls K3 entering the special electric winning device 32 to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) <000139a>· Fourth parameter: The ratio of the total number of game balls K4 entering the first operation port 33 to the total number of game balls discharged from the game area PA (K1 + K2 + K3 + K4 + K5) (hereinafter, this ratio is referred to as "D2") It should be noted that there seems to be a typo in the original text where <000139a> should probably be . This has been corrected in the translation for the sake of clarity.· Fifth parameter: Ratio of the total number of game balls K5 entering the second operation port 34 to the total number of game balls (K1 + K2 + K3 + K4 + K5) discharged from the game area PA (hereinafter, this ratio is referred to as "D3") · Sixth parameter: D1 - (D2 × "number of prize balls for winning at the first operation port 33" + D3 × "number of prize balls for winning at the second operation port 34") · Seventh parameter: Ratio of (K3 × "number of prize balls for winning at the special electric winning device 32" + K5 × "number of prize balls for winning at the second operation port 34") to the total number of game balls paid out (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operation port 33" + K5 × "number of prize balls for winning at the second operation port 34") · Eighth parameter: Ratio of K3 × "number of prize balls for winning at the special electric winning device 32" to the total number of game balls paid out (K2 × "number of prize balls for winning at the general winning port 31" + K3 × "number of prize balls for winning at the special electric winning device 32" + K4 × "number of prize balls for winning at the first operation port 33" + K5 × "number of prize balls for winning at the second operation port 34") In step S1404, the above first to eighth parameters, which are the calculation results, are stored in the normal-time storage area in the calculation result memory 131. The above first to eighth parameters stored in the normal-time storage area are retained until the next step S1404 is executed. That is, when the next step S1404 is executed and the above first to eighth parameters are calculated, the newly calculated above first to eighth parameters are stored in the normal-time storage area, thereby overwriting the calculation results of the previous first to eighth parameters that were stored in the normal-time storage area until then.

[0328] Thereafter, by referring to the history information storage area 125 existing during the period between the history information storage area 125 in which the correspondence information and start information indicating the open / close execution mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence information and end information indicating the open / close execution mode are stored, the number of balls entering each of the out ports 24a, general winning ports 31, special electric winning devices 32, first operation ports 33, and second operation ports 34 that occurred in the open / close execution mode is calculated (step S1405). The period between the history information storage area 125 in which the correspondence information and start information indicating the open / close execution mode are stored in the history area 124 of the history memory 117 and the history information storage area 125 in which the correspondence information and end information indicating the open / close execution mode are stored is calculated from the RTC information stored in these history information storage areas 125. Also, in the whole of the pointer information with consecutive numbers, when there are a plurality of sections between the history information storage area 125 in which the correspondence information and start information indicating the open / close execution mode are stored and the history information storage area 125 in which the correspondence information and end information indicating the open / close execution mode are stored, the number of balls entering for each total of those sections is calculated. Further, although the history information storage area 125 in which the correspondence information and start information indicating the open / close execution mode are stored exists, when the correspondence information and end information indicating the open / close execution mode are not stored in the history information storage area 125 corresponding to the time after the said history information storage area 125, all of the history information in the history information storage area 125 corresponding to the time after the history information storage area 125 in which the correspondence information and start information indicating the open / close execution mode are stored is treated as being in the open / close execution mode.

[0329] After that, among the periods in the opening / closing execution mode specified in step S1405, the number of game balls entering each of the out-port 24a, the general winning port 31, the special-electric winning device 32, the first operation port 33, and the second operation port 34 that occurred in the situation where the front door frame 14 was in the open state is calculated (step S1406). The method for calculating these numbers of game balls entering is the same as in the case of step S1403, except that it is premised on the period in the opening / closing execution mode specified in step S1405.

[0330] After that, various parameters are calculated using the calculation results of step S1405 and step S1406 (step S1407). Specifically, first, the number of game balls entering during the opening of the front door frame 14 calculated in step S1406 is subtracted from each number of game balls entering calculated in step S1405. Then, the following 11th to 18th parameters are calculated using the number of game balls entering after the subtraction. Note that the difference between the number of game balls entering the out-port 24a calculated in step S1406 and the number of game balls entering the out-port 24a calculated in step S1405 is defined as the number of game balls entering K11, the difference between the number of game balls entering the general winning port 31 calculated in step S1406 and the number of game balls entering the general winning port 31 calculated in step S1405 is defined as the number of game balls entering K12, the difference between the number of game balls entering the special-electric winning device 32 calculated in step S1406 and the number of game balls entering the special-electric winning device 32 calculated in step S1405 is defined as the number of game balls entering K13, the difference between the number of game balls entering the first operation port 33 calculated in step S1406 and the number of game balls entering the first operation port 33 calculated in step S1405 is defined as the number of game balls entering K14, and the difference between the number of game balls entering the second operation port 34 calculated in step S1406 and the number of game balls entering the second operation port 34 calculated in step S1405 is defined as the number of game balls entering K15. · 11th parameter: The ratio of the total number of paid-out game balls (K12 × "number of bonus balls for winning at the general winning port 31" + K13 × "number of bonus balls for winning at the special-electric winning device 32" + K14 × "number of bonus balls for winning at the first operation port 33" + K15 × "number of bonus balls for winning at the second operation port 34") to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio is referred to as "D11") 12th parameter: The ratio of the total number of game balls entering the general winning slot 31 (K12) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 13th parameter: The ratio of the total number of game balls entering the special winning device 32 (K13) to the total number of game balls discharged from the game area PA (K11+K12+K13+K14+K15) 14th parameter: The ratio of the total number of game balls entering the first operating port 33 (K14) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D12") 15th parameter: The ratio of the total number of game balls entering the second operating port 34 (K15) to the total number of game balls discharged from the game area PA (K11 + K12 + K13 + K14 + K15) (hereinafter, this ratio will be referred to as "D13") 16th parameter: D11 - (D12 x "Number of winning balls for winning into the first operating port 33" + D13 x "Number of winning balls for winning into the second operating port 34") 17th parameter: (K13 × "Number of prize balls for winning the special electric winning device 32" + K15 × "Number of prize balls for winning the second operating port 34") / Total number of game balls paid out (K12 × "Number of prize balls for winning the general winning port 31" + K13 × "Number of prize balls for winning the special electric winning device 32" + K14 × "Number of prize balls for winning the first operating port 33" + K15 × "Number of prize balls for winning the second operating port 34") ratio 18th parameter: K13 × "Number of prize balls for winning the special electric winning device 32" / Total number of game balls paid out (K12 × "Number of prize balls for winning the general winning port 31" + K13 × "Number of prize balls for winning the special electric winning device 32" + K14 × "Number of prize balls for winning the first operating port 33" + K15 × "Number of prize balls for winning the second operating port 34") ratio In step S1407, the 11th to 18th parameters, which are the calculation results, are stored in a storage area for the open / close execution mode in the calculation result memory 131. The 11th to 18th parameters stored in the storage area for the open / close execution mode are held until the next time step S1407 is executed. In other words, when the next time step S1407 is executed and the 11th to 18th parameters are calculated, the newly calculated 11th to 18th parameters are stored in the storage area for the open / close execution mode, overwriting the previous calculation results of the 11th to 18th parameters that had been stored in the storage area for the open / close execution mode.

[0331] Thereafter, by referring to the history information storage area 125 existing in the period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high frequency support mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the high frequency support mode, the number of balls entering each of the out hole 24a, the general winning hole 31, the special electric winning device 32, the first operating hole 33, and the second operating hole 34 that occurred in the high frequency support mode situation is calculated (step S1408). The period between the history information storage area 125 storing the correspondence relationship information and start information indicating the high frequency support mode in the history area 124 of the history memory 117 and the history information storage area 125 storing the correspondence relationship information and end information indicating the high frequency support mode is calculated from the RTC information stored in these history information storage areas 125. Furthermore, if there are multiple sections within the entire set of consecutive pointer information between history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode and history information storage area 125 storing correspondence relationship information and end information indicating the high frequency support mode, the total number of balls scored for each section is calculated. Furthermore, if there is a history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode, but the history information storage area 125 storing RTC information corresponding to a time later than that of the history information storage area 125 does not store correspondence relationship information and end information indicating the high frequency support mode, all history information in history information storage area 125 storing RTC information corresponding to a time later than that of the history information storage area 125 storing correspondence relationship information and start information indicating the high frequency support mode is treated as being in the high frequency support mode.

[0332] After that, among the periods in the high-frequency support mode specified in step S1408, the number of game balls entering each of the out port 24a, the general winning port 31, the special electric winning device 32, the first operation port 33, and the second operation port 34 that occurred in the situation where the front door frame 14 was in the open state is calculated (step S1409). The method for calculating these numbers of game balls entering is the same as in the case of step S1403, except that it is premised on the period in the high-frequency support mode specified in step S1408.

[0333] After that, various parameters are calculated using the calculation results of steps S1408 and S1409 (step S1410). Specifically, first, the number of game balls entering during the opening of the front door frame 14 calculated in step S1409 is subtracted from each number of game balls entering calculated in step S1408. Then, the following 21st to 26th parameters are calculated using the number of game balls entering after the subtraction. Note that the difference between the number of game balls entering the out port 24a calculated in step S1409 and the number of game balls entering the out port 24a calculated in step S1408 is defined as the number of game balls entering K21, the difference between the number of game balls entering the general winning port 31 calculated in step S1409 and the number of game balls entering the general winning port 31 calculated in step S1408 is defined as the number of game balls entering K22, the difference between the number of game balls entering the special electric winning device 32 calculated in step S1409 and the number of game balls entering the special electric winning device 32 calculated in step S1408 is defined as the number of game balls entering K23, the difference between the number of game balls entering the first operation port 33 calculated in step S1409 and the number of game balls entering the first operation port 33 calculated in step S1408 is defined as the number of game balls entering K24, and the difference between the number of game balls entering the second operation port 34 calculated in step S1409 and the number of game balls entering the second operation port 34 calculated in step S1408 is defined as the number of game balls entering K25. · 21st parameter: The ratio of the total number of paid-out game balls (K22 × "number of prize balls for winning at the general winning port 31" + K23 × "number of prize balls for winning at the special electric winning device 32" + K24 × "number of prize balls for winning at the first operation port 33" + K25 × "number of prize balls for winning at the second operation port 34") / the total number of game balls discharged from the game area PA (K21 + K22 + K23 + K24 + K25) (hereinafter, this ratio is referred to as "D11") · 22nd parameter: Ratio of the total number of game balls K22 that have entered the general winning opening 31 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA · 23rd parameter: Ratio of the total number of game balls K23 that have entered the special electric winning device 32 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA · 24th parameter: Ratio of the total number of game balls K24 that have entered the first activation opening 33 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D22") · 25th parameter: Ratio of the total number of game balls K25 that have entered the second activation opening 34 to the total number of game balls (K21 + K22 + K23 + K24 + K25) discharged from the game area PA (hereinafter, this ratio is referred to as "D23") · 26th parameter: D21 - (D22 × "number of prize balls for winning at the first activation opening 33" + D23 × "number of prize balls for winning at the second activation opening 34") In step S1410, the 21st to 26th parameters, which are the calculation results, are stored in the storage area for the high-frequency support mode in the calculation result memory 131. The 21st to 26th parameters stored in the storage area for the high-frequency support mode are retained until the next step S1410 is executed. That is, when the next step S1410 is executed and the 21st to 26th parameters are calculated, the newly calculated 21st to 26th parameters are stored in the storage area for the high-frequency support mode, thereby overwriting the calculation results of the previous 21st to 26th parameters that were stored in the storage area for the high-frequency support mode until then.

[0334] Thereafter, the occurrence frequency of the opening / closing execution mode is calculated and stored (step S1411). Specifically, the number of history information storage areas 125 in which the correspondence information indicating the opening / closing execution mode and the start information are stored in the history area 124 of the history memory 117 is counted to calculate the number of occurrences of the opening / closing execution mode. Also, the number of history information storage areas 125 in which the correspondence information indicating the start of a game round is stored in the history area 124 of the history memory 117 is counted to calculate the number of occurrences of the game round. Then, the number of occurrences of the opening / closing execution mode per unit game round is calculated. Note that the number of occurrences of the opening / closing execution mode is defined as the occurrence number K31, and the number of occurrences of the game round is defined as the occurrence number K32. · 31st parameter: K31 / K32 In step S1411, the above 31st parameter, which is the calculation result, is stored in the storage area for the opening / closing execution mode frequency in the calculation result memory 131. The above 31st parameter stored in the storage area for the opening / closing execution mode frequency is stored and held until the next step S1411 is executed. That is, when the next step S1411 is executed and the above 31st parameter is calculated, the newly calculated above 31st parameter is stored in the storage area for the opening / closing execution mode frequency, thereby overwriting the calculation result of the previous 31st parameter stored in the storage area for the opening / closing execution mode frequency until then.

[0335] Thereafter, the occurrence frequency of the high-frequency support mode is calculated and stored (step S1412). Specifically, the number of history information storage areas 125 in which the correspondence information and start information indicating that it is the high-frequency support mode are stored in the history area 124 of the history memory 117 is counted to calculate the number of occurrences of the high-frequency support mode. Also, the number of occurrences of the game rounds is calculated by counting the number of history information storage areas 125 in which the correspondence information indicating the start of the game rounds is stored in the history area 124 of the history memory 117. Then, the number of occurrences of the high-frequency support mode per unit game round and the ratio of the number of occurrences of the high-frequency support mode to the number of occurrences of the opening / closing execution mode are calculated. Note that the number of occurrences of the high-frequency support mode is the number of occurrences K41, the number of occurrences of the game rounds is the number of occurrences K42, and the number of occurrences of the opening / closing execution mode calculated in step S1411 is the number of occurrences K43. · Parameter 41: K41 / K42 · Parameter 42: K41 / K43 In step S1412, the above-mentioned 41st to 42nd parameters, which are the calculation results, are stored in the high-frequency support mode frequency storage area in the calculation result memory 131. The above-mentioned 41st to 42nd parameters stored in the high-frequency support mode frequency storage area are stored and held until the next step S1412 is executed. That is, when the next step S1412 is executed and the above-mentioned 41st to 42nd parameters are calculated, the newly calculated above-mentioned 41st to 42nd parameters are stored in the high-frequency support mode frequency storage area, and thus the calculation results of the previous 41st to 42nd parameters stored in the high-frequency support mode frequency storage area until then are overwritten.

[0336] When a negative determination is made in step S1401, or when the process of step S1412 is executed, display processing is executed (step S1413). FIG. 31 is a flowchart showing the display processing.

[0337] First, decrement the value of the update timing counter provided in the management-side RAM 114 by 1 (step S1501). The update timing counter is a counter for the mana...

Claims

【Claim 1】 A history storage execution means for storing, in a history storage means, history information of a game corresponding to a predetermined event when the game is executed; An information derivation means for deriving mode information corresponding to the result of the game by using the history information stored in the history storage means; A mode information storage means for storing the mode information derived by the information derivation means; A mode information display control means for performing control so that a display corresponding to the mode information stored in the mode information storage means is performed by an information display means; A predetermined corresponding display control means for performing control so that a predetermined corresponding display is performed by the information display means before a display corresponding to the mode information is newly started based on the occurrence of a predetermined display timing; A setting means for setting a set value corresponding to the advantage degree of the player; A situation generation means for making it a settable situation in which the set value can be set by the setting means; Comprising: The mode information storage means includes a plurality of specific storage areas so as to be able to store each of the plurality of mode information; The mode information display control means performs control so that displays corresponding to each of the plurality of mode information stored in the plurality of specific storage areas are sequentially executed by the information display means according to a predetermined display order. When causing the information display means to perform a display corresponding to the mode information after the predetermined corresponding display is performed by the information display means, it starts from the display corresponding to the mode information corresponding to the first order in the predetermined display order; The information derivation means derives the mode information by using the history information in a predetermined advantageous period; This gaming machine: A control means for executing various processes; A predetermined storage means for storing information when a process is executed by the control means; Comprising: The control means: An in-area process execution means for executing an in-area process which is a process using a program stored in a storage area within a predetermined address range in a program storage means; An out-of-area process execution means for executing an out-of-area process which is a process using a program stored in a storage area in an address range outside the predetermined address range in the program storage means; A means for calculating predetermined numerical information corresponding to a plurality of predetermined information stored in the predetermined storage means when the supply of operating power is started; means for specifying whether or not the predetermined numerical information is normal; comprising; information on an area for storing information on the set value set by the setting means is included in the plurality of predetermined information; this gaming machine; an in-area corresponding storage area in which writing and reading of information are possible when the in-area process is executed, while reading of information is possible but writing of information is impossible when the out-of-area process is executed; an out-of-area corresponding storage area in which writing and reading of information are possible when the out-of-area process is executed, while reading of information is possible but writing of information is impossible when the in-area process is executed; comprising; The gaming machine according to claim 1, wherein the in-area process execution means includes means capable of executing, as the in-area process, a process for making the set value set as a use target visually confirmable in a situation where the game can be started after the process at the start of supply of operating power is completed.

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