field-effect transistor
The field-effect transistor design with a p-type trench lower layer and p-type deep layers addresses electric field concentration issues, improving breakdown voltage and switching characteristics by stabilizing potential and reducing capacitance.
JP7750347B2Active Publication Date: 2025-10-07DENSO CORP
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Patent Information
- Application Number
- JP2024121992
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- Priority Date
- 2021-04-15
- Filing Date
- 2024-07-29
- Publication Date
- 2025-10-07
- Estimated Expiration
- 2041-06-23
AI Technical Summary
Technical Problem
Existing field-effect transistors with multiple p-type deep layers face challenges in alleviating electric field concentration at the trench bottom, which affects breakdown voltage and switching characteristics.
Method used
The transistor design includes a p-type trench lower layer and multiple p-type deep layers that extend downward, intersecting with trenches, and are connected to a gate insulating film, stabilizing potential and reducing electric field concentration, thereby improving breakdown voltage while maintaining switching characteristics.
Benefits of technology
The design achieves a high breakdown voltage and stable switching characteristics by alleviating electric field concentration, reducing feedback capacitance, and enhancing switching speed.
✦ Generated by Eureka AI based on patent content.
Abstract
To provide a technique of achieving a higher withstanding voltage in a field effect transistor including a plurality of p-type deep layers.SOLUTION: A field effect transistor 10 includes a p-type trench lower layer 35 disposed on a lower side of a trench 14 and extending along a longitudinal direction of the trench when a semiconductor substrate 12 is viewed from above, a plurality of p-type deep layers 36, and a plurality of n-type deep layers 37. The p-type deep layers protrude downward from a body layer 34, extend in a first direction intersecting with the trench when the semiconductor substrate is viewed from above, are disposed with a space part therebetween in a second direction that is orthogonal to the first direction, and are in contact with the p-type trench lower layer disposed on a lower side of the trench. Each n-type deep layer is disposed in the corresponding space part and is in contact with a gate insulating film on a side surface of the trench existing on a lower side of the body layer.SELECTED DRAWING: Figure 1
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