Semiconductor device, display device, and electronic device

Abstract

Provided is a highly reliable semiconductor device. The present invention relates to a shift register circuit including sequential circuits of a plurality of stages. An output signal of a sequential circuit is input to the sequential circuit of the next stage. Before and after the sequential circuit outputs a signal, in order to prevent a voltage stress from being applied between a gate and a source of a transistor including the sequential circuit for a long time, the potential of the gate of the transistor is varied according to a clock signal. The shift register circuit described above can be applied, for example, to a scanning line drive circuit of a display device.

Description

[Technical Field]

[0001] 1. Field of the Invention An embodiment of the present invention relates to a semiconductor device, a display device, or an electronic device.

[0002] Note that one embodiment of the present invention is not limited to the above technical field. Examples of the technical field of one embodiment of the present invention disclosed in this specification and the like include semiconductor devices, display devices, light-emitting devices, power storage devices, memory devices, electronic devices, lighting devices, input devices, input / output devices, driving methods thereof, and manufacturing methods thereof. A semiconductor device refers to any device that can function by utilizing semiconductor characteristics. [Background technology]

[0003] In recent years, display devices are expected to be used in a variety of applications. For example, applications of large display devices include home television devices (also called televisions or television receivers), digital signage, and public information displays (PIDs). In addition, development of smartphones and tablet devices equipped with touch panels as mobile information terminals is progressing.

[0004] There is also a demand for higher resolution display devices. Devices requiring high resolution display devices, such as those for virtual reality (VR), augmented reality (AR), substitutional reality (SR), and mixed reality (MR), are being actively developed.

[0005] As a display device, for example, a light-emitting device having a light-emitting element has been developed. A light-emitting element (also called a light-emitting device, an EL element, or an EL device) utilizing the electroluminescence (hereinafter referred to as EL) phenomenon has features such as being easily thin and lightweight, being capable of high-speed response to input signals, and being capable of being driven by a DC constant voltage power supply, and is therefore applied to display devices.

[0006] Patent Document 1 discloses a display device for VR that uses an organic EL element (also called an organic EL device). [Prior art documents] [Patent documents]

[0007] [Patent Document 1] International Publication No. 2018 / 087625 Summary of the Invention [Problem to be solved by the invention]

[0008] Display devices include various semiconductor devices. For example, semiconductor devices are provided in driver circuits, such as scanning line driver circuits, for driving pixel circuits. High-resolution display devices have high pixel densities, resulting in a large number of pixel circuits electrically connected to scanning lines per unit length. This increases the wiring capacitance of the scanning lines due to factors such as the gate capacitance of transistors in the pixel circuits and electrically connected to the scanning lines. Furthermore, the number of scanning lines increases as the display device includes a large number of pixel circuits. Therefore, in order to ensure a high frame frequency, it is necessary to shorten one horizontal period, which is the period from when a signal is supplied to a scanning line until when a signal is supplied to the next scanning line. As described above, the increase in wiring capacitance of the scanning lines and the shortening of one horizontal period necessitates a larger current flowing through the scanning lines when charging them.

[0009] In order to increase the current flowing through the scan lines, the potential of the signal output from the scan line driver circuit to the scan lines is increased, which applies a large voltage stress to the transistors electrically connected to the scan lines and provided in the scan line driver circuit. Therefore, in a high-resolution display device or a display device with a large number of pixels, the reliability of the semiconductor device provided in the display device may be reduced.

[0010] An object of one embodiment of the present invention is to provide a highly reliable semiconductor device and display device.An object of one embodiment of the present invention is to provide a high-resolution display device.An object of one embodiment of the present invention is to provide a display device with a large number of pixels.An object of one embodiment of the present invention is to provide a novel semiconductor device and display device.An object of one embodiment of the present invention is to provide a method for driving the semiconductor device or the like.An object of one embodiment of the present invention is to provide a method for manufacturing the display device or the like.

[0011] Note that the description of these problems does not preclude the existence of other problems. Note that one embodiment of the present invention does not necessarily solve all of these problems. Note that problems other than these can be extracted from the description of the specification, drawings, claims, etc. [Means for solving the problem]

[0012] One embodiment of the present invention includes a first circuit and a second circuit. The first circuit includes a first wiring, a second wiring, a first transistor, a second transistor, a third transistor, and a fourth transistor. A gate of the first transistor is electrically connected to the second circuit through the first wiring. The gate of the second transistor, one of a source or a drain of the third transistor, and one of a source or a drain of the fourth transistor are electrically connected to the second circuit through a second wiring. One of the source or the drain of the first transistor is electrically connected to the one of the source or the drain of the second transistor. A first clock signal is input to the other of the source or the drain of the first transistor. A semiconductor device is provided in which a first potential is supplied to the other of the source or the drain of the second transistor, a second clock signal is input to the gate of the third transistor, a second potential is supplied to the other of the source or the drain of the third transistor, a third clock signal is input to the gate of the fourth transistor, and a third potential is supplied to the other of the source or the drain of the fourth transistor, a difference between the third potential and the first potential is larger than a difference between the second potential and the first potential, and the second circuit has a function of supplying a first control potential to a first wiring based on a first signal and a second signal input to the second circuit, and the second circuit has a function of supplying a second control potential to a second wiring based on the first signal and the second signal.

[0013] Alternatively, in the above aspect, the second circuit may have a function of setting the second control potential to an inverted potential of the first control potential when the potential of the second signal is an inverted potential of the potential of the first signal.

[0014] Alternatively, in the above aspect, the second circuit may include a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor, wherein one of a source or a drain of the fifth transistor and one of a source or a drain of the sixth transistor are electrically connected to a first wiring, a gate of the sixth transistor, one of a source or a drain of the seventh transistor, and one of a source or a drain of the eighth transistor are electrically connected to a second wiring, and a first signal is input to the gate of the fifth transistor and the gate of the eighth transistor, and a second signal is input to the gate of the seventh transistor.

[0015] Alternatively, in the above aspect, a fourth potential may be supplied to the other of the source or drain of the fifth transistor, a fifth potential may be supplied to the other of the source or drain of the sixth transistor, a sixth potential may be supplied to the other of the source or drain of the seventh transistor, and a seventh potential may be supplied to the other of the source or drain of the eighth transistor, the fifth potential being an inverted potential of the fourth potential, and the seventh potential being an inverted potential of the sixth potential.

[0016] Alternatively, in the above aspect, the first circuit may have a ninth transistor, the ninth transistor may be electrically connected to one of the source or drain of the first transistor, a second clock signal may be input to the gate of the ninth transistor, an eighth potential may be supplied to the other of the source or drain of the ninth transistor, and a difference between the second potential and the eighth potential may be smaller than a difference between the third potential and the eighth potential.

[0017] Alternatively, one embodiment of the present invention includes a first circuit and a second circuit. The first circuit includes a first wiring, a second wiring, a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, and a capacitor. One of a source or a drain of the first transistor is electrically connected to one of a source or a drain of the second transistor. The one of the source or the drain of the second transistor is electrically connected to one electrode of the capacitor. The one of the source or the drain of the fifth transistor is electrically connected to the second circuit through a first wiring. The other of the source or the drain of the fifth transistor is electrically connected to a gate of the first transistor. The gate of the first transistor is electrically connected to the other electrode of the capacitor. a first clock signal is input to the other of the source or drain of the first transistor, a first potential is supplied to the other of the source or drain of the second transistor, a second clock signal is input to the gate of the third transistor, a second potential is supplied to the other of the source or drain of the third transistor, a third clock signal is input to the gate of the fourth transistor, and a third potential is supplied to the other of the source or drain of the fourth transistor, a difference between the third potential and the first potential is larger than a difference between the second potential and the first potential, and the second circuit has a function of supplying a first control potential to the first wiring based on the first signal and the second signal input to the second circuit, and the second circuit has a function of supplying a second control potential to the second wiring based on the first signal and the second signal.

[0018] Alternatively, in the above aspect, the fourth clock signal may be input to the gate of the fifth transistor.

[0019] Alternatively, in the above aspect, the second circuit may have a function of setting the second control potential to an inverted potential of the first control potential when the potential of the second signal is an inverted potential of the potential of the first signal.

[0020] Alternatively, in the above aspect, the second circuit may include a sixth transistor, a seventh transistor, an eighth transistor, and a ninth transistor, wherein one of a source or a drain of the sixth transistor and one of a source or a drain of the seventh transistor are electrically connected to a first wiring, a gate of the seventh transistor, one of a source or a drain of the eighth transistor, and one of a source or a drain of the ninth transistor are electrically connected to a second wiring, and a first signal is input to the gate of the sixth transistor and the gate of the ninth transistor, and a second signal is input to the gate of the eighth transistor.

[0021] Alternatively, in the above aspect, a fourth potential may be supplied to the other of the source or drain of the sixth transistor, a fifth potential may be supplied to the other of the source or drain of the seventh transistor, a sixth potential may be supplied to the other of the source or drain of the eighth transistor, and a seventh potential may be supplied to the other of the source or drain of the ninth transistor, the fifth potential being an inverted potential of the fourth potential, and the seventh potential being an inverted potential of the sixth potential.

[0022] Alternatively, in the above aspect, the first circuit may have a tenth transistor, the tenth transistor may be electrically connected to one of the source or drain of the first transistor, a second clock signal may be input to the gate of the tenth transistor, an eighth potential may be supplied to the other of the source or drain of the tenth transistor, and a difference between the second potential and the eighth potential may be smaller than a difference between the third potential and the eighth potential.

[0023] Another embodiment of the present invention is a display device including a semiconductor device of one embodiment of the present invention, a first light-emitting element, a second light-emitting element, and an insulating layer, in which the first light-emitting element has a first bottom electrode, a first light-emitting layer over the first bottom electrode, and a first upper electrode over the first light-emitting layer, and the second light-emitting element has a second bottom electrode, a second light-emitting layer over the second bottom electrode, and a second upper electrode over the second light-emitting layer, and the insulating layer is provided to cover an end portion of the first upper electrode and an end portion of the second upper electrode.

[0024] An electronic device including the display device of one embodiment of the present invention and at least one of a battery, a camera, a speaker, and a microphone is also one embodiment of the present invention. [Effects of the Invention]

[0025] According to one embodiment of the present invention, a highly reliable semiconductor device and a display device can be provided. According to one embodiment of the present invention, a high-resolution display device can be provided. According to one embodiment of the present invention, a display device with a large number of pixels can be provided. According to one embodiment of the present invention, a novel semiconductor device and a display device can be provided. According to one embodiment of the present invention, a driving method of the semiconductor device or the like can be provided. According to one embodiment of the present invention, a manufacturing method of the display device or the like can be provided.

[0026] Note that the description of these effects does not preclude the existence of other effects. Note that one embodiment of the present invention does not necessarily have all of these effects. Note that effects other than these can be extracted from the description in the specification, drawings, claims, etc. [Brief explanation of the drawings]

[0027] Fig. 1A is a diagram showing an example of the configuration of a shift register circuit, and Fig. 1B is a timing chart showing an example of a method for driving the shift register circuit. FIG. 2 is a diagram illustrating an example of the configuration of a sequential circuit. Fig. 3A is a diagram showing an example of the configuration of a sequential circuit, and Fig. 3B is a timing chart showing an example of a method for driving the sequential circuit. 4A and 4B are diagrams showing an example of a method for driving a sequential circuit. 5A and 5B are diagrams showing an example of a method for driving a sequential circuit. 6A and 6B are diagrams showing an example of a method for driving a sequential circuit. 7A and 7B are diagrams showing an example of a method for driving a sequential circuit. FIG. 8 is a diagram illustrating an example of the configuration of a sequential circuit. Fig. 9A is a diagram showing an example of the configuration of a sequential circuit, and Fig. 9B is a timing chart showing an example of a method for driving the sequential circuit. FIG. 10 is a diagram illustrating an example of a method for driving a sequential circuit. 11A and 11B are diagrams showing configuration examples of sequential circuits. Fig. 12A is a diagram showing an example of the configuration of a shift register circuit, and Fig. 12B is a timing chart showing an example of a method of driving the shift register circuit. FIG. 13 is a diagram illustrating an example of the configuration of a sequential circuit. Fig. 14A is a diagram showing an example of the configuration of a sequential circuit, and Fig. 14B is a timing chart showing an example of a method of driving the sequential circuit. 15A and 15B are diagrams showing an example of a method for driving a sequential circuit. 16A and 16B are diagrams showing an example of a method for driving a sequential circuit. 17A and 17B are diagrams showing an example of a method for driving a sequential circuit. 18A and 18B are diagrams showing an example of a method for driving a sequential circuit. 19A and 19B are diagrams showing an example of a method for driving a sequential circuit. FIG. 20 is a diagram illustrating an example of the configuration of a sequential circuit. Fig. 21A is a diagram showing an example of the configuration of a sequential circuit, and Fig. 21B is a timing chart showing an example of a method for driving the sequential circuit. 22A and 22B are diagrams illustrating configuration examples of sequential circuits. Fig. 23A is a diagram showing an example of the configuration of a shift register circuit, and Fig. 23B is a timing chart showing an example of a method of driving the shift register circuit. Fig. 24A is a diagram showing an example of the configuration of a shift register circuit, and Fig. 24B is a timing chart showing an example of a method of driving the shift register circuit. Fig. 25A is a diagram showing a configuration example of a display device, and Fig. 25B is a diagram showing a configuration example of a pixel circuit. 26A and 26B are diagrams showing configuration examples of sequential circuits. 27A and 27B are diagrams showing configuration examples of sequential circuits. FIG. 28 is a diagram illustrating an example of the configuration of a sequential circuit. FIG. 29 is a diagram illustrating an example of the configuration of a sequential circuit. FIG. 30 is a diagram illustrating an example of the configuration of a sequential circuit. FIG. 31 is a diagram illustrating an example of the configuration of a sequential circuit. FIG. 32 is a diagram illustrating an example of the configuration of a sequential circuit. FIG. 33 is a diagram illustrating an example of the configuration of a sequential circuit. 34A to 34C are diagrams showing configuration examples of a display device. 35A to 35C are diagrams showing configuration examples of a display device. 36A to 36C are diagrams showing configuration examples of light-emitting elements. FIG. 37 is a diagram showing an example of the configuration of a display device. Fig. 38A is a diagram showing a configuration example of a display device, Fig. 38B and Fig. 38C are diagrams showing configuration examples of a transistor. FIG. 39 is a diagram illustrating an example of the configuration of a display device. 40A and 40B are diagrams showing configuration examples of a display module. FIG. 41 is a diagram showing an example of the configuration of a display device. FIG. 42 is a diagram showing an example of the configuration of a display device. FIG. 43 is a diagram showing an example of the configuration of a display device. 44A and 44B are diagrams showing an example of an electronic device. 45A and 45B are diagrams showing an example of an electronic device. 46A and 46B are diagrams showing an example of an electronic device. 47A to 47D are diagrams showing an example of an electronic device. 48A to 48G are diagrams showing an example of an electronic device. 49A to 49C are graphs showing the change in potential over time. 50A to 50C are graphs showing the change in potential over time. DETAILED DESCRIPTION OF THE INVENTION

[0028] Hereinafter, embodiments will be described with reference to the drawings. However, it will be readily understood by those skilled in the art that the embodiments can be implemented in many different ways and that various changes in form and details can be made without departing from the spirit and scope of the present invention. Therefore, the present invention should not be interpreted as being limited to the following description of the embodiments.

[0029] In the configuration of the invention described below, the same parts or parts having similar functions are denoted by the same reference numerals in different drawings, and repeated explanations thereof will be omitted. In addition, when referring to similar functions, the same hatch pattern may be used and no particular reference numeral may be assigned.

[0030] In the drawings described in this specification, the size of each component, the thickness of a layer, or an area may be exaggerated for clarity, and therefore, the drawings are not necessarily limited to the scale.

[0031] In this specification, ordinal numbers such as "first" or "second" are used to avoid confusion of components and do not limit the number.

[0032] A transistor is a type of semiconductor element that can, for example, amplify a current or a voltage. Furthermore, a transistor can perform a switching operation to control conduction or non-conduction. The term "transistor" as used herein includes an insulated gate field effect transistor (IGFET) and a thin film transistor (TFT).

[0033] Furthermore, the functions of "source" and "drain" may be interchanged when transistors of different polarities are used, when the direction of current flow changes during circuit operation, etc. Therefore, in this specification, the terms "source" and "drain" may be used interchangeably.

[0034] Furthermore, in this specification, "electrically connected" includes connection via "something that has some kind of electrical action." Here, "something that has some kind of electrical action" is not particularly limited as long as it allows electrical signals to be transmitted and received between the connected objects. For example, "something that has some kind of electrical action" includes electrodes and wiring, as well as switching elements such as transistors, resistive elements, coils, capacitors, and other elements with various functions.

[0035] In this specification and the like, a display panel, which is one aspect of a display device, has a function of displaying (outputting), for example, an image on a display surface, and therefore the display panel is one aspect of an output device.

[0036] In addition, in this specification, a display panel having a connector such as an FPC (Flexible Printed Circuit) or TCP (Tape Carrier Package) attached to the substrate, or having an IC mounted on the substrate using a COG (Chip On Glass) method or the like, may be referred to as a display panel module, display module, or simply a display panel, etc.

[0037] (Embodiment 1) In this embodiment, structural examples of a semiconductor device and a display device according to one embodiment of the present invention will be described.

[0038] One embodiment of the present invention relates to a shift register circuit having a multi-stage sequential circuit. An output signal from a sequential circuit is input to a next-stage sequential circuit. Before and after the sequential circuit outputs a signal, the potential of the gate of a transistor included in the sequential circuit is changed in response to a clock signal to prevent voltage stress from being applied to the gate-source of the transistor for a long period of time. This can suppress fluctuations in the electrical characteristics of the transistor, such as fluctuations in threshold voltage. Therefore, the shift register circuit can be a highly reliable semiconductor device.

[0039] The semiconductor device of one embodiment of the present invention can be applied to a display device. Specifically, the semiconductor device of one embodiment of the present invention can be applied to, for example, a scan line driver circuit included in a display device. As described above, the semiconductor device of one embodiment of the present invention has high reliability. Therefore, by applying the semiconductor device of one embodiment of the present invention to a display device, the reliability of the display device can be improved.

[0040] In this specification and the like, a display device to which the semiconductor device of one embodiment of the present invention is applied is referred to as a display device of one embodiment of the present invention.

[0041] A display device according to one embodiment of the present invention includes a light-emitting element such as an organic EL element, and can display an image by controlling the luminance of light emitted from the light-emitting element. The light-emitting element includes at least a light-emitting layer, and the light-emitting layer can be separated into individual light-emitting elements. The light-emitting layer can be separated by, for example, photolithography. That is, the light-emitting layer can be separated without using a shadow mask such as a metal mask. Therefore, the display device according to one embodiment of the present invention can be a high-resolution display device.

[0042] As mentioned above, high-resolution display devices have a high pixel density, which means that, for example, a large number of pixel circuits per unit length are electrically connected to a scanning line. Therefore, the wiring capacitance of the scanning line increases due to the gate capacitance of a transistor provided in the pixel circuit and electrically connected to the scanning line. Furthermore, when a large number of pixel circuits are provided in a display device, the number of scanning lines also increases. Therefore, in order to ensure a high frame frequency, it is necessary to shorten one horizontal period, which is the period from when a signal is supplied to a scanning line to when a signal is supplied to the scanning line of the next row. As described above, the increase in wiring capacitance of the scanning lines and the shortening of one horizontal period necessitates the increase in the current flowing through the scanning lines when charging them.

[0043] For example, to increase the current flowing through the scan line, the potential of a signal output to the scan line by a scan line driver circuit, which is a semiconductor device of one embodiment of the present invention, is increased. As a result, for example, a large voltage stress is applied to a transistor electrically connected to the scan line, which is provided in the scan line driver circuit. Therefore, in a high-resolution display device or a display device with a large number of pixels, the reliability of the semiconductor device provided in the display device may be reduced.

[0044] A semiconductor device that can be applied to a display device of one embodiment of the present invention can shorten the period during which voltage stress is applied to a transistor electrically connected to a scan line, for example. Therefore, fluctuations in the electrical characteristics of the transistor, such as fluctuations in the threshold voltage, can be suppressed. Therefore, by applying the semiconductor device of one embodiment of the present invention, the reliability of the display device can be improved. As described above, the display device of one embodiment of the present invention can be a high-resolution display device with a large number of pixels and high reliability.

[0045] <Shift register circuit configuration example 1> 1A is a block diagram illustrating a configuration example of a shift register circuit 40, which is a semiconductor device of one embodiment of the present invention. The shift register circuit 40 includes a plurality of sequential circuits 10. Sequential circuits 10_1 to 10_5 are illustrated in FIG.

[0046] In this specification and the like, the sequential circuit 10 can be a semiconductor device of one embodiment of the present invention. Other circuits described in this specification and the like can also be semiconductor devices of one embodiment of the present invention. Furthermore, components of the circuits described in this specification and the like, such as transistors, can also be semiconductor devices of one embodiment of the present invention.

[0047] A signal LIN and a signal RIN are input to the sequential circuit 10. A signal OUT is output from the sequential circuit 10. A start pulse signal SP is input as the signal LIN to the sequential circuit 10_1. A signal OUT output from the preceding sequential circuit 10 is input as the signal LIN to the sequential circuits 10_2 and onward. Furthermore, in the example shown in FIG. 1A, a signal OUT output from the sequential circuit 10 two stages later is input as the signal RIN to the sequential circuit 10.

[0048] In this specification and the like, a sequential circuit 10_1 to which a start pulse signal SP is input is defined as the first stage, and a sequential circuit 10 located at the nth stage (n is an integer equal to or greater than 1) is denoted as a sequential circuit 10_n. Furthermore, signals input to the sequential circuit 10_n and signals output from the sequential circuit 10 are denoted by symbols with _n added. Similar notations are used for other sequential circuits.

[0049] In the example shown in FIG. 1A, a start pulse signal SP (signal LIN_1) and a signal RIN_1 are input to a sequential circuit 10_1, and a signal OUT_1 is output. The signal OUT_1 is input to a sequential circuit 10_2 as a signal LIN_2. The signal RIN_2 is input to the sequential circuit 10_2, and a signal OUT_2 is output. The signal OUT_2 is input to a sequential circuit 10_3 as a signal LIN_3. The signal RIN_3 is input to the sequential circuit 10_3, and a signal OUT_3 is output. The signal OUT_3 is input to the sequential circuit 10_1 as a signal RIN_1 and input to the sequential circuit 10_4 as a signal LIN_4. The signal RIN_4 is input to the sequential circuit 10_4, and a signal OUT_4 is output. The signal OUT_4 is input to the sequential circuit 10_2 as a signal RIN_2 and input to the sequential circuit 10_5 as a signal LIN_5. Furthermore, the sequential circuit 10_5 receives the signal RIN_5 as input and outputs the signal OUT_5, which is input as the signal RIN_3 to the sequential circuit 10_3.

[0050] In addition to the above signals, clock signals CLK1, CLK2, CLK3, and CLK4 are input to the sequential circuit 10. For example, three clock signals out of the clock signals CLK1, CLK2, CLK3, and CLK4 are input to one sequential circuit 10.

[0051] For example, clock signals CLK1, CLK2, and CLK3 are input to sequential circuit 10_1, clock signals CLK2, CLK3, and CLK4 are input to sequential circuit 10_2, clock signals CLK3, CLK4, and CLK1 are input to sequential circuit 10_3, clock signals CLK4, CLK1, and CLK2 are input to sequential circuit 10_4, and clock signals CLK1, CLK2, and CLK3 are input to sequential circuit 10_5. In the example shown in FIG. 1A, the combination of clock signals input to sequential circuit 10 is the same for every four stages. That is, for example, when clock signals CLK1, CLK2, and CLK3 are input to sequential circuit 10_n, clock signals CLK2, CLK3, and CLK4 are input to sequential circuit 10_n+1, clock signals CLK3, CLK4, and CLK1 are input to sequential circuit 10_n+2, and clock signals CLK4, CLK1, and CLK2 are input to sequential circuit 10_n+3. The combination of clock signals input to sequential circuit 10_n and the combination of clock signals input to sequential circuit 10_n+4 are the same.

[0052] In this specification, a clock signal refers to a signal in which high and low potentials are repeated and the interval between the rising edge of one potential and the rising edge of the next potential, or the interval between the falling edge of one potential and the falling edge of the next potential, is constant.

[0053] In addition, in this specification and the like, a high potential may be expressed as a potential VDD, and a low potential may be expressed as a potential VSS.

[0054] The configuration of the shift register circuit 40 is not limited to the configuration shown in Fig. 1A. For example, Fig. 1A shows a configuration in which three of four types of clock signals are input to the sequential circuit 10, but a configuration in which three or more of five or more types of clock signals are input may also be used. Furthermore, Fig. 1A shows a configuration in which the signal RIN input to the sequential circuit 10 is the signal OUT output by the sequential circuit 10 two stages later, but it may also be the signal OUT output by the sequential circuit 10 three or more stages later.

[0055] <Example of a shift register circuit driving method_1> 1B is a timing chart showing an example of a method for driving the shift register circuit 40. From the top to the bottom, FIG. 1B shows the transition of potential changes for the start pulse signal SP, the clock signals CLK1 to CLK4, and the signals OUT_1 to OUT_5. Note that the timing chart shown in FIG. 1B does not take into account the influence of the threshold voltage of the transistor, the resistance of the transistor in the on-state, the gate capacitance of the transistor, the wiring resistance, the parasitic capacitance, and the like. The same applies to other timing charts unless otherwise noted.

[0056] 1B, the clock signals CLK1 to CLK4 may be signals that are shifted by a quarter cycle from one another. The high potential periods of the clock signals CLK1 to CLK4 may not overlap. The high potential periods of the clock signals CLK1 to CLK4 may overlap in part.

[0057] 1B, the start pulse signal SP is at a high potential and the clock signal CLK1 is at a low potential, and the potentials of the signals OUT_1 to OUT_5 are also at a low potential.

[0058] At time T100, the clock signal CLK1 changes from low potential to high potential, that is, the clock signal CLK1 rises, causing the sequential circuit 10_1 to output a high-potential signal OUT_1. Next, in response to the rising edges of the clock signals CLK2 to CLK4, the sequential circuits 10_2 to 10_4 sequentially output high-potential signals OUT_2 to OUT_4. Thereafter, in response to the rising edges of the clock signals CLK1 to CLK4, the sequential circuits 10_5 and subsequent circuits sequentially output high-potential signals OUT_5 and subsequent.

[0059] <Example of sequential circuit configuration_1> 2 is a circuit diagram showing an example of the configuration of a sequential circuit 10a that can be applied to the sequential circuit 10. The sequential circuit 10a includes a circuit 11a and a circuit 12. The circuits 11a and 12 are electrically connected via a wiring Wa. The circuits 11a and 12 are also electrically connected via a wiring Wb. The circuit 12 can be called a control circuit.

[0060] In this specification and the like, the high potential and the low potential are in a relationship of inverted potentials, that is, the high potential is an inverted potential of the low potential, and the low potential is an inverted potential of the high potential.

[0061] Signals LIN and RIN are input to the circuit 12. The circuit 12 has a function of supplying potentials based on the potentials of the signals LIN and RIN as control potentials to the wirings Wa and Wb. For example, when the potential of the signal LIN is high and the potential of the signal RIN is low, the circuit 12 supplies a high control potential to the wiring Wa and a low control potential to the wiring Wb. When the potential of the signal LIN is low and the potential of the signal RIN is high, the circuit 12 supplies a low control potential to the wiring Wa and a high control potential to the wiring Wb. In other words, for example, if the potential supplied by the circuit 12 to the wiring Wa is a first control potential and the potential supplied by the circuit 12 to the wiring Wb is a second control potential, when the potential of the signal RIN is an inverted potential of the potential of the signal LIN, the second control potential can be an inverted potential of the first control potential.

[0062] The circuit 11a includes a transistor 21, a transistor 22, a transistor 23, and a transistor 24. For the transistors 21 to 24, a metal oxide (hereinafter also referred to as an oxide semiconductor) exhibiting semiconductor characteristics can be preferably used as a semiconductor in which a channel is formed. Note that the semiconductor is not limited to an oxide semiconductor, and a semiconductor such as silicon (single crystal silicon, polycrystalline silicon, or amorphous silicon), germanium, or a compound semiconductor may also be used. The same applies to transistors included in circuits other than the circuit 11a.

[0063] In the following description, unless otherwise noted, all transistors included in a circuit or the like according to one embodiment of the present invention are n-channel transistors. However, the following description can also be applied to a case where some or all of the transistors are p-channel transistors by, for example, switching between high and low potentials as needed.

[0064] The gate of the transistor 21 is electrically connected to the wiring Wa. The gate of the transistor 22, one of the source or drain of the transistor 23, and one of the source or drain of the transistor 24 are electrically connected to the wiring Wb. One of the source or drain of the transistor 21 is electrically connected to one of the source or drain of the transistor 22, and a signal OUT is output from the transistor 21.

[0065] The other of the source and drain of the transistor 21 is connected to a clock signal CLK. i1 The gate of the transistor 23 receives the clock signal CLK. i2 The gate of the transistor 24 receives the clock signal CLK. i3 is entered.

[0066] Here, the clock signal CLK i1 to clock signal CLK i3 1A and the like. For example, in the sequential circuit 10_1 and the sequential circuit 10_5, the clock signal CLKi1 is the clock signal CLK1, and the clock signal CLK i2 is the clock signal CLK2, and the clock signal CLK i3 is the clock signal CLK3. In the sequential circuit 10_2, the clock signal CLK i1 is the clock signal CLK2, and the clock signal CLK i2 is the clock signal CLK3, and the clock signal CLK i3 is the clock signal CLK4. In the sequential circuit 10_3, the clock signal CLK i1 is the clock signal CLK3, and the clock signal CLK i2 is the clock signal CLK4, and the clock signal CLK i3 is the clock signal CLK1. Furthermore, in the sequential circuit 10_4, the clock signal CLK i1 is the clock signal CLK4, and the clock signal CLK i2 is the clock signal CLK1, and the clock signal CLK i3 is the clock signal CLK2.

[0067] A low potential is supplied to the other of the source or drain of the transistor 22 and the other of the source or drain of the transistor 23. A high potential is supplied to the other of the source or drain of the transistor 24. Here, the potential supplied to the other of the source or drain of the transistor 22 is a first potential, the potential supplied to the other of the source or drain of the transistor 23 is a second potential, and the potential supplied to the other of the source or drain of the transistor 24 is a third potential. In this case, the difference between the third potential and the first potential and the difference between the third potential and the second potential are larger than the difference between the second potential and the first potential. The third potential can be an inverted potential of the first potential or an inverted potential of the second potential.

[0068] In this specification, unless otherwise specified, when a potential difference is said to be small, it means that the "absolute value" of the potential difference is small. Even if not otherwise specified, the potential difference may be said to be small when the sign is taken into consideration, that is, when the potential difference is large in the negative direction.

[0069] Fig. 3A is a circuit diagram illustrating a more detailed configuration example of the sequential circuit 10a illustrated in Fig. 2. A circuit 12 included in the sequential circuit 10 includes a transistor 31, a transistor 32, a transistor 33, and a transistor .

[0070] One of the source or drain of the transistor 31 and one of the source or drain of the transistor 32 are electrically connected to a wiring Wa. The gate of the transistor 32, one of the source or drain of the transistor 33, and one of the source or drain of the transistor 34 are electrically connected to a wiring Wb. A signal LIN is input to the gate of the transistor 31 and the gate of the transistor 34. A signal RIN is input to the gate of the transistor 33.

[0071] A high potential is supplied to the other of the source or the drain of the transistor 31 and the other of the source or the drain of the transistor 33. A low potential is supplied to the other of the source or the drain of the transistor 32 and the other of the source or the drain of the transistor 34. Thus, if the potential supplied to the other of the source or the drain of the transistor 31 is a fourth potential, the potential supplied to the other of the source or the drain of the transistor 32 is a fifth potential, the potential supplied to the other of the source or the drain of the transistor 33 is a sixth potential, and the potential supplied to the other of the source or the drain of the transistor 34 is a seventh potential, the fifth potential can be an inverted potential of the fourth potential, and the seventh potential can be an inverted potential of the sixth potential.

[0072] <Example of how to drive a sequential circuit_1> An example of a method for driving the sequential circuit 10a shown in Fig. 3A will be described below with reference to Fig. 3B and Fig. 4A to Fig. 7B. Fig. 3B is a timing chart showing an example of a method for driving the sequential circuit 10a shown in Fig. 3A. In Fig. 3B, from the top, a signal LIN, a signal RIN, a clock signal CLK i1 to clock signal CLK i44A to 7B show the transition of potential changes for the wiring Wa, the wiring Wb, and the signal OUT. Also, Figures 4A to 7B are circuit diagrams showing an example of a method for driving the sequential circuit 10a.

[0073] Here, the clock signal CLK i4 For example, among the clock signals CLK1 to CLK4 shown in FIG. 1A, the clock signal CLK i1 to clock signal CLK i3 For example, in the sequential circuit 10_1 and the sequential circuit 10_5, the clock signal CLK i4 is the clock signal CLK4. In the sequential circuit 10_2, the clock signal CLK i4 is the clock signal CLK1. In addition, in the sequential circuit 10_3, the clock signal CLK i4 is the clock signal CLK2. Furthermore, in the sequential circuit 10_4, the clock signal CLK i4 is the clock signal CLK3.

[0074] 4A to 7B, transistors in an off state are marked with an x. High potential is indicated by "H" and low potential is indicated by "L." Similar notations are used in other circuit diagrams showing how the circuits are driven.

[0075] Before time T101, the potential of the signal LIN, the potential of the signal RIN, and the potential of the clock signal CLK i1 potential, clock signal CLK i2 potential, clock signal CLK i4 The potential of the wiring Wa and the potential of the signal OUT are low. i3 and the potential of the wiring Wb are assumed to be high.

[0076] 4A is a circuit diagram showing the state of the sequential circuit 10a from time T101 to time T102. At time T101, the potential of the signal LIN becomes high. Also, the clock signal CLK i3 The potential of the clock signal CLK becomes low. i4The potential of the signal LIN becomes high. When the potential of the signal LIN becomes high, the transistors 31 and 34 are turned on. When the transistor 31 is turned on, the potential of the wiring Wa becomes high, and the transistor 21 is turned on. When the transistor 34 is turned on, the potential of the wiring Wb becomes low, and the transistors 22 and 32 are turned off.

[0077] 4B is a circuit diagram showing the state of the sequential circuit 10a from time T102 to time T103. In FIG. 4B, signals whose potentials have changed from time T101 to time T102 are shown enclosed by dashed lines.

[0078] At time T102, the potential of the signal LIN becomes low. i1 becomes high potential, and the clock signal CLK i4 The potential of the signal LIN becomes low. When the potential of the signal LIN becomes low, the transistor 31 is turned off, so the wiring Wa becomes a floating state, but the transistor 21 remains on. In this state, the clock signal CLK i1 When the potential of the signal OUT becomes high, the potential of the signal OUT becomes high.

[0079] Fig. 5A is a circuit diagram showing the state of the sequential circuit 10a from time T103 to time T104. In Fig. 5A, signals whose potentials have changed from time T102 to time T103 are shown enclosed by dashed lines.

[0080] At time T103, the clock signal CLK i1 The potential of the clock signal CLK becomes low. i2 The transistor 21 is in the on state from time T102 to time T103, and therefore the potential of the clock signal CLK i1 When the potential of the clock signal CLK becomes low, the potential of the signal OUT becomes low. i2 When the potential of the transistor 23 becomes high, the transistor 23 is turned on.

[0081] 5B is a circuit diagram showing the state of the sequential circuit 10a from time T104 to time T105. In FIG. 5B, signals and wirings whose potentials have changed from time T103 to time T104 are shown surrounded by dashed lines.

[0082] At time T104, the potential of the signal RIN becomes high. i2 The potential of the clock signal CLK becomes low. i3 When the potential of the signal RIN becomes high, the transistor 33 is turned on, and the clock signal CLK i3 When the potential of the clock signal CLK becomes high, the transistor 24 is turned on. i2 The potential of the wiring Wb becomes low, so that the transistor 23 is turned off. As a result, the potential of the wiring Wb becomes high. As the potential of the wiring Wb becomes high, the transistors 22 and 32 are turned on. As the transistor 32 is turned on, the potential of the wiring Wa becomes low, so that the transistor 21 is turned off. As the transistor 21 is turned off and the transistor 22 is turned on, the potential of the signal OUT becomes low, so that the potential of the clock signal CLK i1 The potential is low regardless of the potential of the

[0083] 6A is a circuit diagram showing the state of the sequential circuit 10a from time T105 to time T106. In FIG. 6A, signals whose potentials have changed from time T104 to time T105 are shown enclosed by dashed lines.

[0084] At time T105, the potential of the signal RIN becomes low. i3 The potential of the clock signal CLK becomes low. i4 When the potential of the signal RIN becomes low, the transistor 33 is turned off, and the clock signal CLK i3 When the potential of the wiring Wb becomes low, the transistor 24 is turned off, and the wiring Wb is brought into a floating state.

[0085] Fig. 6B is a circuit diagram showing the state of the sequential circuit 10a from time T106 to time T107. In Fig. 6B, signals whose potentials have changed from time T105 to time T106 are shown enclosed by dashed lines.

[0086] At time T106, the clock signal CLK i1 becomes high potential, and the clock signal CLK i4 The potential of the clock signal CLK becomes low. i1 becomes high, but the potential of the signal OUT does not change because the transistor 21 is off.

[0087] 7A is a circuit diagram showing the state of the sequential circuit 10a from time T107 to time T108. In FIG. 7A, signals and wirings whose potentials have changed from time T106 to time T107 are shown surrounded by dashed lines.

[0088] At time T107, the clock signal CLK i1 The potential of the clock signal CLK becomes low. i2 The potential of the clock signal CLK becomes high. i2 As a result, the potential of the wiring Wb becomes low, and the transistors 22 and 32 are turned off.

[0089] 7B is a circuit diagram showing the state of the sequential circuit 10a from time T108 to time T109. In FIG. 7B, signals and wirings whose potentials have changed from time T107 to time T108 are shown surrounded by dashed lines.

[0090] At time T108, the clock signal CLK i2 The potential of the clock signal CLK becomes low. i3 The potential of the clock signal CLK becomes high. i2 When the potential of the clock signal CLK becomes low, the transistor 23 is turned off. i3The potential of the wiring Wb becomes high, turning on the transistor 24. As a result, the potential of the wiring Wb becomes high, turning on the transistors 22 and 32.

[0091] At time T109, the clock signal CLK i3 The potential of the clock signal CLK becomes low. i4 The potential of the clock signal CLK becomes high. i3 When the potential of the wiring Wb becomes low, the transistor 24 is turned off, and the wiring Wb is brought into a floating state.

[0092] From time T110 to time T114, the sequential circuit 10a performs the same operation as from time T106 to time T110. The same operation as from time T106 to time T110 is repeated until, for example, the final-stage sequential circuit 10a outputs a high-potential signal OUT. Note that the same operation as from time T106 to time T110 is also performed before time T101.

[0093] Here, by providing the transistor 24 in the circuit 11a, the clock signal CLK i1 The potential of the wiring Wb can be set to a high potential during the period when the clock signal CLK i1 During the period when the potential of the clock signal CLK fluctuates from a low potential to a high potential, the transistor 32 is in an on state. Therefore, the wiring Wa is not in a floating state during this period. Therefore, it is possible to suppress the potential rise of the wiring Wa due to, for example, the bootstrap effect caused by the gate capacitance of the transistor 21. Therefore, the clock signal CLK i1 This can prevent the transistor 21 from unintentionally turning on during a period when the potential of the wiring Wa is high, thereby preventing the potential of the signal OUT from increasing. This can prevent the shift register circuit 40 from malfunctioning. As a result, the shift register circuit 40 can be a highly reliable semiconductor device. i1If the shift register circuit 40 does not malfunction even when the potential of the wiring Wb is low during a period when the potential of the wiring Wb is high, or if the malfunction is within an acceptable range, the transistor 24 can be omitted.

[0094] The above is an example of the method for driving the sequential circuit 10a.

[0095] The sequential circuit 10, which is a semiconductor device of one embodiment of the present invention, includes a transistor 23, and a clock signal is input to the gate of the transistor 23. For example, if the sequential circuit 10 does not include the transistor 23, the potential of the wiring Wb is constantly high after time T104. Although not shown in FIG. 3B , the potential of the wiring Wb is constantly high even before time T101. As a result, voltage stress is applied for a long period between the gate and source of the transistor 22 and between the gate and source of the transistor 32, which makes it easier for the threshold voltages of the transistors 22 and 32 to fluctuate. On the other hand, in one embodiment of the present invention, as shown in FIG. 3B , the potential of the wiring Wb is constantly low after time T104. Although not shown in FIG. 3B , the potential of the wiring Wb is constantly low before time T101. In FIG. 3B , the period in which the potential of the wiring Wb is low after time T104 is indicated by a dashed line.

[0096] By periodically setting the potential of the wiring Wb to a low potential, the period during which voltage stress is applied between the gate and source of the transistor 22 and between the gate and source of the transistor 32 can be shortened compared to when the potential of the wiring Wb remains high for a long period of time. This can suppress fluctuations in the electrical characteristics of the transistors 22 and 32, such as fluctuations in threshold voltage. Therefore, the sequential circuit 10 can be a highly reliable semiconductor device.

[0097] Note that the signal input to the gate of the transistor 23 does not have to be a clock signal. For example, a signal whose potential is controlled independently of other signals may be input to the gate of the transistor 23. This can lengthen the period during which the potential of the wiring Wb is low, for example, and shorten the period during which voltage stress is applied between the gate and source of the transistor 22 and between the gate and source of the transistor 32. This can further improve the reliability of the sequential circuit 10.

[0098] <Example of sequential circuit configuration_2> 8 is a circuit diagram illustrating an example of a configuration of a sequential circuit 10b that can be used in the sequential circuit 10. The sequential circuit 10b includes a circuit 11b and a circuit 12. The circuit 11b is a modified example of the circuit 11a and differs from the circuit 11a in that it includes a transistor 25.

[0099] One of the source and the drain of the transistor 25 is electrically connected to one of the source and the drain of the transistor 21 and one of the source and the drain of the transistor 22. The gate of the transistor 25 receives a clock signal CLK i2 is entered.

[0100] A low potential is supplied to the other of the source and the drain of the transistor 25. Therefore, if the potential supplied to the other of the source and the drain of the transistor 25 is an eighth potential, the difference between the first potential and the eighth potential and the difference between the second potential and the eighth potential are smaller than the difference between the third potential and the eighth potential. The eighth potential can be an inverted potential of the third potential.

[0101] The sequential circuit 10b can be driven by, for example, a method similar to that shown in FIG. 3B. In this case, even during periods when both the potential of the wiring Wa and the potential of the wiring Wb are low and both the transistor 21 and the transistor 22 are off, such as from time T107 to time T108 and from time T111 to time T112 shown in FIG. 3B, the source or drain of the transistor 21 can be prevented from floating. Therefore, malfunction of the shift register circuit 40 caused by the potential of the signal OUT becoming an unintended potential can be prevented. As a result, the shift register circuit 40 can be a highly reliable semiconductor device.

[0102] <Example of sequential circuit configuration_3> 9 is a circuit diagram illustrating an example of a configuration of a sequential circuit 10c that can be applied to the sequential circuit 10. The sequential circuit 10c includes a circuit 11c and a circuit 12. The circuit 11c is a modified example of the circuit 11a, and differs from the circuit 11a in that it includes a transistor 26 and a capacitor 27.

[0103] One of the source or drain of the transistor 21 is electrically connected to one of the source or drain of the transistor 22 and one electrode of the capacitor 27. One of the source or drain of the transistor 26 is electrically connected to the circuit 12 via a wiring Wa. The other of the source or drain of the transistor 26 is electrically connected to the gate of the transistor 21. The gate of the transistor 21 is electrically connected to the other electrode of the capacitor 27. A node to which the gate of the transistor 21, the other of the source or drain of the transistor 26, and the other electrode of the capacitor 27 are electrically connected is referred to as a node N. A high potential can be supplied to the gate of the transistor 26.

[0104] <Example of how to drive a sequential circuit_2> Fig. 9B is a timing chart showing an example of a method for driving the sequential circuit 10c shown in Fig. 9A. Fig. 9B shows the transition of potential changes of the node N in addition to the transition of potential changes of the signals and wirings shown in Fig. 3B.

[0105] Signal LIN, signal RIN, and clock signal CLK from time T121 to time T134 i1 to clock signal CLK i4 The potential changes of the wiring Wa, the wiring Wb, and the signal OUT can be similar to those from time T101 to time T114 shown in FIG. 3B. The potential of the node N before time T121 is low.

[0106] At time T121, the signal LIN becomes high, turning on the transistor 31, and the potential of the wiring Wa becomes high. As a result, from time T121 to time T122, the potential of the node N increases to a potential that is lower than the potential of the wiring Wa by the threshold voltage of the transistor 26.

[0107] 10 is a circuit diagram showing the state of the sequential circuit 10c from time T122 to time T123. In FIG. 10, "L→H" indicates a change from low potential to high potential at time T122, and "H→L" indicates a change from high potential to low potential at time T122. Also, in FIG. 10, the clock signal CLK i1 , and node N are shown surrounded by dashed lines for emphasis.

[0108] At time T122, the clock signal CLK i1 After the potential of the node N rises to a potential that is lower than the potential of the wiring Wa by the threshold voltage of the transistor 26, the clock signal CLK i1 As the potential at node N changes from a low potential to a high potential, the potential at node N rises due to the bootstrap effect. As the potential at node N rises, the potential difference between the gate and source of transistor 26 becomes smaller than the threshold voltage of transistor 26 (increases in the negative direction). This turns transistor 26 off, and node N becomes floating. Here, the potential at node N at time T123 is set to a potential VN H Let's say.

[0109] If the sequential circuit 10 does not have the transistor 26 and the capacitor 27, the clock signal CLK i1 A potential that is lower than the high potential of the transistor 26 by the threshold voltage of the transistor 21 is output as the signal OUT. On the other hand, since the sequential circuit 10 includes the transistor 26 and the capacitor 27, the gate potential of the transistor 21 rises to a potential that is nearly twice the potential VDD (for example, a potential that is nearly twice the difference between the potential VDD and the potential VSS). As a result, the clock signal CLK is not affected by the threshold voltage of the transistor 21. i1 This makes it possible to realize a sequential circuit 10 with high output performance without increasing the number of types of power supply potentials.

[0110] As described above, for example, when the potential of the node N is the potential VN H In this case, the transistor 26 is turned off. This can prevent the potential of the wiring Wa from increasing from time T122 to time T123. This can prevent a high voltage from being applied to the transistor 31 and the transistor 32. Therefore, the sequential circuit 10c can be a highly reliable semiconductor device.

[0111] At time T123, the clock signal CLK i1 As a result, the potential of the node N drops from time T123 to time T124. For example, the potential drops to approximately the same level as the potential of the node N from time T121 to time T122.

[0112] At time T124, the wiring Wb becomes high potential, turning on the transistor 32, and the potential of the wiring Wa becomes low potential. As a result, the potential difference between the gate and source of the transistor 26 becomes equal to or greater than the threshold voltage of the transistor 26, turning on the transistor 26. Therefore, the potential of the node N becomes low potential from time T124 to time T125. Furthermore, the potential of the node N also becomes low potential after time T125. This is an example of a method for driving the sequential circuit 10c.

[0113] <Sequential circuit configuration example 4> 11A is a circuit diagram showing an example of the configuration of a sequential circuit 10d that can be applied to the sequential circuit 10. The sequential circuit 10d includes a circuit 11d and a circuit 12. The circuit 11d is a modified example of the circuit 11c, and a clock signal CLK is applied to the gate of the transistor 26. i4 The difference from the circuit 11c is that the input is

[0114] When the potential of the gate of the transistor 26 is high and the potential of the wiring Wa or the potential of the node N is low, voltage stress is applied between the gate and source of the transistor 26. Therefore, when the clock signal CLK i4 By inputting the voltage Vout, the period during which voltage stress is applied between the gate and source of the transistor 26 can be shortened. This can suppress fluctuations in the electrical characteristics of the transistor 26, such as fluctuations in the threshold voltage. Therefore, the sequential circuit 10d can be a highly reliable semiconductor device.

[0115] Furthermore, by inputting a clock signal to the gate of the transistor 26, it is possible to more easily control the driving of the sequential circuit 10 than when a signal whose potential is controlled independently of other signals is input to the gate of the transistor 26. Note that a signal whose potential is controlled independently of other signals may also be input to the gate of the transistor 26. In this case, for example, the period during which the gate potential of the transistor 26 is low can be extended, thereby shortening the period during which voltage stress is applied between the gate and source of the transistor 26. This further improves the reliability of the sequential circuit 10d.

[0116] <Sequential circuit configuration example 5> 11B is a circuit diagram showing an example configuration of a sequential circuit 10e that can be applied to the sequential circuit 10. The sequential circuit 10e includes a circuit 11e and a circuit 12. The circuit 11e is a modified example of the circuit 11d, and differs from the circuit 11d in that it includes a transistor 25. The circuit 11e has a configuration that combines the configurations of the circuit 11b and the circuit 11d.

[0117] <Shift register circuit configuration example 2> 12A is a block diagram illustrating a configuration example of a shift register circuit 140, which is a semiconductor device of one embodiment of the present invention. The shift register circuit 140 is a modified example of the shift register circuit 40 illustrated in FIG. 1A, and includes a sequential circuit 110 instead of the sequential circuit 10.

[0118] In the shift register circuit 140, for example, the signal OUT_4 is input to the sequential circuit 110_1 as the signal RIN_1. Furthermore, the signal OUT_5 is input to the sequential circuit 110_2 as the signal RIN_2. That is, the signal RIN input to the sequential circuit 110 can be the signal OUT output by the sequential circuit 110 three stages later. Note that the signal RIN input to the sequential circuit 110 may also be the signal OUT output by the sequential circuit 110 four or more stages later.

[0119] Furthermore, in addition to the clock signals CLK1 to CLK4, a clock signal CLK5 is also input to the sequential circuit 110. Furthermore, for example, four clock signals out of the clock signals CLK1 to CLK5 can be input to one sequential circuit 110.

[0120] 12A, the combination of clock signals CLK1, CLK2, CLK3, and CLK4 is input to the sequential circuit 110_1, the clock signal CLK2, the clock signal CLK3, the clock signal CLK4, and the clock signal CLK5 is input to the sequential circuit 110_2, the clock signal CLK3, the clock signal CLK4, the clock signal CLK5, and the clock signal CLK1 is input to the sequential circuit 110_3, the clock signal CLK4, the clock signal CLK5, the clock signal CLK1, and the clock signal CLK2 is input to the sequential circuit 110_5, and the clock signal CLK5, the clock signal CLK1, the clock signal CLK2, and the clock signal CLK3 is input to the sequential circuit 110. For example, if clock signals CLK1, CLK2, CLK3, and CLK4 are input to sequential circuit 10_n, clock signals CLK2, CLK3, CLK4, and CLK5 are input to sequential circuit 10_n+1, clock signals CLK3, CLK4, CLK5, and CLK1 are input to sequential circuit 10_n+2, clock signals CLK4, CLK5, CLK1, and CLK2 are input to sequential circuit 10_n+3, and clock signals CLK5, CLK1, CLK2, and CLK3 are input to sequential circuit 10_n+4. The combination of clock signals input to sequential circuit 10_n and the combination of clock signals input to sequential circuit 10_n+5 are the same. The shift register circuit 140 may be configured to receive four or more of the six or more clock signals.

[0121] <Example of shift register circuit driving method_2> Fig. 12B is a timing chart showing an example of a method for driving the shift register circuit 140. Fig. 12B shows, from the top, the transition of potential changes for the start pulse signal SP, the clock signals CLK1 to CLK5, and the signals OUT_1 to OUT_5.

[0122] 12B, the clock signals CLK1 to CLK5 may be shifted by one-fifth of a cycle. The high potential periods of the clock signals CLK1 to CLK5 may overlap. For example, the high potential periods of two clock signals may overlap.

[0123] 12B, the start pulse signal SP is at a high potential and the clock signal CLK1 is at a low potential, and the potentials of the signals OUT_1 to OUT_5 are also at a low potential.

[0124] At time T200, the clock signal CLK1 changes from low potential to high potential, that is, the clock signal CLK1 rises, causing the sequential circuit 110_1 to output a high-potential signal OUT_1. Next, in response to the rising edges of the clock signals CLK2 to CLK5, the sequential circuits 10_2 to 10_5 sequentially output high-potential signals OUT_2 to OUT_5. Thereafter, in response to the rising edges of the clock signals CLK1 to CLK5, the sequential circuits 10_6 and subsequent circuits sequentially output high-potential signals OUT_6 and subsequent.

[0125] <Example of sequential circuit configuration_6> 13 is a circuit diagram showing an example of the configuration of a sequential circuit 110a that can be applied to the sequential circuit 110. The sequential circuit 110a includes a circuit 111a and a circuit 12. The circuit 111a and the circuit 12 are electrically connected via a wiring Wa. The circuit 111a and the circuit 12 are also electrically connected via a wiring Wb.

[0126] The circuit 111a includes a transistor 21, a transistor 22, a transistor 171, a transistor 172, a transistor 173, and a transistor 174. The gate of the transistor 21 is electrically connected to a wiring Wa. The gate of the transistor 22, one of the source or the drain of the transistor 171, and one of the source or the drain of the transistor 174 are electrically connected to a wiring Wb. The other of the source or the drain of the transistor 171 is electrically connected to one of the source or the drain of the transistor 172. The other of the source or the drain of the transistor 174 is electrically connected to one of the source or the drain of the transistor 173. The one of the source or the drain of the transistor 21 is electrically connected to one of the source or the drain of the transistor 22, and a signal OUT is output from the transistor 21.

[0127] The other of the source and drain of the transistor 21 is connected to a clock signal CLK. j1 The gate of the transistor 171 receives the clock signal CLK. j2 The gate of the transistor 172 and the gate of the transistor 173 receive the clock signal CLK. j3 The gate of the transistor 174 receives the clock signal CLK. j4 is entered.

[0128] Here, the clock signal CLK j1 to clock signal CLK j4 12A and the like. For example, in the sequential circuit 110_1, the clock signal CLK j1 is the clock signal CLK1, and the clock signal CLK j2 is the clock signal CLK2, and the clock signal CLK j3 is the clock signal CLK3, and the clock signal CLK j4 is the clock signal CLK4. In the sequential circuit 110_2, the clock signal CLK j1 is the clock signal CLK2, and the clock signal CLK j2 is the clock signal CLK3, and the clock signal CLKj3 is the clock signal CLK4, and the clock signal CLK j4 is the clock signal CLK5. In addition, in the sequential circuit 110_3, the clock signal CLK j1 is the clock signal CLK3, and the clock signal CLK j2 is the clock signal CLK4, and the clock signal CLK j3 is the clock signal CLK5, and the clock signal CLK j4 is the clock signal CLK1. In addition, in the sequential circuit 110_4, the clock signal CLK j1 is the clock signal CLK4, and the clock signal CLK j2 is the clock signal CLK5, and the clock signal CLK j3 is the clock signal CLK1, and the clock signal CLK j4 is the clock signal CLK2. Furthermore, in the sequential circuit 110_5, the clock signal CLK j1 is the clock signal CLK5, and the clock signal CLK j2 is the clock signal CLK1, and the clock signal CLK j3 is the clock signal CLK2, and the clock signal CLK j4 is the clock signal CLK3.

[0129] A low potential is supplied to the other of the source or the drain of the transistor 22 and the other of the source or the drain of the transistor 172. A high potential is supplied to the other of the source or the drain of the transistor 173. Here, the potential supplied to the other of the source or the drain of the transistor 22 is a first potential, the potential supplied to the other of the source or the drain of the transistor 172 is a second potential, and the potential supplied to the other of the source or the drain of the transistor 173 is a third potential. In this case, the difference between the third potential and the first potential and the difference between the third potential and the second potential in the sequential circuit 110a are larger than the difference between the second potential and the first potential in the sequential circuit 110a. The third potential in the sequential circuit 110a can be an inverted potential of the first potential or an inverted potential of the second potential in the sequential circuit 110a.

[0130] Fig. 14A is a circuit diagram showing a more detailed example of the configuration of the sequential circuit 110a illustrated in Fig. 13. The configuration of the circuit 12 shown in Fig. 14A can be the same as that of the circuit 12 shown in Fig. 3A, for example.

[0131] <Example of how to drive a sequential circuit_3> An example of a method for driving the sequential circuit 110a shown in Fig. 14A will be described below with reference to Fig. 14B and Fig. 15A to Fig. 19B. Fig. 14B is a timing chart showing an example of a method for driving the sequential circuit 110a shown in Fig. 14A. In Fig. 14B, from the top, signals LIN, RIN, and clock signal CLK are shown. j1 to clock signal CLK j5 15A to 19B show the transition of potential changes for the wiring Wa, the wiring Wb, and the signal OUT. Also, Figures 15A to 19B are circuit diagrams showing an example of a method for driving the sequential circuit 110a.

[0132] Here, the clock signal CLK j5 For example, among the clock signals CLK1 to CLK5 shown in FIG. 12A, the clock signal CLK j1 to clock signal CLK j4 For example, in the sequential circuit 10_1, the clock signal CLK j5 is the clock signal CLK5. In addition, in the sequential circuit 10_2, the clock signal CLK j5 is the clock signal CLK1. In addition, in the sequential circuit 10_3, the clock signal CLK j5 is the clock signal CLK2. In the sequential circuit 10_4, the clock signal CLK j5 is the clock signal CLK3. Furthermore, in the sequential circuit 10_5, the clock signal CLK j5 is the clock signal CLK4.

[0133] Before time T201, the potential of the signal LIN, the potential of the signal RIN, the potential of the clock signal CLK j1 potential, clock signal CLK j2 potential, clock signal CLK j5The potential of the wiring Wa and the potential of the signal OUT are low. j3 potential, clock signal CLK j4 and the potential of the wiring Wb are assumed to be high.

[0134] 15A is a circuit diagram showing the state of the sequential circuit 110a from time T201 to time T202. At time T201, the potential of the signal LIN becomes high. Also, the clock signal CLK j3 The potential of the clock signal CLK becomes low. j5 The potential of the signal LIN becomes high. When the potential of the signal LIN becomes high, the transistors 31 and 34 are turned on. When the transistor 31 is turned on, the potential of the wiring Wa becomes high, and the transistor 21 is turned on. When the transistor 34 is turned on, the potential of the wiring Wb becomes low, and the transistors 22 and 32 are turned off.

[0135] Fig. 15B is a circuit diagram showing the state of the sequential circuit 110a from time T202 to time T203. In Fig. 15B, signals whose potentials have changed from time T201 to time T202 are shown enclosed by dashed lines.

[0136] At time T202, the clock signal CLK j1 becomes high potential, and the clock signal CLK j4 The potential of the wiring Wa remains high and the transistor 21 is on, so that the potential of the clock signal CLK j1 When the potential of the signal OUT becomes high, the potential of the signal OUT becomes high.

[0137] Fig. 16A is a circuit diagram showing the state of the sequential circuit 110a from time T203 to time T204. In Fig. 16A, signals whose potentials have changed from time T202 to time T203 are shown enclosed by dashed lines.

[0138] At time T203, the potential of the signal LIN becomes low. j2 becomes high potential, and the clock signal CLK j5 The potential of the signal LIN becomes low. When the potential of the signal LIN becomes low, the transistor 31 is turned off, and the wiring Wa becomes a floating state, but the transistor 21 remains on. In addition, the potential of the clock signal CLK j1 The potential of the signal OUT remains high from time T202 to time T203. As a result, the potential of the signal OUT remains high from time T202 to time T203. j2 When the potential of the transistor 171 becomes high, the transistor 171 is turned on.

[0139] Fig. 16B is a circuit diagram showing the state of the sequential circuit 110a from time T204 to time T205. In Fig. 16B, signals whose potentials have changed from time T203 to time T204 are shown enclosed by dashed lines.

[0140] At time T204, the clock signal CLK j1 The potential of the clock signal CLK becomes low. j3 The transistor 21 is in the on state from time T203 to time T204, and therefore the potential of the clock signal CLK j1 When the potential of the signal OUT becomes low, the potential of the signal OUT becomes low.

[0141] Between time T204 and time T205, the clock signal CLK j3 As a result, the transistors 172 and 173 are turned on. j2 Since the transistor 171 and the transistor 172 are turned on, a low potential is supplied to the wiring Wb.

[0142] Fig. 17A is a circuit diagram showing the state of the sequential circuit 110a from time T205 to time T206. In Fig. 17A, signals whose potentials have changed from time T204 to time T205 are shown enclosed by dashed lines.

[0143] At time T205, the potential of the signal RIN becomes high. j2 The potential of the clock signal CLK becomes low. j4 When the potential of the signal RIN becomes high, the transistor 33 is turned on, and the clock signal CLK j4 As a result of the potential of the clock signal CLK becoming high, the transistor 174 is turned on. j3 is at a high potential, the transistor 173 is in an on state. j2 When the potential of the transistor 171 becomes low, the transistor 171 is turned off.

[0144] As a result, the potential of the wiring Wb becomes high. This causes the transistors 22 and 32 to be turned on. When the transistor 32 is turned on, the potential of the wiring Wa becomes low, and the transistor 21 is turned off. When the transistor 21 is turned off and the transistor 22 is turned on, the potential of the signal OUT becomes low, and the potential of the clock signal CLK j1 The potential is low regardless of the potential of the

[0145] Fig. 17B is a circuit diagram showing the state of the sequential circuit 110a from time T206 to time T207. In Fig. 17B, signals whose potentials have changed from time T205 to time T206 are shown enclosed by dashed lines.

[0146] At time T206, the clock signal CLK j3 becomes low potential, and the clock signal CLK j5 The clock signal CLK is at high potential. j3becomes a low potential, turning off the transistor 172 and the transistor 173. When the transistor 173 is turned off, the wiring Wb is in a floating state.

[0147] Fig. 18A is a circuit diagram showing the state of the sequential circuit 110a from time T207 to time T208. In Fig. 18A, signals whose potentials have changed from time T206 to time T207 are shown enclosed by dashed lines.

[0148] At time T207, the potential of the signal RIN becomes low. j1 becomes high potential, and the clock signal CLK j4 When the potential of the signal RIN becomes low, the transistor 33 is turned off, and the clock signal CLK j4 When the potential of the transistor 174 becomes low, the transistor 174 is turned off.

[0149] Fig. 18B is a circuit diagram showing the state of the sequential circuit 110a from time T208 to time T209. In Fig. 18B, signals whose potentials have changed from time T207 to time T208 are shown enclosed by dashed lines.

[0150] At time T208, the clock signal CLK j2 becomes high potential, and the clock signal CLK j5 The potential of the clock signal CLK becomes low. j2 When the potential of the transistor 171 becomes high, the transistor 171 is turned on.

[0151] Fig. 19A is a circuit diagram showing the state of the sequential circuit 110a from time T209 to time T210. In Fig. 19A, signals whose potentials have changed from time T208 to time T209 are shown enclosed by dashed lines.

[0152] At time T209, the clock signal CLK j1 The potential of the clock signal CLK becomes low. j3The potential of the clock signal CLK becomes high. j3 As a result, the transistors 172 and 173 are turned on. j2 is at a high potential, the transistor 171 is on. When the transistors 171 and 172 are on, the potential of the wiring Wb becomes low. Therefore, the transistors 22 and 32 are off.

[0153] Fig. 19B is a circuit diagram showing the state of the sequential circuit 110a from time T210 to time T211. In Fig. 19B, signals whose potentials have changed from time T209 to time T210 are shown enclosed by dashed lines.

[0154] At time T210, the clock signal CLK j2 The potential of the clock signal CLK becomes low. j4 The potential of the clock signal CLK becomes high. j2 When the potential of the clock signal CLK becomes low, the transistor 171 is turned off. j4 As a result of the potential of the clock signal CLK becoming high, the transistor 174 is turned on. j3 is at a high potential, the transistors 172 and 173 are on. The transistor 171 is turned off and the transistors 173 and 174 are turned on, so the potential of the wiring Wb becomes high. Therefore, the transistors 22 and 32 are turned on.

[0155] At time T211, the clock signal CLK j3 The potential of the clock signal CLK becomes low. j5 The potential of the clock signal CLK becomes high. j3When the potential of the wiring Wb becomes low, the transistors 172 and 173 are turned off. When the transistor 173 is turned off, the wiring Wb is brought into a floating state.

[0156] From time T212 to time T217, the sequential circuit 110a performs the same operation as from time T207 to time T212. The same operation as from time T207 to time T212 is repeated until, for example, the final-stage sequential circuit 110a outputs a high-potential signal OUT. Note that the same operation as from time T207 to time T212 is also performed before time T201.

[0157] Here, by providing the transistors 173 and 174 in the circuit 111a, the clock signal CLK j1 The potential of the wiring Wb can be set to a high potential during the period when the clock signal CLK j1 This can suppress the potential rise of the wiring Wa due to the bootstrap effect described above, which occurs when the potential of the signal OUT changes from a low potential to a high potential. This can prevent the transistor 21 from unintentionally turning on and causing the potential of the signal OUT to rise. This can prevent malfunction of the shift register circuit 40. As a result, the shift register circuit 40 can be a highly reliable semiconductor device.

[0158] The above is an example of the method for driving the sequential circuit 110a.

[0159] The sequential circuit 110, which is a semiconductor device of one embodiment of the present invention, includes a transistor 171 and a transistor 172, which are connected in series. A clock signal, the high-potential periods of which partially overlap, is input to the gate of the transistor 171 and the gate of the transistor 172. As a result, as shown in FIG. 14B , the potential of the wiring Wb is low at regular intervals even after time T205. Although not shown in FIG. 14B , the potential of the wiring Wb is low at regular intervals even before time T201. In FIG. 14B , the period in which the potential of the wiring Wb is low after time T205 is indicated by a dashed line.

[0160] As described above, the period during which voltage stress is applied between the gate and source of the transistor 22 and between the gate and source of the transistor 32 can be shortened by periodically setting the potential of the wiring Wb to a low potential, compared to when the potential of the wiring Wb is kept high for a long period of time. This can suppress fluctuations in the electrical characteristics of the transistor 22 and the transistor 32, such as fluctuations in threshold voltage. Therefore, the sequential circuit 110 can be a highly reliable semiconductor device.

[0161] Note that the signal input to the gate of the transistor 171 and the signal input to the gate of the transistor 172 do not have to be a clock signal. For example, a signal whose potential is controlled independently of other signals may be input to the gate of the transistor 171 and the gate of the transistor 172. This can lengthen the period during which the potential of the wiring Wb is low, for example, and shorten the period during which voltage stress is applied between the gate and source of the transistor 22 and between the gate and source of the transistor 32. This can further improve the reliability of the sequential circuit 110.

[0162] As described above, the periods in which the multiple clock signals input to the sequential circuit 110 are at high potential can be partially overlapped with each other. This can prevent the wiring Wa from being in a floating state when the potential of the signal OUT changes from low to high. The potential of the wiring Wb can be controlled by an AND circuit. For example, an AND circuit including transistors 171 and 172 and an AND circuit including transistors 173 and 174 can be used to control the clock signal CLK j2 to clock signal CLK j4 The potential of the wiring Wb can be controlled based on the above. As described above, malfunction of the semiconductor device of one embodiment of the present invention can be prevented, and the reliability of the semiconductor device of one embodiment of the present invention can be improved.

[0163] <Example of sequential circuit configuration_7> 20 is a circuit diagram illustrating a configuration example of a sequential circuit 110b that can be used in the sequential circuit 110. The sequential circuit 110b includes a circuit 111b and a circuit 12. The circuit 111b is a modified example of the circuit 111a and differs from the circuit 111a in that it includes a transistor 175 and a transistor 176.

[0164] One of the source and the drain of the transistor 175 is electrically connected to one of the source and the drain of the transistor 21 and one of the source and the drain of the transistor 22. The other of the source and the drain of the transistor 175 is electrically connected to one of the source and the drain of the transistor 176. A clock signal CLK is input to the gate of the transistor 175. j2 The gate of the transistor 176 receives the clock signal CLK. j3 is entered.

[0165] A low potential is supplied to the other of the source and the drain of the transistor 176. Therefore, when the potential supplied to the other of the source and the drain of the transistor 176 is an eighth potential, the difference between the first potential and the eighth potential and the difference between the second potential and the eighth potential in the sequential circuit 110b are smaller than the difference between the third potential and the eighth potential in the sequential circuit 110b. The eighth potential in the sequential circuit 110b can be an inverted potential of the third potential in the sequential circuit 110b.

[0166] The sequential circuit 110b can be driven by, for example, the same method as the method shown in Fig. 14B. In this case, as with the sequential circuit 10b, it is possible to prevent malfunction of the shift register circuit 140 caused by the potential of the signal OUT becoming an unintended potential. Therefore, the shift register circuit 140 can be a highly reliable semiconductor device.

[0167] <Example of sequential circuit configuration_8> 21 is a circuit diagram illustrating a configuration example of a sequential circuit 110c that can be used in the sequential circuit 110. The sequential circuit 110c includes a circuit 111c and a circuit 12. The circuit 111c is a modified example of the circuit 111a and differs from the circuit 111a in that it includes a transistor 26 and a capacitor 27.

[0168] Similar to the circuit 11c, one of the source or drain of the transistor 21 is electrically connected to one of the source or drain of the transistor 22 and one electrode of the capacitor 27. One of the source or drain of the transistor 26 is electrically connected to the circuit 12 via a wiring Wa. The other of the source or drain of the transistor 26 is electrically connected to the gate of the transistor 21. The gate of the transistor 21 is electrically connected to the other electrode of the capacitor 27. As described above, the node N is a node to which the gate of the transistor 21, the other of the source or drain of the transistor 26, and the other electrode of the capacitor 27 are electrically connected. A high potential can be supplied to the gate of the transistor 26.

[0169] <Example of how to drive a sequential circuit_4> Fig. 21B is a timing chart showing an example of a method for driving the sequential circuit 110c shown in Fig. 21A. Fig. 21B shows the transition of potential changes of the node N in addition to the transition of potential changes of the signals and wirings shown in Fig. 14B.

[0170] Signal LIN, signal RIN, and clock signal CLK at times T221 to T237 j1 to clock signal CLK j5 The potential changes of the wiring Wa, the wiring Wb, and the signal OUT can be similar to those from time T201 to time T217 shown in Fig. 14B. The potential of the node N before time T221 is low.

[0171] At time T221, the signal LIN becomes high, turning on the transistor 31, and the potential of the wiring Wa becomes high. As a result, from time T221 to time T222, the potential of the node N increases to a potential that is lower than the potential of the wiring Wa by the threshold voltage of the transistor 26.

[0172] At time T222, the clock signal CLK j1 The potential at node N changes from a low potential to a high potential. As a result, the potential at node N rises due to the bootstrap effect described above. Therefore, transistor 26 is turned off, and node N is in a floating state. Here, the potential at node N at time T223 is set to a potential VN H Let's say.

[0173] The potential of node N is VN H In this case, the transistor 26 is turned off. This can prevent the potential of the wiring Wa from increasing from time T222 to time T224. This can prevent a high voltage from being applied to the transistors 31 and 32. Therefore, the sequential circuit 110c can be a highly reliable semiconductor device.

[0174] At time T224, the clock signal CLK j1 As a result, the potential of the node N drops from time T224 to time T225. For example, the potential drops to approximately the same level as the potential of the node N from time T221 to time T222.

[0175] At time T225, the potential of the wiring Wb becomes high, turning on the transistor 32, and the potential of the wiring Wa becomes low. As a result, the potential difference between the gate and source of the transistor 26 becomes equal to or greater than the threshold voltage of the transistor 26, turning on the transistor 26. Therefore, the potential of the node N becomes low from time T225 to time T226. Furthermore, the potential of the node N remains low even after time T226. This is an example of a method for driving the sequential circuit 110c.

[0176] <Example of sequential circuit configuration_9> 22A is a circuit diagram showing an example of the configuration of a sequential circuit 110d that can be applied to the sequential circuit 110. The sequential circuit 110d includes a circuit 111d and a circuit 12. The circuit 111d is a modified example of the circuit 111c, and applies a clock signal CLK to the gate of the transistor 26. j5 The difference from the circuit 111c is that the input is

[0177] The clock signal CLK is applied to the gate of transistor 26. j5 By inputting the voltage Vout, the period during which voltage stress is applied between the gate and source of the transistor 26 can be shortened, as in the circuit 11d. This can suppress fluctuations in the electrical characteristics of the transistor 26, such as fluctuations in the threshold voltage. Therefore, the sequential circuit 110d can be a highly reliable semiconductor device.

[0178] Furthermore, similarly to the sequential circuit 10d, by inputting a clock signal to the gate of the transistor 26, it is possible to more easily control the driving of the sequential circuit 110 than when a signal whose potential is controlled independently of other signals is input to the gate of the transistor 26. Note that a signal whose potential is controlled independently of other signals may also be input to the gate of the transistor 26. In this case, for example, the period during which the gate potential of the transistor 26 is low can be extended, thereby shortening the period during which voltage stress is applied between the gate and source of the transistor 26. This further improves the reliability of the sequential circuit 110d.

[0179] <Example of sequential circuit configuration_10> 22B is a circuit diagram illustrating an example configuration of a sequential circuit 110e that can be applied to the sequential circuit 110. The sequential circuit 110e includes a circuit 111e and a circuit 12. The circuit 111e is a modified example of the circuit 111d and differs from the circuit 111d in that it includes a transistor 175 and a transistor 176. The circuit 111e has a configuration that combines the configuration of the circuit 111b and the configuration of the circuit 111d.

[0180] <Shift register circuit configuration example 3> 23A is a block diagram illustrating a configuration example of a shift register circuit 40a, which is a semiconductor device of one embodiment of the present invention. In FIG. 23A, sequential circuits 50_1 to 50_5 are illustrated instead of the sequential circuits 10_1 to 10_5 illustrated in FIG. 1A.

[0181] A signal RES is input to the sequential circuit 50. In addition, signals PWC1 to PWC4 are input to the sequential circuit 50. For example, one signal from among the signals PWC1, PWC2, PWC3, and PWC4 is input to one sequential circuit 50.

[0182] For example, a signal PWC1 is input to the sequential circuits 50_1 and 50_5, a signal PWC2 is input to the sequential circuit 50_2, a signal PWC3 is input to the sequential circuit 50_3, and a signal PWC4 is input to the sequential circuit 50_4. Furthermore, for example, when a signal PWC1 is input to the sequential circuit 50_n, a signal PWC2 is input to the sequential circuit 50_n+1, a signal PWC3 is input to the sequential circuit 50_n+2, and a signal PWC4 is input to the sequential circuit 50_n+3.

[0183] A signal GOUT is output from the sequential circuit 50. Although the signals OUT and GOUT are different signals in Fig. 23A, they may be the same signal.

[0184] <Example of shift register circuit driving method_3> FIG. 23B is a timing chart showing an example of a method for driving the shift register circuit 40a. FIG. 23B shows, from top to bottom, the transition of potential changes for the signal RES, the start pulse signal SP, the clock signals CLK1 to CLK4, and the signals OUT_1 to OUT_5. The signals PWC1 to PWC4 are shown together because they have the same phase and period as the clock signals CLK1 to CLK4, respectively. The signals GOUT_1 to GOUT_5 are also shown together because they have the same phase as the signals OUT_1 to OUT_5, respectively. The amplitudes of the clock signals CLK1 to CLK4 and the signals PWC1 to PWC4 may be different. The amplitude of the signal OUT may be different from the amplitude of the signal GOUT.

[0185] The potential changes of the start pulse signal SP, the clock signals CLK1 to CLK4, and the signals OUT_1 to OUT_5 can be similar to those shown in Fig. 1B. The potential of the signal RES can be set to a low potential.

[0186] <Shift register circuit configuration example 4> 24A is a block diagram illustrating a configuration example of a shift register circuit 140a, which is a semiconductor device of one embodiment of the present invention. In FIG. 24A, sequential circuits 150_1 to 150_5 are illustrated instead of the sequential circuits 110_1 to 110_5 illustrated in FIG. 12A.

[0187] 23A, the signal RES is input to the sequential circuit 150. In addition, the signals PWC1 to PWC5 are input to the sequential circuit 150. For example, one signal from the signals PWC1, PWC2, PWC3, PWC4, and PWC5 is input to one sequential circuit 150.

[0188] For example, a signal PWC1 is input to the sequential circuit 150_1, a signal PWC2 is input to the sequential circuit 150_2, a signal PWC3 is input to the sequential circuit 150_3, a signal PWC4 is input to the sequential circuit 150_4, and a signal PWC5 is input to the sequential circuit 150_5. Furthermore, for example, when a signal PWC1 is input to the sequential circuit 150_n, a signal PWC2 is input to the sequential circuit 150_n+1, a signal PWC3 is input to the sequential circuit 150_n+2, a signal PWC4 is input to the sequential circuit 150_n+3, and a signal PWC5 is input to the sequential circuit 150_n+4.

[0189] The sequential circuit 150 outputs the signal GOUT, similar to the sequential circuit 50. Note that, similar to the shift register circuit 40a, the signals OUT and GOUT may be the same signal.

[0190] <Example of shift register circuit driving method_4> FIG. 24B is a timing chart showing an example of a method for driving the shift register circuit 140a. From the top, FIG. 24B shows the transition of potential changes for the signal RES, the start pulse signal SP, the clock signals CLK1 to CLK5, and the signals OUT_1 to OUT_5. The signals PWC1 to PWC5 are shown together because they have the same phase and period as the clock signals CLK1 to CLK5, respectively. Similarly to the shift register circuit 40a, the signals GOUT_1 to GOUT_5 are also shown together because they have the same phase as the signals OUT_1 to OUT_5, respectively. The amplitudes of the clock signals CLK1 to CLK5 may differ from the amplitudes of the signals PWC1 to PWC5.

[0191] The potential changes of the start pulse signal SP, the clock signals CLK1 to CLK5, and the signals OUT_1 to OUT_5 can be similar to those shown in Fig. 12B. The potential of the signal RES can be set to a low potential.

[0192] <Example of display device configuration> The shift register circuit 40a and the shift register circuit 140a, which are semiconductor devices according to embodiments of the present invention, can be applied to a display device. Fig. 25A is a block diagram illustrating a configuration example of a display device 500 to which the shift register circuit 40a and the shift register circuit 140a can be applied.

[0193] The display device 500 includes a display portion 502, a driver circuit portion 504, a protection circuit 506, and a terminal portion 507. Note that the protection circuit 506 may not be provided.

[0194] The display unit 502 has pixel circuits 501 arranged in X rows and Y columns (X and Y are each independently an integer of 2 or greater). The driver circuit unit 504 has driver circuits such as a scanning line driver circuit 504a that outputs scan signals to the scan lines GL_1 to GL_X and a signal line driver circuit 504b that outputs data signals to the signal lines DL_1 to DL_Y.

[0195] The scan line driver circuit 504a includes a shift register circuit 40a, a shift register circuit 140a, or the like, and has a function of outputting signals GOUT_1 to GOUT_X as scan signals to the scan lines GL_1 to GL_X, respectively. That is, the semiconductor device of one embodiment of the present invention can be applied to the scan line driver circuit 504a, for example. As described above, the semiconductor device of one embodiment of the present invention has high reliability. Therefore, by applying the semiconductor device of one embodiment of the present invention to the display device 500, the display device 500 can have high reliability.

[0196] The signal line driver circuit 504b is configured using, for example, a plurality of analog switches. The signal line driver circuit 504b may include a shift register circuit, such as the shift register circuit 40 or the shift register circuit 140.

[0197] The terminal portion 507 is a portion provided with terminals for inputting power, control signals, image signals, and the like from an external circuit to the display device.

[0198] The protection circuit 506 is a circuit that, when a potential outside a certain range is applied to a wiring connected to the protection circuit 506, brings the wiring into a conductive state with another wiring. The protection circuit 506 shown in Fig. 25A is connected to various wirings, such as a scanning line GL that is a wiring between the scanning line driving circuit 504a and the pixel circuit 501, or a signal line DL that is a wiring between the signal line driving circuit 504b and the pixel circuit 501. Note that in Fig. 25A, the protection circuit 506 is hatched to distinguish it from the pixel circuit 501.

[0199] The scanning line driver circuit 504a and the signal line driver circuit 504b may be provided on the same substrate as the display unit 502. Alternatively, a substrate on which the scanning line driver circuit 504a or the signal line driver circuit 504b is separately formed, for example, a driver circuit substrate made of a single crystal semiconductor or a polycrystalline semiconductor, may be separately prepared, and the substrate may be mounted on the substrate on which the display unit 502 is provided by COG or TAB (Tape Automated Bonding).

[0200] Fig. 25B shows an example of the configuration of a pixel circuit that can be applied to pixel circuit 501. Fig. 25B shows a pixel circuit in the pth row and qth column (p is an integer greater than or equal to 1 and less than or equal to X, and q is an integer greater than or equal to 1 and less than or equal to Y).

[0201] The pixel circuit 501 includes a transistor 552, a transistor 554, a capacitor 562, and a light-emitting element 572. The pixel circuit 501 is also connected to a scanning line GL_p, a signal line DL_q, ​​a potential supply line VL_a, a potential supply line VL_b, and the like.

[0202] An organic EL, a light emitting diode (LED), or the like can be used as the light emitting element 572. Furthermore, for example, a micro LED can be used as the LED.

[0203] A high potential is supplied to one of the potential supply line VL_a and the potential supply line VL_b. A low potential is supplied to the other of the potential supply line VL_a and the potential supply line VL_b. The current flowing through the light-emitting element 572 is controlled in accordance with the potential supplied to the gate of the transistor 554, thereby controlling the luminance of light emitted from the light-emitting element 572.

[0204] <Example of sequential circuit configuration_11> 26A, 26B, 27A, 27B, and 28 are circuit diagrams showing configuration examples of the sequential circuit 50 shown in Fig. 23A. Here, the sequential circuits 50 shown in Fig. 26A to 28 are referred to as sequential circuit 50a, sequential circuit 50b, sequential circuit 50c, sequential circuit 50d, and sequential circuit 50e, respectively.

[0205] 26A includes a sequential circuit 10a, a circuit 51a, and a transistor 28. The circuit 51a includes a transistor 61 and a transistor 62.

[0206] One of the source and the drain of the transistor 28 is electrically connected to the wiring Wb. A high potential is supplied to the other of the source and the drain of the transistor 28. A signal RES is supplied to the gate of the transistor 28.

[0207] One of the source or drain of the transistor 61 is electrically connected to one of the source or drain of the transistor 62, and a signal GOUT is output from the transistor 61. A signal PWC is supplied to the other of the source or drain of the transistor 61. A gate of the transistor 61 is electrically connected to a wiring Wa. A low potential is supplied to the other of the source or drain of the transistor 62. A gate of the transistor 62 is electrically connected to a wiring Wb. Here, the signal PWC can be, for example, any of the signals PWC1 to PWC4 shown in FIG. 23A. Note that if the signal GOUT is the same signal as the signal OUT, the sequential circuit 50a does not need to include the circuit 51a.

[0208] When the potential of the signal RES is set to a high potential, the transistor 28 is turned on, and the potential of the wiring Wb is set to a high potential. As a result, the transistors 22 and 62 are turned on, and the potential of the signal OUT and the potential of the signal GOUT are set to a low potential. When the potential of the signal RES is set to a high potential, the potential of all the signals OUT and GOUT in the shift register circuit 40a are set to a low potential. This resets the operation of the shift register circuit 40a. Therefore, the signal RES is a reset signal. Here, during the period when the potential of the signal RES is high, the clock signal CLK i2 The potential of the signal RES is controlled so that the potential of the signal RES is set to a low potential.

[0209] The sequential circuit 50a can be driven, for example, by the method shown in FIG. 3B. This can shorten the period during which voltage stress is applied between the gate and source of the transistor 62, similar to the transistor 22. This can suppress fluctuations in the electrical characteristics of the transistor 62, such as fluctuations in the threshold voltage. Therefore, a display device including the sequential circuit 50a can be a highly reliable display device.

[0210] 26B includes a sequential circuit 10b, a circuit 51b, and a transistor 28. The circuit 51b is a modification of the circuit 51a and differs from the circuit 51a in that a transistor 65 is included.

[0211] One of the source and the drain of the transistor 65 is electrically connected to one of the source and the drain of the transistor 61 and one of the source and the drain of the transistor 62. A low potential is supplied to the other of the source and the drain of the transistor 65. A clock signal CLK is supplied to the gate of the transistor 65. i2 is entered.

[0212] By using the sequential circuit 50b as the sequential circuit 50, it is possible to prevent malfunction of the shift register circuit 40a caused by the potential of the signal OUT and the potential of the signal GOUT becoming unintended potentials. Therefore, a display device having the shift register circuit 40a can be a highly reliable display device.

[0213] 27A includes a sequential circuit 10c, a circuit 51c, and a transistor 28. The circuit 51c is a modification of the circuit 51a and differs from the circuit 51a in that it includes a transistor 66 and a capacitor 67.

[0214] One of the source or drain of the transistor 61 is electrically connected to one of the source or drain of the transistor 62 and one electrode of the capacitor 67. One of the source or drain of the transistor 66 is electrically connected to a wiring Wa. The other of the source or drain of the transistor 66 is electrically connected to the gate of the transistor 61. The gate of the transistor 61 is electrically connected to the other electrode of the capacitor 67. A high potential can be supplied to the gate of the transistor 66.

[0215] 9B, the sequential circuit 50c can be driven by the method shown in FIG. i1 As a result, the high potential of the signal PWC can be output as the signal OUT. Furthermore, the high potential of the signal PWC can be output as the signal GOUT without being affected by the threshold voltage of the transistor 61. This makes it possible to realize a sequential circuit 50 with high output performance without increasing the number of types of power supply potentials.

[0216] 27B includes a sequential circuit 10d, a circuit 51d, and a transistor 28. The circuit 51d is a modified example of the circuit 51c, and includes a transistor 66 connected to a gate of the transistor 66 and a clock signal CLK i4 is input to the circuit 51c.

[0217] The clock signal CLK is applied to the gate of transistor 66. i4 By inputting the sequential circuit 50d, it is possible to shorten the period during which voltage stress is applied between the gate and source of the transistor 66. This makes it possible to suppress fluctuations in the electrical characteristics of the transistor 66, such as fluctuations in the threshold voltage. This makes it possible to provide a display device having high reliability, including the sequential circuit 50d.

[0218] Furthermore, by inputting a clock signal to the gate of the transistor 66, it is possible to more easily control the driving of the sequential circuit 50 than when a signal whose potential is controlled independently of other signals is input to the gate of the transistor 66. Note that a signal whose potential is controlled independently of other signals may be input to the gate of the transistor 66. In this case, for example, the period during which the gate potential of the transistor 66 is low can be extended, thereby shortening the period during which voltage stress is applied between the gate and source of the transistor 66. This further improves the reliability of a display device including the sequential circuit 50d.

[0219] 28 includes a sequential circuit 10e, a circuit 51e, and a transistor 28. The circuit 51e is a modification of the circuit 51d and differs from the circuit 51d in that it includes a transistor 65. The circuit 51e has a configuration that combines the configuration of the circuit 51b and the configuration of the circuit 51d.

[0220] <Example of sequential circuit configuration_12> 29 to 33 are circuit diagrams showing configuration examples of the sequential circuit 150 shown in Fig. 24A. Here, the sequential circuits 150 shown in Fig. 29 to 33 are assumed to be sequential circuits 150a, 150b, 150c, 150d, and 150e, respectively. Here, the signal PWC in the sequential circuit 150 can be, for example, any of the signals PWC1 to PWC5 shown in Fig. 24A.

[0221] 29 includes a sequential circuit 110a, a circuit 151a, and a transistor 28. The circuit 151a can have a structure similar to that of the circuit 51a.

[0222] As in the sequential circuit 50a, one of the source and drain of the transistor 28 is electrically connected to the wiring Wb. A high potential is supplied to the other of the source and drain of the transistor 28. A signal RES is supplied to the gate of the transistor 28. As described above, the signal RES is a reset signal, and when the potential of the signal RES is set to a high potential, the potentials of all signals OUT and all signals GOUT in the shift register circuit 140a become low. Here, during the period when the potential of the signal RES is high, the clock signal CLK j2 or the clock signal CLK j3 The potential of the signal RES is controlled so that at least one of the potentials is a low potential.

[0223] The sequential circuit 150a can be driven by, for example, the method shown in FIG. 14B. This can shorten the period during which voltage stress is applied between the gate and source of the transistor 62, similar to the transistor 22. This can suppress fluctuations in the electrical characteristics of the transistor 62, such as fluctuations in the threshold voltage. Therefore, a display device including the sequential circuit 150a can be a highly reliable display device.

[0224] 30 includes a sequential circuit 110b, a circuit 151b, and a transistor 28. The circuit 151b is a modified example of the circuit 151a and differs from the circuit 151a in that a transistor 185 and a transistor 186 are included.

[0225] One of the source or the drain of the transistor 185 is electrically connected to one of the source or the drain of the transistor 61 and one of the source or the drain of the transistor 62. The other of the source or the drain of the transistor 185 is electrically connected to one of the source or the drain of the transistor 186. A low potential is supplied to the gate of the transistor 185. A clock signal CLK j2 The gate of the transistor 186 receives the clock signal CLK. j3 is entered.

[0226] By using the sequential circuit 150b as the sequential circuit 150, it is possible to prevent malfunction of the shift register circuit 140a caused by the potentials of the signal OUT and the signal GOUT becoming unintended potentials. Therefore, a display device including the shift register circuit 140a can be a highly reliable display device.

[0227] 31 includes a sequential circuit 110c, a circuit 151c, and a transistor 28. The circuit 151c can have a structure similar to that of the circuit 51c.

[0228] 21B, the sequential circuit 150c can be driven by the method shown in FIG. j1 The high potential of the signal PWC can be output as the signal OUT. Furthermore, the high potential of the signal PWC can be output as the signal GOUT without being affected by the threshold voltage of the transistor 61. This makes it possible to realize a sequential circuit 150 with high output performance without increasing the number of types of power supply potentials.

[0229] 32 includes a sequential circuit 110d, a circuit 151d, and a transistor 28. The circuit 151d is a modified example of the circuit 151c, and includes a transistor 66 connected to a gate of the transistor 66 and a clock signal CLK. j5 is input to the circuit 151c.

[0230] The clock signal CLK is applied to the gate of transistor 66. j5 By inputting the voltage Vout, the period during which voltage stress is applied between the gate and source of the transistor 66 can be shortened. This can suppress fluctuations in the electrical characteristics of the transistor 66, such as fluctuations in the threshold voltage, as in the sequential circuit 50d. This allows a display device including the sequential circuit 150d to have high reliability.

[0231] Furthermore, similarly to the sequential circuit 50d, by inputting a clock signal to the gate of the transistor 66, it is possible to more easily control the driving of the sequential circuit 150 than when a signal whose potential is controlled independently of other signals is input to the gate of the transistor 66. Note that a signal whose potential is controlled independently of other signals may be input to the gate of the transistor 66. In this case, for example, the period during which the gate potential of the transistor 66 is low can be extended, thereby shortening the period during which voltage stress is applied between the gate and source of the transistor 66. This further improves the reliability of a display device including the sequential circuit 150d.

[0232] 33 includes a sequential circuit 110e, a circuit 151e, and a transistor 28. The circuit 151e is a modification of the circuit 151d and differs from the circuit 151d in that it includes a transistor 185 and a transistor 186. The circuit 151e has a configuration that combines the configuration of the circuit 151b and the configuration of the circuit 151d.

[0233] <Light-emitting element> A structural example of the light-emitting element 572 shown in FIG. 25B and an example of a manufacturing method thereof will be described below.

[0234] FIG. 34A is a schematic top view illustrating an example of the configuration of the display unit 502 illustrated in FIG. 25A. The display unit 502 includes a plurality of light-emitting elements 572R that emit red light, a plurality of light-emitting elements 572G that emit green light, and a plurality of light-emitting elements 572B that emit blue light. In FIG. 34A, the light-emitting elements are labeled R, G, and B within their light-emitting regions to easily distinguish between them. The configuration illustrated in FIG. 34A illustrates a configuration having three colors, red (R), green (G), and blue (B), but is not limited thereto. For example, a configuration having four or more colors may be used. Furthermore, all of the light-emitting elements 572 provided in the display unit 502 may emit light of the same color. For example, all of the light-emitting elements 572 provided in the display unit 502 may emit white light.

[0235] In this specification etc., a structure in which a separate light-emitting layer is created for each color light-emitting element (here, blue (B), green (G), and red (R)), or in which the light-emitting layers are painted differently, may be referred to as an SBS (Side By Side) structure. Also, in this specification etc., a light-emitting element that can emit white light may be referred to as a white light-emitting element (also called a white light-emitting device). Note that by combining a white light-emitting element with a colored layer (for example, a color filter), the display device can perform full-color display.

[0236] Light-emitting elements 572R, 572G, and 572B are arranged in a matrix. Fig. 34A shows a so-called stripe arrangement in which light-emitting elements of the same color are arranged in one direction. Note that the arrangement of the light-emitting elements is not limited to this, and arrangement methods such as a delta arrangement or a zigzag arrangement may also be applied, or a pentile arrangement may also be used.

[0237] As the light-emitting elements 572R, 572G, and 572B, it is preferable to use organic EL elements such as OLEDs (organic light-emitting diodes) or QLEDs (quantum-dot light-emitting diodes). Examples of light-emitting materials included in the EL elements include fluorescent materials, phosphorescent materials, inorganic compounds (e.g., quantum dot materials), and thermally activated delayed fluorescence (TADF) materials. Note that the TADF material may be a material that is in thermal equilibrium between a singlet excited state and a triplet excited state. Such TADF materials have a short emission lifetime (excitation lifetime), which can suppress a decrease in efficiency in the high-brightness region of the light-emitting element.

[0238] Furthermore, LEDs such as micro LEDs can also be used as the light emitting elements 572R, 572G, and 572B.

[0239] FIG. 34B is a schematic cross-sectional view corresponding to the dashed dotted line A1-A2 in FIG. 34A.

[0240] 34B shows cross sections of the light-emitting element 572R, the light-emitting element 572G, and the light-emitting element 572B. The light-emitting element 572R, the light-emitting element 572G, and the light-emitting element 572B are each provided over a substrate 451 and include a conductive layer 772 functioning as a pixel electrode and a conductive layer 788 functioning as a common electrode.

[0241] In this specification and the like, a conductive layer that functions as a pixel electrode may be referred to as a lower electrode, and a conductive layer that functions as a common electrode may be referred to as an upper electrode. For example, the conductive layer 772 may be referred to as a lower electrode, and the conductive layer 788 may be referred to as an upper electrode. Note that a conductive layer that functions as a pixel electrode may be referred to as an upper electrode, and a conductive layer that functions as a common electrode may be referred to as a lower electrode.

[0242] The light-emitting element 572R has an EL layer 786R between the conductive layer 772 functioning as a pixel electrode and the conductive layer 788 functioning as a common electrode. The light-emitting element 572G has an EL layer 786G between the conductive layer 772 and the conductive layer 788, and the light-emitting element 572B has an EL layer 786B between the conductive layer 772 and the conductive layer 788.

[0243] The EL layer 786R contains a light-emitting organic compound that emits light having an intensity at least in the red wavelength range, the EL layer 786G contains a light-emitting organic compound that emits light having an intensity at least in the green wavelength range, and the EL layer 786B contains a light-emitting organic compound that emits light having an intensity at least in the blue wavelength range.

[0244] Each of the EL layers 786R, 786G, and 786B may include, in addition to a layer containing a light-emitting organic compound (light-emitting layer), one or more of a layer containing a substance with high electron-injecting properties (electron-injecting layer), a layer containing a substance with high electron-transporting properties (electron-transporting layer), a layer containing a substance with high hole-injecting properties (hole-injecting layer), and a layer containing a substance with high hole-transporting properties (hole-transporting layer).

[0245] The conductive layer 772 functioning as a pixel electrode is provided for each light-emitting element. The conductive layer 788 functioning as a common electrode is provided as a continuous layer common to each light-emitting element. A conductive film that is transparent to visible light is used for either the conductive layer 772 functioning as a pixel electrode or the conductive layer 788 functioning as a common electrode, and a conductive film that is reflective is used for the other. By making the conductive layer 772 functioning as a pixel electrode light-transmitting and the conductive layer 788 functioning as a common electrode light-reflective, a bottom-emission display device can be obtained. Conversely, by making the conductive layer 772 functioning as a pixel electrode reflective and the conductive layer 788 functioning as a common electrode light-transmitting, a top-emission display device can be obtained. Note that by making both the conductive layer 772 functioning as a pixel electrode and the conductive layer 788 functioning as a common electrode light-transmitting, a dual-emission display device can also be obtained.

[0246] An insulating layer 472 is provided to cover an edge portion of the conductive layer 772 that functions as a pixel electrode. The edge portion of the insulating layer 472 is preferably tapered.

[0247] The EL layer 786R, the EL layer 786G, and the EL layer 786B each have a region in contact with the top surface of the conductive layer 772 that functions as a pixel electrode and a region in contact with the surface of the insulating layer 472. Ends of the EL layer 786R, the EL layer 786G, and the EL layer 786B are located on the insulating layer 472.

[0248] As shown in Figure 34B, a gap is provided between two EL layers between light-emitting elements of different colors. In this way, it is preferable that the EL layer 786R, the EL layer 786G, and the EL layer 786B are provided so as not to be in contact with each other. This makes it possible to effectively prevent current from flowing through two adjacent EL layers, which would otherwise cause unintended light emission (also known as crosstalk). This allows for increased contrast and a display device with high display quality to be realized.

[0249] The EL layer 786R, the EL layer 786G, and the EL layer 786B can be separately formed using a photolithography method or the like. This allows the separate formation without using a shadow mask such as a metal mask. This makes it possible to realize a high-resolution display device. Note that the separate formation of the EL layer 786R, the EL layer 786G, and the EL layer 786B may also be performed using a metal mask or the like.

[0250] As described above, a high-resolution display device 500 has a high pixel density, and therefore, for example, a large number of pixel circuits 501 are electrically connected to a scanning line GL per unit length as shown in FIG. 25A. Therefore, the wiring capacitance of the scanning line GL increases due to, for example, the gate capacitance of the transistor 552 shown in FIG. 25B. Furthermore, when a large number of pixel circuits 501 are provided in the display device 500, the number of scanning lines GL also increases (X increases). Therefore, in order to ensure the frame frequency of the display device 500, it is necessary to shorten one horizontal period, which is the period from when the scanning line driving circuit 504a supplies a signal to a scanning line GL to when the signal is supplied to the scanning line GL of the next row. As described above, the increase in the wiring capacitance of the scanning line GL and the shortening of one horizontal period necessitate the increase in the current flowing through the scanning line GL when charging the scanning line GL.

[0251] In order to increase the current flowing through the scanning line GL, the potential of the signal GOUT is increased. As a result, for example, when the potential of the signal GOUT is high, a large voltage stress is applied to the transistor 62 electrically connected to the scanning line GL. Therefore, if the display device 500 is a high-definition display device or a display device with a large number of pixels, the reliability of the display device 500 may be reduced.

[0252] For example, a semiconductor device that can be applied to the scan line driver circuit 504a of the display device 500 can shorten the period during which voltage stress is applied to the transistor 62 electrically connected to the scan line GL, as described above. Therefore, for example, fluctuations in the electrical characteristics of the transistor 62, such as fluctuations in the threshold voltage, can be suppressed. Therefore, by applying the semiconductor device of one embodiment of the present invention, the reliability of the display device can be improved. As described above, the display device 500 can be a high-definition display device with a large number of pixels and high reliability.

[0253] In addition, a protective layer 471 is provided over the conductive layer 788 functioning as a common electrode to cover the light-emitting elements 572R, 572G, and 572B. The protective layer 471 has a function of preventing impurities such as water from diffusing from above to each light-emitting element.

[0254] The protective layer 471 may have, for example, a single-layer structure or a stacked structure including at least an inorganic insulating film. Examples of the inorganic insulating film include oxide films or nitride films such as a silicon oxide film, a silicon oxynitride film, a silicon nitride oxide film, a silicon nitride film, an aluminum oxide film, an aluminum oxynitride film, and a hafnium oxide film. Alternatively, a semiconductor material such as indium gallium oxide or indium gallium zinc oxide may be used for the protective layer 471. Note that the protective layer 471 may be formed by an atomic layer deposition (ALD) method, a chemical vapor deposition (CVD) method, or a sputtering method. Note that, although the protective layer 471 includes an inorganic insulating film, the present invention is not limited to this. For example, the protective layer 471 may have a stacked structure of an inorganic insulating film and an organic insulating film.

[0255] In this specification, an oxynitride refers to a material whose composition contains more oxygen than nitrogen, and a nitride oxide refers to a material whose composition contains more nitrogen than oxygen. For example, silicon oxynitride refers to a material whose composition contains more oxygen than nitrogen, and silicon nitride oxide refers to a material whose composition contains more nitrogen than oxygen.

[0256] FIG. 34C shows a different example from the above.

[0257] 34C includes a light-emitting element 572W that emits white light. The light-emitting element 572W includes an EL layer 786W that emits white light between a conductive layer 772 that functions as a pixel electrode and a conductive layer 788 that functions as a common electrode.

[0258] The EL layer 786W may be configured by stacking two or more light-emitting layers selected so that the emitted colors are complementary to each other. Alternatively, a stacked EL layer may be used in which a charge generating layer is sandwiched between light-emitting layers.

[0259] FIG. 34C shows three light-emitting elements 572W lined up. A colored layer 264R is provided on the top of the left light-emitting element 572W. The colored layer 264R functions as a bandpass filter that transmits red light. Similarly, a colored layer 264G that transmits green light is provided on the top of the center light-emitting element 572W, and a colored layer 264B that transmits blue light is provided on the top of the right light-emitting element 572W. This allows the display device to display color images.

[0260] Here, the EL layer 786W and the conductive layer 788 functioning as a common electrode are separated between two adjacent light-emitting elements 572W. This effectively prevents current from flowing through the EL layer 786W between the two adjacent light-emitting elements 572W, resulting in unintended light emission. In particular, when a stacked EL element in which a charge-generating layer is provided between two light-emitting layers is used as the EL layer 786W, the higher the resolution, i.e., the smaller the distance between adjacent pixels, the more pronounced the effect of crosstalk becomes, resulting in a decrease in contrast. Therefore, by using this configuration, a display device that combines high resolution and high contrast can be realized.

[0261] When the conductive layer 788 is separated, the protective layer 471 is provided so as to cover the upper surface and edges of the conductive layer 788. The protective layer 471 may also be provided so as to cover the side edges of the EL layer 786R, the EL layer 786G, and the EL layer 786B.

[0262] The EL layer 786W and the conductive layer 788 functioning as a common electrode are preferably separated by photolithography, which can reduce the distance between light-emitting elements and realize a display device with a higher aperture ratio than when a shadow mask such as a metal mask is used.

[0263] In this specification, etc., a device fabricated using a metal mask or FMM (fine metal mask, high-resolution metal mask) may be referred to as a device with an MM (metal mask) structure. In addition, in this specification, etc., a device fabricated without using a metal mask or FMM may be referred to as a device with an MML (metal maskless) structure.

[0264] In the case of a bottom-emission light-emitting element, a colored layer may be provided between the conductive layer 772 functioning as a pixel electrode and the substrate 451 .

[0265] FIG. 35A shows an example different from the above. Specifically, FIG. 35A shows a configuration in which the insulating layer 472 is not provided between the light-emitting elements 572R, 572G, and 572B. This configuration allows a display device with a high aperture ratio. Furthermore, the protective layer 471 covers the side surfaces of the light-emitting elements 572R, 572G, and 572B. This configuration can suppress impurities (typically, water) that may enter through the side surfaces of the light-emitting elements 572R, 572G, and 572B. Furthermore, in the configuration shown in FIG. 35A, the conductive layer 772, the EL layer 786R, and the conductive layer 788 have substantially the same top surface shape. This structure can be formed collectively using a resist mask or the like after the conductive layer 772, the EL layer 786R, and the conductive layer 788 are formed. This process can also be called self-aligned patterning because the EL layer 786R and the conductive layer 772 are processed using the conductive layer 788 as a mask. Note that although the light-emitting element 572R has been described here, the light-emitting element 572G and the light-emitting element 572B can also have a similar configuration.

[0266] 35A shows a structure in which a protective layer 458 is further provided on the protective layer 471. For example, the protective layer 471 is formed using an apparatus (typically an ALD apparatus) capable of depositing a film with high coverage, and the protective layer 458 is formed using an apparatus (typically a sputtering apparatus) capable of depositing a film with lower coverage than the protective layer 471, whereby a region 459 can be provided between the protective layer 471 and the protective layer 458. In other words, the region 459 is located between the light-emitting element 572R and the light-emitting element 572G, and between the light-emitting element 572G and the light-emitting element 572B.

[0267] The region 459 contains, for example, one or more elements selected from air, nitrogen, oxygen, carbon dioxide, and a Group 18 element (typically, helium, neon, argon, xenon, and krypton). The region 459 may also contain, for example, a gas used when forming the protective layer 458. For example, when the protective layer 458 is formed by sputtering, the region 459 may contain one or more of the above Group 18 elements. When the region 459 contains a gas, the gas can be identified by, for example, gas chromatography. Alternatively, when the protective layer 458 is formed by sputtering, the gas used during sputtering may also be contained in the film of the protective layer 458. In this case, when the protective layer 458 is analyzed by, for example, energy dispersive X-ray analysis (EDX analysis), elements such as argon may be detected.

[0268] Furthermore, when the refractive index of region 459 is lower than the refractive index of protective layer 471, light emitted from light-emitting element 572R, light-emitting element 572G, or light-emitting element 572B is reflected at the interface between protective layer 471 and region 459. This makes it possible to prevent light emitted from light-emitting element 572R, light-emitting element 572G, or light-emitting element 572B from entering an adjacent pixel. This makes it possible to prevent light of different colors from mixing, thereby improving the image quality of the display device.

[0269] 35A, the area between light-emitting element 572R and light-emitting element 572G or the area between light-emitting element 572G and light-emitting element 572B (hereinafter simply referred to as the distance between the light-emitting elements) can be narrowed. Specifically, the distance between the light-emitting elements can be set to 1 μm or less, preferably 500 nm or less, and more preferably 200 nm or less, 100 nm or less, 90 nm or less, 70 nm or less, 50 nm or less, 30 nm or less, 20 nm or less, 15 nm or less, or 10 nm or less. In other words, the distance between the side surface of light-emitting element 572R and the side surface of light-emitting element 572G or the distance between the side surface of light-emitting element 572G and the side surface of light-emitting element 572B has an area of ​​1 μm or less, preferably an area of ​​0.5 μm (500 nm) or less, and more preferably an area of ​​100 nm or less.

[0270] Furthermore, for example, when the region 459 contains air, it is possible to isolate the light emitting elements while suppressing color mixing and crosstalk of light from the light emitting elements.

[0271] Region 459 may also have an insulating layer containing, for example, an organic material. For example, region 459 may be filled with acrylic resin, polyimide resin, epoxy resin, imide resin, polyamide resin, polyimideamide resin, silicone resin, siloxane resin, benzocyclobutene resin, phenolic resin, or precursors of these resins. Region 459 may also be filled with a photosensitive resin. Photoresist may be used as the photosensitive resin. The photosensitive resin may be a positive material or a negative material.

[0272] The region 459 may also include an insulating layer containing, for example, an inorganic material. Examples of the inorganic material that can be used include inorganic insulating films such as an oxide insulating film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. The inorganic insulating film may have a single-layer structure or a stacked-layer structure. Examples of oxide insulating films include a silicon oxide film, an aluminum oxide film, a magnesium oxide film, an indium gallium zinc oxide film, a gallium oxide film, a germanium oxide film, an yttrium oxide film, a zirconium oxide film, a lanthanum oxide film, a neodymium oxide film, a hafnium oxide film, and a tantalum oxide film. Examples of nitride insulating films include a silicon nitride film and an aluminum nitride film. Examples of oxynitride insulating films include a silicon oxynitride film and an aluminum oxynitride film. Examples of nitride oxide insulating films include a silicon nitride oxide film and an aluminum nitride oxide film.

[0273] It is also preferable that the region 459 contains both the inorganic material and the organic material described above. For example, the region 459 may have a stacked structure of an aluminum oxide film and a photoresist on the aluminum oxide film.

[0274] FIG. 35B shows a different example. Specifically, the configuration shown in FIG. 35B differs from the configuration shown in FIG. 35A in the configuration of the substrate 451. The substrate 451 has a recess formed by removing a portion of its upper surface during processing of the light-emitting elements 572R, 572G, and 572B. A protective layer 471 is formed in the recess. In other words, the substrate 451 has a region where the lower surface of the protective layer 471 is located lower than the lower surface of the conductive layer 772 in a cross-sectional view. By providing this region, impurities (typically water) can be effectively prevented from entering the light-emitting elements 572R, 572G, and 572B from below. The recess can be formed when impurities (also referred to as residue) that may adhere to the side surfaces of the light-emitting elements 572R, 572G, and 572B are removed by wet etching or the like during processing of the light-emitting elements 572R, 572G, and 572B. After removing the residue, the side surfaces of the light-emitting elements are covered with the protective layer 471, thereby providing a highly reliable display device.

[0275] FIG. 35C shows a different example. Specifically, the configuration shown in FIG. 35C includes an insulating layer 776 and a microlens array 777 in addition to the configuration shown in FIG. 35B. The insulating layer 776 functions as an adhesive layer. If the refractive index of the insulating layer 776 is lower than that of the microlens array 777, the microlens array 777 may be able to focus the light emitted from the light-emitting elements 572R, 572G, and 572B. Focusing the light emitted from the light-emitting elements 572R, 572G, and 572B is advantageous because it allows a bright image to be viewed, especially when the user views the display surface from directly in front of the display device. Note that various curing adhesives, such as a photo-curing adhesive (e.g., an ultraviolet-curing adhesive), a reactive-curing adhesive, a thermosetting adhesive, or an anaerobic adhesive, can be used as the insulating layer 776. These adhesives include epoxy resin, acrylic resin, silicone resin, phenolic resin, polyimide resin, imide resin, PVC (polyvinyl chloride) resin, PVB (polyvinyl butyral) resin, and EVA (ethylene vinyl acetate) resin. In particular, materials with low moisture permeability, such as epoxy resin, are preferred. Two-component resins may also be used. Adhesive sheets may also be used.

[0276] 36A to 36C are cross-sectional views showing a configuration example of the light-emitting element 572, illustrating a more detailed configuration example of the EL layer 786. As shown in FIG. 36A, the EL layer 786 of the light-emitting element 572 can be composed of multiple layers, such as a layer 420, a light-emitting layer 411, and a layer 430. The layer 420 can include, for example, an electron injection layer and an electron transport layer. The light-emitting layer 411 includes, for example, a light-emitting compound. The layer 430 can include, for example, a hole injection layer and a hole transport layer.

[0277] A structure having layer 420, light-emitting layer 411, and layer 430 provided between a pair of electrodes can function as a single light-emitting unit, and the structure of FIG. 36A is referred to as a single structure in this specification.

[0278] As shown in FIG. 36B, a configuration in which a plurality of light-emitting layers (light-emitting layer 411, light-emitting layer 412, and light-emitting layer 413) are provided between layer 420 and layer 430 is also a variation of the single structure.

[0279] Furthermore, as shown in Figure 36C, a configuration in which a plurality of light-emitting units (EL layer 786a and EL layer 786b) are connected in series via an intermediate layer (charge generating layer) 440 is referred to as a tandem structure in this specification. Note that, although the configuration shown in Figure 36C is referred to as a tandem structure in this specification, the present invention is not limited to this, and for example, the tandem structure may also be referred to as a stack structure. Note that by using a tandem structure, a light-emitting element capable of emitting light with high brightness can be obtained.

[0280] The emitted color of the light-emitting element 572 can be red, green, blue, cyan, magenta, yellow, white, or the like, depending on the material constituting the EL layer 786. Furthermore, the color purity can be further improved by providing the light-emitting element 572 with a microcavity structure.

[0281] A light-emitting element that emits white light preferably has a structure in which two or more light-emitting substances are contained in the light-emitting layer. To obtain white light emission, light-emitting substances are selected such that the respective emissions of the two or more light-emitting substances are in a complementary color relationship.

[0282] The light-emitting layer preferably contains two or more light-emitting materials that emit light of R (red), G (green), B (blue), Y (yellow), O (orange), or the like.

[0283] Furthermore, when comparing the above-mentioned white light-emitting element (single structure or tandem structure) with a light-emitting element having an SBS structure, the light-emitting element having an SBS structure can reduce power consumption compared to the white light-emitting element. If it is desired to keep power consumption low, it is preferable to use a light-emitting element having an SBS structure. On the other hand, the manufacturing process of the white light-emitting element is simpler than that of the light-emitting element having an SBS structure, and therefore the manufacturing cost can be reduced or the manufacturing yield can be increased, making it preferable.

[0284] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0285] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes or examples described in this specification.

[0286] (Embodiment 2) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0287] The display device of the present embodiment can be a high-resolution display device or a large-sized display device, and therefore can be used in electronic devices having relatively large screens, such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as display units of digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound reproducing devices.

[0288] [Display device 500A] Fig. 37 is a perspective view showing a configuration example of a display device 500A that can be applied to the display device 500 shown in Fig. 25A. Fig. 38A is a cross-sectional view showing the configuration example of the display device 500A.

[0289] Display device 500A has a configuration in which substrate 652 and substrate 651 are bonded together. In Fig. 37, substrate 652 is clearly indicated by a dashed line.

[0290] The display device 500A has a display unit 502, a circuit 664, wiring 665, etc. Fig. 37 shows an example in which an IC 673 and an FPC 672 are mounted on the display device 500A. Therefore, the configuration shown in Fig. 37 can also be said to be a display module having the display device 500A, an IC (integrated circuit), and an FPC.

[0291] The circuit 664 can be, for example, a scanning line driver circuit.

[0292] The wiring 665 has a function of supplying signals and power to the display portion 502 and the circuit 664. The signals and power are input to the wiring 665 from the outside via the FPC 672. Alternatively, the signals and power are input to the wiring 665 from the IC 673.

[0293] 37 shows an example in which an IC 673 is provided on a substrate 651 by a COG method or a COF (Chip On Film) method. The IC 673 may be, for example, an IC having a scanning line driver circuit or a signal line driver circuit. The display device 500A and the display module may not include an IC. Alternatively, the IC may be mounted on an FPC by, for example, a COF method.

[0294] FIG. 38A shows an example of a cross section of the display device 500A, in which a part of the region including the FPC 672, a part of the circuit 664, a part of the display unit 502, and a part of the region including the end portion are cut away.

[0295] The display device 500A shown in Fig. 38A includes a transistor 201, a transistor 205, a light-emitting element 572R, a light-emitting element 572G, and a light-emitting element 572B between a substrate 651 and a substrate 652. Here, Fig. 38A shows the configuration of Fig. 35A as the light-emitting element 572R, the light-emitting element 572G, and the light-emitting element 572B.

[0296] The protective layer 458 and the substrate 652 are bonded via an adhesive layer 642. A solid sealing structure, a hollow sealing structure, or the like can be applied to seal the light-emitting element. In FIG. 38A, the space between the substrates 652 and 651 is filled with the adhesive layer 642, and a solid sealing structure is applied. Alternatively, the space may be filled with an inert gas (nitrogen, argon, or the like), and a hollow sealing structure may be applied. In this case, the adhesive layer 642 may be provided so as not to overlap with the light-emitting element. Furthermore, the space may be filled with a resin different from the frame-shaped adhesive layer 642.

[0297] The conductive layer 772 is connected to the conductive layer 222 b included in the transistor 205 through an opening provided in the insulating layer 214 .

[0298] The display device 500A is a top-emission type. Light emitted from the light-emitting elements is emitted toward the substrate 652. The substrate 652 is preferably made of a material that is highly transparent to visible light.

[0299] The transistor 201 and the transistor 205 are both formed over a substrate 651. These transistors can be manufactured using the same material and the same process.

[0300] An insulating layer 211, an insulating layer 213, an insulating layer 215, and an insulating layer 214 are provided over the substrate 651 in this order. A part of the insulating layer 211 functions as a gate insulating layer for each transistor. A part of the insulating layer 213 functions as a gate insulating layer for each transistor. The insulating layer 215 is provided to cover the transistor. The insulating layer 214 is provided to cover the transistor and functions as a planarization layer. Note that the number of gate insulating layers and the number of insulating layers covering the transistors are not limited, and each may be a single layer or two or more layers.

[0301] At least one insulating layer covering the transistor is preferably made of a material that is resistant to the diffusion of impurities such as water and hydrogen. This allows the insulating layer to function as a barrier layer. With this structure, it is possible to effectively prevent impurities from diffusing into the transistor from the outside, thereby improving the reliability of the display device.

[0302] It is preferable to use an inorganic insulating film for each of the insulating layers 211, 213, and 215. Examples of the inorganic insulating film that can be used include a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a silicon nitride oxide film, an aluminum oxide film, and an aluminum nitride film. Alternatively, a hafnium oxide film, an yttrium oxide film, a zirconium oxide film, a gallium oxide film, a tantalum oxide film, a magnesium oxide film, a lanthanum oxide film, a cerium oxide film, and a neodymium oxide film may also be used. Two or more of the above insulating films may be stacked.

[0303] Here, organic insulating films often have lower barrier properties than inorganic insulating films. Therefore, it is preferable that the organic insulating film has an opening near the edge of the display device 500A. This can prevent impurities from entering from the edge of the display device 500A through the organic insulating film. Alternatively, the organic insulating film may be formed so that the edge of the organic insulating film is located inside the edge of the display device 500A, so that the organic insulating film is not exposed at the edge of the display device 500A.

[0304] An organic insulating film is suitable for the insulating layer 214, which functions as a planarizing layer. Materials that can be used for the organic insulating film include acrylic resin, polyimide resin, epoxy resin, polyamide resin, polyimideamide resin, siloxane resin, benzocyclobutene resin, phenol resin, and precursors of these resins. Alternatively, the insulating layer 214 may have a laminated structure of an organic insulating film and an inorganic insulating film.

[0305] 38A, an opening is formed in insulating layer 214. This makes it possible to prevent impurities from entering display unit 502 from the outside through insulating layer 214, even when an organic insulating film is used for insulating layer 214. This makes it possible to improve the reliability of display device 500A.

[0306] The transistor 201 and the transistor 205 each include a conductive layer 221 that functions as a gate electrode, an insulating layer 211 that functions as a gate insulating layer, conductive layers 222a and 222b that function as a source electrode and a drain electrode, a semiconductor layer 231, an insulating layer 213 that functions as a gate insulating layer, and a conductive layer 223 that functions as a gate electrode. Here, the same hatching pattern is applied to multiple layers obtained by processing the same conductive film. The insulating layer 211 is located between the conductive layer 221 and the semiconductor layer 231. The insulating layer 213 is located between the conductive layer 223 and the semiconductor layer 231.

[0307] The structure of the transistor included in the display device of this embodiment is not particularly limited. For example, a planar transistor, a staggered transistor, an inverted staggered transistor, or the like can be used. Furthermore, either a top-gate transistor or a bottom-gate transistor structure may be used. Alternatively, gates may be provided above and below a semiconductor layer in which a channel is formed.

[0308] The transistor 201 and the transistor 205 have a structure in which a semiconductor layer in which a channel is formed is sandwiched between two gates. The two gates may be connected and the same signal may be supplied to drive the transistor. Alternatively, the threshold voltage of the transistor may be controlled by applying a potential for controlling the threshold voltage to one of the two gates and a potential for driving to the other.

[0309] The crystallinity of a semiconductor material used for a transistor is not particularly limited, and any of an amorphous semiconductor and a crystalline semiconductor (a microcrystalline semiconductor, a polycrystalline semiconductor, a single crystal semiconductor, or a semiconductor having a crystalline region in part) may be used. The use of a crystalline semiconductor is preferable because it can suppress deterioration of transistor characteristics.

[0310] The semiconductor layer of the transistor preferably contains metal oxide. That is, the display device of this embodiment preferably uses a transistor using metal oxide in a channel formation region (hereinafter referred to as an OS transistor). Alternatively, the semiconductor layer of the transistor may contain silicon. Examples of silicon include amorphous silicon and crystalline silicon (such as low-temperature polysilicon and single-crystal silicon).

[0311] The semiconductor layer preferably contains, for example, indium, M (wherein M is one or more elements selected from gallium, aluminum, silicon, boron, yttrium, tin, copper, vanadium, beryllium, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, and magnesium), and zinc. In particular, M is preferably one or more elements selected from aluminum, gallium, yttrium, and tin.

[0312] In particular, it is preferable to use an oxide containing indium (In), gallium (Ga), and zinc (Zn) (also referred to as IGZO) as the semiconductor layer.

[0313] When the semiconductor layer is an In-M-Zn oxide, the atomic ratio of In in the In-M-Zn oxide is preferably equal to or greater than the atomic ratio of M. Examples of atomic ratios of metal elements in such In-M-Zn oxides include In:M:Zn=1:1:1 or a composition thereabout, In:M:Zn=1:1:1.2 or a composition thereabout, In:M:Zn=2:1:3 or a composition thereabout, In:M:Zn=3:1:2 or a composition thereabout, In:M:Zn=4:2:3 or a composition thereabout, In:M:Zn=4:2:4.1 or a composition thereabout, In:M:Zn=5:1:3 or a composition thereabout, In:M:Zn=5:1:6 or a composition thereabout, In:M:Zn=5:1:7 or a composition thereabout, In:M:Zn=5:1:8 or a composition thereabout, In:M:Zn=6:1:6 or a composition thereabout, and In:M:Zn=5:2:5 or a composition thereabout. The term "nearby composition" includes a range of ±30% of the desired atomic ratio.

[0314] For example, when describing a composition with an atomic ratio of In:Ga:Zn=4:2:3 or thereabout, this includes a case where, when the atomic ratio of In is 4, the atomic ratio of Ga is 1 or more and 3 or less, and the atomic ratio of Zn is 2 or more and 4 or less. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn=5:1:6 or thereabout, this includes a case where, when the atomic ratio of In is 5, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is 5 or more and 7 or less. Furthermore, when describing a composition with an atomic ratio of In:Ga:Zn=1:1:1 or thereabout, this includes a case where, when the atomic ratio of In is 1, the atomic ratio of Ga is more than 0.1 and 2 or less, and the atomic ratio of Zn is more than 0.1 and 2 or less.

[0315] The transistors included in the circuit 664 may have the same structure as or different from the transistors included in the display portion 502. The transistors included in the circuit 664 may all have the same structure or may have two or more types of structures. Similarly, the transistors included in the display portion 502 may all have the same structure or may have two or more types of structures.

[0316] 38B and 38C show other examples of transistor configurations.

[0317] The transistor 209 and the transistor 210 each include a conductive layer 221 functioning as a gate electrode, an insulating layer 211 functioning as a gate insulating layer, a semiconductor layer 231 including a channel formation region 231i and a pair of low-resistance regions 231n, a conductive layer 222a connected to one of the pair of low-resistance regions 231n, a conductive layer 222b connected to the other of the pair of low-resistance regions 231n, an insulating layer 225 functioning as a gate insulating layer, a conductive layer 223 functioning as a gate electrode, and an insulating layer 215 covering the conductive layer 223. The insulating layer 211 is located at least between the conductive layer 221 and the channel formation region 231i. The insulating layer 225 is located at least between the conductive layer 223 and the channel formation region 231i. An insulating layer 218 may be provided to cover the transistor.

[0318] 38B shows an example in which the insulating layer 225 covers the top surface and side surface of the semiconductor layer 231. The conductive layer 222a and the conductive layer 222b are connected to the low-resistance region 231n through openings provided in the insulating layer 225 and the insulating layer 215, respectively. One of the conductive layer 222a and the conductive layer 222b functions as a source electrode, and the other functions as a drain electrode.

[0319] 38C, the insulating layer 225 overlaps with the channel formation region 231i of the semiconductor layer 231 but does not overlap with the low-resistance region 231n. For example, the structure shown in FIG. 38C can be manufactured by processing the insulating layer 225 using the conductive layer 223 as a mask. In FIG. 38C, the insulating layer 215 is provided to cover the insulating layer 225 and the conductive layer 223, and the conductive layer 222a and the conductive layer 222b are each connected to the low-resistance region 231n through openings in the insulating layer 215.

[0320] A terminal portion 507 is provided in a region of the substrate 651 where the substrate 652 does not overlap. In the terminal portion 507, a wiring 665 is electrically connected to the FPC 672 via a conductive layer 666 and a connection layer 242. The conductive layer 666 can be a conductive film obtained by processing the same conductive film as the conductive layer 772. The conductive layer 666 is exposed on the upper surface of the terminal portion 507. This allows the wiring 665 and the FPC 672 to be electrically connected via the connection layer 242.

[0321] It is preferable to provide a light-shielding layer 617 on the surface of substrate 652 facing substrate 651. In addition, various optical members can be arranged on the outside of substrate 652. Examples of optical members include a polarizing plate, a retardation plate, a light diffusion layer (such as a diffusion film), an anti-reflection layer, and a light-collecting film. In addition, an antistatic film that suppresses the adhesion of dust, a water-repellent film that makes it difficult for dirt to adhere, a hard coat film that suppresses the occurrence of scratches during use, an impact absorbing layer, etc. may be arranged on the outside of substrate 652.

[0322] By providing the protective layers 471 and 458 that cover the light-emitting element, impurities such as water can be prevented from entering the light-emitting element, and the reliability of the light-emitting element can be improved.

[0323] In region 228 near the edge of display device 500A, insulating layer 215 and protective layer 471 or protective layer 458 preferably contact each other through the opening in insulating layer 214. In particular, it is preferable that inorganic insulating films contact each other. This makes it possible to prevent impurities from entering display unit 502 from the outside through the organic insulating film. This can therefore improve the reliability of display device 500A.

[0324] The substrate 651 and the substrate 652 can each be made of glass, quartz, ceramic, sapphire, resin, metal, alloy, semiconductor, or the like. A material that transmits light is used for the substrate on the side from which light from the light-emitting element is extracted. Using a flexible material for the substrate 651 and the substrate 652 can increase the flexibility of the display device. Alternatively, a polarizing plate may be used for the substrate 651 or the substrate 652.

[0325] Substrate 651 and substrate 652 can be made of polyester resin such as polyethylene terephthalate (PET) or polyethylene naphthalate (PEN), polyacrylonitrile resin, acrylic resin, polyimide resin, polymethyl methacrylate resin, polycarbonate (PC) resin, polyethersulfone (PES) resin, polyamide resin (nylon, aramid, etc.), polysiloxane resin, cycloolefin resin, polystyrene resin, polyamideimide resin, polyurethane resin, polyvinyl chloride resin, polyvinylidene chloride resin, polypropylene resin, polytetrafluoroethylene (PTFE) resin, ABS resin, cellulose nanofiber, etc. One or both of substrates 651 and 652 may be made of glass having a thickness sufficient to provide flexibility.

[0326] When a circularly polarizing plate is superimposed on a display device, it is preferable that the display device has a substrate with high optical isotropy. It can also be said that a substrate with high optical isotropy has small birefringence (small amount of birefringence).

[0327] The absolute value of the retardation (phase difference) of a substrate having high optical isotropy is preferably 30 nm or less, more preferably 20 nm or less, and even more preferably 10 nm or less.

[0328] Examples of films with high optical isotropy include triacetyl cellulose (TAC, also known as cellulose triacetate) films, cycloolefin polymer (COP) films, cycloolefin copolymer (COC) films, and acrylic films.

[0329] Furthermore, when a film is used as a substrate, the film may absorb water, causing deformation such as wrinkles in the display panel. Therefore, it is preferable to use a film with low water absorption for the substrate. For example, it is preferable to use a film with a water absorption rate of 1% or less, more preferably 0.1% or less, and even more preferably 0.01% or less.

[0330] The adhesive layer 642 can be made of a material similar to that used for the insulating layer 776 .

[0331] The connection layer 242 may be an anisotropic conductive film (ACF), an anisotropic conductive paste (ACP), or the like.

[0332] Materials that can be used for conductive layers such as gate electrodes, source electrodes, and drain electrodes of transistors, as well as various wirings and electrodes that constitute a display device, include metals such as aluminum, titanium, chromium, nickel, copper, yttrium, zirconium, molybdenum, silver, tantalum, and tungsten, and alloys containing these metals as main components, etc. Films containing these materials can be used as a single layer or a stacked layer structure.

[0333] Examples of light-transmitting conductive materials include conductive oxides such as indium oxide, indium tin oxide, indium zinc oxide, zinc oxide, and zinc oxide containing gallium, or graphene. Alternatively, metal materials such as gold, silver, platinum, magnesium, nickel, tungsten, chromium, molybdenum, iron, cobalt, copper, palladium, and titanium, or alloy materials containing such metal materials, can be used. Alternatively, nitrides of such metal materials (e.g., titanium nitride) can be used. When using metal materials or alloy materials (or their nitrides), it is preferable to thin them sufficiently to ensure light-transmitting properties. A stacked film of the above materials can also be used as a conductive layer. For example, a stacked film of an alloy of silver and magnesium and indium tin oxide is preferable because it can enhance conductivity. These can also be used for conductive layers such as various wirings and electrodes constituting a display device, and for conductive layers (conductive layers functioning as pixel electrodes or common electrodes) of light-emitting elements.

[0334] Examples of insulating materials that can be used for each insulating layer include resins such as acrylic resin and epoxy resin, and inorganic insulating materials such as silicon oxide, silicon oxynitride, silicon nitride oxide, silicon nitride, and aluminum oxide.

[0335] [Display device 500B] 39 is different from the display device 500A mainly in that it is a bottom emission type. Note that a description of the same parts as the display device 500A will be omitted.

[0336] Light emitted from the light-emitting element is emitted to the substrate 651 side. A material that is highly transparent to visible light is preferably used for the substrate 651. On the other hand, the light-transmitting property of a material used for the substrate 652 does not matter.

[0337] A light-shielding layer 617 is preferably formed between the substrate 651 and the transistor 201 and between the substrate 651 and the transistor 205. Figure 39 shows an example in which the light-shielding layer 617 is provided over the substrate 651, the insulating layer 653 is provided over the light-shielding layer 617, and the transistor 201, the transistor 205, and the like are provided over the insulating layer 653.

[0338] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0339] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes or examples described in this specification.

[0340] (Embodiment 3) In this embodiment, a display device according to one embodiment of the present invention will be described.

[0341] The display device of the present embodiment can be a high-definition display device, and can therefore be used as a display unit for information terminals (wearable devices) such as wristwatches and bracelets, as well as for wearable devices that can be worn on the head, such as VR devices such as head-mounted displays and AR devices such as glasses.

[0342] [Display module] 40A shows a perspective view of display module 280. Display module 280 has a display device 500C and an FPC 290. Note that the display device included in display module 280 is not limited to display device 500C, and may be display device 500D or display device 500E, which will be described later.

[0343] The display module 280 includes a substrate 291 and a substrate 292. The display module 280 includes a display unit 502. The display unit 502 is a region that displays an image in the display module 280, and is a region where light from each pixel provided in a pixel unit 284 (described later) can be viewed.

[0344] 40B is a perspective view showing a schematic configuration of the substrate 291 side. On the substrate 291, a circuit section 282, a pixel circuit section 283 on the circuit section 282, and a pixel section 284 on the pixel circuit section 283 are stacked. In addition, a terminal section 507 for connecting to the FPC 290 is provided in a portion of the substrate 291 that does not overlap with the pixel section 284. The terminal section 507 and the circuit section 282 are electrically connected by a wiring section 286 consisting of a plurality of wirings.

[0345] The pixel section 284 has a plurality of periodically arranged pixels 284a. An enlarged view of one pixel 284a is shown on the right side of FIG. 40B. The pixel 284a has light-emitting elements 572R, 572G, and 572B, which emit light of different colors. The plurality of light-emitting elements can be arranged in a stripe array as shown in FIG. 40B. Various light-emitting element arrangement methods, such as a delta array or a pentile array, can also be used.

[0346] The pixel circuit section 283 has a plurality of pixel circuits 283a arranged periodically.

[0347] One pixel circuit 283a is a circuit that controls the light emission of three light-emitting elements included in one pixel 284a. One pixel circuit 283a may be configured to have three circuits that control the light emission of one light-emitting element. For example, the pixel circuit 283a may be configured to have at least one selection transistor, one current control transistor (drive transistor), and a capacitor for each light-emitting element. In this case, a gate signal is input to the gate of the selection transistor, and a video signal is input to either the source or the drain. This realizes an active matrix display device.

[0348] The circuit portion 282 includes a circuit for driving each pixel circuit 283a of the pixel circuit portion 283. For example, it is preferable that the circuit portion 282 includes one or both of a gate line driver circuit and a source line driver circuit. In addition, the circuit portion 282 may include at least one of an arithmetic circuit, a memory circuit, a power supply circuit, and the like.

[0349] The FPC 290 functions as wiring for supplying a video signal, a power supply potential, or the like from the outside to the circuit section 282. An IC may be mounted on the FPC 290.

[0350] The display module 280 can be configured such that one or both of the pixel circuit unit 283 and the circuit unit 282 are stacked below the pixel unit 284, thereby enabling the aperture ratio (effective display area ratio) of the display unit 502 to be extremely high. For example, the aperture ratio of the display unit 502 can be set to 40% or more and less than 100%, preferably 50% or more and 95% or less, and more preferably 60% or more and 95% or less. Furthermore, the pixels 284a can be arranged at an extremely high density, enabling the resolution of the display unit 502 to be extremely high. For example, it is preferable that the pixels 284a are arranged in the display unit 502 at a resolution of 2000 ppi or more, preferably 3000 ppi or more, more preferably 5000 ppi or more, and even more preferably 6000 ppi or more, and 20000 ppi or less, or 30000 ppi or less.

[0351] Such a display module 280 has extremely high resolution and can therefore be suitably used in VR devices such as head-mounted displays or eyeglass-type AR devices. For example, even in a configuration in which the display unit of the display module 280 is viewed through lenses, the display module 280 has an extremely high-resolution display unit 502, so that even if the display unit is enlarged with lenses, the pixels are not visible, allowing for a highly immersive display. Furthermore, the display module 280 is not limited to this, and can be suitably used in electronic devices having relatively small display units. For example, it can be suitably used in the display unit of a wearable electronic device such as a wristwatch.

[0352] [Display device 500C] A display device 500C shown in Fig. 41 includes a substrate 301, a light emitting element 572R, a light emitting element 572G, a light emitting element 572B, a capacitor 240, and a transistor 310. The substrate 301 corresponds to the substrate 291 in Figs. 40A and 40B.

[0353] The transistor 310 has a channel formation region in a substrate 301. The substrate 301 can be, for example, a semiconductor substrate such as a single crystal silicon substrate. The transistor 310 includes a part of the substrate 301, a conductive layer 311, a low-resistance region 312, an insulating layer 313, and an insulating layer 314. The conductive layer 311 functions as a gate electrode. The insulating layer 313 is located between the substrate 301 and the conductive layer 311 and functions as a gate insulating layer. The low-resistance region 312 is a region in which the substrate 301 is doped with impurities and functions as a source or drain. The insulating layer 314 is provided to cover a side surface of the conductive layer 311.

[0354] Furthermore, an element isolation layer 315 is provided between two adjacent transistors 310 so as to be embedded in the substrate 301 .

[0355] In addition, an insulating layer 261 is provided to cover the transistor 310 , and a capacitor 240 is provided on the insulating layer 261 .

[0356] Capacitor 240 has conductive layer 241, conductive layer 245, and insulating layer 243 positioned therebetween. Conductive layer 241 functions as one electrode of capacitor 240, conductive layer 245 functions as the other electrode of capacitor 240, and insulating layer 243 functions as a dielectric of capacitor 240.

[0357] The conductive layer 241 is provided over the insulating layer 261 and is buried in the insulating layer 254. The conductive layer 241 is electrically connected to one of the source and drain of the transistor 310 by a plug 271 buried in the insulating layer 261. The insulating layer 243 is provided to cover the conductive layer 241. The conductive layer 245 is provided in a region overlapping with the conductive layer 241 with the insulating layer 243 interposed therebetween.

[0358] An insulating layer 255a is provided to cover the capacitor 240, an insulating layer 255b is provided on the insulating layer 255a, and light-emitting elements 572R, 572G, and 572B are provided on the insulating layer 255b. In this embodiment, an example is shown in which the light-emitting elements 572R, 572G, and 572B have the layered structure shown in FIG. 35B. Side surfaces of the conductive layer 772, the EL layer 786R, the EL layer 786G, the EL layer 786B, and the conductive layer 788 are each covered with a protective layer 471. A protective layer 458 is provided on the protective layer 471, and a substrate 620 is bonded to the protective layer 458 with a resin layer 622. The substrate 620 corresponds to the substrate 292 in FIG. 40A.

[0359] The insulating layer 255a and the insulating layer 255b can be preferably formed using various inorganic insulating films such as an insulating oxide film, a nitride insulating film, an oxynitride insulating film, and a nitride oxide insulating film. The insulating layer 255a is preferably formed using an oxide insulating film or an oxynitride insulating film such as a silicon oxide film, a silicon oxynitride film, or an aluminum oxide film. The insulating layer 255b is preferably formed using a nitride insulating film or a nitride oxide insulating film such as a silicon nitride film or a silicon nitride oxide film. More specifically, the insulating layer 255a is preferably formed using a silicon oxide film, and the insulating layer 255b is preferably formed using a silicon nitride film. The insulating layer 255b preferably functions as an etching protective film. Alternatively, the insulating layer 255a may be formed using a nitride insulating film or a nitride oxide insulating film, and the insulating layer 255b may be formed using an oxide insulating film or an oxynitride insulating film. Although this embodiment shows an example in which a recess is provided in the insulating layer 255b, the insulating layer 255b does not necessarily have a recess.

[0360] The pixel electrode of the light-emitting element is electrically connected to one of the source and drain of the transistor 310 via a plug 256 embedded in the insulating layer 255a, the insulating layer 255b, and the insulating layer 243, a conductive layer 241 embedded in the insulating layer 254, and a plug 271 embedded in the insulating layer 261. The height of the top surface of the insulating layer 255b and the height of the top surface of the plug 256 are the same or approximately the same. Various conductive materials can be used for the plug.

[0361] [Display device 500D] 42 differs from display device 500C mainly in the configuration of the transistors. Note that descriptions of parts that are the same as those of display device 500C may be omitted.

[0362] The transistor 320 is a transistor (OS transistor) in which a metal oxide is applied to a semiconductor layer in which a channel is formed.

[0363] The transistor 320 includes a semiconductor layer 321, an insulating layer 323, a conductive layer 324, a pair of conductive layers 325, an insulating layer 326, and a conductive layer 327. A substrate 331 corresponds to the substrate 291 in Figures 40A and 40B. The substrate 331 can be an insulating substrate or a semiconductor substrate.

[0364] An insulating layer 332 is provided over a substrate 331. The insulating layer 332 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the substrate 331 to the transistor 320 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 332. The insulating layer 332 can be, for example, a film through which hydrogen or oxygen is less likely to diffuse than a silicon oxide film, such as an aluminum oxide film, a hafnium oxide film, or a silicon nitride film.

[0365] A conductive layer 327 is provided over the insulating layer 332, and an insulating layer 326 is provided to cover the conductive layer 327. The conductive layer 327 functions as a first gate electrode of the transistor 320, and part of the insulating layer 326 functions as a first gate insulating layer. An oxide insulating film such as a silicon oxide film is preferably used for at least a portion of the insulating layer 326 that is in contact with the semiconductor layer 321. The top surface of the insulating layer 326 is preferably planarized.

[0366] The semiconductor layer 321 is provided over the insulating layer 326. The semiconductor layer 321 preferably includes a metal oxide film having semiconductor properties.

[0367] A pair of conductive layers 325 is provided over and in contact with the semiconductor layer 321 and functions as a source electrode and a drain electrode.

[0368] An insulating layer 328 is provided to cover top surfaces and side surfaces of the pair of conductive layers 325 and side surfaces of the semiconductor layer 321, and an insulating layer 264 is provided over the insulating layer 328. The insulating layer 328 functions as a barrier layer that prevents impurities such as water or hydrogen from the insulating layer 264 or the like from diffusing into the semiconductor layer 321 and prevents oxygen from being released from the semiconductor layer 321 toward the insulating layer 328. The insulating layer 328 can be formed using an insulating film similar to the insulating layer 332.

[0369] An opening reaching the semiconductor layer 321 is provided in the insulating layer 328 and the insulating layer 264. An insulating layer 323 and a conductive layer 324 are buried inside the opening and are in contact with the side surfaces of the insulating layer 264, the insulating layer 328, and the conductive layer 325 and the top surface of the semiconductor layer 321. The conductive layer 324 functions as a second gate electrode, and the insulating layer 323 functions as a second gate insulating layer.

[0370] The upper surfaces of the conductive layer 324, the insulating layer 323, and the insulating layer 264 are planarized so that their heights are the same or approximately the same, and insulating layers 329 and 265 are provided to cover them.

[0371] The insulating layer 264 and the insulating layer 265 function as interlayer insulating layers. The insulating layer 329 functions as a barrier layer that prevents impurities such as water or hydrogen from diffusing from the insulating layer 265 or the like to the transistor 320. The insulating layer 329 can be formed using an insulating film similar to the insulating layer 328 and the insulating layer 332.

[0372] The plug 274 electrically connected to one of the pair of conductive layers 325 is provided to be embedded in the insulating layer 265, the insulating layer 329, the insulating layer 264, and the insulating layer 328. Here, the plug 274 preferably includes a conductive layer 274a covering the side surfaces of the openings in the insulating layer 265, the insulating layer 329, the insulating layer 264, and the insulating layer 328 and part of the top surface of the conductive layer 325, and a conductive layer 274b in contact with the top surface of the conductive layer 274a. In this case, the conductive layer 274a is preferably made of a conductive material through which hydrogen and oxygen do not easily diffuse.

[0373] The configuration of the display device 500D from the insulating layer 254 to the substrate 620 is the same as that of the display device 500C.

[0374] [Display device 500E] 43 has a stacked structure of a transistor 310 in which a channel is formed in a substrate 301 and a transistor 320 in which a channel is formed and a semiconductor layer in which a metal oxide is included. Note that descriptions of parts that are the same as those of the display device 500C and the display device 500D may be omitted.

[0375] An insulating layer 261 is provided to cover the transistor 310, and a conductive layer 251 is provided over the insulating layer 261. An insulating layer 262 is provided to cover the conductive layer 251, and a conductive layer 252 is provided over the insulating layer 262. The conductive layers 251 and 252 each function as wirings. An insulating layer 263 and an insulating layer 332 are provided to cover the conductive layer 252, and a transistor 320 is provided over the insulating layer 332. An insulating layer 265 is provided to cover the transistor 320, and a capacitor 240 is provided over the insulating layer 265. The capacitor 240 and the transistor 320 are electrically connected by a plug 274.

[0376] The transistor 320 can be used as a transistor included in a pixel circuit. The transistor 310 can be used as a transistor included in a pixel circuit or a driver circuit (such as a scan line driver circuit or a signal line driver circuit) for driving the pixel circuit. The transistors 310 and 320 can be used as transistors included in various circuits such as an arithmetic circuit or a memory circuit.

[0377] By using this configuration, not only the pixel circuit but also, for example, a driver circuit can be formed directly under the light-emitting element, which makes it possible to reduce the size of the display device compared to when the driver circuit is provided around the periphery of the display area.

[0378] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0379] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes or examples described in this specification.

[0380] (Fourth embodiment) In this embodiment, a metal oxide that can be used for the OS transistor described in the above embodiment will be described.

[0381] The metal oxide preferably contains at least indium or zinc. It is particularly preferable that it contains indium and zinc. Furthermore, it is preferable that it contains aluminum, gallium, yttrium, tin, or the like in addition to these. It may also contain one or more elements selected from boron, silicon, titanium, iron, nickel, germanium, zirconium, molybdenum, lanthanum, cerium, neodymium, hafnium, tantalum, tungsten, magnesium, cobalt, and the like.

[0382] The metal oxide can be formed by a sputtering method, a CVD method such as a metal organic chemical vapor deposition (MOCVD: Metal Organic CVD) method, or an ALD method.

[0383] <Classification of crystal structures> Examples of the crystalline structure of oxide semiconductors include amorphous (including completely amorphous), c-axis-aligned crystalline (CAAC), nanocrystalline (nc), cloud-aligned composite (CAC), single crystal, and polycrystal.

[0384] The crystalline structure of the film or substrate can be evaluated using X-ray diffraction (XRD) spectra. For example, it can be evaluated using XRD spectra obtained by GIXD (Grazing-Incidence XRD) measurements. The GIXD method is also called the thin film method or the Seemann-Bohlin method.

[0385] For example, in the case of a quartz glass substrate, the peak shape of the XRD spectrum is nearly symmetrical. On the other hand, in the case of an IGZO film having a crystalline structure, the peak shape of the XRD spectrum is asymmetrical. The asymmetrical peak shape of the XRD spectrum clearly indicates the presence of crystals in the film or substrate. In other words, if the peak shape of the XRD spectrum is not symmetrical, the film or substrate cannot be said to be in an amorphous state.

[0386] The crystalline structure of a film or substrate can be evaluated by a diffraction pattern (also called a nanobeam electron diffraction pattern) observed using nanobeam electron diffraction (NBED). For example, a halo is observed in the diffraction pattern of a quartz glass substrate, confirming that the quartz glass is in an amorphous state. Furthermore, a spot-like pattern is observed in the diffraction pattern of an IGZO film deposited at room temperature, rather than a halo. For this reason, it is estimated that an IGZO film deposited at room temperature is neither crystalline nor amorphous, but is in an intermediate state, and it cannot be concluded that it is in an amorphous state.

[0387] <<Oxide semiconductor structure>> Note that oxide semiconductors may be classified differently from the above when focusing on their structures. For example, oxide semiconductors are divided into single-crystal oxide semiconductors and other non-single-crystal oxide semiconductors. Examples of non-single-crystal oxide semiconductors include the above-mentioned CAAC-OS and nc-OS. Non-single-crystal oxide semiconductors include polycrystalline oxide semiconductors, amorphous-like oxide semiconductors (a-like OSs), amorphous oxide semiconductors, and the like.

[0388] Here, the above-mentioned CAAC-OS, nc-OS, and a-like OS will be described in detail.

[0389] [CAAC-OS] CAAC-OS is an oxide semiconductor having multiple crystalline regions, each with its c-axis aligned in a specific direction. The specific direction can be the thickness direction of the CAAC-OS film, the normal direction to the surface on which the CAAC-OS film is formed, or the normal direction to the surface of the CAAC-OS film. A crystalline region is a region with periodic atomic arrangement. Considering an atomic arrangement as a lattice arrangement, a crystalline region can also be a region with a uniform lattice arrangement. Furthermore, CAAC-OS has a region where multiple crystalline regions are connected in the ab-plane direction, and the region may have distortion. The distortion refers to a location where the lattice orientation changes between a region with a uniform lattice arrangement and a region with a different uniform lattice arrangement in the region where multiple crystalline regions are connected. In other words, CAAC-OS is an oxide semiconductor with a c-axis aligned but no clear orientation in the ab-plane direction.

[0390] Each of the multiple crystalline regions is composed of one or more minute crystals (crystals with a maximum diameter of less than 10 nm). When a crystalline region is composed of one minute crystal, the maximum diameter of the crystalline region is less than 10 nm. When a crystalline region is composed of many minute crystals, the size of the crystalline region may be several tens of nm.

[0391] In an In-M-Zn oxide (wherein element M is one or more elements selected from aluminum, gallium, yttrium, tin, titanium, etc.), the CAAC-OS tends to have a layered crystal structure (also referred to as a layered structure) in which a layer containing indium (In) and oxygen (hereinafter referred to as an In layer) and a layer containing element M, zinc (Zn), and oxygen (hereinafter referred to as an (M, Zn) layer) are stacked. Note that indium and element M are mutually substituted. Therefore, the (M, Zn) layer may contain indium. Furthermore, the In layer may contain element M. Furthermore, the In layer may contain Zn. The layered structure is observed as a lattice image in, for example, a high-resolution transmission electron microscope (TEM) image.

[0392] When the CAAC-OS film is subjected to structural analysis using, for example, an XRD apparatus, a peak indicating c-axis orientation is detected at or near 2θ=31° in out-of-plane XRD measurement using θ / 2θ scan. Note that the position of the peak indicating c-axis orientation (2θ value) may vary depending on the type or composition of the metal elements constituting the CAAC-OS.

[0393] For example, in the electron diffraction pattern of a CAAC-OS film, multiple bright spots are observed, and the spots are observed at positions that are point-symmetric with respect to the spot of the incident electron beam that has passed through the sample (also called the direct spot).

[0394] When the crystalline region is observed from the specific direction, the lattice arrangement in the crystalline region is basically a hexagonal lattice, but the unit cell is not necessarily a regular hexagon and may be non-regular hexagonal. The distortion may also have a pentagonal or heptagonal lattice arrangement. In the CAAC-OS, no clear grain boundaries can be observed even near the distortion. This indicates that the formation of grain boundaries is suppressed by the distortion of the lattice arrangement. This is thought to be because the CAAC-OS can tolerate distortion due to the lack of close-packed oxygen atom arrangement in the ab-plane direction and the change in interatomic bond distance caused by metal atom substitution.

[0395] A crystal structure with clear grain boundaries is called polycrystalline. Grain boundaries are likely to become recombination centers, trapping carriers and reducing the on-state current and field-effect mobility of a transistor. Therefore, CAAC-OS, which lacks clear grain boundaries, is one of the crystalline oxides with a crystal structure suitable for use in a transistor semiconductor layer. Zn is preferred for use in CAAC-OS. For example, In-Zn oxide and In-Ga-Zn oxide are suitable because they can suppress the generation of grain boundaries more effectively than In oxide.

[0396] The CAAC-OS is an oxide semiconductor with high crystallinity and no clear grain boundaries. Therefore, it can be said that the CAAC-OS is less susceptible to a decrease in electron mobility due to grain boundaries. Furthermore, since the crystallinity of an oxide semiconductor can be reduced by impurities or defects, the CAAC-OS can be said to be an oxide semiconductor with few impurities and defects (such as oxygen vacancies). Therefore, oxide semiconductors with CAAC-OS have stable physical properties. Therefore, oxide semiconductors with CAAC-OS are heat-resistant and highly reliable. Furthermore, the CAAC-OS is stable even under high temperatures (so-called thermal budgets) during the manufacturing process. Therefore, using a CAAC-OS for an OS transistor can increase the flexibility of the manufacturing process.

[0397] [nc-OS] The nc-OS has periodic atomic arrangement in a microscopic region (e.g., a region of 1 nm to 10 nm, particularly a region of 1 nm to 3 nm). In other words, the nc-OS has microcrystals. Note that the size of the microcrystals is, for example, 1 nm to 10 nm, particularly 1 nm to 3 nm, and therefore the microcrystals are also called nanocrystals. Furthermore, the nc-OS exhibits no regularity in the crystal orientation between different nanocrystals. Therefore, no orientation is observed throughout the film. Therefore, depending on the analytical method, the nc-OS may be indistinguishable from an a-like OS or an amorphous oxide semiconductor. For example, when a structural analysis of an nc-OS film is performed using an XRD apparatus, no peaks indicating crystallinity are detected in out-of-plane XRD measurements using θ / 2θ scanning. Furthermore, when an nc-OS film is subjected to electron diffraction (also known as selected-area electron diffraction) using an electron beam with a probe diameter larger than that of nanocrystals (e.g., 50 nm or larger), a halo-like diffraction pattern is observed. On the other hand, when electron diffraction (also called nanobeam electron diffraction) is performed on an nc-OS film using an electron beam with a probe diameter close to or smaller than the size of the nanocrystals (for example, 1 nm to 30 nm), an electron diffraction pattern can be obtained in which multiple spots are observed within a ring-shaped region centered on the direct spot.

[0398] [a-like OS] The a-like OS is an oxide semiconductor having a structure between the nc-OS and the amorphous oxide semiconductor. The a-like OS has a pore or low-density region. That is, the a-like OS has lower crystallinity than the nc-OS and CAAC-OS. Furthermore, the a-like OS has a higher hydrogen concentration in the film than the nc-OS and CAAC-OS.

[0399] <<Oxide semiconductor structure>> Next, the above-mentioned CAC-OS will be described in detail, which relates to the material composition.

[0400] [CAC-OS] CAC-OS is a material structure in which elements constituting a metal oxide are unevenly distributed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof. Note that, hereinafter, a metal oxide in which one or more metal elements are unevenly distributed and the regions containing the metal elements are mixed in a size range of 0.5 nm to 10 nm, preferably 1 nm to 3 nm, or in the vicinity thereof, is also referred to as a mosaic or patch state.

[0401] Furthermore, CAC-OS has a mosaic structure in which the material is separated into first and second regions, and the first regions are distributed throughout the film (hereinafter also referred to as a cloud structure). That is, CAC-OS is a composite metal oxide having a structure in which the first and second regions are mixed.

[0402] Here, the atomic ratios of In, Ga, and Zn to the metal elements constituting the CAC-OS in the In-Ga-Zn oxide are denoted as [In], [Ga], and [Zn], respectively. For example, in the CAC-OS in the In-Ga-Zn oxide, the first region is a region where [In] is larger than [In] in the composition of the CAC-OS film. The second region is a region where [Ga] is larger than [Ga] in the composition of the CAC-OS film. Alternatively, for example, the first region is a region where [In] is larger than [In] in the second region and [Ga] is smaller than [Ga] in the second region. The second region is a region where [Ga] is larger than [Ga] in the first region and [In] is smaller than [In] in the first region.

[0403] Specifically, the first region is a region whose main component is indium oxide, indium zinc oxide, or the like. The second region is a region whose main component is gallium oxide, gallium zinc oxide, or the like. In other words, the first region can be rephrased as a region whose main component is In. The second region can be rephrased as a region whose main component is Ga.

[0404] It should be noted that there are cases where a clear boundary between the first region and the second region cannot be observed.

[0405] In addition, CAC-OS in In-Ga-Zn oxide refers to a material structure containing In, Ga, Zn, and O, in which some regions primarily composed of Ga and other regions primarily composed of In are randomly arranged in a mosaic pattern. Therefore, it is presumed that CAC-OS has a structure in which metal elements are distributed nonuniformly.

[0406] The CAC-OS can be formed, for example, by a sputtering method without heating the substrate. When the CAC-OS is formed by a sputtering method, one or more of an inert gas (typically argon), oxygen gas, and nitrogen gas may be used as the deposition gas. The lower the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition, the more preferable it is. For example, the flow rate of oxygen gas relative to the total flow rate of deposition gas during deposition is preferably 0% or more and less than 30%, and more preferably 0% or more and 10% or less.

[0407] Furthermore, for example, in the case of CAC-OS in an In-Ga-Zn oxide, EDX mapping obtained using EDX (Energy Dispersive X-ray spectroscopy) confirms that the CAC-OS has a structure in which a region containing In as a main component (first region) and a region containing Ga as a main component (second region) are unevenly distributed and mixed.

[0408] Here, the first region has higher conductivity than the second region. That is, the flow of carriers through the first region causes the metal oxide to exhibit conductivity. Therefore, the first region is distributed in a cloud-like manner in the metal oxide, thereby achieving a high field-effect mobility (μ).

[0409] On the other hand, the second region has higher insulating properties than the first region. That is, the second region is distributed in the metal oxide, thereby suppressing leakage current.

[0410] Therefore, when CAC-OS is used in a transistor, the conductivity due to the first region and the insulating property due to the second region act complementarily, thereby providing the CAC-OS with a switching function (the ability to turn on and off). In other words, CAC-OS has a conductive function in part of the material and an insulating function in part of the material, and the material as a whole functions as a semiconductor. By separating the conductive function from the insulating function, both functions can be maximized. Therefore, by using CAC-OS in a transistor, a high on-current (I on ), high field-effect mobility (μ), and good switching behavior can be achieved.

[0411] Furthermore, transistors using CAC-OS have high reliability, making them ideal for various semiconductor devices such as display devices.

[0412] Oxide semiconductors have a variety of structures and each has different characteristics. The oxide semiconductor of one embodiment of the present invention may include two or more of an amorphous oxide semiconductor, a polycrystalline oxide semiconductor, an a-like OS, a CAC-OS, an nc-OS, and a CAAC-OS.

[0413] <Transistors containing oxide semiconductors> Next, a case where the oxide semiconductor is used in a transistor will be described.

[0414] By using the oxide semiconductor for a transistor, a transistor with high field-effect mobility and high reliability can be realized.

[0415] For the transistor, an oxide semiconductor having a low carrier concentration is preferably used. For example, the carrier concentration of the oxide semiconductor is 1×10 17 cm -3 Less than 1 × 10 15 cm -3 or less, more preferably 1 × 10 13 cm-3 Less than 1×10, more preferably 11 cm -3 or less, more preferably 1 × 10 10 cm -3 Less than 1 x 10 -9 cm -3 The above is the case. Note that in order to reduce the carrier concentration of an oxide semiconductor film, the impurity concentration in the oxide semiconductor film may be reduced to reduce the density of defect states. In this specification and the like, a semiconductor having a low impurity concentration and a low density of defect states is referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor. Note that an oxide semiconductor having a low carrier concentration may also be referred to as a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor.

[0416] Furthermore, a highly purified intrinsic or substantially highly purified intrinsic oxide semiconductor film has a low density of defect states, and therefore the density of trap states may also be low.

[0417] Furthermore, charges trapped in the trap states of an oxide semiconductor take a long time to dissipate and may behave like fixed charges. Therefore, a transistor in which a channel formation region is formed in an oxide semiconductor with a high density of trap states may have unstable electrical characteristics.

[0418] Therefore, in order to stabilize the electrical characteristics of a transistor, it is effective to reduce the impurity concentration in the oxide semiconductor. Furthermore, in order to reduce the impurity concentration in the oxide semiconductor, it is preferable to also reduce the impurity concentration in the adjacent film. Examples of impurities include hydrogen, nitrogen, alkali metals, alkaline earth metals, iron, nickel, and silicon.

[0419] <Impurities> Here, the influence of each impurity in an oxide semiconductor will be described.

[0420] When an oxide semiconductor contains silicon or carbon, which is one of the Group 14 elements, defect levels are formed in the oxide semiconductor. Therefore, the concentration of silicon or carbon in the oxide semiconductor and the concentration of silicon or carbon near the interface with the oxide semiconductor (concentration obtained by secondary ion mass spectrometry (SIMS)) are calculated to be 2×10 18 atoms / cm 3 Less than or equal to 2 x 10 17 atoms / cm 3 The following applies.

[0421] Furthermore, when an oxide semiconductor contains an alkali metal or an alkaline earth metal, defect states may be formed and carriers may be generated. Therefore, a transistor using an oxide semiconductor containing an alkali metal or an alkaline earth metal is likely to have normally-on characteristics. For this reason, when the concentration of the alkali metal or the alkaline earth metal in the oxide semiconductor obtained by SIMS is 1×10 18 atoms / cm 3 Less than or equal to 2 x 10 16 atoms / cm 3 Do the following:

[0422] Furthermore, when nitrogen is contained in an oxide semiconductor, electrons serving as carriers are generated, the carrier concentration increases, and the semiconductor is likely to become n-type. As a result, a transistor using an oxide semiconductor containing nitrogen as a semiconductor tends to have normally-on characteristics. Alternatively, when nitrogen is contained in an oxide semiconductor, trap states may be formed. As a result, the electrical characteristics of the transistor may become unstable. For this reason, the nitrogen concentration in the oxide semiconductor obtained by SIMS is set to 5×10 19 atoms / cm 3 Less than 5 x 10 18 atoms / cm 3 Less than 1×10, more preferably 18 atoms / cm 3 Less than 5 × 10, more preferably 17 atoms / cm 3 Do the following:

[0423] Furthermore, hydrogen contained in an oxide semiconductor may react with oxygen bonded to a metal atom to form water, forming an oxygen vacancy. When hydrogen enters the oxygen vacancy, electrons serving as carriers may be generated. Furthermore, some of the hydrogen may bond with oxygen bonded to a metal atom to generate electrons serving as carriers. Therefore, a transistor using an oxide semiconductor containing hydrogen is likely to have normally-on characteristics. For this reason, it is preferable to reduce the amount of hydrogen in the oxide semiconductor as much as possible. Specifically, when the hydrogen concentration in an oxide semiconductor obtained by SIMS is 1×10 20 atoms / cm 3 Less than 1 x 10 19 atoms / cm 3 less than 5 × 10 18 atoms / cm 3 less than 1×10 18 atoms / cm 3 Make it less than.

[0424] When an oxide semiconductor with sufficiently reduced impurities is used for a channel formation region of a transistor, stable electrical characteristics can be obtained.

[0425] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes or examples described in this specification.

[0426] (Embodiment 5) In this embodiment, electronic devices of one embodiment of the present invention will be described with reference to FIGS.

[0427] The electronic devices of this embodiment include, for example, the display device of one embodiment of the present invention, which can provide high-definition display and high reliability.

[0428] Examples of electronic devices include electronic devices with relatively large screens such as television sets, desktop or notebook personal computers, computer monitors, digital signage, large game machines such as pachinko machines, as well as digital cameras, digital video cameras, digital photo frames, mobile phones, portable game machines, personal digital assistants, and sound playback devices.

[0429] In particular, the display device of one embodiment of the present invention can have high resolution and can therefore be suitably used in electronic devices having a relatively small display area. Examples of such electronic devices include wristwatch-type and bracelet-type information terminals (wearable devices), and head-mounted wearable devices such as VR devices (head-mounted displays), eyeglass-type AR devices, and MR devices.

[0430] The display device of one embodiment of the present invention preferably has an extremely high resolution such as HD (1280 × 720 pixels), FHD (1920 × 1080 pixels), WQHD (2560 × 1440 pixels), WQXGA (2560 × 1600 pixels), 4K (3840 × 2160 pixels), or 8K (7680 × 4320 pixels). A resolution of 4K, 8K, or higher is particularly preferable. Furthermore, the pixel density (resolution) of the display device of one embodiment of the present invention is preferably 100 ppi or higher, preferably 300 ppi or higher, more preferably 500 ppi or higher, more preferably 1000 ppi or higher, more preferably 2000 ppi or higher, more preferably 3000 ppi or higher, more preferably 5000 ppi or higher, and even more preferably 7000 ppi or higher. By using a display device having either or both of high resolution and high definition, it is possible to further enhance the sense of realism and depth in electronic devices for personal use, such as portable or home use. Furthermore, the screen ratio (aspect ratio) of the display device of one embodiment of the present invention is not particularly limited. For example, the display device can support various screen ratios such as 1:1 (square), 4:3, 16:9, or 16:10.

[0431] The electronic device of this embodiment may have a sensor (including a function to measure force, displacement, position, velocity, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor, or infrared rays).

[0432] The electronic device of the present embodiment can have various functions, such as a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to execute various software (programs), a wireless communication function, a function to read out programs or data recorded on a recording medium, etc.

[0433] Examples of wearable devices that can be worn on the head will be described using Figures 44A, 44B, 45A, and 45B. These wearable devices have one or both of a function to display AR content and a function to display VR content. Note that these wearable devices may also have a function to display SR or MR content in addition to AR and VR. By having an electronic device have the function to display content such as AR, VR, SR, or MR, it is possible to enhance the user's sense of immersion.

[0434] Electronic device 700A shown in FIG. 44A and electronic device 700B shown in FIG. 44B each have a pair of display panels 751, a pair of housings 721, a communication unit (not shown), a pair of mounting units 723, a control unit (not shown), an imaging unit (not shown), a pair of optical members 753, a frame 757, and a pair of nose pads 758.

[0435] The display device of one embodiment of the present invention can be applied to the electronic device 700A and the electronic device 700B. Therefore, the electronic device 700A and the electronic device 700B can be highly reliable electronic devices capable of displaying images with extremely high resolution.

[0436] Each of electronic devices 700A and 700B can project an image displayed on display panel 751 onto display area 756 of optical member 753. Because optical member 753 is translucent, the user can see the image displayed in the display area superimposed on a transmitted image visually recognized through optical member 753. Therefore, each of electronic devices 700A and 700B is an electronic device capable of AR display.

[0437] Electronic device 700A and electronic device 700B may be provided with a camera capable of capturing an image in front of them as an imaging unit. Furthermore, electronic device 700A and electronic device 700B may each be provided with an acceleration sensor such as a gyro sensor, thereby detecting the orientation of the user's head and displaying an image corresponding to that orientation in display area 756.

[0438] The communication unit has a wireless communication device, and can supply, for example, a video signal via the wireless communication device. Note that instead of or in addition to the wireless communication device, a connector to which a cable through which a video signal and a power supply potential can be connected may be provided.

[0439] Furthermore, the electronic device 700A and the electronic device 700B are provided with batteries, which can be charged wirelessly and / or by wire.

[0440] The housing 721 may be provided with a touch sensor module. The touch sensor module has a function of detecting a touch on the outer surface of the housing 721. The touch sensor module can detect a tap operation, a slide operation, or the like by the user and perform various processes. For example, a tap operation can perform a process such as pausing or resuming a video, and a slide operation can perform a process such as fast-forwarding or fast-rewinding. Furthermore, providing a touch sensor module on each of the two housings 721 can widen the range of operations.

[0441] The touch sensor module can be implemented using various touch sensors or near-touch sensors, such as capacitance sensors, resistive sensors, infrared sensors, electromagnetic induction sensors, surface acoustic wave sensors, and optical sensors. In particular, it is preferable to use capacitance sensors or optical sensors in the touch sensor module.

[0442] When an optical touch sensor is used, a photoelectric conversion element (also called a photoelectric conversion device) can be used as a light receiving element (also called a light receiving device). The active layer of the photoelectric conversion element can be made of either an inorganic semiconductor or an organic semiconductor, or both.

[0443] Here, the touch sensor or near-touch sensor can detect the proximity or contact of an object (such as a finger, hand, or pen). The touch sensor can detect an object when the display device and the object are in direct contact with each other. The near-touch sensor can detect an object even if the object does not touch the display device. For example, it is preferable that the display device be configured to detect the object when the distance between the display device and the object is in the range of 0.1 mm to 300 mm, preferably 3 mm to 50 mm. This configuration makes it possible to operate the display device without the object directly touching it, in other words, to operate the display device in a contactless (touchless) manner. This configuration reduces the risk of the display device becoming dirty or scratched, or makes it possible to operate the display device without the object directly touching dirt (e.g., dust, viruses, etc.) attached to the display device.

[0444] Furthermore, the display device of one embodiment of the present invention can have a variable refresh rate. For example, the refresh rate can be adjusted (for example, adjusted within a range of 1 Hz to 240 Hz) depending on the content displayed on the display device, thereby reducing power consumption. Furthermore, the drive frequency of the touch sensor or near-touch sensor may be changed depending on the refresh rate. For example, when the refresh rate of the display device is 120 Hz, the drive frequency of the touch sensor or near-touch sensor can be configured to be higher than 120 Hz (typically 240 Hz). With this configuration, low power consumption can be achieved and the response speed of the touch sensor or near-touch sensor can be increased.

[0445] The electronic device 800A shown in FIG. 45A and the electronic device 800B shown in FIG. 45B each have a pair of display units 820, a housing 821, a communication unit 822, a pair of mounting units 823, a control unit 824, a pair of imaging units 825, and a pair of lenses 832.

[0446] The display device of one embodiment of the present invention can be applied to the electronic device 800A and the electronic device 800B. Therefore, the electronic device 800A and the electronic device 800B can be highly reliable electronic devices capable of displaying images with extremely high resolution. The electronic device 800A and the electronic device 800B can provide a highly immersive experience to the user because they can display images with extremely high resolution.

[0447] Display unit 820 is provided inside housing 821 at a position that can be viewed through lens 832. Also, by displaying different images on the pair of display units 820, it is possible to perform a three-dimensional display using parallax.

[0448] Electronic device 800A and electronic device 800B can each be said to be electronic devices for VR. A user wearing electronic device 800A or electronic device 800B can view an image displayed on display unit 820 through lens 832.

[0449] It is preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the left and right positions of lens 832 and display unit 820 so that they are optimally positioned according to the position of the user's eyes. It is also preferable that electronic device 800A and electronic device 800B each have a mechanism that can adjust the focus by changing the distance between lens 832 and display unit 820.

[0450] The user can wear electronic device 800A or electronic device 800B on the head via wearing unit 823. Note that, for example, in Fig. 45A, the wearing unit 823 is shaped like the temples of glasses (also called joints or temples), but is not limited to this. Wearing unit 823 may be shaped like a helmet or a band, for example, as long as it can be worn by the user.

[0451] The imaging unit 825 has a function of acquiring external information. Data acquired by the imaging unit 825 can be output to the display unit 820. An image sensor can be used for the imaging unit 825. Furthermore, multiple cameras may be provided to support multiple angles of view, such as telephoto and wide angle.

[0452] Although an example having the imaging unit 825 has been shown here, a distance measuring sensor (hereinafter also referred to as a detection unit) capable of measuring the distance to an object may be provided. That is, the imaging unit 825 is one aspect of the detection unit. As the detection unit, for example, an image sensor or a range image sensor such as a LIDAR (Light Detection and Ranging) can be used. By using an image obtained by the camera and an image obtained by the range image sensor, more information can be obtained, enabling more accurate gesture operations.

[0453] Electronic device 800A may have a vibration mechanism that functions as a bone conduction earphone. For example, a configuration having such a vibration mechanism can be applied to one or more of display unit 820, housing 821, and wearing unit 823. This allows a user to enjoy video and audio simply by wearing electronic device 800A, without the need for separate audio equipment such as headphones, earphones, or speakers.

[0454] The electronic device 800A and the electronic device 800B may each have an input terminal to which a cable can be connected for supplying a video signal from a video output device or the like and power for charging a battery provided in the electronic device.

[0455] The electronic device of one embodiment of the present invention may have a function of wirelessly communicating with earphone 750. Earphone 750 includes a communication unit (not shown) and has a wireless communication function. Earphone 750 can receive information (e.g., audio data) from the electronic device through the wireless communication function. For example, electronic device 700A shown in FIG. 44A and electronic device 800A shown in FIG. 45A have a function of transmitting information to earphone 750 through the wireless communication function.

[0456] The electronic device may also have an earphone unit. Electronic device 700B shown in Fig. 44B has earphone unit 727. For example, earphone unit 727 and the control unit may be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 727 and the control unit may be disposed inside housing 721 or wearing unit 723.

[0457] Similarly, electronic device 800B shown in FIG. 45B has earphone unit 827. For example, earphone unit 827 and control unit 824 can be configured to be connected to each other by wire. Part of the wiring connecting earphone unit 827 and control unit 824 may be disposed inside housing 821 or wearing unit 823. Furthermore, earphone unit 827 and wearing unit 823 may have magnets. This allows earphone unit 827 to be fixed to wearing unit 823 by magnetic force, which is preferable as it makes storage easier.

[0458] The electronic device may have an audio output terminal to which earphones or headphones can be connected. The electronic device may also have one or both of an audio input terminal and an audio input mechanism. For example, a sound collection device such as a microphone can be used as the audio input mechanism. By having the audio input mechanism, the electronic device may be endowed with the functionality of a so-called headset.

[0459] As described above, the electronic devices of one embodiment of the present invention are preferably either glasses-type devices (such as the electronic devices 700A and 700B) or goggle-type devices (such as the electronic devices 800A and 800B).

[0460] Furthermore, the electronic device of one embodiment of the present invention can transmit information to the earphone by wire or wirelessly.

[0461] Electronic device 6500 shown in FIG. 46A is a portable information terminal that can be used as a smartphone.

[0462] The electronic device 6500 includes a housing 6501, a display portion 6502, a power button 6503, a button 6504, a speaker 6505, a microphone 6506, a camera 6507, and a light source 6508. The display portion 6502 has a touch panel function.

[0463] The display device of one embodiment of the present invention can be applied to the electronic device 6500. Therefore, the electronic device 6500 can be a highly reliable electronic device that can display images with extremely high definition.

[0464] FIG. 46B is a schematic cross-sectional view including the end of the housing 6501 on the microphone 6506 side.

[0465] A light-transmitting protective member 6510 is provided on the display surface side of the housing 6501, and a display panel 6511, optical members 6512, a touch sensor panel 6513, a printed circuit board 6517, a battery 6518, etc. are arranged in the space surrounded by the housing 6501 and the protective member 6510.

[0466] A display panel 6511, an optical member 6512, and a touch sensor panel 6513 are fixed to the protective member 6510 by adhesive layers (not shown).

[0467] In an area outside the display unit 6502, a part of the display panel 6511 is folded back, and an FPC 6515 is connected to the folded back part. An IC 6516 is mounted on the FPC 6515. The FPC 6515 is connected to a terminal provided on a printed circuit board 6517.

[0468] 47A shows an example of a television device. A television device 7100 has a display unit 7000 built into a housing 7101. Here, the housing 7101 is supported by a stand 7103.

[0469] The display device of one embodiment of the present invention can be applied to the television set 7100. Thus, the television set 7100 can be a highly reliable electronic device capable of displaying images with extremely high definition.

[0470] 47A can be operated using operation switches provided on the housing 7101 and a separate remote control 7111. Alternatively, a touch sensor may be provided in the display unit 7000, and the television 7100 may be operated by touching the display unit 7000 with a finger or the like. The remote control 7111 may have a display unit that displays information output from the remote control 7111. Using operation keys or a touch panel provided on the remote control 7111, the channel and volume can be controlled, and the video displayed on the display unit 7000 can be controlled.

[0471] The television device 7100 is configured to include a receiver, a modem, and the like. The receiver can receive general television broadcasts. In addition, by connecting to a wired or wireless communication network via the modem, it is possible to perform one-way (from sender to receiver) or two-way (between sender and receiver, or between receivers, etc.) information communication.

[0472] 47B shows an example of a laptop personal computer 7200. The laptop personal computer 7200 includes a housing 7211, a keyboard 7212, a pointing device 7213, and an external connection port 7214. The housing 7211 includes a display portion 7000.

[0473] The display device of one embodiment of the present invention can be applied to the laptop personal computer 7200. Thus, the television set 7100 can be a highly reliable electronic device capable of displaying images with extremely high definition.

[0474] 47C and 47D show an example of digital signage.

[0475] 47C includes a housing 7301, a display unit 7000, and a speaker 7303. The digital signage 7300 may further include an LED lamp, operation keys (including a power switch or an operation switch), a connection terminal, various sensors, a microphone, and the like.

[0476] 47D shows a digital signage 7400 attached to a cylindrical pillar 7401. The digital signage 7400 has a display unit 7000 provided along the curved surface of the pillar 7401.

[0477] The display device of one embodiment of the present invention can be applied to the digital signage 7300 and the digital signage 7400. As a result, the digital signage 7300 and the digital signage 7400 can be highly reliable electronic devices capable of displaying images with extremely high definition.

[0478] The larger the display unit 7000, the more information can be provided at one time. Also, the larger the display unit 7000, the more easily it will attract people's attention, which can increase the advertising effectiveness of, for example, advertisements.

[0479] Applying a touch panel to the display unit 7000 is preferable because it not only displays images or videos on the display unit 7000 but also allows the user to intuitively operate it. Furthermore, when used to provide information such as route information or traffic information, intuitive operation can improve usability.

[0480] 47C and 47D, it is preferable that the digital signage 7300 or the digital signage 7400 can be linked via wireless communication with an information terminal 7311 or an information terminal 7411 such as a smartphone carried by a user. For example, advertising information displayed on the display unit 7000 can be displayed on the screen of the information terminal 7311 or the information terminal 7411. Furthermore, the display on the display unit 7000 can be switched by operating the information terminal 7311 or the information terminal 7411.

[0481] Furthermore, the digital signage 7300 or the digital signage 7400 can be made to run a game using the screen of the information terminal 7311 or the information terminal 7411 as an operation means (controller), thereby allowing an unspecified number of users to simultaneously participate in and enjoy the game.

[0482] The electronic device shown in Figures 48A to 48G has a housing 9000, a display unit 9001, a speaker 9003, operation keys 9005 (including a power switch or an operation switch), a connection terminal 9006, a sensor 9007 (including a function to measure force, displacement, position, speed, acceleration, angular velocity, rotation speed, distance, light, liquid, magnetism, temperature, chemical substance, sound, time, hardness, electric field, current, voltage, power, radiation, flow rate, humidity, gradient, vibration, odor or infrared rays), a microphone 9008, etc.

[0483] 48A to 48G have various functions. For example, they may have a function to display various information (still images, videos, text images, etc.) on a display unit, a touch panel function, a function to display a calendar, date, time, etc., a function to control processing using various software (programs), a wireless communication function, a function to read and process programs or data recorded on a recording medium, etc. Note that the functions of the electronic device are not limited to these, and the electronic device may have various other functions. The electronic device may have multiple display units. Furthermore, the electronic device may have a function to include a camera or the like to capture still images or videos and store them on a recording medium (external or built-in to the camera), a function to display the captured images on the display unit, etc.

[0484] The electronic devices shown in FIGS. 48A to 48G will be described in detail below.

[0485] FIG. 48A is a perspective view showing a mobile information terminal 9101. The mobile information terminal 9101 can be used as, for example, a smartphone. The mobile information terminal 9101 may be provided with a speaker 9003, a connection terminal 9006, a sensor 9007, or the like. The mobile information terminal 9101 can display text and image information on multiple surfaces thereof. FIG. 48A shows an example in which three icons 9050 are displayed. Information 9051, indicated by a dashed rectangle, can also be displayed on another surface of the display unit 9001. Examples of the information 9051 include notifications of incoming emails, SNS messages, phone calls, etc., the title of the email or SNS message, the sender's name, the date and time, the remaining battery level, and radio wave intensity. Alternatively, the icon 9050 or the like may be displayed in the position where the information 9051 is displayed.

[0486] The display device of one embodiment of the present invention can be applied to the portable information terminal 9101. As a result, the portable information terminal 9101 can be a highly reliable electronic device capable of displaying images with extremely high resolution.

[0487] 48B is a perspective view showing mobile information terminal 9102. Mobile information terminal 9102 has a function of displaying information on three or more sides of display unit 9001. Here, an example is shown in which information 9052, information 9053, and information 9054 are displayed on different sides. For example, while mobile information terminal 9102 is placed in a breast pocket of clothes, the user can check information 9053 displayed in a position that can be observed from above mobile information terminal 9102. The user can check the display without taking mobile information terminal 9102 out of the pocket and decide, for example, whether to answer a call.

[0488] The display device of one embodiment of the present invention can be applied to the portable information terminal 9102. As a result, the portable information terminal 9102 can be a highly reliable electronic device capable of displaying images with extremely high resolution.

[0489] 48C is a perspective view showing a tablet terminal 9103. The tablet terminal 9103 is capable of executing various applications such as mobile phone calls, e-mail, text browsing and creation, music playback, internet communication, computer games, etc. The tablet terminal 9103 has a display unit 9001, a camera 9002, a microphone 9008, and a speaker 9003 on the front side of a housing 9000, operation keys 9005 as operation buttons on the left side of the housing 9000, and a connection terminal 9006 on the bottom.

[0490] The display device of one embodiment of the present invention can be applied to the tablet terminal 9103. As a result, the tablet terminal 9103 can be a highly reliable electronic device capable of displaying images with extremely high resolution.

[0491] FIG. 48D is a perspective view showing a wristwatch-type mobile information terminal 9200. The mobile information terminal 9200 can be used as, for example, a smart watch (registered trademark). The display surface of the display unit 9001 is curved, and display can be performed along the curved display surface. The mobile information terminal 9200 can also perform hands-free calling by communicating with, for example, a headset capable of wireless communication. The mobile information terminal 9200 can also perform data transmission and reception with another information terminal and charge itself via a connection terminal 9006. Note that charging may be performed by wireless power supply.

[0492] The display device of one embodiment of the present invention can be applied to the portable information terminal 9200. Thus, the portable information terminal 9200 can be a highly reliable electronic device capable of displaying images with extremely high resolution.

[0493] 48E to 48G are perspective views showing a foldable mobile information terminal 9201. FIG. 48E is a perspective view of the mobile information terminal 9201 in an unfolded state, FIG. 48G is a perspective view of the mobile information terminal 9201 in a folded state, and FIG. 48F is a perspective view of a state in the process of changing from one of FIG. 48E and FIG. 48G to the other. The mobile information terminal 9201 is highly portable when folded, and has a seamless, wide display area when unfolded, providing excellent viewability of the display. The display unit 9001 of the mobile information terminal 9201 is supported by three housings 9000 connected by hinges 9055. For example, the display unit 9001 can be bent with a curvature radius of 0.1 mm or more and 150 mm or less.

[0494] The display device of one embodiment of the present invention can be applied to the portable information terminal 9201. Thus, the portable information terminal 9201 can be a highly reliable electronic device capable of displaying images with extremely high resolution.

[0495] At least a part of the configuration examples exemplified in this embodiment and the corresponding drawings can be implemented by appropriately combining with other configuration examples or drawings.

[0496] This embodiment mode can be implemented by appropriately combining at least a part thereof with other embodiment modes or examples described in this specification. [Example]

[0497] Example 1 In this example, the results of a simulation performed on a sequential circuit included in a semiconductor device of one embodiment of the present invention will be described.

[0498] In this example, simulations were performed on a sequential circuit 50e shown in Fig. 28 and a sequential circuit 150e shown in Fig. 33. In the simulation of the sequential circuit 50e, it was assumed that the sequential circuit was driven by the methods shown in Fig. 9B and Fig. 23B. In addition, in the simulation of the sequential circuit 150e, it was assumed that the sequential circuit was driven by the methods shown in Fig. 21B and Fig. 24B.

[0499] 49A to 49C are graphs showing simulation results of the change in potential over time in the fifth-stage sequential circuit 50e, i.e., the sequential circuit 50e_5. Also, FIGS. 50A to 50C are graphs showing simulation results of the change in potential over time in the fifth-stage sequential circuit 150e, i.e., the sequential circuit 150e_5. Specifically, FIGS. 49A and 50A show the change in potential of the wiring Wb over time, FIGS. 49B and 50B show the change in potential of the node N over time, and FIGS. 49C and 50C show the change in potential of the signal OUT over time.

[0500] 49A, 49C, 50A, and 50C, it was confirmed by simulation that the potential of the wiring Wb periodically becomes low before and after the signal OUT becomes high. Furthermore, it was confirmed by simulation that the potentials of the wiring Wb, the node N, and the signal OUT become desired potentials.

[0501] From the above, it was confirmed that the sequential circuit 50e and the sequential circuit 150e can perform the desired operations in the simulation.

[0502] At least a part of this embodiment can be implemented in appropriate combination with the embodiment modes described in this specification. [Explanation of symbols]

[0503] 10: sequential circuit, 10a: sequential circuit, 10b: sequential circuit, 10c: sequential circuit, 10d: sequential circuit, 10e: sequential circuit, 11a: circuit, 11b: circuit, 11c: circuit, 11d: circuit, 11e: circuit, 12: circuit, 21: transistor, 22: transistor, 23: transistor, 24: transistor, 25: transistor, 26: transistor, 27: capacitor, 28: transistor, 31: transistor, 32: transistor, 33: transistor, 34: transistor, 40: shift register circuit, 40a: shift register circuit, 50: sequential circuit, 50a: Introduction,Circuit,50b: Sequential circuit,50c: Sequential circuit,50d: Sequential circuit,50e: Sequential circuit,51a: Circuit,51b: Circuit,51c: Circuit,51d: Circuit,51e: Circuit,61: Transistor,62: Transistor,65: Transistor,66: Transistor,67: Capacitor,110: Sequential circuit,110a: Sequential circuit,110b: Sequential circuit,110c: Sequential circuit,110d: Sequential circuit,110e: Sequential circuit,111a: Circuit,111b: Circuit,111c: Circuit,111d: Circuit,111e: Circuit,140: Shift register circuit,140a: Shift register circuit,1 50: sequential circuit, 150a: sequential circuit, 150b: sequential circuit, 150c: sequential circuit, 150d: sequential circuit, 150e: sequential circuit, 151a: circuit, 151b: circuit, 151c: circuit, 151d: circuit, 151e: circuit, 171: transistor, 172: transistor, 173: transistor, 174: transistor, 175: transistor, 176: transistor, 185: transistor, 186: transistor, 201: transistor, 205: transistor, 209: transistor, 210: transistor, 211: insulating layer, 213: insulating layer, 214: Insulating layer, 215: insulating layer, 218: insulating layer, 221: conductive layer, 222a: conductive layer, 222b: conductive layer, 223: conductive layer, 225: insulating layer, 228: region, 231: semiconductor layer, 231i: channel formation region, 231n: low resistance region, 240: capacitor, 241: conductive layer, 242: connection layer, 243: insulating layer, 245: conductive layer, 251: conductive layer, 252: conductive layer, 254: insulating layer, 255a: insulating layer, 255b: insulating layer, 256: plug, 261: insulating layer, 262: insulating layer, 263: insulating layer, 264: insulating layer, 264B: colored layer, 264G: colored layer, 264R: colored layer,265: insulating layer, 271: plug, 274: plug, 274a: conductive layer, 274b: conductive layer, 280: display module, 282: circuit section, 283: pixel circuit section, 283a: pixel circuit, 284: pixel section, 284a: pixel, 286: wiring section, 290: FPC, 291: substrate, 292: substrate, 301: substrate, 310: transistor, 311: conductive layer, 312: low resistance region, 313: insulating layer, 314: insulating layer, 315: element isolation layer, 320: transistor, 321: semiconductor layer, 323: insulating layer, 324: conductive layer, 325: conductive layer, 326: insulating layer, 327: conductive layer , 328: insulating layer, 329: insulating layer, 331: substrate, 332: insulating layer, 411: light-emitting layer, 412: light-emitting layer, 413: light-emitting layer, 420: layer, 430: layer, 451: substrate, 458: protective layer, 459: region, 471: protective layer, 472: insulating layer, 500: display device, 500A: display device, 500B: display device, 500C: display device, 500D: display device, 500E: display device, 501: pixel circuit, 502: display unit, 504: drive circuit unit, 504a: scanning line drive circuit, 504b: signal line drive circuit, 506: protection circuit, 507: terminal unit, 552: transistor, 554: Transistor, 562: Capacitor, 572: Light-emitting element, 572B: Light-emitting element, 572G: Light-emitting element, 572R: Light-emitting element, 572W: Light-emitting element, 617: Light-shielding layer, 620: Substrate, 622: Resin layer, 642: Adhesive layer, 651: Substrate, 652: Substrate, 653: Insulating layer, 664: Circuit, 665: Wiring, 666: Conductive layer, 672: FPC, 673: IC, 700A: Electronic device, 700B: Electronic device, 721: Housing, 723: Wearing part, 727: Earphone part, 750: Earphone, 751: Display panel, 753: Optical member, 756: Display area, 757: Frame, 758 : nose pad, 772: conductive layer, 776: insulating layer, 777: microlens array, 786: EL layer, 786a: EL layer, 786b: EL layer, 786B: EL layer, 786G: EL layer, 786R: EL layer, 786W: EL layer, 788: conductive layer, 800A: electronic device, 800B: electronic device, 820: display unit, 821: housing, 822: communication unit, 823: wearing unit, 824: control unit, 825: imaging unit, 827: earphone unit, 832: lens, 6500: electronic device, 6501: housing, 6502: display unit, 6503: power button, 6504: button, 6505: speaker,6506: microphone, 6507: camera, 6508: light source, 6510: protective member, 6511: display panel, 6512: optical member, 6513: touch sensor panel, 6515: FPC, 6516: IC, 6517: printed circuit board, 6518: battery, 7000: display unit, 7100: television device, 7101: housing, 7103: stand, 7111: remote control device, 7200: notebook personal computer, 7211: housing, 7212: keyboard, 7213: pointing device, 7214: external connection port, 7300: digital signage, 7 301: Housing, 7303: Speaker, 7311: Information terminal, 7400: Digital signage, 7401: Pillar, 7411: Information terminal, 9000: Housing, 9001: Display, 9002: Camera, 9003: Speaker, 9005: Operation keys, 9006: Connection terminal, 9007: Sensor, 9008: Microphone, 9050: Icon, 9051: Information, 9052: Information, 9053: Information, 9054: Information, 9055: Hinge, 9101: Portable information terminal, 9102: Portable information terminal, 9103: Tablet terminal, 9200: Portable information terminal, 9201: Portable information terminal,

Claims

1. A semiconductor device comprising first to ninth transistors, one of the source and the drain of the first transistor is electrically connected to an output signal wiring; the other of the source and the drain of the first transistor is electrically connected to a first clock signal line; one of the source and the drain of the second transistor is electrically connected to the output signal wiring; the other of the source and the drain of the second transistor is electrically connected to a first power supply line; one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor; a gate of the third transistor electrically connected to a second clock signal line; one of the source and the drain of the fourth transistor is electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the fourth transistor is electrically connected to a second power supply line; a gate of the fourth transistor electrically connected to a first signal line; one of the source and the drain of the fifth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the fifth transistor is electrically connected to the first power supply line; a gate of the fifth transistor electrically connected to a third clock signal line; one of the source and the drain of the sixth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the sixth transistor is electrically connected to the second power supply line; a gate of the sixth transistor is electrically connected to a fourth clock signal line; one of the source and the drain of the seventh transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the seventh transistor is electrically connected to the first power supply line; a gate of the seventh transistor electrically connected to the first signal line; one of the source and the drain of the eighth transistor is electrically connected to the gate of the second transistor; the other of the source and the drain of the eighth transistor is electrically connected to the second power supply line; a gate of the eighth transistor electrically connected to a second signal line; one of the source and the drain of the ninth transistor is electrically connected to the other of the source and the drain of the third transistor; the other of the source and the drain of the ninth transistor is electrically connected to the first power supply line; The semiconductor device, wherein the gate of the ninth transistor is electrically connected to the gate of the second transistor.

2. A semiconductor device comprising: the semiconductor device according to claim 1; a first light-emitting element; a second light-emitting element; and an insulating layer; the first light-emitting element has a first lower electrode, a first light-emitting layer on the first lower electrode, and a first upper electrode on the first light-emitting layer; the second light-emitting element has a second lower electrode, a second light-emitting layer on the second lower electrode, and a second upper electrode on the second light-emitting layer; The insulating layer is provided so as to cover an end portion of the first upper electrode and an end portion of the second upper electrode.

3. The display device according to claim 2; An electronic device having at least one of a battery, a camera, a speaker, and a microphone.

Images