Gaming machine

Abstract

To provide a game machine further improved in a performance control operation.SOLUTION: A display device DS1 has a display driving circuit MONI which drives a group of display elements constituting a display screen LCD, and a lighting circuit BL which lights the display screen LCD. Image control means 51 reserves, as a frame buffer FBa, a storage area in a RAM in which a drawing circuit 76 produces image data, and then starts a lighting operation of the lighting circuit BL.SELECTED DRAWING: Figure 21

Description

[Technical Field]

[0001] The present invention relates to a gaming machine that performs a lottery process resulting from gameplay and executes an image presentation corresponding to the lottery result, and more particularly to a gaming machine that can stably execute a powerful image presentation. [Background technology]

[0002] Pachinko machines and other ball-based gaming machines are composed of a symbol start port on the game board, a symbol display unit that displays a series of symbol variation patterns using multiple display symbols, and a large prize opening with an opening / closing plate. When a detection switch in the symbol start port detects the passage of a game ball, a prize is awarded, and after the game ball is paid out as a prize, the displayed symbols in the symbol display unit change for a predetermined time. After that, when the symbols stop in a predetermined pattern such as 7-7-7, a jackpot is awarded, and the large prize opening is repeatedly opened, creating a game state that is advantageous to the player.

[0003] Whether or not this type of game state occurs is determined by a jackpot lottery that is executed when a game ball enters the symbol starting slot, and the symbol change operation described above is based on the result of this lottery. For example, if the lottery result is a winning state, a performance operation called a reach action is performed for about 20 seconds, and then the special symbols are aligned. On the other hand, even if the result is a losing state, a similar reach action may be performed, in which case the player will intently watch the progress of the performance operation while strongly hoping that they will enter the jackpot state. Then, when the symbol change operation ends and the predetermined symbols are aligned on the stop line, the player is guaranteed that they are in the jackpot state.

[0004] Such pattern changes are typically performed in liquid crystal displays (LCDs). An LCD generally consists of a liquid crystal display unit (MONI) that displays the three primary colors RGB, and a backlight unit (BL) on the back of the LCD display unit where LEDs emit light. Generally, the LCD display unit (MONI) is composed of pixels arranged in a horizontal H dot x vertical V dot pattern, and each H x V dot pixel is composed of basic pixels of the three RGB colors. When the backlight unit (BL) is lit, the color of each basic pixel is activated.

[0005] The driving of each pixel in the liquid crystal display is performed in synchronization with the device's operating clock CK (=dot clock DCK). The driving of the H dots corresponding to one horizontal line is repeated in synchronization with the horizontal synchronization signal HS, and once the driving of the V line is complete, the system returns to driving the pixels of the first line in synchronization with the vertical synchronization signal VS (see Figure 42). Therefore, the liquid crystal display needs to be supplied with the image signal corresponding to the resolution H × V dots from an external device, along with the horizontal synchronization signal HS, the vertical synchronization signal VS, and the dot clock DCK.

[0006] Here, in order to smoothly perform the display update operation (frame update) of the liquid crystal display, certain conditions are required for the pulse width of each synchronization signal HS, Vs, and the relationship between each synchronization signal HS, Vs and the transmission timing of the image signal. For example, Figure 42(g) illustrates an example of the drive timing conditions required for a 640 x 408 dot VGA (Video Graphics Array).

[0007] Under the illustrated driving conditions, first, the pulse width PWh of the horizontal synchronization signal HS is 96 times the operating clock CK, and the front porch FPh and back port BPh required before and after the horizontal synchronization signal PWh are specified to be 16 times and 48 times the operating clock CK, respectively.

[0008] On the one hand, the pulse width PWv of the vertical synchronization signal VS is for two lines, and the front porch FPv and the back porch BPv required before and after the vertical synchronization signal VS are defined as 19 lines and 33 lines, respectively.

[0009] Therefore, in this liquid crystal display unit, the operation cycle of one line of the driving operation is counted by the operation clock CK and is 16 + 96 + 48 + 640 ( = 800) in number, and by repeating this for 10 + 2 + 33 + 480 lines ( = 525) in the vertical direction, the display for one frame of the display screen is updated.

[0010] The above operation cycle is counted by the operation clock CK and is 800 × 525 in number. For example, when the frequency of the operation clock is 25 MHz, the time required for updating one frame is 800 × 525 / (25 × 10 6 ) = 16.8 mS, which is an operation cycle of about 1 / 60 second.

[0011] And the external control device that controls the liquid crystal display unit supplies an image signal corresponding to the number of pixels of the display screen to the liquid crystal display unit repeatedly, together with the horizontal synchronization signal HS that satisfies the above horizontal conditions (PWh, FPh, BPh) and the horizontal synchronization signal HS that satisfies the above vertical conditions (PWvh, FPvh, BPvh).

Prior Art Documents

Patent Documents

[0012]

Patent Document 1

Patent Document 2

Patent Document 3

Patent Document 4

Summary of the Invention

Problems to be Solved by the Invention

[0013] Incidentally, in this type of gaming machine, there is a desire to make various effects more complex and abundant, and there is a particularly high demand for image effects using liquid crystal displays. Therefore, the applicant has made various proposals (References 1 to 4), but further sophistication of image effects and further improvement of various effect control operations, mainly image effect control, are desired. Furthermore, improvements to the driving operation of the liquid crystal display are desirable to reduce the control burden of image rendering control. In addition, measures must be taken to ensure the synchronized operation of the liquid crystal display unit (MONI) and the backlight unit (BL) so that inappropriate displays do not occur under any circumstances.

[0014] This invention has been made in view of the above-mentioned problems, and aims to provide a gaming machine in which various performance control operations, mainly image performance control, have been further improved. [Means for solving the problem]

[0015] To achieve the above objective, the gaming machine according to the present invention includes a CPU circuit having a CPU that executes program processing, a DMAC (Direct Memory Access Controller) circuit that operates under the control of the CPU, and an operation control register in which setting values ​​that define the operation of the DMAC circuit are set, and a VDP register And a display circuit that outputs an image signal to a display device, The system is configured to have a performance control means that includes a built-in VDP circuit (Video Display Processor), and the CPU circuit sets the necessary setting values ​​in the VDP register, The aforementionedA gaming machine in which a display list specifying the display content of the display device is issued to the VDP circuit, thereby executing performance operations including image effects realized on the display screen of the display device, wherein the memory space accessible by the CPU includes an address space located outside the CPU circuit and divided into multiple sections, each capable of defining a data bus width, and the VDP register, the address space of the multiple sections being broadly divided into a non-volatile space composed of non-volatile memory and a volatile space composed of volatile memory, and the information to be transferred, which is at least a part of the program and data stored in a predetermined address space included in the non-volatile space, is entered into the operation control register after the CPU is reset. The DMAC circuit is configured to function based on the setting of a value, thereby transferring to the address space included in the volatile space. The display device is configured to have a display drive circuit (MONI) that drives a group of display elements constituting the display screen based on image data received from the performance control means, and an illumination circuit (BL) that illuminates the display screen. A power supply control means (SPY) arranged between the display device and the performance control means controls the illumination circuit (BL) to an operable state based on a first control signal (STBY) received from the performance control means, while simultaneously starting the illumination operation of the illumination circuit (BL) based on a second control signal (PWM) received from the performance control means. The VDP register includes a first-type register in which necessary operating parameters are set to optimize the access operation to the CGROM that stores the data necessary for the image presentation, and a second-type register indicating that the initialization operation of the display circuit has been completed. The first and second-type registers are configured to be set or referenced after the CPU reset, before the start of a steady-state process that is repeated at predetermined intervals and after the image presentation can be executed. Yes, they are. [Effects of the Invention]

[0016] According to the present invention described above, further advancements in image presentation and further improvements in various performance control operations, primarily image presentation control, can be achieved. In addition, the lighting operation of the lighting circuit (BL) is started at an appropriate time, which improves image control operation, such as preventing abnormal displays. [Brief explanation of the drawing]

[0017] [Figure 1] This is a perspective view showing the pachinko machine of this embodiment. [Figure 2] Figure 1 is a front view showing the game area of ​​the gaming machine. [Figure 3] This is a block diagram showing the overall circuit configuration of the gaming machine in Figure 1. [Figure 4] This is a diagram illustrating the specifications of a display device. [Figure 5] This is a block diagram illustrating the internal configuration of the display device. [Figure 6] This is a diagram illustrating the circuit configuration and operation of the power supply control circuit. [Figure 7] Figure 1 is a block diagram showing a slightly more detailed circuit configuration of the performance control unit for the gaming machine. [Figure 8] This is a diagram illustrating the composite chip that constitutes the performance control unit. [Figure 9] Figure 4 is a block diagram showing the internal configuration of the CPU circuit. [Figure 10] This diagram illustrates the memory map of the built-in CPU (performance control CPU) within the CPU circuit. [Figure 11] This diagram illustrates the various transfer operation modes (a) to (b) and transfer operation procedures (c) to (e) for DMAC. [Figure 12] This diagram illustrates the index space, index table, virtual drawing space, and drawing area. [Figure 13] This is a block diagram showing the internal configuration of the data transfer circuit, along with related circuit configurations. [Figure 14] This is a block diagram showing the internal configuration of the display circuit, along with related circuit configurations. [Figure 15] This diagram illustrates the data validity signals ENAB output from the VDP circuit. [Figure 16] This is a flowchart explaining the power reset operation after a CPU reset. [Figure 17] This is a flowchart illustrating the memory section initialization process, which is part of Figure 16. [Figure 18] This flowchart explains the main introductory process and interrupt processing, which are part of Figure 16. [Figure 19] This flowchart explains the CGROM initialization process, which is part of the main installation process. [Figure 20]This flowchart illustrates the operation of other embodiments that use interrupt handling. [Figure 21] This flowchart, following Figure 18, explains the main introductory process and the steps leading up to the steady-state process. [Figure 22] This is a flowchart explaining the steady-state process that follows Figure 21. [Figure 23] This is a diagram illustrating the configuration of the display list. [Figure 24] This is a flowchart showing the DL issuance process for issuing a display list DL. [Figure 25] This flowchart explains the operation when DMAC is involved in the operation shown in Figure 24. [Figure 26] This is a flowchart explaining the actions that follow the process shown in Figure 25. [Figure 27] This flowchart explains the steady-state process when using a preloader. [Figure 28] This is a flowchart that explains a part of Figure 27. [Figure 29] This is a flowchart explaining another part of Figure 27. [Figure 30] This is a time chart showing the operation of each part of the VDP in an embodiment that does not use a preloader. [Figure 31] This is a time chart showing the operation of each part of the VDP in an example using a preloader. [Figure 32] This is a diagram showing the overall circuit configuration for another embodiment. [Figure 33] This is a block diagram showing a portion of Figure 32 in slightly more detail. [Figure 34] This is a time chart illustrating the operation of another embodiment. [Figure 35] This is a drawing illustrating yet another embodiment. [Figure 36] This diagram illustrates an example in which the set values ​​are repeatedly set. [Figure 37] This is a diagram illustrating the circuit configuration of an embodiment that uses a built-in audio circuit. [Figure 38] This is a flowchart explaining the initial setup operation of the audio circuit. [Figure 39] This diagram illustrates another embodiment of the power reset operation after a CPU reset. [Figure 40] This is a time chart showing an example of memory read and memory write operations. [Figure 41] This is a drawing illustrating another embodiment. [Figure 42] This is a diagram illustrating the driving method of a general display device. [Figure 43] This is a diagram illustrating the display list. [Figure 44] This is a diagram illustrating the zoom preview. [Figure 45] This diagram illustrates the CPU processing required to achieve rotational motion. [Figure 46] This diagram shows the basis for the calculation formula. [Figure 47] This is a time chart showing the deformation of the backlight and LCD display when the power is turned on. [Figure 48] This is a time chart showing the different transformation movements of the backlight and LCD display when the power is turned on. [Modes for carrying out the invention]

[0018] The present invention will be described in detail below based on an embodiment. Figure 1 is a perspective view showing a pachinko machine GM of this embodiment. This pachinko machine GM consists of a rectangular wooden outer frame 1 that is detachably attached to an island structure, and an inner frame 3 that is pivotally attached to the outer frame 1 via a hinge 2 that is fixed to the outer frame 1 so as to be openable and closable. A game board 5 is detachably attached to this inner frame 3 from the front side, not the back side, and a glass door 6 and a front panel 7 are pivotally attached to the front side so as to be openable and closable. In this specification, the glass door 6 and the front panel 7 are collectively referred to as the front door member. The inner frame 3 in the state in which the front door member (glass door 6 and front panel 7) is pivotally attached is sometimes referred to as the game frame.

[0019] Around the outer perimeter of the glass door 6, decorative lights such as LED lamps are arranged in a roughly C-shape. Meanwhile, a total of three speakers are positioned at the upper left and right positions and at the bottom of the glass door 6. The two speakers positioned at the top are configured to output left and right channel (R and L) audio, respectively, while the lower speaker is configured to output bass.

[0020] The front panel 7 is fitted with an upper tray 8 for storing game balls to be launched, and the lower part of the inner frame 3 is provided with a lower tray 9 for storing game balls that overflow from the upper tray 8 or are removed, and a launching handle 10. The launching handle 10 is linked to a launching motor, and game balls are launched by a striking hammer that operates according to the rotation angle of the launching handle 10.

[0021] A chance button 11 is provided on the outer surface of the upper tray 8. This chance button 11 is positioned so that it can be operated with the player's left hand, allowing the player to operate the chance button 11 without taking their right hand off the launch handle 10. This chance button 11 is normally inactive, but when the game state becomes a button chance state, its built-in lamp lights up and it becomes operable. The button chance state is a game state that is set up as needed.

[0022] Furthermore, a rotary switch-type volume switch VLSW is located below the chance button 11, allowing the player to adjust the speaker volume in eight steps, from silent (=0) to maximum (=7). The speaker volume is initially set by a setting switch (not shown) that can only be operated by an attendant, and the initial volume is maintained unless the player operates the volume switch VLSW. In addition, an abnormal alert sound, which notifies the player of an abnormal situation, is emitted at the maximum volume regardless of the initial volume set by the attendant or the player's setting.

[0023] On the right part of the upper tray 8, an operation panel 12 for the ball lending operation of the card-type ball lending machine is provided, which includes a frequency display unit that displays the remaining card balance as a three-digit number, a ball lending switch for instructing the lending of a predetermined amount of game balls, and a return switch for instructing the return of the card at the end of the game.

[0024] As shown in FIG. 2, on the surface of the game board 5, a guide rail 13 composed of a metal outer rail and an inner rail is provided in a circular shape, and a central opening HO is provided at approximately the center thereof. And below the central opening HO, a movable effect body (not shown) is stored in a concealed state. During the movable preview effect, the movable effect body rises and becomes exposed, thereby realizing a preview effect with a predetermined reliability. Here, the preview effect is an effect that notifies the player uncertainly that a jackpot state advantageous to the player will be brought about, and the reliability of the preview effect means the probability that the jackpot state will be brought about.

[0025] In the central opening HO, a main display device DS1 composed of a large-sized (for example, 1280 horizontal pixels × 1024 vertical pixels) liquid crystal color display is arranged. On the right side of the main display device DS1, a movable sub-display device DS2 composed of a small-sized (for example, 480 horizontal pixels × 800 vertical pixels) liquid crystal color display is arranged. The main display device DS1 is composed of a main liquid crystal display unit MONI and an LED backlight unit BL, and is a device that variably displays specific symbols related to the jackpot state and animates the display of background images and various characters. This display device DS1 has a special symbol display section Da to Dc at the center and a normal symbol display section 19 at the upper right. And in the special symbol display section Da to Dc, a reach effect that expects the occurrence of the jackpot state may be executed, and appropriate preview effects and the like are executed around the special symbol display section Da to Dc and its vicinity.

[0026] Normally, the sub-display device DS2 displays image information in a stationary state with its display screen tilted at an angle easy for the player to view. However, during a predetermined preview effect, while changing the tilt angle to an angle easy for the player to view, it moves to the left side shown in the figure and displays a predetermined preview image.

[0027] In other words, the sub-display device DS2 in this embodiment functions not merely as a display device, but also as a movable display unit that executes pre-announcement effects. Here, the pre-announcement effects by the sub-display device DS2 are set to have a high level of reliability, so players will pay close attention to the movement of the sub-display device DS2 with great anticipation. The sub-display device DS2 is also composed of a sub-LCD display unit MONI and an LED backlight unit BL.

[0028] Incidentally, the game area in which the game balls fall and move is equipped with a first symbol start opening 15a, a second symbol start opening 15b, a first major prize opening 16a, a second major prize opening 16b, a regular prize opening 17, and a gate 18. Each of these prize openings 15 to 18 has a detection switch inside that can detect the passage of the game balls.

[0029] Above the first symbol start opening 15a, there is a performance stage 14 configured to allow game balls that enter from the entry opening IN to move in a seesaw-like or roulette-like manner before entering the first symbol start opening 15. When a game ball enters the first symbol start opening 15, the special symbol display sections Da to Dc begin to change.

[0030] The second symbol start opening 15b is configured to be opened and closed by an electrically operated tulip with a pair of opening and closing claws on the left and right. When the stopping symbol after the change in the normal symbol display unit 19 displays a winning symbol, the opening and closing claws are opened for a predetermined time or until a predetermined number of game balls are detected.

[0031] The regular symbol display unit 19 displays regular symbols. When a game ball that has passed through the gate 18 is detected, the regular symbols change for a predetermined time, and then stop displaying a stopping symbol determined by a random value for the lottery extracted at the time the game ball passes through the gate 18.

[0032] The first large prize opening 16a is configured with a sliding plate that moves back and forth in the front-rear direction, and the second large prize opening 16b is configured with an opening / closing plate whose lower end is pivotally supported and opens forward. The operation of the first large prize opening 16a and the second large prize opening 16b is not particularly limited, but in this embodiment, the first large prize opening 16a corresponds to the first symbol start opening 15a, and the second large prize opening 16b corresponds to the first symbol start opening 15b.

[0033] In other words, when a game ball enters the first symbol starting opening 15a, the special symbol display section Da to Dc starts moving, and then when the predetermined jackpot symbols are aligned in the special symbol display section Da to Dc, the special game for the first jackpot begins, and the sliding disc of the first jackpot opening 16a opens forward, making it easier for game balls to enter.

[0034] On the other hand, as a result of the fluctuation operation initiated by a game ball entering the second symbol starting opening 15b, when the predetermined jackpot symbols align in the special symbol display section Da~Dc, a special game, which is the second jackpot, begins, and the opening and closing plate of the second jackpot entry opening 16b is opened, making it easier for game balls to enter. The game value of the special game (jackpot state) varies depending on the aligning jackpot symbols, but which game value is assigned is predetermined based on the lottery result corresponding to the timing of the game ball's entry.

[0035] In a typical jackpot state, the opening and closing plate of the large prize winning slot 16 opens, and then closes after a predetermined time has elapsed or a predetermined number of game balls (for example, 10) have entered. This operation can continue for up to, for example, 15 times, and is controlled to be advantageous to the player. Furthermore, if the stopping symbols after the special symbol display section Da~Dc changes are specific symbols among the special symbols, the game after the special game ends will be in a high-probability state (probability change state), which is a special bonus.

[0036] Figure 3(a) is a block diagram showing the overall circuit configuration of the pachinko machine GM that realizes each of the operations described above. Figure 3(b) is a circuit diagram showing the circuit configuration of the power supply monitor unit MNI located on the payout control board 25, and Figure 3(c) is a diagram illustrating the specifications of the main display device DS1 used in this embodiment.

[0037] First, the specifications of the main display device DS1 used in this embodiment will be explained based on Figure 3(c). As previously explained, this display device DS1 is a liquid crystal color display with 1280 pixels horizontally and 1024 pixels vertically, but it is configured so that odd-numbered pixels (ODD) and even-numbered pixels (EVEN) adjacent to each other in the left-right direction are received by the receiving unit RV (RVa + RVb) through separate LVDS (Low Voltage Differential Signaling) transmission lines. In this embodiment, in accordance with this dual-link specification, the ODD signal is transmitted via the first transmission line LVDS1 and the EVEN signal is transmitted via the second transmission line LVDS2 (lower right of Figure 3(a)).

[0038] Furthermore, in this display device DS1, the operating clock CK (see Figure 42) that defines the internal operation of the display device DS1 is specified to have a frequency in the range of 40MHz to 70MHz (typical value = 54MHz). This operating clock CK corresponds to the LVDS clock CLK described later, but for the sake of explanation, the frequency of the operating clock CK will be assumed to be the typical value of 54MHz below. We will also describe a configuration that matches the update time FR (Frame Rate) required to update one frame of image to approximately 1 / 60th of a second with a 54MHz operating clock CK.

[0039] The display device DS1 is configured to process two adjacent pixels in the left-right direction of the display screen simultaneously using a single operating clock CK, based on the ODD signal received from the first transmission line LVDS1 and the EVEN signal received from the second transmission line LVDS2. As a result, the pixel data of 1280 pixels in one horizontal line is updated in an operating time of 640 / 54MHz = 11.85μS, and this operation is repeated for 1024 lines, updating the image display of 1280 × 1024 pixels for one frame. The image is updated line by line in a non-interlaced manner, such as from the first line to the second line, ..., to the 1024th line.

[0040] However, as shown in Figure 3(c), the specifications of the display device DS1 stipulate that a typical waiting time (blank period) of 204 clock cycles be provided horizontally, and a typical waiting time (blank period) of 42 lines be provided vertically. Therefore, the actual screen update cycle FR considering these blank periods is (204 + 640) × (42 + 1024) / 54 MHz ≈ 16.66 mS, calculated based on the typical values ​​mentioned above, so the frame rate FR is approximately 1 / 60 Hz.

[0041] Note that the horizontal standby time WTh and the vertical standby time WTv each have specified tolerance ranges relative to their typical values, and in practice, values ​​different from the typical values ​​mentioned above can be selected. However, in order to achieve a frame rate FR = 1 / 60 seconds, it is necessary to accurately set the horizontal / vertical standby times WTh / WTv so that (WTh + 640) × (WTv + 1024) / 54MHz = 1 / 60 seconds.

[0042] On the other hand, while the DS1 display device does not require the reception of the horizontal synchronization signal HS and the vertical synchronization signal VS, it does require the transmission of a data valid signal ENAB at an H level when transmitting the ODD signal and the EVEN signal. In other words, when a significant signal (ODD / EVEN signal) is being transmitted to the transmission paths LVDS1 and LVDS2, the data valid signal ENAB must be at an active level (H).

[0043] Therefore, in this embodiment, based on the specifications of the main display device DS1 described above, the performance control board 23 and the main display device DS1 are connected via LVDS using a dual-link transmission path of an LVDS clock CLK with a frequency of 54 MHz (= 1 / 2 of the dot clock DCK) (Figures 5 and 14(a)). In addition, the VDP circuit 52 in this embodiment is provided with a horizontal blanking period WTh and a vertical blanking period WTv that satisfy the specifications of the main display device DS1, and when image data (ODD / EVEN signals) is output, the data validity signal ENAB is set to an active level (H level).

[0044] In other words, as shown in Figure 4(b), the data valid signal ENAB is configured such that only the horizontal display period THd of the horizontal synchronization period TH is at an H level. Therefore, the data valid signal ENAB is always at an L level except for the vertical display period TVd of the vertical synchronization period TV. Note that the horizontal blank period WTh and the vertical blank period WTv use values ​​different from their typical values ​​(WTh=204 / WTv=42), but the specific design values ​​will be described later based on Figure 15.

[0045] In any case, the data valid signal ENAB is repeatedly transmitted as a discrete DE signal via the differential signal lines RA2 / RB2 during each operating cycle of the LVDS clock CLK. The data valid signal ENAB shown in Figures 4(b) and 4(c) is a demodulated DE signal, which is discrete data transmitted via LVDS, and is a continuous sequence of discrete DE signals on the time axis. In addition, the vertical synchronization signal VS and the horizontal synchronization signal HS are also repeatedly transmitted via the differential signal lines RA2 / RB following the DE signal (data valid signal ENAB), but the main display device DS1 used in this embodiment does not utilize these synchronization signals VS and HS.

[0046] However, the display device DS1 does not prohibit the transmission of the horizontal synchronization signal HS or the vertical synchronization signal VS. However, the internal operations specified by these synchronization signals are not executed. In other words, the horizontal line break timing of the display line is determined to be the optimal timing for the internal circuitry of the display device DS1, based on the falling edge timing of the data valid signal ENAB and the number of operation clocks CK (corresponding to the LVDS clock CLK) after the rising edge timing of the data valid signal ENAB (640 in the embodiment = 1280 / 2), regardless of the received horizontal synchronization signal HS (downward arrow in Figure 4(b)).

[0047] This also applies to the vertical line break timing after displaying one frame of image. This timing is determined by the optimal timing for the internal circuitry of the display device DS1 based on the number of consecutive data valid signals ENAB with a predetermined pulse width (1024 in this embodiment), and is not affected by the received vertical synchronization signal VS. Thus, in this embodiment, there is no need to transmit the horizontal synchronization signal HS or the vertical synchronization signal VS to the display device DS1. Therefore, there is no need to optimally set the pulse widths PWh / PWv of the synchronization signals HS and VS, or the front port FPh / FPv and back port BPh / BPv, and the control burden on the performance control unit 23 and the VDP circuit 52 is greatly reduced.

[0048] Furthermore, the DS1 display device operates internally by executing horizontal and vertical line breaks at optimal timings based on its own internal configuration, thus eliminating the risk of unnatural display behavior. Incidentally, in the case of display devices that operate based on externally received horizontal synchronization signals HS and vertical synchronization signals VS, if the pulse width of the synchronization signals HS and VS, or the front porch and back porch periods before and after the synchronization signals HS and VS, are inappropriate, normal display operation may be impaired.

[0049] By the way, in Figure 4(a), the first differential signal LVDS1, which uses differential signal lines RA0~RA3 and RACLK, transmits the odd-numbered pixels (A-side ODD signal), and the second differential signal LVDS2, which uses differential signal lines RB0~RB3 and RBCLK, transmits the even-numbered pixels (B-side EVEN signal). In this embodiment, by transmitting two types of ODD and EVEN signals over a dual-link transmission line, the frequency of the dot clock DCK can be reduced by half, resulting in improved noise immunity and increased transmission distance.

[0050] On the other hand, the main display device DS1 has a built-in conversion receiver RV for the ODD signal and EVEN signal transmitted via the dual-link transmission line. It reconstructs the RGB signal from the two LVDS signals (ODD signal and EVEN signal) and displays one frame (1280 x 1024 dots) of image. As explained earlier, each RGB signal is composed of 8 bits, so the main display device DS1 has a gradation of 2 8 ×2 8 ×2 8 A full-color image will be displayed.

[0051] Figure 5 is a block diagram illustrating the internal configuration of the liquid crystal display unit MONI, along with the related parts of the VDP circuit 52, for the display device DS1, which consists of a main liquid crystal display unit MONI and an LED backlight unit BL. As shown in the figure, the ODD signal is transmitted to the LVDS-to-parallel converter RVa via the first LVDS line (A side), and the EVEN signal is transmitted to the LVDS-to-parallel converter RVb via the second LVDS line (B side). From the 8-bit RGB data transmitted on the differential lines RA0 / RB0, image data R0~R5 and G0 are output, and image data G1~G5 and B0~B1 are output from the differential lines RA1 / RB1.

[0052] Furthermore, image data B2-B5, DE signals, VS signals, and HS signals are output from differential lines RA2 / RB2, and image data G6-G7, R6-R7, and B6-B7 are output from differential lines RA3 / RB3. Here, the DE signal is none other than the data validity signals ENAB. As mentioned above, the outputted VS signals and HS signals are not used.

[0053] Next, the LVDS clock CLK of the differential line RACK / RBCK is supplied to the PLL circuit, generating an operating clock CK with the same frequency as the LVDS clock CLK, at 54 MHz. This operating clock CK defines the internal operation of the liquid crystal controller LCD_CTL, which processes image data corresponding to two adjacent RGB pixels (8 bits x 3 x 2) in the left-right direction of the liquid crystal panel LCD, synchronized with a single operating clock CK.

[0054] Therefore, a pixel with 1280 horizontal dots (=640×2) will be processed in 11.85 μS (=640 / 54 MHz), which is the processing time for 640 operating clocks CK. Each pixel is composed of three basic RGB color pixels, and the image data for each of these basic RGB color pixels is 1 byte in length and has a gradation of 2. 8 ×2 8 ×2 8 Therefore, the image data for all pixels (1280 dots) of one line will have a total length of 3 × 1280 bytes.

[0055] As shown in Figure 5, the liquid crystal controller LCD_CNT has 1280 source signal lines, each with 2 8(=256) The source driver SDV, which is driven by the grayscale drive signal, and the gate driver GDV, which controls the ON / OFF state of 1024 gate signal lines, are controlled as appropriate. Specifically, the liquid crystal controller LCD_CNT operates each part as appropriate based on the DE signal output from the LVDS transmission line and the operating clock CK, thereby achieving image update operation at a frame rate of FR=1 / 60Hz. As confirmed earlier, the DE signal corresponds to the data validity signal ENAB output by the VDP circuit 52.

[0056] In this embodiment, the source driver SDV is configured with 10 driver elements, each having 384 output terminals. As explained earlier, one line of pixels (1280 dots) of the liquid crystal panel LCD consists of 3 × 1280 basic pixels of the three RGB colors, so 10 driver elements are required to drive them. These 10 driver elements are sequentially supplied with image data DAT from the liquid crystal controller LCD_CNT, which is then transferred as appropriate based on the start signal SP and the transfer clock DCLK. Then, synchronized with the latch signal LT, the analog-converted drive signals are supplied to the 3840 source signal lines. As explained earlier, the time required for all pixels (1280 dots) of one line of the liquid crystal panel LCD to be updated is 11.85 μS (= 640 / 54 MHz).

[0057] Meanwhile, the liquid crystal controller LCD_CNT updates the gate signal line to be driven by supplying the gate start signal GS and the gate clock signal GCLK to the gate driver GDV. Here, the gate driver GDV is composed of four driver elements, each having 256 output terminals.

[0058] The update timing of the gate signal line is determined based on the falling edge timing of the DE signal and the operating clock CK. The horizontal rewind period of the gate signal line is counted by the operating clock CK and is typically calculated to be 640 + 204 clocks (see Figure 3(c)). Also, based on the number of DE signals (1024), the gate signal line to be driven is reset to its initial state, the gate start signal GS is output at the optimal timing, and the output of the gate clock signal GCLK is resumed. The vertical rewind period of the gate signal line is counted by the operating clock CK and is typically calculated to be 42 + 1024 clocks (see Figure 3(c)). However, as explained earlier, in this embodiment, the display device DS1 is operated with a design different from the typical value (see Figure 15).

[0059] Incidentally, the above display operation requires that the main liquid crystal display unit MONI is supplied with a power supply voltage of 5V while the LED backlight unit BL is lit. Therefore, in this embodiment, a power supply control circuit SPY is provided to ensure that the liquid crystal display unit MONI and the backlight unit BL operate in a consistent manner. The power supply control circuit SPY receives three types of DC voltages (3.3V, 5V, 12V) from the performance interface board 22, and also receives various power supply control signals (STBY, PWM, PS1, PS2) from the performance control CPU 63 of the composite chip 50 (see Figure 7(a)).

[0060] The power supply control circuit SPY then supplies a DC voltage of 5V as the power supply voltage for the main LCD display unit MONI at the optimal timing (see Figures 6(c) and 6(g)). In addition, the power supply control circuit SPY controls the power supply voltage of the backlight unit BL to 12V DC, and controls the BL_EN terminal and PWM terminal of the LED backlight unit BL to the appropriate H / L level to achieve optimal lighting operation.

[0061] Figure 6(a) is a circuit diagram showing the circuit configuration of the power supply control circuit SPY and its relationship to the backlight section BL and the liquid crystal display section MONI. As shown in the figure, the power supply control circuit SPY is mainly composed of a first switch circuit having transistor Tr1 and MOS transistor Q1, a second switch circuit having transistor Tr2 and MOS transistor Q2, a third switch circuit having transistor Tr3 and MOS transistor Q3, a fourth switch circuit having transistor Tr4 and MOS transistor Q4, and a buffer circuit SBUF that receives various control signals.

[0062] The buffer circuit SBUF is a high-speed Schmitt buffer (e.g., TC74VHC9125) that uses a DC voltage of 3.3V supplied from the performance interface board 22 as its power supply voltage, and operates in a non-inverting input / output relationship. That is, the performance control CPU 63 of the composite chip 50 outputs a power supply control signal (STBY, PWM, PS1, PS2) with a theoretical H / L width of 3.3V based on the power supply voltage of 3.3V, and the buffer circuit SBUF, upon receiving this, outputs a control signal (STBY, PWM, PS1, PS2) with the same logic (see Figure 7(a)).

[0063] As shown in Figure 6(a), all four input terminals (STBY, PWM, PS1, PS2) of the buffer circuit SBUF are connected to ground via pull-down resistors Rpd. This configuration ensures that all control signals are at a low level when the connection connectors are disconnected or when the power is turned on, or when each control signal is in a HiZ (high impedance) state.

[0064] Next, in the first to fourth switch circuits, transistors Tr1 to Tr4 are all NPN bipolar transistors and are driven to perform switching operations. That is, each transistor Tr1 / Tr2 / Tr3 / Tr4 operates ON based on the voltage division ratio of the bias resistor when the corresponding control signals PS1 / STBY / PWM / PS2 are at a high level, while it operates OFF when the control signals PS1 / STBY / PWM / PS2 are at a low level, as no current flows through the bias resistor.

[0065] Here, when transistors Tr1 and Tr4 are in the OFF position, the collector outputs of each transistor Tr1 and Tr4 are at a level higher than 3.3V (12V and 5V). Also, when MOS transistor Q1 is in the ON position and transistors Tr2 and Tr3 are in the OFF position, the collector outputs of each transistor Tr2 and Tr3 are approximately 12V. In this sense, each transistor Tr1 to Tr4, together with the bias resistor, constitutes a level shift circuit that increases the logic H level of the power supply control signals (STBY, PWM, PS1, PS2).

[0066] The bias resistors for transistors Tr1 to Tr4 are R11+R12, R21+R22, R31+R32, and R41+R42, respectively, and the voltage determined by the voltage division ratio of each bias resistor is supplied to the base terminals of transistors Tr1 to Tr4.

[0067] In this embodiment, by providing the level shift circuits (Tr1 to Tr4) described above, the luminescence brightness of the backlight can be increased while the power consumption of the performance control unit 23 can be significantly suppressed. That is, the power supply voltage (12V) of the backlight unit BL can be set to the highest possible level, while the logic H level of the power supply control signals (STBY, PWM, PS1, PS2) can be set to any low level (3.3V).

[0068] On the other hand, MOS transistors Q1 to Q4 are all P-channel type and perform switching operations according to the ON / OFF state of transistors Tr1 to Tr4. When ON, the source terminal S and drain terminal D are almost in a conductive state.

[0069] To be more specific, first, the MOS transistor Q1 receives a DC voltage of 12V supplied by the performance interface board 22 at its source terminal S. When transistor Tr1 is turned ON based on the H-level control signal PS1, the MOS transistor Q1 also turns ON based on the voltage across the bias resistor Rb1, which transitions to a powered state in response, and outputs a DC voltage of 12V to its drain terminal D.

[0070] This DC voltage of 12V is supplied to the backlight section BL via an RC filter circuit and a Zener diode. In this embodiment, in particular, the MOS transistor Q1 used has an ON resistance between source S and drain D of 25mΩ or more and 35mΩ or less. Therefore, even when a drive current (drain current ID) of 2.5A is continuously flowed, for example, the voltage drop across the MOS transistor Q1 is 0.1V or less, and the power loss is suppressed to about 0.22W (=2.5*2.5*35 / 1000). The ON resistance is the measurement result for pulse drive at VGS=-10V, ID=-4.5A.

[0071] Furthermore, transistors Q2 and Q3 receive the voltage from the drain terminal D of transistor Q1 at their respective source terminals S. Therefore, when MOS transistor Q1 is in the ON state, and transistors Tr2 / Tr3 turn ON based on the H-level control signal STBY / PWM, MOS transistors Q2 and Q3 also turn ON based on the voltage across the bias resistors Rb2 / Rb3, which transition to a current-enhanced state in response. As a result, a DC voltage of 12V is output to the drain terminals D of MOS transistors Q2 and Q3, via the ON state of transistor Q1.

[0072] This DC voltage of 12V is output as the control signal STBY from the drain terminal D of MOS transistor Q2, and as the control signal PWM from the drain terminal D of MOS transistor Q3. The control signal STBY is supplied to the BL_EN terminal (back light enable) of the backlight unit BL in a pulled-down state by the pull-down resistor Rpd, and the control signal PWM is supplied to the PWM terminal (pulse width modulation) of the backlight unit BL in a pulled-down state by the pull-down resistor Rpd.

[0073] In this embodiment, by setting the pull-down resistors Rpd to approximately 33kΩ, the current flowing through the pull-down resistors Rpd due to the DC voltage of 12V (STBY / PWM) is suppressed to approximately 0.36mA. Therefore, it is not necessary to select expensive elements as MOS transistors Q2 and Q3, and in this embodiment, elements with an ON resistance between source S and drain D of 2.5Ω or more and 3.8Ω or less are used. Note that the ON resistance is the measurement result under pulse drive at VGS=-4.5V, ID=-100mA.

[0074] Next, regarding the backlight section BL, the backlight section BL is composed of N x M light-emitting diodes (LEDs) arranged in a vertical and horizontal alignment, and a driver DVL that outputs negative logic drive pulses to synchronously light up the N x M light-emitting diodes. This driver DVL is composed of a BL_EN terminal that specifies whether or not to enable its internal operation, a PWM terminal that specifies the duty cycle of the negative logic drive pulses in the range of positive logic from 10% to 100%, and output terminals LED1 to LEDn that output drive pulses.

[0075] As explained earlier, the BL_EN terminal receives the control signal STBY from the power supply control circuit SPY, and the PWM terminal receives the control signal PWM. When the control signal STBY is at a high level (12V), the internal circuit of the driver DVL operates, enabling the output of drive pulses from the output terminals LED1 to LEDn. These drive pulses are negative logic pulses obtained by logically inverting the control signal PWM.

[0076] Thus, since the drive pulse in this embodiment is a negative logic pulse obtained by logically inverting the control signal PWM supplied to the PWM terminal, the closer the duty cycle of the control signal PWM is to 100%, the longer the L-level period of the output terminals LED1 to LEDn becomes, and the higher the average current flowing through the light-emitting diodes becomes, resulting in brighter backlighting. On the other hand, the closer the duty cycle is to 10%, the lower the average current flowing through the light-emitting diodes becomes, resulting in dimmer backlighting.

[0077] Therefore, the light intensity of the backlight can be changed by appropriately changing the duty cycle of the control signal (control pulse) PWM. For example, the backlight can be dimmed in a demo state when no player is present. However, in this embodiment, in order to avoid the complexity of such light emission control, the duty cycle of the control signal is maintained at 100%, and the control signal PWM does not change in a pulse-like manner, but maintains a constant H level (12V) in the operating state. As a result, the output terminals LED1 to LEDn of the driver DVL maintain a constant L level when the backlight section BL is operating.

[0078] Incidentally, both the BL_EN terminal and the PWM terminal are connected to ground via the pull-down resistor Rpd. Therefore, when the MOS transistor Q2 is OFF and the control signal STBY is in the HiZ state, the driver DVL is inactive, and the output terminals LED1 to LEDn are in the HiZ state, so all light-emitting diodes are turned off.

[0079] Furthermore, when MOS transistor Q3 is OFF and the control signal PWM is in the HiZ state, even if the control signal STBY is at the H level, the duty cycle is maintained at 0%, causing output terminals LED1 to LEDn to remain at the H level (12V) and all light-emitting diodes to turn off. Therefore, when power is turned on and no significant image data is transferred, or when the power supply control circuit SPY malfunctions, the backlight will turn off, thus preventing unnatural image display. Connecting the pull-down resistor Rpd between the four input terminals of the buffer circuit SBUF and ground is based on the same intention.

[0080] Next, we will explain the relationship between the fourth switch circuit, which has transistor Tr4 and MOS transistor Q4, and the main liquid crystal display unit MONI. As explained earlier, transistor Tr4 of the fourth switch circuit operates ON / OFF based on the H / L level of the control signal PS2.

[0081] Meanwhile, the MOS transistor Q4 receives a DC voltage of 5V supplied by the performance interface board 22 at its source terminal S. When transistor Tr1 is turned ON, the MOS transistor Q4 also turns ON based on the voltage across the bias resistor Rb4, which is energized in response, and outputs a DC voltage of 5V to its drain terminal D.

[0082] This DC voltage of 5V is supplied to the liquid crystal display unit MONI shown in Figure 5 via an RC filter circuit and a Zener diode, and is used as the power supply voltage for the liquid crystal display unit MONI. In this embodiment, in particular, the MOS transistor Q4 is an element in which the ON resistance between source S and drain D is 48mΩ or more and 65mΩ or less. Therefore, for example, even when a drive current (drain current ID) of 1.5A is steadily flowed, the voltage drop across the MOS transistor Q1 is 0.1V or less, and the power loss is suppressed to about 0.15W (=1.5*1.5*65 / 1000). The ON resistance is the measurement result under pulse drive with VGS=-4.5 and ID=-2.5A.

[0083] Next, the circuit operation of the power supply control circuit SPY will be explained based on Figures 6(b) to 6(j). After power-on, the composite chip 50 starts control operation after an assertion period in which the system reset signal SYS maintains an L level (timing T1 in Figure 6(d)). Then, 1000 mS after timing T1, the performance control CPU 63 of the composite chip 50 transitions the control signals PS1 and PS2 to an H level (timing T2).

[0084] Then, based on the H-level control signal PS1, MOS transistor Q1 turns ON, and the supply of 12V DC power to the backlight unit BL begins. Also, based on the H-level control signal PS2, MOS transistor Q4 turns ON, and the supply of 5V DC power to the liquid crystal display unit MONI begins. However, at this timing T2, both control signals STBY and PWM remain at the L level, so the backlight unit BL does not emit light. Therefore, no matter how the liquid crystal display unit MONI operates, there is no risk of an unnatural image being displayed.

[0085] Next, the performance control CPU 63 starts the initialization operation of the display clock and display circuit 74 approximately 5 ms after timing T2. The details of this control will be described in detail later, but these operations are one of the initialization operations before the operation of the VDP circuit 52 begins, and at this stage, no significant image signal is output to the display device DS1.

[0086] Subsequently, the performance control CPU 63 initializes the display registers as appropriate and then starts the operation of the display circuit 74 and the LVDS circuit 80 (timing T4). Therefore, from timing T4 onward, the LVDS signal, which is a significant image signal, is repeatedly output to the display device DS1 every 1 / 60th of a second (see Figure 6(f)).

[0087] However, at timing T4, the control signal PWM remains at the L level, so the backlight does not emit light. In other words, at timing T3, the performance control CPU 63 transitions the control signal STBY to the H level to control the driver DVL into an operational state, but at timing T4, the control signal PWM is still L, and the duty cycle of the drive pulse is 0%, so the backlight section BL remains off.

[0088] Meanwhile, after the display control CPU 63 starts the operation of the display circuit 74 and the LVDS circuit 80 (SS4 in Figure 21), at timing T5, which is more than 300 mS later, it transitions the control signal PWM to the H level (SS6 in Figure 21), and transitions the backlight unit BL to a 100% duty cycle illumination state. If the operation at timing T5 is performed, for example, by timer interrupt processing, at timing T5 the liquid crystal display unit MONI has already repeatedly received the LVDS signal as a meaningful image signal every 1 / 60th of a second, so an image based on that image signal will be displayed. In other words, immediately after the processing of step SS6 in Figure 21, steady-state processing (ST4~ST14 in Figure 22) starts, so at timing T5 the initial screen based on the display list DL is displayed.

[0089] However, as shown in Figure 21, if the performance control CPU 63 performs a 300ms standby process (step SS5 in Figure 21), the display list DL has not yet been issued at timing T5, so the displayed content will be a screen based on the VRAM (frame buffer FBa) after power-on. Therefore, considering this point, it is preferable to zero-clear the VRAM (especially frame buffers FBa and FBb) after power-on, but even if zero-clearing is not performed, the display of random images is only for a brief moment at the start of business at the gaming hall, so there is no problem. In other words, immediately after the processing of step SS6 in Figure 21, the steady-state processing (ST4 to ST14 in Figure 22) begins, and the initial screen based on the display list DL is displayed.

[0090] Incidentally, in this embodiment, the program is designed so that the program execution time from timing T2 to timing T4 is within 20 mS. This is because the display device DS1 used in this embodiment recommends that the transmission of the image signal (LVDS signal) start within a predetermined time τ (for example, 20 mS) from the time power is turned on to the liquid crystal display unit MONI.

[0091] In this embodiment, delaying the power supply timing to the liquid crystal display unit MONI by about 1 second using the control signal PS2 is also based on the above requirement. If power supply to the liquid crystal display unit MONI were to start simultaneously with power-on, it would be impossible to start transmitting the LVDS signal within a predetermined time τ (e.g., 20 mS) thereafter, given the assertion period and program execution time (processing time of SP1 to SP10) (see timing T4).

[0092] The main display device DS1 has been described in detail above, but the operation of the sub-display device DS2 is substantially the same. By performing the operation shown in Figure 6(b), the sub-liquid crystal display unit MONI and the backlight unit BL are configured to operate in a consistent manner, preventing inappropriate displays.

[0093] Furthermore, the sub-display device DS2 operates in the same manner as shown in Figure 42, based on the horizontal synchronization signal HS and vertical synchronization signal VS received from the VDP circuit 52. However, it is also preferable for the sub-control device DS2 to operate based on the data valid signal ENAB, rather than on the horizontal synchronization signal HS or vertical synchronization signal VS. Note that the data valid signal ENAB is transmitted to the sub-display device DS2 as a continuous signal ENAB, not in the form of a discrete DE signal (see lower right of Figure 14(a)).

[0094] Next, let's return to Figure 3(a) and explain the overall circuit configuration of the GM pachinko machine. As shown in Figure 3(a), the GM pachinko machine is mainly composed of a power supply board 20 that receives AC24V and outputs various DC voltages (35V, 12V, 5V) along with AC24V, a main control board 21 that is primarily responsible for game control operations, an effects interface board 22 equipped with circuit elements SND for sound effects, an effects control board 23 that uniformly executes lamp effects, sound effects, and image effects based on control commands CMD received from the main control board 21, a liquid crystal interface board 24 located between the effects control board 23 and the display devices DS1 and DS2, a payout control board 25 that controls the payout motor M to dispense game balls based on control commands CMD' received from the main control board 21, and a launch control board 26 that launches game balls in response to the player's operation.

[0095] Furthermore, the performance interface board 22, the performance control board 23, and the liquid crystal interface board 24 are directly connected via male and female connectors without the need for wiring cables. Therefore, even if the circuit configuration of each electronic circuit is made more complex and sophisticated, the overall space required for the board can be minimized, and noise immunity can be improved by minimizing the connection lines.

[0096] As shown in the diagram, the control command CMD' output by the main control board 21 is transmitted to the payout control board 25. On the other hand, the control command CMD output by the main control board 21 is transmitted to the performance control board 23 via the performance interface board 22. Here, both control commands CMD and CMD' are 16 bits long, but they are transmitted in parallel in two separate 8-bit segments.

[0097] The main control board 21 and the payout control board 25 are equipped with computer circuits including a one-chip microcontroller. The performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as a VDP circuit (Video Display Processor) 52 and an internal CPU circuit 51. In this specification, these control boards 21, 25, and 23, the circuits mounted on the performance interface board 22 and the liquid crystal interface board 24, and the operations realized by these circuits are functionally referred to collectively as the main control unit 21, the performance control unit 23, and the payout control unit 25. The performance control unit 23 and the payout control unit 25 are sub-control units with respect to the main control unit 21.

[0098] Furthermore, this pachinko machine GM is broadly divided into the frame-side member GM1, enclosed by the dashed line in Figure 3(a), and the board-side member GM2, which is fixed to the back of the game board 5. The frame-side member GM1 includes the inner frame 3 to which the glass door 6 and front panel 7 are pivotally attached, and the outer wooden frame 1 outside of it, and is permanently installed in the gaming hall for a long period of time regardless of changes in the machine model. On the other hand, the board-side member GM2 is replaced in response to changes in the machine model, and the new board-side member GM2 is attached to the frame-side member GM1 in place of the original board-side member. Note that everything except the frame-side member 1 is the board-side member GM2.

[0099] As shown in the dashed box in Figure 3(a), the frame-side member GM1 includes a power supply board 20, a backup power supply board 33, a payout control board 25, a launch control board 26, a frame relay board 36, and a motor / lamp drive board 37, and these circuit boards are fixed to the appropriate locations on the inner frame 3. On the other hand, the main control board 21 and the performance control board 23 are fixed to the back of the game board 5 together with the display devices DS1, DS2 and other circuit boards. The frame-side member GM1 and the game board-side member GM2 are electrically connected by centralized connection connectors C1 to C3 which are located in one place.

[0100] The power supply board 20 generates three types of DC voltages (35V, 12V, and 5V) based on the AC voltage (AC24V) distributed from the gaming hall, and distributes each DC voltage to the performance interface board 22 via the central connection connector C2. The three types of DC voltages (35V, 12V, and 5V), along with the AC voltage (AC24V), are also distributed to the payout control board 25. The DC voltages (35V, 12V, and 5V) distributed to the payout control board 25, along with the backup power supply BAK, are then distributed to the main control board 21 via the central connection connector C1.

[0101] 35V DC is used as the power supply for the ball feeding solenoid and launch solenoid in relation to the launching operation of the game balls, and as the power supply for the electromagnetic solenoid that drives the opening and closing of the electric tulip (variable prize device) and the large prize opening 16. 12V DC is used as the power supply for the LED lamps and motors controlled by each control board, and as the power supply voltage for the digital amplifier. Meanwhile, 5V DC is used as the power supply voltage for the one-chip microcontroller on the payout control board 25 and the main control board 21, and as the power supply voltage for the logic elements mounted on each control board. Furthermore, after the 5V DC voltage is reduced in level by the DC / DC converter on the performance interface board 22, the reduced voltages are used as the power supply voltage for various computer circuits (such as the composite chip 50 and the audio processor 27).

[0102] The backup power supply BAK is a DC 5V DC power supply used to retain data in the built-in RAM of the one-chip microcontrollers of the main control unit 21 and the payout control unit 25 after the power supply is cut off, and is implemented, for example, by an electric double-layer capacitor. In this embodiment, a dedicated backup power supply board 33 is provided, and the electric double-layer capacitor placed on the backup power supply board 33 is configured to be charged during game operation by the DC voltage of 5V received from the payout control board 25.

[0103] On the other hand, after the power is cut off, the backup power supply BAK retains the data from the built-in RAM of the one-chip microcontrollers of the main control unit 21 and the payout control unit 25, so that the main control unit 21 and the payout control unit 25 can resume the game operation that was in place before the power was cut off after the power is turned on. The backup power supply board 33 is equipped with electric double-layer capacitors that can retain the contents of the built-in RAM of each one-chip microcontroller for at least several days.

[0104] Incidentally, in this embodiment, unlike conventional equipment configurations, the power supply abnormality signal ABN, which indicates an abnormal drop in the AC voltage AC24V, is generated not in the power supply board 20, but in the power supply monitor unit MNT of the payout control board 25. As shown in Figure 3(b), the power supply monitor unit MNT is configured to include a full-wave rectifier circuit that rectifies the AC24V received from the power supply board 20, a photodiode D that receives the output of the full-wave rectifier circuit and emits light when energized, a phototransistor TR that uses the DC voltage 5V received from the power supply board 20 as its power source and turns ON based on the light emitted by the photodiode D, and an output unit that outputs a high-level detection signal ABN (power supply abnormality signal) based on the ON operation of the phototransistor TR. Note that the photodiode D and the phototransistor TR constitute a photocoupler PH.

[0105] In the above configuration, after power is turned on, the photocoupler PH quickly turns ON, causing the power abnormality signal ABN to reach a normal level (H). However, if the AC power then drops abnormally for any reason (normally a power outage), the photocoupler PH changes to the OFF state, causing the power abnormality signal ABN to change to an abnormal level (L). This power abnormality signal ABN is transmitted to the one-chip microcontroller on the payout control board 25, and is also transmitted to the one-chip microcontroller on the main control board 21 via the central connection connector C1. Therefore, each one-chip microcontroller that receives an abnormal level power abnormality signal ABN will perform a backup process to store the necessary information in its built-in RAM. As explained earlier, the information in the built-in RAM is maintained by the backup power supply BAK, so the game operation before the power outage can be resumed after power is turned on.

[0106] As shown in Figure 3(a), the performance interface board 22 is equipped with an audio circuit SND such as an audio processor 27, and the performance control board 23 is equipped with a composite chip 50 that incorporates computer circuits such as a VDP circuit 52 and an internal CPU circuit 51. Hereinafter, the internal CPU circuit may be abbreviated as the CPU circuit.

[0107] The performance interface board 22 is equipped with reset circuits RST3 and RST4 that detect an increase in power supply voltage when power is turned on and generate various reset signals RT3 and RT4. First, the reset circuit RST3 generates the reset signal RT3 based on the DC voltages of 12V and 5V distributed from the power supply board 20. Then, the reset signal RT3 resets only the audio memory 28 and is transmitted directly to the performance control board 23.

[0108] As shown in Figure 7(a), the reset signal RT3 transmitted to the performance control board 23 is ANDed with the output of the WDT (Watch Dog Timer) circuit 58 at the AND gate G1, and the system reset signal SYS is generated, which powers down the CPU circuit 51 and the VDP circuit 52 (see Figures 7(a) and 7(d)).

[0109] The reset signal RT3 generated by the reset circuit RST3 maintains a low level for a predetermined time as a power reset signal after power-on, and then rises to a high level. However, if the DC voltage drops by one or more of either 12V or 5V (usually when the power is cut off), the system reset signal SYS also drops to a low level in response to the level drop of the reset signal RT3, causing the CPU circuit 51 and VDP circuit 52 of the performance control board 23 to stop operating.

[0110] This system reset signal SYS also changes based on the output of the WDT circuit 58 (which is normally at a high level). Therefore, when the reset signal RT3 is high, if the output of the WDT circuit 58 drops to a low level due to a program malfunction or other reasons, the system reset signal SYS also changes to a low level, causing the CPU circuit 51 and VDP circuit 52 to be abnormally reset (see Figure 7(d)).

[0111] Meanwhile, the reset circuit RST4 generates a reset signal RT4 based on 3.3V, which is generated by stepping down the 5V supplied from the power supply board 20. This reset signal RT4 acts as a power reset signal when the power is turned on, and power-resets the audio processor 27.

[0112] As shown in the diagram, the reset circuit RST4 is also supplied with the system reset signal SYS returned from the performance control board 23. Therefore, when the CPU circuit 51 or VDP circuit 52 undergoes an abnormal reset, the audio processor 27 is also abnormally reset in synchronization with the abnormal reset of these circuits. As a result, the audio performance, along with the image and lamp performances, returns to its initial state, eliminating the risk of unnatural audio performances continuing.

[0113] Next, the payout control board 25, which is the frame-side member GM1, and the main control unit 21, which is the panel-side member GM2, are equipped with reset circuits RST1 and RST2, respectively. When the power is turned on, a power reset signal is generated, and each computer circuit is power-reset.

[0114] Thus, in this embodiment, reset circuits RST1 to RST4 are arranged on the main control unit 21, the payout control unit 25, and the performance interface board 22, respectively, so that the system reset signal SYS is not transmitted between circuit boards. In other words, since there is no wiring cable to transmit the system reset signal SYS, the risk of the computer circuit being abnormally reset due to noise superimposed on the wiring cable is eliminated.

[0115] However, the reset circuits RST1 and RST2 provided in the main control unit 21 and the payout control unit 25 each have a built-in watchdog timer, and if they do not receive a regular clear pulse from the CPU of each control unit 21 or 25, each CPU is forcibly reset.

[0116] Furthermore, the main control unit 21 is equipped with an initialization switch SW that can be operated by an operator, and is configured to output a RAM clear signal CLR indicating whether or not the initialization switch SW was turned ON when the power is turned on. This RAM clear signal CLR is transmitted to the one-chip microcontrollers of the main control unit 21 and the dispensing control unit 25, which determine whether or not to initialize the entire area of ​​the built-in RAM of the one-chip microcontrollers of each control unit 21 and 25.

[0117] Furthermore, as explained earlier, the one-chip microcontrollers in the main control unit 21 and the dispensing control unit 25 receive a power abnormality signal ABN from the power monitor MNT located in the dispensing control unit 25, and are configured to initiate necessary termination processes prior to power outages or business closures.

[0118] As shown in Figure 3(a), the main control unit 21 receives from the payout control unit 25 a prize ball counting signal indicating the payout operation of game balls, a status signal CON related to abnormalities in the payout operation, and an operation start signal BGN. The status signal CON includes, for example, a supply depletion signal, a payout shortage error signal, and a lower tray full signal. The operation start signal BGN is a signal that notifies the main control unit 21 that the initial operation of the payout control unit 25 has been completed after power is turned on.

[0119] Furthermore, the main control unit 21 receives switch signals from detection switches built into each of the prize entry slots 16-18 on the game board, while also driving solenoids such as the electric tulips. The solenoids and detection switches are configured to operate with the power supply voltage VB (12V) distributed from the main control unit 21. In addition, the switch signals indicating the entry status into the symbol entry slot 15, etc., are converted into TTL level or CMOS level switch signals by an interface IC that operates with power supply voltage VB (12V) and power supply voltage Vcc (5V), and then transmitted to the main control unit 21.

[0120] As explained earlier, the performance interface board 22 receives DC voltages (5V, 12V, 35V) at various levels from the power supply board 20 via the central connection connector C2 (see Figures 3(a) and 7(a)). The DC voltage of 12V is used as the power supply voltage for the digital amplifier 29 and as the driving voltage for LED lamps and the like. The DC voltage of 35V is distributed to the appropriate locations on the game frame and used as the driving voltage for solenoids that move movable parts back and forth.

[0121] Meanwhile, the 5V DC voltage is supplied as the power supply voltage for the circuit elements at various locations on the performance interface board 22, and is also supplied to two DC / DC converters DC1 and DC2 to generate 3.3V and 1.0V (see Figure 7(a)). The generated 3.3V and 1.0V DC voltages are supplied to the audio processor 27 as power supply voltages for I / O (input / output) and the chip core, respectively. In addition, the 3.3V DC voltage becomes the base voltage for the power reset signal RT4 generated by the reset circuit RST4.

[0122] The 5V DC voltage distributed to the performance interface board 22, along with the 3.3V generated by the DC / DC converter DC1, is distributed to the performance control board 23. The 3.3V DC voltage distributed to the performance control board 23 is then supplied as the power supply voltage to the composite chip 50, the PROM 53, and the CGROM 55.

[0123] As shown in Figure 7(a), the performance control board 23 is equipped with two DC / DC converters, DC3 and DC4, which generate 1.5V and 1.05V respectively based on the 5V DC voltage supplied to them. Here, the 1.05V DC voltage is the power supply voltage for the chip core of the composite chip 50, and the 1.5V DC voltage is the power supply voltage for I / O (input / output) with the DRAM 54. Therefore, the 1.5V DC voltage is also supplied to the DRAM 54 as a power supply voltage.

[0124] As shown in Figure 3(a), the performance interface board 22 receives the control command CMD and the strobe signal STB from the main control unit 21 and forwards them to the performance control board 23. More specifically, as shown in Figure 7(a), the control command CMD and the strobe signal STB are forwarded via the input buffer 40 to the composite chip 50 (CPU circuit 51) of the performance control board 23. Here, the strobe signal STB is the received interrupt signal IRQ_CMD, and the performance control CPU 63 obtains the control command CMD based on the interrupt processing program (interrupt handler) that is activated upon receiving the received interrupt signal IRQ_CMD.

[0125] As shown in Figure 7(a), the input buffer 44 of the performance interface board 22 receives switch signals from the chance button 11 and the volume switch VLSW from the frame relay boards 35 and 36, and transmits each switch signal to the CPU circuit 51 of the performance control board 23. Specifically, it transmits a 3-bit length of encoder output indicating the contact position (0 to 7) of the volume switch VLSW and a 1-bit length indicating the ON / OFF state of the chance button 11 to the CPU circuit 51.

[0126] Furthermore, the performance interface board 22 is connected to the lamp drive board 30 and the motor lamp drive board 31, and is also connected to the lamp drive board 37 via the frame relay boards 35 and 36. As shown in the figure, an output buffer 42 is arranged corresponding to the lamp drive board 30, and an input buffer 43a and an output buffer 43b are arranged corresponding to the motor lamp drive board 31. In Figure 7(a), for convenience, the input buffer 43a and the output buffer 43b are collectively referred to as the input / output buffer 43. The input buffer 43a receives the output SN0 to SNn of the origin sensor, which determines the current position of the movable performance element (the rotational position of the performance motors M1 to Mn), and transmits it to the CPU circuit 51 of the performance control board 23.

[0127] The lamp drive board 30, motor lamp drive board 31, and lamp drive board 37 are equipped with the same type of driver IC, and the performance interface board 22 forwards the serial signals received from the performance control board 23 to each driver IC. Specifically, the serial signals are the lamp (motor) drive signal SDATA and the clock signal CK. The drive signal SDATA is transmitted to each driver IC in a clock-synchronous manner, and lamp effects using numerous LED lamps and illuminated lamps, as well as mechanical effects using performance motors M1 to Mn, are executed.

[0128] In this embodiment, the lamp effects are performed by three lamp groups CH0 to CH2. The lamp drive board 37 receives the lamp drive signal SDATA0 of CH0 via frame relay boards 35 and 36, synchronized with the clock signal CK0. The series of lamp drive signals SDATA0, transmitted as serial signals, are output from the driver IC to the lamp group CH0 when the operation control signal ENABLE0 changes to an active level, thereby updating the illumination state of all lamps simultaneously.

[0129] The same applies to the lamp drive board 30. The driver IC of the lamp drive board 30 receives the lamp drive signal SDATA1 of the lamp group CH1 in synchronization with the clock signal CK1, and simultaneously updates the lighting status of the lamp group CH1 when the operation control signal ENABLE1 changes to the active level.

[0130] Meanwhile, the driver IC mounted on the motor lamp drive board 31 receives a lamp drive signal transmitted in a clock-synchronous manner to drive the lamp group CH2, and also receives a motor drive signal transmitted in a clock-synchronous manner to drive the performance motor group M1 to Mn, which consists of multiple stepping motors. The lamp drive signal and motor drive signal are a series of serial signals SDATA2, which are transmitted serially in synchronization with the clock signal CK1. The driver IC that receives these signals updates the drive state of the lamp group CH2 and the motor group M1 to Mn at the timing when the operation control signal ENABLE2 changes to the active level.

[0131] Next, we will explain the audio circuit SND. As shown in Figure 7(a), the performance interface board 22 is equipped with an audio processor (speech synthesis circuit) 27 that reproduces audio signals based on instructions received from the CPU circuit 51 (performance control CPU 63) of the performance control board 23, an audio memory 28 that stores compressed audio data and other data which are the source data of the audio signals to be reproduced, and a digital amplifier 29 that receives the audio signals output from the audio processor 27.

[0132] The audio processor 27 incorporates a WDT circuit that automatically resets the internal circuit settings to their default values ​​(initial values) in the event of an abnormal operation of the internal circuit, and an audio control register SRG. Based on the operation parameters (settings made by voice commands) received from the performance control CPU 63 to the audio control register SRG, the audio processor 27 accesses the audio memory 28 and plays and outputs the necessary audio signals.

[0133] As shown in Fig. 7(a), the audio processor 27 and the audio memory 28 are connected by a 26-bit audio address bus and a 16-bit audio data bus. Therefore, the audio memory 28 can store 1 Gbit (= 2 26 × 16) of data.

[0134] The audio control register SRG is divided into register banks 1 to 6, and is specified by register numbers 00H to FFH respectively. Therefore, a predetermined setting operation is realized by the production control CPU 63 writing a 1-byte operation parameter to the audio control register SRG with a predetermined register number (1-byte length) after specifying the register bank.

[0135] In the case of this embodiment, the register numbers (00H to FFH) of the audio control register SRG correspond to the address space CS3 of the production control CPU 63. For example, when setting the operation parameter YYH to the audio control register SRG with the register number XXH, the production control CPU 63 writes XXH to the zero address of the address space CS3, and then writes YYH to the first address. That is, the production control CPU 63 writes XXH and YYH to its data bus in this order. In this specification, the suffix H and the prefix 0X / 0x indicate that the numerical value is in hexadecimal notation.

[0136] Also, in this specification, the address spaces CS0 to CS7 mean external memories (excluding built-in memories) for the CPU circuit 51 that can define the memory type including volatility and the data bus width (8 / 16 / 32 bits) respectively. These address spaces CS0 to CS7 are selected by different chip select signals CS0 to CS7, and are configured to be set so that the READ / WRITE control signals that function during READ / WRITE access can be optimized according to the memory type. This setting operation is executed for the bus state controller 66.

[0137] Figure 7(e) illustrates the setting operation of the audio register SRG by the performance control CPU 63, showing the contents of the 2-bit address bus A1-A0 and the 1-byte data bus D7-D0. In this embodiment, the chip select signal CS3 is set to automatically become active when accessing the address space CS3 at power-on, but this point will be explained later in relation to Figures 9 and 16.

[0138] In any case, in this embodiment, the compressed audio data stored in the audio memory 28 is phrase compressed data identified by a 13-bit phrase number NUM(000H~1FFFH), and can include up to 8192 types (=2 13 Each of these is stored corresponding to the phrase number NUM. This phrase number NUM is then identified by the setting value (operation parameter) of the voice command transmitted from the performance control CPU 63 to the voice control register SRG of the voice processor 27.

[0139] As described above, the audio memory 28 having the above configuration is power-reset by the reset signal RT3, and the audio processor 27 is power-reset by the reset signal RT4. As shown in Figure 7(c), the reset signal RT4 rises to the H level after a predetermined assertion period ASRT (L level section) following power-on. In this embodiment, the internal circuitry of the audio processor 27 then automatically functions to execute an initialization sequence process. This initialization sequence process is an internal operation performed in a predetermined procedure, and the performance control CPU 63 cannot access the audio register SRG while the initialization sequence process is running.

[0140] Then, once the internal initialization sequence processing is complete, the interrupt signal IRQ_SND to the CPU circuit 51 changes to a low level, and the CPU circuit 51 (performance control CPU 63) executes an interrupt processing program based on the interrupt signal IRQ_SND. Then, based on a predetermined instruction, the interrupt signal IRQ_SND is returned to a high level, but the details of this will be further described later with reference to Figure 18(c).

[0141] As shown in Figure 7(a), the data bus and address bus of the CPU circuit 51 of the performance control unit 23 also extend to the clock circuit (real time clock) 38 and performance data memory 39 mounted on the liquid crystal interface board 24. The clock circuit 38 is connected to the lower 4 bits of the address bus and the lower 4 bits of the data bus of the CPU circuit 51, and when the clock circuit 38 is selected by the chip select signal CS4, the CPU circuit 51 is configured to be able to arbitrarily access the internal register (which has a 4-bit address value).

[0142] Furthermore, the performance data memory 39 is a high-speed accessible memory element SRAM (Static Random Access Memory) connected to 16 bits of the address bus and the lower 16 bits of the data bus of the CPU circuit 51. When a chip is selected by the chip select signal CS4, the game performance information and other data stored in the SRAM (performance data memory) 39 are accessed by the CPU circuit 51 as appropriate (read / write). Note that in the address space CS4 selected by the chip select signal CS4, addresses 0 to 15 are assigned to the clock circuit 38 and are therefore not used by the SRAM 39.

[0143] The clock circuit 38 and the performance data memory 39 are powered by a secondary battery (not shown), which is charged as needed by the power supply voltage from the power supply board 20 during game operation. Therefore, even after the power is cut off, the clock circuit 38 continues to time, and the game performance information stored in the performance data memory 39 is permanently retained (non-volatile). The clock circuit (RTC) 38 is configured to output an interrupt signal IRQ_RTC to the CPU circuit 51 (RTC interrupt). This RTC interrupt includes an alarm interrupt that can specify the day, day of the week, hour, minute, and second, and a timer interrupt that is activated after a predetermined time has elapsed. In this embodiment, the alarm interrupt is used to update the daily game performance information at the end of each day of business.

[0144] As shown on the right side of Figure 7(a), the performance control board 23 is equipped with a composite chip 50 that incorporates a CPU circuit 51 and a VDP circuit 52, a control memory (PROM) 53 that stores the control program for the CPU circuit 51, a DRAM (Dynamic Random Access Memory) 54 that can access large amounts of data at high speed, and a CGROM 55 that stores a large amount of CG data necessary for performance control.

[0145] As will be described later with respect to Figure 10, in this embodiment, the control memory (PROM) 53 is located in address space CS0, which is selected by the chip select signal CS0. Also, the DRAM (Dynamic Random Access Memory) 54, which is composed of DDR (Double-Data-Rate 3), is located in address space CS5, which is selected by the chip select signal CS5.

[0146] Figure 8(a) is a circuit block diagram showing the composite chip 50 that constitutes the performance control unit 23, including related circuit elements. As shown in the figure, the composite chip 50 of this embodiment incorporates a CPU circuit 51 that issues a display list DL at predetermined intervals, and a VDP circuit 52 that generates image data based on the issued display list DL and drives the display devices DS1 and DS2. The CPU circuit 51 and the VDP circuit 52 are connected through a CPUIF circuit 56 that relays the transmitted and received data between them.

[0147] The VDP circuit 52 incorporates an audio circuit SND that performs the same functions as the audio processor 27, but the first embodiment described below does not utilize the audio circuit SND. However, as in the last embodiment described, if the audio circuit SND built into the VDP circuit 52 is utilized, the placement of the audio memory 28 and the audio processor 27 becomes unnecessary.

[0148] First, the CPU circuit 51 receives the oscillation output of the oscillator OSC1 (for example, 100 / 3MHz) at the HCLKI terminal, and multiplies its frequency (for example, by 8) to obtain a CPU operating clock of approximately 266.7MHz (see Figure 14(b)). Here, the oscillator OSC1 is configured to output a spread spectrum wave, thereby providing EMI (Electromagnetic Interference) protection against radio interference / electromagnetic interference.

[0149] Incidentally, in this embodiment, the CPU operating clock can also be generated based on the output of oscillator OSC2, which will be described later, instead of oscillator OSC1, thus eliminating the need for oscillator OSC1. However, in a configuration with a single oscillator, the frequency multiplication ratio of the PLL circuit becomes the same fixed value (for example, 5) as in the case of the system clock described below, so the frequency of the CPU operating clock becomes 200MHz (=40MHz × 5), which is the same as the system clock of the VDP circuit 52.

[0150] While this configuration has the advantage of sharing the operating cycles of the built-in CPU circuit 51 and the VDP circuit 52, it contradicts the requirement to speed up the CPU operation as much as possible. In other words, the VDP operation cannot be sped up beyond a certain point, so it cannot reliably meet the requirement for faster CPU operation. Therefore, in this embodiment, two oscillators are provided to optimize the operating cycles of the VDP circuit 52 and the CPU circuit 51, respectively. Furthermore, by providing a separate oscillator OSC1, the above-mentioned EMI countermeasures can be improved.

[0151] Based on the above, the VDP circuit 52 is described as follows: The VDP circuit 52 receives the oscillation output (40MHz) of oscillator OSC2, which is separate from oscillator OSC1, at the PLLREF terminal, multiplies the frequency using a PLL (Phase Locked Loop) circuit, and uses this as the system clock for the VDP circuit 52. The frequency multiplication ratio of the PLL circuit is fixed by a setting value at a predetermined setting terminal, and in this embodiment, the setting value at the setting terminal (3-bit PLLMD terminal) is a fixed value of 5, so the system clock of the VDP circuit 52 becomes 200MHz (=40MHz × 5) (see Figure 14(b)).

[0152] Furthermore, in this embodiment, the dot clock DCK defines the operation of the display circuits 74A to 74C. A ~DCK C Furthermore, the DDR clock for the external DRAM 54 is also generated based on the oscillation output (40MHz) of the oscillator OSC2. In other words, the output (40MHz) of the oscillator OSC2 functions as the reference clock for the entire VDP circuit 52.

[0153] As will be explained later regarding Figures 14 and 15, the display circuits 74A to 74C typically drive different display devices, so the dot clock DCK defines the operation of each display circuit 74A to 74C. A ~DCK CThis needs to be adapted to the specifications of the display device to be driven. Based on this need, in this embodiment, the display circuits 74A to 74C receive one of the output clocks (DCLKAI to DCLKCI) of the dedicated oscillator circuits DCLKA to DCLKC and convert it to the dot clock DCK A ~DCK C It is configured to allow for this as well.

[0154] When this configuration is used, the design of the multiplication ratio and division ratio, as well as the setting process for the VDP register RGij, which will be described later, become unnecessary, and the dot clock DCK A ~DCK C The frequency can be easily optimized. That is, the dot clock frequency F of the main display device DS1. DOT1 Corresponding to the oscillation frequency F DOT1 A dedicated oscillator circuit DCLKA is provided, and the dot clock frequency F of the sub-display unit DS2 is also provided. DOT2 Corresponding to the oscillation frequency F DOT2 It is also possible to provide a dedicated oscillator circuit DCLKB.

[0155] However, adopting such a configuration would require a dedicated oscillation circuit for each display device, complicating the equipment configuration. Therefore, in this embodiment, in order to simplify the equipment configuration, the dot clock DCK of the display circuits 74A / 74B is controlled based on the oscillation output (40MHz) of the oscillator OSC2. A / DCK B Specifically, as shown in Figure 14(b), for the display circuit 74A that drives the main display device DS1, the oscillation output (40MHz) of the oscillator OSC2 is subjected to a predetermined multiplication process (×10⁸) and frequency division process (1 / 40), thereby generating a dot clock DCK with a frequency of 108MHz. A It is generating.

[0156] Similarly, in the display circuit 74B that drives the sub-display device DS2, the oscillation output (40MHz) of the oscillator OSC2 is subjected to predetermined frequency multiplication (×10⁸) and frequency division (1 / 160) to obtain the frequency F dot =27MHz dot clock DCK BThis generates the following. Designing these multiplication and division ratios is somewhat complicated, and it would be easier to provide a dedicated oscillator circuit, but in this embodiment, prioritizing the simplification of the equipment configuration, a dedicated oscillator circuit is not provided.

[0157] In any case, Dot Clock DCK A ~DCK C These are set individually for each display circuit 74A~74C, but these dot clock DCK A ~DCK C In this specification, when referring to them collectively, they may be called "display clock DCK". Also, in the following description, the dot clock DCK A ya DCK B For convenience, this is sometimes abbreviated as "Dot Clock DCK".

[0158] In this embodiment, a low-speed LVDS output configuration is not adopted, so the LVDS clock CLK of the LVDS signal output via the display circuit 74A is also the dot clock DCK. A The same generation process is used to achieve a frequency of 108 MHz. However, in this embodiment, a dual-link transmission line is used, so the actual frequency of the LVDS clock CLK is 54 MHz, as explained with respect to Figure 4. Note that when a single-link transmission line is used, the frequency of the LVDS clock CLK is 108 MHz.

[0159] As described above, in this embodiment, the oscillation output (40MHz) of oscillator OSC2 is used as the reference clock for the system clock, dot clock DCK, and DDR clock. Considering this importance, oscillator OSC2 is configured to operate at the same power supply voltage of 3.3V as the VDP circuit 52, and to oscillate and output the reference clock only when the output enable terminal OE is at a high level (=3.3V). Furthermore, if the power supply voltage of 3.3V drops below a predetermined level, normal operation of the display cannot be expected thereafter, so the system is configured to generate an unmaskable interrupt (NMI).

[0160] Furthermore, the composite chip 50 is provided with an HBTSL terminal, and based on the logic level of the HBTSL terminal, it is determined whether the boot program (initial setup program) executed after power-on (CPU reset) is stored in CGROM 55 (HBTSL = H) or in another memory (HBTSL = L). As shown in the figure, in this embodiment, it is set to the HBTSL = L level, and address zero of the address space CS0 of the performance control CPU 63 is assigned to a location other than CGROM. Specifically, address space CS0 is assigned to the control memory 53.

[0161] On the other hand, when the HBTSL terminal is set to the H level (see dashed line), address zero in the address space CS0 of the performance control CPU 63 is assigned to the CGROM 55. In this case, the memory type and bus width (64 / 32 / 16 bits) of the CGROM 55 are determined based on the input values ​​to the 2-bit HBTBBWD terminal and the 4-bit HBTRMSL terminal, respectively. These points will be further described later based on Figure 39.

[0162] Next, we will explain the CPUIF circuit 56, which relays the transmitted and received data between the CPU circuit 51 and the VDP circuit 52. As shown in Figure 8(a), the CPUIF circuit 56 is connected to a control memory (PROM) 53 that nonvolatilously stores the control program and necessary control data, and a work memory (RAM) 57 with a storage capacity of about 2 MB, and both are configured to be accessible from the CPU circuit 51. As explained earlier, the control memory (PROM) 53 is located in address space CS0 selected by the chip select signal CS0, and the work memory (RAM) 57 is located in address space CS6 selected by the chip select signal CS6.

[0163] The work memory (RAM) 57 is equipped with a DL buffer BUF that temporarily stores a display list DL, which contains a series of instruction commands that specify one frame each of the display devices DS1 and DS2. In this embodiment, the series of instruction commands includes texture loading commands such as the TXLOAD command for reading image materials (textures) from the CGROM 55 and decoding (decoding) them; texture setting commands such as the SETINDEX command, which has the function of pre-specifying the VRAM area (index space) to which the images are decoded (decoded); primitive drawing commands such as the SPRITE command for placing the decoded (decoded) image materials in a predetermined position in the virtual drawing space; environment setting commands such as the SETDAVR command and SETDAVF command for specifying the drawing area to be actually drawn on the display device from the image drawn in the virtual drawing space by the drawing commands; and index table control commands (WRIDXTBL) related to the index table IDXTBL that manages the index space.

[0164] Figure 12(c) illustrates the relationship between the virtual drawing space (horizontal X direction ±8192: vertical Y direction ±8192), the drawing area that can be arbitrarily set within the virtual drawing space, and the actual drawing area in the frame buffers FBa and FBb that temporarily store the image data to be output to the display devices DS1 and DS2.

[0165] Next, the CPU circuit 51 is a circuit with performance equivalent to that of a general-purpose one-chip microcontroller, and is configured to include an image control CPU 63 that comprehensively controls image effects based on the control program in the control memory 53, a watchdog timer (WDT) that forcibly resets the CPU if the program goes into a runaway state, an internal RAM 59 with a memory capacity of about 16k bytes used as the CPU's working area, a DMAC (Direct Memory Access Controller) 60 that enables data transfer without going through the CPU 63, a serial input / output port (SIO) 61 with multiple input ports Si and output port So, a parallel input / output port (PIO) 62 with multiple input ports Pi and output port Po, and an operation control register REG in which setting values ​​are set to control the operation of each of the above parts. However, in this embodiment, in which an external WDT circuit 58 is provided, the watchdog timer (WDT) built into the CPU circuit 51 is not utilized.

[0166] For convenience, this specification uses the term "input / output port," but in the performance control unit 23, the input / output port includes an input port and an output port that operate independently. This also applies to the input / output circuits 64p and 64s described below.

[0167] The parallel input / output port 62 is connected to an external device (performance interface board 22) via the input / output circuit 64p, and the performance control CPU 63 receives the 3-bit encoder output of the volume switch VLSW, the switch signal of the chance button 11, the control command CMD, and the interrupt signal STB via the input circuit 64p. The 3-bit encoder output and the 1-bit switch signal are supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p.

[0168] Similarly, the received control command CMD is supplied to the parallel input / output port (PIO) 62 via the input / output circuit 64p. In addition, the strobe signal STB is supplied to the interrupt terminal of the performance control CPU 63 via the input / output circuit 64p, thereby activating the receive interrupt processing. Therefore, based on the receive interrupt processing, the performance control CPU 63, having grasped the control command CMD, will then uniformly control the sound effects, lamp effects, motor effects, and image effects corresponding to this control command CMD, after performing a performance lottery and other processes.

[0169] While not particularly limited, in this embodiment, the SMC (Serial Management Controller) 78 of the VDP circuit 52 is used for lamp and motor effects. The SMC 78 is a composite controller that incorporates an LED controller and a motor controller, and is configured to output serial signals in a clock-synchronous manner. The motor controller is configured to output latch pulses at any timing based on a predetermined setting value in the control register 70, and is also configured to accept serial signals in a clock-synchronous manner.

[0170] Therefore, in this embodiment, motor drive signals and LED drive signals are output from the SMC unit 78 in synchronization with the clock signal, while a latch pulse is output as the operation control signal ENABLE at an appropriate timing. In addition, the origin sensor signals SN0 to SNn from the performance motor group M1 to Mn are configured to be input serially in a clock-synchronous manner.

[0171] As explained with respect to Figure 7(a), the clock signals CK0~CK2, drive signals SDATA0~SDATA2, and operation control signals ENABLE0~ENABLE2 are transmitted to predetermined drive boards 30, 31, and 37 via output buffers 41~43. In addition, the origin sensor signals SN0~SNn are serially input from the motor lamp drive board 31 to the SMC unit 78 via input / output buffer 43.

[0172] However, in this embodiment, it is not essential to use the SMC unit 78. That is, since the CPU circuit 51 has a general-purpose serial input / output port SIO61 built in, the lamp and motor effects can also be performed using these.

[0173] Specifically, as shown by the dashed line in Figure 8(a), in the configuration shown by the dashed line, clock signals CK0~CK2 and drive signals SDATA0~SDATA2 are output via the input / output circuit 64s which is internally connected to the serial input / output port SIO61, and operation control signals ENABLE0~ENABLE2 are output via the input / output circuit 64p. For convenience, these are referred to as input / output ports and input / output circuits, but in reality, they are output ports and output circuits that perform the function.

[0174] Here, the serial output port SO is configured to incorporate a 16-stage FIFO register. The DMAC circuit 60 is activated upon receiving an operation start instruction (see Figure 22(b)ST18) from the performance control CPU 63, and is configured to sequentially read the necessary drive data from the lamp / motor drive table (see Figure 22(b)) and DMA transfer it to the FIFO register of the serial output port SO. The drive data stored in the FIFO register is output serially from the serial output port SO using a clock synchronization method. The DMAC circuit has multiple (e.g., 7) DMA channels, but it is configured to DMA transfer lamp drive data using the third DMA channel, which has lower priority, and motor drive data using the first DMA channel, which has the highest priority.

[0175] The operation control register REG, built into the CPU circuit 51, is an 8-bit, 16-bit, or 32-bit register with a register number (address value) starting from 0xFF400000, and is configured to be accessible via WRITE / READ from the performance control CPU 63 as needed (see Figure 10). Therefore, due to the influence of noise and other factors, the operation control register REG may be set to an unreasonable value.

[0176] However, the composite chip 50 can be abnormally reset by, for example, intentionally causing an infinite loop to be executed and activating the external WDT circuit 58. In this case, the value of the operation control register REG is returned to the same default value (initial value) as after power-on, and the value of the VDP register RGij in the VDP circuit 52 is also returned to the default value (initial value), thereby resolving the abnormal state.

[0177] Figure 7(b) shows the circuit configuration related to this reset operation and illustrates the reset mechanism characteristic of this embodiment. In this specification, the VDP register referred to as RGij does not refer to the operation control register REG built into the CPU circuit 51, but rather to one of the control registers 70 (see Figure 10) that control the internal operation of the VDP circuit 52. Furthermore, the system control circuit 520 shown in Figure 7(b) refers to the internal control circuit of the VDP circuit 52 that functions based on the setting value of the VDP register RGij (one of the control registers 70 in Figure 10) (see Figure 7(a)). The VDP register RGij is located in the address space CS7 selected by the chip select signal CS7 in the address map of the performance control CPU 63.

[0178] Based on the above, the reset mechanism can be described as follows: As shown in Figure 7(b), the composite chip 50 is configured so that its internal circuitry can be reset via three OR gates G2 to G4 that receive the logically inverted system reset signal SYS bar. However, in this embodiment, as shown by the dashed line, the built-in WDT is not activated, so the input and output terminals of OR gate G2 are directly connected.

[0179] In any case, a pattern check circuit CHK is provided between the CPU circuit 51 and the VDP circuit 52, and the pattern check circuit CHK is configured to output a reset signal RST on the condition that it receives a predetermined keyword sequence (a cryptographic sequence for reset) from the parallel input / output port (PIO) 62.

[0180] The internal circuitry of the composite chip 50 is divided into three parts: (1) the CPU circuit 51, (2) the display circuit 74 of the VDP circuit 52, and (3) the parts of the VDP circuit 52 other than the display circuitry. Each part is configured to receive reset signals from OR gates G2 to G4 via the first reset path to the third reset path.

[0181] First, OR gate G2, whose input / output terminals are directly connected, is associated with the first reset path and is configured to reset the entire CPU circuit 51 based on the system reset signal SYS bar. OR gate G3 is associated with the second reset path and is configured to reset the entire VDP circuit 52 based on OR logic, receiving the system reset signal SYS bar and the reset signal RST from the pattern check circuit CHK.

[0182] This second reset path is used not only for power-on reset operations, but also when the performance control CPU 63 detects a predetermined abnormality and performs an abnormal reset of the entire VDP circuit 52 to return it to its initial state. Specifically, if a serious abnormality is determined to have occurred based on a predetermined status register RGij indicating the internal operation of the VDP circuit 52, the pattern check circuit CHK generates a reset signal RST, thereby performing an abnormal reset of the entire VDP circuit 52. The display circuit 74 is abnormally reset via the OR gate G4 through the second reset path → third reset path.

[0183] On the other hand, the internal circuits built into the VDP circuit 52 are configured to be individually reset when necessary via a fourth reset path. The internal circuits that can be individually reset include the index table IDXTBL shown in Figure 8(a), the data transfer circuit 72, the preloader 73, the display circuit 74, the drawing circuit 76, the SMC circuit 78, and the audio circuit SND, as well as the ICM circuit shown in Figure 13.

[0184] The method for achieving individual reset operations is as shown at the bottom of Figure 7(b). For example, the display circuit 74 is reset by writing a first reset value to a predetermined VDP register RGij (system command register), via the fourth reset path 4A → third reset path.

[0185] Furthermore, each internal circuit of the VDP circuit 52 (72, 73, 74, 76, SND, ...) is individually reset by (1) writing a setting value that identifies the target circuit to the first VDP register RGij (reset RQ register), and then (2) writing a second reset value to a predetermined VDP register RGij (system command register) (fourth reset path 4B). Although not used in this embodiment, the audio circuit SND can be reset not only by the fourth reset path 4B, but also by writing a reset value to a predetermined VDP register (circuit setting command register) (fourth reset path 4C).

[0186] Because this embodiment has the above configuration, when the power is turned on or when the program malfunctions, the entire VDP circuit 52 automatically returns to its initial state, and if necessary, each part can be returned to its initial state to recover from the abnormal situation. For example, when the drawing circuit 76 freezes due to no READ / WRITE access to the built-in VRAM 71 for a certain period of time, the drawing circuit 76 is individually initialized via the fourth reset path 4B (see ST16a in Figure 22(d)). The same applies to the preloader 73 and the data transfer circuit 72; in the event of a predetermined abnormality, the preloader 73 is initialized via the fourth reset path 4B (see ST27 in Figure 29), and the data transfer circuit 72 is initialized via the fourth reset path 4B (see ST27 in Figures 24 and 29).

[0187] Furthermore, with respect to the display circuit 74, if an underrun error occurs where the generation of display data cannot keep up with the display timing every 1 / 60th of a second, the display circuit 74 is individually initialized via the fourth reset path 4A or the fourth reset path 4B (see ST10c in Figure 22). These individual reset operations will be further described later in relation to the program processing shown in Figure 22 and subsequent figures.

[0188] The reset mechanism characteristic of this embodiment has been described above. When any of the reset paths 1 to 4 is activated and the internal circuitry of the composite chip 50 is reset, the setting value of the VDP register RGij corresponding to that internal circuitry returns to the same default value as after power-on.

[0189] Next, let's return to the internal configuration of the CPU circuit 51 and continue explaining its characteristic circuit configuration. Figure 9 is a block diagram showing the internal configuration of the CPU circuit 51 in some detail. In addition to the built-in RAM 59, DMAC circuit 60, SIO 61, PIO 62, and WDT described earlier, the CPU circuit 51 is composed of many other characteristic circuits.

[0190] Firstly, the CPU circuit 51 implements the Harvard architecture by having separate CPU fetch buses for instructions and CPU memory access buses for data. As a result, the fetch operation in which the CPU core (performance control CPU) 63 reads instructions from memory and the memory access operation do not conflict, and high-speed processing is achieved by performing fetch operations continuously.

[0191] Furthermore, the CPU core 63 is configured to have multiple (for example, 15) register banks RB0 to RB14, and is configured to allow selection of whether or not to use them. When register bank RBi is enabled, at the start of interrupt processing, the register values ​​(each 32 bits long) of the CPU's internal registers (for example, 19) are automatically saved to the available register bank RBi.

[0192] Furthermore, when a predetermined return instruction is executed at the end of the interrupt processing, for example, 19 saved data items are automatically restored to their corresponding internal registers. Therefore, unlike in a normal configuration, there is no need to execute 19 PUSH instructions at the start of the interrupt processing and 19 POP instructions at the end of the interrupt processing, resulting in high-speed processing.

[0193] Furthermore, the CPU circuit 51 of this embodiment implements Harvard cache operation by providing an instruction cache memory 67, an operand cache memory 89, and a cache controller 69. When accessing the same address, it utilizes cached data to further speed up program processing. In addition, a bus bridge 65 and controllers for peripheral bus (1), peripheral bus (2), and peripheral bus (3) are provided to appropriately connect the internal bus to peripheral bus (1), peripheral bus (2), and peripheral bus (3).

[0194] Next, in the circuit configuration shown in Figure 9, the bus state controller 66 operates based on appropriate settings in the operation control register REG to optimize memory READ and memory WRITE operations with various memory devices connected to the CPU circuit 51. Memory READ and memory WRITE operations are performed, for example, at the timings illustrated in Figure 40. The timings of the address data output from the address bus (28-bit), the READ data read to the READ data bus (32-bit), the WRITE data written to the WRITE data bus (32-bit), and control signals such as the chip select signals CS0 to CS7 are appropriately defined based on the settings in the operation control register REG, corresponding to the characteristics of each memory device.

[0195] Since separate READ and WRITE data buses are provided, the high-speed operation based on the Harvard architecture described above is achieved. In this specification, the address bus (28-bit), READ data bus (32-bit), and WRITE data bus (32-bit) are sometimes collectively referred to as external buses to distinguish them from the internal bus and peripheral buses (1) to (3) shown in Figure 9.

[0196] Figure 10 illustrates the address spaces CS0 to CS7 selected by the chip select signals CS0 to CS7, and shows the address map for the performance control CPU 63 accessed via the bus state controller 66. First, each address space CS0 to CS7 is defined to a maximum of 64 MB (=0x4000000H=67108864).

[0197] As explained earlier, address spaces CS0 to CS7 refer to external memory for the CPU circuit 51, which can define memory types, including volatility, and data bus widths (8 / 16 / 32 bits). In this embodiment, as shown in Figures 9(b) and 10, the control memory (PROM) 53 is located in address space CS0, the voice control register SRG of the voice processor 27 is located in address space CS3, the internal registers and SRAM 39 of the clock circuit 38 are located in address space CS4, the external DRAM (DDR) 54 is located in address space CS5, the work memory 57 is located in address space CS6, and the VDP register RGij is located in address space CS7. The explanation of address spaces CS1 and CS2 is omitted.

[0198] Incidentally, as can be seen from Figure 10, the address space CS0 to CS7 is allocated not only in the address values ​​0x00000000 to 0x1FFFFFFF (cache-enabled space) but also in the address values ​​0x20000000 to 0x3FFFFFFF (cache-inactive space). This allows for the arbitrary selection of how to utilize the cache function by disabling the cache when address bit A29=1 based on the internal operation of the CPU circuit 51, and enabling the cache when address bit A29=0.

[0199] Therefore, in this embodiment, even if the value of bit A29 is either 1 or 0 among the 32 bits of address information (bits A31 to A30 and bits A28 to A0), if the values ​​of the remaining 31 bits are the same, it will refer to the same memory location and address. For example, whether you access address 0x18000000 or address 0x38000000, the same data will be read from address zero in work memory 57. Note that when accessing address 0x18000000, the read data is stored in the cache, and Figure 9(b) illustrates the access operation with the cache enabled / disabled.

[0200] However, it is also possible to disable cache operations for the instruction cache and / or operand cache based on a predetermined setting in the operation control register REG. However, in this embodiment, after power-on, cache operations are enabled for the instruction cache and operand cache, and then, if necessary, cache operations are disabled by accessing the cache invalidation space.

[0201] Continuing the explanation of the memory map in Figure 10, the memory space from address 0x40000000 onwards is an internal memory space where the bus state controller 66 does not function, and addresses 0xF0000000 to 0xFF3FFFFF are allocated to the cache address array space. In addition, addresses 0xFF400000 to 0xFFF7FFFF and 0xFFFC0000 to 0xFFFFFFFF are allocated to the built-in peripheral modules, specifically to the CPU circuit operation control register REG. The address range of the built-in RAM 59 is 0xFFF80000 to 0xFFFBFFFF.

[0202] Continuing the explanation of the internal configuration of the CPU circuit 51, the compare match timer CMT and the multifunction timer unit MTU are circuits that count external signals supplied to the CPU circuit 51, or count counting clocks obtained by multiplying or dividing the internal clock, and generate interrupt signals when the count result reaches a predetermined value. Although not particularly limited, in this embodiment, the multifunction timer unit MTU is used to generate a 1ms interrupt signal and a 20μS interrupt signal. Furthermore, the multifunction timer unit MTU is also used to realize a timing timer TM that measures the elapsed time after a CPU reset.

[0203] Next, the interrupt controller INTC is a circuit that receives internal interrupts from the VDP circuit 52, DMAC circuit 60, multifunction timer unit MTU, etc., as well as external interrupts such as IRQ_CMD, IRQ_SND, and IRQ_RCT, and activates interrupt processing (interrupt handlers) based on a predetermined priority. Here, IRQ_CMD is a command receive interrupt signal that should receive the control command CMD, IRQ_SND is a completion interrupt signal that indicates the voice processor 27 has finished its initialization sequence, and IRQ_RCT is an alarm interrupt signal.

[0204] In this embodiment, the interrupt priority is highest for the command receive interrupt IRQ_CMD, followed by 20μS interrupts → 1mS interrupts → interrupts from the VDP circuit (IRQ0, IRQ1, IRQ2, IRQ3) → DMAC interrupts → IRQ_SND → IRQ_RCT (see Figure 18(d)). Note that all of these are maskable interrupts, and the non-maskable interrupt NMI is output to the performance control CPU 63 when the reference clock is not output from the oscillator OSC2, as explained earlier.

[0205] In any interrupt handler, the register values ​​(32 bits each) of multiple CPU internal registers are automatically saved to one of the available register banks, RBi. Then, when a predetermined return instruction is executed at the end of the interrupt handler, the saved data is automatically restored to the corresponding internal register.

[0206] Next, the DMAC circuit 60 will be described. The DMAC circuit 60 in this embodiment is a circuit that, based on a predetermined setting value in a predetermined operation control register REG, repeatedly transfers data from the source to the destination in a predetermined DMA transfer mode, for a predetermined number of times at predetermined data transfer units. Multiple channels of DMAC0 to DMACn, each with the same internal configuration, are provided and can operate in parallel. However, a priority order is set (channel 0 > ... > channel n), and during parallel operation in channel arbitration mode, the operation of DMACi, which has higher priority, is prioritized by channel arbitration at a predetermined timing.

[0207] In an example of how the DMAC circuit 60 is utilized, such as in the embodiment where the serial output port SO is functioning (see the dashed line in Figure 10(a)), the operation control register REG of the CPU circuit 51 is specified with the starting address of the lamp / motor drive table (the starting value of the source address), the address of the input register of the serial output port SO (a fixed value of the destination address), the data transfer unit (8 bits), and the number of transfers. The DMAC circuit 60, upon receiving an operation start instruction from the predetermined operation control register REG, updates the source address and performs a DMA transfer of the drive data to the predetermined destination address. The system is configured to generate a DMAC interrupt (operation completion interrupt) once all DMA transfers are complete.

[0208] This point is almost the same in the embodiment where the DMAC circuit 60 issues the display list DL (Figures 25 and 29(c)). In other words, the performance control CPU 63 sets the starting address of the source (DL buffer BUF), the address of the destination (transfer port TR_PORT), the DMA transfer mode, the data transfer unit, the number of transfers, and other conditions in a predetermined operation control register REG of the CPU circuit 51. These points will be further described in relation to Figure 25.

[0209] Incidentally, generally speaking, DMA transfer modes can include a cycle steal transfer mode in which the DMA operation does not occupy the memory bus, such as releasing bus control rights in the middle of a unit operation (R operation / W operation) of DMA transfer; a burst transfer (pipeline transfer) mode in which the bus control rights are not released until a specified number of transfers are completed, such as by performing multiple R or W operations in succession; and a demand transfer mode in which the DMA operation continues as long as there is an active DMA transfer request (demand) from another device. However, the DMAC circuit 60 in this embodiment functions in a cycle steal transfer mode that provides at least one memory release period between the read access activation (R operation) and the write access activation (W operation) during DMA transfer, so as not to interfere with the operation of the performance control CPU 63.

[0210] Figure 11 is a diagram illustrating cycle-steal transfer operation (a1) and pipeline transfer (a2). As shown in Figure 11(a1), the DMAC circuit 60, which functions in cycle-steal transfer mode, operates with at least one cycle between the read access activation (R) and write access activation (W) of one data transfer, and during this idle cycle, the bus can be used by the performance control CPU 63. As is clear from the comparison between Figure 11(a1) and Figure 11(a2), in pipeline transfer, the bus is not released to the CPU until one cycle (one operand transfer) is completed, whereas in cycle-steal transfer mode, the bus is released to the CPU after each read access, so the CPU operation is not significantly delayed.

[0211] For example, in an embodiment where the DMAC circuit 60 is used when issuing the display list DL to the VDP circuit 52, the data transfer unit (1 operand) for one cycle is set to 32 × 2 bits, and while appropriately increasing the source address of the built-in RAM 59 where the display list DL is stored (by +8 for each operand transfer), a DMA transfer operation is performed to the transfer port register TR_PORT (see Figure 13) of the data transfer circuit 72, which is identified by a fixed address.

[0212] As described later, in this embodiment, the total data size is adjusted to a fixed value (for example, 4 × 64 = 256 bytes, or an integer multiple thereof) by adding the required number of NOP (no operation) commands to the display list DL. The issuance of the display list DL is completed by repeating a 32-bit × 2-operand transfer 32 times (or an integer multiple thereof). Even if the drawing circuit 76 executes a NOP command, it remains in a no operation state, and effectively no change occurs.

[0213] Furthermore, when classifying the operating modes with respect to DMA transfer conditions, generally, there are single-operand transfers (see Figure 11(b1)), continuous-operand transfers (see Figure 11(b2)), and nonstop transfers (see Figure 11(b3)).

[0214] Here, single-operand transfer refers to an operating mode in which, as shown in Figure 11(b1), a single operand is transferred repeatedly each time a DMA transfer request is given, and a DMA interrupt request is generated when the byte count, which counts the number of bytes transferred, reaches zero. Next, continuous-operand transfer refers to an operating mode in which, as shown in Figure 11(b2), DMA transfers are repeated in a single DMA request until the byte count reaches zero.

[0215] In these continuous operand transfers (b2) and single operand transfers (b1), channel arbitration is performed after each operand transfer is completed, and the transfer on the current channel continues provided there are no DMA requests on higher-priority channels (channel arbitration operation mode). Therefore, in this embodiment, the issuance of the display list DL to the VDP circuit and the DMA transfer of lamp drive data and motor drive data employ the single operand transfer method. Furthermore, during parallel operation, the optimal channel's DMACi is used so that, for example, channel arbitration is performed with the priority of motor data > display list DL > lamp data.

[0216] On the other hand, nonstop transfer is an operating mode in which channel arbitration is not performed, and as shown in Figure 11(b3), DMA transfer is continuously repeated in a single DMA request until the byte count becomes zero. In this embodiment, during the memory section initialization process at power-up (SP8 in Figure 16), programs and data are transferred via DMA using nonstop transfer.

[0217] Having explained the CPU circuit 51, the VDP circuit 52 will now be explained. The VDP circuit 52 is connected to a CGROM 55 that stores compressed data which constitutes the still images and video components of the image presentation, an external DRAM (Dynamic Random Access Memory) 54 with a storage capacity of approximately 4 Gbit, a main display device DS1, and a sub-display device DS2. The DRAM 54 is preferably composed of DDR3 (Double-Data-Rate3 SDRAM).

[0218] As shown in Figure 14(b), the DRAM 54 receives a DDR clock generated based on the oscillation output (40MHz) of the oscillator OSC2. Furthermore, the DRAM 54 in this embodiment has a built-in refresh counter, and the self-refresh function is enabled during initial setup (SP4 in Figure 16), so refresh control operation by the performance control CPU 63 is unnecessary.

[0219] While not particularly limited, in this embodiment, the CGROM55 is composed of a flash SSD (solid state drive) made of NAND flash memory with a storage capacity of approximately 62 Gbit, and is configured to acquire the necessary compressed data via serial transmission. Therefore, the problem of skew (difference in transmission speed for each bit of data) that inevitably occurs in parallel transmission is eliminated, enabling extremely high-speed transmission operation. While not particularly limited, in this embodiment, the CGROM55 is accessed at high speed using the HSS (High Speed ​​Serial) method compliant with SerialATA.

[0220] Regardless of whether or not the HSS method conforming to SerialATA is adopted, NAND flash memory is mechanically more stable and allows for faster access than hard disks. However, because it is a sequential access memory, it has problems with random access compared to DRAM and SRAM (Static Random Access Memory). Therefore, in this embodiment, a preload operation is performed in which a group of compressed data (CG data) is read into DRAM 54 prior to the drawing operation, thereby achieving smooth random access of CG data during the drawing operation. Incidentally, the access speed slows down in the order of built-in VRAM > external DRAM > CGROM.

[0221] The VDP circuit 52 comprises, in detail, a group of control registers 70 in which various operating parameters defining the operation of the VDP (Video Display Processor) can be set by the performance control CPU 63; a built-in VRAM (video RAM) 71 of about 48 MB used when generating image data to be displayed on the display devices DS1 and DS2; a data transfer circuit 72 that performs data transmission and reception between various parts of the chip and data transmission and reception with the outside of the chip; an index table IDXTBL that can identify the source and destination address information of the built-in VRAM 71; a preloader 73 that can perform a preload operation that reads the CGROM 55 prior to the drawing operation; a graphics decoder (GDEC) 75 that decodes (decodes and decompresses / unpacks) the compressed data read from the CGROM 55; a drawing circuit 76 that generates image data for one frame each of the display devices DS1 and DS2 by appropriately combining the still image data and video data after decoding (unpacking); a geometry engine 77 that generates a 3D image by appropriate coordinate transformation as part of the operation of the drawing circuit 76; and a component that reads the image data from the frame buffers FBa and FBb generated by the drawing circuit 76. The system is configured to include three display circuits (A / B / C) 74A to 74C capable of performing appropriate image processing in parallel, an output selection unit 79 that appropriately selects and outputs the output of the three display circuits 74, an LVDS unit 80 that converts the image data output by the output selection unit 79 into an LVDS signal, an SMC unit 78 capable of sending and receiving serial data, a CPUIF unit 81 that relays data transmission and reception with the CPUIF circuit 56, a CG bus IF unit 82 that relays data reception from the CGROM 55, a DRAMIF unit 83 that relays data transmission and reception with the external DRAM 54, and a VRAMIF unit 84 that relays data transmission and reception with the built-in VRAM 71 (see Figure 8(a)). An audio circuit SND is also built in.

[0222] Figure 8(b) illustrates the relationship between the CPUIF unit 81, the CG bus IF unit 82, the DRAMIF unit 83, and the VRAMIF unit 84, and the control register group 70, the CGROM 55, the DRAM 54, and the built-in VRAM 71. As shown in the figure, the CG data acquired from the CGROM 55 is transferred, for example, as preload data to the preload area of ​​the external DRAM 54 via the data transfer circuit 72 and the DRAMIF unit 83.

[0223] However, the preload operation described above is not mandatory, and the data transfer destination is not limited to the external DRAM 54, but may also be the built-in VRAM 71. Therefore, for example, in an embodiment where the preload operation is not performed, the CG data is transferred to the built-in VRAM 71 via the data transfer circuit 72 and the VRAMIF unit 84 (Figure 8(b)).

[0224] In this embodiment, the built-in VRAM 71 requires a decompression area for compressed data read from the CGROM 55, a frame buffer area for storing image data that identifies each of the W x H display pixels of the display device's ARGB information (32 bits = 8 x 4), and a Z buffer area for storing depth information for each display pixel. In ARGB information, A represents 8-bit alpha plane data, and RGB represents 8-bit data for the three primary colors.

[0225] Here, the aforementioned areas of the built-in VRAM 71 are accessed indirectly by the performance control CPU 63 based on various instruction commands (such as the texture and SPRITE commands mentioned above) written in the display list DL. However, it would be cumbersome to specify the destination address and source address of the built-in VRAM 71 each time for READ / WRITE access. Therefore, in this embodiment, during the initial processing after a CPU reset, a one-dimensional or two-dimensional logical address space (hereinafter referred to as the index space) necessary for the drawing operation is secured, and an index number is assigned to each index space, thereby enabling access based on the index number.

[0226] Specifically, after a CPU reset, the built-in VRAM 71 is divided into three main memory areas, and the necessary number of index spaces are allocated in each memory area. Then, an index table IDXTBL (see Figure 12(a)) is constructed that stores the index spaces and index numbers in association, thereby enabling subsequent operations based on the index numbers.

[0227] This index space may need to be (1) added to after initial processing, or conversely, (2) released. Therefore, a flag area FG is provided in the index table IDXTBL that can determine whether it is possible to perform the addition / release process when the CPU 63 controls the addition / release process, and whether the addition / release process has actually been completed. The built-in VRAM 71 is broadly divided into three types of memory areas: two AAC areas (a1, a2) described below, a page area (b), and an arbitrary area (c). The index table IDXTBL is divided into three sections corresponding to these three types of memory areas (a1, a2), (b), and (c) (Figure 12(a)). As shown in the figure, in this embodiment, the first AAC area (a1) and the second AAC area (a2) are allocated as the AAC area (a), but this is not particularly limited, and either one alone may suffice. In the following explanation, the first and second AAC regions (a1, a2) may be collectively referred to as AAC region (a).

[0228] In this embodiment, the built-in VRAM 71 is configured to be divided into (a) an AAC area in which an index space and its index number are automatically assigned by internal processing and which has a memory cache function, (b) a page area in which an index space can be allocated in a range of integer multiples thereof, with a two-dimensional space of, for example, 4096 bits × 128 lines as the unit space, and (c) an arbitrary area in which the starting address (space starting address) STx and horizontal size Hx can be arbitrarily set (see Figure 12(b)). However, in order to facilitate the internal operation of the VDP circuit 52, the space starting address STx of the index space arbitrarily set in the arbitrary area (c) must have its lower 11 bits set to 0 and be in units of a predetermined number of bits (2048 bits = 256 bytes).

[0229] After the CPU reset, the maximum required address space for each region and the starting address of the region (lower 11 bits = 0) are defined, and the AAC region (a1), the second AAC region (a2), and the page region (b) are allocated, with the remaining memory region becoming the arbitrary region (c). To facilitate the internal operation of the VDP circuit 52, the maximum value of the address space for the AAC region is defined in units of 2048 bits, and the maximum value of the address space for the page region is set to an integer multiple of the aforementioned 4096-bit × 128-line unit space.

[0230] Next, the required number of index spaces are set in each of the allocated regions (a1, a2), (b), and (c). Note that when using the arbitrary region (c), in order to facilitate the internal operation of the VDP circuit 52, the horizontal size Hx of the index space handling two-dimensional data can be arbitrarily set as a multiple of 256 bits, while its vertical size is fixed (for example, 2048 lines).

[0231] In any case, the first and second AAC regions (a1, a2) are automatically assigned index spaces and index numbers by the VDP circuit 52. For example, if the decoding destination is specified as the AAC region (a) using the SETINDEX command of the texture setting commands, then the TXLOAD (texture load) command, which reads CG data from the CGROM 55, only needs to specify the source address of the CGROM 55 and the horizontal and vertical sizes after decompression (decoding). Therefore, in this embodiment, the decoding destination for still images (textures) of characters that appear temporarily during preview sequences, etc., and I-stream videos is set to the AAC region (a).

[0232] Since each of these AAC areas (a) is equipped with a memory cache function, for example, if the same texture from CGROM55 is read into the AAC area (a) multiple times, the decoded data cached in the AAC area (a) can be used from the second time onward, suppressing unnecessary READ access and decoding processes. However, if the AAC area (a) is exhausted, the old data is automatically destroyed. Therefore, in this embodiment, when using the AAC area (a), the first AAC area (a1) is used as a general rule, and only specific textures that are used repeatedly are acquired in the second AAC area (a2).

[0233] Examples of textures that are used repeatedly include characters that appear repeatedly during a specific preview sequence, and background images when constructing a background screen using still images. In such cases, the SETINDEX command of the texture setting commands is used to set the decoding destination to the second AAC area (a2), and after decoding textures such as characters and background images into the second AAC area (a2) using the TXLOAD command, the decoding result is protected by not using the second AAC area (a2).

[0234] Then, by specifying the decoding destination as the second AAC area (a2) using the SETINDEX command and executing the same TXLOAD command to reacquire the already acquired texture, the acquired texture will be cache-hit, thus eliminating the time required for READ access to CGROM55 and the decoding process. As will be described later, this cache-hit function is also effective for preloaded data that has been pre-fetched into the preload area, but the significance lies in the fact that the preloaded data that is cache-hit in the preload area is compressed data before decoding, whereas the data that is cache-hit in the AAC area is decompressed data after decoding.

[0235] Incidentally, while texture generally refers to the feel or texture of an object's surface, in this specification, it is used as a concept that includes not only sprite image data that makes up still images, image data that makes up a single frame of a video, and image data that is applied to drawing primitives such as triangles and rectangles, but also decoded image data. Furthermore, when copying image data within the built-in VRAM71 (hereinafter referred to as "moving" for convenience), the source image data is set as a texture using the SETINDEX command of the texture setting commands, and then the SPRITE command is executed.

[0236] When the SPRITE command is executed, the source image data is formally drawn to the virtual rendering space shown in Figure 12(c). However, if the correspondence between the rendering area in the virtual rendering space that is actually drawn to the display device and the index space that serves as the frame buffer is set in advance using environment setting commands (SETDAVR, SETDAVF) or texture setting commands (SETINDEX), then, for example, when the SPRITE command is used to draw to the virtual rendering space, the source image data will be drawn to the predetermined index space (frame buffer) (see Figure 12(c)).

[0237] In any case, in this embodiment, the built-in VRAM 71 is broadly divided into an AAC area (a1, a2), a page area (b), and an arbitrary area (c), and an appropriate number of index spaces can be allocated to each, and each index space is identified by an independent index number for each area (a), (b), and (c). The index number is, for example, 1 byte in length, and for the page area (b) and arbitrary area (c) (excluding the AAC area (a) which is automatically assigned by the internal circuit), the performance control CPU 63 can freely assign index numbers in the range of 0 to 255.

[0238] Therefore, in this embodiment, as shown in Figure 12(a), a pair of frame buffers FBa are reserved in an arbitrary area (c) for the display device DS1, and index numbers 255 and 254 are assigned to both sides of the double buffer structure. That is, index spaces 255 and 254 are reserved as frame buffers FBa for the main display device DS1, which are switched on and off in a toggle manner. Although not particularly limited, these index spaces 255 and 254 have a horizontal size of 1280, corresponding to the number of horizontal pixels of the display device DS1. Since each pixel is identified by 32 bits of ARGB information, a horizontal size of 1280 means 32 × 1280 = 40960 bits (a multiple of 256 bits).

[0239] Furthermore, for the display device DS2, another pair of frame buffers FBb are reserved in an arbitrary area (c), and index numbers 252 and 251 are assigned to both sides of the double buffer structure. That is, index spaces 252 and 251 are reserved as frame buffers FBb for the sub-display device DS2. These index spaces 252 and 251 correspond to the number of horizontal pixels of the display device DS2, and have a horizontal size of 480. In this case as well, each pixel is identified by 32 bits of ARGB information, so a horizontal size of 480 means 32 × 480 = 15360 bits (a multiple of 256 bits).

[0240] Note that securing the frame buffers FBa and FBb in the arbitrary area (c) means that the arbitrary area (c) can be set to any horizontal size as a multiple of 32 bytes (= 256 bits = 8 pixels). As described above, if it is made to match the horizontal pixel numbers of the display devices DS1 and DS2, there will be no waste in the secured area. On the other hand, in the page area (b), only a horizontal / vertical size that is an integer multiple of the unit space of 128 pixels × 128 lines can be set.

[0241] However, the two-dimensional index space secured in the arbitrary area (c) has a fixed vertical size (for example, 2048 lines). Therefore, in the frame buffer FBa, only the area with a horizontal size of 1280 × a vertical size of 1024 becomes the valid data area for the main display device DS1. The same applies to the sub-display device DS2. In the frame buffer FBb, only the area with a horizontal size of 480 × a vertical size of 800 becomes the valid data area for the sub-display device DS2 (see FIGS. 12(c) and 22(e)).

[0242] This point will be further described later. In any case, the frame buffers FBa and FBb are used alternately by each double buffer (255 / 254, 252 / 251) as the drawing area for the drawing circuit 76, and are also used alternately by each double buffer (255 / 254, 252 / 251) as the display area for the display circuits 74A and 74B. Note that in this embodiment, since a Z-buffer for storing the depth information of the display pixels is not used, there is a missing number (253). However, when a Z-buffer is used, the index spaces 253 and 250 with index numbers 253 and 250 in the arbitrary area (c) become the Z-buffers for the display device DS1 and the display device DS2.

[0243] Furthermore, in this embodiment, when allocating additional index space (memory area) in the arbitrary area (c) where frame buffers FBa and FBb are allocated, an index number starting from 0 is assigned. Although not limited in any way, in this embodiment, an index space (0) is allocated in the arbitrary area (c) as a work area for preview effects that make performance images composed of characters and other still images appear on a part of the display screen in an appropriate rotational position as needed.

[0244] However, the use of a work area is not mandatory, and instead of the arbitrary area (c), an index space may be allocated in the page area (b) as a work area. If the page area (b) is used, the horizontal size will be 12 8 Since it can secure an index space with dimensions that are multiples of a square unit space of (=4096 bits) × vertical size 128, it is suitable for handling small animation images.

[0245] In this embodiment, the background image is also composed of video, and the image effects are realized almost entirely by video. In particular, during variable effects, a large number of videos (usually 10 or more) are drawn simultaneously. These videos are all stored in the CGROM 55 in a compressed state as a series of video frames, but they are divided into I-stream videos, which consist only of I-frames, and IP-stream videos, which consist of I-frames and P-frames. Here, an I-frame (Intra coded frame) means a frame that compresses the input image as is, independently of other screens. On the other hand, a P-frame (Predictive coded frame) means a frame that performs forward predictive coding, and requires an I-frame or P-frame located in the past in time.

[0246] Therefore, in this embodiment, IP stream video is expanded into the page area (b) rather than the AAC area (a) where there is concern about the corruption of old data. That is, a large number of index spaces (IDX0~IDX) are placed in the page area (b), which can secure an index space with dimensions that are a multiple of 128 horizontal x 128 vertical sizes. NBy securing a space, a series of video frames are decoded using the same index space IDXi corresponding to each video MVi. That is, video MV1 is expanded into index space IDX1, video MV2 is expanded into index space IDX2, and so on, with each video MVi being expanded into index space IDXi.

[0247] To explain video MVi in more detail, the SETINDEX command is used to pre-specify that "the decoding destination for IP stream video MVi is the index space (i) of index number i in the page area (b)," and then the TXLOAD command is executed to obtain one frame of the IP stream video MVi.

[0248] Then, the video frame (any of a series of video frames) on the CGROM55 identified by the TXLOAD command is first acquired in the AAC area (a), and then the acquired video frame is decoded and expanded in the index space (i) of the page area (b) by the GDEC (graphics decoder)75, which is automatically activated.

[0249] On the other hand, in this embodiment, I-stream videos are treated the same as still images, and the SETINDEX command is used to specify that "the decoding destination for I-stream video MVj is the first AAC area (a1)," and the TXLOAD command is executed. As a result, the video frames are acquired in the first AAC area (a1), and then GDEC75, which is automatically launched, expands the decoded data into the first AAC area (a1). As explained earlier, the index space of the AAC area (a) is automatically generated, so it is not necessary to specify the index number. Note that the expansion volume required for the index space, that is, the horizontal and vertical sizes of the decoded texture (video frame), is determined by the TXLOAD command regardless of whether the expansion destination is the AAC area (a) or the page area (b).

[0250] Incidentally, IP stream video MVi and I stream video MVj generally consist of N video frames (I-frames and P-frames). Therefore, the TXLOAD command specifies, for example, the Source address of the CGROM 55 where the k-th (1≦k≦N) video frame is stored, and the horizontal and vertical sizes after expansion. In an embodiment where still images are rarely used, although not limited in any way, most of the 48MB address space of the built-in VRAM 71 (about 30MB) is allocated to the page area (b). Furthermore, in an embodiment where still images are rarely used, only the first AAC area (a1) is reserved as the AAC area, the second AAC area (a2) is not reserved, and the cache hit function of the AAC area described above is not utilized.

[0251] Furthermore, to speed up the decoding process of compressed video data, it is conceivable to provide a dedicated GDEC (graphics decoder) circuit. If the dedicated GDEC circuit is built into the VDP circuit 52, then in the decoding process of compressed video data consisting of N compressed video frames, it will be sufficient to instruct the GDEC circuit with the starting address of the compressed video data, eliminating the need to specify the starting address for each of the N compressed video frames.

[0252] However, incorporating multiple dedicated GDEC circuits for each compression algorithm would further complicate the internal configuration of the VDP circuit 52. Therefore, in this embodiment, software GDEC is used, and decoding of IP stream video, I stream video, still images, and other data such as alpha values ​​is achieved through software processing corresponding to each compression algorithm. The difference in processing time between hardware processing and software processing is not a major issue; the processing time that matters is primarily the access (READ) time from CGROM 55.

[0253] Next, returning to Figure 8(a), the data transfer circuit 72 is a circuit that performs DMA (Direct Memory Access) data transfer operations between the resources (storage medium) inside the VDP circuit and the external storage medium, using the source port and destination port respectively. Figure 13 is a block diagram showing the internal configuration of this data transfer circuit 72 along with related circuit configurations.

[0254] As shown in Figure 13, the data transfer circuit 72 is configured to send and receive data to and from the CGROM 55, DRAM 54, and built-in VRAM 71 via the integrated connection bus ICM, which has router functionality. The CGROM 55 and DRAM 54 are accessed via the CG bus IF unit 82 and the DMAMIF unit 83.

[0255] Meanwhile, the CPU circuit 51 issues a display list DL to the drawing circuit 76 and the preloader 73 via the transfer port register TR_PORT built into the data transfer circuit 72. The CPU circuit 51 and the data transfer circuit 72 are connected bidirectionally, but when issuing the display list DL, the transfer port register TR_PORT functions as a data writing port that accepts one unit of data that constitutes the display list DL. The write unit (one unit data length) of the transfer port register TR_PORT is 32 bits, corresponding to the FIFO structure of the CPU bus control unit 72d.

[0256] As shown in the diagram, the performance control CPU 63 can access the transfer port register TR_PORT via the CPUIF unit 81 using WRITE, while when the DMAC circuit 60 is utilized, the DMAC circuit 60 directly accesses the transfer port register TR_PORT using WRITE. The series of instruction commands written to the transfer port register TR_PORT (i.e., the sequence of instruction commands that constitute the display list DL) are automatically stored in 32-bit units in the CPU bus control unit 72d, which has a built-in FIFO buffer with a FIFO structure (32 bits x 130 stages).

[0257] Furthermore, this data transfer circuit 72 performs data transmission and reception operations on a 3-channel ChA to ChC transmission path, and includes a ChA control circuit 72a (N=130 stages) having a FIFO buffer with a FIFO structure (64 bits × N stages), a ChB control circuit 72b (N=1026 stages), and a ChC control circuit 72c (N=130 stages).

[0258] The instruction command sequence (display list DL) stored in the CPU bus control unit 72d is then transferred to the drawing circuit 76 or the preloader 73 based on the setting value in the data transfer register RGij (a type of various control register 70) by the performance control CPU 63. As indicated by the arrows, the display list DL is configured to be transferred from the CPU bus control unit 72d to the drawing circuit 76 via the FIFO buffer of the ChB control circuit 72b, and then to the preloader 73 via the FIFO buffer of the ChC control circuit 72c.

[0259] In this embodiment, the ChB control circuit 72b and the ChC control circuit 72b are specialized for the transfer operation of the display list DL. The data stored in the FIFO buffer of the CPU bus control unit 72d is transferred as part of the display list DL to the drawing circuit 76 or the display list analyzer of the preloader 73 via the FIFO buffer of either the ChB control circuit 72b or the ChC control circuit 72c.

[0260] Then, the drawing circuit 76 starts drawing operations based on the transferred display list DL. Meanwhile, the preloader 73 performs the necessary preload operations based on the transferred display list DL. The preload operations pre-read the CG data from the CGROM 55 into the preload area allocated in the DRAM 54, and a display list DL with the texture source address changed (hereinafter referred to as the rewritten list DL') with respect to commands such as TXLOAD is saved in the DL buffer area BUF' allocated in the DRAM 54.

[0261] On the other hand, the ChA control circuit 72a and the connection bus access arbitration circuit 72e function for data transfer between storage media such as CGROM 55, DRAM 54, and built-in VRAM 71. In addition, the IDXTBL access arbitration circuit 72f functions when accessing the built-in VRAM 71, which requires address information from the index table IDXTBL. Specifically, the ChA control circuit 72a functions, for example, when (a) transferring compressed data from CGROM 55 to the built-in VRAM 71, (b) preloading (reading ahead) compressed data from CGROM 55 and transferring it to the external DRAM 54, or (c) transferring pre-read data from the preloaded area to the built-in VRAM 71.

[0262] Here, the ChA control circuit 72a is configured to operate in parallel with the ChB control circuit 72b and the ChC control circuit 72c, and the operations (a) to (c) described above can be executed in parallel with the display list DL issuance operation (ST8 in Figure 22, PT11 in Figure 27) and the rewrite list DL' transfer operation (PT10 in Figure 27). In addition, the ChB control circuit 72b and the ChC control circuit 72c can also be executed simultaneously, for example, the processing of step PT10 in Figure 27 when the ChB control circuit 72b is functioning and the processing of step PT11 when the ChC control circuit 72c is functioning can be executed in parallel. However, since there is only one transfer port register TR_PORT, when either one (72b / 72c) is using the transfer port register TR_PORT, the other (72c / 72b) cannot access the transfer port register TR_PORT.

[0263] During the operation of the ChA control circuit 72a, the connection bus access arbitration circuit 72e arbitrates (Arbitration) the data transmission with each memory element (CGROM55, DRAM54) via the integrated connection bus ICM. On the other hand, the IDXTBL access arbitration circuit 72f arbitrates the data communication with the built-in VRAM 71 by controlling the ChA control circuit 72a based on the index table IDXTBL. In the case of the embodiment where the pre-loader 73 functions, the rewrite list DL' stored in the DL buffer area BUF' of the DRAM 54 is transferred to the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b (see FIG. 28(b)).

[0264] As described above, the data transfer circuit 72 of this embodiment realizes high-speed data transfer between a data transfer source arbitrarily selected from various memory resources (Resource) and a data transfer destination arbitrarily selected from various memory resources (Resource). As confirmed from FIG. 13, the memory resources in which the data transfer circuit 72 functions include not only the built-in VRAM 71 but also external devices via the CPUIF unit 56, the CG bus IF unit 82, and the DRAMIF unit 83.

[0265] And the data transfer amount with the external device in which the ChA control circuit 72a functions, such as the amount of data to be acquired at one time from the CGROM55 (memory sequential READ), is huge compared to the case of the display list DL in which the ChB control circuit 72b and the ChC control circuit 72c function, and the data transfer amounts are greatly different from each other.

[0266] Here, it is conceivable to configure the unit data amount and total data transfer amount for these various data transfers to be finely configurable, but this would complicate the control operations within the VDP and hinder smooth transfer operation. Therefore, in this embodiment, the minimum data amount Dmin for data transfer is uniquely defined, and the total data transfer amount is limited to an integer multiple of the minimum data amount DTmin, thereby achieving high-speed and smooth data transfer operation. Although not particularly limited, in the data transfer circuit 72 of this embodiment, the minimum data amount Dmin (unit data amount) is set to 256 bytes, and the total data transfer amount is limited to an integer multiple of this.

[0267] Therefore, the instruction command sequence of the display list DL, which is accumulated in the FIFO buffer of the CPU bus control unit 72d every 32 bits, is transferred to the ChB control circuit 72b and the ChC control circuit 72b when its total amount reaches the minimum data amount Dmin, and is accumulated in their respective FIFO buffers.

[0268] The display list DL consists of a series of instruction commands, but in this embodiment, corresponding to the write unit (32 bits) of the transfer port register TR_PORT, the display list DL consists only of instruction commands whose command length is N times a 32-bit integer (N>0). Therefore, the drawing circuit 76 and preloader 73, which receive the instruction commands of the display list DL via the data transfer circuit 72, can quickly and smoothly start command analysis processing (DL analyze). Note that the command length of N times a 32-bit integer does not necessarily mean that all of them are significant bits; it means that N times a 32-bit integer includes non-significant bits (Don't care bits).

[0269] Next, the preloader 73 will be explained. As briefly explained earlier, the preloader 73 is a circuit that interprets the display list DL transferred from the data transfer circuit 72 (ChC control circuit 72b) and transfers the CG data on the CGROM 55 that the TXLOAD command refers to to the preload area of ​​the DRAM 54 in advance. The preloader 73 also stores a rewritten list DL' in the DL buffer BUF' of the DRAM 54, in which the reference destination of the CG data for this TXLOAD command has been rewritten to the address after the transfer. Note that the DL buffer BUF' and the preload area are allocated in advance during the initial processing after the CPU reset (SS3 in Figure 21).

[0270] The rewrite list DL' is then transferred to the display list analyzer (DL Analyzer) of the drawing circuit 76 via the connection bus access arbitration circuit 72e and the ChB control circuit 72b of the data transfer circuit 72 when the drawing operation of the drawing circuit 76 begins. The drawing circuit 76 then performs the drawing operation based on the rewrite list DL'. Consequently, CG data that should originally be obtained from the CGROM 55 based on a TXLOAD command, etc., is obtained from the preload area of ​​the DRAM 54 as preloaded data that has been pre-read into the preload area. In this case, the preloaded data can be reused repeatedly unless it is overwritten and erased, and preloaded data that has been cached in the preload area is reused repeatedly.

[0271] In this embodiment, since the preload area is set in the external DRAM 54 which has sufficient memory capacity, the cache hit function described above functions effectively. Furthermore, because the external DRAM 54 has a large memory capacity, it is possible to perform multiple preloads, for example, by preloading CG data for multiple frames at once. In other words, regarding the operation period of the preloader 73, multiple preloads are realized by appropriately setting the operation period of a series of preload operations, including the pre-reading operation of CG data, within an integer multiple of the operation period δ of the VDP circuit 52 during intermittent operation.

[0272] However, for convenience, the following description will explain an embodiment without multiple preloads, so the preloader 73 in this embodiment will complete the preload operation for one frame during one operating cycle (δ). As will be described later with respect to Figure 22, in this embodiment, the operating cycle δ of the VDP circuit 52 during intermittent operation is 1 / 30 seconds, which is twice the period of the vertical synchronization signal of the display device DS1.

[0273] Next, the drawing circuit 76 sequentially analyzes the instruction command sequences of the display list DL and rewrite list DL' transferred via the data transfer circuit 72, and works in cooperation with the graphics decoder 75 and geometry engine 77 to draw an image for one frame of each display device DS1 and DS2 into the frame buffer formed in the VRAM 71.

[0274] As described above, in the embodiment in which the preloader 73 functions, the CG data referenced in the rewrite list DL' is not the CGROM 55, but the preload area set in the DRAM 54. Therefore, sequential access to the CG data that occurs during drawing by the drawing circuit 76 can be performed quickly, and even high-resolution videos with rapid movement can be drawn without problems. In other words, according to this embodiment, complex and advanced image effects can be performed while utilizing an inexpensive SATA module as the CGROM 55.

[0275] Incidentally, regardless of whether the preloader 73 is activated or not, even if data corruption occurs during the transfer of the display list DL or the rewrite list DL', the drawing circuit 76 cannot detect it. Also, due to the influence of noise or other factors, the drawing circuit 76 may freeze, and the READ / WRITE access to the built-in VRAM 71 may be abnormally stopped. Therefore, in this embodiment, the drawing circuit 76 is configured to generate a drawing abnormal interrupt if it detects an unreasonable instruction command (a bit sequence that cannot be analyzed) or if there has been no READ / WRITE access to the built-in VRAM 71 for a certain period of time (drawing abnormal interrupt is enabled). This point will be discussed later with respect to Figure 22(d).

[0276] Next, as explained with respect to Figure 12, the frame buffer FB allocated in the arbitrary area (c) of the VRAM 71 is a double buffer divided into a drawing area and a reading area, and the two areas are used alternately, switching their purpose. In this embodiment, since two display devices DS1 and DS2 are connected, two frame buffers FBa / FBb are allocated as shown in Figure 12. Therefore, the drawing circuit 76 draws image data for one frame into the drawing area (writing area) of the frame buffer FBa for display device DS1, and also draws image data for one frame into the drawing area (writing area) of the frame buffer FBa for display device DS2. When image data is written to the drawing area, the display circuit 74 reads the image data from the other reading area (display area) and outputs it to each display device DS1 and DS2.

[0277] The display circuit 74 reads image data from frame buffers FBa and FBb, performs final image processing, and then outputs the image (see Figure 14(a)). Final image processing includes, for example, scaling processing by a scaler to enlarge / reduce the image, subtle color correction processing, and dithering processing to minimize the quantization error of the entire image. The digital RGB signal (24 bits in total) that has undergone these image processing steps is then output, usually along with the horizontal sync signal HS and the vertical sync signal VS.

[0278] As shown in Figure 14(a), this embodiment is provided with three display circuits A / B / C that perform the above operations in parallel. Each display circuit 74A to 74C reads image data from its corresponding frame buffers FBa / FBb / FBc and performs the final image processing described above. However, in this embodiment, since there are two display devices, the frame buffer FBc is not allocated, and display circuit 74C does not function.

[0279] Here, examining the specifications of the main display device DS1, it is necessary for the main display device DS1 to receive adjacent odd-numbered pixels (ODD) and even-numbered pixels (EVEN) in the left-right direction through separate LVDS (Low Voltage Differential Signaling) transmission paths at the receiving unit RV (RVa + RVb). Furthermore, the operating clock frequency CK of the main display device DS1 must be around 40-70MHz (typical value 54MHz), and the horizontal / vertical waiting times WTh / WTv must be set so that (WTh + 640) × (WTv + 1024) / 54MHz ≈ 1 / 60 seconds. In addition, at the timing of outputting image data (ODD / EVEN signals) to the main display device DS1, an active-level data validity signal ENAB must be output.

[0280] Therefore, the display circuit 74A needs to output a signal that satisfies all of the above specifications. Figures 15(a) to 15(e) illustrate the various signals output from the display circuit 74A. First, it is necessary to determine the frequency of the dot clock (LVDS clock) DCK. In this embodiment, the main display device DS1 is operated with an operating clock CK of a typical value of 54 MHz, so correspondingly, the design dot clock DCK (in the VDP circuit 52) ​​is set to 108 MHz (= 54 × 2).

[0281] This is because, in a display panel LCD with 1280 horizontal dots and 1024 vertical lines (see Figure 15(f)), two adjacent pixels are processed simultaneously in synchronization with the 54MHz operating clock CK, which is essentially equivalent to operating with a 108MHz dot clock DCK.

[0282] Then, various operation parameters that define the operation of the display circuit 74A are defined based on a dot clock DCK with a frequency of 108 MHz. First, it is necessary to set the horizontal / vertical standby times WTh / WTv so that (WTh + 640) × (WTv + 1024) / 54 MHz ≒ 1 / 60 second. However, as operation parameters WTh, WTv for the display circuit 74A, it is necessary to satisfy (WTh + 1280) × (WTv + 1024) / 108 MHz ≒ 1 / 60 second.

[0283] Also, regarding the horizontal / vertical standby times WTh / WTv, it is necessary to consider the allowable range in the specifications of the display device DS1. Therefore, in this embodiment, the horizontal standby time WTh is counted with a dot clock DCK of 108 MHz and set to 382 clocks, and the vertical standby time WTv is set to 59 lines. Therefore, the time required for updating an image for one frame is (382 + 1280) × (59 + 1024) / 108 MHz = 16.666 mS, and the frame rate FR (Frame Rate) becomes 1 / 60 second.

[0284] This relationship defines the update period FR [seconds] of the display device DS1. Using the frequency F of the dot clock DCK, the number of cycles THc of horizontal synchronization, and the number of lines TVl of vertical synchronization described later, FR = THc × TVl / F dot results. Here, if the update period FR is too long, there is a risk of abnormalities such as flicker. On the other hand, if the update period FR is too short, the display device cannot execute normal update processing. Therefore, it should be defined within the range of 0.95 / 60 < FR [seconds] < 1.05 / 60. dot

[0285] ​In response to this setting, the data valid signal ENAB is at a low level during the standby time WTh (=382 / 108MHz) corresponding to 382 clocks in the image update operation of each line, and then at an active level (H) during the active section (=1280 / 108MHz) corresponding to 1280 clocks (Figure 15(c)). As shown in Figures 15(d) and 15(e), during the active section of the data valid signal ENAB, image data is output so that the image update operation is completed for each of the 1280 dots in one line in a predetermined time (11.85μS = 1280 / 108MHz). In other words, 1280 pixel data is output in synchronization with the 1280 dot clocks DCK. The display device DS1 has a gradation of 2 8 ×2 8 ×2 8 Since a full-color image is displayed, the pixel data for one pixel is 3 x 8 bits long.

[0286] Incidentally, in this embodiment, although not required by the main display device DS1, it outputs a vertical synchronization signal VS and a horizontal synchronization signal HS. The vertical synchronization signal VS is output within the vertical standby time WTv, and the horizontal synchronization signal HS is output within the horizontal standby time WTh. For ease of understanding, Figures 15(a) and 15(b) show the respective operating cycles. Also, in Figure 15(f), circles are shown at the top left and bottom right corners of a rectangular frame specified by TH×TV (=1083×1662 clock), labeled "Start of display operation" and "End of display operation." These circles represent the "V blank start," which defines the operating cycle of the display circuit 74A, which starts every 1 / 60 second. Since the 1083×1662 clock that defines the display operation coincides with 1 / 60 second, the elapsed time from "Start of display operation" to "End of display operation" (operating cycle of the display circuit 74A) is 1 / 60 second. The "V-blank start" will be explained later based on Figure 22.

[0287] Returning to Figure 14 and continuing the explanation, the output selection unit 79 of the embodiment divides the output signal of the display circuit 74A into a dual-link that divides the 108MHz dot clock DCK by two, and transmits them to the LVDS unit 80a and the LVDS unit 80b respectively (see Figures 14(a) and 5). Then, each LVDS unit 80a and 80b converts the image data (a total of 24 bits of digital RGB signal) into first and second LVDS signals, adds a pair that transmits a clock signal (54MHz = 108 / 2) to these, and outputs a total of five pairs of differential signals LVDS1 and LVDS2 to the main display device DS1 via two paths (see Figures 14(a) and 4).

[0288] As explained earlier, in the main display device DS1, the ODD signal for one pixel and the EVEN signal for an adjacent pixel are processed at the same time. Therefore, the effective operating clock frequency CK matches the 108MHz dot clock DCK output by the display circuit 74A.

[0289] The above describes the display circuit 74A which generates images to be transmitted to the main display device DS1, but the display circuit 74B generates image data to be transmitted to the sub-display device DS2. The digital RGB signal output by the display circuit 74B is supplied to the digital RGB unit 80c via the output selection unit 79 and transmitted to the sub-display device DS2 along with the vertical synchronization signal VS and the horizontal synchronization signal HS.

[0290] Furthermore, along with the synchronization signals VS and HS, the data validity signal ENAB is also transmitted via the digital RGB section 80c. However, these signals are transmitted as continuous signals, not discrete values ​​as in the case of an LVDS transmission line (see Figure 14(a)).

[0291] In this embodiment, each display circuit 74A to 74B is equipped with underrun counters URCNTa to URCNTc that count underrun errors, where the generation of display data did not keep up with the display timing (see Figure 15). The counter values ​​of these underrun counters URCNTa to URCNTc are configured to be automatically incremented for each VBLANK when an underrun error occurs.

[0292] Next, the SMC unit 78 (Serial Management Controller) is a composite controller that incorporates both an LED controller and a motor controller. It outputs LED drive signals and motor drive signals to the LED / Motor driver (a driver IC with a built-in shift register) mounted on an external board, synchronized with the clock signal, while also being configured to output latch pulses at appropriate timings.

[0293] Regarding the internal circuitry and operation of the VDP circuit 52 described above, the operations that the internal circuitry should perform are defined by the operation parameters (setting values) that the performance control CPU 63 sets in the control register group 70, and the execution state of the VDP circuit 52 can be determined by reading the operation status values ​​of the control register group 70. The control register group 70 refers to a number of VDP registers RGij mapped to an address space of about 1 MB (0 to FFFFFH) on the memory map of the performance control CPU 63, and the performance control CPU 63 performs WRITE (setting) operations of operation parameters and READ operations of operation status values ​​via the CPUIF unit 81 (see Figure 8(b)).

[0294] The control register group 70 (VDP register RGij) includes a "system control register" where initial settings related to system operations such as interrupt operations are written; an "index table register" which determines the AAC area (a) and page area (b) in the built-in VRAM and is related to constructing or modifying the index table IDXTBL; a "data transfer register" where settings related to data transfer processing by the data transfer circuit 72 between the performance control CPU 63 and the internal circuit of the VDP circuit 52 are written; a "GDEC register" which identifies the execution status of the graphics decoder 75; a "drawing register" where setting values ​​related to instruction commands and the drawing circuit 76 are written; a "preloader register" where setting values ​​related to the operation of the preloader 73 are written; a "display register" where setting values ​​related to the operation of the display circuit 74 are written; an "LED control register" where setting values ​​related to the LED controller (SMC unit 78) are written; a "motor control register" where setting values ​​related to the motor controller (SMC unit 78) are written; and a "sound control register SRG" where setting values ​​related to the sound circuit SND are written. However, this embodiment does not utilize the audio circuit SND.

[0295] In any case, in the following explanation, one or more registers RGij included in the control register group 70 may be referred to by the individual names described above, or collectively as VDP register RGij. In either case, the performance control CPU 63 controls the internal operation of the VDP circuit 52 by writing appropriate setting values ​​to predetermined VDP register RGij. Specifically, the performance control CPU 63 realizes predetermined image effects based on the display list DL, which is updated at appropriate time intervals, and the setting values ​​to predetermined VDP register RGij. In this embodiment, the performance control CPU 63 is also responsible for lamp effects and motor effects, so VDP register RGij also includes LED control registers and motor control registers.

[0296] Next, we will explain the unified control operation of image effects, sound effects, motor effects, and lamp effects, which are realized by the composite chip 50 incorporating the CPU circuit 51 and VDP circuit 52 described above.

[0297] In this embodiment, the operation of the composite chip 50 is initiated by a power-on reset operation due to power-up or abnormal reset (see Figure 16(a)), followed by initial setup processing (SP1 to SP9) by the initial setup program (boot program) Pinit, and then transitioning to the main control processing (SP10) by the performance control program Main and the interrupt processing program (vector handler) Vopt. The processing content of the introductory part of the main control processing is shown in Figure 18(a), and the processing content of the main body is shown in Figure 22(a). Note that the processing of step SP27 in Figure 18 does not include the processing of steps SS1 to SS3 in Figure 21(a).

[0298] Based on the above, the power-on reset operation will be explained using Figure 16(a). When the system reset signal SYS is maintained at a low level for a predetermined period (assertion period), such as when the power is turned on, all operation control registers REG and all VDP registers RGij are automatically set to predetermined default values.

[0299] Then, when the system reset signal SYS changes to the H level (negate level) (see timing T1 in Figure 6(d)), in this embodiment, the timing timer TM (Figure 9(a)) is started to measure the elapsed time after the CPU reset (SP1). In addition, 32 bits of data from the first address of the address space CS0 are set to the program counter PC of the performance control CPU 63, and the following 32 bits of data are set to the stack pointer SP (SP1). Note that in Figures 10 and 17(c), the first memory region that stores the initial values ​​of the program counter PC and the stack pointer SP is referred to as the vector table VECT.

[0300] As shown in Figure 16(b), the vector table VECT stores corresponding vector numbers that identify priority and interrupt factors, along with address information. A smaller vector number indicates a higher priority. For example, vector number 11 is an unmaskable interrupt (NMI), and its address information stores the starting address of the interrupt handler program executed when an NMI interrupt occurs. Similarly, vector number 64 is an internal interrupt from the VDP (VDP_IRQ0), and its address information stores the starting address of the interrupt handler program executed when a VDP_IRQ0 interrupt occurs.

[0301] As shown in Figure 18(d), the interrupt priorities are as follows: the columns for vector numbers smaller than vector number 64 store the starting addresses of the interrupt handling programs for the control command receive interrupt IRQ_CMD, the 20μS timer interrupt, and the 1mS timer interrupt, respectively. On the other hand, the columns for vector numbers larger than vector number 64 store the starting addresses of interrupt handling programs with lower priority than VDP_IRQ 1 (such as IRQ_SND and IRQ_RTC).

[0302] Furthermore, in the vector table VECT, vector numbers 0 and 1 have defined settings that should be automatically set to the CPU's program counter and stack pointer during power-on reset. As shown in Figure 16(b), in this embodiment, during power-on reset (reset assertion period), the internal operation involves setting the 4-byte data "****" to the program counter PC and setting the 4-byte data "++++" to the stack pointer SP. "****" is the starting address value of the initial setup program Pinit (SP1~SP9 in Figure 16), which is non-volatilely stored in the address space CS0, and "++++" is the address value of the beginning or end of the stack area, which is allocated in the built-in RAM 59 and functions in a LIFO (Last-In First-Out) manner.

[0303] In this embodiment, since the register bank RBi is effectively utilized, the stack area is not consumed during interrupt processing, and therefore, not much memory capacity is required. In other words, in this embodiment, the stack area is used exclusively for function processing and subroutine processing.

[0304] As a result of the above operations, the performance control CPU 63 will then execute the initial setup program Pinit, which is described after the address value "****". However, the memory READ operation in address space CS0 is performed based on the default value (initial value) of the operation control register REG, which defines the operation of the bus state controller 66 (Figure 9). The initial value of this operation control register REG is a value that is automatically set during the reset assertion period (the period shown in Figure 7(d) during which the system reset signal SYS maintains an L level), and is set to the slowest READ access operation (default access operation) so that READ access to address space CS0 can be performed without problems regardless of what memory device is configured in it.

[0305] Therefore, in order to change this default access operation to the optimal access operation, first, an optimal value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (Figure 9) with respect to the address space CS0 (SP1). That is, in order to optimize the memory READ operation when accessing the initial setup program Pinit (SP1~SP9), the performance control program MainB (SP10 and below), and the PROM 53 which stores constant data, the bus width and whether or not there is page access are set, and the timing of the chip select signal CS0, the READ control signal, the WRITE control signal, and other operation timings are set to the optimal value (see Figure 40).

[0306] As a result of the above settings, the processing from step SP2 onward will be executed by optimally reading the program stored in address space CS0 from memory. Next, in order to optimize the READ / WRITE access operation when the performance control CPU 63 accesses the VDP register RGij, an optimal value is set in a predetermined operation control register REG that defines the operation of the bus state controller 66 (Figure 9) with respect to the VDP register RGij (SP2).

[0307] As explained earlier, in this embodiment, the VDP register RGij is located in the address space CS7 of the performance control CPU 63. Therefore, a predetermined value is written to a predetermined operation control register REG in order to optimize the operation timing of the chip select signal CS7 and other control signals.

[0308] Next, the register value of a specific VDP register RGij is read, and it is determined whether or not that value is a predetermined value (device code) (SP3). This is a confirmation that the system clock of the VDP circuit 52 has stabilized. In other words, the VDP circuit 52 operates based on the oscillation output of the oscillator OSC2 supplied to the PLLREF terminal, and this is a determination of whether or not the VDP circuit 52 can properly accept commands from the CPU circuit 51 (i.e., settings for the VDP register RGij).

[0309] Then, once it is confirmed that the system clock has stabilized through the device code reading process (SP3), the normal operation of the VDP circuit 52 can be expected, and the setting process for the predetermined VDP register RGij is executed (SP4~SP6). In step SP4, first, the endianness setting (big / little) and data bus width for when the performance control CPU 63 accesses the VDP register RGij are set (SP40), and the interrupt significance level (H / L) for internal interrupts from the VDP circuit to the CPU circuit (VDP_IRQ0, VDP_IRQ1, VDP_IRQ2, VDP_IRQ3) is set (SP41).

[0310] In this embodiment, the most significant bit of the setting value is set to big-endian, which stores it in the most significant bit of the VDP register RGij, and the data 32 bus width is set to 32 bits. However, if these setting values ​​are the same as the default values, these setting processes can be omitted (the same applies to the following processes).

[0311] Furthermore, in step SP4, the frequency of the display clock is set based on the value set in a predetermined system control register RGij (SP42~SP44). Specifically, for display circuits 74A and 74B, the predetermined system control register RGij is set to generate the dot clock DCKA and DCKB based on a 40MHz reference clock (output of oscillator OSC2) (SP42), and the multiplication ratio and division ratio for this reference clock are appropriately defined for each display circuit (SP43). In addition, the system control register RGij is set to synchronize the start of operation of display circuit 74B with the start of operation of display circuit 74A (SP44). Furthermore, the sampling clock of the LVDS is set to be the same as the dot clock DCKA of display circuit A (SP43).

[0312] In these processes, the dot clock DCK is set separately for display circuit 74A and display circuit 74B. The frequency of the dot clock DCKA for the main display device DS1 applied to display circuit 74A is set to 108MHz, as explained earlier. On the other hand, the frequency of the dot clock DCKB for the sub-display device DS2 applied to display circuit 74B is set to 27MHz, corresponding to 480 pixels horizontally and 800 pixels vertically.

[0313] Furthermore, in step SP4, the LVDS unit 80 is set to be used as a dual link (a pair of LVDS transmission lines) (SP45), and the operating state of the LVDS unit 80 is switched from a masked state (default state) that outputs zero to an unmasked state that follows the output of the display circuit 74, based on the setting value of a predetermined system control register RGij (SP45). If the LVDS unit 80 is to be used as a single link (a single LVDS transmission line), this setting will be made in the process of step SP45.

[0314] As shown in Figure 6(f), as a result of the processing in step SP45, the operation of the LVDS unit 80 switches from the default state to the unmasked state. Subsequently, after the timing T4 in which the display circuit 74 starts operating (see SS4 in Figure 21), the LVDS units 80a and 80b are supplied with the ODD signal and the EVEN signal via the output selection unit 79, and the LVDS signal (LVDS1 / LVDS2) is transmitted to the display device DS1 via the dual link (see Figure 14(a)). The sampling clock for LVDS is set to 108MHz, the same as the dot clock DCKA of the display circuit A. However, in this embodiment, a dual-link configuration is adopted, so the LVDS sampling clock in each dual link is 54MHz (see Figure 4).

[0315] Furthermore, in step SP4, the system is configured to activate the DDR (DRAM 54) based on the clock signal (reference clock) sent to the PLLREF terminal (see Figure 8(a)) (SP46). As explained with respect to Figure 8(a), the reference clock of the oscillator OSC2 is supplied to the PLLREF terminal. In addition, by setting appropriate values ​​in the registers built into the DDR (DRAM 54), the self-refresh function of the DRAM 54 is enabled, and other settings are made to ensure that the DRAM 54 operates normally (SP47). Through these processes, the DRAM 54 becomes ready to operate normally, and the subsequent data transfer operation from the PROM 53 to the DRAM 54 (SP8) and the execution of the control program transferred to the DRAM 54 (SP10) are carried out without any problems.

[0316] Next, address spaces CS1 to CS6 are defined (SP5) to realize the memory map shown in Figure 10. As explained earlier, address space CS3 is assigned to the internal registers of the audio processor 27, address space CS4 is assigned to the internal registers of the RTC 38 and the address space of the SRAM 39, address space CS5 is assigned to the external DRAM (DDR) 54, and address space CS6 is assigned to the work memory 57 of the built-in CPU.

[0317] Furthermore, since it is fixed that the VDP register RGij is allocated to address space CS7, no definition process for address space CS7 is necessary. Also, it is fixed in advance that address space CS0 is located at memory map address 0x000000000 or later in the CPU circuit 51. Based on this specification, whether address space CS0 is allocated in CGROM 55 or assigned to another memory device is determined by the H / L level of the HBTSL terminal.

[0318] As explained earlier, in this embodiment, the HBTSL terminal is set to L, indicating that an address space CS0 is defined in addition to the CGROM 55. Furthermore, since the specific bus width and optimal access operation of the control memory 53, which is separate from the CGROM 55, have already been set in step SP1, the processing in step SP5 is unnecessary for the address space CS0 as well.

[0319] Next, for the address spaces CS1 to CS6 defined in step SP5, predetermined values ​​are written to the predetermined operation control register REG (SP6) regarding the bus width and whether or not page access is performed when accessing each address space CSi. In addition, predetermined values ​​are written to the predetermined operation control register REG (SP6) to optimize the chip select signal CSi and other settings. These processes are the same as those in steps SP1 and SP2, and the writing process to the operation control registers that define the operation of the bus state controller 66 (Figure 9) optimizes the timing of the chip select signal CSi, READ control signal, WRITE control signal, and other operations.

[0320] Next, regarding the WDT circuit 58, which has already started operating, a clear signal is output to the WDT circuit 58 to prevent an abnormal reset (SP7). This takes into account that the WDT circuit 58 automatically starts operating after power-on, and the same process is repeated thereafter. The process of step SP9 is stored in the control memory 53 as subroutine SP7, but until the end of step SP9, subroutine SP7 in the control memory 53 is called, and after the end of step SP9, another subroutine SP7' transferred to the external DRAM 54 is called and executed.

[0321] Next, the following programs and data stored in the address space CS0 are transferred to the external DRAM 54 or the internal RAM 59 (SP8): the vector handler Vopt (interrupt handling program), the error recovery program Piram, the performance control program MainB, the variable D with an initial value, and the constant data C, as shown in Figures 16(b) and 17(c). Note that the variable D with an initial value refers to the initial value data stored in a predetermined variable area. This memory section initialization process (SP8) is a process to transfer programs and data in order to speed up the performance control process, and is a process to avoid accessing ROM, which has a slower access speed.

[0322] Next, the system is configured to use register bank RBi (SP9). As a result, register banks RB0 to RB14 will function during interrupt handling, speeding up interrupt processing and reducing stack memory consumption.

[0323] The above process is achieved by executing the "initialization program Pinit" stored in the control memory 53, which is address space CS0 (see Figure 17(c)). After the execution of this initialization program Pinit is complete, the main control process by the performance control program Main is then executed (SP10). Here, the execution of the main control process means the execution of the "performance control program Main" that was transferred from the control memory 53 to the external DRAM 54 by the transfer process in step SP8 (see Figure 16(b)).

[0324] The processing of the "Performance Control Program Main" is divided into the main introduction processing shown in Figure 18(a) and the upper part of Figure 21, and the main body processing shown in the lower part of Figure 21 and Figure 22(a). The specific details will be explained based on Figure 18(a) and Figures 21 to 22, but before that, the memory section initialization process (SP8) will be explained. As shown in Figure 17(a), in the memory section initialization process (SP8), the multi-channel DMAC is initially set to a disabled state. Note that this process is merely a formality for the sake of being sure.

[0325] Once the above processing is complete, the DMACi on the designated channel is activated, and the vector handler Vopt (interrupt processing program) stored in the control memory 53 is DMA-transferred to the internal RAM 59 using a nonstop transfer method (see Figure 11(b3)). In this embodiment, since the interrupt processing program Vopt is transferred to the internal RAM 59, appropriate error handling processing is possible even in the event of an error in the external DRAM 54.

[0326] The subsequent processing is the same, and is executed using a DMACi on a predetermined channel in a nonstop transfer manner, transferring the error recovery processing program Piram to the built-in RAM 59 via DMA (SP62). In this embodiment, since the error recovery processing program Piram is transferred to the built-in RAM 59, the peripheral circuits can be reliably reset during the error recovery process. For example, if the error recovery processing program Piram were transferred to an external DRAM 54 other than the built-in RAM 59, the external DRAM 54 could not be reset during the error recovery process.

[0327] Next, the performance control program Main is DMA-transferred to the external DRAM 54 (SP63), and the constant data C is DMA-transferred to the external DRAM 54 (SP64). The constant data includes lottery data used for performance lottery, and lamp drive data and motor drive data from the various drive data tables shown in Figure 22(b). In addition, a variable D with an initial value is DMA-transferred to the external DRAM 54 (SP65). All of these are executed using a nonstop transfer method with a predetermined channel of DMACi.

[0328] Finally, clear data is written to the beginning of variable area B of the external DRAM (SP66). If we assume this starting address is ADb, then in the subsequent DMA transfer process, the source address is set to ADb and the destination address is initially set to ADb+1. Then, the clear data is spread while incrementing the address values ​​ADb and ADb+1, thereby clearing variable area B (SP67).

[0329] The processes described above in steps SP61 to SP66 and step SP67 are all similar operations and are shown in Figure 17(b). Specifically, first, the DMACi of a predetermined channel is set to have the following DMA transfer conditions: (1) cycle steal transfer mode, (2) nonstop transfer method, and (3) increment update of the Source and Destination address values ​​(SP68).

[0330] Next, the initial values ​​of the source address and destination address are set (SP69), the transfer size is set, interrupts are disabled, etc. (SP70), and then the DMA transfer operation is started (SP71). Note that the settings in steps SP68 to SP71 are all achieved by setting operations in a predetermined operation control register REG.

[0331] In the initialization process of this memory section, the interrupt for the end of DMA transfer is disabled (SP70). Therefore, after the DMA transfer operation is started, the status flag of a predetermined operation control register REG is repeatedly read and accessed to wait for the DMA transfer to end (SP72). However, considering the processing time until the operation ends, a clear signal is repeatedly output to the WDT circuit 58 (SP73). Then, when the DMA transfer ends, DMACi is set to stop based on the setting operation of the predetermined operation control register REG.

[0332] Next, the operation of the main control process (main setup process + main body process) will be explained based on Figures 18(a) to 22. Regarding the main control process (main setup process + main body process), the main setup process (SP20 to SP27) is described at the top of Figures 18(a) and 21, while the initial setup process (SS1 to SS6), which is part of the main body process, is described at the bottom of Figure 21. The contents of the remaining steady-state processing (ST4 to ST14) of the main body process are described in Figure 22.

[0333] As shown in Figure 18(a), the main setup process first identifies the bus width and ROM device type of the CGROM55 (SP20). Specifically, as shown in Figure 19(a), a predetermined VDP register RGij (e.g., the CG bus Status register), which identifies the operating state of the CG bus that controls the interface with the CGROM55, is accessed via READ (SP80) to determine whether or not the operation of the CG bus can be configured (SP81).

[0334] Here, if the value of the CG bus Status register is 1, it means that the internal circuitry of the CG bus is in the process of resetting, and that it cannot accept the setting value for the VDP register RGij. Therefore, after confirming that the value of the CG bus Status register has changed from 1 to 0 (SP81), the following operational parameters are set in the predetermined VDP register RGij for each device section (SPA0 to SPAn) that can be defined corresponding to the memory devices constituting the CGROM: ​​(1) enable / disable each device section SPAi, (2) type of ROM device, and (3) data bus width (SP82).

[0335] As shown in Figure 18(a), in this embodiment, the CGROM 55 can be divided into multiple regions (device sections), and for example, the memory device and data bus width can be selected for each device section (SPA0 to SPAn). Memory devices can be broadly classified into, for example, (1) the SATA module (AHSI / F) used in this embodiment, (2) memory elements that adopt a parallel I / F (Interface) format, and (3) memory elements that adopt a sequential I / F format. For each of these broadly classified memory devices, it is possible to specifically select the memory device and arbitrarily define the data bus width, etc.

[0336] Next, in order to optimize the memory READ operation with the memory device selected for each device section (SPA0 to SPAn), predetermined operating parameters are set to a predetermined VDP register RGij (SP83). The operating parameters include setting values ​​that define the timing of operation between the chip select signal and other control signals (such as the READ control signal). Furthermore, if a memory element adopting a sequential I / F format is selected, the output timing of the address latch and the number of read clocks are also specified in order to achieve the operation shown in Figure 19(b).

[0337] Therefore, it is also possible to configure CGROM55 by combining different types of memory devices. However, in this embodiment, CGROM55 is configured using only SATA modules, with only the device section (SPA0) enabled and the other device sections (SPA1 to SPAn) disabled.

[0338] In any case, once the setting process in steps SP82 to SP83 is complete, a predetermined value is written to the designated VDP register RGij (SP84) in order to implement the setting process. This takes into account that the internal circuitry of the CG bus requires a certain amount of time to operate in response to the setting process in steps SP82 to SP83, and while the internal circuitry is operating, the value of the aforementioned CG bus Status register (see SP80) becomes 0.

[0339] Therefore, the CG bus Status register is repeatedly accessed via READ (SP85) to confirm that the value of the Status register returns from 1 to 0, and the process ends (SP86). However, regardless of the predetermined number of attempts, the process in step SP66 may be terminated if the value of the Status register does not return from 1 to 0. In that case, the game process will start with the CGROM unable to be accessed properly, and the WDT circuit 58 will activate at some point thereafter, causing the composite chip 50 to enter an abnormal reset state. In this case, the power-on reset operation will be performed again.

[0340] On the other hand, after the processing of step SP20 in Figure 18 is successfully executed, the built-in circuits of the CPU circuit 51, such as the interrupt controller INTC, the DMAC circuit 60, and the multifunction timer unit MTU, are individually initialized by software processing (SP21).

[0341] Next, with respect to the multifunction timer unit MTU, after starting the predetermined timer measurement operation (SP22), the internal interrupt and the internal interrupt are set to the interrupt-enabled state by writing the enable setting value to the predetermined operation control register REG (SP23).

[0342] As a result, various interrupts shown in Figure 18(d) may occur thereafter. Normally, at this timing, the audio processor 27 has finished its initialization sequence, so the termination interrupt signal IRQ_SND should drop to a low level, as shown in Figure 7(c). Therefore, the interrupt handler shown in Figure 18(c) is activated, and the performance control CPU 63 initializes the error flag ERR to 1, and also performs a READ access to the address space CS3 (SP30) to obtain the value of a predetermined audio register SRG of the audio processor 27 and determines whether the initialization sequence has completed successfully (SP31).

[0343] If the initialization sequence does not complete successfully, the performance control CPU 63 writes a reset command to a predetermined audio register SRG of the audio processor 27 (SP32) and sets the error flag ERR, which is initially set to 1, to 2 (SP33). This error flag ERR determines whether or not to execute the audio processor initialization process (SP26), and error flag ERR=1 is the condition for executing step SP26.

[0344] Meanwhile, in response to receiving the reset command, the audio processor 27 restarts the initialization sequence with the termination interrupt signal IRQ_SND at the H level. Once the initialization sequence is complete, the termination interrupt signal IRQ_SND is lowered to the L level. As a result, the process shown in Figure 18(c) is re-executed.

[0345] The above describes exceptional cases where the initialization sequence does not complete normally. However, normally, the processing in step SP32 is executed following step SP31, and the performance control CPU 63 restores the termination interrupt signal IRQ_SND from L level to H level by writing a predetermined value to a predetermined audio register SRG (SP34).

[0346] Finally, by writing a predetermined value to the designated audio register SRG, READ / WRITE access to all audio registers SRG is permitted (SP35). As a result of this process, the necessary configuration processes can be executed during the subsequent audio processor initialization process (SP26).

[0347] The above describes an example of a Maskable Interrupt corresponding to the interrupt enable setting in step SP23. However, a Non-Maskable Interrupt based on the cessation of oscillation by oscillator OSC2 can be triggered at any time. As explained earlier, the operating clock (CPU system clock) of circuits other than the built-in CPU (performance control CPU 63) is generated by frequency multiplying the output clock of oscillator OSC2 using a PLL (Phase Locked Loop). If the oscillation of oscillator OSC2 stops, the normal operation of the VDP circuit 52 is impossible.

[0348] On the other hand, the operating clock of the performance control CPU 63 is generated by multiplying the output clock of the oscillator OSC1 using a PLL, allowing program processing to continue. Moreover, the interrupt processing program is stored in the built-in RAM 59. Therefore, the performance control CPU 63 notifies the occurrence of an abnormal situation with sound and lights (SP28), and continuously outputs a clear signal to the WDT circuit 58 (SP29). The abnormal notification is, for example, an audio notification saying, "An abnormal situation has occurred. Please contact an attendant immediately." The reason for continuously outputting a clear signal to the WDT circuit 58 is to avoid abnormal reset operation. In other words, in the event of a serious abnormality in which the oscillator OSC1 stops operating, it is considered unlikely that the equipment will return to normal even if the abnormal reset process is repeated.

[0349] Having explained Figures 18(b) and 18(c), let's return to Figure 18(a) and continue the explanation. In step SP24, in order to protect the program area of ​​the external DRAM 54, the necessary area is set to write-protected. Next, regarding the clock circuit 38, which is powered by a battery when the power is cut off, the normal operation when the power is cut off is confirmed, and the alarm interrupt is reset as a precaution (SP25).

[0350] Then, under the condition that the error flag ERR=1, the necessary settings are written to the built-in register (audio register SRG) of the audio processor 27 and the initialization process is executed (SP26). If the error flag ERR=0, the system waits for a predetermined time until the error flag ERR becomes 1, but if the time limit is exceeded, the system switches to an infinite loop process to activate the WDT circuit 58.

[0351] Next, the power supply control circuit SPY is controlled to prepare for the startup of the display device DS1, and the necessary setting values ​​are written to the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP27). The process of step SP27 is shown in detail as the processes of steps SP50 to SP57 in Figure 21.

[0352] The above describes an embodiment in which the termination interrupt signal IRQ_SND is received from the audio processor. However, it is also preferable to omit the interrupt processing shown in Figure 18(c). Figure 20 shows a modified embodiment in which the 1ms timer interrupt signal generated by the multifunction timer unit MTU is used instead of the termination interrupt signal IRQ_SND.

[0353] Figure 20 illustrates a part of the 1ms timer interrupt processing, which implements four stages of operation based on the value of the operation management flag FLG (0 / 1 / 2 / 3), with the initial state being zero. The IRQ_SND output terminal of the audio processor 27 is left open, and the IRQ_SND input terminal of the CPU circuit 51 is fixed at a high level.

[0354] In the 1ms timer interrupt processing, first, in step SP42, if the operation management flag FLG is determined to be 0, it is confirmed that the initialization sequence of the audio processor 27 has completed successfully (SP43). If it has completed successfully, the interrupt signal (IRQ_SND) is cleared by writing a predetermined value to the predetermined audio register SRG (SP46), and the operation management flag FLG is set to 1 (SP47). Note that the processing in steps SP43 and SP46 is the same as the processing in steps SP31 and SP34 in Figure 18(c).

[0355] On the other hand, if the initialization sequence has not completed successfully, a reset command is written to a predetermined audio register SRG to start the initialization sequence in the audio processor 27 (SP44), and the operation management flag FLG is reset to zero (SP45). Note that the processing in step SP44 corresponds to the processing in step SP32 in Figure 18(c).

[0356] Normally, after processing in step SP47, the operation management flag FLG becomes 1. In the next 1ms timer interrupt, a predetermined value is written to a predetermined audio register to allow access to all audio registers (SP48), and the operation management flag FLG is set to 2 (SP49). The processing in step SP48 corresponds to the processing in step SP35 in Figure 18(c).

[0357] Next, in the 1ms timer interrupt with the operation management flag FLG=2, the necessary setting values ​​are written to the built-in register (audio register SRG) of the audio processor 27 and the initialization process is performed (SP50), similar to step SP26 in Figure 18(a), and the operation management flag FLG is set to 3.

[0358] The operation management flag FLG=3 indicates the normal voice control state, and voice control proceeds by setting the necessary operation parameters in the required voice register SRG (SP52).

[0359] The above describes two methods for confirming the successful completion of the initialization sequence of the audio processor 27: one using interrupt processing triggered by an interrupt signal (IRQ_SND) (SP31 in Figure 18(c)) and another using 1ms timer interrupt processing (SP43 in Figure 20). However, the method is not limited to these methods. For example, it is also preferable to determine whether the initialization sequence of the audio processor 27 has completed successfully as part of the processing in step SP26 of Figure 18.

[0360] Having explained the overview of the main setup process (SP20-SP26 in Figure 18), the following will explain the details of the process in step SP27 (startup preparation process + initialization process) and the operation of the main body processing processes (SS1-SS6 and ST4-ST14) based on Figures 21-22.

[0361] As shown in Figure 21, the performance control CPU 63, as part of step SP27, first checks the timing timer TM and confirms that 1 second has elapsed since the start of operation of the performance control CPU 63 (timing T1 in Figure 6(d)) by outputting a clear signal to the WDT circuit 58 (SP50). This is to keep the display device DS1 in a non-operating state until the VDP circuit 52 actually starts operation. Also, since a clear signal is output to the WDT circuit 58, the WDT circuit 58 is reliably prevented from starting, and there is no risk of the composite chip 50 being abnormally reset, thus rendering the initialization process up to this point useless (this significance is the same in the following standby process).

[0362] Next, the performance control CPU 63 transitions the control signals PS1 and PS2 to the power supply control circuit SPY from L level to H level (SP51). This process corresponds to the timing T2 shown in Figures 6(g) and 6(h), and the control signals PS1 and PS2 are maintained at the H level thereafter.

[0363] When the control signal PS1 reaches a high level, the MOS transistor Q1 turns ON, and the power supply voltage of 12V is supplied to the backlight unit BL. However, at this timing T2, both the BL_EN terminal and the PWM terminal of the backlight unit BL driver DVL are at a low level, so the backlight unit BL does not light up.

[0364] Furthermore, when the control signal PS2 reaches a high level, the MOS transistor Q4 turns ON, and power supply voltage 5 is supplied to the liquid crystal display unit MONI. However, at this timing T2, the backlight unit BL is off, so there is no risk of unnatural images being displayed.

[0365] Once the processing in step SP51 is complete, the performance control CPU 63 then defines the refresh mode based on the setting value of a predetermined VDP register RGij, sets the refresh period and initial value of the row address (refresh address) of the built-in VRAM 71, and executes the initialization process of the built-in VRAM 71 (SP52).

[0366] The VRAM 71 in this embodiment is composed of DRAM (Dynamic Random Access Memory), and the charge stored in the memory cells is gradually lost due to leakage current within the element. Therefore, in this embodiment, for example, a distributed refresh method is adopted in which one row at a time is refreshed, and all rows (ROWs) in the element are refreshed at the refresh cycle defined in the processing of step SP52 to prevent the loss of charge in the memory cells. Thus, even if there are memory cells in the VRAM 71 that are not accessed for a long time, there is no risk of data loss. Note that the refresh mode is not limited to the distributed refresh method, and a centralized refresh method can also be adopted.

[0367] Next, the necessary settings are written to the VDP register RGij to initialize the display clock DCK and the display circuit 74 (SP54). This process is essentially a hardware reset of the corresponding internal circuitry.

[0368] Next, the control signal STBY to the power supply control circuit SPY is transitioned from L level to H level (SP56). This process corresponds to the operation at timing T3 shown in Figure 6(i), and the H level of the control signal STBY is maintained thereafter. At timing T3, the driver DVL of the backlight unit BL is already powered by a 12V power supply (timing T2), so the driver DVL becomes operational. However, since the control signal PWM remains at the L level, the backlight unit BL does not emit light.

[0369] Next, the execution of the process in step SP4 in Figure 16 and the execution of the process in step SP54 in Figure 21 are confirmed by reading the predetermined VDP register (status register STS) RGij (SP57). Specifically, first, the status register STS(1) is checked to confirm that the display clock set in the process of step SP4 in Figure 16 has stabilized.

[0370] Next, the status register STS(2) is used to confirm that the initialization of the display circuit has been successfully completed in response to the processing in step SP54. Subsequently, the status register STS(3) is used to confirm that the initialization of each part LVDS1 / LVDS2 of the LVDS circuit 80, which was configured for dual-link in step SP45, has been successfully completed. Once it is confirmed that all initializations have been successfully completed, the main introduction process ends (SP57).

[0371] Next, we will describe the subsequent processing in an example where the preloader does not function. As shown in Figures 21 to 22(a), the main processing is divided into VDP initial setup processing (SS1 to SS6) which is executed after the CPU reset, and then steady-state processing (ST4 to ST14) which is executed repeatedly every 1 / 30 second.

[0372] The steady-state processing (ST4~ST14) starts when the interrupt counter VCNT becomes VCNT ≥ 2 (ST4), so the operating period δ of the steady-state processing is 1 / 30 of a second. This operating period δ is none other than the effective operating period δ of the VDP circuit 52, which operates intermittently based on the control of the performance control CPU 63. The decision condition is set to VCNT ≥ 2 to account for the possibility that the steady-state processing (ST4~ST14) may take an unusually long time and miss the timing when VCNT = 2, but the system is designed so that the situation where VCNT = 3 does not occur.

[0373] Based on the above, the VDP initialization process will now be explained. As shown in Figure 21, in this embodiment, the built-in VRAM 71 with a storage capacity of 48 MB is appropriately divided into an ACC area (a) with an appropriate storage capacity, a page area (b), and an arbitrary area (c) (SS1). Specifically, for the ACC area (a1, a2) and the page area (b), the starting address of each area and the required total data size are set in a predetermined index table register RGij (SS1). Then, the remaining area not included in the allocated ACC area (a1, a2) and the page area (b) becomes the arbitrary area (c).

[0374] Here, the starting addresses of the first and second ACC areas (a1, a2) and the page area (b) must have their lower 11 bits set to 0, but they can be arbitrarily selected in units of 2048 bits (selection in units of 256 addresses, assuming 1 address = 1 byte). The total data size can also be arbitrarily selected within the range of integer multiples of the unit size. While not particularly limited, the unit size of the ACC area (a) is 2048 bits, and the unit size of the page area (b) is 512 kbit.

[0375] In this embodiment, certain conditions are imposed on the area settings of the ACC area (a1, a2) and the page area (b). This is to eliminate as much wasted space as possible in the built-in VRAM 71, which has limited memory capacity, while also ensuring smooth internal operation of the VDP circuit 52. In other words, unnecessarily increasing the storage capacity of the built-in VRAM 71 raises concerns about increased manufacturing costs and larger chip area, while allowing free area settings that completely eliminate wasted space would complicate internal processing and prevent shortening the processing time for VRAM access. The same reason applies to imposing certain constraints on the allocation of the index space, which will be explained below.

[0376] Based on the above, the explanation continues as follows: Following the processing in step SS1, the necessary index space IDXi is allocated for the page area (b) and the arbitrary area (c) (SS2). Specifically, the index space IDXi for each area (b) and (c) is allocated by setting the necessary information in a predetermined index table register RGij.

[0377] For example, if an index space IDXi is provided in the page area (b), then information on multiples of an arbitrary horizontal size Hx and an arbitrary vertical size Wx (multiple information of the length and width relative to the unit space) corresponding to an arbitrary index number i is set in a predetermined index table register RGij (SS2).

[0378] As explained earlier, the index space IDXi of page area (b) uses a unit space of 128 horizontal x 128 vertical lines, and since one pixel is identified by 32 bits of information, an index space IDXi with a data size (bit length) of 32 x 128 x Hx x 128 x Wx is allocated based on the settings of the horizontal size Hx and vertical size Wx. Note that the starting address (space start address) of the index space IDXi of page area (b) is automatically assigned internally.

[0379] Furthermore, when an index space IDXi is provided in the arbitrary area (c), an arbitrary starting address (space starting address) STx and information that is a multiple of an arbitrary horizontal size Hx are set in a predetermined index table register RGij, corresponding to an arbitrary index number i (SS2). Here, "arbitrary" is based on predetermined conditions, where the horizontal size Hx is arbitrarily determined in 256-bit units, the lower 11 bits of the starting address STx are 0, and the horizontal size Hx is arbitrarily determined in 2048-bit units. As explained earlier, the vertical size of the arbitrary area is fixed at 2048 lines, so based on the setting of the horizontal size Hx, an index space with a data size (bit length) = 2048 × Hx is secured from the starting address STx onward.

[0380] Specifically, for the main display device DS1, a pair of index spaces with a horizontal size of 1280 x vertical lines of 2048 are set in one or more predetermined index table registers RGij, each with a specified index number, as the frame buffer FBa. Similarly, for the sub-display device DS2, a pair of index spaces with a horizontal size of 480 x vertical lines of 2048 are set in one or more predetermined index table registers RGij, each with a specified index number, as the frame buffer FBb. If the number of horizontal pixels of a display device does not match an integer multiple of 256 bits / 32 bits, the horizontal size of each index space is set to a value that is greater than the number of horizontal pixels of that display device and is an integer multiple of 256 / 32 = 8, thereby minimizing the generation of wasted memory.

[0381] As described above, by setting the necessary size and address information for the page area (b) and the arbitrary area (c) in the predetermined index table register RGij, the required number of index spaces IDXi are generated (SS2). Then, corresponding to this setting process (SS2), an index table IDXTBL is automatically constructed that identifies the address and size information of each index space IDXi. As shown in Figure 12(a), the index table IDXTBL stores the starting address of each index space IDXi along with other necessary information, and is referenced during data transfer within the VDP circuit 52 and when acquiring data from an external storage resource (Resource) (see Figure 13). Note that the index spaces IDXi in the AAC area (a) are automatically generated and automatically destroyed when needed, so the setting process in step SS2 is unnecessary.

[0382] As shown in Figures 12(a) and 12(b), a pair of frame buffers FBa and FBb are allocated in the arbitrary region (c), and each is assigned an index number. In the embodiment where the Z buffer is not used, a pair of index spaces 255 and 254 are allocated as frame buffer FBa, with index numbers 255 and 254 assigned to them. Similarly, a pair of index spaces 252 and 251 are allocated as frame buffer FBb, with index numbers 252 and 251 assigned to them. In this embodiment, a working area (index space 0) with index number 0 is also allocated in the arbitrary region (c).

[0383] Furthermore, in this embodiment, the necessary number of index spaces IDXi, which will serve as the decoding area for IP stream video, are allocated in the page area (a), and index numbers i are assigned to them. However, initially, only the index space IDX0 for background video (IP stream video) is allocated. Then, depending on the need for image effects (variation effects and preview effects), the index space IDXj in the page area (a) is increased based on setting processes in the index table register RGij and instruction commands in the display list DL, and then the index space IDXj is released when it is no longer needed. In other words, Figure 12(a) shows the index table IDXTBL during steady operation.

[0384] The index space of the ACC area (a) is automatically generated as needed based on the instruction commands listed in the display list DL, and the index table IDXTBL is automatically populated with the starting address of the automatically generated index space IDXj and other necessary information. In this embodiment, this AAC area (a) is used as the decoding area for still images and other textures.

[0385] The above operation to secure the index space is achieved primarily by setting the index table register RGij included in the control register group 70. Following the processing of steps SS1 to SS2, the necessary setting operation (SS3) is performed on other VDP registers RGij, enabling the steady-state operation (intermittent operation) of the VDP circuit 52 shown in Figures 30 to 31.

[0386] In this embodiment, the necessary setting process (SS3) includes at least SS30 to SS39. Note that steps SS30 to SS37 can be executed in any order, not limited to the order described below.

[0387] In this embodiment, first, predetermined operating parameters (number of lines and number of pixels) are written to a predetermined display register RGij that defines the operation of the display circuit 74, thereby setting the number of display lines and horizontal pixels for each display device DS1 and SD2 (SS30). In this embodiment, the main display device DS1 has 1280 horizontal pixels and 1024 display lines. The sub-display device DS2 has 480 horizontal pixels and 80 display lines. As a result of the setting process in step SS34, the vertical and horizontal dimensions of the valid data area (dashed line area in Figure 22(e)) that the display circuits 74A and 74B should access via READ are determined for each frame buffer FBa and FBb.

[0388] Next, predetermined operating parameters (THc, WTh) are written to a predetermined display register RGij that defines the operation of the display circuit 74, thereby setting the number of cycles THc for the horizontal period TH and the horizontal standby time WTh for each display device DS1 and SD2 (SS31). Additionally, predetermined operating parameters (TVl, WTv) are written to a predetermined display register RGij, thereby setting the number of lines TVl for the vertical period TV and the vertical standby time WTv for each display device DS1 and SD2 (SS32).

[0389] As explained with respect to Figure 15, the main display device DS1 is set to have a horizontal period TH with a cycle count of THc = 1662 and a vertical period TV with a line count of TVl = 1083. It is also set to have a horizontal standby time WTh = 382 and a vertical standby time WTv = 59 lines. On the other hand, the sub-display device DS2 is set, for example, to have a horizontal period TH with a cycle count of THc = 519 and a vertical period TV with a line count of TVl = 867, with a horizontal standby time WTh = 39 and a vertical standby time WTv = 67 lines. Note that THc - WTh = 519 - 39 = 480 and TVl - WTv = 867 - 67 = 800, which matches the number of pixels of the sub-display device (480 horizontally x 800 vertically).

[0390] In any case, the processing in step SP4 of Figure 16 determines the frequency F of the dot clock DCK. dot(=108MHz) is determined, and through the processing in steps SS30 to SS32, the number of cycles THc (=1662) for the horizontal period TH and the number of lines TVl (=1083) for the vertical period TV are defined for the main display device DS1. As a result, the display period of one frame is THc × TVl / F dot This is then confirmed. Specifically, the display period for one frame is 1083 × 1662 / 108MHz = 16.667 mS, and the frame rate FR is confirmed to be 1 / 60 second.

[0391] Furthermore, regarding the sub-display unit DS2, for example, the frequency F of the dot clock DCK. dot Based on a frequency of 27MHz, the number of cycles of the horizontal period THc = 519, and the number of lines of the vertical period TVl = 867, the duration is determined to be 519 × 867 / 27MHz = 16.66mS.

[0392] Next, in this embodiment, with respect to the sub-display device DS2, the pulse width of the horizontal periodic signal HS and the number of cycles from the V-blank start timing of the pulse rising edge are set in a predetermined display register RGij (SS33). Also, with respect to the sub-display device DS2, the pulse width of the vertical periodic signal VS and the number of cycles from the V-blank start timing of the pulse rising edge are set (SS34).

[0393] As explained earlier, the main display device DS1 does not require the horizontal sync signal HS or the vertical sync signal VS, so the above processing (SS33~SS34) for the main display device DS1 is unnecessary. However, if the setting process in steps SS33~SS34 is omitted, the default values ​​set at the time of power reset will be used, so in reality, the display device 74A will also output the horizontal sync signal HS and the vertical sync signal VS.

[0394] According to the default settings, for example, a horizontal synchronization signal HS with a pulse width of 40 clock cycles is output, which becomes active 16 clock cycles after the V-blank start timing, and a vertical synchronization signal VS with a pulse width of 3 lines is output, which becomes active in synchronization with the V-blank start timing.

[0395] This operation means that, during the horizontal standby time WTh = 382 clock cycles, a horizontal synchronization signal HS with horizontal front porch HPv = 16, pulse width PWh = 40, and horizontal back porch BPv = 326 is output to the main display device DS1, and during the vertical standby time WTv = 59 lines, a vertical synchronization signal VS with vertical front porch HPv = 0, pulse width PWv = 3, and vertical back porch BPv = 56 is output. However, as mentioned above, these synchronization signals are ignored by the main display device.

[0396] Furthermore, to prevent the output of synchronization signals HS and VS based on default values, a configuration may be adopted in which a predetermined system control register RGij is set to not output the horizontal synchronization signal HS or the vertical synchronization signal VS. When such a mask setting is provided, the output terminals of the horizontal synchronization signal HS and the vertical synchronization signal VS of the VDP circuit 52 can maintain fixed values ​​of H level or L level.

[0397] Next, the predetermined system control register RGij is set to allow V-blank interrupts (SS35). As a result, in this embodiment, a VBLANK start interrupt, as shown in Figure 22(c), occurs in accordance with the V-blank start timing that occurs every 16.667 mS = 1 / 60 second. This V-blank interrupt timing defines the start timing of the steady-state processing (ST5~ST14) of the performance control CPU 63, and also signifies the start timing of the display period for the display circuits 74A and 74B (the end timing of the previous display period).

[0398] Next, predetermined operation parameters (address values) are written to a predetermined display register RGij to determine the vertical display start position and horizontal display start position for each frame buffer FBa and FBb (SS36). As a result, the valid data area whose vertical and horizontal dimensions were determined in step SS34 is fixed on the frame buffers FBa and FBb. Here, the vertical display start position and horizontal display start position are relative address values ​​in each index space, and in the embodiment shown in Figure 22(e), the display start position is (0,0).

[0399] Here, "display area" refers to the index space (frame buffers FBa, FBb) from which the display circuits 74A and 74B should read image data in order to drive the display devices DS1 and DS2, and refers to either one of the double buffers in the frame buffers FBa and FBb, which are each double buffer structures. However, the display circuits 74A and 74B actually read image data only from the "effective data area" specified in steps SS30 and SS36 in display area (0) or display area (1).

[0400] Next, the display register RGij(DSPAINDEX) for the display circuit 74A that drives the main display device DS1 and the display register RGij(DSPBINDEX) for the display circuit 74B that drives the sub-display device DS2 are set to "display area (0)" and "display area (1)" respectively, thereby defining each display area (SS37).

[0401] In this embodiment, although not limited in any way, for the frame buffer FBa, the index space 254 of index number 254 in the VRAM arbitrary area (c) is defined as "display area (0)", and the index space 255 of index number 255 in the VRAM arbitrary area (c) is defined as "display area (1)" (SS37).

[0402] Furthermore, for the frame buffer FBb, the index space 251 of index number 251 in the arbitrary VRAM area (c) is designated as "display area (0)", and the index space 252 of index number 252 in the arbitrary VRAM area (c) is designated as "display area (1)" (SS37). It should be noted that defining the "display area" in the initial processing (SS3) is not particularly limited, and the display circuit 74 may toggle between the index spaces (display areas) to which it should READ access image data at each operation cycle δ. It is also preferable to zero-clear the respective display areas (0) and (1) of the frame buffers FBa and FBb at this timing, in which case no unnatural image will be displayed on the display device.

[0403] In this embodiment, once the initial setup including the above processes (SS30~SS37) is completed, a predetermined prohibition value is set in the first type prohibition setting register RGij to prevent the setting value in the predetermined system control register RGij from being changed by noise or other influences (first prohibition setting SS38).

[0404] Here, the settings that will be prohibited from being written in the future include: (1) the settings related to the display clock DCK of the display devices DS1 and DS2, (2) the settings related to the sampling clock of the LVDS, (3) the settings related to the selection operation of the output selection circuit 79, and (4) the synchronization relationship of the multiple display devices DS1 and DS2 (display circuit 74B being dependent on the operating cycle of display circuit 74A). Although there is a software process to release the first prohibition setting, it is not used in this embodiment. However, it is preferable to use it as needed.

[0405] Next, the VDP register RGij of the initial setup system is set to write-protected by setting a predetermined prohibition value in the second type prohibition setting register RGij (second prohibition setting SS39). Here, the registers that are prohibited include the VDP register RGij related to step SP4 and steps SS30 to SS37.

[0406] On the other hand, by setting a predetermined prohibition value in the third type of prohibition setting register RGij, it is also possible to prohibit a large number of VDP registers, including the VDP registers related to the setting process of steps SS1 to SS3 (third prohibition setting). However, this is not used in principle in this embodiment. In any case, the second prohibition setting and the third prohibition setting can be arbitrarily released by writing a release value to the predetermined release register RGij, and it is also possible to change the setting value during steady operation.

[0407] Once the above processes are complete, the next step, SP52 in Figure 21, checks the status register (4) to confirm that the initialization of the built-in VRAM 71, which has a defined refresh cycle, is complete and that the operation is stable (successful completion of initialization) (SS40).

[0408] Based on the values ​​in status registers (1) to (4), it is confirmed that the built-in VRAM 71, the display circuit 74, and the LVDS circuit 30 have all successfully completed their initialization processes. Next, by writing a predetermined value to the designated display register RGij (DSPACTL / DSPBCTL), the operation of the display circuits 74A and 74B is started (SS4a). Additionally, by writing a predetermined value to the designated system control register RGij (SYSDSPLVDS1MD / SYSDSPLVDS2MD), output data from the display circuit 74A is output from the LVDS circuit 80 (LVDS1 / LVDS2) (SS4b).

[0409] This operation is none other than the processing at timing T4 in Figure 6(e). In this embodiment, the program is designed so that the processing of steps SS4a to SS4b is executed within a predetermined time τ (for example, 20 mS) from timing T2. Then, in response to the start of operation of the display circuits 74A, 74B and the LVDS circuit 80 (timing T4), the timing timer TM is restarted from zero (SS4c). Note that the processing procedure of steps SS4a to SS4b is not necessarily limited. Even if the processing of steps SS4a to SS4b is executed in reverse order, the LVDS circuit 80 will only output useless image data for at most a moment, and since the backlight section BL is off, there is no problem.

[0410] In any case, in this embodiment, in response to the processing in steps SS4a to SS4b described above, the display circuit 74 enters the V-blank start state every 1 / 60 second, and the LVDS circuit (LVDS1 / LVDS2) 80 operates, causing the display operation shown in Figure 15 to be repeated. Note that in Figure 15, the start timing and end timing of the display operation, indicated by the circle, represent the V-blank start timing.

[0411] Based on this V-blank start timing, the horizontal reference point TH0 (=horizontal reference time) and the vertical reference point (=vertical reference time) TV0 in the operation of the display circuit 74 are defined, and the display circuit 74 waits without outputting image data corresponding to each pixel of the display device until the horizontal waiting time WTh has elapsed from the horizontal reference point TH0. Similarly, the display circuit 74 is configured to wait without outputting image data corresponding to each pixel of the display device until the vertical waiting time WTv has elapsed from the vertical reference point TV0.

[0412] Furthermore, since the display circuit 74B operates in synchronization with the display device 74A (SP4 in Figure 16), the start and end timings of the display operation for the sub-display device DS2 are the same as those for the main display device DS1. Therefore, the frame period for the sub-display device DS2 (519 × 867 / 27) is set to be shorter than the frame period for the sub-display device DS2 (1083 × 1662 / 108), so that the update process for the sub-display device DS2 is completed when the V-blank starts.

[0413] Once the processing of step SS4, which has the above significance, is completed, the system waits for 300 mS to elapse based on the timing timer TM (SS5), and then transitions the control signal PWM to the power supply control circuit SPY from L level to H level (SS6). As a result, the backlight unit BL becomes illuminated, and the liquid crystal display unit MONI, which started operating before this, starts displaying based on the image data received from the display circuit 74A. As explained earlier, since the display list has not yet been issued at this timing, the contents of the VRAM are displayed as is. Therefore, it is also preferable to delegate the processing of steps SS5 to SS6 to timer interrupt processing (see dashed line), and if such a configuration is adopted, the display list DL will have been issued by the time T5, so the display device DS1 will display a predetermined initial screen.

[0414] Next, the remaining part of the main processing, which consists of steady-state processing that is repeatedly executed at predetermined intervals, will be explained based on Figure 22. As shown in Figure 22, the operation of the performance control CPU 63 consists of the main control processing (a), a timer interrupt processing (b) that is started every 1 ms, a receive interrupt processing (not shown) that is started when a control command CMD is received, a VBLANK interrupt processing (c) that is started when a VBLANK signal occurs at the start timing of the V-blank (vertical retrace period) of the display device DS1 is received, and a drawing abnormality interrupt processing (d) that occurs when the operation freezes or when an unreasonable instruction command is detected. The explanation of the 20 μS interrupt processing will be omitted.

[0415] In the receive interrupt processing, the control command CMD received from the main control unit 21 is stored in a predetermined receive buffer so that it can be referenced in the main control processing (ST13), and processing is completed. In addition, in the VBLANK interrupt processing (Figure 22(b)), the interrupt counter VCNT is incremented for each VBLANK interrupt (ST15), and at the start timing of the main control processing, the interrupt counter VCNT is reset to zero after determining the start timing of 1 / 30th of a second based on the value of the interrupt counter VCNT (ST4).

[0416] On the other hand, as shown in Figure 22(b), the timer interrupt processing includes the processing of lamp and motor effects (ST18) and the sensor signal acquisition processing (ST19) which acquires the origin sensor signals SN0 to SNn and the chance button signal. The lamp and motor effects are controlled based on an effect scenario that centrally manages all effect operations, and when the effect counter EN reaches the start of an effect, the motor drive table and lamp drive table are identified in the effect scenario update processing (ST11).

[0417] Subsequently, the motor effects proceed based on the identified motor drive table, and the lamp effects proceed based on the identified motor drive table. As explained earlier, there are also embodiments in which the DMAC circuit (first and second DMA channels) 60 functions when step ST18 is performed. Note that the motor effects proceed every 1 ms, while the lamp effects proceed at appropriate intervals longer than 1 ms.

[0418] On the other hand, as shown in Figure 22(d), the drawing error interrupt handler identifies the cause of the interrupt by READ accessing the status register RGij, which indicates the operating state of the drawing circuit 76. Specifically, it identifies whether (1) the drawing error interrupt is due to the detection of an abnormal instruction command (bit corruption) or (2) the drawing error interrupt is due to an operational abnormality (freeze) of the drawing circuit 76 (ST16a). If the drawing error interrupt is based on the detection of an abnormal instruction command, the drawing circuit 76 is initialized by writing a predetermined value to a predetermined system control register RGij (ST16b). This operation is none other than the individual reset operation of the reset path 4B shown in Figure 7(b).

[0419] Next, after confirming the successful completion of the individual reset operation in a predetermined status register RGij, a set of operating parameters that define the operation of the drawing circuit 76 are reset in the predetermined drawing register RGij, and the process ends (ST16c). Then, after adjusting the stack area that stores the return address (release process that erases the return address after interrupt processing), the process proceeds to step ST13 (ST16c).

[0420] On the other hand, in the case of a drawing error interrupt due to an operational abnormality of the drawing circuit 76, the process transitions to an infinite loop (ST16d), activating the WDT circuit 58 and resetting the entire composite chip 50. If it is not desired to reset the CPU circuit 51, a predetermined keyword sequence can be output to the pattern check circuit CHK, and only the VDP circuit 52 can be reset by the reset signal RST (see Figure 7(b)). In this case, after confirming the successful completion of the reset operation of the VDP circuit 52, the process proceeds to steps ST4 and ST13. In order to avoid missing control command CMD readings as much as possible, it is better to proceed to step ST13 rather than step ST4, including in other cases.

[0421] Resetting the entire composite chip 50 erases all previous effects and returns the effect control to its initial state (power-on state). However, if only the VDP circuit 52 is reset, a predetermined waiting time occurs until the reset operation of the VDP circuit 52 is completed, but the series of effect controls can be continued. Furthermore, since the effect control CPU 63 controls image effects, lamp effects, and sound effects in a unified manner, there are no unnatural discrepancies in each effect.

[0422] The initial setup processes described above in steps SS1 to SS3 are executed based on the initial value setting table SETTABLE (see Figure 36), which associates the register address value of the VDP register RGij with the value set for that register RGij. Having explained the initial setup process, before explaining the steady-state processing (ST4 to ST14), we will briefly explain the steady-state operation (intermittent operation) of the VDP circuit 52 controlled by the performance control CPU 63 based on Figures 30(a) and 31(b).

[0423] The intermittent operation of the VDP circuit 52 is as shown in Figures 30 and 31. In an embodiment where the preloader 73 is not used, as shown in Figure 30(a), the display list DLi completed by the performance control CPU 63 is issued to the drawing circuit 76 in its operation cycle (T1). The drawing circuit 76 completes the image data in the frame buffers FBa and FBb based on the display list DLi. The image data completed in the frame buffers FBa and FBb is then output by the display circuit 74 to the display devices DS1 and DS2 in the next operation cycle T1+δ, resulting in the display screen perceived by the player based on the subsequent drawing operations of the display devices DS1 and DS2.

[0424] On the other hand, in the embodiment using the preloader 73, as shown in Figure 31(a), the display list DLi completed by the performance control CPU 63 is issued to the preloader 73 in its operating cycle (T1). The preloader 73 interprets the display list DLi, performs the necessary pre-read operations, and rewrites a portion of the display list DLi to complete the rewrite list DL'. The pre-read CG data and the rewrite list DL' are stored in the appropriate locations in the DRAM 54.

[0425] Next, in the following operating cycle (T1+δ), the drawing circuit 76 obtains the rewrite list DL' from the DRAM 54 and completes the image data in the frame buffers FBa and FBb through drawing operations based on the rewrite list DL'. Then, in the following operating cycle (T1+2δ), the display circuit 74 outputs the completed image data in the frame buffers FBa and FBb to the display devices DS1 and DS2, which then become the display screen perceived by the player based on the subsequent drawing operations of the display devices DS1 and DS2.

[0426] The intermittent operation of the VDP circuit 52 has been briefly explained above. In order to realize the operation shown in Figures 30 to 31 above, the performance control CPU 63, after the initial processing (SS1 to SS3), repeatedly checks the value of the interrupt counter VCNT and waits for the start timing to be reached. Once the start timing (the V-blank start timing, skipping one position) is reached, the interrupt counter VCNT is reset to zero (ST4).

[0427] Subsequently, steady-state operation begins, but in this embodiment, it is first determined whether the conditions for starting steady-state operation are met (ST5). The timing of this determination is the timing of T1, T1+δ, T1+2δ, ... shown in Figures 30 to 31, that is, the start timing of the vertical blank period (VBLANK) of the display device DS1. The display timing of the display device DS2 is set to be dependent on the display timing of the display device DS1 during the initial setup (ST3).

[0428] The operation start condition, which is determined at the start timing of the vertical blanking period (VBLANK), differs depending on whether or not the preloader 73 is used. Therefore, we will first explain the embodiment in which the preloader 73 is not used (Figure 22). In this case, the circuit configuration and program are designed so that the internal operation of the VDP proceeds as shown in the time chart of Figure 30(a). That is, based on the display list DL1 completed in the operation cycle (T1), the drawing circuit 76 should complete the drawing operation within that operation cycle (T1 to T1+δ). However, it is not impossible that the drawing operation may not be completed within that operation cycle (T1+2δ to T1+3δ), for example, as in the display list DL3 completed in the operation cycle (T1+2δ) in Figure 30(a). Furthermore, regarding the display circuit 74, there is a possibility that an Underrun error occurs where the generation of display data does not keep up with the display timing.

[0429] The determination process in step ST5 takes such a situation into consideration, and the performance control CPU 63 accesses the status register RGij (a type of control register group 70) which indicates the operating state of the drawing circuit 76, and determines at the timing of step ST5 whether the drawing circuit 76 has completed the necessary operations and whether there is an underrun error. The presence or absence of an underrun error is determined based on the underrun counters URCNTa~URCNTc. In an embodiment that does not utilize the preloader 73, for example, at timing T1+δ in Figure 30(a), the status information of the drawing registers related to the drawing circuit 76 is accessed via READ to confirm that the drawing operation based on the display list DL1 has finished.

[0430] If the conditions for starting operation are not met (abnormal / non-compliant), the abnormality flag ER, which counts the number of abnormalities, is incremented, and steps ST6 to ST8 are skipped. The abnormality flag ER, along with other serious abnormality flags ABN, is checked in steps ST9 and ST10. Assuming that the serious abnormality flag ABN is in a reset state, if the number of consecutive abnormalities is not large (ER ≤ 2), the performance command analysis process is executed as in the normal state (ST13).

[0431] Similarly, in the case of an Underrun error, steps ST6 to ST8 are skipped. Then, the display clock DCK (frequency) and the display circuit 74 are initialized by writing a predetermined clear value to a predetermined system control register RGij (ST10c). After confirming the successful completion of this initialization process, the frequency of the display clock DCK and the values ​​of a group of system control registers RGij that define the operation of the display circuit 74 are reset to their predetermined values ​​(ST10c), and then the performance command analysis process is executed (ST13).

[0432] In the performance command analysis process (ST13), it is determined whether or not a control command CMD has been received from the main control board 21. If a control command CMD has been received, the control command CMD is analyzed and the necessary processing is executed (ST13). The necessary processing here includes the preparation process for starting a new variable performance based on a control command CMD that instructs the start of a variable performance, and the start of error notification based on a control command CMD that indicates an error has occurred. Subsequently, a clear pulse is output to the WDT circuit (ST14), and the process returns to step ST4.

[0433] The above describes the case of minor Underrun errors or when the operation start conditions are not met, and the error flag ER is ER≦2. In such cases, the process of toggling the display area read by the display circuit 74 (ST6) and the process of creating the display list (ST7) are skipped during that operation cycle, and the presentation scenario does not proceed (see ST8~ST12). This is to prevent the output of incomplete image data from frame buffers FBa and FBb. Therefore, for example, in the operation cycle (T1+3δ) in Figure 30(a), the image presentation does not proceed, and a frame drop occurs in which the original screen (screen based on DL2) is redisplayed.

[0434] Here, in order to avoid frame drops, a configuration that waits until the operation start condition is satisfied can also be considered. However, since there are many control processes (ST6 to ST12) that the production control CPU 63 should execute and it is necessary to ensure the processing time for each, in this embodiment, frame drops are caused when the operation start condition is not satisfied.

[0435] However, even if a frame drop occurs, compared to the lamp production and motor production that proceed by the interrupt processing (Fig. 22(b)), the progress of the image production is only delayed by about 1 / 30 to 2 / 30 seconds, and the player will not notice this. Moreover, when a frame drop occurs, the production scenario processing (ST11) including the update processing of the production counter EN and the voice progress processing (ST12) are also skipped together, so in the reach production, notice production, and accessory production that are started thereafter, there is no possibility that the start timings of the image production, voice production, lamp production, motor production, etc. will deviate.

[0436] That is, in the production scenario, the start timings of the image production, voice production, lamp production, and motor production, and the production content to be executed thereafter are managed integrally, and the start timings are controlled by the production counter EN that is updated only during normal times, so the synchronization of various productions does not deviate. For example, when there is a production operation that combines an explosion sound, an explosion image, accessory movement, and a lamp flash operation, even after a frame drop occurs, the above-described production operations start correctly in synchronization.

[0437] As described above, relatively minor abnormalities have been explained. However, when the serious abnormality flag ABN is in the set state, when the number of consecutive abnormalities is large (ER > 2), or when repeated Underrun abnormalities occur, after the determination in step ST10, an infinite loop state is set (ST10b). As a result, the timing operation of the WDT circuit 58 proceeds, and the composite chip 50 including the production control CPU 63 is abnormally reset, and thereafter, by re-executing the initial processing (SS1 to SS3), it is expected to eliminate the root cause of the occurrence of the abnormal situation.

[0438] Note that this reset operation is performed by activating the WDT circuit 58, so the entire composite chip 50, including the CPU circuit 51, enters a reset state (Figure 7(b)). Therefore, in order to avoid resetting the CPU circuit 51, it is also preferable for the performance control CPU 63 to output a predetermined keyword sequence (for example, three 1-byte data) to the pattern check circuit CHK and output a reset signal RST to the VDP circuit 52 (see ST100 in Figure 36). In this case as well, after confirming the successful completion of the reset operation of the VDP circuit 52 (ST101), the process will proceed to steps ST4 and ST13.

[0439] In any case, when this abnormality occurs, the audio circuit SND is also reset, so the image effects, sound effects, lamp effects, and motor effects will all return to their initial state. However, these reset operations do not affect the main control unit 21 or the payout control unit 25, so there is no risk of situations such as the disappearance of the jackpot state or the loss of prize balls.

[0440] The above describes abnormal situations, but in reality, such abnormalities rarely occur, even in minor cases. After the processing in step ST5, the "display area" of the frame buffers FBa and FBb, which store the image data to be read by the display circuits 74A and 74B, is toggled (ST6) based on the setting of the predetermined display register RGij (DSPACTL / DSPBCTL). As explained earlier, "display area (0)" and "display area (1)" are defined in advance during the initial processing (ST3), so in the processing of step ST6, the system identifies whether the current "display area" for the frame buffers FBa and FBb is display area (0) or display area (1).

[0441] When step ST6 is executed, the display circuit 74A drives the display device DS1 by alternately reading image data from index space 254 (display area (0)) and index space 255 (display area (1)) at each operation cycle δ. Similarly, the display circuit 74B drives the sub-display device DS2 by alternately reading image data from index space 251 (display area (0)) and index space 252 (display area (1)) at each operation cycle δ. As explained earlier, the display circuit 74 actually performs READ access only to the valid data area in display area (0) / display area (1).

[0442] In any case, in this embodiment, the "display area" switches with each operation cycle, so the display circuits 74A and 74B start outputting the image data completed by the drawing circuit 76 in the previous operation cycle to the display devices DS1 and DS2. However, since the processing in step ST5 starts from the beginning of the vertical retrace period (V-blank) of the main display device DS1, in reality, the output processing of the image data starts after the vertical retrace period is completed. In Figure 30(a), the arrows shown in the display circuit column indicate the operation cycle of this output processing.

[0443] Once the processing of step ST6, which has the significance described above, is completed, the performance control CPU 63 then completes the display list DL, which identifies the image data that the display circuit 74 should output to the display device, in the next operation cycle (ST7). Although not particularly limited, in this embodiment, a list buffer area (DL buffer BUF) of RAM 59 is allocated and the display list DL is completed there (see Figure 13).

[0444] The display list DL is composed of a series of instruction commands listed in an appropriate order, and is configured to end with an EODL (End Of DL) command. In this embodiment, in order to ensure the smooth operation of the data transfer circuit 72, the drawing circuit 76, and the preloader 73, all instruction commands, including the EODL command, are limited to instruction commands whose command length is a multiple of a 32-bit integer N (N>0). As explained earlier, instruction commands composed of a multiple of a 32-bit integer N may include a "Don't Care Bit".

[0445] Thus, since the display list DL in this embodiment consists only of instruction commands with a command length of an integer N times (N>0) of 32 bits, the total data volume value (total data amount) of the entire display list DL is always an integer multiple of the smallest unit of command length (32 bits = 4 bytes). Furthermore, in this embodiment, taking into account the minimum data amount Dmin of the data transfer circuit 72, the data volume value of the display list DL is adjusted to be an integer multiple (1 or more) of the minimum data amount Dmin, and also an integer multiple of the smallest unit of instruction command (4 bytes). For example, if Dmin = 256 bytes, the data volume value of the display list DL will be adjusted to one of the following values: 256 bytes, 512 bytes, etc.

[0446] Here, depending on the complexity of the performance content, it is also preferable to adjust the data volume to 256 bytes or 512 bytes as appropriate. However, in this embodiment, considering that there are two display devices and the sub-display device DS2 does not perform particularly complex image performances, the data volume value of the display list DL is always adjusted to 256 bytes.

[0447] However, this method is not limited in any way, and in the case of gaming machines that use three or more display devices, or that perform complex image effects including the sub-display device DS2, the data volume can be adjusted to 512 bytes or 768 bytes. In addition, it is also preferable to adjust the data volume value of the display list DL to 256 bytes during normal effects, and to adjust the data volume value of the display list DL to 512 bytes or 768 bytes only when performing special effects.

[0448] However, in this embodiment, the data volume value of the display list DL is adjusted to a predetermined byte length (256 bytes) in each operation cycle δ. Possible adjustment methods include a simple method (A) in which a 32-bit NOP (No Operation) command is inserted after a 32-bit EODL command to fill in the missing area, or a standard method (B) in which the missing area is filled with a 32-bit NOP command, and then a 32-bit EODL command is written at the end. Alternatively, an unadjusted method (C) can be considered in which the data volume value (total data amount) of the display list DL is not adjusted at all and the process is terminated with the EODL command, and dummy data is additionally transferred when the data transfer circuit 72 is operating to ensure a transfer amount that is an integer multiple of the minimum data amount Dmin.

[0449] In this case, if the standard method (B) is adopted, the command counter CNT is initially initialized to a predetermined value (64-1 corresponding to 256 bytes), and each time a significant instruction command is written to the DL buffer area BUF, the command counter CNT is decremented accordingly. Once the writing of a series of significant instruction commands is complete, NOP commands are written until the command counter CNT becomes zero, and finally the EODL command is written. In this embodiment, since the instruction commands are limited to those whose command length is a multiple of a 32-bit integer N (N>0), the above processing is straightforward, and the decrementing of the command counter CNT is a decrementing process corresponding to the integer N.

[0450] On the other hand, when using the simplified method (A), it is sufficient to fill the entire list buffer area (DL buffer BUF) with NOP commands when creating the display list DL, which at first glance seems superior to the standard method (B). Also, from the standpoint of simplicity, the unadjusted method (C) also seems superior. However, in this embodiment, the standard method (B) is basically adopted, and the amount of actual data from the beginning of the display list DL to the EODL command, that is, the amount of data up to the EODL command, is always adjusted to be an integer multiple of the minimum data amount Dmin of the data transfer circuit 72.

[0451] This is based on an example that utilizes the preloader 73. If the simplified method (A) or the unadjusted method (C) were adopted, the actual amount of data in the display list DL up to the EODL command would be a random value, causing problems when the rewritten list DL' rewritten by the preloader 73 is transferred to the DRAM 54, and when the rewritten list DL' is transferred from the DRAM 54 to the drawing circuit 76. Note that when the rewritten list DL' is transferred to the DRAM 54, the ChA control circuit 72a of the data transfer circuit 72 functions, and when the rewritten list DL' is transferred to the drawing circuit 76, the ChB control circuit 72b functions (see Figure 28). However, in either case, only the rewritten list DL' up to the EODL command is transferred.

[0452] The advantages of the standard method (B) for adjusting the data volume value of the display list DL have been explained above. However, in embodiments that do not use the preloader 73, the issued display list DL is only processed by the drawing circuit 76, so there is no prohibition against using the simplified method (A) or the unadjusted method (C).

[0453] However, in the following explanation, regardless of whether or not the preloader 73 is used, the standard method (B) will be adopted as a general rule, and the details of the display list DL will be explained based on Figure 23.

[0454] While not particularly limited, in this embodiment, the display list DL first contains a sequence of instruction commands (L11-L16) related to the main display device DS1, and then a sequence of instruction commands (L17-L20) related to the sub-display device DS2. Furthermore, the standard method (B) is employed to adjust the data volume value of the display list DL to a fixed length (256 bytes). Figure 23 also effectively illustrates the procedure by which the performance control CPU 63 writes instruction commands to the list buffer area of ​​the RAM 59, and the operation of the drawing circuit 76 based on the display list DL.

[0455] As shown in Figure 23, the beginning of the display list DL contains an environment setting instruction command (SETDAVR) to specify the top-left base address (X,Y) on the index space IDX for the frame buffer FBa of the display device DS1 (L11). As explained with respect to Figure 12(a), in this embodiment, a pair of frame buffers FBa are reserved in an arbitrary area (c) for the display device DS1. Normally, the base address (X,Y) = (0,0) is set to correspond to the effective data area for the display circuit 74, and the frame buffer FBa is utilized by the drawing circuit 76 from its starting position.

[0456] In Figure 12(c), the actual drawing area in the lower left is labeled L11. This indicates that the instruction command L11 has identified the actual drawing area on the frame buffer FBa as starting from the base address (0,0) of the frame buffer FBa. However, the vertical and horizontal dimensions of the actual drawing area and the index number that specifically identifies it are not yet determined and will be determined by the instruction command (SETINDEX) L13, which will be described later. The instruction command L11 also specifies whether or not to use the Z buffer.

[0457] Next, the environment setting command (SETDAVF) is used to set the top-left corner coordinates (Xs, Ys) and the bottom-right diagonal point coordinates (Xe, Ye) in the virtual drawing space, defining a drawing area with W×H dimensions (L12). Here, the virtual drawing space is a virtual two-dimensional space with a range of ±8192 in the X direction and ±8192 in the Y direction that can be drawn using drawing command instructions (such as the SPRITE command) (see Figure 12(c)).

[0458] The instruction command L12 (SETDAVF) divides the virtual drawing space into a drawing area where the drawing content is actually reflected on the display device DS1, and other non-drawing areas. Furthermore, the instruction command L12 (SETDAVF) associates the actual drawing area, whose starting position (base address) is defined by instruction command L11, with the drawing area in the virtual drawing space.

[0459] To put it another way, the instruction command L12 defines a W×H actual drawing area in the frame buffer FBa (whose index space is undetermined), starting from the base address and corresponding to the drawing area in the virtual drawing space. Therefore, the drawing area specified by the instruction command L12 must be the same as or smaller than the horizontal size of the frame buffer FBa. Typically, the drawing area and the actual drawing area are defined to have the same dimensions as the effective data area for the display circuit 74 (Figure 22(e)).

[0460] After the drawing circuit 76 executes instruction commands L11 and L12, only the drawing content within the drawing area of ​​the virtual drawing space will be reflected in the actual drawing area of ​​the frame buffer FBa. Therefore, the drawing content of parts that extend beyond the drawing area, or the part labeled as the work area in Figure 12(c), will not be reflected in the frame buffer as is. When a work area is to be allocated in the virtual drawing space, the non-drawing area of ​​the virtual drawing space is used.

[0461] Next, in the current operation cycle, the drawing circuit 76 specifies where the drawing content to be drawn based on the display list DL to be completed should be drawn (L13). Specifically, for the frame buffer FBa of the double-buffered display device DS1, the index space IDX, which will be the "write area" for the drawing content based on the current display list DL, is identified (L13). Specifically, the SETINDEX command, which is a texture setting command, specifies that (1) the frame buffer FBa is allocated in an arbitrary area, and (2) the index space IDX will be the "write area". N An index number N in an arbitrary region is identified.

[0462] If, for example, N=255 is specified by this instruction command L13, the actual drawing area corresponding to the drawing area defined on the virtual drawing space is specifically the index space IDX in the double-buffered frame buffer FBa. 255 This is how it is defined.

[0463] In this embodiment, the index number of the frame buffer FBa is either 255 or 254 (Figure 12(a)), and one of these is selected via a toggle (L13). This index number is the index number other than the display area (0) / (1) specified in step ST6 of the main control processing. For example, if display area (0) is specified for the display circuit 74 in step ST6, then display area (1) becomes the "write area" for the drawing circuit 76.

[0464] As described above, after the correspondence between the actual drawing area (the logical space of W x H) and the drawing area (the virtual space of W x H) is generally defined by instruction commands L11 and L12, the instruction command L13 (SETINDEX), which specifically identifies the index space IDX, associates the virtual space of W x H with the logical space of W x H in that particular index space IDX.

[0465] To put it another way, in the future, based on a series of instruction commands, the content virtually drawn in the W×H virtual space will become image data in the built-in VRAM71 (frame buffer), based on a conversion table within the VDP that defines the correspondence between the virtual space and the actual addresses of the built-in VRAM71.

[0466] Next, a command is included to instruct the execution of a frame buffer clear process, which involves, for example, filling the specified index space IDX with black, as the "write area" (L14, L15). This is nothing more than the process of erasing image data written to the frame buffer FBa two operation periods prior.

[0467] Specifically, the SETFCOLOR command, a type of environment setting command, is used to select, for example, black, and the RECTANGLE command, a primitive drawing command, is used to specify that a rectangular area should be filled. The RECTANGLE command specifies the XY coordinates of the top-left and bottom-right endpoints of the drawing area set in the virtual drawing space (the virtual space corresponding to the frame buffer FBa) (see Figure 12(c)).

[0468] With the above processing complete, the rendering preparation process is finished. Next, we list the command instructions for rendering appropriate textures, such as still images or single frames of video, into the virtual rendering space. Typically, first, the index space IDX to which the textures will be deployed is identified using the texture setting command SETINDEX. Then, the TXLOAD command, which is a texture loading command, is written to specify the display list DL to deploy the predetermined texture read from CGROM55 into the predetermined index space IDX.

[0469] As explained earlier, in this embodiment, the background video is composed of IP stream video. Therefore, for example, regarding the background video, the index space IDX to be expanded is identified as IDX0 of page area (b) using the texture setting system's SETINDEX command, and then the texture loading system's TXLOAD command is written. Note that the TXLOAD command requires specifying the starting address of CGROM55 (the texture source address) and the data size after expansion (horizontal × vertical) for the video frame to be loaded.

[0470] In the VDP circuit 52, when the above TXLOAD command is executed, one video frame (texture) of the background video is first acquired in the AAC area (a), and then automatically expanded into the index space IDX0 of the page area (b) by the GDEC75, which is launched automatically. Next, this video frame is drawn to the virtual rendering space. In this case, it is also possible to set "the index space IDX0 of the page area (b) is the texture to be processed" using the SETINDEX command (texture setting system), but if processing is performed consecutively with the TXLOAD command, the description of this SETINDEX command can be omitted.

[0471] In any case, with the index space IDX0 of page area (b) identified as the texture to be processed next, appropriate inter-draw operation commands are then written, such as setting parameters for alpha blending. Alpha blending is a process that involves transparency / semi-transparency between an image already written in the drawing area (frame buffer FBa) and the image to be overwritten. Therefore, in the first drawing operation, such as for a video frame of a background video, it is not necessary to use inter-draw operation commands.

[0472] Next, we will write the SPRITE command, which is a command for instructing primitive drawing systems, to draw the texture of index space IDX0 in page area (b) (a video frame from the background video) to the appropriate location (rectangular Destination area) in the virtual drawing space. Note that the SPRITE command requires specifying the upper left and lower right endpoints of the Destination area in the virtual drawing space.

[0473] This Destination area is the entirety or a part of the drawing area (a virtual space defined on the virtual drawing space) that has been previously associated with the actual drawing area (FBa) by instruction commands L11 and L12. However, since background videos are usually drawn across the entire display screen, in such cases the Destination area will be the entirety of the drawing area or more. Note that the Destination area is larger than the entire drawing area when, for example, the background video is zoomed in.

[0474] With the above processing complete, the rendering of the background video frames is finished. Next, the display list DL is constructed to render various textures by listing instruction commands such as texture loading, texture setting, inter-rendering calculation, and primitive rendering commands in an appropriate order and overlaying them on the background video. As explained earlier, a large number of videos are required during variable effects, so in that case, the index table control instruction command (NEWPIX) is written to increase the index space IDX in the page area (b) of the built-in VRAM 71.

[0475] For example, with respect to the second IP stream video, the NEWPIX command allocates an additional index space IDX1 in the page area (b), then identifies this index space IDX1 (SETINDEX), instructs the system to unpack one frame of the second video (TXLOAD), and places the unpacked texture in the appropriate location in the rendering area (SPRITE). Typically, the Destination area in this case becomes part of the rendering area.

[0476] The same applies to the following, and the NEWPIX command successively generates the index space IDX k After securing the necessary space, if multiple IP streams are drawn to the rendering area while performing appropriate alpha blending, the content drawn to the rendering area will be sequentially accumulated as image data in the frame buffer FBa, which is the actual rendering area. When multiple N IP stream videos are being drawn, multiple N index spaces are functioning in the page area (b).

[0477] Then, when the series of fluctuation effects has finished, the numerous index spaces IDX1~IDX reserved in the page area (b) k To free up any unnecessary index spaces (IDX), you can use the DELPIX command to delete them.

[0478] When rendering still images or I-stream videos, the SETINDEX command specifies that the decoding destination for these textures is the AAC region (a), and then the TXLOAD command is executed. The textures obtained in the AAC region (a) are then automatically expanded into the ACC region (a) by GDEC75. The expanded textures can then be rendered in the appropriate location on the rendering area using the SPRITE command. Depending on whether or not the cache hit function is utilized, either the first AAC region (a1) or the second AAC region (a2) will be used.

[0479] In the explanation so far, each texture is drawn directly to the drawing area of ​​the main display device DS1, but the operation is not necessarily limited to this. For example, by creating an appropriate drawing area that does not overlap with the drawing area already reserved for the display device DS1 (Figure 12(c)), and associating this drawing area with the working area of ​​the built-in VRAM 71, an intermediate drawing area can be constructed to complete the appropriate visual effect image. The reason for ensuring that the drawing area does not overlap with the drawing area for the display device DS1 is that, in the case of overlapping areas, the later association setting takes precedence, and the contents drawn to that area are not reflected in the frame buffer FBa.

[0480] As shown in Figure 12(c), the work area in this embodiment is the index space IDX0 in the arbitrary area (c). At the timing of the performance that uses this work area, a sequence of instruction commands (SETDAVR, SETDAVF, SETINDEX) is pre-programmed to map the drawing area for the performance image (see Figure 12(c)) to the work area (the actual drawing area of ​​the index space IDX0). As shown in Figure 12(c), the drawing area for the performance image is reserved in an area not included in the drawing area for the main display device DS1.

[0481] Then, a series of instruction commands similar to the instruction command sequence L16 for the frame buffer FBa are listed to complete the appropriate animation image in the index space IDX0. In this embodiment, since the animation image consists of still images, an instruction command (SETINDEX) is written to expand the decoded data into the first AAC area (a1), and then a primitive drawing system instruction command (SPRITE) is used with the appropriate location in the drawing area of ​​the index space IDX0 as the Destination. This operation is repeated once or multiple times depending on the animation content.

[0482] Then, after positioning the completed image in index space IDX0 as a texture (SETINDEX), the image (texture) from index space IDX0 can be drawn to the appropriate location in the drawing area of ​​the main display device DS1 using the SPRITE command. In such cases, it is conceivable to decompose the image in index space IDX0 into triangular drawing primitives, rotate them to appropriate angles, and then draw them in the drawing area. The rotation angle of the texture can be associated with, for example, the reliability of the preview effect.

[0483] The above describes the instruction command sequence (L11~L16) for completing one frame of the main display device DS1, and the same applies to the instruction command sequence (L17~L12) for completing one frame of the sub-display device DS2. Specifically, the starting XY coordinates of the frame buffer FBb are identified (L17) and defined (usually X=0,Y=0), and a drawing area for the sub-display device DS2 is defined on the virtual drawing space shown in Figure 12(c) (L18).

[0484] Incidentally, in this embodiment, after the generation of image data for the main display device DS1 is completed, the process moves on to the generation process for the sub-display device DS2. Therefore, even if the drawing area for the sub-display device DS2 overlaps with the drawing area for the main display device DS1, there is no problem, and the drawing area can be freely set. For this reason, when developing the program for generating the display list DL, for example, when applying an appropriate texture to a newly set drawing area using the SPRITE command, the settings of the SPRITE command's operation parameters (Destination area) and other settings can be standardized to some extent.

[0485] Once the definition of such arbitrary drawing areas is complete (L18), the next step is to identify the index space IDX, which will be the "write area" for the drawing content based on the display list DL, for the frame buffer FBb of the double-buffered display device DS2 (L19). The index number of this index space IDX is the index number that does not correspond to the display area (0) / (1) specified in step ST6 of the main control process for the frame buffer FBb.

[0486] Then, the command sequences L20-L22 for the sub-display device DS2 are listed in the same way as the command sequences L14-L16 for the main display device DS1. Furthermore, the completed animation image can also be used in the index space IDX0.

[0487] In this embodiment, all instruction commands L11 to L22 that constitute the display list DL are limited to commands with a command length that is an integer multiple of 32 bits. As explained earlier, the data volume value (total data amount) of the display list DL in this embodiment is adjusted to a fixed length (256 bytes), and after adding the necessary number of dummy NOP commands (L23), it is terminated with an EODL command (L24). In other words, the embodiment in Figure 23 employs the standard method (B) described above.

[0488] However, even when adopting the standard method (B), it is not necessarily required to fix the total amount of data in the display list DL to 256 bytes in all operation cycles. That is, in another embodiment, if the total amount of data in the display list DL excluding NOP commands exceeds 256 bytes (for example, during special performance periods), the total amount of data in the display list DL is adjusted to 512 bytes or more, or N × 256 bytes, by adding NOP commands. As explained earlier, when adopting the standard method (B), the end of the N × 256 bytes is terminated with an EODL command.

[0489] The configuration of the display list DL has been explained in detail above. The performance control CPU 63 will then issue the completed fixed-byte length display list DL to the VDP circuit (ST7~ST8). Figure 24 is a flowchart illustrating the DL issuance process (ST8 in Figure 22) in which the performance control CPU 63 directly WRITE accesses the transfer port register TR_PORT of the transfer circuit 72 and issues the display list DL to the drawing circuit 76. Note that the transfer port register TR_PORT is a type of data transfer register RGij that defines the operation of the data transfer circuit 72.

[0490] To implement the DL issuance process, it is first necessary to set the required values ​​in the multiple data transfer registers RGij that define the operation of the data transfer circuit 72. Specifically, the transfer operation mode of the data transfer circuit 72 and the transmission route within the data transfer circuit 72 are specified in the predetermined data transfer registers RGij. The settings are not particularly limited, but here, it is set that the data is transferred from the CPUIF unit 56 via the ChB control circuit 72b, and that the CPU bus control unit 72d performs the data transfer operation while checking the remaining amount of its FIFO buffer (ST20). In the following explanation, the ChB control circuit 72b may be abbreviated as "transfer circuit ChB" for convenience.

[0491] Next, the total transfer size is set to a predetermined data transfer register RGij. As explained earlier, in this embodiment, the total amount of data in the display list DL is adjusted to an integer multiple of 256 bytes, so that value is set. Note that the total data amount = 256 × N is also an integer N multiple of the minimum data amount Dmin of the data transfer circuit 72. Normally, the multiple N is 1 or 2, but in the following explanation, we will assume N=1.

[0492] Here, since the transfer port register TR_PORT (hereinafter sometimes abbreviated as transfer port) is a 32-bit register, the performance control CPU 63 will perform a register WRITE operation on the transfer port TR_PORT every 32 bits. Therefore, the value of the management counter CN, which manages the number of register WRITE operations, is initialized to 64 (ST21). If the no-adjustment method (C) is adopted, the data transfer amount, which is an integer multiple of the minimum data amount Dmin, is determined at this time and the management counter CN is set accordingly.

[0493] With the initial setup completed by the above process, the next step is to set the data transfer operation via the transfer circuit ChB to the start state (ST22), and to start the drawing operation based on the setting value of a predetermined drawing register RGij that defines the operation of the drawing circuit 76 (ST23). As a result, the performance control CPU 63 is then able to ensure that the drawing circuit 76 (display list analyzer) performs a quick and smooth analysis of the instruction command sequence that the transfer port TR_PORT WRITE register operation WRITE.

[0494] Furthermore, the fact that the instruction commands listed in the display list DL are limited to instruction commands with a command length that is a multiple of a 32-bit integer also contributes effectively to the rapid and smooth Analyze processing. Timings t1, t2, t3, and t4 in Figure 30(a) indicate the operation timing of step ST23. Note that the issuance process of the display list DL (ST8) is completed quickly, so the time required for the issuance process is not shown in Figures 30 to 31.

[0495] Next, it is checked whether the settings in step ST22 have functioned correctly (ST24). This is because the initial settings of each part of the data transfer circuit 72 take longer to process than the register WRITE operation (setting operation) by the performance control CPU 63, and no further instructions are given to the data transfer circuit 72 if it is in an incomplete state. If, for any reason, the system does not start up even after waiting for a predetermined time, the critical error flag ABN is set and the DL issuance process is terminated (ST25). As a result, the WDT circuit 58 then functions, and the composite chip 50 is abnormally reset (ST10).

[0496] As mentioned above, the performance control CPU 63 may output a predetermined keyword sequence to the pattern check circuit CHK to avoid resetting the CPU circuit 51, and then perform an abnormal reset of only the VDP circuit 52 based on the reset signal RST.

[0497] However, since the setup in step ST22 is usually completed quickly, the CPU bus control unit 72d then checks that the FIFO buffer (32 bits x 130 rows) is not full (ST26), and then writes instruction commands to the transfer port TR_PORT line by line, starting from the first line that makes up the display list DL (ST28).

[0498] Then, while decrementing the management counter CN (ST29), the process of steps ST26 to ST29 is repeated (ST30) until the management counter CN becomes zero. In this embodiment, since a minimum data amount Dmin is defined for the data transfer circuit 72, the data transfer operation is executed when the minimum data amount Dmin is accumulated in the FIFO buffer, resulting in an intermittent transfer operation.

[0499] In any case, in this embodiment, the DL issuance process (ST28) is completed quickly. However, if, for any reason, the settings in the VDP register RGij become inconsistent due to noise or other factors, the FIFO buffer Full state may not be resolved even after waiting for a predetermined time during the determination in step ST26. In such cases, initialization data is set in the predetermined VDP register RGij to initialize the drawing circuit 76 and the data transfer circuit 72, and then the critical error flag ABN is set to end the DL issuance process (ST27).

[0500] By this time, the data transfer circuit 72 and the drawing circuit 76 have already started operating and completed a certain amount of processing. Therefore, the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial state, (3) initializing GDEC 75, and (4) initializing the cache state of the AAC area, while maintaining the contents of the drawing register RGij. Similarly, the initialization process of the data transfer circuit 72 includes the initialization process of the entire data transfer up to that point, such as clearing the FIFO buffer. As a result, the status information indicating the operating state of the data transfer circuit 72 changes to a predetermined value (a value indicating that the entire data transfer is being initialized).

[0501] In the initialization process of step ST27 described above, the contents of the drawing register RGij were maintained, but the contents of certain drawing registers may be initialized. The certain drawing registers that are cleared to their initial values ​​include (a) an execution control register that sets the start of drawing execution (see ST23 in Figure 24), (b) a status register that shows the execution status of the drawing circuit 76, and (c) a status register that identifies the position of the display list currently being processed.

[0502] In any case, as a result of setting the critical error flag ABN, the WDT circuit 58 and the performance control CPU 63 then function, and the composite chip 50 or the VDP circuit 52 is abnormally reset (ST10a), so the process of initializing the drawing circuit 76 and the data transfer circuit 72 is not necessarily required. On the other hand, if the drawing circuit 76 and the data transfer circuit 72 are initialized, abnormal recovery can be expected as a result, so it is also preferable to return to the process of step ST20 and re-execute the DL issuance process without setting the critical error flag ABN.

[0503] This also applies to the processing in step ST25, where it is preferable to initialize the data transfer circuit 72 and the drawing circuit 76 and then return to the processing in step ST20 without setting the critical error flag ABN. However, in such cases, the number of times the DL issuance process is re-executed is counted, and if the number of re-executions exceeds the limit, the critical error flag ABN is set and the DL issuance process is terminated.

[0504] Figure 24(b) illustrates the normal operating state for confirmation. As shown in the figure, the issued display list DL is analyzed by the drawing circuit 76 (display list analyzer) in the order of the listed instruction commands, and the operation based on each instruction command is executed. This operation is performed in parallel with the issuance process of the display list DL and the data transfer operation (ST26~ST30) of the data transfer circuit 72.

[0505] For example, when an instruction command (TXLOAD) is executed, the necessary texture is read from CGROM 55 and acquired in the AAC area (a). Then, GDEC 75 is automatically started and the decoding operation is performed, and the decoded data is expanded into a predetermined index space. Depending on the instruction command, the geometry engine 77 and others may also function, but in any case, the various parts of the drawing circuit 76 work together to complete the image data corresponding to the display list DL in the frame buffers FBa and FBb.

[0506] Next, the case in which a display list DL is issued via the DMAC circuit 60 will be explained based on Figure 25. Although not limited in any way, we will use the third DMA channel out of the first to fourth DMA channels built into the DMAC circuit 60.

[0507] In the embodiment shown in Figure 25, first, the data transfer circuit 72 and the drawing circuit 76 are initialized by setting clear values ​​in a predetermined data transfer register RGij and a predetermined drawing register RGij, respectively (ST20). This process is the same as the error handling in step ST27 of Figure 24. The internal circuitry of the data transfer circuit 72, including the FIFO buffer, is initialized, the status bit of the data transfer register indicating the progress of data transfer is set to its initial value, and the bit indicating that the entire data transfer is being initialized is set to a predetermined value.

[0508] The same applies to the drawing circuit 76, which includes the processes of (1) setting internal parameters to their initial values, (2) setting the internal control circuit to its initial state, (3) initializing GDEC75, and (4) initializing the cache state of the AAC area. In addition, the initialization process of the drawing circuit (ST20 in Figure 25) may also initialize the predetermined drawing register RGij mentioned above. Note that in the process of Figure 24, such initialization may be performed first.

[0509] In the process shown in Figure 25, the next step is to confirm that the initialization process has been completed successfully by reading a predetermined status register RGij, which identifies the operating status of the data transfer circuit 72 and the drawing circuit 76 (ST21). If initialization fails, the critical error flag ABN is set and the process ends (ST22). However, such a situation rarely occurs in practice.

[0510] Next, the transfer operation mode of the data transfer circuit 72 and the transmission route within the data transfer circuit 72 are set in a predetermined data transfer register RGij. The settings are not particularly limited, but here, the transfer protocol from the CPUIF unit 56 to the ChB control circuit 72b and to the CPU bus control unit 72d is set to follow the settings in the DMAC circuit 60 (ST23).

[0511] Next, the total transfer size is set to a predetermined data transfer register RGij. As in the case of Figure 24, the total data amount = 256. Note that if the unadjusted method (C) is adopted, the total transfer size will be determined and set at this timing to be an integer multiple of the minimum data amount Dmin. Next, the drawing operation of the drawing circuit 76 is started based on the value set in the predetermined drawing register RGij (ST25). Timings t1, t2, t3, and t4 in Figure 30(a) are also the timings for the operation of step ST25. Then, the operation of the DMAC circuit 60 is started (ST26), and the data transfer operation of the data transfer circuit 72 is started (ST27).

[0512] The process for starting the operation of the DMAC circuit 60 is as shown in Figure 25(b). First, with DMAC transfer disabled, it waits for the transfer of one data transfer unit (1 operand) of one cycle to be completed (ST40). The detailed operation is the same as the process shown in Figure 26, and is divided into the process of setting DMAC transfer to disabled (ST53) and the subsequent waiting process (ST54).

[0513] The reason for providing this processing is to consider that (1) in other embodiments, the DMAC circuit 60 (third DMA channel) may be used in the main control processing or timer interrupt processing (Figure 22), and (2) in other embodiments that do not provide the processing of step ST5 in Figure 22, the DMAC circuit 60 that has started issuing the display list DL may not be able to complete the DL issuance operation within its operating cycle (δ).

[0514] In the exceptional circumstances described above, if a new setting value (such as a conflicting setting value) is added to the operating DMAC circuit 60, normal DMA operation cannot be guaranteed at all, and serious trouble is a concern. However, by providing the processing in step ST40, normal operation based on the subsequent setting value is guaranteed. In other words, even in a modified embodiment that partially alters this embodiment, normal DMA operation can be achieved regardless of the preceding trouble.

[0515] After executing the process of step ST40, which has the significance described above, the next step is to set the operating conditions of the DMAC circuit 60 (ST41). Specifically, as shown in Figure 9, the cycle steal transfer mode is selected, and one operand transfer is set to 32-bit transfer x 2. It is also specified that the Source address should be recognized as increasing sequentially since it is the address of the list buffer area (DL buffer BUF) of RAM 59, while the Destination address should be a fixed value since it is the transfer port TR_PORT.

[0516] Next, the starting address of the DL buffer BUF of RAM 59 is set to a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST42), and the address of the transfer destination address, the transfer port TR_PORT, is set (ST43). In addition, the total transfer size, that is, the total amount of data in the display list DL, is set to 256 bytes (ST44), and the DMA operation of the DMAC circuit 60 is started (ST45).

[0517] By the way, the explanation so far has assumed that the actual bit length of all instruction commands is a multiple of 32 bits. However, the structure of display list DL and instruction commands is not necessarily limited, so the following will explain such cases.

[0518] For example, including when the aforementioned no-adjustment method (C) is adopted, if the total data amount X of the display list DL is an arbitrary value X that is not an integer multiple of 32 bits, the process in step ST44 adjusts this arbitrary value X to an appropriate transfer amount MOD and then performs the process of setting the total transfer size. Here, the appropriate transfer amount MOD is determined based on the settings for one operand transfer and the minimum data amount Dmin (bytes) of the data transfer circuit 72.

[0519] Specifically, if the single operand transfer setting is N bytes × M times, the transfer amount MOD will be adjusted to a value that is an integer multiple of N × M (bytes) and also an integer multiple of Dmin (bytes). For example, if N × M = 8 × 4 and Dmin = 256, an arbitrary value X (= 300) bytes will be adjusted to a transfer amount MOD (= 512) bytes.

[0520] As explained above, including general principles, the DMA operation of the DMAC circuit 60 initiates a cycle steal transfer operation as shown in Figure 9, and without particularly hindering the CPU's operation, the display list DL is transferred to the transfer port TR_PORT every 32 bits in this embodiment. The transferred data is then transferred to the drawing circuit 76 via the transfer circuit ChB.

[0521] To achieve this operation, in this embodiment, following the processing of step ST45, the data transfer circuit 72 starts its transfer operation and the processing is completed (ST27). Subsequently, the data transfer circuit 72 receives a sequence of instruction commands for the display list DL from the DMAC circuit 60, with the minimum data amount Dmin as one unit, and transfers this to the drawing circuit 76. The drawing circuit 76 then executes the drawing operation based on the instruction commands for the display list DL. Therefore, after the processing of step ST27, the performance control CPU 63 can start the processing of step ST11 in Figure 22, and can control sound effects, lamp effects, and motor effects in parallel with the drawing operation by the VDP circuit 52 (DL issuance processing by the DMAC circuit 60).

[0522] Figure 25(c) illustrates this operation. Prior to the DMA transfer, the drawing circuit starts operating (ST25), and the display list analyzer of the drawing circuit 76 quickly and smoothly performs the Analyze process. Based on the operation of GDEC75 and the geometry engine 77, image data for one frame is generated in the frame buffers FBa and FBb for each display device DS1 and DS2.

[0523] By the way, the configuration in Figure 25, in which the DL issuance process ends with the processing in step ST27, is not necessarily limited. For example, as shown in Figures 32 to 33, when sound effects, lamp effects, and motor effects are controlled by other CPUs, it is preferable to confirm the normal operation of the DMAC circuit 60 and the data transfer circuit 72 after the processing in step ST27. Figure 26 is a flowchart illustrating the operation following step ST27 in Figure 25 and the process for confirming normal operation.

[0524] First, the system checks a predetermined status register to confirm that the transfer operation of the DMAC circuit 60 has completed successfully (ST50). It also confirms that the data transfer circuit 72 has completed its transfer operation (ST51). Typically, the DL issuance process shown in Figure 25 is completed through this process.

[0525] On the other hand, if the .DMAC circuit 60 has not completed its operation after waiting for a predetermined time, or if the data transfer circuit 72 has not completed its transfer operation, the drawing circuit 76 and the data transfer circuit 72 are initialized by setting a clear value in a predetermined VDP register RGij (ST52). This operation is based on the fact that the display list DL issuance process has not completed successfully, and is specifically the same as the error handling in step ST27 in Figure 24 and the initial processing in step ST20 in Figure 25.

[0526] In other words, in this case as well, the drawing circuit 76 has already started operating and has completed a certain amount of processing, so the initialization process of the drawing circuit 76 includes (1) setting all internal parameters that may be set by the display list DL to their initial values, (2) setting all internal control circuits to their initial state, (3) initializing the GDEC 75, and (4) initializing the cache state of the AAC area.

[0527] Next, new DMA transfer operations are prohibited (ST53), and the system waits for the transfer operation of one operand that is currently running to finish (ST54). As explained earlier, in this embodiment, two 32-bit transfers are treated as one operand, and this is done to avoid suddenly initializing the operating DMAC circuit 60.

[0528] Once this preparation is complete, the DMAC circuit 60 is initialized by setting a clear value in a predetermined operation control register REG that defines the operation of the DMAC circuit 60 (ST52). Then, the critical error flag ABN is set and the DL issuance process ends. In this case, since the processing in steps ST52 and ST55 can be expected to recover from the error, it is also preferable to return to step ST20 in Figure 25 and re-execute the DL issuance process without setting the critical error flag ABN. However, the number of times the DL issuance process (ST23~ST27) is re-executed should be counted, and if the number of re-executions exceeds the limit, it is necessary to set the critical error flag ABN and end the DL issuance process.

[0529] Next, the main control processing when using the preloader 73 will be explained based on Figure 27. The processing in Figure 27 is similar to the processing in Figure 22, but first, the content of the start condition determination (ST5') is different. That is, in the embodiment using the preloader, at the start of each operation cycle, the status information of the drawing circuit 76 and the preloader 73 is accessed via READ to confirm that the drawing operation based on the display list DL1 has been completed and the preload operation based on the display list DL2 has been completed (ST5').

[0530] As shown in the time chart in Figure 31(a), the preloader 76 should have completed its pre-read operation (preload operation) during the operation cycle (T1 to T1+δ) based on the display list DL1 issued during the operation cycle (T1). S...

Claims

[Claim 1] The system is configured with a CPU circuit that includes a CPU for executing program processing, a DMAC (Direct Memory Access Controller) circuit that operates under the control of the CPU, and an operation control register in which setting values ​​that define the operation of the DMAC circuit are set, and a VDP circuit (Video Display Processor) that incorporates a VDP register and a display circuit that outputs an image signal to a display device, and a performance control means. In a gaming machine in which the CPU circuit sets the necessary setting values ​​in the VDP register and issues a display list to the VDP circuit that specifies the display content of the display device, the performance operation including image effects realized on the display screen of the display device is executed, The memory space accessible by the CPU includes an address space located outside the CPU circuit and divided into multiple sections, each capable of defining a data bus width, and the VDP register. The address spaces of the aforementioned multiple partitions are broadly divided into a non-volatile space composed of non-volatile memory and a volatile space composed of volatile memory. The transfer information, which is at least a part of the programs and data stored in a predetermined address space included in the non-volatile space, is configured to be transferred to the address space included in the volatile space when the DMAC circuit functions based on the setting of a predetermined setting value in the operation control register after the CPU is reset. The display device is configured to include a display drive circuit (MONI) that drives a group of display elements constituting the display screen based on image data received from the performance control means, and an illumination circuit (BL) that illuminates the display screen. A power supply control means (SPY) positioned between the display device and the performance control means controls the lighting circuit (BL) to an operational state based on a first control signal (STBY) received from the performance control means, while simultaneously starting the lighting operation of the lighting circuit (BL) based on a second control signal (PWM) received from the performance control means. The VDP register includes a first-type register in which necessary operating parameters are set to optimize the access operation to the CGROM that stores the data necessary for the image presentation, and a second-type register indicating that the initialization operation of the display circuit has been completed. The first and second type registers are configured to be set or referenced after the CPU is reset, before the start of the steady-state processing that is repeated at predetermined intervals and after the image rendering can be executed. A gaming machine.

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