Display device

Abstract

To provide a display device that can reduce brightness and color coordinate fluctuations due to temperature fluctuations.SOLUTION: This specification relates to a display device that can improve optical quality by reducing brightness and color coordinate fluctuations due to temperature fluctuations. The display device includes a first subpixel including a first light-emitting element configured to emit light of a first color and a first driving transistor configured to drive the first light-emitting element, and a second subpixel including a second light-emitting element configured to emit light of a second color and a second driving transistor configured to drive the second light-emitting element, the first driving transistor and the second driving transistor can have a different dummy hole total opening area.SELECTED DRAWING: Figure 1

Description

Technical Field

[0001] This specification relates to a display device capable of reducing luminance and color coordinate variations caused by temperature fluctuations.

Background Art

[0002] An electroluminesence display device has the advantages of high luminance, low driving voltage, being capable of ultra-thin film formation, and being able to be embodied in a free form by using self-emitting elements.

[0003] An electroluminesence display device has the characteristic that the luminance of the light-emitting element varies with temperature, and luminance variations may occur due to temperature fluctuations.

[0004] The content of the above-described background art is technical information held by the inventor of this specification for deriving examples of this specification or acquired in the process of deriving examples of this specification, and it cannot necessarily be said to be publicly known technology publicly disclosed to the general public before the filing of this specification.

Summary of the Invention

Problems to be Solved by the Invention

[0005] In an electroluminesence display device, since the luminance variation characteristics of red, green, and blue light-emitting elements with different light-emitting substances vary with temperature, a luminance variation difference may occur between the three-color sub-pixels due to temperature fluctuations. As a result, the white color coordinates of the electroluminesence display device may vary due to temperature fluctuations, and the optical quality may deteriorate.

[0006] This specification provides a display device capable of reducing luminance and color coordinate variations caused by temperature fluctuations and improving optical quality.

[0007] The problems that this specification seeks to solve are not limited to those mentioned above, and other problems not mentioned can be clearly understood by those with ordinary skill in the technical field to which the technical concept of this specification belongs from the following description. [Means for solving the problem]

[0008] A display device according to one embodiment includes a first subpixel comprising a first light-emitting element that emits a first color of light and a first drive transistor that drives the first light-emitting element, and a second subpixel comprising a second light-emitting element that emits a second color of light and a second drive transistor that drives the second light-emitting element, wherein the first drive transistor and the second drive transistor may have different dummy hole total aperture areas.

[0009] A display device according to one embodiment includes a first light-emitting element that emits a first color of light, a first drive transistor that drives the first light-emitting element, a first subpixel including at least one first dummy hole superimposed on the first gate electrode of the first drive transistor, a second light-emitting element that emits a second color of light, a second drive transistor that drives the second light-emitting element, a second subpixel including at least one second dummy hole superimposed on the second gate electrode of the second drive transistor, a third light-emitting element that emits a third color of light, a third drive transistor that drives the third light-emitting element, and a third subpixel including at least one third dummy hole superimposed on the third gate electrode of the third drive transistor, wherein the total aperture area of ​​at least one first dummy hole is different from the total aperture area of ​​at least one second dummy hole and the total aperture area of ​​at least one third dummy hole, and the total aperture area of ​​at least one second dummy hole may be the same as or different from the total aperture area of ​​at least one third dummy hole.

[0010] A display device according to one embodiment includes a first subpixel comprising a first light-emitting element that emits a first color of light and a first drive transistor that drives the first light-emitting element, and a second subpixel comprising a second light-emitting element that emits a second color of light and a second drive transistor that drives the second light-emitting element, wherein the first drive transistor and the second drive transistor may have different total dummy hole aperture areas depending on the brightness variation characteristics with respect to temperature of the first light-emitting element and the second light-emitting element.

[0011] A display device according to one embodiment includes a first subpixel comprising a first light-emitting element that emits a first color of light and a first drive transistor that drives the first light-emitting element, and a second subpixel comprising a second light-emitting element that emits a second color of light and a second drive transistor that drives the second light-emitting element, wherein the first drive transistor and the second drive transistor may have different total dummy hole aperture areas depending on the aperture areas of the first light-emitting element and the second light-emitting element.

[0012] Specific details of the various embodiments of this specification, other than the means of solving the problems described above, are included in the following description and figures. [Effects of the Invention]

[0013] In one embodiment, a display device can reduce or minimize the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of subpixels by applying a dummy hole to the insulating layer of the drive transistor and controlling the amount of critical voltage fluctuation of the drive transistor due to temperature.

[0014] In one embodiment, the display device can minimize the difference in brightness fluctuations between subpixels due to temperature fluctuations by applying different numbers and area ratios of dummy holes to the insulating layer of subpixels based on the aperture ratio (area) of the light-emitting element or the brightness fluctuation characteristics due to the temperature of the light-emitting element, thereby controlling the amount of critical voltage fluctuation of the drive transistor due to temperature fluctuations. As a result, it is possible to minimize fluctuations in the white color coordinate due to temperature fluctuations and improve optical quality.

[0015] The display device according to one embodiment can improve optical quality by controlling the critical voltage fluctuation of the drive transistor due to temperature, thereby reducing or minimizing the temperature luminance sensitivity and temperature color sensitivity of subpixels, and thus can provide improved image quality with low power consumption. [Brief explanation of the drawing]

[0016] [Figure 1] This is a block diagram schematically showing the configuration of a display device according to one embodiment. [Figure 2A] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 2B] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 3A] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 3B] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 4A] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 4B] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 4C] This figure illustrates a drive transistor structure having a dummy hole according to one embodiment. [Figure 5] This figure illustrates a portion of the pixel array of a display device according to one embodiment. [Figure 6] It is a diagram illustrating a part of a pixel array of a display device according to an embodiment. [Figure 7] It is an equivalent circuit diagram illustrating a sub-pixel configuration according to an embodiment. [Figure 8A] It is a diagram illustrating the layout structures of sub-pixels according to a comparative example and an embodiment. [Figure 8B] It is a diagram illustrating the layout structures of sub-pixels according to a comparative example and an embodiment. [Figure 8C] It is a diagram illustrating the layout structures of sub-pixels according to a comparative example and an embodiment. [Figure 8D] It is a diagram illustrating the layout structures of sub-pixels according to a comparative example and an embodiment. [Figure 9] It is a cross-sectional view illustrating the structure of a sub-pixel according to an embodiment. <​​​​​​​​​​​​​​​​​​​​​​​The advantages and features of this specification, as well as the methods for achieving them, will become apparent by referring to the examples described below in detail with accompanying figures. However, this specification is not limited to the examples disclosed below, but can be embodied in a variety of different forms, and these examples are provided merely to complete the disclosure of this specification and to fully inform those who have ordinary skill in the art to which this specification belongs of the scope of the invention, and this specification is defined only by the scope of the claims.

[0018] The shapes, sizes, proportions, angles, numbers, etc., disclosed in the figures illustrating the embodiments of this specification are illustrative, and this specification is not limited to what is shown in the figures. Throughout the specification, the same reference numeral refers to the same component. Where a specific description of the relevant prior art would be deemed to unnecessarily obscure the gist of this specification, such detailed description is omitted. Where "includes," "has," "consists of," etc., used herein, other parts may be added unless "only" is used. When a component is expressed singularly, it includes multiple components unless otherwise explicitly stated.

[0019] In interpreting the constituent elements, even if there is no separate explicit mention of the error range, it shall be interpreted as including the error range.

[0020] When describing spatial relationships, for example, when the positional relationship between two parts is described using phrases such as "above," "above," "below," or "beside," one or more other parts may be located between the two parts, unless the expressions "immediately" or "directly" are used.

[0021] When describing temporal relationships, for example, when a temporal sequence is described using phrases like "after," "following," "next," or "before," it can include non-continuous events unless expressions like "immediately" or "directly" are used.

[0022] The terms "first," "second," etc., are used to describe various components, but these components are not limited by these terms. These terms are simply used to distinguish one component from another. Therefore, the first component referred to below may also be the second component within the technical concept of this specification.

[0023] In describing the components of this specification, terms such as 1st, 2nd, A, B, a, b, etc., may be used. Such terms are used solely to distinguish a component from other components, and do not limit the nature, order, sequence, or number of the components. Where it is stated that a component "connects," "joins," or "links" another component, it should be understood that the component can connect or link directly to the other component, but that other components may "intersect" between each component that can connect or link indirectly, unless otherwise explicitly stated.

[0024] The term "at least one" should be understood to include all combinations of one or more of the related components. For example, "at least one of the first, second, and third components" may mean not only the first, second, or third component, but also all combinations of two or more of the first, second, and third components.

[0025] Each feature of some of the embodiments described herein can be combined or combined with one another, either partially or as a whole, and various technical interdependencies and drives are possible. Each embodiment can be implemented independently of one another or together in a related manner.

[0026] Preferred embodiments will be described below with reference to the attached figures. The scales of the components shown in the figures are different from actual scales for the sake of explanation and are not limited to the scales shown in the figures.

[0027] Figure 1 is a block diagram schematically showing the configuration of a display device according to one embodiment.

[0028] The display device according to one embodiment may be an electroluminescent display device. The electroluminescent display device may be, but is not limited to, any one of the following: an organic light-emitting diode (OLED) display device, a quantum-dot light-emitting diode (Quantum-dot) display device, an inorganic light-emitting diode (Inorganic Light-Emitting Diode) display device, a micro LED display device, or a mini LED display device.

[0029] Referring to Figure 1, a display device 1000 according to one embodiment may include, but is not limited to, a display panel 100, a gate driver 200, a data driver 300, a timing controller 400, a gamma voltage generation unit 500, and a power management circuit 700. A display device may include more components. The gate driver 200 and the data driver 300 can be integrated and represented in a panel driver that drives the display panel 100. The gate driver 200, the data driver 300, the timing controller 400, the gamma voltage generation unit 500, and the power management circuit 700 can be integrated and represented in a display driver.

[0030] The display panel 100 can be a rigid display panel or a flexible display panel that can change shape, such as a foldable, bendable, rollable, or stretchable display panel.

[0031] The display panel 100 can display an image via a pixel array in which subpixels (SP) are arranged in a matrix within the display area (DA). In one embodiment, the display panel 100 may further include a touch sensor array positioned within the display area (DA) to sense the user's touch.

[0032] Pixels arranged in a display area (DA) may include multiple subpixels (SPs) that emit light of different colors from each other to embody white light. A subpixel (SP) may include a red (R) subpixel that emits red light, a green (G) subpixel that emits green light, a blue (B) subpixel that emits blue light, and may further include a white (W) subpixel that emits white light.

[0033] A subpixel (SP) may comprise a pixel circuit including an EL (light-emitting element) and a driver transistor (DT) that independently drives the EL. The EL may be, but is not limited to, an organic light-emitting diode, a quantum dot light-emitting diode, an inorganic light-emitting diode, a micro LED, or a mini LED. The pixel circuit may have various circuit configurations including the driver transistor (DT) and a transistor and capacitor connected to at least one of the nodes (N1, N2, N3) connected to the driver transistor (DT). The pixel circuit of the subpixel (SP) may be connected to signal lines, including gate lines, data lines, and power lines, located on the display panel 100.

[0034] Light-emitting elements (ELs) have luminance fluctuation characteristics with temperature, and may exhibit high temperature luminance sensitivity (TLS). Red, green, and blue light-emitting elements (ELs) made of different types of light-emitting materials have different luminance fluctuation characteristics with temperature, and may exhibit high temperature color sensitivity (TCS).

[0035] In one embodiment, the display panel 100 can control the brightness fluctuation of the light-emitting element (EL) due to temperature by controlling the critical voltage fluctuation (ΔVth) of the drive transistor (DT) due to temperature.

[0036] In one embodiment, the display panel 100 can increase the temperature-dependent critical voltage fluctuation (ΔVth) of the drive transistor (DT) by applying dummy holes to multiple insulating layers of the drive transistor (DT) in the subpixel (SP). The dummy holes for the drive transistor (DT) can be provided in multiple insulating layers in the same process as the contact holes. As a result, process steps can be reduced and the manufacturing process can be simplified. The dummy holes for the drive transistor (DT) are used as passages through which hydrogen atoms in the multiple insulating layers are expelled during the contact holes and heat treatment process, and by increasing the degree of dehydrogenation, the temperature-dependent critical voltage fluctuation (ΔVth) of the drive transistor (DT) can be increased.

[0037] As a result, the display panel 100 can reduce or minimize the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the subpixels (SP) by increasing the critical voltage fluctuation (ΔVth) of the drive transistor (DT) due to temperature, thereby suppressing the brightness fluctuation due to the temperature of the light-emitting element (EL).

[0038] In one embodiment, the display panel 100 can control the critical voltage fluctuation amount (ΔVth) of the drive transistor (DT) by applying different values ​​to the number of dummy holes and area ratio (aperture ratio, aperture area) of the drive transistor (DT) depending on the aperture ratio (aperture area, light-emitting area) of the light-emitting element (EL) or the brightness fluctuation characteristics due to the temperature of the light-emitting element (EL). A detailed explanation of this will be given later.

[0039] As a result, the display panel 100 can control the critical voltage fluctuation amount (ΔVth) of the drive transistor (DT) to be different for at least two subpixels (SP) of different colors, thereby reducing or minimizing the difference in brightness fluctuations between subpixels (SP) due to temperature fluctuations. Consequently, the optical quality of the display panel 100 can be improved by reducing or minimizing the white color coordinate fluctuations due to temperature fluctuations.

[0040] The gate driver 200 is controlled according to a plurality of gate control signals supplied from the timing controller 400 and can individually drive the gate lines of the display panel 100. The gate driver 200 can supply a gate-on voltage to the gate line during the drive period of each gate line and a gate-off voltage to the gate line during the non-drive period of each gate line. The gate driver 200 can be integrated into the bezel area of ​​the display panel 100 in the form of a gate-in-panel (GIP) configuration, formed together with the thin-film transistors of the display area (DA).

[0041] In one embodiment, a gate driver 200 built into the display panel 100 can receive multiple gate control signals from a timing controller 400 via a level shifter. The level shifter receives timing control signals from the timing controller 400 and can generate multiple gate control signals through level shifting or logic processing and supply them to the gate driver 200.

[0042] The gamma voltage generation unit 500 can generate multiple reference gamma voltages with different gamma voltage levels and supply them to the data driver 300. The gamma voltage generation unit 500 can generate multiple reference gamma voltages corresponding to the gamma characteristics of the display device 1000 under the control of the timing controller 400 and supply them to the data driver 300. The gamma voltage generation unit 500 can adjust the reference gamma voltage level according to the gamma data supplied from the timing controller 400 and output it to the data driver 300. The gamma voltage generation unit 500 can adjust the high-potential power supply voltage, which is the maximum gamma voltage, according to the peak brightness control from the timing controller 400, and adjust the multiple reference gamma voltages with the adjusted high-potential power supply voltage and output them to the data driver 300.

[0043] The data driver 300 is controlled according to multiple data control signals supplied from the timing controller 400, and can convert digital data supplied from the timing controller 400 into analog data signals using a digital-to-analog conversion circuit. The data driver 300 subdivides multiple reference gamma voltages supplied from the gamma voltage generation unit 500 into gamma voltages, and can convert digital data into analog data signals using the subdivided gamma voltages. The data driver 300 can supply the converted data signals to the data lines of the display panel 100.

[0044] In one embodiment, the data driver 300 can supply an additional reference voltage to the reference line of the display panel 100 under the control of the timing controller 400. The data driver 300 can supply the reference voltage separately for display and sensing under the control of the timing controller 400.

[0045] In one embodiment, the data driver 300 further includes a sensing unit that, in accordance with the control of the timing controller 400, senses a signal reflecting the driving characteristics of subpixels (SP) via a reference line or power line using a voltage sensing method or a current sensing method, and transmits the sensing result to the timing controller 400.

[0046] The timing controller 400 can receive source video data and timing control signals from an external host system. The host system may be a computer, television system, set-top box, mobile device system such as a tablet or mobile phone, or in-vehicle system. The timing control signals may include a dot clock, data enable signal, vertical sync signal, horizontal sync signal, etc.

[0047] The timing controller 400 can control the gate driver 200 and the data driver 300 using timing control signals supplied from the host system and timing setting information stored internally. The timing controller 400 can generate and supply a plurality of gate control signals to the gate driver 200 to control the drive timing of the gate driver 200. The timing controller 400 can generate and supply a plurality of data control signals to the data driver 300 to control the drive timing of the data driver 300. In one embodiment, the timing controller 400 can be represented as a controller.

[0048] The timing controller 400 can perform at least one of various video processing operations on the input video data supplied from the host system, including image quality correction, degradation correction, and brightness correction for reducing power consumption.

[0049] In one embodiment, the timing controller 400 can further correct the image-processed data by applying a compensation value for the characteristic deviation of subpixels (SPs) stored in memory before supplying it to the data driver 300.

[0050] In one embodiment, the timing controller 400 can execute a sensing mode according to the host system or user's request or a predetermined drive sequence. The timing controller 400 can control the panel drivers 200, 300 and the power management circuit 700 to drive the display panel 100 in sensing mode and update compensation data stored in memory. In sensing mode, the timing controller 400 can sense the critical voltage and mobility of the drive transistors (DTs) of the display panel 100, reflecting the characteristics and degradation of the subpixels (SPs), via the data driver 300, and can further sense the critical voltage of the light-emitting elements (ELs). The timing controller 400 can process the sensing results to update the compensation data for the subpixels (SPs).

[0051] In one embodiment, the timing controller 400 can accumulate video data of subpixels (SPs) to predict subpixel (SP) degradation, sense the critical voltage of the light-emitting element (EL) for subpixels (SPs) that are predicted to have relatively large degradation, and update the compensation data.

[0052] The power management circuit 700 can use the input voltage to generate and supply various drive voltages necessary for the operation of all components of the display device 1000, including the display panel 100, gate driver 200, data driver 300, timing controller 400, and gamma voltage generation unit 500.

[0053] Figures 2A to 4C illustrate the structure of a drive transistor having a dummy hole according to one embodiment.

[0054] Referring to Figures 2A and 3A, the first drive transistor (DT_SP1) of the first subpixel according to one embodiment includes an active layer (ACT) on a substrate (SUB), a gate insulating layer (GI) on the active layer (ACT), a gate electrode (GE1) on the gate insulating layer (GI), and a first source / drain electrode (SD11) and a second source / drain electrode (SD12) provided in the conductive regions of the active layer (ACT) facing each other across the channel (CH1). The first drive transistor (DT_SP1) may further include a first source / drain connecting electrode (SD14) arranged on a plurality of insulating layers including an interlayer insulating layer (ILD) on the gate electrode (GE1) and connected to the first source / drain electrode (SD11) via a contact hole 11, and a second source / drain connecting electrode (SD15) connected to the second source / drain electrode (SD12) via a contact hole 12.

[0055] Referring to Figures 2B and 3B, the second drive transistor (DT_SP2, DTa_SP2) of the second subpixel according to one embodiment includes an active layer (ACT) on a substrate (SUB), a gate insulating layer (GI) on the active layer (ACT), a gate electrode (GE2) on the gate insulating layer (GI), and a first source / drain electrode (SD21) and a second source / drain electrode (SD22) provided in the conductive regions of the active layer (ACT) facing each other across a channel (CH2). The second drive transistor (DT_SP2, DTa_SP2) may further include a first source / drain connecting electrode (SD23) disposed on an interlayer insulating layer (ILD) and connected to the first source / drain electrode (SD21) via a contact hole 21, and a second source / drain connecting electrode (SD24) connected to the second source / drain electrode (SD22) via a contact hole 22.

[0056] The gate electrodes (GE1, GE2) of the drive transistors (DT_SP1, DT_SP2, DTa_SP2) can be connected to the second node (N2) of the corresponding subpixel, the first source / drain electrodes (SD11, SD21) can be connected to the first node (N1) of the corresponding subpixel via the first source / drain connecting electrodes (SD14, SD23), and the second source / drain electrodes (SD12, SD22) can be connected to the third node (N3) of the corresponding subpixel via the second source / drain connecting electrodes (SD15, SD24).

[0057] The contact holes 11, 12, 21, and 22 of the drive transistors (DT_SP1, DT_SP2, DTa_SP2) can be provided through multiple insulating layers, including the interlayer insulating layer (ILD) and the gate insulating layer (GI).

[0058] In one embodiment, the first and second drive transistors (DT_SP1, DT_SP2, DTa_SP2) may further include dummy holes 13, 23, 23a provided in a plurality of insulating layers, including an interlayer insulating layer (ILD) on the gate electrodes (GE1, GE2).

[0059] The dummy holes 13, 23, and 23a of the drive transistors (DT_SP1, DT_SP2, DTa_SP2) can be provided in multiple insulating layers, including the interlayer insulating layer (ILD), in the same process as the contact holes 11, 12, 21, and 22. The dummy holes 13, 23, and 23a, together with the contact holes 11, 12, 21, and 22, can be used as passages for degassing by expelling hydrogen atoms from the insulating layer, including the interlayer insulating layer (ILD), during the heat treatment process after the contact hole process. As a result, in one embodiment, the drive transistors (DT_SP1, DT_SP2, DTa_SP2) can increase the degree of dehydrogenation via the dummy holes 13, 23, and 23a, increasing the critical voltage fluctuation amount (ΔVth) due to temperature, and consequently reducing the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the first and second subpixels.

[0060] Furthermore, in one embodiment of the display device, the aperture ratio (aperture area, light-emitting area) of the light-emitting element or the brightness fluctuation characteristics due to the temperature of the light-emitting element can be applied differently to the first and second drive transistors (DT_SP1, DT_SP2, DTa_SP2) by applying different aperture ratios (number or area) of the dummy holes 13, 23, and 23a, thereby controlling the temperature-dependent critical voltage fluctuation amount (ΔVth) of the first and second drive transistors (DT_SP1, DT_SP2, DTa_SP2).

[0061] Referring to Figures 2A and 2B, in one embodiment, the number of dummy holes 13 for the first drive transistor (DT_SP1) of the first subpixel and the number of dummy holes 23 for the second drive transistor (DT_SP2) of the second subpixel may differ. Each of the dummy holes 13 and 23 may have the same width (W1) and area as each of the contact holes 11, 12, 21, and 22.

[0062] The number of dummy holes 23 in the second drive transistor (DT_SP2) shown in Figure 2B may be greater than the number of dummy holes 13 in the first drive transistor (DT_SP1) shown in Figure 2A. For example, the first drive transistor (DT_SP1) may contain one dummy hole 13, while the second drive transistor (DT_SP2) may contain two dummy holes 23.

[0063] Referring to Figures 3A and 3B, in one embodiment, the width (W1) and area of ​​the dummy hole 13 of the first drive transistor (DT_SP1) of the first subpixel may differ from the width (W2) and area of ​​the dummy hole 23a of the second drive transistor (DTa_SP2) of the second subpixel.

[0064] The width (W2) and area of ​​the dummy hole 23a of the second drive transistor (DTa_SP2) shown in Figure 3B may be larger than the width (W1) and area of ​​the dummy hole 13 of the first drive transistor (DT_SP1) shown in Figure 3A. The width (W2) and area of ​​the dummy hole 23a of the second drive transistor (DTa_SP2) may be larger than the respective widths and areas of the contact holes 21 and 22 of the second drive transistor (DTa_SP2).

[0065] Referring to Figures 2A to 3B, the drive transistors (DT_SP1, DT_SP2, DTa_SP2) according to one embodiment may include dummy electrodes (SD16, SD25) arranged on multiple insulating layers including an interlayer insulating layer (ILD) and connected to gate electrodes (GE1, GE2) via dummy holes 13, 23, 23a. The dummy electrodes (SD16, SD25) are electrically floating and can be described as floating electrodes. By covering the dummy holes 13, 23, 23a, the dummy electrodes (SD16, SD25) can prevent defects that may occur in subsequent processes after the heat treatment process due to the dummy holes 13, 23, 23a. In one embodiment, the dummy electrodes (SD16, SD25) can be omitted.

[0066] Referring to Figures 4A to 4C, in one embodiment, the dummy hole 13b located in the first drive transistor (DTb_SP1) of the first subpixel and the dummy holes 23b and 23c located in the second drive transistors (DTb_SP2, DTc_SP2) of the second subpixel can have a structure in which they are filled with insulating material of a planarization layer (PLN) located on the source / drain connecting electrodes (SD14, SD15, SD23, SD24).

[0067] Second drive transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having dummy holes 23, 23a, 23b, 23c with a larger aperture ratio (number or area) than dummy holes 13, 13b of the first drive transistors (DT_SP1, DTb_SP1) may have a larger temperature-dependent critical voltage fluctuation (ΔVth) than the first drive transistors (DT_SP1, DTb_SP1). When multiple dummy holes are included as shown in Figure 4B, the aperture ratio and area (aperture area) of the dummy holes can mean the total aperture ratio and total area (total aperture area) of the multiple dummy holes. In one embodiment, the first drive transistors (DT_SP1, DTb_SP1) can be applied to a first subpixel with relatively small luminance fluctuation characteristics due to temperature of the light-emitting element, and the second drive transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be applied to a second subpixel with relatively large luminance fluctuation characteristics due to temperature of the light-emitting element.

[0068] As a result, the second subpixel can further reduce its temperature-luminance sensitivity (TLS) with the second drive transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2), thereby reducing or minimizing the temperature-dependent luminance difference between the first and second subpixels, and consequently reducing or minimizing the temperature-color sensitivity (TCS) of the subpixel, and thus reducing or minimizing the white color coordinate variation due to temperature changes.

[0069] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, and 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be arranged superimposed on the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) or placed in the insulating layer of an adjacent region that does not superimpose on the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2).

[0070] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, and 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be placed in the insulating layer in the region adjacent to the gate electrodes (GE1, GE2).

[0071] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, and 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be arranged to overlap with or not overlap with at least one of the gate electrodes (GE1, GE2) and the active layer (ACT).

[0072] In one embodiment, at least some of the dummy holes 13, 13b, 23, 23a, 23b, and 23c of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can be arranged so as not to overlap with the gate electrodes (GE1, GE2) or the active layer (ACT).

[0073] In one embodiment, the dummy holes 13, 13b, 23, 23a, 23b, and 23c in the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) can further increase the critical voltage fluctuation (ΔVth) due to temperature by increasing the amount of emission of a small number of atoms from the insulating layer closer to the active layer (ACT) as they are closer to the active layer (ACT) and channels (CH1, CH2). Therefore, the display device according to one embodiment can further reduce the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of subpixels and further improve optical quality.

[0074] Figures 5 and 6 illustrate a portion of the pixel array of a display device according to one embodiment.

[0075] Referring to Figure 5, a display panel 100a according to one embodiment may include a pixel matrix in which pixels (PXa) containing R / G / B subpixels (Ra, Ga, Ba) are repeatedly arranged in a first direction (X) and a second direction (Y). G subpixels (Ga) and R subpixels (Ra) may be arranged adjacent to each other in the second direction (Y), and B subpixels (Ba) may be arranged adjacent to G subpixels (Ga) and R subpixels (Ra) in the first direction (X), but the arrangement is not limited to this configuration.

[0076] Referring to Figure 6, a display panel 100b according to one embodiment may include a pixel matrix in which first type pixels (PXb) containing R / G subpixels (Rb, Gb) and second type pixels (PXc) containing B / G subpixels (Bb, Gb) are arranged alternately in a first direction (X) and a second direction (Y). R subpixels (Rb) and B subpixels (Bb) can be arranged adjacent to each other in the first direction (X) and the second direction (Y), G subpixels (Gb) can be arranged adjacent to R subpixels (Rb) in the first diagonal direction, and G subpixels (Gb) can be arranged adjacent to B subpixels (Bb) in the second diagonal direction, but the arrangement is not limited to this configuration.

[0077] R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) can have the form of an emissive region where the R / G / B light-emitting element emits light, and the remaining region excluding the emissive region may be a non-emissive region where a black matrix is ​​located.

[0078] Among the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb), considering the efficiency and lifetime of the B light-emitting element, the light-emitting area (aperture ratio) of the B light-emitting element in the B subpixel (Ba, Bb) may be the largest. The light-emitting area (aperture ratio) of either the R light-emitting element in the R subpixel (Ra, Rb) or the G light-emitting element in the G subpixel (Ga, Gb) may be the smallest. In one embodiment, as shown in Figure 5, the light-emitting area of ​​the G light-emitting element in the G subpixel (Ga) may be larger than the light-emitting area of ​​the R light-emitting element in the R subpixel (Ra), but in one embodiment, as shown in Figure 6, the light-emitting area of ​​the R light-emitting element in the R subpixel (Rb) may be larger than the light-emitting area of ​​the G light-emitting element in the G subpixel (Gb).

[0079] Referring to Figures 2A to 6, each of the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) in one embodiment may include one of either a first drive transistor (DT_SP1, DTb_SP1) having dummy holes 13, 13b or a second drive transistor (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having dummy holes 23, 23a, 23b, 23c.

[0080] As a result, in one embodiment, the display panels 100a and 100b can increase the temperature-dependent critical voltage fluctuation (ΔVth) of the drive transistors (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2), and reduce the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb).

[0081] In one embodiment of R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb), at least one of the R / G subpixels (Ra / Ga, Rb / Gb) may include a first drive transistor (DT_SP1, DTb_SP1) having dummy holes 13, 13b. B subpixels (Ba, Bb) with relatively large brightness fluctuations due to aperture ratio or temperature of the B light-emitting element may include a second drive transistor (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2) having dummy holes 23, 23a, 23b, 23c.

[0082] As a result, in one embodiment, the display panels 100a and 100b have different critical voltage fluctuations (ΔVth) with respect to temperature between the first drive transistors (DT_SP1, DTb_SP1) and the second drive transistors (DT_SP2, DTa_SP2, DTb_SP2, DTc_SP2). By reducing or minimizing the difference in brightness fluctuations with temperature between R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb), the temperature color sensitivity (TCS) of the R / G / B subpixels (Ra / Ga / Ba, Rb / Gb / Bb / Gb) can be reduced or minimized, thereby minimizing the fluctuation of the white color coordinate due to temperature fluctuations. For example, the B subpixel can be configured to include the number, shape, or size of dummy holes, which can generate a greater critical voltage fluctuation ΔVth than the R or G subpixel, thus reducing the difference in brightness fluctuations with temperature between R / G / B subpixels. Configurations that form dummy holes at different depths can also be used to adjust the critical voltage fluctuation (dummy holes formed closer to the ACT layer can increase the critical voltage fluctuation).

[0083] Figure 7 is an equivalent circuit diagram illustrating the configuration of a subpixel according to one embodiment.

[0084] Referring to Figure 7, a subpixel (SPa) according to one embodiment includes a light-emitting element (OLED) and a pixel circuit that independently drives the light-emitting element (OLED), and the pixel circuit may, but is not limited to, include a driver transistor (DT) and multiple transistors (T2-T8) and a storage capacitor (Cst). A subpixel may include other numbers of transistors and / or capacitors and / or other circuit configurations in addition to those shown in Figure 7.

[0085] Each of the transistors (DT, T2-T8) in the pixel circuit can be made of one of the following: polysilicon semiconductor, amorphous silicon semiconductor, or oxide semiconductor. In one embodiment, all or some of the transistors (DT, T2-T8) in the pixel circuit can be made of P-type transistors, such as P-type polysilicon transistors or P-type oxide transistors. In one embodiment, all or some of the transistors (DT, T2-T8) in the pixel circuit can be made of N-type transistors, such as N-type polysilicon transistors or N-type oxide transistors. In one embodiment, the transistors (DT, T2-T8) in the pixel circuit can be made by mixing P-type polysilicon transistors and N-type oxide transistors.

[0086] In one embodiment, the drive transistor (DT) and some transistors (T2, T4~T8) can be composed of high-mobility P-type LTPS (Low-Temperature Polycrystalline Silicon) transistors, and at least one of the transistors (T3, T4) can be composed of an N-type oxide transistor which has a smaller off-current (leakage current) than the LTPS transistor.

[0087] The sampling transistor (T3, the third transistor) is controlled by the first gate line 31 and can connect the second node (N2), to which the gate electrode of the driving transistor (DT) is connected, to the third node (N3), to which the second source / drain electrodes of the driving transistor (DT) are connected. The sampling transistor (T3) is turned on by the gate-on voltage of the first scan signal (Scan1) supplied via the first gate line 31, and can connect the driving transistor (DT) to a diode structure by connecting the gate electrode of the driving transistor (DT) to the second source / drain electrodes during the sampling period.

[0088] The switching transistor (T2, second transistor) is controlled by the second gate line 32 and can connect the data line 53 to the first node (N1) connected to the first source / drain electrodes of the drive transistor (DT). The switching transistor (T2) is turned on by the gate-on voltage of the second scan signal (Scan2) supplied via the second gate line 32 and can supply the data voltage (Vdata) supplied via the data line 53 to the drive transistor (DT) during the data programming period.

[0089] The operation control transistor (T5, fifth transistor) is controlled by the fifth gate line 35 and can connect the first power supply line 51, which supplies the first power supply voltage (VDD), to the first node (N1) of the drive transistor (DT). The operation control transistor (T5) is turned on by the gate-on voltage of the light emission control signal (EM) supplied via the fifth gate line 35 and can supply the first power supply voltage (VDD) supplied via the first power supply line 51 to the first node (N1) of the drive transistor (DT) during the light emission period.

[0090] The light emission control transistor (T6, the sixth transistor) is controlled by the fifth gate line 35 and can connect the third node (N3) of the drive transistor (DT) to the fourth node (N4) connected to the anode electrode of the light-emitting element (OLED). The light emission control transistor (T6) is turned on by the gate-on voltage of the light emission control signal (EM) supplied via the fifth gate line 35 and can connect the third node (N3) of the drive transistor (DT) to the anode electrode of the light-emitting element (OLED) during the light emission period.

[0091] The first initialization transistor (T4, the fourth transistor) is controlled by the fourth gate line 34 and can connect the second node (N2) of the drive transistor (DT) to the first initialization voltage line 41. The first initialization transistor (T4) is turned on by the gate-on voltage of the fourth scan signal (Scan4) supplied via the fourth gate line 34 and can supply the first initialization voltage (Vinit) to the second node (N2) of the drive transistor (DT) via the first initialization voltage line 41 during the initialization period.

[0092] The second initialization transistor (T7, the seventh transistor) is controlled by the third gate line 33 and can connect the second initialization voltage line 42 to the fourth node (N4) connected to the anode of the light-emitting element (OLED). The second initialization transistor (T7) is turned on by the gate-on voltage of the third scan signal (Scan3) supplied via the third gate line 33 and can supply the second initialization voltage (VAR) to the fourth node (N4) connected to the anode electrode of the light-emitting element (OLED) via the second initialization voltage line 42 during the initialization period. The second initialization voltage (VAR) can be expressed as the anode reset voltage.

[0093] The third initialization transistor (T8, the eighth transistor) is controlled by the third gate line 33 and can connect the third initialization voltage line 43 to the first node (N1) of the drive transistor (DT). The third initialization transistor (T8) is turned on by the gate-on voltage of the third scan signal (Scan3) supplied via the third gate line 33 and can supply the third initialization voltage (Vobs) supplied via the third initialization voltage line 43 to the first node (N1) to which the first source / drain electrodes of the drive transistor (DT) are connected during the initialization period. The third initialization voltage (Vobs) can be represented as an on-bias stress voltage that suppresses the critical voltage shift of the drive transistor (DT).

[0094] A storage capacitor (Cst) can be connected between the first power line 51 and the second node (N2) of the drive transistor (DT). The storage capacitor (Cst) can charge the differential voltage between the first power supply voltage (VDD) supplied via the first power line 51 and the data voltage (Vdata) supplied from the data line 53 to the second node (N2) via the switching transistor (T2) and the drive transistor (DT) and sampling transistor (T3). During the sampling period when the drive transistor (DT) is connected to the diode structure via the sampling transistor (T3), the storage capacitor (Cst) can sample and store the critical voltage (Vth) of the drive transistor (DT), and can provide the second node (N2) of the drive transistor (DT) with a data voltage compensated for the critical voltage. The storage capacitor (Cst) can charge and hold the difference voltage between the first power supply voltage (VDD) and the data voltage (Vdata) which is compensated for the critical voltage (Vth) of the drive transistor (DT) to a target voltage, and can provide the held target voltage as the drive voltage for the drive transistor (DT).

[0095] The drive transistor (DT, first transistor) can have its gate electrode connected to the second node (N2), its first source / drain electrode connected to the first node (N1), and its second source / drain electrode connected to the third node (N3). The drive transistor (DT) can control the light emission intensity of the light-emitting element (EL) by controlling the amount of current flowing to the light-emitting element (OLED) via the light emission control transistor (T6) using the target voltage charged in the storage capacitor (Cst).

[0096] In one embodiment, the drive transistor (DT) is one of the drive transistors having dummy holes as described above (DT_SP1, DTb_SP1, DT_SP2, DTa_SP2, DTb_SP2, DTC_SP2), and the critical voltage fluctuation amount (ΔVth) due to temperature may be large.

[0097] The light-emitting element (OLED) may comprise an anode connected to the third node of the drive transistor (DT) via a light-emitting control transistor (T6), a cathode connected to a second power supply line 52 that supplies a second power supply voltage (VSS), and an organic light-emitting layer between the anode and the cathode. The light-emitting element (EL) can generate light with a brightness proportional to the amount of drive current supplied from the drive transistor (DT) via the light-emitting control transistor (T6).

[0098] Referring to Figures 1 and 7, the first to fourth gate lines 31, 32, 33, and 34 can be driven by the scan driver included in the gate driver 200, and the fifth gate line 35 can be driven by the light emission control driver included in the gate driver 200. The data voltage (Vdata) is supplied from the data driver 300, and the first power supply voltage (VDD), second power supply voltage (VSS), first initialization voltage (Vinit), second initialization voltage (VAR), and third initialization voltage (Vobs) can be supplied from the power management circuit 700.

[0099] Figures 8A to 8D illustrate the subpixel layout structure according to a comparative example and one embodiment.

[0100] Specifically, the subpixels shown in Figures 8A to 8D illustrate the layout of the first active layer, first gate metal layer, upper metal layer, second active layer, second gate metal layer, and first source / drain metal layer arranged in the circuit element layer of the display panel. The layout of the second source / drain metal layer of the circuit element layer and the light-emitting element layer arranged on the circuit element layer are omitted.

[0101] Referring to Figures 8A to 8D, the subpixel pixel circuits in the comparative example and one embodiment can include the drive transistor (DT) and multiple transistors (T2 to T8) and storage capacitor (Cst) shown in Figure 7.

[0102] The first initialization voltage line 41 supplying the first initialization voltage (Vini), the fourth gate line 34 supplying the fourth scan signal (Scan4), the second gate line 32 supplying the second scan signal (Scan2), the first gate line 31 supplying the first scan signal (Scan1), the first power supply line 51 supplying the first power supply voltage (VDD), the fifth gate line 35 supplying the light emission control signal (EM), the third scan line 33 supplying the third scan signal (Scan3), the third initialization voltage line 43 supplying the third initialization voltage (Vobs), and the second-first and second-second initialization voltage lines 42r and 42gb supplying the second-first and second-second initialization voltages (VARr and VARgb, respectively) can be arranged extending in the first direction (X) and spaced apart in the second direction (Y). A redundant line (WDR) extending in the first direction (X) can be further placed between the fifth gate line 35 and the third scan line 33 for scotoma repair.

[0103] In one embodiment, the drive transistor (DT), switching transistor (T2), operation control transistor (T5), light emission control transistor (T6), second initialization transistor (T7), and third initialization transistor (T8) may be integrated into a first active layer (ACT) composed of an LTPS.

[0104] In one embodiment, the sampling transistor (T3) and the first initialization transistor (T4) may be made of oxide semiconductors and may include an integrally linked second active layer (OACT).

[0105] In one embodiment, the drive transistor (DT) and the plurality of transistors (T2-T8) of the pixel circuit may include an active layer made of LTPS, or an active layer made of oxide semiconductor.

[0106] The third scan line 33, which includes the gate electrode (GE1) of the drive transistor (DT), the first capacitor electrode (C1) of the storage capacitor (Cst), the gate electrode (GE5) of the operation control transistor (T5), the gate electrode (GE6) of the light emission control transistor (T6), and the gate electrodes (GE7, GE8) of the second and third initialization transistors (T7, T8), can be provided as a first gate metal layer on the first active layer (ACT).

[0107] The second capacitor electrode (C2) of the storage capacitor (Cst), the light-shielding electrodes 112 and 114 of the sampling transistor (T3), and the first initialization transistor (T4) can be provided as an upper metal layer on the first gate metal layer.

[0108] The lower line 103 of the first gate line 31, which includes the gate electrode (GE3) of the sampling transistor (T3), and the gate electrode (GE4) of the first initialization transistor (T4) can be provided as a second gate metal layer on the second active layer (OACT).

[0109] The first initialization voltage line 41, the fourth gate line 34, the second gate line 32, the upper line 104 of the first gate line 31, the first power supply line 51, the fifth gate line 35, the third scan line 33 that supplies the third scan signal (Scan3), the third initialization voltage line 43, the second-first and second-second initialization voltage lines 42r, 42gb, and the connecting electrodes 102, 105, 106, 107 can be provided as the first source / drain metal layer on the second gate metal layer.

[0110] A drive transistor (DT) and a storage capacitor (Cst) can be placed between the fourth gate line 34 and the fifth gate line 35. The drive transistor (DT) and storage capacitor (Cst) can be superimposed in the third direction (Z), and the first power supply line 51 can be superimposed with the drive transistor (DT) and storage capacitor (Cst) in the third direction (Z).

[0111] The drive transistor (DT, first transistor) may include a first channel (CH1), a first-first source / drain electrode (SD11), and a first-second source / drain electrode (SD12) located in the first active layer (ACT), and a first gate electrode (GE1) superimposed on the first channel (CH1) in the third direction (Z). The first gate electrode (GE1) can be connected to a connecting electrode 105 via a second node (N2) and a contact hole 64. The connecting electrode 105 can be connected to a sampling transistor (T3, third transistor) and a first initialization transistor (T4, fourth transistor) via a contact hole 65. The first-first source / drain electrode (SD11) can be connected to the fifth-first source / drain electrode (SD51) of the operation control transistor (T5, fifth transistor) via a first node (N1), and can be connected to the second-second source / drain electrode (SD22) of the switching transistor (T2, second transistor). The first and second source / drain electrodes (SD12) can be connected to the sampling transistor (T3) and the light emission control transistor (T6, sixth transistor) via the third node (N3).

[0112] The storage capacitor (Cst) may include a first capacitor electrode (C1) integrally positioned with the first gate electrode (GE1) of the drive transistor (DT), and a second capacitor electrode (C2) superimposed on the first capacitor electrode (C1) in a third direction (Z). The second capacitor electrode (C2) can be connected to the first power supply line 51 via a contact hole 70.

[0113] The switching transistor (T2, second transistor) may include a second channel (CH2), a second-first source / drain electrode (SD21), and a second-second source / drain electrode (SD22) located in the first active layer (ACT), and a second gate electrode (GE2) superimposed on the second channel (CH2) in the third direction (Z). The second gate electrode (GE2) can be connected to a second gate line 32 superimposed in the third direction (Z) via a contact hole 62. The second-first source / drain electrode (SD21) can be connected to a data line 53 (Figure 7) provided in the second source / drain metal layer via a contact hole 61 and a connecting electrode 102. The second-second source / drain electrode (SD22) can be connected to the first-first source / drain electrode (SD11) of the drive transistor (DT) via a first node (N1).

[0114] The operation control transistor (T5, fifth transistor) may include a fifth channel (CH5), a fifth-first source / drain electrode (SD51), and a fifth-second source / drain electrode (SD52) located in the first active layer (ACT), and a fifth gate electrode (GE5) superimposed on the fifth channel (CH5) in the third direction (Z). The fifth gate electrode (GE5) can be connected to the fifth gate line 32 via a contact hole 72. The fifth-first source / drain electrode (SD51) can be connected to the first-first source / drain electrode (SD11) of the drive transistor (DT) via a first node (N1). The second-second source / drain electrode (SD22) can be connected to the first power line 51 via a contact hole 71.

[0115] The light-emitting control transistor (T6, the sixth transistor) may include a sixth channel (CH6), a sixth-first source / drain electrode (SD61), and a sixth-second source / drain electrode (SD62) located in the first active layer (ACT), and a sixth gate electrode (GE6) superimposed on the sixth channel (CH6) in the third direction (Z). The sixth gate electrode (GE6) can be connected to the fifth gate line 32 via a contact hole 72. The sixth-first source / drain electrode (SD61) can be connected to the first-second source / drain electrode (SD12) of the drive transistor (DT) via a third node (N3). The sixth-second source / drain electrode (SD62) can be connected to the anode electrode of the light-emitting element (OLED, Figure 7) via a contact hole 73 and a connecting electrode 107.

[0116] The third initialization transistor (T8, the eighth transistor) may include an eighth channel (CH8), an eighth-first source / drain electrode (SD81), and an eighth-second source / drain electrode (SD82) located in the first active layer (ACT), and an eighth gate electrode (GE8) superimposed on the eighth channel (CH8) in the third direction (Z). The eighth gate electrode (GE8) can be integrally connected to the third gate line 32. The eighth-first source / drain electrode (SD81) can be connected to the fifth-second source / drain electrode (SD52) of the operation control transistor (T5). The eighth-second source / drain electrode (SD82) can be connected to the third initialization voltage line 43 via a contact hole 74.

[0117] The second initialization transistor (T7, the seventh transistor) may include a seventh channel (CH7), a seventh-first source / drain electrode (SD71), and a seventh-second source / drain electrode (SD72) located in the first active layer (ACT), and a seventh gate electrode (GE7) superimposed on the seventh channel (CH7) in the third direction (Z). The seventh gate electrode (GE7) can be integrally connected to the third gate line 32. The seventh-first source / drain electrode (SD71) can be connected to the sixth-second source / drain electrode (SD62) of the light emission control transistor (T6). The seventh-second source / drain electrode (SD72) can be connected to the second-second initialization voltage line 42gb via a contact hole 75.

[0118] The sampling transistor (T3) may include a third channel (CH3), a third-first source / drain electrode (SD31), and a third-second source / drain electrode (SD32) located in the second active layer (OACT), and a third gate electrode (GE3) superimposed on the third channel (CH3) in the third direction (Z). The third gate electrode (GE3) is integrally formed with the lower line 103 of the first gate line 31 and can be connected to the upper line 104 of the first gate line 31 via a contact hole 63. The third-first source / drain electrode (SD31) can be connected to the third node (N3) of the drive transistor (DT) via contact holes 68, 69 and a connecting electrode 106. The third-second source / drain electrode (SD32) can be connected to the second node (N2) of the drive transistor (DT) via contact holes 64, 65 and a connecting electrode 105. The sampling transistor (T3) and the first light-shielding electrode 112 superimposed in the third direction (Z) can be connected to the upper line 104 of the first gate line 31 via the contact hole 163.

[0119] The first initialization transistor (T4, fourth transistor) may include a fourth channel (CH4), a fourth-first source / drain electrode (SD41), and a fourth-second source / drain electrode (SD42) located in the second active layer (OACT), and a fourth gate electrode (GE4) superimposed on the fourth channel (CH4) in the third direction (Z). The fourth gate electrode (GE4) can be connected to the fourth gate line 34 via a contact hole 66. The fourth-first source / drain electrode (SD41) can be connected to the second node (N2) of the drive transistor (DT) via contact holes 64, 65 and a connecting electrode 105. The fourth-second source / drain electrode (SD42) can be connected to the first initialization voltage line 41 via a contact hole 67. The third light-shielding electrode 114 superimposed on the first initialization transistor (T4) in the third direction (Z) can be connected to the fourth gate line 34 via a contact hole 166.

[0120] Referring to Figure 8A, the subpixel driver transistor (DT) in the comparative example can have a structure without dummy holes.

[0121] Referring to Figure 8B, a subpixel driver transistor (DT) according to one embodiment may include a gate electrode (GE1) and a dummy hole 120 and dummy electrode 122 superimposed in the third direction (Z).

[0122] Referring to Figure 8C, a subpixel driver transistor (DT) according to one embodiment may include a gate electrode (GE1) and two dummy holes 124 and dummy electrodes 126 superimposed in the third direction (Z).

[0123] Referring to Figure 8D, a subpixel drive transistor (DT) according to one embodiment includes a gate electrode (GE1) and two dummy holes 124 and a dummy electrode 126 superimposed in the third direction (Z), and may include a plurality of contact holes (dummy holes) 69a, 73a, 77 further arranged in a region adjacent to the drive transistor (DT). For example, the number of contact holes 69a of the connecting electrode 106, to which the sampling transistor (T3) and the third node (N3) of the drive transistor (DT) are connected, can be increased to two, and the number of contact holes 73a of the connecting electrode 107, to which the light emission control transistor (T6) is connected, can be increased to two. Two more dummy holes 77 can be arranged in a protruding region projecting in the second direction (Y) from the third initialization voltage line 43.

[0124] Table 1 below shows the subthreshold swing factor (S-factor value), critical voltage (Vth), and temperature-dependent critical voltage fluctuation (ΔVth) of the drive transistor (DT) in the subpixels for the comparative example shown in Figure 8A and each embodiment shown in Figures 8B to 8D.

[0125] [Table 1]

[0126] Referring to Table 1, compared to the driver transistor (DT) without dummy holes shown in Figure 8A, the driver transistors (DT) with dummy holes 120, 124, 69a, 73a, and 77 shown in Figures 8B to 8D show that as the number of dummy holes increases, the S-factor value and the critical voltage fluctuation amount (ΔVth) due to temperature increase, and the critical voltage (Vth) decreases.

[0127] Figure 9 is a cross-sectional view illustrating the structure of a subpixel according to one embodiment.

[0128] Specifically, Figure 9 illustrates the cross-sectional structure of subpixels along the I-I' and II-II' sections shown in Figure 8C.

[0129] Referring to Figures 8C and 9, a subpixel according to one embodiment may include a circuit element layer containing a pixel circuit disposed on a substrate (SUB), an light-emitting element layer containing a light-emitting element disposed on the circuit element layer, and a sealing layer (ENCAP) disposed on the light-emitting element layer. The circuit element layer may include a drive transistor (DT), a switching transistor (T2), a sampling transistor (T3), a first initialization transistor (T4), an operation control transistor (T5), a light emission control transistor (T6), a second initialization transistor (T7), a third initialization transistor (T8), and a storage capacitor (Cst).

[0130] In one embodiment, a touch sensor array including multiple touch electrodes can be further arranged on the sealing layer (ENCAP). A color filter array including a color filter and a black matrix, or a lens array, can be further arranged on the touch sensor array.

[0131] Figure 9 shows typical cross-sectional structures of the light emission control transistor (T6), the drive transistor (DT), the storage capacitor (Cst), and the sampling transistor (T3).

[0132] In one embodiment, the light-emitting control transistor (T6) and the drive transistor (DT) may include a first active layer (ACT) made of LTPS.

[0133] In one embodiment, the sampling transistor (T3) may include a second active layer (OACT) made of an oxide semiconductor. For example, the second active layer (OACT) may be made of an oxide semiconductor containing at least one of the following: IZO (InZnO) system, IGO (InGaO) system, ITO (InSnO) system, ZTO (ZnSnO) system, IGZO (InGaZnO) system, IGZTO (InGaZnSnO) system, GZTO (GaZnSnO) system, GZO (GaZnO) system, and ITZO (InSnZnO) system. In one embodiment, the sampling transistor (T3) may include an active layer made of LTPS.

[0134] The substrate (SUB) may include a plastic substrate or a glass substrate. The plastic substrate may be made of a flexible material. For example, the substrate (SUB) may include at least one organic insulating material from among acrylic resins, epoxy resins, siloxane resins, polyimide resins, and polyamide resins.

[0135] A lower buffer layer (MBF) can be placed on the substrate (SUB). The lower buffer layer (MBF) can prevent impurities such as hydrogen from flowing into the first active layer (ACT) through the substrate (SUB). The lower buffer layer (MBF) may include an inorganic insulating material. For example, the lower buffer layer (MBF) may include an oxide-based insulating material such as silicon oxide (SiOx) or aluminum oxide (Al2O3). In one embodiment, a barrier layer that can block the inflow of particles may be further placed between the substrate (SUB) and the lower buffer layer (MBF). The barrier layer may consist of a multi-barrier layer in which at least one organic insulating layer and at least one inorganic insulating layer are alternately laminated.

[0136] The drive transistor (DT) may include a first channel (CH1), a first-first source / drain electrode (SD11), and a first-second source / drain electrode (SD12) located in the first active layer (ACT), and a first gate electrode (GE1) superimposed on the first channel (CH1) in the third direction (Z) with a first gate insulating layer (GI1) in between.

[0137] The light-emitting control transistor (T6) may include a sixth channel (CH6), a sixth-first source / drain electrode (SD61), and a sixth-second source / drain electrode (SD62) located in the first active layer (ACT), and a sixth gate electrode (GE6) superimposed in the third direction (Z) with the sixth channel (CH6) and the first gate insulating layer (GI1) in between.

[0138] The first and second source / drain electrodes (SD12) of the drive transistor (DT) and the sixth and first source / drain electrodes (SD61) of the light emission control transistor (T6) can be connected via the first active layer (ACT). The first gate electrode (GE1) of the drive transistor (DT) can be formed integrally with the first capacitor electrode (C1) of the storage capacitor (Cst).

[0139] The drive transistor (DT) may further include a dummy hole 124 that penetrates multiple insulating layers, including first and second upper buffer layers (ABF1, ABF2), a second gate insulating layer (GI2), and an interlayer insulating layer (ILD) stacked on a first gate electrode (GE1), and a dummy electrode 126 disposed on the interlayer insulating layer (ILD) and connected to the first gate electrode (GE1) via the dummy hole 124.

[0140] The gate insulating layers (GI1, GI2), upper buffer layers (ABF1, ABF2), and interlayer insulating layer (ILD) may contain inorganic insulating materials such as silicon oxide (SiO2) or silicon nitride (SiNx).

[0141] The storage capacitor (Cst) may include a first capacitor electrode (C1) connected to the first gate electrode (GE1) of the drive transistor (DT), and a second capacitor electrode (C2) superimposed in the third direction (Z) with a first upper buffer layer (ABF1) in between. The second upper buffer layer (ABF2) can be placed on the second capacitor electrode (C2).

[0142] The sampling transistor (T3) located on the second upper buffer layer (ABF2) may include the third channel (CH3), third-first source / drain electrode (SD31), and third-second source / drain electrode (SD32) of the second active layer (OACT) located on the second upper buffer layer (ABF2), and a third gate electrode (GE3) superimposed on the third channel (CH3) in the third direction (Z) with the second gate insulating layer (GI2) in between. The sampling transistor (T3) may further include a light-shielding electrode 112 located between the first and second upper buffer layers (ABF1, ABF2) and superimposed on the third channel (CH3) of the second active layer (OACT) in the third direction (Z).

[0143] An interlayer insulating layer (ILD) can be placed on the sampling transistor (T3). The third-first source / drain electrode (SD31) of the sampling transistor (T3) can be connected to a connecting electrode 106 placed on the interlayer insulating layer (ILD) via a contact hole 68. The third-second source / drain electrode (SD32) of the sampling transistor (T3) can be connected to a connecting electrode 105 placed on the interlayer insulating layer (ILD) via a contact hole 65, and the connecting electrode 105 can be connected to the first capacitor electrode (C1) via a contact hole 64. The gate electrode (GE3) of the sampling transistor (T3) can be superimposed in the third direction on the upper line 104 of the first gate line 31.

[0144] The first gate line 31 may include a lower line 103 on the second gate insulating layer (GI2) and an upper line 104 located on the interlayer insulating layer (ILD) and superimposed on the lower line 103 in a third direction.

[0145] The 6-2 source / drain electrode (SD62) of the light-emitting control transistor (T6) can be connected to a connecting electrode 102 located on the interlayer insulating layer (ILD) via a contact hole 73.

[0146] The connecting electrode 102 of the light-emitting control transistor (T6) can be connected to the connecting electrode 92-3 located on the first planarization layer (PLN1) via the contact hole 83-2, and can also be connected to the anode electrode (AE3) located on the second planarization layer (PLN2) via the contact hole 84-3.

[0147] A light-emitting element layer, including a light-emitting element, a bank layer (BK), and a spacer (SP), can be arranged on the second planarization layer (PLN2).

[0148] The light-emitting element may include an anode electrode (first electrode) (AE3), an emission stack (EML3), and a cathode electrode (second electrode) (CE) arranged on a second planarization layer (PLN2). The anode electrode (AE3) may be separated and arranged independently for each subpixel. The anode electrode (AE3) may be formed from a multiple conductive layer structure with high reflectivity. For example, the anode electrode (AE3) may be formed from a laminated structure of aluminum (Al) and titanium (Ti) (Ti / Al / Ti), a laminated structure of aluminum (Al) and ITO (Indium Tin Oxide) (ITO / Al / ITO), or a laminated structure of APC and ITO (ITO / APC / ITO). APC is an alloy of silver (Ag), palladium (Pd), and copper (Cu).

[0149] The anode electrode (AE3) has an opening on the placed second planarization layer (PLN2) that exposes the anode electrode (AE3), and a bank layer (BK) can be placed over the end of the anode electrode (AE3). The opening of the bank layer (BK) can be defined as the light-emitting region (EA3), and the region on which the bank layer (BK) is placed can be defined as the non-light-emitting region. The bank layer (BK) surrounding the light-emitting region can be formed as a single-layer or double-layer structure. A spacer (SP) having an opening wider than the opening of the bank layer (BK) can be further placed on the bank layer (BK). The spacer (SP) can support a fine metal mask (FMM), which is a deposition mask when forming the light-emitting stack (EML3). The bank layer (BK) and spacer (SP) can be formed from an organic insulating material. The bank layer (BK) can contain a light-shielding material that can block light leakage between adjacent pixels and reduce reflection of external light.

[0150] The light-emitting stack (EML3) can be formed by stacking a hole control layer, a light-emitting layer, and an electron control layer in either the order or the reverse order. The hole control layer may include at least a hole transport layer from among a hole injection layer and a hole transport layer, and the electron control layer may include at least an electron transport layer from among an electron transport layer and an electron injection layer.

[0151] The cathode electrode (CE) may be a common electrode positioned on the light-emitting stack (EML3) and connected along the surfaces of the bank layer (BK) and spacer (SP). The cathode electrode (CE) can be formed from a conductive material with high light transmittance or a semi-transparent conductive material. For example, the cathode electrode (CE) can be formed from a transparent conductive material such as ITO or IZO. The cathode electrode (CE) can be formed from a semi-transparent metallic material such as magnesium (Mg), silver (Ag), or alloys thereof. A capping layer may be further positioned on the cathode electrode (CE) to enhance the optical resonance and luminescence efficiency of the light-emitting element.

[0152] An encapsulation layer (ENCAP) is placed on the light-emitting element layer to seal it, preventing moisture and oxygen from penetrating the light-emitting element and covering particles to prevent them from flowing. The encapsulation layer (ENCAP) can have a laminated structure of first and second inorganic encapsulation layers (PAS1, PAS2) and an organic encapsulation layer (PCL) placed between the first and second inorganic encapsulation layers (PAS1, PAS2). The inorganic encapsulation layers (PAS1, PAS2) can prevent moisture and oxygen from penetrating from the outside. The organic encapsulation layer (PCL) can cover particles and buffer the stress between each layer when the display panel is bent.

[0153] Figure 10 is a graph comparing the temperature luminance sensitivity of the display devices according to the comparative example and one embodiment, and Figure 11 is a graph comparing the temperature color sensitivity of the display devices according to the comparative example and one embodiment.

[0154] In Figure 10, the vertical axis represents temperature luminance sensitivity (TLS). In Figure 11, the vertical axis represents the shift amount (Δu'v') of the white color coordinates corresponding to temperature color sensitivity (TCS).

[0155] Referring to Figures 10 and 11, the display device according to the comparative example, as shown in the comparative example in Figure 8A, can include drive transistors (DTs) without dummy holes for the R / G / B subpixels. In the comparative example, the critical voltage fluctuation (ΔVth) of each drive transistor (DT) of the R / G / B subpixels may be relatively low, around 7.7 mV / °C. As a result, in the display device according to the comparative example, the temperature luminance sensitivity (TLS) (1.19, 1.34, 4.50) of each R / G / B subpixel and the temperature luminance sensitivity (TLS, 1.62) of white light (W) are relatively high, and in particular the temperature luminance sensitivity (TLS) of the B subpixel is relatively high (4.50), and the white color coordinate shift amount (Δu'v'=0.044) is also relatively high.

[0156] The display device according to the first embodiment, as shown in the embodiment in Figure 8B, can include a drive transistor (DT) in which each R / G / B subpixel has one dummy hole 120. In the first embodiment, the critical voltage fluctuation amount (ΔVth) of each drive transistor (DT) with respect to temperature can be increased to about 10.6 mV / °C compared to the comparative example (7.7 mV / °C). As a result, in the display device according to the first embodiment, the temperature luminance sensitivity (TLS) (0.92, 1.10, 2.20) of each R / G / B subpixel and the temperature luminance sensitivity (TLS, 1.22) of white light (W) are reduced compared to the comparative example. Furthermore, in the display device according to the first embodiment, the difference between the temperature luminance sensitivity (TLS) (0.92, 1.10) of the R / G subpixels and the temperature luminance sensitivity (TLS, 2.20) of the B subpixels is reduced, and the amount of white color coordinate shift (Δu'v'=0.018) is also reduced compared to the comparative example (Δu'v'=0.044).

[0157] The display device according to the second embodiment may include a drive transistor (DT) with one dummy hole 120 for the R / G subpixel, as shown in the embodiment in Figure 8B, and a drive transistor (DT) with two dummy holes 124 for the B subpixel, as shown in the embodiment in Figure 8C. The critical voltage fluctuation (ΔVth) of the B subpixel's drive transistor (DT) due to temperature is approximately 11.5 mV / °C, which is higher than the comparative example (7.7 mV / °C) and the critical voltage fluctuation (10.6 mV / °C) of the R / G subpixel's drive transistor. As a result, the temperature luminance sensitivity (TLS) (1.44, 1.59, 2.04) of each R / G / B subpixel and the temperature luminance sensitivity (TLS, 1.71) of white light (W) are reduced in the display device according to the second embodiment compared to the comparative example. Furthermore, in the display device according to the second embodiment, the difference between the temperature luminance sensitivity (TLS) (1.44, 1.59) of the R / G subpixels and the temperature luminance sensitivity (TLS, 2.04) of the B subpixels was reduced compared to the first embodiment, and the amount of white color coordinate shift (Δu'v'=0.009) was also reduced compared to the comparative example (Δu'v'=0.044) and the first embodiment (Δu'v'=0.018).

[0158] The display device according to the third embodiment includes a drive transistor (DT) having one dummy hole 120 for the R / G subpixel, as shown in the embodiment in Figure 8B, and a drive transistor (DT) having two dummy holes 124 for the B subpixel, as shown in the embodiment in Figure 8D. The peripheral region of the drive transistor (DT) may further include six dummy holes 69a, 73a, and 77. The critical voltage fluctuation amount (ΔVth) of the drive transistor (DT) of the B subpixel due to temperature is approximately 11.8 mV / °C, which can be increased compared to the comparative example (7.7 mV / °C) and the critical voltage fluctuation amount of the drive transistor of the R / G subpixel due to temperature (10.6 mV / °C). As a result, it can be seen that in the display device according to the third embodiment, the temperature luminance sensitivity (TLS) (1.18, 1.22, 1.87) of each R / G / B subpixel and the temperature luminance sensitivity (TLS, 1.36) of white light (W) are reduced compared to the comparative example. Furthermore, in the display device according to the third embodiment, the difference between the temperature luminance sensitivity (TLS) (1.18, 1.22) of the R / G subpixels and the temperature luminance sensitivity (TLS, 1.87) of the B subpixels was reduced compared to the first embodiment, and the amount of white color coordinate shift (Δu'v'=0.010) was also reduced compared to the comparative example (Δu'v'=0.044) and the first embodiment (Δu'v'=0.018).

[0159] Figures 12A to 12D show a comparison of the white color coordinate variation due to temperature fluctuations in a display device according to a comparative example and one embodiment.

[0160] In Figures 12A to 12D, the horizontal axis represents u' chromaticity, the vertical axis represents v' chromaticity, and the white color coordinates are shown with respect to temperature in the u'v' chromaticity coordinate system.

[0161] Referring to Figure 12A, the display device according to the comparative example, as shown in the comparative example in Figure 8A, can include drive transistors (DTs) without dummy holes for the R / G / B subpixels, and the critical voltage fluctuation (ΔVth) of each drive transistor (DT) of the R / G / B subpixels with respect to temperature may be relatively low, around 7.7mV / °C. As a result, in the display device according to the comparative example, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels are relatively low, and the range of white color coordinate fluctuation due to temperature fluctuations is relatively large. Consequently, the range of white color coordinate fluctuation between room temperature (20°C) and high temperature (40°C) is also large, as is the range of white color coordinate fluctuation between room temperature (20°C) and low temperature (10°C).

[0162] Referring to Figure 12B, the display device according to the first embodiment can include a drive transistor (DT) with one dummy hole 120 for each R / G / B subpixel, as shown in the embodiment in Figure 8B. The critical voltage fluctuation amount (ΔVth) of each drive transistor (DT) with respect to temperature can be increased to about 10.6 mV / °C compared to the comparative example (7.7 mV / °C). As a result, in the display device according to the first embodiment, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels are reduced compared to the comparative example, resulting in a reduction in the range of white color coordinate fluctuations due to temperature fluctuations. This means that the range of white color coordinate fluctuations between room temperature (20°C) and high temperature (40°C), and between room temperature (20°C) and low temperature (10°C) are all reduced compared to the comparative example.

[0163] Referring to Figure 12C, in the display device according to the first embodiment, the R / G subpixel may include a drive transistor (DT) having one dummy hole 120, as in the embodiment shown in Figure 8B, and the B subpixel may include a drive transistor (DT) having two dummy holes 124, as in the embodiment shown in Figure 8C. The critical voltage fluctuation (ΔVth) of the B subpixel's drive transistor (DT) due to temperature is approximately 11.5 mV / °C, which can be increased from the comparative example (7.7 mV / °C) and the critical voltage fluctuation (10.6 mV / °C) of the R / G subpixel's drive transistor. This shows that the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels in the display device according to the second embodiment are reduced compared to the comparative example and the first embodiment, as the range of variation in the white color coordinates at room temperature (20°C) and high temperature (40°C), and the range of variation in the white color coordinates at room temperature (20°C) and low temperature (10°C) are both reduced compared to the comparative example and the first embodiment.

[0164] Referring to Figure 12D, in the display device according to the third embodiment, the R / G subpixel may include a drive transistor (DT) having one dummy hole 120, as in the embodiment shown in Figure 8B, and the B subpixel may further include six dummy holes (69a, 73a, 77) in the peripheral region of the drive transistor (DT) having two dummy holes 124, as in the embodiment shown in Figure 8D. The critical voltage fluctuation amount (ΔVth) of the drive transistor (DT) of the B subpixel due to temperature is approximately 11.8 mV / °C, which can be increased compared to the comparative example (7.7 mV / °C) and the critical voltage fluctuation amount of the drive transistor of the R / G subpixel due to temperature (10.6 mV / °C). In the display device according to the third embodiment, the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of the R / G / B subpixels were reduced compared to the comparative example and the first embodiment, resulting in a reduction in the range of variation of the white color coordinate with temperature fluctuations. Consequently, the range of variation between the white color coordinate at room temperature (20°C) and high temperature (40°C), and between the white color coordinate at room temperature (20°C) and low temperature (10°C) were all reduced compared to the comparative example and the first embodiment.

[0165] As described above, the display device according to one embodiment can reduce or minimize the temperature luminance sensitivity (TLS) and temperature color sensitivity (TCS) of subpixels by applying a dummy hole to the insulating layer of the drive transistor and controlling the amount of critical voltage fluctuation of the drive transistor due to temperature.

[0166] In one embodiment, the display device applies different numbers and area ratios of dummy holes to the insulating layer of subpixels based on the aperture ratio (area) of the light-emitting element or the brightness fluctuation characteristics due to the temperature of the light-emitting element. By controlling the amount of critical voltage fluctuation of the drive transistor due to temperature to vary, the difference in brightness fluctuations between subpixels due to temperature fluctuations can be minimized, and as a result, the fluctuation of the white color coordinate due to temperature fluctuations can be minimized, thereby improving optical quality.

[0167] The display device according to one embodiment can improve optical quality by controlling the critical voltage fluctuation of the drive transistor due to temperature, thereby reducing or minimizing the temperature luminance sensitivity and temperature color sensitivity of subpixels, and thus can provide improved image quality with low power consumption.

[0168] A display device according to one embodiment includes a first subpixel comprising a first light-emitting element that emits a first color of light and a first drive transistor that drives the first light-emitting element, a second light-emitting element that emits a second color of light, and a second subpixel comprising a second drive transistor that drives the second light-emitting element, wherein the first drive transistor and the second drive transistor may have different dummy hole area ratios.

[0169] In one embodiment of the display device, the dummy hole area of ​​the first drive transistor may be larger than the dummy hole area of ​​the second drive transistor.

[0170] In one embodiment of the display device, the number of dummy holes of the first drive transistor may be greater than the number of dummy holes of the second drive transistor.

[0171] In a display device according to one embodiment, the first subpixel may further include a peripheral dummy hole located in the insulating layer surrounding the first drive transistor.

[0172] A display device according to one embodiment further includes a third subpixel comprising a third light-emitting element that emits a third color of light and a third drive transistor that drives the third light-emitting element, wherein the third drive transistor may have the same dummy hole area ratio as any one of the first and second drive transistors, or may have a different dummy hole area ratio than the first and second drive transistors.

[0173] In a display device according to one embodiment, each of the first to third drive transistors may further include a dummy electrode connected to the corresponding gate electrode via the corresponding dummy hole.

[0174] In a display device according to one embodiment, the dummy holes of the first to third drive transistors can be configured to be filled with an upper insulating layer.

[0175] In one embodiment of the display device, the area of ​​each dummy hole may be the same as the area of ​​each contact hole located in the first to third subpixels.

[0176] In a display device according to one embodiment, the first to third subpixels are blue, green, and red subpixels, respectively. The dummy hole area of ​​the first drive transistor for the blue subpixel is larger than the dummy hole area of ​​the second drive transistor for the green subpixel, and larger than the dummy hole area of ​​the third drive transistor for the red subpixel. The dummy hole area of ​​the second drive transistor and the dummy hole area of ​​the third drive transistor may be the same.

[0177] In a display device according to one embodiment, the first to third subpixels are blue, green, and red subpixels, respectively. The number of dummy holes of the first drive transistor for the blue subpixel is greater than the number of dummy holes of the second drive transistor for the red subpixel, and greater than the number of dummy holes of the third drive transistor for the green subpixel. The number of dummy holes of the second drive transistor and the number of dummy holes of the third drive transistor may be the same.

[0178] A display device according to one embodiment includes a first subpixel comprising a first light-emitting element that emits a first color of light, a first drive transistor that drives the first light-emitting element, and a first dummy hole superimposed on the first gate electrode of the first drive transistor; a second subpixel comprising a second light-emitting element that emits a second color of light, a second drive transistor that drives the second light-emitting element, and a second dummy hole superimposed on the second gate electrode; and a third subpixel comprising a third light-emitting element that emits a third color of light, a third drive transistor that drives the third light-emitting element, and a third dummy hole superimposed on the third gate electrode of the third drive transistor. The area ratio of the first dummy hole is different from the area ratio of the second dummy hole and the area ratio of the third dummy hole, and the area ratio of the second dummy hole may be the same as or different from the area ratio of the third dummy hole.

[0179] In one embodiment of the display device, the number of first dummy holes of the first drive transistor may be greater than the number of second dummy holes of the second drive transistor and greater than the number of third dummy holes of the third drive transistor.

[0180] In one embodiment of the display device, the area of ​​the first dummy hole of the first drive transistor may be larger than the area of ​​the second dummy hole of the second drive transistor and larger than the area of ​​the third dummy hole of the third drive transistor.

[0181] In one embodiment of the display device, the number or area of ​​the second dummy holes of the second drive transistor may be the same as the number or area of ​​the third dummy holes of the third drive transistor.

[0182] In one embodiment of the display device, the area of ​​each of the first to third dummy holes may be the same as the area of ​​each of the contact holes arranged in the multiple insulating layers of the first to third subpixels.

[0183] A display device according to one embodiment further includes a first dummy electrode connected to a first gate electrode via a first dummy hole of a first drive transistor, a second dummy electrode connected to a second gate electrode via a second dummy hole of a second drive transistor, and a third dummy electrode connected to a third gate electrode via a third dummy hole of a third drive transistor, wherein the area of ​​the first dummy electrode is different from the area of ​​the second dummy electrode and the area of ​​the third dummy electrode, and the area of ​​the second dummy electrode is the same as or may be different from the area of ​​the third dummy electrode.

[0184] In a display device according to one embodiment, the first to third dummy holes may be filled with an upper insulating layer.

[0185] In a display device according to one embodiment, the first subpixel may further include a plurality of peripheral dummy holes arranged in a plurality of insulating layers around the first drive transistor.

[0186] In one embodiment of the display device, the aperture ratios of the first to third light-emitting elements may differ.

[0187] In one embodiment of the display device, the brightness variation characteristics due to temperature of the first to third light-emitting elements may differ.

[0188] In a display device according to one embodiment, the critical voltage fluctuation amount due to the temperature of the first drive transistor is different from the critical voltage fluctuation amount due to the temperature of the second drive transistor and the critical voltage fluctuation amount due to the temperature of the third drive transistor, and the critical voltage fluctuation amount due to the temperature of the second drive transistor may be the same as or different from the critical voltage fluctuation amount due to the temperature of the third drive transistor.

[0189] In one embodiment of the display device, a plurality of transistors are further included, each of the first to third drive transistors, and the first to third drive transistors and the plurality of transistors may include at least one active layer from among a polysilicon semiconductor layer and an oxide semiconductor.

[0190] In each of the first to third subpixels of a display device according to one embodiment, at least one of a plurality of transistors and the corresponding driving transistor is a polysilicon transistor including a polysilicon semiconductor layer, and at least one of the plurality of transistors is an oxide transistor including an oxide semiconductor layer, the oxide transistor is disposed on at least one lower insulating layer disposed on the polysilicon transistor, and each of the first to third dummy holes can be provided penetrating at least one insulating layer of the polysilicon transistor, at least one lower insulating layer on the polysilicon transistor and at least one upper insulating layer on the oxide transistor.

[0191] In a display device according to one embodiment, each of the first to third drive transistors further includes first to third dummy electrodes connected to the first to third gate electrodes, respectively, via first to third dummy holes, and the first to third dummy electrodes can be arranged on at least one upper insulating layer on the oxide transistor.

[0192] A display device according to one embodiment includes a first light-emitting element that emits a first color of light, a first drive transistor that drives the first light-emitting element, and a first subpixel including at least one first dummy hole disposed on the first drive transistor, a second light-emitting element that emits a second color of light, and a second drive transistor that drives the second light-emitting element, and a second subpixel including at least one second dummy hole disposed on the second drive transistor, wherein the first drive transistor and the second drive transistor may have different total dummy hole aperture areas depending on the brightness variation characteristics of the first light-emitting element and the second light-emitting element due to temperature.

[0193] A display device according to one embodiment includes a first light-emitting element that emits light of a first color, a first drive transistor that drives the first light-emitting element, and a first subpixel including at least one first dummy hole disposed on the first drive transistor, a second light-emitting element that emits light of a second color, and a second drive transistor that drives the second light-emitting element, and a second subpixel including at least one second dummy hole disposed on the second drive transistor, wherein the first drive transistor and the second drive transistor may have different total dummy hole aperture areas depending on the aperture areas of the first light-emitting element and the second light-emitting element.

[0194] The display devices described herein can be applied to any electronic device. For example, the display devices described herein can be applied to mobile devices, video phones, smartwatches, watch phones, wearable devices, foldable devices, rollable devices, bendable devices, flexible devices, curved devices, electronic organizers, ebooks, portable multimedia players (PMPs), personal digital assistants (PDAs), MP3 players, mobile medical devices, desktop PCs, laptop PCs, netbook computers, workstations, navigation systems, vehicle navigation systems, vehicle display devices, televisions, wallpaper display devices, signage devices, game consoles, laptops, monitors, cameras, video cameras, and consumer electronics.

[0195] The features, structures, effects, etc., described in the various examples of this specification described above are included in, and not necessarily limited to, at least one example of this specification. Furthermore, the features, structures, effects, etc., exemplified in at least one example of this specification can be combined or modified and implemented in other examples by a person with ordinary skill in the art to which the technical idea of ​​this specification belongs. Accordingly, the content related to such combinations and modifications should be construed as being included in the scope of the technology or rights of this specification.

[0196] This specification, as described above, is not limited by the embodiments and accompanying figures, and it will be apparent to those with ordinary skill in the art to which this specification belongs that various substitutions, modifications, and alterations are possible without departing from the technical matters of this specification. Accordingly, the scope of this specification is indicated by the claims set forth below, and all modified or altered forms derived from the meaning, scope, and equivalent concepts of the claims should be construed as being included within the scope of this specification. [Explanation of symbols]

[0197] 100: Display panel 200: Gate Driver 300: Data Driver 400: Timing Controller 500: Gamma voltage generation unit 700: Power management circuit 1000: Display device SUB: Circuit board ACT: Active Layer CH1: Channel SD11, SD12, SD21, SD22: Source / Drain electrodes 11, 12: Contact holes 13, 23, 23a, 13b, 23b, 23c: Dummy holes SD14, SD15, SD23, SD24: Connecting electrodes SD16, SD25: Dummy electrodes DT_SP1, DT_SP2, DTa_SP2, DTb_SP1, DTb_SP2, DTC_SP2, DT: drive transistor

Claims

1. A first subpixel including a first light-emitting element that emits light of a first color, and a first drive transistor that drives the first light-emitting element, A second subpixel including a second light-emitting element that emits a second color of light, and a second drive transistor that drives the second light-emitting element, At least one first dummy hole is placed in the first drive transistor, At least one second dummy hole is placed in the second drive transistor and Includes, A display device in which the total aperture area of ​​at least one first dummy hole of the first drive transistor is different from the total aperture area of ​​at least one second dummy hole of the second drive transistor.

2. The display device according to claim 1, wherein the total aperture area of ​​at least one first dummy hole of the first drive transistor is greater than the total aperture area of ​​at least one second dummy hole of the second drive transistor.

3. The display device according to claim 1, wherein the number of at least one first dummy holes of the first drive transistor is greater than the number of at least one second dummy holes of the second drive transistor.

4. The display apparatus according to claim 1, wherein the first subpixel further comprises at least one peripheral dummy hole disposed in the insulating layer surrounding the first drive transistor.

5. A third subpixel including a third light-emitting element that emits a third color of light, and a third drive transistor that drives the third light-emitting element, At least one third dummy hole is placed in the third drive transistor and It further includes, The display device according to claim 1, wherein the total opening area of ​​the at least one third dummy hole of the third drive transistor is the same as the total opening area of ​​the at least one first dummy hole of the first drive transistor and the total opening area of ​​the at least one second dummy hole of the second drive transistor, or is different from the total opening area of ​​the at least one first dummy hole of the first drive transistor and the total opening area of ​​the at least one second dummy hole of the second drive transistor.

6. The first drive transistor further includes a first dummy electrode connected to the first gate electrode of the first drive transistor via at least one first dummy hole, The second drive transistor further includes a second dummy electrode connected to the second gate electrode of the second drive transistor via at least one second dummy hole, The display apparatus according to claim 5, wherein the third drive transistor further includes a third dummy electrode connected to the third gate electrode of the third drive transistor via at least one third dummy hole.

7. The display device according to claim 5, wherein the aperture area of ​​each of the at least one first to third dummy holes is the same as the aperture area of ​​each of the at least one contact holes arranged in the first to third subpixels.

8. The first to third subpixels are, respectively, a blue subpixel, a green subpixel, and a red subpixel. The total aperture area of ​​at least one first dummy hole of the first drive transistor for the blue subpixel is greater than the total aperture area of ​​at least one second dummy hole of the second drive transistor for the green subpixel, and greater than the total aperture area of ​​at least one third dummy hole of the third drive transistor for the red subpixel. The display device according to claim 5, wherein the total opening area of ​​at least one second dummy hole of the second drive transistor and the total opening area of ​​at least one third dummy hole of the third drive transistor are the same.

9. The first to third subpixels are, respectively, a blue subpixel, a green subpixel, and a red subpixel. The number of at least one first dummy holes in the first drive transistor of the blue subpixel is greater than the number of at least one second dummy holes in the second drive transistor of the green subpixel, and greater than the number of at least one third dummy holes in the third drive transistor of the red subpixel. The display device according to claim 5, wherein the number of at least one second dummy holes of the second drive transistor and the number of at least one third dummy holes of the third drive transistor are the same.

10. A first light-emitting element that emits light of a first color, a first drive transistor that drives the first light-emitting element, and a first subpixel including at least one first dummy hole superimposed on the first gate electrode of the first drive transistor, A second light-emitting element that emits a second color of light, a second drive transistor that drives the second light-emitting element, and a second subpixel including at least one second dummy hole superimposed on the second gate electrode of the second drive transistor, A display device comprising a third light-emitting element that emits a third color of light, a third drive transistor that drives the third light-emitting element, and a third subpixel including at least one third dummy hole superimposed on the third gate electrode of the third drive transistor.

11. The total opening area of ​​the at least one first dummy hole is different from the total opening area of ​​the at least one second dummy hole and the total opening area of ​​the at least one third dummy hole. The display device according to claim 10, wherein the total opening area of ​​the at least one second dummy hole is the same as or different from the total opening area of ​​the at least one third dummy hole.

12. The display device according to claim 11, wherein the number of at least one first dummy holes of the first drive transistor is greater than the number of at least one second dummy holes of the second drive transistor and greater than the number of at least one third dummy holes of the third drive transistor.

13. The display device according to claim 11, wherein the total opening area of ​​the at least one first dummy hole of the first drive transistor is greater than the total opening area of ​​the at least one second dummy hole of the second drive transistor and greater than the total opening area of ​​the at least one third dummy hole of the third drive transistor.

14. The display device according to claim 11, wherein the number or total aperture area of ​​at least one second dummy hole of the second drive transistor is the same as the number or total aperture area of ​​at least one third dummy hole of the third drive transistor.

15. The display device according to claim 11, wherein the opening area of ​​each of the first to third dummy holes is the same as the opening area of ​​each of the at least one contact holes arranged in the plurality of insulating layers of the first to third subpixels.

16. A first dummy electrode connected to the first gate electrode via at least one first dummy hole of the first drive transistor, A second dummy electrode connected to the second gate electrode via at least one second dummy hole of the second drive transistor, A third dummy electrode connected to the third gate electrode via at least one third dummy hole of the third drive transistor and It further includes, The area of ​​the first dummy electrode is different from the area of ​​the second dummy electrode and the area of ​​the third dummy electrode. The display device according to claim 11, wherein the area of ​​the second dummy electrode is the same as or different from the area of ​​the third dummy electrode.

17. The display device according to claim 11, wherein at least one of the first to third dummy holes is filled with the upper insulating layer of the first to third gate electrodes.

18. The display apparatus according to claim 11, wherein the first subpixel further comprises a plurality of peripheral dummy holes disposed in a plurality of insulating layers around the first drive transistor.

19. The display device according to claim 11, wherein the aperture ratios of the first to third light-emitting elements are different.

20. The brightness variation characteristics due to temperature are different for the first to third light-emitting elements, or The critical voltage fluctuation amount due to the temperature of the first drive transistor is different from the critical voltage fluctuation amount due to the temperature of the second drive transistor and the critical voltage fluctuation amount due to the temperature of the third drive transistor. The display device according to claim 11, wherein the critical voltage fluctuation amount due to the temperature of the second drive transistor is the same as or different from the critical voltage fluctuation amount due to the temperature of the third drive transistor.

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