Level shift circuit
The level shift circuit addresses interrupted assist operations and transistor stress by using N-type and P-type transistor configurations with controlled inverters, enhancing speed and reducing voltage stress for improved performance.
Patent Information
- Authority / Receiving Office
- JP · JP
- Patent Type
- Patents
- Current Assignee / Owner
- SOCIONEXT INC
- Filing Date
- 2022-09-13
- Publication Date
- 2026-06-10
Smart Images
Figure 0007872498000001 
Figure 0007872498000002 
Figure 0007872498000003
Abstract
Description
【Technical Field】 【0001】 The present invention relates to a level shift circuit that converts a signal potential required when passing a signal between circuits supplied with different power supply voltages. 【Background Art】 【0002】 A level shift circuit is provided, for example, in an interface portion that transfers a signal from a relatively low-voltage circuit inside a semiconductor chip to a relatively high-voltage circuit outside the semiconductor chip, and is used when converting a signal potential. 【0003】 For example, Patent Document 1 discloses a level shift circuit that generates an output signal of a desired level according to the level of an input signal and supplies it to a next-stage semiconductor device or the like. 【0004】 Specifically, in FIG. 1 of Patent Document 1, when the initial state is Φ21 = L, since the node N23 = H (Vcc), the transistor 31 is off, the transistor 33 is on, the nodes N32, NZ5 = L, and the transistor 42 is off. Also, since the node N24 = L, the transistor 41 is on, the transistor 43 is off, the nodes N42, N26 = H (Vpp), and the transistor 32 is on. 【0005】 When Φ21 transitions from L to H, the transistor 31 turns on and the transistor 33 turns off, and Vcc is connected to the nodes NZ2, N25 through the transistors 31 and 32, and the node N25 rises. Thereby, in the level shift circuit of Patent Document 1, the level shift operation is assisted. 【Prior Art Documents】 【Patent Documents】 【0006】 【Patent Document 1】 Japanese Patent Laid-Open No. 7-202650 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0007】 However, in Figure 1 of Patent Document 1, when Φ21 transitions from L to H and node N23 becomes L, node N24 becomes H(Vcc), transistor 43 turns on, and nodes N42 and N26 change from H(Vpp) to L. As a result, transistor 32 turns off, and the connection between Vcc and nodes N25 and N32 via transistors 31 and 32 is broken. Consequently, as shown by the dashed circle in Figure 6, the level shift assist operation may be interrupted while the signal is rising to Vcc, resulting in insufficient speed enhancement. 【0008】 Furthermore, in the initial state shown in Figure 1 of Patent Document 1, transistor 41 is on and transistor 42 is off, so the node between transistor 41 and transistor 42 is Vcc. When Φ21 transitions from L to H from this state, node N24 transitions from L to H (Vcc), so transistor 41 turns off and transistor 43 turns on. Since transistor 42 remains in the off state, the node between transistor 41 and transistor 42 is boosted from Vcc by the gate-drain coupling capacitance of transistor 41. This presents the problem of stress being placed between the source and drain of transistor 42. While such voltage stress was not much of a problem in conventional transistors, it has become a problem that needs to be addressed with the miniaturization of manufacturing processes in recent years. 【0009】 This disclosure aims to solve the above problems and to further enhance the effectiveness of the assist operation in the level shift circuit, as well as to alleviate voltage stress on the transistor. [Means for solving the problem] 【0010】 A level shift circuit in one aspect of the present disclosure includes an input node that receives an input signal transitioning between a first power supply and a second power supply having a lower potential than the first power supply, an inverting input node that receives an inverting input signal obtained by inverting the input signal, a first N-type transistor whose gate is connected to the input node, whose source is connected to the second power supply or the inverting input node, and whose drain is connected to an inverting output node, a first P-type transistor whose drain is connected to the inverting output node, whose source is connected to a third power supply having a higher potential than the first power supply, and whose gate is connected to an output node, and a level shift circuit in one aspect of the present disclosure includes an input node that receives an input signal transitioning between a first power supply and a second power supply having a lower potential than the first power supply, an inverting input node that receives an inverting input signal obtained by inverting the input signal, and whose drain is connected to the The system comprises a second N-type transistor connected to an output node, a second P-type transistor whose drain is connected to the output node, whose source is connected to the third power supply, and whose gate is connected to the inverting output node, a third N-type transistor whose source is connected to the inverting input node, and whose drain is connected to the inverting output node, a first inverter whose input is connected to the inverting output node, and whose output is connected to the gate of the third N-type transistor, a fourth N-type transistor whose source is connected to the input node, and whose drain is connected to the output node, and a second inverter whose input is connected to the output node, and whose output is connected to the gate of the fourth N-type transistor. 【0011】 In the level shift circuit of this embodiment, the assist operation of the third transistor, which switches the supply of charge on and off, is turned off after a predetermined delay time by the first inverter has elapsed since the inverting output signal changed. Similarly, the assist operation of the fourth transistor, which switches the supply of charge on and off, is turned off after a predetermined delay time by the second inverter has elapsed since the output signal changed. As a result, a sufficient assist operation period can be ensured compared to the conventional technology, and the effectiveness of the assist operation can be further enhanced. 【0012】 Furthermore, in the technology described in Patent Document 1, when node N24 shown in Figure 1 becomes H, both transistors 41 and 42 turn off, resulting in a problem where the node between transistors 41 and 42 is boosted. In contrast, in this embodiment, during the assist operation, there is no point where transistors on both sides of a particular node simultaneously turn off and become floating, so the problem of boosting the voltage at a particular node does not occur. [Effects of the Invention] 【0013】 This disclosure provides a level shift circuit that can further enhance the effectiveness of the assist operation and reduce voltage stress on the transistor. [Brief explanation of the drawing] 【0014】 [Figure 1] Circuit diagram showing an example of the configuration of a level shift circuit according to the first embodiment. [Figure 2A] This diagram shows an example of the voltage waveforms at each node of a level shift circuit. [Figure 2B] This diagram shows another example of the voltage waveform at each node of a level shift circuit. [Figure 3A] Circuit diagram showing a modified example of the level shift circuit according to the first embodiment. [Figure 3B] Circuit diagram showing another variation of the level shift circuit according to the first embodiment. [Figure 4] Circuit diagram showing an example of the configuration of a level shift circuit according to the second embodiment. [Figure 5] Circuit diagram showing a modified configuration of the level shift circuit according to the second embodiment. [Figure 6] This figure shows an example of the voltage waveforms at each node of a conventional level shift circuit. [Figure 7] Circuit diagram showing another variation of the level shift circuit according to the first embodiment. [Figure 8] Circuit diagram showing another modified configuration of the level shift circuit according to the second embodiment. [Modes for carrying out the invention] 【0015】 Hereinafter, embodiments will be described. Note that the specific numerical values and the like shown in the following embodiments are merely examples for facilitating the understanding of the invention, and are not intended to limit the scope of the invention. In the following description, a circuit node, a signal passing through the node, and the voltage of the node may be described with the same reference numeral. Also, a power supply name and the power supply voltage of the power supply may be described with the same reference numeral. 【0016】 <First Embodiment> The level shift circuit 1 receives an input signal IN and an inverted input signal NIN that transition between a first power supply VDD and a ground VSS, and outputs an output signal OUT and an inverted output signal NOUT that transition between a third power supply VDDIO and a ground VSS. In other words, the input signal IN and the inverted input signal NIN are signals with an amplitude of VDD, and the output signal OUT and the inverted output signal NOUT are signals with an amplitude of VDDIO. The first power supply VDD is, for example, 0.8 [V], and the third power supply is, for example, 1.3 [V]. 【0017】 FIG. 1 shows an example of a circuit diagram of the level shift circuit 1 according to the first embodiment. 【0018】 The level shift circuit 1 includes a basic circuit composed of first and second N-type transistors N1 and N2 and first and second P-type transistors P1 and P2, and a rise assist circuit 2. 【0019】 - Basic Circuit - The gate of the first N-type transistor N1 is connected to the input node IN, the source is connected to the ground VSS, and the drain is connected to the inverted output node NOUT. The input signal IN is applied to the gate of the first N-type transistor N1 via the input node IN. Note that the ground VSS corresponds to the second power supply. In other words, the second power supply is not limited to the ground VSS, and may be a power supply having another potential lower than the first power supply VDD. 【0020】 The second N-type transistor N2 has its gate connected to the inverting input node NIN, its source connected to ground VSS, and its drain connected to the output node OUT. The gate of the second N-type transistor N2 is supplied with an inverting input signal NIN via the inverting input node NIN. 【0021】 In this example, the inverted input signal NIN is the signal obtained by inverting the input signal XIN via inverter 81. The input signal IN is the signal obtained by inverting the input signal XIN twice via inverters 81 and 82. Although not shown, the power terminal of inverter 81 is connected to the first power supply VDD, and the ground terminal is connected to ground VSS. Similarly, the power terminal of inverter 82 is connected to the first power supply VDD, and the ground terminal is connected to ground VSS. Note that inverters 81 and 82 may be omitted from Figure 1, and the input signal IN and the inverted input signal NIN may be generated in the pre-stage circuit (not shown) of the level shift circuit 1 and input to the level shift circuit 1. 【0022】 The first P-type transistor P1 has its gate connected to the output node OUT, its source connected to the third power supply VDDIO, and its drain connected to the inverting output node NOUT. In other words, the first P-type transistor P1 and the first N-type transistor N1 are connected in series between the third power supply VDDIO and ground VSS. The third power supply VDDIO is a power supply with a higher potential than the first power supply VDD. 【0023】 The second P-type transistor P2 has its gate connected to the inverting output node NOUT, its source connected to the third power supply VDDIO, and its drain connected to the output node OUT. In other words, the second P-type transistor P2 and the second N-type transistor N2 are connected in series between the third power supply VDDIO and ground VSS. 【0024】 -Rise assist circuit- Rise assist circuit 2 is a circuit that assists the rising edge of the output signal OUT or the rising edge of the inverted output signal NOUT. 【0025】 In this example, the rise assist circuit 2 comprises third and fourth N-type transistors N3 and N4, and first and second inverters 21 and 22. 【0026】 The third N-type transistor N3 has its source connected to the inverting input node NIN and its drain connected to the inverting output node NOUT. 【0027】 The first inverter 21 has its input connected to the inverting output node NOUT, and its output connected to the gate of the third N-type transistor N3. Although not shown, the first inverter 21 has a circuit configuration similar to the second inverter 22 in Figure 1, for example, a P-type transistor and an N-type transistor are connected in series between the third power supply VDDIO and the ground VSS. In the following description, the output signal of the first inverter 21 will be referred to as S1. 【0028】 The fourth N-type transistor, N4, has its source connected to the input node IN and its drain connected to the output node OUT. 【0029】 The second inverter 22 has its input connected to the output node OUT, and its output connected to the gate of the fourth N-type transistor N4. For example, in the second inverter 22, a P-type transistor P11 (high-potential switching element) and an N-type transistor N11 (low-potential switching element) are connected in series between the third power supply VDDIO and the ground VSS. In the following description, the output signal of the second inverter 22 will be referred to as S2. 【0030】 -Level shift circuit operation- Next, the operation of the level shift circuit 1 will be explained. 【0031】 <Operation when the input signal IN transitions from L to H> Here, referring to Figure 2A, the operation of the level shift circuit 1 when the input signal IN transitions from L to H will be explained. 【0032】 As shown in Figure 2A, in the initial state (time T0), the input signal XIN = L, the input signal IN = L, and the inverting input signal NIN = H. The second N-type transistor N2 is turned on and the second P-type transistor P2 is turned off, so the output signal OUT = L. The output signal S2 of the second inverter 22 is H, and the fourth N-type transistor N4 is in the ON state. 【0033】 Furthermore, the first N-type transistor N1 is turned off and the first P-type transistor P1 is turned on, so the inverted output signal NOUT = H. The output signal S1 of the first inverter 21 is L, and the third N-type transistor N3 is in the off state. 【0034】 At time T1, when the input signal XIN rises, the inverted input signal NIN changes from high to low, and the input signal IN changes from low to high. 【0035】 When the inverting input signal NIN becomes low, the second N-type transistor N2 turns off. In the initial state, the fourth N-type transistor N4 is on, so as the input signal IN rises from low to high, charge is supplied from the first power supply VDD to the output node OUT via the fourth N-type transistor N4. This charge supply assists the rise of the output signal OUT, thereby speeding up the rise of the output signal OUT. 【0036】 Furthermore, when the input signal IN becomes high, the first N-type transistor N1 turns on, and the inverting output signal NOUT begins to fall. When the inverting output signal NOUT falls, the second P-type transistor P2 turns on, and the supply of charge from the third power supply VDDIO to the output node OUT begins. 【0037】 As mentioned above, the second inverter 22 is a circuit that operates with the third power supply VDDIO, so when the voltage of the output signal OUT rises to a threshold value based on the third power supply, the output signal S2 changes from H to L. In other words, the second inverter 22 changes from H to L after a predetermined delay time has elapsed. When this happens, the fourth N-type transistor N4 is turned off, and the assist operation by the rise assist circuit 2 ends. 【0038】 Since the second P-type transistor P2 is turned on, the output signal OUT eventually rises up to the third power supply VDDIO. 【0039】 Thus, in this embodiment, the end time of the assist operation can be extended according to the delay time of the second inverter 22. Specifically, in the example of Figure 2A, the assist operation of the rise assist circuit 2 continues until the output signal OUT is near the first power supply VDD. The inverter 82 is a circuit that operates with the first power supply VDD, and in the example of Figure 2A, the assist operation can be realized up to the vicinity of that power supply voltage. In other words, the effectiveness of the assist operation can be further enhanced. 【0040】 Furthermore, when the inverting output signal NOUT falls and the output signal S1 of the first inverter 21 becomes high, the third N-type transistor N3 turns on. However, both the inverting input signal NIN and the inverting output signal NOUT are low. In other words, both the source and drain of the third N-type transistor N3 are low. Therefore, even if the third N-type transistor N3 is turned on, it does not affect the operation of the other circuits. 【0041】 <Operation when the input signal IN transitions from H to L> Here, referring to Figure 2B, the operation of the level shift circuit 1 when the input signal IN transitions from H to L will be explained. 【0042】 As shown in Figure 2B, in the initial state (time T0), the input signal XIN = H, or in other words, the input signal IN = H and the inverting input signal NIN = L. The second N-type transistor N2 is turned off and the second P-type transistor P2 is turned on, so the output signal OUT = H. The output signal S2 of the second inverter 22 is L, and the fourth N-type transistor N4 is in the off state. 【0043】 Furthermore, the first N-type transistor N1 is turned on and the first P-type transistor P1 is turned off, so the inverted output signal NOUT = L. The output signal S1 of the first inverter 21 is H, and the third N-type transistor N3 is in the ON state. 【0044】 At time T1, when the input signal XIN falls, the inverted input signal NIN changes from low to high, and the input signal IN changes from high to low. 【0045】 When the input signal IN becomes low, the first N-type transistor N1 turns off. In the initial state, the third N-type transistor N3 is on, so as the inverting input signal NIN rises from low to high, charge is supplied from the first power supply VDD to the inverting output node NOUT via the third N-type transistor N3. This charge supply assists the rising edge of the inverting output signal NOUT, thereby speeding up the rising edge of the inverting output signal NOUT. 【0046】 Furthermore, when the inverting input signal NIN becomes high, the second N-type transistor N2 turns on, and the output signal OUT begins to fall. When the output signal OUT falls, the first P-type transistor P1 turns on, and the supply of charge from the third power supply VDDIO to the inverting output node NOUT begins. 【0047】 As described above, the first inverter 21 is a circuit that operates with the third power supply VDDIO, so when the voltage of the inverted output signal NOUT rises to a threshold valued from the third power supply VDDIO, the output signal S1 changes from H to L. That is, the first inverter 21 changes from H to L after a predetermined delay time has elapsed. When this happens, the third N-type transistor N3 is turned off, and the assist operation by the rise assist circuit 2 ends. In this way, in this embodiment, the end time of the assist operation can be extended according to the delay time of the first inverter 21. As a result, for example, in the example of Figure 2B, the assist operation is performed until the inverted output signal NOUT is near the first power supply VDD. Since the inverter 81 is a circuit that operates with the first power supply VDD, the assist operation can be realized up to near its power supply voltage. In other words, the effectiveness of the assist operation can be further increased. 【0048】 Since the first P-type transistor P1 is turned on, the inverted output signal NOUT eventually rises up to the third power supply VDDIO. 【0049】 Furthermore, when the output signal OUT falls and the output signal S2 of the second inverter 22 becomes high, the fourth N-type transistor N4 turns on. However, both the input signal IN and the output signal OUT are low. In other words, both the source and drain of the fourth N-type transistor N4 are low. Therefore, even if the fourth N-type transistor N4 is turned on, it does not affect the operation of the other circuits. 【0050】 -Effects of the First Embodiment- As mentioned above, in the prior art described in Patent Document 1 (hereinafter simply referred to as "prior art"), the assist operation is interrupted at a relatively early stage of the rising edge of the output signal due to changes in the output signal of the level shift circuit, so there was room for improvement (see Figure 6). 【0051】 In contrast, in the level shift circuit 1 of the first embodiment, even if the output state of the output signal OUT changes, the rise assist circuit 2 stops after a further delay time of the second inverter 22 has elapsed. The same applies to the output signal NOUT. As a result, sufficient assist operation can be obtained compared to the conventional technology. 【0052】 Furthermore, as mentioned above, in the conventional technology, there was a problem in that transistors 41 and 42 could be turned off simultaneously, causing the intermediate node between the two transistors to be boosted. 【0053】 In contrast, in this embodiment, unlike the conventional technology, there is no point in the process of assisting the output signal where transistors on both sides of a particular node simultaneously turn off and enter a floating state, so the problem of boosting the voltage at a particular node does not arise. More specifically, in this embodiment, the fourth N-type transistor N4 corresponds to the transistor 42 of the conventional technology, and the input node IN corresponds to the intermediate node between the transistors 41 and 42 of the conventional technology. The P-type transistor of the inverter 82 (not shown) corresponds to the transistor 41 of the conventional technology. In this embodiment, the N-type transistor of the inverter 82 is also connected to the input node IN that connects the fourth N-type transistor N4 and the P-type transistor of the inverter 82. Due to the action of this N-type transistor, the input node IN is not boosted by the transition of the input signal as in the conventional technology, thus solving the problems of the conventional technology. 【0054】 (modified version) Figures 3A and 3B show modified examples of the level shift circuit 1 according to the first embodiment. In Figures 3A and 3B, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment. The basic operation is the same as that of the first embodiment described above. 【0055】 In this modified example, the circuit configurations of the first inverter 21 and the second inverter 22 differ from those in the configuration shown in Figure 1. While Figures 3A and 3B show the circuit configuration of the second inverter 22, the same circuit configuration is used for the first inverter 21. 【0056】 Specifically, in the second inverter 22 of the level shift circuit 1 shown in Figures 3A and 3B, the switching element on the low-potential side is configured with two N-type transistors N12 and N13 connected in series between node S2 and ground VSS. In other words, the second inverter 22 has a configuration in which a P-type transistor P11 and two N-type transistors N12 and N13 are connected in series between the third power supply VDDIO and ground VSS. The same applies to the first inverter 21, where the switching element on the low-potential side is configured with two N-type transistors N12 and N13 connected in series between node S1 and ground VSS. 【0057】 In Figure 3A, in the second inverter 22, the gates of both N-type transistors N12 and N13 are connected to the output node OUT. The drain of N-type transistor N12 is connected to node S2, and the source is connected to the drain of N-type transistor N13. The source of N-type transistor N13 is connected to ground VSS. 【0058】 Similarly, in the first inverter 21 in Figure 3A, the gates of both N-type transistors N12 and N13 are connected to the inverting output node NOUT. The drain of N-type transistor N12 is connected to node S1, and the source is connected to the drain of N-type transistor N13. The source of N-type transistor N13 is connected to ground VSS. 【0059】 In Figure 3B, the only difference from Figure 3A is that the gate of the N-type transistor N12 is connected to the third power supply VDDIO. The other configurations are the same as in Figure 3A. In other words, the switching element on the low-potential side of the second inverter 22 in Figure 3B is a configuration in which the N-type transistor N12 (corresponding to the seventh N-type transistor), whose gate is connected to the third power supply VDDIO, and the N-type transistor N13 (corresponding to the eighth N-type transistor), whose gate is connected to the output node OUT, are connected in series. Similarly, the switching element on the low-potential side of the first inverter 21 is a configuration in which the N-type transistor N12 (corresponding to the fifth N-type transistor), whose gate is connected to the third power supply VDDIO, and the N-type transistor N13 (corresponding to the sixth N-type transistor), whose gate is connected to the inverting output node NOUT, are connected in series. 【0060】 In this modified example (Figures 3A and 3B), the high-potential switching element of the second inverter 22 is a P-type transistor P11, similar to Figure 1, with its gate connected to the output node OUT, its source connected to the third power supply VDDIO, and its drain connected to node S2. Similarly, the high-potential switching element of the first inverter 21 is a P-type transistor P11, with its gate connected to the inverting output node NOUT, its source connected to the third power supply VDDIO, and its drain connected to node S1. 【0061】 By adopting a configuration like this modified example, the voltage stress applied between the source and drain of a single transistor in the switching elements on the low-potential side of the first inverter 21 and the second inverter 22 can be reduced. 【0062】 A specific example will be explained following the "operation when the input signal IN transitions from L to H" described above. When the input signal IN rises from the initial state (time T0), IN=L, to IN=H, the voltage at node S2 rises due to the gate-source coupling capacitance of the fourth N-type transistor N4. This may cause an overvoltage to be applied between node S2 and ground VSS (for example, between the source and drain of the low-potential switching element constituting the second inverter 22). Similarly, in the "operation when the input signal IN transitions from H to L" described above, when the input signal IN falls from the initial state (time T0), IN=H, to IN=L, the voltage at node S1 rises due to the gate-source coupling capacitance of the third N-type transistor N3. This may cause an overvoltage to be applied between node S1 and ground VSS (for example, between the source and drain of the low-potential switching element constituting the first inverter 21). 【0063】 Therefore, as shown in this modified example, by using a configuration in which two N-type transistors are connected in series for the switching element on the low-potential side, the voltage stress on each N-type transistor can be reduced. In other words, degradation of the N-type transistors due to overvoltage can be prevented. 【0064】 Furthermore, in the configurations of Figures 1, 3A, and 3B, the source of the first N-type transistor N1 may be connected to the inverting input node NIN, and the source of the second N-type transistor N2 may be connected to the input node IN. Figure 7 shows a modified example of the configuration in Figure 1. In this case as well, the operation is substantially the same as the first embodiment and its modified examples described above, and similar effects can be obtained. 【0065】 Here, we will explain the operation in Figure 7 when the input signal IN transitions from L to H, focusing on the differences from the configuration in Figure 1. 【0066】 First, in the configuration shown in Figure 7, in the initial state, the inverting input signal NIN is high, so the source of the first N-type transistor N1 is high, which is different from the case in Figure 1. However, since the first N-type transistor N1 is turned off at this time, there is no substantial difference in operation between Figure 1 and Figure 7. 【0067】 Next, in Figure 7, when the input signal XIN rises, the input signal IN changes from L to H, and the source of the second N-type transistor N2 becomes H, which is different from the case in Figure 1. However, at this time the second N-type transistor N2 is turned off, so there is no substantial difference from the operation in the above embodiment. 【0068】 Other than the above, the operation is the same as in the previously described embodiment. That is, although there are some differences in the connections between Figure 1 and Figure 7, there is no substantial difference in operation. 【0069】 The same applies to the operation when the input signal IN transitions from H to L, and to the modified examples shown in Figures 3A and 3B above, when the same modifications as in Figure 7 are applied. 【0070】 <Second Embodiment> Figure 4 shows an example of a circuit diagram of the level shift circuit 1 according to the second embodiment. In Figure 4, components corresponding to those in Figure 1 are denoted by the same reference numerals. The following description will focus on the differences from the first embodiment. It should be noted that there is no intention to limit the various design parameters / process parameters, etc., of components (e.g., transistors and inverters) that are denoted by the same reference numerals in Figure 1 and Figure 4 to being identical. In other words, the technical scope of this disclosure includes configurations in which the various parameters of components denoted by the same reference numerals in Figure 1 and Figure 4 differ between Figure 1 and Figure 4. The same applies to the relationships between other drawings. 【0071】 The configuration in Figure 4 differs from that in Figure 1 in that the gates of the first N-type transistor N1 and the second N-type transistor N2 are connected to the first power supply VDD. Furthermore, the configuration in Figure 4 differs from that in Figure 1 in that the source of the first N-type transistor N1 is connected to the inverting input node NIN, and the source of the second N-type transistor N2 is connected to the input node IN. 【0072】 -Level shift circuit operation- Next, the operation of the level shift circuit 1 of this embodiment will be described. 【0073】 <Operation when the input signal IN transitions from L to H> This section describes the operation of the level shift circuit 1 when the input signal IN transitions from L to H. The signal waveforms are the same as in Figure 2A. 【0074】 In the initial state (time T0), the input signal XIN = L, the input signal IN = L, and the inverting input signal NIN = H. Since VDD is applied to the gates of the first N-type transistor N1 and the second N-type transistor N2, the inverting output signal NOUT = H and the output signal OUT = L. Consequently, the output signal S1 of the first inverter 21 is L, and the third N-type transistor N3 is in the off state. Also, the output signal S2 of the second inverter 22 is H, and the fourth N-type transistor N4 is in the on state. 【0075】 At time T1, when the input signal XIN rises, the input signal IN begins to rise from L to H. The gate-source voltage of the second N-type transistor N2 is VDD in its initial state. Therefore, during the rise of the input signal IN, charge is supplied from the first power supply VDD to the output node OUT via the second N-type transistor N2 until the output signal OUT = VDD - Vt (where Vt is the threshold voltage of N2). Furthermore, since the fourth N-type transistor N4 is turned on, charge is supplied from the first power supply VDD to the output node OUT via the fourth N-type transistor N4. This charge supply via the second N-type transistor N2 and the fourth N-type transistor N4 assists the rise of the output signal OUT, thereby speeding up its rise. 【0076】 Furthermore, when the inverting input signal NIN becomes low, the inverting output signal NOUT begins to fall via the first N-type transistor N1. When the inverting output signal NOUT falls, the second P-type transistor P2 is turned on, and the supply of charge from the third power supply VDDIO to the output node OUT begins. 【0077】 Since the second inverter 22 is a circuit that operates with the third power supply VDDIO, when the voltage of the output signal OUT rises to a predetermined threshold referenced to the third power supply VDDIO, the output signal S2 changes from H to L. That is, the second inverter 22 changes from H to L after a predetermined delay time has elapsed. When this happens, the fourth N-type transistor N4 is turned off, and the assist operation by the rise assist circuit 2 ends. 【0078】 Since the second P-type transistor P2 is turned on, the output signal OUT eventually rises up to the third power supply VDDIO. 【0079】 Thus, in this embodiment, similar to the first embodiment, the end time of the assist operation can be extended according to the delay time of the inverter 22. 【0080】 Furthermore, when the inverting output signal NOUT falls and the output signal S1 of the first inverter 21 becomes high, the third N-type transistor N3 turns on, but both the inverting input signal NIN and the inverting output signal NOUT are low. In other words, both the source and drain of the third N-type transistor N3 are low. Therefore, even if the third N-type transistor N3 is turned on, it does not affect the operation of other circuits. 【0081】 <Operation when the input signal IN transitions from H to L> This section describes the operation of the level shift circuit 1 when the input signal IN transitions from high to low. The signal waveforms are the same as in Figure 2B. 【0082】 In the initial state (time T0), the input signal XIN = H, the input signal IN = H, and the inverting input signal NIN = L. Since VDD is applied to the gates of the first N-type transistor N1 and the second N-type transistor N2, the inverting output signal NOUT = L and the output signal OUT = H. Consequently, the output signal S1 of the first inverter 21 is H, and the third N-type transistor N3 is ON. Also, the output signal S2 of the second inverter 22 is L, and the fourth N-type transistor N4 is OFF. 【0083】 At time T1, as the input signal XIN falls, the inverting input signal NIN begins to rise from L to H. The gate-source voltage of the first N-type transistor N1 is VDD in its initial state. Therefore, during the rising process of the inverting input signal NIN, charge is supplied from the first power supply VDD to the inverting output node NOUT via the first N-type transistor N1 until the inverting output signal NOUT = VDD - Vt (where Vt is the threshold voltage of N1). Furthermore, since the third N-type transistor N3 is turned on, charge is supplied from the first power supply VDD to the inverting output node NOUT via the third N-type transistor N3. This charge supply via the first N-type transistor N1 and the third N-type transistor N3 assists the rising of the inverting output signal NOUT, thereby speeding up its rise. 【0084】 Furthermore, when the input signal IN becomes low, the output signal OUT begins to fall via the second N-type transistor N2. When the output signal OUT falls, the first P-type transistor P1 is turned on, and the supply of charge from the third power supply VDDIO to the inverting output node NOUT begins. 【0085】 Since the first inverter 21 is a circuit that operates with the third power supply VDDIO, when the voltage of the inverting output signal NOUT rises to a predetermined threshold referenced to the third power supply VDDIO, the output signal S1 changes from H to L. That is, the first inverter 21 changes from H to L after a predetermined delay time has elapsed. When this happens, the third N-type transistor N3 is turned off, and the assist operation by the rise assist circuit 2 ends. 【0086】 Since the first P-type transistor P1 is turned on, the inverted output signal NOUT eventually rises up to the third power supply VDDIO. 【0087】 Thus, in this embodiment, similar to the first embodiment, the end time of the assist operation can be extended according to the delay time of the inverters 21 and 22. 【0088】 Furthermore, when the output signal OUT falls and the output signal S2 of the second inverter 22 becomes high, the fourth N-type transistor N4 turns on. However, both the input signal IN and the output signal OUT are low. In other words, both the source and drain of the fourth N-type transistor N4 are low. Therefore, even if the fourth N-type transistor N4 is turned on, it does not affect the operation of the other circuits. 【0089】 -Effects of the second embodiment- As described above, in the level shift circuit 1 of the second embodiment, similar to the first embodiment, even if the output state of the output signal OUT changes, the rise assist circuit 2 stops after a further delay time of the second inverter 22 has elapsed. The same applies to the output inversion signal NOUT. As a result, sufficient assist operation can be obtained compared to the conventional technology. Also, similar to the first embodiment, there are no points in the process of assist operation where transistors on both sides of a particular node turn off simultaneously and become floating, so no problems arise regarding the boost of a particular node. 【0090】 Furthermore, in this embodiment, the gates of the first and second N-type transistors N1 and N2 are connected to the first power supply VDD, the source of the first N-type transistor N1 is connected to the inverting input node NIN, and the source of the second N-type transistor N2 is connected to the input node IN. This makes it possible to reduce the voltage across the source / drain / gate of each of the first and second N-type transistors N1 and N2 compared to the first embodiment. Specifically, in the first embodiment, for example, the gate voltage of the first N-type transistor N1 may be VSS, the source voltage may be VSS, and the drain voltage may be VDDIO. In this case, the source-drain voltage is VDDIO. In contrast, in the second embodiment, when the drain voltage of the first N-type transistor N1 or the second N-type transistor N2 is VDDIO, the gate voltage and source voltage are VDD. In this case, the source-drain voltage becomes VDDIO-VDD, which is smaller compared to the first embodiment. As a result, in this embodiment, a transistor with a low breakdown voltage but high speed can be used as the first N-type transistor N1, making it possible to speed up the operation of the circuit compared to the first embodiment. 【0091】 (Variation 1) Figure 5 shows a modified example of the level shift circuit 1 according to the second embodiment. In Figure 5, components corresponding to those in Figure 4 are denoted by the same reference numerals. The following description will focus on the differences from the second embodiment. The basic operation is the same as that of the second embodiment described above. 【0092】 In this modified configuration, the differences compared to the configuration in Figure 4 are that a fifth N-type transistor N5 is provided between the inverting output node NOUT and the first N-type transistor N1, and a sixth N-type transistor N6 is provided between the output node OUT and the second N-type transistor N2. 【0093】 Specifically, the gate of the fifth N-type transistor N5 is connected to the third power supply VDDIO, and the source is connected to the drain of the first N-type transistor N1. The drain of the fifth N-type transistor N5 is connected to the inverting output node NOUT, the input of the first inverter 21, and the drain of the third N-type transistor N3. 【0094】 The sixth N-type transistor N6 has its gate connected to the third power supply VDDIO and its source connected to the drain of the second N-type transistor N2. The drain of the sixth N-type transistor N6 is also connected to the output node OUT, the input of the second inverter 22, and the drain of the fourth N-type transistor N4. 【0095】 According to this modified example, the maximum source voltage of the fifth N-type transistor N5, in other words, the maximum drain voltage of the first N-type transistor N1, can be set to VDDIO-Vt (where Vt is the threshold voltage of the fifth N-type transistor N5). The same applies to the drain voltage of the second N-type transistor N2. This reduces the potential difference between the source and drain of the first and second N-type transistors N1 and N2, allowing the use of transistors with lower breakdown voltages for the first and second N-type transistors N1 and N2. 【0096】 The above embodiments and modifications can be combined as appropriate. For example, in the configurations of Figures 4 and 5, the configurations shown in Figure 3A or Figure 3B may be used instead of the configuration in Figure 1 for the first inverter 21 and the second inverter 22, and the same effects as the first embodiment can be obtained in each case. 【0097】 Specifically, in the configurations shown in Figures 4 and 5, the circuit X in Figure 3A may be applied, and the switching element on the low-potential side of the first inverter 21 may be configured as two N-type transistors connected in series, with their gates connected to the inverting output node NOUT. Similarly, the switching element on the low-potential side of the second inverter 22 may be configured as two N-type transistors connected in series, with their gates connected to the output node OUT. 【0098】 Similarly, in the configurations of Figures 4 and 5, the circuit X in Figure 3B may be applied, and the switching element on the low-potential side of the first inverter 21 may be configured by connecting in series an N-type transistor (corresponding to the fifth N-type transistor) whose gate is connected to the third power supply VDDIO and an N-type transistor (corresponding to the sixth N-type transistor) whose gate is connected to the inverting output node NOUT. Furthermore, the switching element on the low-potential side of the second inverter 22 may be configured by connecting in series an N-type transistor (corresponding to the seventh N-type transistor) whose gate is connected to the third power supply VDDIO and an N-type transistor (corresponding to the eighth N-type transistor) whose gate is connected to the output node OUT. 【0099】 (Modification 2) Figure 8 shows another modified example of the level shift circuit 1 according to the second embodiment. In Figure 8, components corresponding to those in Figure 4 are denoted by the same reference numerals. The following description will focus on the differences from the second embodiment. The basic operation is the same as that of the second embodiment described above. 【0100】 Figure 8 includes a power supply detection circuit 4 in addition to the configuration shown in Figure 4. The power supply detection circuit 4 comprises two N-type transistors N41 and N42 and two inverters 43 and 44. 【0101】 N-type transistor N41 is placed between the third power supply VDDIO and node Xp, with its gate connected to the first power supply VDD. N-type transistor N42 has its gate connected to the third power supply VDDIO, its source connected to node Xp, and its drain connected to the first power supply VDD. Two inverters 43 and 44 are connected in series between node Xp and the output of the power supply detection circuit 4. Although not shown in the diagram, the power supply terminals of inverters 43 and 44 are connected to the first power supply VDD, and their ground terminals are connected to ground VSS. 【0102】 In this modified example, the gates of the first N-type transistor N1 and the gates of the second N-type transistor N2 are connected to the output of the power supply detection circuit 4 instead of the first power supply VDD. In other words, the gates of the first N-type transistor N1 and the gates of the second N-type transistor N2 are connected to the first power supply VDD via the power supply detection circuit 4. 【0103】 The power supply detection circuit 4 outputs the first power supply VDD when both the first power supply VDD and the third power supply VDDIO are on, and outputs ground VSS when the first power supply VDD is on and the third power supply VDDIO is off. 【0104】 Specifically, (1) when both the first power supply VDD and the third power supply VDDIO are on, and VDDIO - Vt2 < VDD (where Vt2 is the threshold voltage of the N-type transistor N42), the voltage Xp of the node Xp becomes Xp = VDDIO - Vt2 due to the action of the N-type transistor N42. Similarly, (2) when both the first power supply VDD and the third power supply VDDIO are on, and VDDIO - Vt2 > VDD, the voltage Xp of the node Xp becomes Xp = VDD. In either case of (1) and (2) above, the input of the inverter 43 becomes H, so the output of the inverter 44 also becomes H. That is, the first power supply VDD is applied from the power supply detection circuit 4 to the gates of the first N-type transistor N1 and the second N-type transistor N2. 【0105】 Next, when the first power supply VDD is on and the third power supply VDDIO is off (VDDIO = VSS), the N-type transistor N41 turns on and the N-type transistor N42 turns off, so the voltage Xp of the node Xp becomes Xp = VSS. Then, the input of the inverter 43 becomes L, so the output of the inverter 44 also becomes L. That is, the ground VSS is applied from the power supply detection circuit 4 to the gates of the first N-type transistor N1 and the second N-type transistor N2. 【0106】 With such a configuration, it is possible to prevent a location where a through-current flows from occurring within the level shift circuit 1 regardless of which of the first power supply VDD and the third power supply VDDIO rises first. 【Industrial Applicability】 【0107】 The level shift circuit of the present disclosure is extremely useful because it can enhance the effectiveness of the assist operation and relieve the voltage stress on the transistors in the level shift circuit. 【Explanation of Reference Numerals】 【0108】 1 Level shift circuit 21 First inverter 22 Second Inverter N1 First N-type transistor N2 Second N-type transistor N3 Third N-type transistor N4: The fourth N-type transistor N5: The fifth N-type transistor N6: The sixth N-type transistor P1 First P-type transistor P2 Second P-type transistor IN Input Management NIN Inverting Input Node VDD 1st power supply VSS 2nd power supply VDDIO Third Power Supply
Claims
[Claim 1] An input node that receives an input signal transitioning between a first power supply and a second power supply having a lower potential than the first power supply, An inverting input node that receives an inverted input signal obtained by inverting the aforementioned input signal, A first N-type transistor having its gate connected to the input node, its source connected to the second power supply or the inverting input node, and its drain connected to the inverting output node, A first P-type transistor is provided, with its drain connected to the inverting output node, its source connected to a third power supply with a higher potential than the first power supply, and its gate connected to the output node. A second N-type transistor having its gate connected to the inverting input node, its source connected to the second power supply or the input node, and its drain connected to the output node, A second P-type transistor, whose drain is connected to the output node, whose source is connected to the third power supply, and whose gate is connected to the inverting output node, A third N-type transistor, the source of which is connected to the inverting input node and the drain of which is connected to the inverting output node, A first inverter whose input is connected to the inverting output node and whose output is connected to the gate of the third N-type transistor, A fourth N-type transistor, the source of which is connected to the input node and the drain of which is connected to the output node, A level shift circuit comprising a second inverter whose input is connected to the output node and whose output is connected to the gate of the fourth N-type transistor. [Claim 2] In the level shift circuit described in claim 1, The switching element on the low-potential side of the first inverter has a configuration in which two N-type transistors, whose gates are connected to the inverting output node, are connected in series. The switching element on the low-potential side of the second inverter is a level-shift circuit, which has a configuration of two N-type transistors connected in series, with their gates connected to the output node. [Claim 3] In the level shift circuit described in claim 1, The switching element on the low-potential side of the first inverter has a configuration in which a fifth N-type transistor, whose gate is connected to the third power supply, and a sixth N-type transistor, whose gate is connected to the inverting output node, are connected in series. The switching element on the low-potential side of the second inverter is a level-shift circuit configured by connecting in series a seventh N-type transistor whose gate is connected to the third power supply and an eighth N-type transistor whose gate is connected to the output node. [Claim 4] An input node that receives an input signal transitioning between a first power supply and a second power supply having a lower potential than the first power supply, An inverting input node that receives an inverted input signal obtained by inverting the aforementioned input signal, A first N-type transistor whose source is connected to the inverting input node, whose gate is connected to the first power supply, and whose drain is connected to the inverting output node, A first P-type transistor whose drain is connected to the inverting output node, whose source is connected to a third power supply at a higher potential than the first power supply, and whose gate is connected to the output node, A second N-type transistor, the source of which is connected to the input node, the gate of which is connected to the first power supply, and the drain of which is connected to the output node, A second P-type transistor, whose drain is connected to the output node, whose source is connected to the third power supply, and whose gate is connected to the inverting output node, A third N-type transistor, the source of which is connected to the inverting input node and the drain of which is connected to the inverting output node, A first inverter whose input is connected to the inverting output node and whose output is connected to the gate of the third N-type transistor, A fourth N-type transistor, the source of which is connected to the input node and the drain of which is connected to the output node, A level shift circuit comprising a second inverter whose input is connected to the output node and whose output is connected to the gate of the fourth N-type transistor. [Claim 5] In the level shift circuit described in claim 4, The switching element on the low-potential side of the first inverter has a configuration in which two N-type transistors, whose gates are connected to the inverting output node, are connected in series. The switching element on the low-potential side of the second inverter is a level-shift circuit, which has a configuration of two N-type transistors connected in series, with their gates connected to the output node. [Claim 6] In the level shift circuit described in claim 4, The switching element on the low-potential side of the first inverter has a configuration in which a fifth N-type transistor, whose gate is connected to the third power supply, and a sixth N-type transistor, whose gate is connected to the inverting output node, are connected in series. The switching element on the low-potential side of the second inverter is a level-shift circuit configured by connecting in series a seventh N-type transistor whose gate is connected to the third power supply and an eighth N-type transistor whose gate is connected to the output node. [Claim 7] An input node that receives an input signal transitioning between a first power supply and a second power supply having a lower potential than the first power supply, An inverting input node that receives an inverted input signal obtained by inverting the aforementioned input signal, A first N-type transistor whose source is connected to the inverting input node and whose gate is connected to the first power supply, A first P-type transistor is provided, with its drain connected to an inverting output node, its source connected to a third power supply at a higher potential than the first power supply, and its gate connected to an output node. A second N-type transistor whose source is connected to the input node and whose gate is connected to the first power supply, A second P-type transistor, whose drain is connected to the output node, whose source is connected to the third power supply, and whose gate is connected to the inverting output node, A third N-type transistor, the source of which is connected to the inverting input node and the drain of which is connected to the inverting output node, A first inverter whose input is connected to the inverting output node and whose output is connected to the gate of the third N-type transistor, A fourth N-type transistor, the source of which is connected to the input node and the drain of which is connected to the output node, A second inverter whose input is connected to the output node and whose output is connected to the gate of the fourth N-type transistor, A fifth N-type transistor whose gate is connected to the third power supply, whose source is connected to the drain of the first N-type transistor, and whose drain is connected to the inverting output node, A level shift circuit comprising a sixth N-type transistor whose gate is connected to the third power supply, whose source is connected to the drain of the second N-type transistor, and whose drain is connected to the output node. [Claim 8] In the level shift circuit described in claim 7, The switching element on the low-potential side of the first inverter has a configuration in which two N-type transistors, whose gates are connected to the inverting output node, are connected in series. The switching element on the low-potential side of the second inverter is a level-shift circuit, which has a configuration of two N-type transistors connected in series, with their gates connected to the output node. [Claim 9] In the level shift circuit described in claim 7, The switching element on the low-potential side of the first inverter has a configuration in which a seventh N-type transistor, whose gate is connected to the third power supply, and an eighth N-type transistor, whose gate is connected to the inverting output node, are connected in series. The switching element on the low-potential side of the second inverter is a level-shift circuit configured by connecting in series a ninth N-type transistor whose gate is connected to the third power supply and a tenth N-type transistor whose gate is connected to the output node. [Claim 10] In the level shift circuit described in claim 4, The system further includes a power supply detection circuit that outputs the first power supply when both the first power supply and the third power supply are on, and outputs the second power supply when the first power supply is on and the third power supply is off. A level shift circuit in which the gates of the first N-type transistor and the gate of the second N-type transistor are connected to the first power supply via the power supply detection circuit.