Encoding method and encoder

Abstract

To provide an encoding method and an encoder capable of enhancing reliability and integrity of a key.SOLUTION: An encoding method includes the steps of: receiving, at an encoder, a series of data bits; performing, at the encoder, first transition encoding on the data bits to generate an encoded series of data bits based on a key; performing, at the encoder, protection encoding on the key to generate key protection data; performing, at the encoder, second transition encoding on the key protection data to generate encoded key protection data; and transmitting an encoded series of transmission bits to a receiver, the encoded series of transmission bits including the encoded series of data bits and the encoded key protection data.SELECTED DRAWING: Figure 3

Description

【Technical Field】 【0001】 The present invention relates to an encoding method and an encoder, and more particularly to a transition encoding method and an encoder in which a key is protected. This application claims priority to U.S. Patent Application No. 63 / 227,278, filed with the U.S. Patent and Trademark Office on July 29, 2021, and the entire contents of the application of U.S. Patent Application No. 63 / 227,278 are incorporated herein by reference. 【Background Art】 【0002】 Electronic devices using serial data communication rely on error-free information provided by a transmitter to a receiver. Also, some serial data communication technologies rely on a key that encodes and then decodes serial data. Since the encoding and decoding processes rely on the key, if the encoding and decoding processes are inaccurate or the receiver receives an erroneous key, the error from the key propagates to the data, thereby preventing the serial data from being properly decoded. Therefore, the reliability and integrity of the key are required. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0003】 The problem to be solved by the present invention is to present an encoding method and an encoder capable of enhancing the reliability and integrity of a key. 【Means for Solving the Problems】 【0004】 An encoding method according to one embodiment of the present invention includes the steps of: receiving a data bit sequence with an encoder; generating an encoded data bit sequence by performing a first transition encoding on the data bit sequence based on a key with the encoder; generating key protection data by performing a protection encoding on the key with the encoder; generating encoded key protection data by performing a second transition encoding on the key protection data with the encoder; and transmitting an encoded transmission bit sequence including the encoded data bit sequence and the encoded key protection data to a receiver. 【0005】 The aforementioned key protection data may include a parity bit. 【0006】 The step of generating the encoded key protection data may include the step of determining the inverse of the parity bit. 【0007】 The encoder further includes the steps of selecting a key whose MSB (most significant bit) is a constant value, and generating a modified key by removing the MSB from the key, wherein the encoded transmission bit sequence may include the modified key. 【0008】 The aforementioned constant may be 0. 【0009】 The aforementioned key protection data may include multiple parity bits. 【0010】 The aforementioned parity bits may be calculated using a Hamming code. 【0011】 The step of generating the encoded key protection data may include the step of finding the inverse of at least one of the plurality of parity bits. 【0012】 The encoder further includes the steps of selecting a key whose MSB is a constant value, and removing the MSB from the key to generate a modified key, wherein the encoded transmission bit sequence may include the modified key. 【0013】 The step of generating the encoded key protection data may further include inserting one or more bits that are the inverse of the parity bit into the leading end of the modification key and inserting one or more bits that are the inverse of the parity bit into the trailing end of the modification key. 【0014】 An encoder according to one embodiment of the present invention includes an input for receiving a data bit string, a processor, and an output for transmitting an encoded transmission bit string, wherein the processor generates an encoded data bit string by performing a first transition encoding on the data bit string based on a key, generates key protection data by performing a protection encoding on the key, generates encoded key protection data by performing a second transition encoding on the key protection data, and the encoded transmission bit string includes the encoded data bit string and the encoded key protection data. 【0015】 The aforementioned key protection data may include a parity bit. 【0016】 The operation to generate the encoded key protection data may include an operation to find the inverse of the parity bit. 【0017】 The processor may further select a key in the encoder whose MSB (most significant bit) is a constant value, remove the MSB from the key to generate a modified key, and the encoded transmission bit sequence may include the modified key. 【0018】 The aforementioned constant may be 0. 【0019】 The key protection data may include a plurality of parity bits. 【0020】 The plurality of parity bits may be calculated by a Hamming code. 【0021】 The operation of generating the encoded key protection data may include an operation of obtaining the inverse of at least one of the plurality of parity bits. 【0022】 The processor further selects the key whose MSB becomes a constant value, removes the MSB from the key to generate a modified key, and the encoded transmission bit string may include the modified key. 【0023】 The operation of generating the encoded key protection data may further include an operation of inserting one or more bits of the inverse of the parity bit at the front of the modified key and inserting one or more bits of the inverse of the parity bit at the end of the modified key. 【0024】 The scope of the present invention is defined by the scope of the claims included in this part by reference herein and their equivalents. By considering the following detailed description of each embodiment of the present invention, those skilled in the art will further understand the embodiments and be able to obtain further advantages. First, the drawings will be described and then they will be cited. 【Effects of the Invention】 【0025】 By using the encoding method and encoder according to an embodiment of the present invention, the reliability and integrity of the key can be enhanced. 【Brief Description of the Drawings】 【0026】 [Figure 1] An example of a data bit string according to an embodiment of the present invention shows transitions in the data. [Figure 2]A table showing an example of a codeword according to an embodiment of the present invention. [Figure 3] A flowchart showing the step of encoding a data bit string according to an embodiment of the present invention. [Figure 4] A flowchart showing the step of encoding key protection data according to an embodiment of the present invention. [Figure 5] A block diagram of an electronic system according to an embodiment of the present invention. 【Best Mode for Carrying Out the Invention】 【0027】 The embodiments and advantages of the present invention can be understood by referring to the detailed description given hereinafter. Throughout the drawings and the entire specification of the embodiments of the present invention, unless otherwise specifically noted, the same reference numerals denote the same components, and redundant descriptions may be omitted. In the drawings, for the sake of clear understanding, the sizes of components, layers, and regions may be exaggerated. 【0028】 By referring to the detailed description and the drawings regarding the embodiments of the present invention, the features of each embodiment and the method of realizing the same can be further understood. Hereinafter, each embodiment of the present invention will be described in detail with reference to the drawings. However, each embodiment to be described can also be realized in various other forms and is not limited to each embodiment shown in the drawings. Each embodiment is illustrated in order to make the present invention clearer and to fully show the features of the present invention to those skilled in the art. Therefore, descriptions of processes, elements, techniques, etc. that can be omitted are omitted in order for those skilled in the art to clearly understand the features of the present invention. 【0029】 In digital communication, an encoder encodes data bits (e.g., data packets) and transmits the encoded data bits to a decoder. The decoder decodes the encoded data bits. As a result, a system, such as a television, display device, or computer, can use the data bits. For example, according to one technique, the encoded data bits can be serialized and transmitted from the encoder to the decoder via a serial digital data link. Such serial digital data may be transmitted with a separate clock signal, or (without a separate clock signal) with a clock signal inherent in the serial digital data signal. 【0030】 Transition encoding is a method of transmitting serial digital data signals without a separate clock signal. Transition encoding relies on the presence of data transitions within a data bit sequence, where data bits transition or change from 0 to 1, or from 1 to 0. In other words, for a decoder to properly use the received data, a certain number of transitions must occur within the data bit sequence. However, if the run-length within the data sequence exceeds a certain limit, the decoder will be unable to accurately decode the data. As a result, the system will have difficulty retaining the data that was originally intended to be received. Run-length indicates the number of consecutive 1s or 0s in the data bit sequence. For example, in the data bit sequence example 10100111001 shown in Figure 1, the run-length between each transition is represented by 1, 2, or 3. For example, a scenario in which 1 appears three times consecutively has a run-length of 3. 【0031】 Some transition encoding techniques include a key [e.g., a scrambling key] used to maintain the integrity of the encoded data bit sequence when encoding data bits as data is transmitted over a serial data link. In this case, the encoder generates a key, applies transition encoding to the data bits based on the key, adds the key to the encoded data bit sequence to generate a transmission bit sequence, and transmits it to the receiver. When the decoder receives the encoded transmission bits, it decodes the received transmission bits using the key. If the key is damaged during transmission, the decoder may have difficulty decoding the transmitted data bits, and error propagation may occur. That is, an error in the key may be transferred to an error in the overall data, rendering the entire data sequence unusable. Therefore, embodiments of the present invention present a method for improving the transmission reliability of the key. It is also preferable to protect the key without changing the transition characteristics of the encoded sequence (e.g., without exceeding the run length limit of the encoding). 【0032】 In one example of a transition encoding method, a set of 31 6-bit data words is encoded, and the key is also 6 bits. Therefore, according to this example, the transmitted bit sequence contains 192 bits, of which 186 bits are data and 6 bits are the key. The 6-bit key can be represented by D, which is a word that is not only different from the 31 original data words but also different from the complements of the 31 original data words. In this way, the value of D can be selected, and an exclusive OR ("XOR") operation can be applied to D and each of the 31 words. For example, if each of the 186 data bits is represented as x1, x2, ..., x31, and the result of applying the XOR operation to each word x1, x2, ..., x31 and key D can be represented as x1^D, x2^D, ..., x31^D. Therefore, when transition encoding is performed on the data word sequence {x1, x2, ..., x31}, the encoded data word becomes {D, x1^D, x2^D, ..., x31^D}. Here, the first data word is key D, followed by 31 data words that are XORed with key D. Thus, the transmitted data stream sequence becomes 32 words long, 192 bits are serialized and transmitted over the serial data link. According to this example of a transition encoding method, the run length is limited to 10. Note that a detailed explanation of how the run length of such a transition encoding method is determined is omitted in the descriptions of each embodiment of the present invention. 【0033】 When the decoder receives the transmitted data stream, it takes key D and applies an XOR operation to each encoded word (i.e., each of the 31 words). Therefore, by XORing D with the first encoded word x1^D, D is removed, leaving only the first word x1. The same XOR operation is applied to all 31 encoded words to decode all 31 words. At this time, if an error enters key D, that error propagates to all 31 words because the decoder performs the XOR operation using the erroneous (i.e., inaccurate) key D. 【0034】 A method for protecting the integrity of key D will be described using various embodiments of the present invention. In other words, if an error occurs in key D (for example, during transmission), an error detection and / or error correction method and technique are implemented and applied to key D by the encoder so that the decoder can detect the error in key D and not apply this faulty key D to decoding the data stream. Alternatively, the decoder can wait, for example, for another key D that does not contain the error to arrive. In other embodiments of the present invention, the decoder can not only detect the presence of an error but also correct it. As a result, the decoder can correct the faulty key and use the corrected key immediately without having to discard key D or wait for the next key. The key integrity protection techniques described herein are applicable to various encoding and / or decoding techniques known to those skilled in the art. Such encoding and / or decoding techniques may include using different logical operations, different word sizes, different word counts, etc. 【0035】 Generally, encoded data includes a parity bit to help detect the presence of errors. One example is to generate an even parity bit and include it in the encoded data. For example, if there are n bits d1 to dn, an even parity bit p can be generated or calculated by performing an XOR operation on bits d1 to dn in a given word (e.g., a 6-bit key) or block. Therefore, the even parity bit p of d1 to dn is JPEG0007873599000001.jpg571 It can be represented as and an encoded block containing an even parity bit p may be represented as {d1,d2,d3,...,dn,p}. Therefore, the dependency between the data bits and the parity bits is JPEG0007873599000002.jpg584 It can also be expressed as follows. In other words, in the case of an even parity bit, if the dependent representation is 0, it is expected that data bits d1 to dn do not contain errors. Conversely, if the dependent representation is 1, it is possible that one of the data bits d1 to dn contains an error. 【0036】 More complex block codes can be created by including multiple parity bits. For example, a Hamming code such as (7,4) Hamming code can be used. In (7,4) Hamming code, three parity bits are implemented in a single encoded data bit block. In this case, parity bits p1, p2, and p3 are generated as follows: The dependency between the parity bit and the data bit in JPEG0007873599000003.jpg2861 may also be expressed as follows: JPEG0007873599000004.jpg2870 【0037】 Another example of a parity bit is the odd parity bit. For an odd parity bit pb, applying an XOR operation to the data bit and the odd parity bit results in 1, which is It can also be represented as JPEG0007873599000005.jpg598. Therefore, the odd parity bits pb are JPEG0007873599000006.jpg6117 It is generated as follows: In other words, the odd parity bit is the inverse of the result of applying an XOR operation to all data bits. 【0038】 In transition encoding, odd parity bits have several useful properties. For example, if a block consists of an odd number of bits, that is, if n is odd, then a transition is guaranteed in that data block. That is, if d1=0, d2=0, d3=0, d4=0, d5=0, JPEG0007873599000007.jpg12142 Therefore, if we insert an odd parity bit at the end of the code, the block code is 000001, which contains a transition. Similarly, if d1=1, d2=1, d3=1, d4=1, d5=1, JPEG0007873599000008.jpg12143 Therefore, the block code is 111110, which includes a transition. Thus, in the worst-case scenario where bits d1~dn (where n is odd) are all 0 or all 1, the run length is limited to n, and the transition is guaranteed by including an odd parity bit. 【0039】 Returning to the transition encoding scheme using a set of 31 6-bit data words and one 6-bit key, the concept of using an odd parity bit can be applied to key D to detect errors, and in some embodiments, errors can be detected and corrected. In this example, key D contains 6 bits, and the MSB (most significant bit) (i.e., the 6th bit) of the key D value is always 0. Therefore, according to one embodiment of the present invention, the 6th bit of key D may be removed and replaced with an odd parity bit of 0. For example, the decoder knows that the MSB of the key D value is always 0. Therefore, when the decoder receives the encoded key D, even if the actual value of the MSB (i.e., 0) is replaced with an odd parity bit, the decoder removes the parity bit from the MSB during the decoding process and replaces it with 0. 【0040】 Thus, by removing the parity bit from the MSB of key D and replacing it with an odd parity bit, the encoded key D now contains 5 bits corresponding to the key data and 1 bit for the odd parity bit (i.e., the 6th bit). For example, key D may be represented as D=d1, d2, d3, d4, d5, pb, where pb corresponds to the odd parity bit. JPEG0007873599000009.jpg6117 Therefore, the relationship between odd parity bits and 5 data bits is: JPEG0007873599000010.jpg598 Therefore, if there is an error in any one of the data bits of key D, the dependency of odd parity is no longer maintained, and it becomes clear that there is an error in one of the data bits d1, d2, d3, d4, or d5. 【0041】 Furthermore, the run length is limited to 5, because, as explained earlier, in the worst-case scenario where all data bits d1 to d5 are 1, the odd parity bits become 0, or if all data bits d1 to d5 are 0, the odd parity bits become 1. This ensures that the run length does not exceed 5, which is within the limit of 10 run lengths as previously noted in the transition encoding method of this embodiment. However, in this embodiment, while the presence of an error can be detected by the execution of one odd parity bit, the specific location of the error cannot be determined. The embodiments described above are merely examples of embodiments and are not limited to them. Therefore, the same or similar techniques can be applied to other schemes where the word has a different number of bits, a different run length limit, and so on. For example, according to another embodiment, the word may be 8 bits and the run length limit may be 9. 【0042】 According to other embodiments of the present invention, multiple parity bits can be included with key D to further improve the integrity of the key. For example, compared to the previous example where key D contains 6 bits and the MSB is always 0, the new key D becomes 9 bits if the 6th bit is dropped and 4 odd parity bits are included, where 5 bits are data bits and 4 bits are parity bits. In some embodiments, 4 odd data bits are generated and inserted into the block. For example, 4 odd data bits are generated as follows: JPEG0007873599000011.jpg4093 【0043】 By generating and including these four parity bits, if there is an error in one of the data bits, the dependency of the parity bits is no longer maintained, thus revealing the presence of an error. Furthermore, because there are four parity bits that depend on whether the dependency equation is maintained further, the system can determine which of the five data bits has an error and correct the bad bit. For example, if there is an error in d1, the dependency equation including pb1 and pb2 becomes invalid. If there is an error in d2, the dependency equation including pb1 and pb3 becomes invalid. If there is an error in d3, the dependency equation including pb1, pb2, pb3 and pb4 becomes invalid. If there is an error in d4, the dependency equation including pb2 and pb4 becomes invalid. If there is an error in D5, the dependency equation including pb3 and pb4 becomes invalid. In this way, since the bits are binary bits, and a bad bit becomes 1 if it is 0 and becomes 0 again if it is 1, the system can accurately find and correct the bad bit. In one embodiment, if there are two errors in a data bit, the system can detect the error, but it cannot accurately identify and correct the bad bit. It simply detects the error. 【0044】 According to one embodiment of the present invention, a 9-bit key is arranged such that the first 2 bits and the last 2 bits are parity bits, and the middle 5 bits are data bits. Thus, a key containing an odd number of parity bits may be represented as pb1, pb2, d1, d2, d3, d4, d5, pb3, pb4. By arranging the data bits and parity bits in this manner, the run length can be limited to 5, and transitions within key D can be guaranteed. Figure 2 is a table showing all combinations of data bits for key D. Since there are 5 data bits, 32 combinations are possible. Among the shaded boxes in Figure 2, the run length limit is 5 when all data bits are 0 and when all data bits are 1. Thus, the run length limit satisfies the run length limit 10 of the example transition encoding techniques described herein, thereby reducing the possibility of errors and error propagation in the serial data link. 【0045】 Figure 3 is a flowchart showing the steps for encoding a data bit sequence according to one embodiment of the present invention. According to one embodiment of the present invention, the encoder receives a data bit sequence to be encoded and transmitted to a receiver (302). In one embodiment, the data may be a data packet, and in another embodiment, the data may be serial data with an embedded clock signal. The data bit sequence received by the encoder is encoded by performing a first transition encoding on the data bits, which generates an encoded data bit sequence based on a key (304). According to one embodiment, the value of the key is used with the data bits in an XOR operation to generate the encoded data bit sequence. Therefore, when decoding the data bits, the decoder performs the decoding operation depending on the key. Thus, the key is important, and for example, the integrity of the key must be protected so that errors are not introduced into the key during transmission. Also, if the key has an error, it is preferable to detect the presence of the error, and in some cases, it is preferable to correct the error. In this way, the encoder can perform a protective encoding on the key to generate key-protected data (306). 【0046】 According to one embodiment of the present invention, the key protection data is a parity bit. For example, an odd parity bit can be generated by performing an XOR operation on each bit of the key and taking the inverse of the result. Therefore, if the key contains bits d1, d2, ... dn, then the odd parity bit (pb) is JPEG0007873599000012.jpg694 It can also be represented as follows. 【0047】 After generating odd parity bits, the encoder can perform a second transition encoding on the key protection data (e.g., odd parity bits) to generate encoded key protection data (308). According to one embodiment of the present invention, the encoded key protection data may be represented by key bits to which the key protection data has been added. In other words, if the key protection data is odd parity data pb, the key may consist of an odd number of bits d1, d2, ... dn (where n is odd), and the encoded key protection data may be represented by d1, d2, ... dn, pb. According to another embodiment of the present invention, which calculates parity bits using Hamming code, the encoded key protection data may be represented, for example, by d1, d2, ... dn, p1, p2, p3. After generating the encoded key protection data, the encoded data bit sequence and the encoded key protection data are combined with the encoded transmission bit sequence and transmitted to the receiver (310). The transmitter and receiver can be connected via a serial data link, and the encoded transmission bit sequence is transmitted from the transmitter to the receiver via the serial data link. According to one embodiment of the present invention, the receiver may include a decoder that receives the encoded transmission bit sequence and decodes it using a key. To reduce error propagation, key integrity can be ensured by using embedded key protection data (e.g., odd parity bits) to accompany the key value to an odd parity bit. 【0048】 Figure 4 is a flowchart showing the steps for encoding key protection data according to one embodiment of the present invention. According to one embodiment of the present invention, a key can be selected so that the key protection data is encoded within the key. For example, the encoder can select a key such that the MSB of the key value is a constant (e.g., always 1 or always 0) (402). Thus, by selecting a key whose MSB is always the same, the receiver can know that the MSB of the key value is always the same, and therefore does not need to transmit the MSB to the receiver. For example, if the selected key is 6 bits and the 6-bit MSB (i.e., the 6th bit) is always 0, the 6th bit can be removed. The MSB may be replaced with key protection data (e.g., an odd parity bit), which allows for better use of the bandwidth occupied by the bit. Subsequently, the modified key is generated and included in the transmission bits (404). 【0049】 According to one embodiment of the present invention, key protection data can include multiple parity bits. As a result, not only can multiple errors be detected, but errors can also be corrected, thereby improving key integrity. For example, in this embodiment, key protection data can include Hamming code. This reduces catastrophic error propagation at the receiver by optimizing serial data transmission while conforming to run length limitations. 【0050】 Figure 5 is a block diagram of the electronic system 500. As an example, the system 500 may be a television or display device and may include, for example, a transmitter 502 and a receiver 504 that communicate with each other via a high-speed digital serial link 506. In this embodiment, the transmitter 502 may include an encoder 508 which acquires data (e.g., digital data) that is generated within the system 500 or receivable from another source (e.g., an external source), encodes the data, and then transmits the encoded data to the receiver 504. The receiver 504 may communicate with, for example, a display driver that controls the pixels of a display device that emit light in response to the received data. The receiver 504 may include a decoder 510 which receives the encoded data from the transmitter 502 via the link 506 and decodes the encoded data so that the data can be used by the system 500. In this embodiment, the encoder 508 may be a transition encoder that performs transition encoding, such as the techniques described using various embodiments of the present invention. In other embodiments, the encoder 508 may perform other digital encoding methods known to those skilled in the art. It should be noted that the illustrated electronic system 500 is merely one example of an electronic system using high-speed serial data transmission that depends on the accuracy of the transmitted data, and it is apparent to those skilled in the art that other systems may also be used. 【0051】 Unless otherwise specified, the same reference numerals throughout the drawings and specification indicate the same components, and redundant descriptions may be omitted. Furthermore, in order to clarify the detailed description of the invention, optional descriptions may be omitted for each embodiment. 【0052】 In drawings, the size of parts, layers, and regions may be exaggerated for clarity. Furthermore, cross-hatching and / or shading can be used in drawings to clearly define boundaries between adjacent elements. Thus, the presence or absence of cross-hatching and shading, unless otherwise specified, does not imply a preference for or requirement of any particular material, physical properties, dimensions, parts, commonalities between illustrated parts, or / or other characteristics, attributes, or properties of the elements. 【0053】 In the detailed description of the invention, various specific embodiments are shown for illustrative purposes to help understand the diverse embodiments. However, these diverse embodiments can be realized without the specific forms shown herein, or using one or more equivalent forms. Furthermore, in the detailed description of the invention, known structures and devices are shown in the form of block diagrams to avoid unnecessary ambiguity of the diverse embodiments. 【0054】 When we say that a part, layer, region, or component is "located on top of" or "connected to" another part, layer, region, or component, this includes not only cases where it is "directly" above or "directly" connected, but also cases where it is located above (formed) at a distance from the other part, layer, region, or component, and cases where other indirectly connected parts, layers, regions, or components are sandwiched in between. This also collectively includes direct or indirect connections and integrated or non-integrated connections. For example, when a layer, region, or component is described as being "electrically connected" or "electrically coupled" to another part, layer, region, or component, it may be directly electrically connected or coupled to the other part, layer, region, or component, and there may be other parts, layers, regions, or components sandwiched in between. When it is described as existing "directly above" or being "directly connected," it means that there are no other parts in between. On the other hand, other expressions indicating relationships between components, such as "between," "directly between," "adjacent," and "directly adjacent," can be interpreted similarly. Furthermore, when we describe a part or layer as being "between" two different parts or layers, that layer may be the only layer between the two layers, or one or more other layers may be placed therein. 【0055】 In this specification, when expressions such as "at least one of" are used to describe components, they refer to the entire set of components, not to individual components. For example, "at least one of X, Y, and Z," "at least one of X, Y, or Z," and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as X alone, Y alone, Z alone, any combination of two or more of X, Y, and Z (e.g., XYZ, XYY, YZ, ZZ, etc.), or variations thereof. Similarly, expressions such as "at least one of A and B" can include A, B, or A and B. Here, the term "and / or" includes any or all of the related items listed. For example, expressions such as "A and / or B" can include A, B, or A and B. 【0056】 In this specification, terms such as "first," "second," and "third" may be used to refer to various elements, components, regions, layers, and parts, but these various elements, components, regions, layers, and parts are not limited by these terms. Such terms are used to distinguish one element, component, region, layer, or part from other elements, components, regions, layers, and parts. Therefore, a first element, component, region, layer, or part can also be called a second element, component, region, layer, or part without departing from the spirit and scope of the present invention. Even if an element is described as a "first" element, it is not necessary for a second element or other elements to exist, nor does it imply the existence of such elements. Terms such as "first," "second," and "third" may be used to distinguish different categories or sets of elements from each other. For concise expression, "first," "second," etc., may also refer to "first category (or first set)," "second category (or second set)," etc., respectively. 【0057】 The terms used herein are for the purpose of describing specific embodiments and are not intended to limit the invention. Here, in numerical terms, unless otherwise specified, numbers include both singular and plural forms. The expression "includes" a certain feature, stage, operation, part, component, etc., means that it may also include other features, stages, operations, parts, components, etc., in addition to that part. The expression "and / or" includes all combinations of one or more of the listed items. 【0058】 Where the expressions "substantially," "about," "approximately," and similar expressions are used in the description of embodiments of the present invention, they are merely approximations and do not indicate a "degree," but rather include the inherent errors of the measured or calculated values ​​that are known to those skilled in the art. Furthermore, where the expressions "about" and "approximately" are used in the description of embodiments of the present invention, they include the numerical value mentioned and its average within an acceptable range of error, which can be determined by those skilled in the art considering the measured value and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system). For example, "about" can mean one or more standard deviations or approximately ±30%, 20%, 10%, or 5% of the value. Where the expression "can" is used in the description of embodiments of the present invention, it means that it is applicable to "one or more embodiments of the present invention," and "use," "utilize," etc., can be used with a similar meaning along with other similar expressions. 【0059】 In describing embodiments of the present invention, if one or more specific embodiments are implemented differently, the specific process sequence may differ from the sequence described. For example, two processes described as being executed consecutively may be executed simultaneously or in the reverse order of the sequence described. 【0060】 In describing embodiments of the present invention, various embodiments may be described with reference to cross-sectional views showing schematic and / or intermediate structures of the embodiments. The illustrated shapes can be varied or altered in many ways, for example, by manufacturing techniques and / or tolerances. Furthermore, descriptions of specific structures or functions described herein are merely examples for illustrating embodiments of the concept of the present invention. Therefore, the embodiments described herein should be interpreted as not being limited to specific shapes of illustrated regions, but also including variations in shape due to manufacturing methods, for example. For example, if a description illustrates an injection region as a rectangle, the injection region may be round or curved, and the injection concentration may change gradually in a concentration gradient rather than abruptly changing binaryly at the boundary between the injection region and the non-injection region. Similarly, if a description describes the formation of an embedded region by injection, particles or ions may also be injected into the region between the surface where injection occurs and the embedded region. Therefore, the shapes of the regions shown in the drawings are schematic and do not represent, nor are they limited to, the actual shape of the region in the apparatus. 【0061】 The electronic, electrical devices and / or other related devices or parts described in embodiments of the present invention can be realized using appropriate hardware, firmware (e.g., application-ordered integrated circuits), software, or a combination thereof for processing data or digital signals. For example, the diverse components of these devices may be formed on a single integrated circuit chip, or they may be realized on different integrated circuit chips. Alternatively, the diverse components of these devices may be realized on flexible printed circuit films, tape carrier packages (TCPs), printed circuit boards, etc., and may be formed on a single substrate. The circuit hardware may include non-transitory storage media, digital signal processors (DSPs), application-specific integrated circuits (ASICs) that execute instructions stored in programmable logic devices such as graphics processing units (GPUs) and FPGAs, and general-purpose or dedicated central processing units (CPUs). 【0062】 Furthermore, the diverse components of these devices may be processes or threads executable by one or more processors within one or more computer devices that execute computer program instructions and interact with other system elements in order to perform the diverse functions described herein. The computer program instructions are stored in memory implemented in the computer device using standard memory devices such as RAM (random access memory). Those skilled in the art can combine or integrate the functions of various computer devices into a single computer device, or distribute the functions of a particular computer device to one or more other computer devices, without departing from the concept and scope of the embodiments of the present invention. 【0063】 Unless otherwise specified, all terms used herein (including technical and scientific terms) have the same meaning as those commonly known to those skilled in the art in the field to which this invention pertains. Terms such as those defined in commonly used dictionaries should be construed to have the meaning consistent with their meaning in the relevant art and / or herein, and should not be construed in an ideal or overly strict sense unless otherwise explicitly stated. 【0064】 The embodiments described above are examples and are not limited thereto. While several embodiments have been described herein, those skilled in the art can modify the embodiments without departing in any way that produces new content and effects as presented in each embodiment. Therefore, all such modifications or variations are included within the scope of the embodiments as defined in the claims. The functional expression of the claims is intended to include structures that perform the functions mentioned herein, as well as their structural equivalents and equivalent structures. Thus, the above description relates to embodiments and is not limited to any particular embodiment; variations of each embodiment and other embodiments also fall within the scope of the claims. The present invention is defined by the following claims and equivalents. [Explanation of Symbols] 【0065】 500: Electronic Systems 502: Transmitter 504: Receiver 508: Encoder 510: Decoder

Claims

[Claim 1] The encoder receives a data bit sequence, The encoder has a step of selecting a key whose MSB (most distinctive bit) is a constant value, The encoder performs a first transition encoding on the data bit sequence based on the key to generate an encoded data bit sequence, The encoder performs a protective encoding on the key to generate key protection data, The steps include: generating encoded key protection data by replacing the constant value of the MSB of the key with the key protection data using the encoder; The steps include transmitting the encoded data bit sequence and the encoded transmission bit sequence including the encoded key protection data to a receiver, Encoding methods that include this. [Claim 2] The encoding method according to claim 1, wherein the key protection data includes a parity bit. [Claim 3] The key has an odd number of bits, and the parity bit is an even parity bit, The encoding method according to claim 2, wherein the step of generating the encoded key protection data includes the step of inverting the parity bit. [Claim 4] The encoding method according to claim 1, wherein the constant is 0. [Claim 5] The encoding method according to claim 1, wherein the key protection data includes a plurality of parity bits. [Claim 6] The encoding method according to claim 5, wherein the plurality of parity bits are calculated using a Hamming code. [Claim 7] The key has an odd number of bits, and the parity bit is an even parity bit, The encoding method according to claim 5, wherein the step of generating the encoded key protection data includes the step of inverting at least one of the plurality of parity bits. [Claim 8] The encoding method according to claim 7, wherein the step of generating the encoded key protection data further includes inserting one or more inverted parity bits into the front end of the key and inserting one or more inverted parity bits into the rear end of the key. [Claim 9] An input that receives a data bit string, Processor and The output transmits the encoded transmission bit sequence. Includes, The aforementioned processor, Select a key whose MSB (most distinctive bit) is a constant value. Based on the key, the first transition encoding is performed on the data bit sequence to generate the encoded data bit sequence. The aforementioned key is subjected to protective encoding to generate key protection data. The value of the constant of the MSB of the key is replaced with the key protection data to generate encoded key protection data. The encoded transmission bit sequence includes the encoded data bit sequence and the encoded key protection data. Encoder. [Claim 10] The encoder according to claim 9, wherein the key protection data includes a parity bit. [Claim 11] The key has an odd number of bits, and the parity bit is an even parity bit, The encoder according to claim 10, wherein the operation to generate the encoded key protection data includes the operation to invert the parity bit. [Claim 12] The encoder according to claim 9, wherein the constant is 0. [Claim 13] The encoder according to claim 9, wherein the key protection data includes a plurality of parity bits. [Claim 14] The encoder according to claim 13, wherein the plurality of parity bits are calculated by a Hamming code. [Claim 15] The key has an odd number of bits, and the parity bit is an even parity bit, The encoder according to claim 13, wherein the operation to generate the encoded key protection data includes the operation to invert at least one of the plurality of parity bits. [Claim 16] The encoder according to claim 15, wherein the operation for generating the encoded key protection data further includes inserting one or more inverted parity bits into the front end of the key and inserting one or more inverted parity bits into the end end of the key.

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