Gate drive circuit and display panel

Abstract

This application discloses a gate driving circuit and a display panel, the gate driving circuit including a plurality of stage circuits, each of which includes an input module, a first output module, a second output module, a voltage regulator module, and a first driving control module, the voltage regulator module including a first transistor whose gate receives a clock signal, when the gate driving circuit operates in a low power mode, the clock signal turns on the first transistor to reduce the rate of the clock signal, thereby reducing the power consumption of the gate driving circuit.

Description

【Technical Field】 【0001】 This application relates to the field of display technologies, and more specifically to gate driving circuits and display panels. 【Background Art】 【0002】 In a display panel, a gate driving circuit is typically used to supply gate driving signals corresponding to different transistors. The gate driving signal includes a plurality of stage circuits, and each stage circuit outputs a gate driving signal for the corresponding stage. 【0003】 In the prior art, in order to reduce the power consumption of the stage circuit, the operating mode of the gate circuit includes a normal mode and a low power mode. In the low power mode, the rates of a plurality of input signals of the stage circuit are reduced compared to the normal mode. For example, the rates of the start signal (STV) and the clock signal (CK) are decreased. However, when the rate of the clock signal is decreased, the control node that controls the output of the control stage circuit is in a floating state, and the voltage of the control node may leak, which may cause an abnormality in the display panel. 【Summary of the Invention】 【Problems to be Solved by the Invention】 【0004】 This application provides a gate driving circuit and a display panel, and improves the technical problem that in the prior art, when the rate of the clock signal is decreased in the low power mode, the control node that controls the output of the control stage circuit is in a floating state, and the voltage of the control node leaks, causing an abnormality in the display panel. 【Means for Solving the Problems】 【0005】 In the first aspect, the present invention provides a gate drive circuit comprising a plurality of cascaded stage circuits, the stage circuits comprising: an input module that receives an initial signal or a stage transmission signal output by another stage circuit and controls the voltage of a second node; a first output module that outputs a first gate drive signal based on the potential of a third node and a fourth node; a second output module that outputs a second gate drive signal based on the potential of the second node; a voltage regulator module electrically connected to a first power line and a second power line and transmitting the voltage of the first power line or the voltage of the second power line to the second node based on the voltage of the fourth node; and a first drive control module that controls the voltage of the fourth node based on the voltage of the second node, wherein the voltage regulator module comprises a first transistor, the gate of the first transistor is used to receive a clock signal, the operating mode of the gate drive circuit comprises a low-power mode, and when the gate drive circuit is in low-power mode, the clock signal is a first voltage, and the first voltage turns on the first transistor. 【0006】 In one embodiment, the first transistor is an N-channel thin-film transistor, and the first voltage is at a high level. 【0007】 In one embodiment, the first transistor is a double-gate indium gallium zinc oxide thin-film transistor, and both the first gate and the second gate of the first transistor are used to receive a clock signal. 【0008】 In one embodiment, the voltage regulator module further includes a second transistor, the gate of the second transistor electrically connected to the fourth node, one of the source or drain of the second transistor electrically connected to the first power line, the other of the source or drain of the second transistor electrically connected to one of the source or drain of the first transistor, and the other of the source or drain of the first transistor electrically connected to the second node, wherein the channel types of the first and second transistors are different. 【0009】 In one embodiment, when the gate drive circuit is in low-power mode, the voltage at the fourth node turns on the second transistor and transmits the voltage of the first power line to either the source or the drain of the first transistor. 【0010】 In one embodiment, the voltage regulator module further includes a third transistor, the source or drain of the third transistor being electrically connected to the second power line, the other source or drain of the third transistor being electrically connected to the second node, and the gate of the third transistor being electrically connected to the fourth node. 【0011】 In one embodiment, when the gate drive circuit is in low-power mode, the voltage at the fourth node turns off the third transistor. 【0012】 In one embodiment, the third transistor is a double-gate indium gallium zinc oxide thin-film transistor, and both the first gate and the second gate of the third transistor are electrically connected to the fourth node. 【0013】 In one embodiment, the stage circuit further includes a reset module that controls the voltage of the second node based on a reset signal. 【0014】 In one embodiment, the reset module includes a fourth transistor, the source or drain of the fourth transistor being electrically connected to the first power line, the other source or drain of the fourth transistor being electrically connected to the second node, and the gate of the fourth transistor receiving the reset signal. 【0015】 In one embodiment, during the first frame in which the gate drive circuit is operating, the reset signal controls the fourth transistor to turn on before the pulse of the start signal arrives, and transmits the voltage of the first power line to the second node. 【0016】 In one embodiment, the first drive control module is electrically connected to the second node and the fourth node, and the first drive control module outputs a voltage to the fourth node that is phase-inverted with respect to the voltage of the second node. 【0017】 In one embodiment, the first drive control module includes a fifth transistor and a sixth transistor, wherein one source or drain of the fifth transistor is electrically connected to the first power line, the other source or drain of the fifth transistor is electrically connected to the fourth node, one source or drain of the sixth transistor is electrically connected to the third power line, the other source or drain of the sixth transistor is electrically connected to the fourth node, and the gates of the fifth transistor and the sixth transistor are electrically connected to the second node. 【0018】 Here, the fifth transistor is a P-channel thin-film transistor, and the sixth transistor is an N-channel thin-film transistor. 【0019】 In one embodiment, the sixth transistor is a double-gate transistor, and both the first gate and the second gate of the sixth transistor are electrically connected to the second node. 【0020】 In one embodiment, when the gate drive circuit is in low-power mode, the sixth transistor is turned on and outputs the voltage of the third power line to the fourth node. 【0021】 In one embodiment, the stage circuit further includes a second drive control module, which is electrically connected between the second node and the third node, the control terminals of the second drive control module are electrically connected to drive control lines, and the second drive control module is used to control the conduction between the second node and the third node. 【0022】 In one embodiment, the second drive control module is used to remove a first pulse that appears in a frame at the second node and to retain a second pulse that appears in the same frame at the second node. 【0023】 In a second aspect, the present invention provides a display panel comprising a pixel circuit and a gate drive circuit in at least one embodiment described above, wherein the pixel circuit comprises a write transistor that controls the input of a data signal and a compensation transistor that controls the data signal and inputs it to the gate of the drive transistor. The output terminal of the first output module is electrically connected to the gate of the write transistor, and the output terminal of the second output module is electrically connected to the gate of the compensation transistor. [Effects of the Invention] 【0024】 By electrically connecting the voltage regulator module to the second node, when the gate drive circuit is in the low-power mode, the first transistor can be turned on to maintain the potential of the second node. Thereby, when the clock signal is at a low rate, the potential of the second node does not decrease due to the influence of leakage, and the potential of the second node can be maintained at a high potential. Therefore, the gate drive circuit provided in this embodiment can reduce the power consumption of the gate drive circuit by reducing the rate of the clock signal, and there is no display abnormality. As a result, it can solve the problem of the conventional technology that when the rate of the clock signal decreases, the output of the stage circuit becomes abnormal, resulting in a display failure on the display panel. 【Brief Description of the Drawings】 【0025】 [Figure 1] It is a structural schematic diagram showing a gate drive circuit of the prior art. [Figure 2] It is a timing schematic diagram showing some signals in the gate drive circuit shown in FIG. 1. [Figure 3] It is a structural schematic diagram showing a gate drive circuit according to an embodiment of the present application. [Figure 4] It is a timing schematic diagram showing some signals in the gate drive circuit shown in FIG. 3. [Figure 5] It is a timing schematic diagram showing some signals in the gate drive circuit shown in FIG. 1. [Figure 6] It is a timing schematic diagram showing some signals in the gate drive circuit shown in FIG. 3. [Figure 7] It is a timing schematic diagram showing the gate drive circuit shown in FIG. 3. [Figure 8] It is a schematic diagram showing the state of the gate drive circuit shown in FIG. 3 at the first stage of FIG. 7. [Figure 9] It is a schematic diagram showing the state of the gate drive circuit shown in FIG. 3 at the second stage of FIG. 7. [Figure 10] It is a schematic diagram showing the state of the gate drive circuit shown in FIG. 3 at the third stage of FIG. 7. [Figure 11]Figure 3 is a schematic diagram showing the gate drive circuit in the fourth stage, as shown in Figure 7. [Figure 12] Figure 3 is a schematic diagram showing the gate drive circuit in the fifth stage of Figure 7. [Figure 13] Figure 3 is a schematic diagram showing the gate drive circuit in the sixth stage of Figure 7. [Figure 14] Figure 3 is a schematic diagram showing the gate drive circuit in the seventh stage of Figure 7. [Figure 15] Figure 3 is a schematic diagram showing the gate drive circuit in the 8th stage of Figure 7. [Figure 16] Figure 3 is a schematic diagram showing the gate drive circuit in the ninth stage of Figure 7. [Figure 17] Figure 3 is a schematic diagram showing the gate drive circuit in the 10th stage of Figure 7. [Figure 18] Figure 3 is a schematic diagram showing the gate drive circuit in the 11th stage of Figure 7. [Figure 19] Figure 3 is a schematic diagram illustrating the cascade connection between different stage circuits in the gate drive circuit shown. [Figure 20] This is a schematic diagram showing the structure of a display panel according to an embodiment of the present invention. [Figure 21] Figure 20 is a schematic diagram showing the pixel circuit in the display panel. [Figure 22] Figure 21 is a schematic timing diagram showing the pixel circuit. [Modes for carrying out the invention] 【0026】 It should be understood that the examples described herein are for illustrative purposes only and are not intended to limit the present application. 【0027】 Referring to Figures 1 and 2, Figure 1 is a schematic diagram showing a gate drive circuit of the conventional technology. This gate drive circuit includes at least one of the following: an input module 10, a second drive control module 70, a first drive control module 50, a first output module 20, a second output module 30, and a voltage regulator module 40. 【0028】 Here, the first output module 20 outputs a first gate drive signal. The second output module 30 outputs a second gate drive signal. For a detailed explanation of this gate drive circuit, please refer to the related explanations below. 【0029】 To reduce the power consumption of the stage circuit, the rates of multiple input signals to the stage circuit are reduced in low-power mode, for example, the rates of the start signal (STV) and clock signals (CK, XCK) are reduced. 【0030】 However, during the application process, the inventors discovered that when the clock signal rate decreases, abnormalities occur in the display panel. As shown in Figure 2a, when the clock signal is in a high potential state for a long time, transistors T2 and the first transistor T4 are both in the off state, and the second node K is in a floating state. Due to the leakage current of transistor T2, the potential of the second node K cannot be maintained for a long time, and the second node K leaks current due to transistor T2, causing the potential of the second node K to continue to decrease. When the potential of the second node K drops to a certain level, the Vgs of the fifth transistor T3 becomes smaller and smaller, eventually reaching a critical value that turns on the fifth transistor T3. After the fifth transistor T3 is turned on, point P is at a high level, the third transistor T14 is turned on, lowers the potential of the second node K to a low level, and finally turns on transistor T9, which outputs the second gate drive signal, resulting in an output abnormality. 【0031】 In other words, in the gate drive circuit shown in Figure 1, if the clock signal rate decreases, it may lead to the problems described above. Specifically, if the clock signal rate decreases, the output of the stage circuit becomes abnormal, causing display problems on the display panel. 【0032】 Therefore, this embodiment provides a gate drive circuit, and referring to Figures 1 to 22, as shown in Figure 3, this gate drive circuit includes a plurality of stage circuits, each stage circuit including at least one of the following: an input module 10, a first output module 20, a second output module 30, a first drive control module 50, and a voltage regulator module 40. 【0033】 The input module 10 receives an initial signal or a stage transmission signal output by another stage circuit and controls the voltage at the second node K. The first output module 20 outputs a first gate drive signal based on the potentials of the third node Q and the fourth node P. The second output module 30 outputs a second gate drive signal based on the potential of the second node K. The voltage regulator module 40 is electrically connected to the first power line and the second power line and transmits the voltage of the first power line or the voltage of the second power line to the second node K based on the voltage at the fourth node P. The first drive control module 50 controls the voltage at the fourth node P based on the voltage at the second node K. 【0034】 The voltage regulator module 40 includes a first transistor T4, the gate of which is used to receive a clock signal, the operating mode of the gate drive circuit includes a low-power mode, and when the gate drive circuit is in low-power mode, the clock signal is a first voltage, which turns on the first transistor. 【0035】 To make it easier to understand, the gate drive circuit provided in this embodiment can maintain the potential of the second node K by electrically connecting the voltage regulator module 40 to the second node K, thereby turning on the first transistor T4 when the gate drive circuit is in low-power mode. As a result, when the clock signal is at a low rate, the potential of the second node K does not decrease due to leakage current, and the potential of the second node K can be maintained at a high potential. Therefore, the gate drive circuit provided in this embodiment reduces the power consumption of the gate drive circuit by lowering the clock signal rate, and prevents display abnormalities. In other words, it can solve the problem of the conventional technology in which the output of the stage circuit becomes abnormal when the clock signal rate decreases, resulting in display problems on the display panel. 【0036】 In one embodiment, the first transistor T4 is an N-channel thin-film transistor, the clock signal includes a first clock signal (XCK), the gate of the first transistor T4 is used to receive the first clock signal, and when the gate drive circuit is in low-power mode, the voltage of the first clock signal is a first voltage, the first voltage is high level, and the first transistor T4 is turned on. 【0037】 Specifically, the first transistor is a double-gate indium gallium zinc oxide thin-film transistor, and both the first gate and the second gate of the first transistor are used to receive a first clock signal. 【0038】 In this embodiment, when the first clock signal maintains a low rate and high potential state, the gate drive circuit maintains the potential of the second node K by the first transistor T4 in the voltage regulator module 40, thereby lowering the rate of the clock signal and preventing the gate drive circuit from outputting an abnormal output. Therefore, in this invention, the power consumption of the gate drive circuit can be reduced by maintaining a low rate and high potential for the clock signal. 【0039】 In one embodiment, the first transistor T4 is a P-channel thin-film transistor, and when the gate drive circuit is in low-power mode, the voltage of the first clock signal is a first voltage, the first voltage is low level, and the first transistor T4 is turned on. 【0040】 In this embodiment, when the first clock signal maintains a low rate and low potential state, the gate drive circuit maintains the potential of the second node K by the first transistor T4 in the voltage regulator module 40, thereby lowering the rate of the clock signal and preventing the gate drive circuit from outputting an abnormal output. Therefore, in this invention, the power consumption of the gate drive circuit can be reduced by maintaining a high potential at a low rate for the clock signal. 【0041】 In one embodiment, the first drive control module 50 is electrically connected to the second node K and the fourth node P, and the first drive control module 50 is used to control the voltage of the fourth node P based on the voltage of the second node K. Here, the input terminal of the first drive control module 50 is electrically connected to the output terminal of the input module 10, and the output terminal of the first drive control module 50 is electrically connected to the fourth node P. 【0042】 The voltage regulator module 40 is electrically connected to the second node K, the first power line, and the second power line, and is used to maintain the potential of the second node K at the potential of the first power line or the second power line based on the first clock signal and the potential of the fourth node P. 【0043】 In one embodiment, the first drive control module 50 includes a fifth transistor T3 and a sixth transistor T1, wherein one source or drain of the fifth transistor T3 is electrically connected to a first power line, the other source or drain of the fifth transistor T3 is electrically connected to one source or drain of the sixth transistor T1 and to the fourth node P, and the other source or drain of the sixth transistor T1 is electrically connected to a third power line, and the output terminal of the input module 10 is electrically connected to the gate of the fifth transistor T3, the first gate of the sixth transistor T1 and the second gate of the sixth transistor T1. 【0044】 Furthermore, the fifth transistor T3 is a P-channel thin-film transistor. The sixth transistor T1 is a double-gate N-channel thin-film transistor. This improves the dynamic performance of the fifth transistor T3 and the sixth transistor T1, and consequently improves the dynamic performance of the first drive control module 50. 【0045】 The voltage regulator module 40 includes a first transistor T4 and a second transistor T5. One of the sources or drains of the first transistor T4 is electrically connected to the output terminal of the input module 10 and to the second node K. The gate of the first transistor T4 is electrically connected to the first clock line to receive the first clock signal. The other of the sources or drains of the first transistor T4 is electrically connected to one of the sources or drains of the second transistor T5. The other of the sources or drains of the second transistor T5 is electrically connected to the first power supply line. The gate of the second transistor T5 is electrically connected to the output terminal of the first drive control module 50 and to the fourth node P. 【0046】 Furthermore, the voltage regulator module 40 can maintain the second node K at a high potential based on the potential of the fourth node P and the potential of the first clock line. That is, when the fourth node P is at a low potential, the first power line can control the potential of the second node K to the potential of the first power signal PVGH. 【0047】 In one embodiment, the voltage regulator module 40 further includes a third transistor T14, the source or drain of the third transistor T14 being electrically connected to the second power line, the other source or drain of the third transistor T14 being electrically connected to the second node K, and the gate of the third transistor T14 being electrically connected to the fourth node P. 【0048】 Furthermore, the voltage regulator module 40 can maintain the potential of the second node K at a low potential based on the potential of the fourth node P. That is, when the fourth node P is at a high potential, the second power line can control the potential of the second node K to the potential of the second power signal VGL. 【0049】 Here, the third transistor T14 is an N-channel thin-film transistor, and the third transistor T14 is a double-gate thin-film transistor, which not only enhances its ability to control the current passing through it, but also reduces the drift amplitude of the threshold voltage. 【0050】 In one embodiment, the sixth transistor T1, the first transistor T4, and the third transistor T14 may all be indium gallium zinc oxide thin-film transistors. 【0051】 In one embodiment, the gate drive circuit further includes a second drive control module 70. The second drive control module 70 is electrically connected between the second node K and the third node Q. The input terminals of the second drive control module 70 are electrically connected to the output terminals of the input module 10, and the control terminals of the second drive control module 70 are electrically connected to the drive control lines. 【0052】 The input terminal of the second output module 30 is electrically connected to the output terminal of the input module 10, and the output terminal of the second output module 30 is electrically connected to the positive pulse gate drive line of the Nth stage, and the number of positive pulses output by the positive pulse gate drive line of the Nth stage in one frame is greater than the number of negative pulses output by the negative pulse gate drive line of the Nth stage in one frame. 【0053】 The positive pulse gate drive line of the Nth stage, i.e., the second gate drive line, is used to transmit the positive pulse gate drive signal Nout[N] of the Nth stage, i.e., the second gate drive signal, and the second gate drive signal can be used as the stage transmission signal of the stage circuit. The negative pulse gate drive line of the Nth stage, i.e., the first gate drive line, is used to transmit the negative pulse gate drive signal Pout[N] of the Nth stage, i.e., the first gate drive signal. 【0054】 Furthermore, the gate drive circuit provided in this embodiment can output a second gate drive signal with a higher number of pulses via the input module 10 and the second output module 30, and can also select the second gate drive signal as a stage transmission signal between different stage circuits. In addition, the input module 10, the second drive control module 70, the first drive control module 50, and the first output module 20 can output a first gate drive signal with a lower number of pulses, thereby satisfying the requirements for pulse duration, number, etc., of the gate drive signal in one frame of the corresponding pixel circuit, and driving the pixel circuit to achieve image quality display. 【0055】 In one embodiment, the second drive control module 70 includes a transistor T11, where either the source or drain of transistor T11 is electrically connected to the output terminal of the input module 10, the other source or drain of transistor T11 is electrically connected to the control terminal of the first output module 20, and the gate of transistor T11 is electrically connected to a drive control line. Here, transistor T11 is a P-channel thin-film transistor. The drive control line is used to transmit a drive control signal RST. 【0056】 The output terminal of the input module 10 is the second node K. One of the control terminals of the first output module 20 is the third node Q. The other of the source or drain of transistor T11 is node W. The second drive control module 70 is used to reduce the double pulses that appear in one frame at the second node K to a single pulse that appears in one frame at the third node Q. Specifically, the first pulse that appears in one frame at the second node K is removed, and the second pulse that appears in the same frame is retained. 【0057】 Furthermore, this embodiment is advantageous in ensuring the output stability of the negative pulse gate drive signal Pout[N] of the Nth stage, and avoids the coupling pull-down phenomenon that occurs before the negative pulse arrives. 【0058】 In one embodiment, the second drive control module 70 further includes a first capacitor C2, one end of which is electrically connected to the gate of the transistor T11, and the other end of which is electrically connected to the other of the source or drain of the transistor T11. 【0059】 Furthermore, this embodiment is advantageous in further improving the output stability of the negative pulse gate drive signal Pout[N] of the Nth stage. 【0060】 The output terminal of the input module 10 is the second node K. The control terminal of the first output module 20 is the third node Q. The other end of the source or drain of transistor T11 is node W. The second drive control module 70 is used to reduce the double pulses that appear in one frame at the second node K to a single pulse that appears in one frame at the third node Q. Specifically, the second node K removes the first pulse that appears in one frame and retains the second pulse that appears in the same frame. 【0061】 In one embodiment, the first output module 20 includes a transistor T6 and a second capacitor C1, wherein the gate of transistor T6 is electrically connected to either the source or the drain of transistor T11, one of the source or the drain of transistor T6 is electrically connected to the second clock line, the other of the source or the drain of transistor T6 is electrically connected to the negative pulse gate drive line of the Nth stage, one end of the second capacitor C1 is electrically connected to the gate of transistor T6, and the other end of the second capacitor C1 is electrically connected to the other of the source or the drain of transistor T6. Here, the ratio of the capacitances of the first capacitor C2 and the second capacitor C1 is 0.5 or greater. 【0062】 Furthermore, this embodiment is advantageous in further ensuring the output stability of the Nth stage negative pulse gate drive signal Pout[N] by setting the ratio value of the capacitance between the first capacitor C2 and the second capacitor C1, and avoids the coupling pull-down phenomenon that occurs before the negative pulse arrives. 【0063】 Specifically, the capacitance of the first capacitor C2 may be 50 fF or more. The capacitance of the second capacitor C1 may be 100 fF or more. In some embodiments, the transistor T6 may be a P-channel thin-film transistor. 【0064】 In one embodiment, the first output module 20 includes a transistor T7, where either the source or drain of transistor T7 is electrically connected to a first power line, the other source or drain of transistor T7 is electrically connected to the negative pulse gate drive line of the Nth stage, and the gate of transistor T7 is electrically connected to the output terminal of the first drive control module 50, i.e., the fourth node P. 【0065】 Note that transistor T7 may be a P-channel thin-film transistor. Under the combined action of the first output module 20, a desired Nth-stage negative pulse gate drive signal Pout[N] can be modulated. 【0066】 In one embodiment, the input module 10 includes transistor T2, transistor T13, and transistor T12. One source or drain of transistor T13 is electrically connected to a third power line, the other source or drain of transistor T13 is electrically connected to the input terminal of the input module 10, the first gate of transistor T13 is electrically connected to a start control line or a positive pulse gate drive line of the NY stage, the first gate of transistor T13 is electrically connected to the second gate of transistor T13, and transistor T13 is an N-channel thin-film transistor. One of the sources or drains of transistor T12 is electrically connected to the first power line, the other of the sources or drains of transistor T12 is electrically connected to the other of the sources or drains of transistor T13, the gate of transistor T12 is electrically connected to the first gate of transistor T13, transistor T12 is a P-channel thin-film transistor, one of the sources or drains of transistor T2 is electrically connected to the output terminals of transistors T13 and T12, the other of the sources or drains of transistor T2 is electrically connected to the input terminal of the second drive control module 70, and the gate of transistor T2 is electrically connected to the first clock line. In some embodiments, transistor T2 may be a P-channel thin-film transistor. 【0067】 Furthermore, the input module 10 in this embodiment not only has an objective inversion effect, but also, that is, the input signal and the output signal are potential-inverted at the same time, causing the positive pulse gate drive signal Nout[N] of the Nth stage to function as a stage transmission signal between stage circuits. Otherwise, stage transmission cannot be achieved between the circuits of each stage, and the gate drive circuit will not be able to supply the corresponding gate drive signal properly. 【0068】 In one embodiment, the second output module 30 includes a P-channel transistor T9 and an N-channel transistor T10, wherein the first pole of transistor T9 is electrically connected to the fourth power line, and the gate of transistor T9 is electrically connected to the second node K. The first pole of transistor T10 is electrically connected to the second pole of transistor T9 to output a second gate drive signal, and the gate of transistor T10 is electrically connected to the gate of transistor T9. 【0069】 In one embodiment, the gate of transistor T10 includes a first gate and a second gate, and the second node K is electrically connected to the first gate and the second gate of transistor T10. 【0070】 In this embodiment, transistor T10 may be a double-gate thin-film transistor, which not only enhances the control capability over the current passing through the body but also reduces the drift amplitude of the threshold voltage. Here, transistor T10 is an indium gallium zinc oxide thin-film transistor. 【0071】 Here, the first power line is used to transmit the first power signal PVGH, which can control the on-on state of an N-channel thin-film transistor or the off-state of a P-channel thin-film transistor. The second power line is used to transmit the second power signal NVGL, which can control the on-on state of a P-channel thin-film transistor or the off-state of an N-channel thin-film transistor. The third power line is used to transmit the third power signal PVGL, and the fourth power line is used to transmit the fourth power signal NVGH. 【0072】 In one embodiment, when the third transistor T14 is in the off state, the third power supply signal PVGL is smaller than the second power supply signal NVGL to ensure it is turned off more completely. 【0073】 In one embodiment, the second output module 30 outputs a second gate drive signal based on the potential of the second node K, and the number of pulses in one frame of the second gate drive signal is greater than the number of pulses in one frame of the first gate drive signal. 【0074】 Transistor T9 is a P-channel thin-film transistor. Transistor T10 is a double-gate N-channel thin-film transistor. This improves the dynamic performance of transistors T9 and T10, and consequently, the dynamic performance of the second output module 30. 【0075】 The positive pulse gate drive line of the Nth stage is used to transmit the positive pulse gate drive signal Nout[N] of the Nth stage. The negative pulse gate drive line of the Nth stage is used to transmit the negative pulse gate drive signal Pout[N] of the Nth stage. The first clock line is used to transmit the first clock signal XCK. The second clock line is used to transmit the second clock signal CK. The start control line is used to transmit the start control signal STV. The positive pulse gate drive line of the NY stage is used to transmit the positive pulse gate drive signal Nout[NY] of the NY stage. The positive pulse gate drive line of the NX stage is used to transmit the positive pulse gate drive signal Nout[NX] of the NX stage. The drive control line is used to transmit the drive control signal RST. 【0076】 In one embodiment, the second drive control module 70 further includes a leakage protection transistor T8, where one source or drain of the leakage protection transistor T8 is electrically connected to the other source or drain of transistor T11, the other source or drain of the leakage protection transistor T8 is electrically connected to the control terminal of the first output module 20, and the gate of the leakage protection transistor T8 is electrically connected to a leakage protection signal line to receive a leakage protection signal. 【0077】 Here, the leakage prevention signal line may be a positive pulse gate drive line N[nX], specifically the positive pulse gate drive line of the (n-2)th stage, and the leakage prevention signal is the positive pulse gate drive signal N[n-2] of the (n-2)th stage. 【0078】 As shown in Figure 5c, if the first clock signal XCK signal of transistor T2 has not started, the second node K is in a floating state, and if the second node K is randomly in a low-level state, the second output module 30 outputs a high level, causing a series of stage transmission reactions and resulting in output abnormalities for the first frame in all rows. 【0079】 To solve the above problems, in one embodiment, the Nth stage circuit further includes a reset module 60 which controls the voltage of the second node based on a reset signal control. The reset module 60 includes a fourth transistor T15, one of which is electrically connected to a first power line, the other of which is electrically connected to the second node, and the gate of the fourth transistor T15 receives the reset signal control. 【0080】 Here, the reset signal control is turned on only once each time the gate drive circuit is energized, that is, it turns on the fourth transistor T15 and raises the potential of the second node K to a high potential. At that time, the start signal STV, the first clock signal XCK, the second clock signal CK, the leakage prevention signal N[n-2], and the drive control signal RST have not yet begun transmitting signals. 【0081】 To make it easier to understand, the reset module 60 ensures that the second node K is kept at a high level each time the gate drive circuit is energized, so that the abnormal output situation described above does not occur, as shown in Figure 6d. 【0082】 The operation process of the above stage circuit in one frame may include the following steps, as shown in Figure 7. 【0083】 In the first stage S1, as shown in Figures 7 and 8, the start control signal STV, drive control signal RST, first clock signal XCK, and leakage prevention signal N[n-2] are all at low potential, the second clock signal CK is at high potential, the first node O, second node K, and third node Q are all at high potential, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0084】 In the second stage S2, as shown in Figures 7 and 9, the start control signal STV, the second clock signal CK, and the leakage prevention signal N[n-2] are all at low potential, the drive control signal RST and the first clock signal XCK are at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0085】 In the third stage S3, as shown in Figures 7 and 10, the start control signal STV, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at low potentials, the drive control signal RST and the second clock signal CK are all at high potentials, the first node O, the second node K, and the third node Q are all at high potentials, the fourth node P is at low potentials, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potentials, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potentials. 【0086】 In the fourth stage S4, as shown in Figures 7 and 11, the drive control signal RST and the start control signal STV are at low potential, the first clock signal XCK, the second clock signal CK, and the leakage prevention signal N[n-2] are all at high potential, the first node O, the second node K, and the third node Q are all at high potential, the fourth node P is at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0087】 In the fifth stage S5, as shown in Figures 7 and 12, the drive control signal RST and the first clock signal XCK are both at low potential, the start control signal STV, the second clock signal CK, and the leakage prevention signal N[n-2] are all at high potential, the third node Q and the fourth node P are both at high potential, the first node O and the second node K are both at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0088】 In the sixth stage S6, as shown in Figures 7 and 13, the start control signal STV, the first clock signal XCK, the second clock signal CK, and the drive control signal RST are all at high potential, the leakage prevention signal N[n-2] is at low potential, the third node Q and the fourth node P are both at high potential, the first node O and the second node K are at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0089】 In the seventh stage S7, as shown in Figures 7 and 14, the start control signal STV, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at low potentials, the second clock signal CK and the drive control signal RST are both at high potentials, the fourth node P is at low potentials, the first node O, the second node K, and the third node Q are at high potentials, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potentials, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potentials. 【0090】 In the eighth stage S8, as shown in Figures 7 and 15, the start control signal STV, the first clock signal XCK, and the leakage prevention signal N[n-2] are all at high potential, the drive control signal RST is at low potential, the first node O and the fourth node P are at low potential, the third node Q and the second node K are both at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0091】 In the ninth stage S9, as shown in Figures 7 and 16, the drive control signal RST and the first clock signal XCK are both at low potential, the start control signal STV, the second clock signal CK, and the leakage prevention signal N[n-2] are at high potential, the first node O and the second node K are at low potential, the fourth node P and the third node Q are both at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0092】 In the tenth stage S10, as shown in Figures 7 and 17, the start control signal STV, drive control signal RST, second clock signal CK, and leakage prevention signal N[n-2] are all at low potential, the first clock signal XCK is at high potential, the first node O and the fourth node P are at high potential, the third node Q and the second node K are at low potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at high potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at low potential. 【0093】 In the 11th stage S11, as shown in Figures 7 and 18, the start control signal STV, drive control signal RST, first clock signal XCK, and leakage prevention signal N[n-2] are all at low potential, the second clock signal CK is at high potential, the fourth node P is at low potential, the first node O, the third node Q, and the second node K are at high potential, the positive pulse gate drive signal Nout[N] of the Nth stage is at low potential, and the negative pulse gate drive signal Pout[N] of the Nth stage is at high potential. 【0094】 In Figures 8 to 18, the "X" marks indicate that the transistor covered by the "X" is in the OFF state, while transistors not covered by the "X" marks are in the ON state. 【0095】 As shown in Figure 7, the positive pulse gate drive signal Nout[N] of the Nth stage has a first positive pulse and a second positive pulse sequentially in one frame. The negative pulse gate drive signal Pout[N] of the Nth stage has a first negative pulse in one frame. 【0096】 In a single frame, the duration of the second positive pulse is longer than the duration of the first negative pulse, and the duration of the first negative pulse is within the duration of the second positive pulse. 【0097】 Figure 19 is a schematic diagram showing the cascade connection between different stage circuits in the gate drive circuit shown in Figure 3, where the stages are sequentially labeled from top to bottom as the first stage circuit 101, the second stage circuit 102, the third stage circuit 103, the fourth stage circuit 104, the fifth stage circuit 105, the sixth stage circuit 106, and so on. The first clock line is electrically connected to each stage circuit, and the second clock line is also electrically connected to each stage circuit. 【0098】 Here, the first stage circuit 101 outputs the first stage negative pulse gate drive signal Pout[1] and the first stage positive pulse gate drive signal Nout[1], respectively, based on the first stage negative pulse gate drive line and the first stage positive pulse gate drive line. 【0099】 The second stage circuit 102 outputs the second stage negative pulse gate drive signal Pout[2] and the second stage positive pulse gate drive signal Nout[2], respectively, based on the second stage negative pulse gate drive line and the second stage positive pulse gate drive line. 【0100】 The third stage circuit 103 outputs the third stage negative pulse gate drive signal Pout[3] and the third stage positive pulse gate drive signal Nout[3], respectively, via the third stage negative pulse gate drive line and the third stage positive pulse gate drive line. 【0101】 The fourth stage circuit 104 outputs the fourth stage negative pulse gate drive signal Pout[4] and the fourth stage positive pulse gate drive signal Nout[4], respectively, via the fourth stage negative pulse gate drive line and the fourth stage positive pulse gate drive line. 【0102】 The fifth stage circuit 105 outputs the fifth stage negative pulse gate drive signal Pout[5] and the fifth stage positive pulse gate drive signal Nout[5], respectively, via the fifth stage negative pulse gate drive line and the fifth stage positive pulse gate drive line. 【0103】 The sixth stage circuit 106 outputs the sixth stage negative pulse gate drive signal Pout[6] and the sixth stage positive pulse gate drive signal Nout[6], respectively, via the sixth stage negative pulse gate drive line and the sixth stage positive pulse gate drive line. The other stage circuits can then be inferred. 【0104】 In the first stage circuit 101, the input terminal (IN) of the input module 10 is electrically connected to the start control line and receives the start control signal STV. In the other stage circuits, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal of the previous stage. For example, in the second stage circuit 102, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[1] of the first stage; in the third stage circuit 103, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[2] of the second stage; in the fourth stage circuit 104, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[3] of the third stage; in the fifth stage circuit 105, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[4] of the fourth stage; and in the sixth stage circuit 106, the input terminal (IN) of the input module 10 receives the positive pulse gate drive signal Nout[5] of the fifth stage. The others can be inferred further. To make it clear, multiple stage circuits can be cascaded at intervals of a different number, which will not be explained further in this application. 【0105】 In the fifth stage circuit 105, the control terminal of the second drive control module 70 (transistor T8) receives the positive pulse gate drive signal Nout[3] from the third stage, and in the sixth stage circuit 106, the control terminal of the second drive control module 70 receives the positive pulse gate drive signal Nout[4] from the fourth stage, and the others can be inferred further. Among these, X may be 3, 4, 5, 6, 7, etc., and here we will explain using X=2 as an example. 【0106】 Furthermore, since the output terminals of some stage circuits are connected to dummy pixels or suspended, it is not the pixel circuits of the Nth row that are connected to each output terminal of the Nth stage circuit. Instead, it is necessary to determine which row the connected pixel circuit is in based on the number of stage circuits connected to dummy pixels or the number of suspended stage circuits. 【0107】 The upper diagram of Figure 20 is a schematic diagram of the structure of a conventional display panel, in which the left side of the display area (AA area) (non-display area or bezel area) is arranged with gate drive circuits used to supply the light emission control signal EM, gate drive signal Nscan1, and gate drive signal Pscan, respectively, and the right side of the display area (AA area) (non-display area or bezel area) is arranged with gate drive circuits used to supply the gate drive signal Pscan and gate drive signal Nscan2, respectively. 【0108】 Here, each gate drive signal Pscan drives one row of pixel circuitry. The operation methods of gate drive signals Nscan1 and Nscan2 are the same as those of gate drive signal Pscan, however, one gate drive signal Nscan1 / Nscan2 needs to drive two rows of pixel circuitry. In actual operation, in order to achieve a narrower bezel, the gate drive circuit used to output gate drive signal Nscan1 and the gate drive circuit used to output gate drive signal Nscan2 are both configured to drive only one side, which degrades the driving capability of these two gate drive circuits and increases power consumption. 【0109】 Therefore, in this embodiment, the gate drive circuit shown in Figure 3 is arranged to drive both sides as shown in the lower part of Figure 20, that is, the gate drive circuits shown in Figure 3 are placed on both sides of the AA region, and the gate drive signals corresponding to both ends of each gate drive line are input simultaneously. This not only improves the driving capability of the negative pulse gate drive signal Pout[N] and the positive pulse gate drive signal Nout of the Nth stage, but also reduces power consumption and further reduces the space occupied by the bezel, which is advantageous for developing narrower bezel designs. 【0110】 Here, the positive pulse gate drive signal Nout includes the positive pulse gate drive signal Nout[N] of the Nth stage and the positive pulse gate drive signal Nout[NL] of the NL stage. Here, L may be an integer greater than or equal to 1, for example, 2, 3, 4, 5, 6, ..., etc. 【0111】 In one embodiment, the embodiment provides a display panel which includes a gate drive circuit and a pixel circuit in at least one embodiment, wherein one row of pixel circuits is electrically connected to a positive pulse gate drive line of the Nth stage and a negative pulse gate drive line of the Nth stage. 【0112】 To make it clear, the display panel provided in this embodiment includes the gate drive circuit in at least one of the embodiments described above. Similarly, by electrically connecting the voltage regulator module 40 to the second node K, the voltage regulator module 40 can control the potential of the fourth node P based on the potential of the second node K, thereby maintaining the potential of the second node K. As a result, when the clock signal is at a low rate, the potential of the second node K will not decrease due to leakage current, and the potential of the second node K can be maintained. Therefore, the gate drive circuit provided in this embodiment reduces the power consumption of the gate drive circuit by lowering the clock signal rate, and prevents display abnormalities. This solves the problem in the conventional technology where a decrease in the clock signal rate causes abnormal output of the stage circuit and results in display failures on the display panel. 【0113】 Figure 21 is a schematic diagram showing the pixel circuit in the display panel shown in Figure 20. To make it easier to understand, the gate drive circuit shown in Figure 3 can supply the positive pulse gate drive signal Nout[N] for the Nth stage, the positive pulse gate drive signal Nout[NL] for the NL stage, and the negative pulse gate drive signal Pout[N] for the Nth stage, corresponding to the pixel circuit shown in Figure 21. 【0114】 The pixel circuit shown in Figure 21 may include at least one of the following: a writing transistor T2P, a driving transistor T1P, a first light emission control transistor T5P, a second light emission control transistor T6P, a first initialization transistor T4P, a second initialization transistor T7P, a third initialization transistor T8P, a compensation transistor T3P, a light-emitting element D1, a storage capacitor Cst, and a bootstrap capacitor Cboost. 【0115】 The first power line is electrically connected to the first pole of the first light-emitting control transistor T5P and one end of the storage capacitor Cst. The second pole of the first light-emitting control transistor T5P is electrically connected to the first pole of the drive transistor T1P and the first pole of the write transistor T2P. The second pole of the drive transistor T1P is electrically connected to the first pole of the compensation transistor T3P and the first pole of the second light-emitting control transistor T6P. The second pole of the second light-emitting control transistor T6P is electrically connected to the first pole of the second initialization transistor T7P and the anode of the light-emitting element D1. The cathode of the light-emitting element D1 is electrically connected to the second power line. The light-emitting control line is electrically connected to the gate of the first light-emitting control transistor T5P and the gate of the second light-emitting control transistor T6P. The second pole of the write transistor T2P is electrically connected to the data line. The gate of the write transistor T2P is electrically connected to the Nth stage negative pulse gate drive line (first gate drive line) and one end of the bootstrap capacitor Cboost. The second pole of the second initialization transistor T7P is electrically connected to the second initialization line, and the gate of the second initialization transistor T7P is electrically connected to the third gate drive line. The second pole of the compensation transistor T3P is electrically connected to the gate of the drive transistor T1P, and the gate of the compensation transistor T3P is electrically connected to the positive pulse gate drive line (second gate drive line) of the Nth stage. The gate of the drive transistor T1P is electrically connected to the other end of the storage capacitor Cst, the other end of the bootstrap capacitor Cboost, and the first pole of the first initialization transistor T4P. The second pole of the first initialization transistor T4P is electrically connected to the first initialization line, and the gate of the first initialization transistor T4P is electrically connected to the positive pulse gate drive line (second gate drive line) of the NL stage. The first pole of the third initialization transistor T8P is electrically connected to the first pole of the drive transistor T1P, the second pole of the third initialization transistor T8P is electrically connected to the third initialization line, and the gate of the third initialization transistor T8P and the gate of the second initialization transistor T7P share the third gate drive line. 【0116】 Furthermore, the second initialization line may be replaced with the first initialization line, which reduces the number of wires required for the pixel circuit by one, and is advantageous in increasing the density of pixel circuits in the display panel. 【0117】 Here, the first electrode may be either a source or a drain, and the second electrode may be either a source or a drain. For example, if the first electrode is a source, the second electrode is a drain. Or, if the first electrode is a drain, the second electrode is a source. 【0118】 Here, the first power line is used to transmit the power positive signal VDD, and the second power line is used to transmit the power negative signal VSS, with the potential of the power positive signal VDD being higher than the potential of the power negative signal VSS. The data line is used to transmit the data signal Data. The light emission control line is used to transmit the light emission control signal EM. The first initialization line is used to transmit the first initialization signal Vi1. The second initialization line is used to transmit the second initialization signal Vi2. The third initialization line is used to transmit the third initialization signal Vi3. The first gate drive line is used to transmit the negative pulse gate drive signal Pout[N] of the Nth stage. The positive pulse gate drive line (second gate drive line) of the Nth stage is used to transmit the positive pulse gate drive signal Nout[N] of the Nth stage. The positive pulse gate drive line (second gate drive line) of the NL stage is used to transmit the positive pulse gate drive signal Nout[NL] of the NL stage. The third gate drive line is used to transmit the gate drive signal Pscan2. 【0119】 The operation timing of the pixel circuit shown in Figure 21 in one frame is such that, as shown in Figure 22, the pixel circuit shown in Figure 21 can normally display when driven by the common drive of the Nth stage negative pulse gate drive signal Pout[N], gate drive signal Pscan2, NL stage positive pulse gate drive signal Nout[NL], Nth stage positive pulse gate drive signal Nout[N], and light emission control signal EM. 【0120】 Here, the negative pulse gate drive signal Pout[N] for the Nth stage, the positive pulse gate drive signal Nout[NL] for the NL stage, and the positive pulse gate drive signal Nout[N] for the Nth stage can be supplied by the gate drive circuit shown in Figure 3. 【0121】 Those skilled in the art should understand that, while there may be variations in specific embodiments and scope of application in light of the concept of this application, in summary, the description herein is not intended to limit this application.

Claims

[Claim 1] It includes multiple cascaded stage circuits, and the stage circuits are An input module that receives an initial signal or a stage transmission signal output by another stage circuit and controls the voltage of the second node, A first output module that outputs a first gate drive signal based on the voltage of the third node and the voltage of the fourth node, A second output module that outputs a second gate drive signal based on the voltage of the second node, A voltage regulator module electrically connected to a first power line and a second power line, which transmits the voltage of the first power line or the voltage of the second power line to the second node based on the voltage of the fourth node, Includes a first drive control module that controls the voltage of the fourth node based on the voltage of the second node, Here, the voltage regulator module includes a first transistor, the gate of the first transistor is used to receive a clock signal, the operating mode of the gate drive circuit includes a low-power mode, and when the gate drive circuit is in low-power mode, the clock signal is a first voltage, the first voltage turns on the first transistor, and based on the voltage of the fourth node and the first voltage, transmits the voltage of the first power line to the second node. Gate drive circuit. [Claim 2] The first transistor is an N-channel thin-film transistor, and the first voltage is high level. The gate drive circuit according to claim 1. [Claim 3] The first transistor is a double-gate indium gallium zinc oxide thin-film transistor, and both the first gate and the second gate of the first transistor are used to receive a clock signal. The gate drive circuit according to claim 2. [Claim 4] The voltage regulator module further includes a second transistor, the gate of which is electrically connected to the fourth node, one of the source or drain of which is electrically connected to the first power line, the other of the source or drain of which is electrically connected to one of the source or drain of which is electrically connected to the second node, Here, the channel types of the first transistor and the second transistor are different. The gate drive circuit according to claim 2. [Claim 5] When the gate drive circuit is in low-power mode, the voltage at the fourth node turns on the second transistor and transmits the voltage of the first power line to either the source or the drain of the first transistor. The gate drive circuit according to claim 4. [Claim 6] The voltage regulator module further includes a third transistor, wherein one of the source or drain of the third transistor is electrically connected to the second power line, the other of the source or drain of the third transistor is electrically connected to the second node, and the gate of the third transistor is electrically connected to the fourth node. The gate drive circuit according to claim 1. [Claim 7] When the gate drive circuit is in low-power mode, the voltage at the fourth node turns off the third transistor. The gate drive circuit according to claim 6. [Claim 8] The third transistor is a double-gate indium gallium zinc oxide thin-film transistor, and both the first gate and the second gate of the third transistor are electrically connected to the fourth node. The gate drive circuit according to claim 7. [Claim 9] The stage circuit further includes a reset module that controls the voltage of the second node based on a reset signal. The gate drive circuit according to claim 1. [Claim 10] The reset module includes a fourth transistor, the source or drain of the fourth transistor being electrically connected to the first power line, the other source or drain of the fourth transistor being electrically connected to the second node, and the gate of the fourth transistor receiving the reset signal. The gate drive circuit according to claim 9. [Claim 11] In the first frame in which the gate drive circuit is operating, the reset signal controls the fourth transistor to turn on before the start signal pulse arrives, and transmits the voltage of the first power line to the second node. The gate drive circuit according to claim 10. [Claim 12] The first drive control module is electrically connected to the second node and the fourth node, and the first drive control module outputs a voltage to the fourth node that is phase-inverted with respect to the voltage of the second node. The gate drive circuit according to claim 2. [Claim 13] The first drive control module includes a fifth transistor and a sixth transistor, wherein one of the source or drain of the fifth transistor is electrically connected to the first power line, and the other of the source or drain of the fifth transistor is electrically connected to the fourth node. One of the source or drain of the sixth transistor is electrically connected to the third power line, the other of the source or drain of the sixth transistor is electrically connected to the fourth node, and the gates of the fifth transistor and the sixth transistor are electrically connected to the second node. Here, the fifth transistor is a P-channel thin-film transistor, and the sixth transistor is an N-channel thin-film transistor. The gate drive circuit according to claim 12. [Claim 14] The sixth transistor is a double-gate transistor, and both the first gate and the second gate of the sixth transistor are electrically connected to the second node. The gate drive circuit according to claim 13. [Claim 15] When the gate drive circuit is in low-power mode, the sixth transistor is turned on and outputs the voltage of the third power line to the fourth node. The gate drive circuit according to claim 14. [Claim 16] The stage circuit further includes a second drive control module, which is electrically connected to the second node and the third node, respectively, and the control terminals of the second drive control module are electrically connected to drive control lines, and the second drive control module is used to control the conduction between the second node and the third node. A gate drive circuit according to any one of claims 1 to 14. [Claim 17] The second drive control module is used to remove the first pulse so that the first pulse appearing in one frame of the second node does not transmit to the third node, and to hold the second pulse so that the second pulse appearing in the same frame of the second node does not transmit to the third node. The gate drive circuit according to claim 16. [Claim 18] The second drive control module includes a transistor, the source or drain of which is electrically connected to the output terminal of the input module, the other source or drain of which is electrically connected to the control terminal of the first output module, and the gate of which is electrically connected to the drive control line, wherein the transistor is a P-channel thin-film transistor, and the drive control line is used to transmit a drive control signal. The gate drive circuit according to claim 16. [Claim 19] The second drive control module further includes a first capacitor, one end of which is electrically connected to the gate of a transistor, and the other end of which is electrically connected to the source or drain of the transistor. The gate drive circuit according to claim 17. [Claim 20] A pixel circuit including a writing transistor that controls the input of a data signal, and a compensation transistor that controls the data signal and inputs it to the gate of a driving transistor, A gate drive circuit according to any one of claims 1 to 15, The output terminal of the first output module is electrically connected to the gate of the writing transistor, and the output terminal of the second output module is electrically connected to the gate of the compensation transistor. Display panel.

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