Master clock generation device

Abstract

This master clock generation device comprises: a reference signal generation unit (104) that generates a master clock; a multiplier (105) that generates a signal obtained by multiplying the frequency of the master clock on the basis of the master clock generated by the reference signal generation unit (104); a first difference detection unit (101a) that is provided for each of one or more systems, and that, on the basis of the signal generated by the multiplier (105) and a signal from an atomic clock (2) of a corresponding system, detects a phase difference or a frequency difference between the signals; a second difference detection unit (101b) that, on the basis of the signal generated by the multiplier (105) and the master clock generated by the reference signal generation unit (104), detects a phase difference or a frequency difference between the signals; a digital signal processing unit (102) that, on the basis of a detection result from the first difference detection unit (101a) and a detection result from the second difference detection unit (101b), generates frequency phase control data that is data for controlling the frequency and phase of the master clock; and a signal synthesis unit (103) that, on the basis of the frequency phase control data generated by the digital signal processing unit (102), controls the frequency and phase of an output signal to the reference signal generation unit (104). The reference signal generation unit (104) generates the master clock according to the output signal from the signal synthesis unit (103).