Method to calibrate, predict, and control stochastic defects in EUV lithography
The method addresses the inefficiencies in predicting and controlling stochastic defects in EUV lithography by using a processor to sort and normalize defect probabilities, reducing the need for extensive data and improving defect capture across complex layouts, thus enhancing yield and reducing costs.
Patent Information
- Application Number
- PCT/US2024/048250
- Authority / Receiving Office
- WO · WO
- Patent Type
- Applications
- Current Assignee / Owner
- Priority Date
- 2024-09-24
- Filing Date
- 2024-09-25
- Publication Date
- 2025-04-03
AI Technical Summary
Current methods for predicting and controlling stochastic defects in EUV lithography are inefficient due to the need for extensive experimental data and the impracticality of applying empirical models across complex design layouts.
A method involving a processor that receives an initial probability of stochastic defect occurrence, sorts defect locations by probability, determines a cumulative expected defect count, normalizes it, and selects defect locations above a threshold to capture potential stochastic defects, thereby optimizing defect prediction and control.
This approach reduces the need for extensive experimental data, allows for more efficient calibration of stochastic defect prediction models, and enables effective capture of potential defects across complex design layouts, thereby improving yield and reducing costs in semiconductor manufacturing.